1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_ASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_ASSEMBLER_AARCH64_HPP
28
29 #include "asm/register.hpp"
30
31 #ifdef __GNUC__
32
33 // __nop needs volatile so that compiler doesn't optimize it away
34 #define NOP() asm volatile ("nop");
35
36 #elif defined(_MSC_VER)
37
38 // Use MSVC instrinsic: https://docs.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=vs-2019#I
39 #define NOP() __nop();
40
41 #endif
42
43
44
45 // definitions of various symbolic names for machine registers
46
47 // First intercalls between C and Java which use 8 general registers
48 // and 8 floating registers
49
50 // we also have to copy between x86 and ARM registers but that's a
51 // secondary complication -- not all code employing C call convention
52 // executes as x86 code though -- we generate some of it
53
54 class Argument {
55 public:
56 enum {
57 n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
58 n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... )
59
60 n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
61 n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ...
62 };
63 };
64
65 REGISTER_DECLARATION(Register, c_rarg0, r0);
66 REGISTER_DECLARATION(Register, c_rarg1, r1);
67 REGISTER_DECLARATION(Register, c_rarg2, r2);
68 REGISTER_DECLARATION(Register, c_rarg3, r3);
69 REGISTER_DECLARATION(Register, c_rarg4, r4);
70 REGISTER_DECLARATION(Register, c_rarg5, r5);
71 REGISTER_DECLARATION(Register, c_rarg6, r6);
72 REGISTER_DECLARATION(Register, c_rarg7, r7);
73
74 REGISTER_DECLARATION(FloatRegister, c_farg0, v0);
75 REGISTER_DECLARATION(FloatRegister, c_farg1, v1);
76 REGISTER_DECLARATION(FloatRegister, c_farg2, v2);
77 REGISTER_DECLARATION(FloatRegister, c_farg3, v3);
78 REGISTER_DECLARATION(FloatRegister, c_farg4, v4);
79 REGISTER_DECLARATION(FloatRegister, c_farg5, v5);
80 REGISTER_DECLARATION(FloatRegister, c_farg6, v6);
81 REGISTER_DECLARATION(FloatRegister, c_farg7, v7);
82
83 // Symbolically name the register arguments used by the Java calling convention.
84 // We have control over the convention for java so we can do what we please.
85 // What pleases us is to offset the java calling convention so that when
86 // we call a suitable jni method the arguments are lined up and we don't
87 // have to do much shuffling. A suitable jni method is non-static and a
88 // small number of arguments
89 //
90 // |--------------------------------------------------------------------|
91 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 |
92 // |--------------------------------------------------------------------|
93 // | r0 r1 r2 r3 r4 r5 r6 r7 |
94 // |--------------------------------------------------------------------|
95 // | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 |
96 // |--------------------------------------------------------------------|
97
98
99 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
100 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
101 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
102 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
103 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
104 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
105 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
106 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
107
108 // Java floating args are passed as per C
109
110 REGISTER_DECLARATION(FloatRegister, j_farg0, v0);
111 REGISTER_DECLARATION(FloatRegister, j_farg1, v1);
112 REGISTER_DECLARATION(FloatRegister, j_farg2, v2);
113 REGISTER_DECLARATION(FloatRegister, j_farg3, v3);
114 REGISTER_DECLARATION(FloatRegister, j_farg4, v4);
115 REGISTER_DECLARATION(FloatRegister, j_farg5, v5);
116 REGISTER_DECLARATION(FloatRegister, j_farg6, v6);
117 REGISTER_DECLARATION(FloatRegister, j_farg7, v7);
118
119 // registers used to hold VM data either temporarily within a method
120 // or across method calls
121
122 // volatile (caller-save) registers
123
124 // r8 is used for indirect result location return
125 // we use it and r9 as scratch registers
126 REGISTER_DECLARATION(Register, rscratch1, r8);
127 REGISTER_DECLARATION(Register, rscratch2, r9);
128
129 // current method -- must be in a call-clobbered register
130 REGISTER_DECLARATION(Register, rmethod, r12);
131
132 // non-volatile (callee-save) registers are r16-29
133 // of which the following are dedicated global state
134
135 // link register
136 REGISTER_DECLARATION(Register, lr, r30);
137 // frame pointer
138 REGISTER_DECLARATION(Register, rfp, r29);
139 // current thread
140 REGISTER_DECLARATION(Register, rthread, r28);
141 // base of heap
142 REGISTER_DECLARATION(Register, rheapbase, r27);
143 // constant pool cache
144 REGISTER_DECLARATION(Register, rcpool, r26);
145 // monitors allocated on stack
146 REGISTER_DECLARATION(Register, rmonitors, r25);
147 // locals on stack
148 REGISTER_DECLARATION(Register, rlocals, r24);
149 // bytecode pointer
150 REGISTER_DECLARATION(Register, rbcp, r22);
151 // Dispatch table base
152 REGISTER_DECLARATION(Register, rdispatch, r21);
153 // Java stack pointer
154 REGISTER_DECLARATION(Register, esp, r20);
155
156 #define assert_cond(ARG1) assert(ARG1, #ARG1)
157
158 namespace asm_util {
159 uint32_t encode_logical_immediate(bool is32, uint64_t imm);
160 };
161
162 using namespace asm_util;
163
164
165 class Assembler;
166
167 class Instruction_aarch64 {
168 unsigned insn;
169 #ifdef ASSERT
170 unsigned bits;
171 #endif
172 Assembler *assem;
173
174 public:
175
176 Instruction_aarch64(class Assembler *as) {
177 #ifdef ASSERT
178 bits = 0;
179 #endif
180 insn = 0;
181 assem = as;
182 }
183
184 inline ~Instruction_aarch64();
185
186 unsigned &get_insn() { return insn; }
187 #ifdef ASSERT
188 unsigned &get_bits() { return bits; }
189 #endif
190
191 static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
192 union {
193 unsigned u;
194 int n;
195 };
196
197 u = val << (31 - hi);
198 n = n >> (31 - hi + lo);
199 return n;
200 }
201
202 static inline uint32_t extract(uint32_t val, int msb, int lsb) {
203 int nbits = msb - lsb + 1;
204 assert_cond(msb >= lsb);
205 uint32_t mask = (1U << nbits) - 1;
206 uint32_t result = val >> lsb;
207 result &= mask;
208 return result;
209 }
210
211 static inline int32_t sextract(uint32_t val, int msb, int lsb) {
212 uint32_t uval = extract(val, msb, lsb);
213 return extend(uval, msb - lsb);
214 }
215
216 static void patch(address a, int msb, int lsb, uint64_t val) {
217 int nbits = msb - lsb + 1;
218 guarantee(val < (1U << nbits), "Field too big for insn");
219 assert_cond(msb >= lsb);
220 unsigned mask = (1U << nbits) - 1;
221 val <<= lsb;
222 mask <<= lsb;
223 unsigned target = *(unsigned *)a;
224 target &= ~mask;
225 target |= val;
226 *(unsigned *)a = target;
227 }
228
229 static void spatch(address a, int msb, int lsb, int64_t val) {
230 int nbits = msb - lsb + 1;
231 int64_t chk = val >> (nbits - 1);
232 guarantee (chk == -1 || chk == 0, "Field too big for insn");
233 unsigned uval = val;
234 unsigned mask = (1U << nbits) - 1;
235 uval &= mask;
236 uval <<= lsb;
237 mask <<= lsb;
238 unsigned target = *(unsigned *)a;
239 target &= ~mask;
240 target |= uval;
241 *(unsigned *)a = target;
242 }
243
244 void f(unsigned val, int msb, int lsb) {
245 int nbits = msb - lsb + 1;
246 guarantee(val < (1U << nbits), "Field too big for insn");
247 assert_cond(msb >= lsb);
248 unsigned mask = (1U << nbits) - 1;
249 val <<= lsb;
250 mask <<= lsb;
251 insn |= val;
252 assert_cond((bits & mask) == 0);
253 #ifdef ASSERT
254 bits |= mask;
255 #endif
256 }
257
258 void f(unsigned val, int bit) {
259 f(val, bit, bit);
260 }
261
262 void sf(int64_t val, int msb, int lsb) {
263 int nbits = msb - lsb + 1;
264 int64_t chk = val >> (nbits - 1);
265 guarantee (chk == -1 || chk == 0, "Field too big for insn");
266 unsigned uval = val;
267 unsigned mask = (1U << nbits) - 1;
268 uval &= mask;
269 f(uval, lsb + nbits - 1, lsb);
270 }
271
272 void rf(Register r, int lsb) {
273 f(r->encoding_nocheck(), lsb + 4, lsb);
274 }
275
276 // reg|ZR
277 void zrf(Register r, int lsb) {
278 f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);
279 }
280
281 // reg|SP
282 void srf(Register r, int lsb) {
283 f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);
284 }
285
286 void rf(FloatRegister r, int lsb) {
287 f(r->encoding_nocheck(), lsb + 4, lsb);
288 }
289
290 unsigned get(int msb = 31, int lsb = 0) {
291 int nbits = msb - lsb + 1;
292 unsigned mask = ((1U << nbits) - 1) << lsb;
293 assert_cond((bits & mask) == mask);
294 return (insn & mask) >> lsb;
295 }
296
297 void fixed(unsigned value, unsigned mask) {
298 assert_cond ((mask & bits) == 0);
299 #ifdef ASSERT
300 bits |= mask;
301 #endif
302 insn |= value;
303 }
304 };
305
306 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
307
308 class PrePost {
309 int _offset;
310 Register _r;
311 public:
312 PrePost(Register reg, int o) : _offset(o), _r(reg) { }
313 int offset() { return _offset; }
314 Register reg() { return _r; }
315 };
316
317 class Pre : public PrePost {
318 public:
319 Pre(Register reg, int o) : PrePost(reg, o) { }
320 };
321 class Post : public PrePost {
322 Register _idx;
323 bool _is_postreg;
324 public:
325 Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; _is_postreg = false; }
326 Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; _is_postreg = true; }
327 Register idx_reg() { return _idx; }
328 bool is_postreg() {return _is_postreg; }
329 };
330
331 namespace ext
332 {
333 enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
334 };
335
336 // Addressing modes
337 class Address {
338 public:
339
340 enum mode { no_mode, base_plus_offset, pre, post, post_reg, pcrel,
341 base_plus_offset_reg, literal };
342
343 // Shift and extend for base reg + reg offset addressing
344 class extend {
345 int _option, _shift;
346 ext::operation _op;
347 public:
348 extend() { }
349 extend(int s, int o, ext::operation op) : _option(o), _shift(s), _op(op) { }
350 int option() const{ return _option; }
351 int shift() const { return _shift; }
352 ext::operation op() const { return _op; }
353 };
354 class uxtw : public extend {
355 public:
356 uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }
357 };
358 class lsl : public extend {
359 public:
360 lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }
361 };
362 class sxtw : public extend {
363 public:
364 sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }
365 };
366 class sxtx : public extend {
367 public:
368 sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }
369 };
370
371 private:
372 Register _base;
373 Register _index;
374 int64_t _offset;
375 enum mode _mode;
376 extend _ext;
377
378 RelocationHolder _rspec;
379
380 // Typically we use AddressLiterals we want to use their rval
381 // However in some situations we want the lval (effect address) of
382 // the item. We provide a special factory for making those lvals.
383 bool _is_lval;
384
385 // If the target is far we'll need to load the ea of this to a
386 // register to reach it. Otherwise if near we can do PC-relative
387 // addressing.
388 address _target;
389
390 public:
391 Address()
392 : _mode(no_mode) { }
393 Address(Register r)
394 : _base(r), _index(noreg), _offset(0), _mode(base_plus_offset), _target(0) { }
395 Address(Register r, int o)
396 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
397 Address(Register r, int64_t o)
398 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
399 Address(Register r, uint64_t o)
400 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
401 #ifdef ASSERT
402 Address(Register r, ByteSize disp)
403 : _base(r), _index(noreg), _offset(in_bytes(disp)), _mode(base_plus_offset), _target(0) { }
404 #endif
405 Address(Register r, Register r1, extend ext = lsl())
406 : _base(r), _index(r1), _offset(0), _mode(base_plus_offset_reg),
407 _ext(ext), _target(0) { }
408 Address(Pre p)
409 : _base(p.reg()), _offset(p.offset()), _mode(pre) { }
410 Address(Post p)
411 : _base(p.reg()), _index(p.idx_reg()), _offset(p.offset()),
412 _mode(p.is_postreg() ? post_reg : post), _target(0) { }
413 Address(address target, RelocationHolder const& rspec)
414 : _mode(literal),
415 _rspec(rspec),
416 _is_lval(false),
417 _target(target) { }
418 Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
419 Address(Register base, RegisterOrConstant index, extend ext = lsl())
420 : _base (base),
421 _offset(0), _ext(ext), _target(0) {
422 if (index.is_register()) {
423 _mode = base_plus_offset_reg;
424 _index = index.as_register();
425 } else {
426 guarantee(ext.option() == ext::uxtx, "should be");
427 assert(index.is_constant(), "should be");
428 _mode = base_plus_offset;
429 _offset = index.as_constant() << ext.shift();
430 }
431 }
432
433 Register base() const {
434 guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg
435 | _mode == post | _mode == post_reg),
436 "wrong mode");
437 return _base;
438 }
439 int64_t offset() const {
440 return _offset;
441 }
442 Register index() const {
443 return _index;
444 }
445 mode getMode() const {
446 return _mode;
447 }
448 bool uses(Register reg) const { return _base == reg || _index == reg; }
449 address target() const { return _target; }
450 const RelocationHolder& rspec() const { return _rspec; }
451
452 void encode(Instruction_aarch64 *i) const {
453 i->f(0b111, 29, 27);
454 i->srf(_base, 5);
455
456 switch(_mode) {
457 case base_plus_offset:
458 {
459 unsigned size = i->get(31, 30);
460 if (i->get(26, 26) && i->get(23, 23)) {
461 // SIMD Q Type - Size = 128 bits
462 assert(size == 0, "bad size");
463 size = 0b100;
464 }
465 unsigned mask = (1 << size) - 1;
466 if (_offset < 0 || _offset & mask)
467 {
468 i->f(0b00, 25, 24);
469 i->f(0, 21), i->f(0b00, 11, 10);
470 i->sf(_offset, 20, 12);
471 } else {
472 i->f(0b01, 25, 24);
473 i->f(_offset >> size, 21, 10);
474 }
475 }
476 break;
477
478 case base_plus_offset_reg:
479 {
480 i->f(0b00, 25, 24);
481 i->f(1, 21);
482 i->rf(_index, 16);
483 i->f(_ext.option(), 15, 13);
484 unsigned size = i->get(31, 30);
485 if (i->get(26, 26) && i->get(23, 23)) {
486 // SIMD Q Type - Size = 128 bits
487 assert(size == 0, "bad size");
488 size = 0b100;
489 }
490 if (size == 0) // It's a byte
491 i->f(_ext.shift() >= 0, 12);
492 else {
493 if (_ext.shift() > 0)
494 assert(_ext.shift() == (int)size, "bad shift");
495 i->f(_ext.shift() > 0, 12);
496 }
497 i->f(0b10, 11, 10);
498 }
499 break;
500
501 case pre:
502 i->f(0b00, 25, 24);
503 i->f(0, 21), i->f(0b11, 11, 10);
504 i->sf(_offset, 20, 12);
505 break;
506
507 case post:
508 i->f(0b00, 25, 24);
509 i->f(0, 21), i->f(0b01, 11, 10);
510 i->sf(_offset, 20, 12);
511 break;
512
513 default:
514 ShouldNotReachHere();
515 }
516 }
517
518 void encode_pair(Instruction_aarch64 *i) const {
519 switch(_mode) {
520 case base_plus_offset:
521 i->f(0b010, 25, 23);
522 break;
523 case pre:
524 i->f(0b011, 25, 23);
525 break;
526 case post:
527 i->f(0b001, 25, 23);
528 break;
529 default:
530 ShouldNotReachHere();
531 }
532
533 unsigned size; // Operand shift in 32-bit words
534
535 if (i->get(26, 26)) { // float
536 switch(i->get(31, 30)) {
537 case 0b10:
538 size = 2; break;
539 case 0b01:
540 size = 1; break;
541 case 0b00:
542 size = 0; break;
543 default:
544 ShouldNotReachHere();
545 size = 0; // unreachable
546 }
547 } else {
548 size = i->get(31, 31);
549 }
550
551 size = 4 << size;
552 guarantee(_offset % size == 0, "bad offset");
553 i->sf(_offset / size, 21, 15);
554 i->srf(_base, 5);
555 }
556
557 void encode_nontemporal_pair(Instruction_aarch64 *i) const {
558 // Only base + offset is allowed
559 i->f(0b000, 25, 23);
560 unsigned size = i->get(31, 31);
561 size = 4 << size;
562 guarantee(_offset % size == 0, "bad offset");
563 i->sf(_offset / size, 21, 15);
564 i->srf(_base, 5);
565 guarantee(_mode == Address::base_plus_offset,
566 "Bad addressing mode for non-temporal op");
567 }
568
569 void lea(MacroAssembler *, Register) const;
570
571 static bool offset_ok_for_immed(int64_t offset, uint shift);
572 };
573
574 // Convience classes
575 class RuntimeAddress: public Address {
576
577 public:
578
579 RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
580
581 };
582
583 class OopAddress: public Address {
584
585 public:
586
587 OopAddress(address target) : Address(target, relocInfo::oop_type){}
588
589 };
590
591 class ExternalAddress: public Address {
592 private:
593 static relocInfo::relocType reloc_for_target(address target) {
594 // Sometimes ExternalAddress is used for values which aren't
595 // exactly addresses, like the card table base.
596 // external_word_type can't be used for values in the first page
597 // so just skip the reloc in that case.
598 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
599 }
600
601 public:
602
603 ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
604
605 };
606
607 class InternalAddress: public Address {
608
609 public:
610
611 InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
612 };
613
614 const int FPUStateSizeInWords = FloatRegisterImpl::number_of_registers *
615 FloatRegisterImpl::save_slots_per_register;
616
617 typedef enum {
618 PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
619 PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
620 PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
621 } prfop;
622
623 class Assembler : public AbstractAssembler {
624
625 #ifndef PRODUCT
626 static const uintptr_t asm_bp;
627
628 void emit_long(jint x) {
629 if ((uintptr_t)pc() == asm_bp)
630 NOP();
631 AbstractAssembler::emit_int32(x);
632 }
633 #else
634 void emit_long(jint x) {
635 AbstractAssembler::emit_int32(x);
636 }
637 #endif
638
639 public:
640
641 enum { instruction_size = 4 };
642
643 //---< calculate length of instruction >---
644 // We just use the values set above.
645 // instruction must start at passed address
646 static unsigned int instr_len(unsigned char *instr) { return instruction_size; }
647
648 //---< longest instructions >---
649 static unsigned int instr_maxlen() { return instruction_size; }
650
651 Address adjust(Register base, int offset, bool preIncrement) {
652 if (preIncrement)
653 return Address(Pre(base, offset));
654 else
655 return Address(Post(base, offset));
656 }
657
658 Address pre(Register base, int offset) {
659 return adjust(base, offset, true);
660 }
661
662 Address post(Register base, int offset) {
663 return adjust(base, offset, false);
664 }
665
666 Address post(Register base, Register idx) {
667 return Address(Post(base, idx));
668 }
669
670 static address locate_next_instruction(address inst);
671
672 Instruction_aarch64* current;
673
674 void set_current(Instruction_aarch64* i) { current = i; }
675
676 void f(unsigned val, int msb, int lsb) {
677 current->f(val, msb, lsb);
678 }
679 void f(unsigned val, int msb) {
680 current->f(val, msb, msb);
681 }
682 void sf(int64_t val, int msb, int lsb) {
683 current->sf(val, msb, lsb);
684 }
685 void rf(Register reg, int lsb) {
686 current->rf(reg, lsb);
687 }
688 void srf(Register reg, int lsb) {
689 current->srf(reg, lsb);
690 }
691 void zrf(Register reg, int lsb) {
692 current->zrf(reg, lsb);
693 }
694 void rf(FloatRegister reg, int lsb) {
695 current->rf(reg, lsb);
696 }
697 void fixed(unsigned value, unsigned mask) {
698 current->fixed(value, mask);
699 }
700
701 void emit() {
702 emit_long(current->get_insn());
703 assert_cond(current->get_bits() == 0xffffffff);
704 current = NULL;
705 }
706
707 typedef void (Assembler::* uncond_branch_insn)(address dest);
708 typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
709 typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
710 typedef void (Assembler::* prefetch_insn)(address target, prfop);
711
712 void wrap_label(Label &L, uncond_branch_insn insn);
713 void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
714 void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
715 void wrap_label(Label &L, prfop, prefetch_insn insn);
716
717 // PC-rel. addressing
718
719 void adr(Register Rd, address dest);
720 void _adrp(Register Rd, address dest);
721
722 void adr(Register Rd, const Address &dest);
723 void _adrp(Register Rd, const Address &dest);
724
725 void adr(Register Rd, Label &L) {
726 wrap_label(Rd, L, &Assembler::Assembler::adr);
727 }
728 void _adrp(Register Rd, Label &L) {
729 wrap_label(Rd, L, &Assembler::_adrp);
730 }
731
732 void adrp(Register Rd, const Address &dest, uint64_t &offset);
733
734 #undef INSN
735
736 void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
737 int negated_op);
738
739 // Add/subtract (immediate)
740 #define INSN(NAME, decode, negated) \
741 void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \
742 starti; \
743 f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
744 zrf(Rd, 0), srf(Rn, 5); \
745 } \
746 \
747 void NAME(Register Rd, Register Rn, unsigned imm) { \
748 starti; \
749 add_sub_immediate(Rd, Rn, imm, decode, negated); \
750 }
751
752 INSN(addsw, 0b001, 0b011);
753 INSN(subsw, 0b011, 0b001);
754 INSN(adds, 0b101, 0b111);
755 INSN(subs, 0b111, 0b101);
756
757 #undef INSN
758
759 #define INSN(NAME, decode, negated) \
760 void NAME(Register Rd, Register Rn, unsigned imm) { \
761 starti; \
762 add_sub_immediate(Rd, Rn, imm, decode, negated); \
763 }
764
765 INSN(addw, 0b000, 0b010);
766 INSN(subw, 0b010, 0b000);
767 INSN(add, 0b100, 0b110);
768 INSN(sub, 0b110, 0b100);
769
770 #undef INSN
771
772 // Logical (immediate)
773 #define INSN(NAME, decode, is32) \
774 void NAME(Register Rd, Register Rn, uint64_t imm) { \
775 starti; \
776 uint32_t val = encode_logical_immediate(is32, imm); \
777 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
778 srf(Rd, 0), zrf(Rn, 5); \
779 }
780
781 INSN(andw, 0b000, true);
782 INSN(orrw, 0b001, true);
783 INSN(eorw, 0b010, true);
784 INSN(andr, 0b100, false);
785 INSN(orr, 0b101, false);
786 INSN(eor, 0b110, false);
787
788 #undef INSN
789
790 #define INSN(NAME, decode, is32) \
791 void NAME(Register Rd, Register Rn, uint64_t imm) { \
792 starti; \
793 uint32_t val = encode_logical_immediate(is32, imm); \
794 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
795 zrf(Rd, 0), zrf(Rn, 5); \
796 }
797
798 INSN(ands, 0b111, false);
799 INSN(andsw, 0b011, true);
800
801 #undef INSN
802
803 // Move wide (immediate)
804 #define INSN(NAME, opcode) \
805 void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \
806 assert_cond((shift/16)*16 == shift); \
807 starti; \
808 f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \
809 f(imm, 20, 5); \
810 rf(Rd, 0); \
811 }
812
813 INSN(movnw, 0b000);
814 INSN(movzw, 0b010);
815 INSN(movkw, 0b011);
816 INSN(movn, 0b100);
817 INSN(movz, 0b110);
818 INSN(movk, 0b111);
819
820 #undef INSN
821
822 // Bitfield
823 #define INSN(NAME, opcode, size) \
824 void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \
825 starti; \
826 guarantee(size == 1 || (immr < 32 && imms < 32), "incorrect immr/imms");\
827 f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \
828 zrf(Rn, 5), rf(Rd, 0); \
829 }
830
831 INSN(sbfmw, 0b0001001100, 0);
832 INSN(bfmw, 0b0011001100, 0);
833 INSN(ubfmw, 0b0101001100, 0);
834 INSN(sbfm, 0b1001001101, 1);
835 INSN(bfm, 0b1011001101, 1);
836 INSN(ubfm, 0b1101001101, 1);
837
838 #undef INSN
839
840 // Extract
841 #define INSN(NAME, opcode, size) \
842 void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \
843 starti; \
844 guarantee(size == 1 || imms < 32, "incorrect imms"); \
845 f(opcode, 31, 21), f(imms, 15, 10); \
846 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
847 }
848
849 INSN(extrw, 0b00010011100, 0);
850 INSN(extr, 0b10010011110, 1);
851
852 #undef INSN
853
854 // The maximum range of a branch is fixed for the AArch64
855 // architecture. In debug mode we shrink it in order to test
856 // trampolines, but not so small that branches in the interpreter
857 // are out of range.
858 static const uint64_t branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
859
860 static bool reachable_from_branch_at(address branch, address target) {
861 return uabs(target - branch) < branch_range;
862 }
863
864 // Unconditional branch (immediate)
865 #define INSN(NAME, opcode) \
866 void NAME(address dest) { \
867 starti; \
868 int64_t offset = (dest - pc()) >> 2; \
869 DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
870 f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \
871 } \
872 void NAME(Label &L) { \
873 wrap_label(L, &Assembler::NAME); \
874 } \
875 void NAME(const Address &dest);
876
877 INSN(b, 0);
878 INSN(bl, 1);
879
880 #undef INSN
881
882 // Compare & branch (immediate)
883 #define INSN(NAME, opcode) \
884 void NAME(Register Rt, address dest) { \
885 int64_t offset = (dest - pc()) >> 2; \
886 starti; \
887 f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \
888 } \
889 void NAME(Register Rt, Label &L) { \
890 wrap_label(Rt, L, &Assembler::NAME); \
891 }
892
893 INSN(cbzw, 0b00110100);
894 INSN(cbnzw, 0b00110101);
895 INSN(cbz, 0b10110100);
896 INSN(cbnz, 0b10110101);
897
898 #undef INSN
899
900 // Test & branch (immediate)
901 #define INSN(NAME, opcode) \
902 void NAME(Register Rt, int bitpos, address dest) { \
903 int64_t offset = (dest - pc()) >> 2; \
904 int b5 = bitpos >> 5; \
905 bitpos &= 0x1f; \
906 starti; \
907 f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
908 rf(Rt, 0); \
909 } \
910 void NAME(Register Rt, int bitpos, Label &L) { \
911 wrap_label(Rt, bitpos, L, &Assembler::NAME); \
912 }
913
914 INSN(tbz, 0b0110110);
915 INSN(tbnz, 0b0110111);
916
917 #undef INSN
918
919 // Conditional branch (immediate)
920 enum Condition
921 {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
922
923 void br(Condition cond, address dest) {
924 int64_t offset = (dest - pc()) >> 2;
925 starti;
926 f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
927 }
928
929 #define INSN(NAME, cond) \
930 void NAME(address dest) { \
931 br(cond, dest); \
932 }
933
934 INSN(beq, EQ);
935 INSN(bne, NE);
936 INSN(bhs, HS);
937 INSN(bcs, CS);
938 INSN(blo, LO);
939 INSN(bcc, CC);
940 INSN(bmi, MI);
941 INSN(bpl, PL);
942 INSN(bvs, VS);
943 INSN(bvc, VC);
944 INSN(bhi, HI);
945 INSN(bls, LS);
946 INSN(bge, GE);
947 INSN(blt, LT);
948 INSN(bgt, GT);
949 INSN(ble, LE);
950 INSN(bal, AL);
951 INSN(bnv, NV);
952
953 void br(Condition cc, Label &L);
954
955 #undef INSN
956
957 // Exception generation
958 void generate_exception(int opc, int op2, int LL, unsigned imm) {
959 starti;
960 f(0b11010100, 31, 24);
961 f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
962 }
963
964 #define INSN(NAME, opc, op2, LL) \
965 void NAME(unsigned imm) { \
966 generate_exception(opc, op2, LL, imm); \
967 }
968
969 INSN(svc, 0b000, 0, 0b01);
970 INSN(hvc, 0b000, 0, 0b10);
971 INSN(smc, 0b000, 0, 0b11);
972 INSN(brk, 0b001, 0, 0b00);
973 INSN(hlt, 0b010, 0, 0b00);
974 INSN(dcps1, 0b101, 0, 0b01);
975 INSN(dcps2, 0b101, 0, 0b10);
976 INSN(dcps3, 0b101, 0, 0b11);
977
978 #undef INSN
979
980 // System
981 void system(int op0, int op1, int CRn, int CRm, int op2,
982 Register rt = dummy_reg)
983 {
984 starti;
985 f(0b11010101000, 31, 21);
986 f(op0, 20, 19);
987 f(op1, 18, 16);
988 f(CRn, 15, 12);
989 f(CRm, 11, 8);
990 f(op2, 7, 5);
991 rf(rt, 0);
992 }
993
994 void hint(int imm) {
995 system(0b00, 0b011, 0b0010, 0b0000, imm);
996 }
997
998 void nop() {
999 hint(0);
1000 }
1001
1002 void yield() {
1003 hint(1);
1004 }
1005
1006 void wfe() {
1007 hint(2);
1008 }
1009
1010 void wfi() {
1011 hint(3);
1012 }
1013
1014 void sev() {
1015 hint(4);
1016 }
1017
1018 void sevl() {
1019 hint(5);
1020 }
1021
1022 // we only provide mrs and msr for the special purpose system
1023 // registers where op1 (instr[20:19]) == 11 and, (currently) only
1024 // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
1025
1026 void msr(int op1, int CRn, int CRm, int op2, Register rt) {
1027 starti;
1028 f(0b1101010100011, 31, 19);
1029 f(op1, 18, 16);
1030 f(CRn, 15, 12);
1031 f(CRm, 11, 8);
1032 f(op2, 7, 5);
1033 // writing zr is ok
1034 zrf(rt, 0);
1035 }
1036
1037 void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1038 starti;
1039 f(0b1101010100111, 31, 19);
1040 f(op1, 18, 16);
1041 f(CRn, 15, 12);
1042 f(CRm, 11, 8);
1043 f(op2, 7, 5);
1044 // reading to zr is a mistake
1045 rf(rt, 0);
1046 }
1047
1048 enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1049 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1050
1051 void dsb(barrier imm) {
1052 system(0b00, 0b011, 0b00011, imm, 0b100);
1053 }
1054
1055 void dmb(barrier imm) {
1056 system(0b00, 0b011, 0b00011, imm, 0b101);
1057 }
1058
1059 void isb() {
1060 system(0b00, 0b011, 0b00011, SY, 0b110);
1061 }
1062
1063 void sys(int op1, int CRn, int CRm, int op2,
1064 Register rt = (Register)0b11111) {
1065 system(0b01, op1, CRn, CRm, op2, rt);
1066 }
1067
1068 // Only implement operations accessible from EL0 or higher, i.e.,
1069 // op1 CRn CRm op2
1070 // IC IVAU 3 7 5 1
1071 // DC CVAC 3 7 10 1
1072 // DC CVAP 3 7 12 1
1073 // DC CVAU 3 7 11 1
1074 // DC CIVAC 3 7 14 1
1075 // DC ZVA 3 7 4 1
1076 // So only deal with the CRm field.
1077 enum icache_maintenance {IVAU = 0b0101};
1078 enum dcache_maintenance {CVAC = 0b1010, CVAP = 0b1100, CVAU = 0b1011, CIVAC = 0b1110, ZVA = 0b100};
1079
1080 void dc(dcache_maintenance cm, Register Rt) {
1081 sys(0b011, 0b0111, cm, 0b001, Rt);
1082 }
1083
1084 void ic(icache_maintenance cm, Register Rt) {
1085 sys(0b011, 0b0111, cm, 0b001, Rt);
1086 }
1087
1088 // A more convenient access to dmb for our purposes
1089 enum Membar_mask_bits {
1090 // We can use ISH for a barrier because the ARM ARM says "This
1091 // architecture assumes that all Processing Elements that use the
1092 // same operating system or hypervisor are in the same Inner
1093 // Shareable shareability domain."
1094 StoreStore = ISHST,
1095 LoadStore = ISHLD,
1096 LoadLoad = ISHLD,
1097 StoreLoad = ISH,
1098 AnyAny = ISH
1099 };
1100
1101 void membar(Membar_mask_bits order_constraint) {
1102 dmb(Assembler::barrier(order_constraint));
1103 }
1104
1105 // Unconditional branch (register)
1106 void branch_reg(Register R, int opc) {
1107 starti;
1108 f(0b1101011, 31, 25);
1109 f(opc, 24, 21);
1110 f(0b11111000000, 20, 10);
1111 rf(R, 5);
1112 f(0b00000, 4, 0);
1113 }
1114
1115 #define INSN(NAME, opc) \
1116 void NAME(Register R) { \
1117 branch_reg(R, opc); \
1118 }
1119
1120 INSN(br, 0b0000);
1121 INSN(blr, 0b0001);
1122 INSN(ret, 0b0010);
1123
1124 void ret(void *p); // This forces a compile-time error for ret(0)
1125
1126 #undef INSN
1127
1128 #define INSN(NAME, opc) \
1129 void NAME() { \
1130 branch_reg(dummy_reg, opc); \
1131 }
1132
1133 INSN(eret, 0b0100);
1134 INSN(drps, 0b0101);
1135
1136 #undef INSN
1137
1138 // Load/store exclusive
1139 enum operand_size { byte, halfword, word, xword };
1140
1141 void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1142 Register Rn, enum operand_size sz, int op, bool ordered) {
1143 starti;
1144 f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1145 rf(Rs, 16), f(ordered, 15), zrf(Rt2, 10), srf(Rn, 5), zrf(Rt1, 0);
1146 }
1147
1148 void load_exclusive(Register dst, Register addr,
1149 enum operand_size sz, bool ordered) {
1150 load_store_exclusive(dummy_reg, dst, dummy_reg, addr,
1151 sz, 0b010, ordered);
1152 }
1153
1154 void store_exclusive(Register status, Register new_val, Register addr,
1155 enum operand_size sz, bool ordered) {
1156 load_store_exclusive(status, new_val, dummy_reg, addr,
1157 sz, 0b000, ordered);
1158 }
1159
1160 #define INSN4(NAME, sz, op, o0) /* Four registers */ \
1161 void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \
1162 guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \
1163 load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \
1164 }
1165
1166 #define INSN3(NAME, sz, op, o0) /* Three registers */ \
1167 void NAME(Register Rs, Register Rt, Register Rn) { \
1168 guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
1169 load_store_exclusive(Rs, Rt, dummy_reg, Rn, sz, op, o0); \
1170 }
1171
1172 #define INSN2(NAME, sz, op, o0) /* Two registers */ \
1173 void NAME(Register Rt, Register Rn) { \
1174 load_store_exclusive(dummy_reg, Rt, dummy_reg, \
1175 Rn, sz, op, o0); \
1176 }
1177
1178 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \
1179 void NAME(Register Rt1, Register Rt2, Register Rn) { \
1180 guarantee(Rt1 != Rt2, "unpredictable instruction"); \
1181 load_store_exclusive(dummy_reg, Rt1, Rt2, Rn, sz, op, o0); \
1182 }
1183
1184 // bytes
1185 INSN3(stxrb, byte, 0b000, 0);
1186 INSN3(stlxrb, byte, 0b000, 1);
1187 INSN2(ldxrb, byte, 0b010, 0);
1188 INSN2(ldaxrb, byte, 0b010, 1);
1189 INSN2(stlrb, byte, 0b100, 1);
1190 INSN2(ldarb, byte, 0b110, 1);
1191
1192 // halfwords
1193 INSN3(stxrh, halfword, 0b000, 0);
1194 INSN3(stlxrh, halfword, 0b000, 1);
1195 INSN2(ldxrh, halfword, 0b010, 0);
1196 INSN2(ldaxrh, halfword, 0b010, 1);
1197 INSN2(stlrh, halfword, 0b100, 1);
1198 INSN2(ldarh, halfword, 0b110, 1);
1199
1200 // words
1201 INSN3(stxrw, word, 0b000, 0);
1202 INSN3(stlxrw, word, 0b000, 1);
1203 INSN4(stxpw, word, 0b001, 0);
1204 INSN4(stlxpw, word, 0b001, 1);
1205 INSN2(ldxrw, word, 0b010, 0);
1206 INSN2(ldaxrw, word, 0b010, 1);
1207 INSN_FOO(ldxpw, word, 0b011, 0);
1208 INSN_FOO(ldaxpw, word, 0b011, 1);
1209 INSN2(stlrw, word, 0b100, 1);
1210 INSN2(ldarw, word, 0b110, 1);
1211
1212 // xwords
1213 INSN3(stxr, xword, 0b000, 0);
1214 INSN3(stlxr, xword, 0b000, 1);
1215 INSN4(stxp, xword, 0b001, 0);
1216 INSN4(stlxp, xword, 0b001, 1);
1217 INSN2(ldxr, xword, 0b010, 0);
1218 INSN2(ldaxr, xword, 0b010, 1);
1219 INSN_FOO(ldxp, xword, 0b011, 0);
1220 INSN_FOO(ldaxp, xword, 0b011, 1);
1221 INSN2(stlr, xword, 0b100, 1);
1222 INSN2(ldar, xword, 0b110, 1);
1223
1224 #undef INSN2
1225 #undef INSN3
1226 #undef INSN4
1227 #undef INSN_FOO
1228
1229 // 8.1 Compare and swap extensions
1230 void lse_cas(Register Rs, Register Rt, Register Rn,
1231 enum operand_size sz, bool a, bool r, bool not_pair) {
1232 starti;
1233 if (! not_pair) { // Pair
1234 assert(sz == word || sz == xword, "invalid size");
1235 /* The size bit is in bit 30, not 31 */
1236 sz = (operand_size)(sz == word ? 0b00:0b01);
1237 }
1238 f(sz, 31, 30), f(0b001000, 29, 24), f(not_pair ? 1 : 0, 23), f(a, 22), f(1, 21);
1239 zrf(Rs, 16), f(r, 15), f(0b11111, 14, 10), srf(Rn, 5), zrf(Rt, 0);
1240 }
1241
1242 // CAS
1243 #define INSN(NAME, a, r) \
1244 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1245 assert(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
1246 lse_cas(Rs, Rt, Rn, sz, a, r, true); \
1247 }
1248 INSN(cas, false, false)
1249 INSN(casa, true, false)
1250 INSN(casl, false, true)
1251 INSN(casal, true, true)
1252 #undef INSN
1253
1254 // CASP
1255 #define INSN(NAME, a, r) \
1256 void NAME(operand_size sz, Register Rs, Register Rs1, \
1257 Register Rt, Register Rt1, Register Rn) { \
1258 assert((Rs->encoding() & 1) == 0 && (Rt->encoding() & 1) == 0 && \
1259 Rs->successor() == Rs1 && Rt->successor() == Rt1 && \
1260 Rs != Rn && Rs1 != Rn && Rs != Rt, "invalid registers"); \
1261 lse_cas(Rs, Rt, Rn, sz, a, r, false); \
1262 }
1263 INSN(casp, false, false)
1264 INSN(caspa, true, false)
1265 INSN(caspl, false, true)
1266 INSN(caspal, true, true)
1267 #undef INSN
1268
1269 // 8.1 Atomic operations
1270 void lse_atomic(Register Rs, Register Rt, Register Rn,
1271 enum operand_size sz, int op1, int op2, bool a, bool r) {
1272 starti;
1273 f(sz, 31, 30), f(0b111000, 29, 24), f(a, 23), f(r, 22), f(1, 21);
1274 zrf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), srf(Rn, 5), zrf(Rt, 0);
1275 }
1276
1277 #define INSN(NAME, NAME_A, NAME_L, NAME_AL, op1, op2) \
1278 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1279 lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, false); \
1280 } \
1281 void NAME_A(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1282 lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, false); \
1283 } \
1284 void NAME_L(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1285 lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, true); \
1286 } \
1287 void NAME_AL(operand_size sz, Register Rs, Register Rt, Register Rn) {\
1288 lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, true); \
1289 }
1290 INSN(ldadd, ldadda, ldaddl, ldaddal, 0, 0b000);
1291 INSN(ldbic, ldbica, ldbicl, ldbical, 0, 0b001);
1292 INSN(ldeor, ldeora, ldeorl, ldeoral, 0, 0b010);
1293 INSN(ldorr, ldorra, ldorrl, ldorral, 0, 0b011);
1294 INSN(ldsmax, ldsmaxa, ldsmaxl, ldsmaxal, 0, 0b100);
1295 INSN(ldsmin, ldsmina, ldsminl, ldsminal, 0, 0b101);
1296 INSN(ldumax, ldumaxa, ldumaxl, ldumaxal, 0, 0b110);
1297 INSN(ldumin, ldumina, lduminl, lduminal, 0, 0b111);
1298 INSN(swp, swpa, swpl, swpal, 1, 0b000);
1299 #undef INSN
1300
1301 // Load register (literal)
1302 #define INSN(NAME, opc, V) \
1303 void NAME(Register Rt, address dest) { \
1304 int64_t offset = (dest - pc()) >> 2; \
1305 starti; \
1306 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1307 sf(offset, 23, 5); \
1308 rf(Rt, 0); \
1309 } \
1310 void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \
1311 InstructionMark im(this); \
1312 guarantee(rtype == relocInfo::internal_word_type, \
1313 "only internal_word_type relocs make sense here"); \
1314 code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \
1315 NAME(Rt, dest); \
1316 } \
1317 void NAME(Register Rt, Label &L) { \
1318 wrap_label(Rt, L, &Assembler::NAME); \
1319 }
1320
1321 INSN(ldrw, 0b00, 0);
1322 INSN(ldr, 0b01, 0);
1323 INSN(ldrsw, 0b10, 0);
1324
1325 #undef INSN
1326
1327 #define INSN(NAME, opc, V) \
1328 void NAME(FloatRegister Rt, address dest) { \
1329 int64_t offset = (dest - pc()) >> 2; \
1330 starti; \
1331 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1332 sf(offset, 23, 5); \
1333 rf((Register)Rt, 0); \
1334 }
1335
1336 INSN(ldrs, 0b00, 1);
1337 INSN(ldrd, 0b01, 1);
1338 INSN(ldrq, 0b10, 1);
1339
1340 #undef INSN
1341
1342 #define INSN(NAME, opc, V) \
1343 void NAME(address dest, prfop op = PLDL1KEEP) { \
1344 int64_t offset = (dest - pc()) >> 2; \
1345 starti; \
1346 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1347 sf(offset, 23, 5); \
1348 f(op, 4, 0); \
1349 } \
1350 void NAME(Label &L, prfop op = PLDL1KEEP) { \
1351 wrap_label(L, op, &Assembler::NAME); \
1352 }
1353
1354 INSN(prfm, 0b11, 0);
1355
1356 #undef INSN
1357
1358 // Load/store
1359 void ld_st1(int opc, int p1, int V, int L,
1360 Register Rt1, Register Rt2, Address adr, bool no_allocate) {
1361 starti;
1362 f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
1363 zrf(Rt2, 10), zrf(Rt1, 0);
1364 if (no_allocate) {
1365 adr.encode_nontemporal_pair(current);
1366 } else {
1367 adr.encode_pair(current);
1368 }
1369 }
1370
1371 // Load/store register pair (offset)
1372 #define INSN(NAME, size, p1, V, L, no_allocate) \
1373 void NAME(Register Rt1, Register Rt2, Address adr) { \
1374 ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
1375 }
1376
1377 INSN(stpw, 0b00, 0b101, 0, 0, false);
1378 INSN(ldpw, 0b00, 0b101, 0, 1, false);
1379 INSN(ldpsw, 0b01, 0b101, 0, 1, false);
1380 INSN(stp, 0b10, 0b101, 0, 0, false);
1381 INSN(ldp, 0b10, 0b101, 0, 1, false);
1382
1383 // Load/store no-allocate pair (offset)
1384 INSN(stnpw, 0b00, 0b101, 0, 0, true);
1385 INSN(ldnpw, 0b00, 0b101, 0, 1, true);
1386 INSN(stnp, 0b10, 0b101, 0, 0, true);
1387 INSN(ldnp, 0b10, 0b101, 0, 1, true);
1388
1389 #undef INSN
1390
1391 #define INSN(NAME, size, p1, V, L, no_allocate) \
1392 void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \
1393 ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \
1394 }
1395
1396 INSN(stps, 0b00, 0b101, 1, 0, false);
1397 INSN(ldps, 0b00, 0b101, 1, 1, false);
1398 INSN(stpd, 0b01, 0b101, 1, 0, false);
1399 INSN(ldpd, 0b01, 0b101, 1, 1, false);
1400 INSN(stpq, 0b10, 0b101, 1, 0, false);
1401 INSN(ldpq, 0b10, 0b101, 1, 1, false);
1402
1403 #undef INSN
1404
1405 // Load/store register (all modes)
1406 void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) {
1407 starti;
1408
1409 f(V, 26); // general reg?
1410 zrf(Rt, 0);
1411
1412 // Encoding for literal loads is done here (rather than pushed
1413 // down into Address::encode) because the encoding of this
1414 // instruction is too different from all of the other forms to
1415 // make it worth sharing.
1416 if (adr.getMode() == Address::literal) {
1417 assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
1418 assert(op == 0b01, "literal form can only be used with loads");
1419 f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
1420 int64_t offset = (adr.target() - pc()) >> 2;
1421 sf(offset, 23, 5);
1422 code_section()->relocate(pc(), adr.rspec());
1423 return;
1424 }
1425
1426 f(size, 31, 30);
1427 f(op, 23, 22); // str
1428 adr.encode(current);
1429 }
1430
1431 #define INSN(NAME, size, op) \
1432 void NAME(Register Rt, const Address &adr) { \
1433 ld_st2(Rt, adr, size, op); \
1434 } \
1435
1436 INSN(str, 0b11, 0b00);
1437 INSN(strw, 0b10, 0b00);
1438 INSN(strb, 0b00, 0b00);
1439 INSN(strh, 0b01, 0b00);
1440
1441 INSN(ldr, 0b11, 0b01);
1442 INSN(ldrw, 0b10, 0b01);
1443 INSN(ldrb, 0b00, 0b01);
1444 INSN(ldrh, 0b01, 0b01);
1445
1446 INSN(ldrsb, 0b00, 0b10);
1447 INSN(ldrsbw, 0b00, 0b11);
1448 INSN(ldrsh, 0b01, 0b10);
1449 INSN(ldrshw, 0b01, 0b11);
1450 INSN(ldrsw, 0b10, 0b10);
1451
1452 #undef INSN
1453
1454 #define INSN(NAME, size, op) \
1455 void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \
1456 ld_st2((Register)pfop, adr, size, op); \
1457 }
1458
1459 INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
1460 // writeback modes, but the assembler
1461 // doesn't enfore that.
1462
1463 #undef INSN
1464
1465 #define INSN(NAME, size, op) \
1466 void NAME(FloatRegister Rt, const Address &adr) { \
1467 ld_st2((Register)Rt, adr, size, op, 1); \
1468 }
1469
1470 INSN(strd, 0b11, 0b00);
1471 INSN(strs, 0b10, 0b00);
1472 INSN(ldrd, 0b11, 0b01);
1473 INSN(ldrs, 0b10, 0b01);
1474 INSN(strq, 0b00, 0b10);
1475 INSN(ldrq, 0x00, 0b11);
1476
1477 #undef INSN
1478
1479 enum shift_kind { LSL, LSR, ASR, ROR };
1480
1481 void op_shifted_reg(unsigned decode,
1482 enum shift_kind kind, unsigned shift,
1483 unsigned size, unsigned op) {
1484 f(size, 31);
1485 f(op, 30, 29);
1486 f(decode, 28, 24);
1487 f(shift, 15, 10);
1488 f(kind, 23, 22);
1489 }
1490
1491 // Logical (shifted register)
1492 #define INSN(NAME, size, op, N) \
1493 void NAME(Register Rd, Register Rn, Register Rm, \
1494 enum shift_kind kind = LSL, unsigned shift = 0) { \
1495 starti; \
1496 guarantee(size == 1 || shift < 32, "incorrect shift"); \
1497 f(N, 21); \
1498 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
1499 op_shifted_reg(0b01010, kind, shift, size, op); \
1500 }
1501
1502 INSN(andr, 1, 0b00, 0);
1503 INSN(orr, 1, 0b01, 0);
1504 INSN(eor, 1, 0b10, 0);
1505 INSN(ands, 1, 0b11, 0);
1506 INSN(andw, 0, 0b00, 0);
1507 INSN(orrw, 0, 0b01, 0);
1508 INSN(eorw, 0, 0b10, 0);
1509 INSN(andsw, 0, 0b11, 0);
1510
1511 #undef INSN
1512
1513 #define INSN(NAME, size, op, N) \
1514 void NAME(Register Rd, Register Rn, Register Rm, \
1515 enum shift_kind kind = LSL, unsigned shift = 0) { \
1516 starti; \
1517 f(N, 21); \
1518 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
1519 op_shifted_reg(0b01010, kind, shift, size, op); \
1520 } \
1521 \
1522 /* These instructions have no immediate form. Provide an overload so \
1523 that if anyone does try to use an immediate operand -- this has \
1524 happened! -- we'll get a compile-time error. */ \
1525 void NAME(Register Rd, Register Rn, unsigned imm, \
1526 enum shift_kind kind = LSL, unsigned shift = 0) { \
1527 assert(false, " can't be used with immediate operand"); \
1528 }
1529
1530 INSN(bic, 1, 0b00, 1);
1531 INSN(orn, 1, 0b01, 1);
1532 INSN(eon, 1, 0b10, 1);
1533 INSN(bics, 1, 0b11, 1);
1534 INSN(bicw, 0, 0b00, 1);
1535 INSN(ornw, 0, 0b01, 1);
1536 INSN(eonw, 0, 0b10, 1);
1537 INSN(bicsw, 0, 0b11, 1);
1538
1539 #undef INSN
1540
1541 #ifdef _WIN64
1542 // In MSVC, `mvn` is defined as a macro and it affects compilation
1543 #undef mvn
1544 #endif
1545
1546 // Aliases for short forms of orn
1547 void mvn(Register Rd, Register Rm,
1548 enum shift_kind kind = LSL, unsigned shift = 0) {
1549 orn(Rd, zr, Rm, kind, shift);
1550 }
1551
1552 void mvnw(Register Rd, Register Rm,
1553 enum shift_kind kind = LSL, unsigned shift = 0) {
1554 ornw(Rd, zr, Rm, kind, shift);
1555 }
1556
1557 // Add/subtract (shifted register)
1558 #define INSN(NAME, size, op) \
1559 void NAME(Register Rd, Register Rn, Register Rm, \
1560 enum shift_kind kind, unsigned shift = 0) { \
1561 starti; \
1562 f(0, 21); \
1563 assert_cond(kind != ROR); \
1564 guarantee(size == 1 || shift < 32, "incorrect shift");\
1565 zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \
1566 op_shifted_reg(0b01011, kind, shift, size, op); \
1567 }
1568
1569 INSN(add, 1, 0b000);
1570 INSN(sub, 1, 0b10);
1571 INSN(addw, 0, 0b000);
1572 INSN(subw, 0, 0b10);
1573
1574 INSN(adds, 1, 0b001);
1575 INSN(subs, 1, 0b11);
1576 INSN(addsw, 0, 0b001);
1577 INSN(subsw, 0, 0b11);
1578
1579 #undef INSN
1580
1581 // Add/subtract (extended register)
1582 #define INSN(NAME, op) \
1583 void NAME(Register Rd, Register Rn, Register Rm, \
1584 ext::operation option, int amount = 0) { \
1585 starti; \
1586 zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \
1587 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1588 }
1589
1590 void add_sub_extended_reg(unsigned op, unsigned decode,
1591 Register Rd, Register Rn, Register Rm,
1592 unsigned opt, ext::operation option, unsigned imm) {
1593 guarantee(imm <= 4, "shift amount must be <= 4");
1594 f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
1595 f(option, 15, 13), f(imm, 12, 10);
1596 }
1597
1598 INSN(addw, 0b000);
1599 INSN(subw, 0b010);
1600 INSN(add, 0b100);
1601 INSN(sub, 0b110);
1602
1603 #undef INSN
1604
1605 #define INSN(NAME, op) \
1606 void NAME(Register Rd, Register Rn, Register Rm, \
1607 ext::operation option, int amount = 0) { \
1608 starti; \
1609 zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \
1610 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1611 }
1612
1613 INSN(addsw, 0b001);
1614 INSN(subsw, 0b011);
1615 INSN(adds, 0b101);
1616 INSN(subs, 0b111);
1617
1618 #undef INSN
1619
1620 // Aliases for short forms of add and sub
1621 #define INSN(NAME) \
1622 void NAME(Register Rd, Register Rn, Register Rm) { \
1623 if (Rd == sp || Rn == sp) \
1624 NAME(Rd, Rn, Rm, ext::uxtx); \
1625 else \
1626 NAME(Rd, Rn, Rm, LSL); \
1627 }
1628
1629 INSN(addw);
1630 INSN(subw);
1631 INSN(add);
1632 INSN(sub);
1633
1634 INSN(addsw);
1635 INSN(subsw);
1636 INSN(adds);
1637 INSN(subs);
1638
1639 #undef INSN
1640
1641 // Add/subtract (with carry)
1642 void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) {
1643 starti;
1644 f(op, 31, 29);
1645 f(0b11010000, 28, 21);
1646 f(0b000000, 15, 10);
1647 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);
1648 }
1649
1650 #define INSN(NAME, op) \
1651 void NAME(Register Rd, Register Rn, Register Rm) { \
1652 add_sub_carry(op, Rd, Rn, Rm); \
1653 }
1654
1655 INSN(adcw, 0b000);
1656 INSN(adcsw, 0b001);
1657 INSN(sbcw, 0b010);
1658 INSN(sbcsw, 0b011);
1659 INSN(adc, 0b100);
1660 INSN(adcs, 0b101);
1661 INSN(sbc,0b110);
1662 INSN(sbcs, 0b111);
1663
1664 #undef INSN
1665
1666 // Conditional compare (both kinds)
1667 void conditional_compare(unsigned op, int o1, int o2, int o3,
1668 Register Rn, unsigned imm5, unsigned nzcv,
1669 unsigned cond) {
1670 starti;
1671 f(op, 31, 29);
1672 f(0b11010010, 28, 21);
1673 f(cond, 15, 12);
1674 f(o1, 11);
1675 f(o2, 10);
1676 f(o3, 4);
1677 f(nzcv, 3, 0);
1678 f(imm5, 20, 16), zrf(Rn, 5);
1679 }
1680
1681 #define INSN(NAME, op) \
1682 void NAME(Register Rn, Register Rm, int imm, Condition cond) { \
1683 int regNumber = (Rm == zr ? 31 : (uintptr_t)Rm); \
1684 conditional_compare(op, 0, 0, 0, Rn, regNumber, imm, cond); \
1685 } \
1686 \
1687 void NAME(Register Rn, int imm5, int imm, Condition cond) { \
1688 conditional_compare(op, 1, 0, 0, Rn, imm5, imm, cond); \
1689 }
1690
1691 INSN(ccmnw, 0b001);
1692 INSN(ccmpw, 0b011);
1693 INSN(ccmn, 0b101);
1694 INSN(ccmp, 0b111);
1695
1696 #undef INSN
1697
1698 // Conditional select
1699 void conditional_select(unsigned op, unsigned op2,
1700 Register Rd, Register Rn, Register Rm,
1701 unsigned cond) {
1702 starti;
1703 f(op, 31, 29);
1704 f(0b11010100, 28, 21);
1705 f(cond, 15, 12);
1706 f(op2, 11, 10);
1707 zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0);
1708 }
1709
1710 #define INSN(NAME, op, op2) \
1711 void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
1712 conditional_select(op, op2, Rd, Rn, Rm, cond); \
1713 }
1714
1715 INSN(cselw, 0b000, 0b00);
1716 INSN(csincw, 0b000, 0b01);
1717 INSN(csinvw, 0b010, 0b00);
1718 INSN(csnegw, 0b010, 0b01);
1719 INSN(csel, 0b100, 0b00);
1720 INSN(csinc, 0b100, 0b01);
1721 INSN(csinv, 0b110, 0b00);
1722 INSN(csneg, 0b110, 0b01);
1723
1724 #undef INSN
1725
1726 // Data processing
1727 void data_processing(unsigned op29, unsigned opcode,
1728 Register Rd, Register Rn) {
1729 f(op29, 31, 29), f(0b11010110, 28, 21);
1730 f(opcode, 15, 10);
1731 rf(Rn, 5), rf(Rd, 0);
1732 }
1733
1734 // (1 source)
1735 #define INSN(NAME, op29, opcode2, opcode) \
1736 void NAME(Register Rd, Register Rn) { \
1737 starti; \
1738 f(opcode2, 20, 16); \
1739 data_processing(op29, opcode, Rd, Rn); \
1740 }
1741
1742 INSN(rbitw, 0b010, 0b00000, 0b00000);
1743 INSN(rev16w, 0b010, 0b00000, 0b00001);
1744 INSN(revw, 0b010, 0b00000, 0b00010);
1745 INSN(clzw, 0b010, 0b00000, 0b00100);
1746 INSN(clsw, 0b010, 0b00000, 0b00101);
1747
1748 INSN(rbit, 0b110, 0b00000, 0b00000);
1749 INSN(rev16, 0b110, 0b00000, 0b00001);
1750 INSN(rev32, 0b110, 0b00000, 0b00010);
1751 INSN(rev, 0b110, 0b00000, 0b00011);
1752 INSN(clz, 0b110, 0b00000, 0b00100);
1753 INSN(cls, 0b110, 0b00000, 0b00101);
1754
1755 #undef INSN
1756
1757 // (2 sources)
1758 #define INSN(NAME, op29, opcode) \
1759 void NAME(Register Rd, Register Rn, Register Rm) { \
1760 starti; \
1761 rf(Rm, 16); \
1762 data_processing(op29, opcode, Rd, Rn); \
1763 }
1764
1765 INSN(udivw, 0b000, 0b000010);
1766 INSN(sdivw, 0b000, 0b000011);
1767 INSN(lslvw, 0b000, 0b001000);
1768 INSN(lsrvw, 0b000, 0b001001);
1769 INSN(asrvw, 0b000, 0b001010);
1770 INSN(rorvw, 0b000, 0b001011);
1771
1772 INSN(udiv, 0b100, 0b000010);
1773 INSN(sdiv, 0b100, 0b000011);
1774 INSN(lslv, 0b100, 0b001000);
1775 INSN(lsrv, 0b100, 0b001001);
1776 INSN(asrv, 0b100, 0b001010);
1777 INSN(rorv, 0b100, 0b001011);
1778
1779 #undef INSN
1780
1781 // (3 sources)
1782 void data_processing(unsigned op54, unsigned op31, unsigned o0,
1783 Register Rd, Register Rn, Register Rm,
1784 Register Ra) {
1785 starti;
1786 f(op54, 31, 29), f(0b11011, 28, 24);
1787 f(op31, 23, 21), f(o0, 15);
1788 zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0);
1789 }
1790
1791 #define INSN(NAME, op54, op31, o0) \
1792 void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \
1793 data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \
1794 }
1795
1796 INSN(maddw, 0b000, 0b000, 0);
1797 INSN(msubw, 0b000, 0b000, 1);
1798 INSN(madd, 0b100, 0b000, 0);
1799 INSN(msub, 0b100, 0b000, 1);
1800 INSN(smaddl, 0b100, 0b001, 0);
1801 INSN(smsubl, 0b100, 0b001, 1);
1802 INSN(umaddl, 0b100, 0b101, 0);
1803 INSN(umsubl, 0b100, 0b101, 1);
1804
1805 #undef INSN
1806
1807 #define INSN(NAME, op54, op31, o0) \
1808 void NAME(Register Rd, Register Rn, Register Rm) { \
1809 data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \
1810 }
1811
1812 INSN(smulh, 0b100, 0b010, 0);
1813 INSN(umulh, 0b100, 0b110, 0);
1814
1815 #undef INSN
1816
1817 // Floating-point data-processing (1 source)
1818 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1819 FloatRegister Vd, FloatRegister Vn) {
1820 starti;
1821 f(op31, 31, 29);
1822 f(0b11110, 28, 24);
1823 f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10);
1824 rf(Vn, 5), rf(Vd, 0);
1825 }
1826
1827 #define INSN(NAME, op31, type, opcode) \
1828 void NAME(FloatRegister Vd, FloatRegister Vn) { \
1829 data_processing(op31, type, opcode, Vd, Vn); \
1830 }
1831
1832 private:
1833 INSN(i_fmovs, 0b000, 0b00, 0b000000);
1834 public:
1835 INSN(fabss, 0b000, 0b00, 0b000001);
1836 INSN(fnegs, 0b000, 0b00, 0b000010);
1837 INSN(fsqrts, 0b000, 0b00, 0b000011);
1838 INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision
1839
1840 private:
1841 INSN(i_fmovd, 0b000, 0b01, 0b000000);
1842 public:
1843 INSN(fabsd, 0b000, 0b01, 0b000001);
1844 INSN(fnegd, 0b000, 0b01, 0b000010);
1845 INSN(fsqrtd, 0b000, 0b01, 0b000011);
1846 INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision
1847
1848 void fmovd(FloatRegister Vd, FloatRegister Vn) {
1849 assert(Vd != Vn, "should be");
1850 i_fmovd(Vd, Vn);
1851 }
1852
1853 void fmovs(FloatRegister Vd, FloatRegister Vn) {
1854 assert(Vd != Vn, "should be");
1855 i_fmovs(Vd, Vn);
1856 }
1857
1858 #undef INSN
1859
1860 // Floating-point data-processing (2 source)
1861 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1862 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1863 starti;
1864 f(op31, 31, 29);
1865 f(0b11110, 28, 24);
1866 f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1867 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1868 }
1869
1870 #define INSN(NAME, op31, type, opcode) \
1871 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \
1872 data_processing(op31, type, opcode, Vd, Vn, Vm); \
1873 }
1874
1875 INSN(fmuls, 0b000, 0b00, 0b0000);
1876 INSN(fdivs, 0b000, 0b00, 0b0001);
1877 INSN(fadds, 0b000, 0b00, 0b0010);
1878 INSN(fsubs, 0b000, 0b00, 0b0011);
1879 INSN(fmaxs, 0b000, 0b00, 0b0100);
1880 INSN(fmins, 0b000, 0b00, 0b0101);
1881 INSN(fnmuls, 0b000, 0b00, 0b1000);
1882
1883 INSN(fmuld, 0b000, 0b01, 0b0000);
1884 INSN(fdivd, 0b000, 0b01, 0b0001);
1885 INSN(faddd, 0b000, 0b01, 0b0010);
1886 INSN(fsubd, 0b000, 0b01, 0b0011);
1887 INSN(fmaxd, 0b000, 0b01, 0b0100);
1888 INSN(fmind, 0b000, 0b01, 0b0101);
1889 INSN(fnmuld, 0b000, 0b01, 0b1000);
1890
1891 #undef INSN
1892
1893 // Floating-point data-processing (3 source)
1894 void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1895 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1896 FloatRegister Va) {
1897 starti;
1898 f(op31, 31, 29);
1899 f(0b11111, 28, 24);
1900 f(type, 23, 22), f(o1, 21), f(o0, 15);
1901 rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1902 }
1903
1904 #define INSN(NAME, op31, type, o1, o0) \
1905 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \
1906 FloatRegister Va) { \
1907 data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \
1908 }
1909
1910 INSN(fmadds, 0b000, 0b00, 0, 0);
1911 INSN(fmsubs, 0b000, 0b00, 0, 1);
1912 INSN(fnmadds, 0b000, 0b00, 1, 0);
1913 INSN(fnmsubs, 0b000, 0b00, 1, 1);
1914
1915 INSN(fmaddd, 0b000, 0b01, 0, 0);
1916 INSN(fmsubd, 0b000, 0b01, 0, 1);
1917 INSN(fnmaddd, 0b000, 0b01, 1, 0);
1918 INSN(fnmsub, 0b000, 0b01, 1, 1);
1919
1920 #undef INSN
1921
1922 // Floating-point conditional select
1923 void fp_conditional_select(unsigned op31, unsigned type,
1924 unsigned op1, unsigned op2,
1925 Condition cond, FloatRegister Vd,
1926 FloatRegister Vn, FloatRegister Vm) {
1927 starti;
1928 f(op31, 31, 29);
1929 f(0b11110, 28, 24);
1930 f(type, 23, 22);
1931 f(op1, 21, 21);
1932 f(op2, 11, 10);
1933 f(cond, 15, 12);
1934 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1935 }
1936
1937 #define INSN(NAME, op31, type, op1, op2) \
1938 void NAME(FloatRegister Vd, FloatRegister Vn, \
1939 FloatRegister Vm, Condition cond) { \
1940 fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm); \
1941 }
1942
1943 INSN(fcsels, 0b000, 0b00, 0b1, 0b11);
1944 INSN(fcseld, 0b000, 0b01, 0b1, 0b11);
1945
1946 #undef INSN
1947
1948 // Floating-point<->integer conversions
1949 void float_int_convert(unsigned op31, unsigned type,
1950 unsigned rmode, unsigned opcode,
1951 Register Rd, Register Rn) {
1952 starti;
1953 f(op31, 31, 29);
1954 f(0b11110, 28, 24);
1955 f(type, 23, 22), f(1, 21), f(rmode, 20, 19);
1956 f(opcode, 18, 16), f(0b000000, 15, 10);
1957 zrf(Rn, 5), zrf(Rd, 0);
1958 }
1959
1960 #define INSN(NAME, op31, type, rmode, opcode) \
1961 void NAME(Register Rd, FloatRegister Vn) { \
1962 float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \
1963 }
1964
1965 INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000);
1966 INSN(fcvtzs, 0b100, 0b00, 0b11, 0b000);
1967 INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000);
1968 INSN(fcvtzd, 0b100, 0b01, 0b11, 0b000);
1969
1970 INSN(fmovs, 0b000, 0b00, 0b00, 0b110);
1971 INSN(fmovd, 0b100, 0b01, 0b00, 0b110);
1972
1973 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110);
1974
1975 #undef INSN
1976
1977 #define INSN(NAME, op31, type, rmode, opcode) \
1978 void NAME(FloatRegister Vd, Register Rn) { \
1979 float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \
1980 }
1981
1982 INSN(fmovs, 0b000, 0b00, 0b00, 0b111);
1983 INSN(fmovd, 0b100, 0b01, 0b00, 0b111);
1984
1985 INSN(scvtfws, 0b000, 0b00, 0b00, 0b010);
1986 INSN(scvtfs, 0b100, 0b00, 0b00, 0b010);
1987 INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010);
1988 INSN(scvtfd, 0b100, 0b01, 0b00, 0b010);
1989
1990 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111);
1991
1992 #undef INSN
1993
1994 // Floating-point compare
1995 void float_compare(unsigned op31, unsigned type,
1996 unsigned op, unsigned op2,
1997 FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) {
1998 starti;
1999 f(op31, 31, 29);
2000 f(0b11110, 28, 24);
2001 f(type, 23, 22), f(1, 21);
2002 f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0);
2003 rf(Vn, 5), rf(Vm, 16);
2004 }
2005
2006
2007 #define INSN(NAME, op31, type, op, op2) \
2008 void NAME(FloatRegister Vn, FloatRegister Vm) { \
2009 float_compare(op31, type, op, op2, Vn, Vm); \
2010 }
2011
2012 #define INSN1(NAME, op31, type, op, op2) \
2013 void NAME(FloatRegister Vn, double d) { \
2014 assert_cond(d == 0.0); \
2015 float_compare(op31, type, op, op2, Vn); \
2016 }
2017
2018 INSN(fcmps, 0b000, 0b00, 0b00, 0b00000);
2019 INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000);
2020 // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000);
2021 // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000);
2022
2023 INSN(fcmpd, 0b000, 0b01, 0b00, 0b00000);
2024 INSN1(fcmpd, 0b000, 0b01, 0b00, 0b01000);
2025 // INSN(fcmped, 0b000, 0b01, 0b00, 0b10000);
2026 // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000);
2027
2028 #undef INSN
2029 #undef INSN1
2030
2031 // Floating-point Move (immediate)
2032 private:
2033 unsigned pack(double value);
2034
2035 void fmov_imm(FloatRegister Vn, double value, unsigned size) {
2036 starti;
2037 f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21);
2038 f(pack(value), 20, 13), f(0b10000000, 12, 5);
2039 rf(Vn, 0);
2040 }
2041
2042 public:
2043
2044 void fmovs(FloatRegister Vn, double value) {
2045 if (value)
2046 fmov_imm(Vn, value, 0b00);
2047 else
2048 fmovs(Vn, zr);
2049 }
2050 void fmovd(FloatRegister Vn, double value) {
2051 if (value)
2052 fmov_imm(Vn, value, 0b01);
2053 else
2054 fmovd(Vn, zr);
2055 }
2056
2057 // Floating-point rounding
2058 // type: half-precision = 11
2059 // single = 00
2060 // double = 01
2061 // rmode: A = Away = 100
2062 // I = current = 111
2063 // M = MinusInf = 010
2064 // N = eveN = 000
2065 // P = PlusInf = 001
2066 // X = eXact = 110
2067 // Z = Zero = 011
2068 void float_round(unsigned type, unsigned rmode, FloatRegister Rd, FloatRegister Rn) {
2069 starti;
2070 f(0b00011110, 31, 24);
2071 f(type, 23, 22);
2072 f(0b1001, 21, 18);
2073 f(rmode, 17, 15);
2074 f(0b10000, 14, 10);
2075 rf(Rn, 5), rf(Rd, 0);
2076 }
2077 #define INSN(NAME, type, rmode) \
2078 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2079 float_round(type, rmode, Vd, Vn); \
2080 }
2081
2082 public:
2083 INSN(frintah, 0b11, 0b100);
2084 INSN(frintih, 0b11, 0b111);
2085 INSN(frintmh, 0b11, 0b010);
2086 INSN(frintnh, 0b11, 0b000);
2087 INSN(frintph, 0b11, 0b001);
2088 INSN(frintxh, 0b11, 0b110);
2089 INSN(frintzh, 0b11, 0b011);
2090
2091 INSN(frintas, 0b00, 0b100);
2092 INSN(frintis, 0b00, 0b111);
2093 INSN(frintms, 0b00, 0b010);
2094 INSN(frintns, 0b00, 0b000);
2095 INSN(frintps, 0b00, 0b001);
2096 INSN(frintxs, 0b00, 0b110);
2097 INSN(frintzs, 0b00, 0b011);
2098
2099 INSN(frintad, 0b01, 0b100);
2100 INSN(frintid, 0b01, 0b111);
2101 INSN(frintmd, 0b01, 0b010);
2102 INSN(frintnd, 0b01, 0b000);
2103 INSN(frintpd, 0b01, 0b001);
2104 INSN(frintxd, 0b01, 0b110);
2105 INSN(frintzd, 0b01, 0b011);
2106 #undef INSN
2107
2108 /* SIMD extensions
2109 *
2110 * We just use FloatRegister in the following. They are exactly the same
2111 * as SIMD registers.
2112 */
2113 public:
2114
2115 enum SIMD_Arrangement {
2116 T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
2117 };
2118
2119 enum SIMD_RegVariant {
2120 B, H, S, D, Q
2121 };
2122
2123 private:
2124 static short SIMD_Size_in_bytes[];
2125
2126 public:
2127 #define INSN(NAME, op) \
2128 void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \
2129 ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
2130 } \
2131
2132 INSN(ldr, 1);
2133 INSN(str, 0);
2134
2135 #undef INSN
2136
2137 private:
2138
2139 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) {
2140 starti;
2141 f(0,31), f((int)T & 1, 30);
2142 f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
2143 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2144 }
2145 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2146 int imm, int op1, int op2, int regs) {
2147
2148 bool replicate = op2 >> 2 == 3;
2149 // post-index value (imm) is formed differently for replicate/non-replicate ld* instructions
2150 int expectedImmediate = replicate ? regs * (1 << (T >> 1)) : SIMD_Size_in_bytes[T] * regs;
2151 guarantee(T < T1Q , "incorrect arrangement");
2152 guarantee(imm == expectedImmediate, "bad offset");
2153 starti;
2154 f(0,31), f((int)T & 1, 30);
2155 f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
2156 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2157 }
2158 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2159 Register Xm, int op1, int op2) {
2160 starti;
2161 f(0,31), f((int)T & 1, 30);
2162 f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
2163 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2164 }
2165
2166 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2, int regs) {
2167 switch (a.getMode()) {
2168 case Address::base_plus_offset:
2169 guarantee(a.offset() == 0, "no offset allowed here");
2170 ld_st(Vt, T, a.base(), op1, op2);
2171 break;
2172 case Address::post:
2173 ld_st(Vt, T, a.base(), a.offset(), op1, op2, regs);
2174 break;
2175 case Address::post_reg:
2176 ld_st(Vt, T, a.base(), a.index(), op1, op2);
2177 break;
2178 default:
2179 ShouldNotReachHere();
2180 }
2181 }
2182
2183 public:
2184
2185 #define INSN1(NAME, op1, op2) \
2186 void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \
2187 ld_st(Vt, T, a, op1, op2, 1); \
2188 }
2189
2190 #define INSN2(NAME, op1, op2) \
2191 void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
2192 assert(Vt->successor() == Vt2, "Registers must be ordered"); \
2193 ld_st(Vt, T, a, op1, op2, 2); \
2194 }
2195
2196 #define INSN3(NAME, op1, op2) \
2197 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
2198 SIMD_Arrangement T, const Address &a) { \
2199 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \
2200 "Registers must be ordered"); \
2201 ld_st(Vt, T, a, op1, op2, 3); \
2202 }
2203
2204 #define INSN4(NAME, op1, op2) \
2205 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
2206 FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \
2207 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \
2208 Vt3->successor() == Vt4, "Registers must be ordered"); \
2209 ld_st(Vt, T, a, op1, op2, 4); \
2210 }
2211
2212 INSN1(ld1, 0b001100010, 0b0111);
2213 INSN2(ld1, 0b001100010, 0b1010);
2214 INSN3(ld1, 0b001100010, 0b0110);
2215 INSN4(ld1, 0b001100010, 0b0010);
2216
2217 INSN2(ld2, 0b001100010, 0b1000);
2218 INSN3(ld3, 0b001100010, 0b0100);
2219 INSN4(ld4, 0b001100010, 0b0000);
2220
2221 INSN1(st1, 0b001100000, 0b0111);
2222 INSN2(st1, 0b001100000, 0b1010);
2223 INSN3(st1, 0b001100000, 0b0110);
2224 INSN4(st1, 0b001100000, 0b0010);
2225
2226 INSN2(st2, 0b001100000, 0b1000);
2227 INSN3(st3, 0b001100000, 0b0100);
2228 INSN4(st4, 0b001100000, 0b0000);
2229
2230 INSN1(ld1r, 0b001101010, 0b1100);
2231 INSN2(ld2r, 0b001101011, 0b1100);
2232 INSN3(ld3r, 0b001101010, 0b1110);
2233 INSN4(ld4r, 0b001101011, 0b1110);
2234
2235 #undef INSN1
2236 #undef INSN2
2237 #undef INSN3
2238 #undef INSN4
2239
2240 #define INSN(NAME, opc) \
2241 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2242 starti; \
2243 assert(T == T8B || T == T16B, "must be T8B or T16B"); \
2244 f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \
2245 rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2246 }
2247
2248 INSN(eor, 0b101110001);
2249 INSN(orr, 0b001110101);
2250 INSN(andr, 0b001110001);
2251 INSN(bic, 0b001110011);
2252 INSN(bif, 0b101110111);
2253 INSN(bit, 0b101110101);
2254 INSN(bsl, 0b101110011);
2255 INSN(orn, 0b001110111);
2256
2257 #undef INSN
2258
2259 #define INSN(NAME, opc, opc2, acceptT2D) \
2260 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2261 guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \
2262 if (!acceptT2D) guarantee(T != T2D, "incorrect arrangement"); \
2263 starti; \
2264 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2265 f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \
2266 rf(Vn, 5), rf(Vd, 0); \
2267 }
2268
2269 INSN(addv, 0, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2270 INSN(subv, 1, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2271 INSN(mulv, 0, 0b100111, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2272 INSN(mlav, 0, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2273 INSN(mlsv, 1, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2274 INSN(sshl, 0, 0b010001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2275 INSN(ushl, 1, 0b010001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2276 INSN(addpv, 0, 0b101111, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2277 INSN(smullv, 0, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2278 INSN(umullv, 1, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2279 INSN(umlalv, 1, 0b100000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2280
2281 #undef INSN
2282
2283 #define INSN(NAME, opc, opc2, accepted) \
2284 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2285 guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \
2286 if (accepted < 3) guarantee(T != T2D, "incorrect arrangement"); \
2287 if (accepted < 2) guarantee(T != T2S, "incorrect arrangement"); \
2288 if (accepted < 1) guarantee(T == T8B || T == T16B, "incorrect arrangement"); \
2289 starti; \
2290 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2291 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \
2292 rf(Vn, 5), rf(Vd, 0); \
2293 }
2294
2295 INSN(absr, 0, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2296 INSN(negr, 1, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2297 INSN(notr, 1, 0b100000010110, 0); // accepted arrangements: T8B, T16B
2298 INSN(addv, 0, 0b110001101110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
2299 INSN(cls, 0, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2300 INSN(clz, 1, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2301 INSN(cnt, 0, 0b100000010110, 0); // accepted arrangements: T8B, T16B
2302 INSN(uaddlp, 1, 0b100000001010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2303 INSN(uaddlv, 1, 0b110000001110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
2304
2305 #undef INSN
2306
2307 #define INSN(NAME, opc) \
2308 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2309 starti; \
2310 assert(T == T4S, "arrangement must be T4S"); \
2311 f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24), f(opc, 23), \
2312 f(T == T4S ? 0 : 1, 22), f(0b110000111110, 21, 10); rf(Vn, 5), rf(Vd, 0); \
2313 }
2314
2315 INSN(fmaxv, 0);
2316 INSN(fminv, 1);
2317
2318 #undef INSN
2319
2320 #define INSN(NAME, op0, cmode0) \
2321 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \
2322 unsigned cmode = cmode0; \
2323 unsigned op = op0; \
2324 starti; \
2325 assert(lsl == 0 || \
2326 ((T == T4H || T == T8H) && lsl == 8) || \
2327 ((T == T2S || T == T4S) && ((lsl >> 3) < 4) && ((lsl & 7) == 0)), "invalid shift");\
2328 cmode |= lsl >> 2; \
2329 if (T == T4H || T == T8H) cmode |= 0b1000; \
2330 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \
2331 assert(op == 0 && cmode0 == 0, "must be MOVI"); \
2332 cmode = 0b1110; \
2333 if (T == T1D || T == T2D) op = 1; \
2334 } \
2335 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \
2336 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \
2337 rf(Vd, 0); \
2338 }
2339
2340 INSN(movi, 0, 0);
2341 INSN(orri, 0, 1);
2342 INSN(mvni, 1, 0);
2343 INSN(bici, 1, 1);
2344
2345 #undef INSN
2346
2347 #define INSN(NAME, op1, op2, op3) \
2348 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2349 starti; \
2350 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2351 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \
2352 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2353 }
2354
2355 INSN(fadd, 0, 0, 0b110101);
2356 INSN(fdiv, 1, 0, 0b111111);
2357 INSN(fmul, 1, 0, 0b110111);
2358 INSN(fsub, 0, 1, 0b110101);
2359 INSN(fmla, 0, 0, 0b110011);
2360 INSN(fmls, 0, 1, 0b110011);
2361 INSN(fmax, 0, 0, 0b111101);
2362 INSN(fmin, 0, 1, 0b111101);
2363
2364 #undef INSN
2365
2366 #define INSN(NAME, opc) \
2367 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2368 starti; \
2369 assert(T == T4S, "arrangement must be T4S"); \
2370 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2371 }
2372
2373 INSN(sha1c, 0b000000);
2374 INSN(sha1m, 0b001000);
2375 INSN(sha1p, 0b000100);
2376 INSN(sha1su0, 0b001100);
2377 INSN(sha256h2, 0b010100);
2378 INSN(sha256h, 0b010000);
2379 INSN(sha256su1, 0b011000);
2380
2381 #undef INSN
2382
2383 #define INSN(NAME, opc) \
2384 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2385 starti; \
2386 assert(T == T4S, "arrangement must be T4S"); \
2387 f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2388 }
2389
2390 INSN(sha1h, 0b000010);
2391 INSN(sha1su1, 0b000110);
2392 INSN(sha256su0, 0b001010);
2393
2394 #undef INSN
2395
2396 #define INSN(NAME, opc) \
2397 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2398 starti; \
2399 assert(T == T2D, "arrangement must be T2D"); \
2400 f(0b11001110011, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2401 }
2402
2403 INSN(sha512h, 0b100000);
2404 INSN(sha512h2, 0b100001);
2405 INSN(sha512su1, 0b100010);
2406
2407 #undef INSN
2408
2409 #define INSN(NAME, opc) \
2410 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2411 starti; \
2412 assert(T == T2D, "arrangement must be T2D"); \
2413 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2414 }
2415
2416 INSN(sha512su0, 0b1100111011000000100000);
2417
2418 #undef INSN
2419
2420 #define INSN(NAME, opc) \
2421 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2422 starti; \
2423 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2424 }
2425
2426 INSN(aese, 0b0100111000101000010010);
2427 INSN(aesd, 0b0100111000101000010110);
2428 INSN(aesmc, 0b0100111000101000011010);
2429 INSN(aesimc, 0b0100111000101000011110);
2430
2431 #undef INSN
2432
2433 #define INSN(NAME, op1, op2) \
2434 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index = 0) { \
2435 starti; \
2436 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2437 assert(index >= 0 && ((T == T2D && index <= 1) || (T != T2D && index <= 3)), "invalid index"); \
2438 f(0, 31), f((int)T & 1, 30), f(op1, 29); f(0b011111, 28, 23); \
2439 f(T == T2D ? 1 : 0, 22), f(T == T2D ? 0 : index & 1, 21), rf(Vm, 16); \
2440 f(op2, 15, 12), f(T == T2D ? index : (index >> 1), 11), f(0, 10); \
2441 rf(Vn, 5), rf(Vd, 0); \
2442 }
2443
2444 // FMLA/FMLS - Vector - Scalar
2445 INSN(fmlavs, 0, 0b0001);
2446 INSN(fmlsvs, 0, 0b0101);
2447 // FMULX - Vector - Scalar
2448 INSN(fmulxvs, 1, 0b1001);
2449
2450 #undef INSN
2451
2452 // Floating-point Reciprocal Estimate
2453 void frecpe(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) {
2454 assert(type == D || type == S, "Wrong type for frecpe");
2455 starti;
2456 f(0b010111101, 31, 23);
2457 f(type == D ? 1 : 0, 22);
2458 f(0b100001110110, 21, 10);
2459 rf(Vn, 5), rf(Vd, 0);
2460 }
2461
2462 // (double) {a, b} -> (a + b)
2463 void faddpd(FloatRegister Vd, FloatRegister Vn) {
2464 starti;
2465 f(0b0111111001110000110110, 31, 10);
2466 rf(Vn, 5), rf(Vd, 0);
2467 }
2468
2469 void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
2470 starti;
2471 assert(T != Q, "invalid register variant");
2472 f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
2473 f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
2474 }
2475
2476 void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {
2477 starti;
2478 f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21);
2479 f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10);
2480 rf(Vn, 5), rf(Rd, 0);
2481 }
2482
2483 #define INSN(NAME, opc, opc2, isSHR) \
2484 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \
2485 starti; \
2486 /* The encodings for the immh:immb fields (bits 22:16) in *SHR are \
2487 * 0001 xxx 8B/16B, shift = 16 - UInt(immh:immb) \
2488 * 001x xxx 4H/8H, shift = 32 - UInt(immh:immb) \
2489 * 01xx xxx 2S/4S, shift = 64 - UInt(immh:immb) \
2490 * 1xxx xxx 1D/2D, shift = 128 - UInt(immh:immb) \
2491 * (1D is RESERVED) \
2492 * for SHL shift is calculated as: \
2493 * 0001 xxx 8B/16B, shift = UInt(immh:immb) - 8 \
2494 * 001x xxx 4H/8H, shift = UInt(immh:immb) - 16 \
2495 * 01xx xxx 2S/4S, shift = UInt(immh:immb) - 32 \
2496 * 1xxx xxx 1D/2D, shift = UInt(immh:immb) - 64 \
2497 * (1D is RESERVED) \
2498 */ \
2499 assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \
2500 int cVal = (1 << (((T >> 1) + 3) + (isSHR ? 1 : 0))); \
2501 int encodedShift = isSHR ? cVal - shift : cVal + shift; \
2502 f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23), \
2503 f(encodedShift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2504 }
2505
2506 INSN(shl, 0, 0b010101, /* isSHR = */ false);
2507 INSN(sshr, 0, 0b000001, /* isSHR = */ true);
2508 INSN(ushr, 1, 0b000001, /* isSHR = */ true);
2509
2510 #undef INSN
2511
2512 private:
2513 void _ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2514 starti;
2515 /* The encodings for the immh:immb fields (bits 22:16) are
2516 * 0001 xxx 8H, 8B/16b shift = xxx
2517 * 001x xxx 4S, 4H/8H shift = xxxx
2518 * 01xx xxx 2D, 2S/4S shift = xxxxx
2519 * 1xxx xxx RESERVED
2520 */
2521 assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
2522 assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
2523 f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16);
2524 f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2525 }
2526
2527 public:
2528 void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2529 assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement");
2530 _ushll(Vd, Ta, Vn, Tb, shift);
2531 }
2532
2533 void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2534 assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement");
2535 _ushll(Vd, Ta, Vn, Tb, shift);
2536 }
2537
2538 // Move from general purpose register
2539 // mov Vd.T[index], Rn
2540 void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
2541 starti;
2542 f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2543 f(0b000111, 15, 10), zrf(Xn, 5), rf(Vd, 0);
2544 }
2545
2546 // Move to general purpose register
2547 // mov Rd, Vn.T[index]
2548 void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
2549 guarantee(T >= T2S && T < T1Q, "only D and S arrangements are supported");
2550 starti;
2551 f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
2552 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2553 f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
2554 }
2555
2556 private:
2557 void _pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2558 starti;
2559 assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
2560 (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
2561 int size = (Ta == T1Q) ? 0b11 : 0b00;
2562 f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
2563 f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0);
2564 }
2565
2566 public:
2567 void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2568 assert(Tb == T1D || Tb == T8B, "pmull assumes T1D or T8B as the second size specifier");
2569 _pmull(Vd, Ta, Vn, Vm, Tb);
2570 }
2571
2572 void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2573 assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
2574 _pmull(Vd, Ta, Vn, Vm, Tb);
2575 }
2576
2577 void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
2578 starti;
2579 int size_b = (int)Tb >> 1;
2580 int size_a = (int)Ta >> 1;
2581 assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
2582 f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
2583 f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
2584 }
2585
2586 void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
2587 {
2588 starti;
2589 assert(T != T1D, "reserved encoding");
2590 f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2591 f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), zrf(Xs, 5), rf(Vd, 0);
2592 }
2593
2594 void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
2595 {
2596 starti;
2597 assert(T != T1D, "reserved encoding");
2598 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2599 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2600 f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2601 }
2602
2603 // AdvSIMD ZIP/UZP/TRN
2604 #define INSN(NAME, opcode) \
2605 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2606 guarantee(T != T1D && T != T1Q, "invalid arrangement"); \
2607 starti; \
2608 f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0, 15); \
2609 f(opcode, 14, 12), f(0b10, 11, 10); \
2610 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); \
2611 f(T & 1, 30), f(T >> 1, 23, 22); \
2612 }
2613
2614 INSN(uzp1, 0b001);
2615 INSN(trn1, 0b010);
2616 INSN(zip1, 0b011);
2617 INSN(uzp2, 0b101);
2618 INSN(trn2, 0b110);
2619 INSN(zip2, 0b111);
2620
2621 #undef INSN
2622
2623 // CRC32 instructions
2624 #define INSN(NAME, c, sf, sz) \
2625 void NAME(Register Rd, Register Rn, Register Rm) { \
2626 starti; \
2627 f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12); \
2628 f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
2629 }
2630
2631 INSN(crc32b, 0, 0, 0b00);
2632 INSN(crc32h, 0, 0, 0b01);
2633 INSN(crc32w, 0, 0, 0b10);
2634 INSN(crc32x, 0, 1, 0b11);
2635 INSN(crc32cb, 1, 0, 0b00);
2636 INSN(crc32ch, 1, 0, 0b01);
2637 INSN(crc32cw, 1, 0, 0b10);
2638 INSN(crc32cx, 1, 1, 0b11);
2639
2640 #undef INSN
2641
2642 // Table vector lookup
2643 #define INSN(NAME, op) \
2644 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \
2645 starti; \
2646 assert(T == T8B || T == T16B, "invalid arrangement"); \
2647 assert(0 < registers && registers <= 4, "invalid number of registers"); \
2648 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \
2649 f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2650 }
2651
2652 INSN(tbl, 0);
2653 INSN(tbx, 1);
2654
2655 #undef INSN
2656
2657 // AdvSIMD two-reg misc
2658 // In this instruction group, the 2 bits in the size field ([23:22]) may be
2659 // fixed or determined by the "SIMD_Arrangement T", or both. The additional
2660 // parameter "tmask" is a 2-bit mask used to indicate which bits in the size
2661 // field are determined by the SIMD_Arrangement. The bit of "tmask" should be
2662 // set to 1 if corresponding bit marked as "x" in the ArmARM.
2663 #define INSN(NAME, U, size, tmask, opcode) \
2664 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2665 starti; \
2666 assert((ASSERTION), MSG); \
2667 f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24); \
2668 f(size | ((int)(T >> 1) & tmask), 23, 22), f(0b10000, 21, 17); \
2669 f(opcode, 16, 12), f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2670 }
2671
2672 #define MSG "invalid arrangement"
2673
2674 #define ASSERTION (T == T2S || T == T4S || T == T2D)
2675 INSN(fsqrt, 1, 0b10, 0b01, 0b11111);
2676 INSN(fabs, 0, 0b10, 0b01, 0b01111);
2677 INSN(fneg, 1, 0b10, 0b01, 0b01111);
2678 INSN(frintn, 0, 0b00, 0b01, 0b11000);
2679 INSN(frintm, 0, 0b00, 0b01, 0b11001);
2680 INSN(frintp, 0, 0b10, 0b01, 0b11000);
2681 #undef ASSERTION
2682
2683 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
2684 INSN(rev64, 0, 0b00, 0b11, 0b00000);
2685 #undef ASSERTION
2686
2687 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
2688 INSN(rev32, 1, 0b00, 0b11, 0b00000);
2689 #undef ASSERTION
2690
2691 #define ASSERTION (T == T8B || T == T16B)
2692 INSN(rev16, 0, 0b00, 0b11, 0b00001);
2693 INSN(rbit, 1, 0b01, 0b00, 0b00101);
2694 #undef ASSERTION
2695
2696 #undef MSG
2697
2698 #undef INSN
2699
2700 void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
2701 {
2702 starti;
2703 assert(T == T8B || T == T16B, "invalid arrangement");
2704 assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
2705 f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
2706 rf(Vm, 16), f(0, 15), f(index, 14, 11);
2707 f(0, 10), rf(Vn, 5), rf(Vd, 0);
2708 }
2709
2710 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2711 }
2712
2713 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2714 Register tmp,
2715 int offset) {
2716 ShouldNotCallThis();
2717 return RegisterOrConstant();
2718 }
2719
2720 // Stack overflow checking
2721 virtual void bang_stack_with_offset(int offset);
2722
2723 static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
2724 static bool operand_valid_for_add_sub_immediate(int64_t imm);
2725 static bool operand_valid_for_float_immediate(double imm);
2726
2727 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
2728 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
2729 };
2730
2731 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
2732 Assembler::Membar_mask_bits b) {
2733 return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
2734 }
2735
2736 Instruction_aarch64::~Instruction_aarch64() {
2737 assem->emit();
2738 }
2739
2740 #undef starti
2741
2742 // Invert a condition
2743 inline const Assembler::Condition operator~(const Assembler::Condition cond) {
2744 return Assembler::Condition(int(cond) ^ 1);
2745 }
2746
2747 class BiasedLockingCounters;
2748
2749 extern "C" void das(uint64_t start, int len);
2750
2751 #endif // CPU_AARCH64_ASSEMBLER_AARCH64_HPP