/* * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2014, 2020 Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. */ #include #include #include "precompiled.hpp" #include "asm/assembler.hpp" #include "asm/assembler.inline.hpp" #include "interpreter/interpreter.hpp" #ifndef PRODUCT const uintptr_t Assembler::asm_bp = 0x00007fffee09ac88; #endif #include "compiler/disassembler.hpp" #include "memory/resourceArea.hpp" #include "runtime/interfaceSupport.inline.hpp" #include "runtime/sharedRuntime.hpp" #include "immediate_aarch64.hpp" extern "C" void entry(CodeBuffer *cb); #define __ _masm. #ifdef PRODUCT #define BLOCK_COMMENT(str) /* nothing */ #else #define BLOCK_COMMENT(str) block_comment(str) #endif #define BIND(label) bind(label); __ BLOCK_COMMENT(#label ":") static float unpack(unsigned value); short Assembler::SIMD_Size_in_bytes[] = { // T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q 8, 16, 8, 16, 8, 16, 8, 16, 16 }; #ifdef ASSERT static void asm_check(const unsigned int *insns, const unsigned int *insns1, size_t len) { bool ok = true; for (unsigned int i = 0; i < len; i++) { if (insns[i] != insns1[i]) { ok = false; printf("Ours:\n"); Disassembler::decode((address)&insns1[i], (address)&insns1[i+1]); printf("Theirs:\n"); Disassembler::decode((address)&insns[i], (address)&insns[i+1]); printf("\n"); } } assert(ok, "Assembler smoke test failed"); } void entry(CodeBuffer *cb) { // { // for (int i = 0; i < 256; i+=16) // { // printf("\"%20.20g\", ", unpack(i)); // printf("\"%20.20g\", ", unpack(i+1)); // } // printf("\n"); // } Assembler _masm(cb); address entry = __ pc(); // Smoke test for assembler // BEGIN Generated code -- do not edit // Generated by aarch64-asmtest.py Label back, forth; __ bind(back); // ArithOp __ add(r20, r0, r26, Assembler::LSL, 52); // add x20, x0, x26, LSL #52 __ sub(r5, r28, r3, Assembler::ASR, 54); // sub x5, x28, x3, ASR #54 __ adds(r11, r22, r3, Assembler::ASR, 39); // adds x11, x22, x3, ASR #39 __ subs(r11, r3, r12, Assembler::LSR, 25); // subs x11, x3, x12, LSR #25 __ addw(r27, r12, r13, Assembler::LSL, 14); // add w27, w12, w13, LSL #14 __ subw(r10, r21, r27, Assembler::ASR, 7); // sub w10, w21, w27, ASR #7 __ addsw(r3, r14, r16, Assembler::LSL, 4); // adds w3, w14, w16, LSL #4 __ subsw(r1, r19, r29, Assembler::LSL, 5); // subs w1, w19, w29, LSL #5 __ andr(r16, r17, r27, Assembler::LSR, 6); // and x16, x17, x27, LSR #6 __ orr(r22, r28, r28, Assembler::LSL, 35); // orr x22, x28, x28, LSL #35 __ eor(r11, r10, r28, Assembler::LSR, 51); // eor x11, x10, x28, LSR #51 __ ands(r13, r8, r14, Assembler::ASR, 48); // ands x13, x8, x14, ASR #48 __ andw(r1, r3, r1, Assembler::LSR, 3); // and w1, w3, w1, LSR #3 __ orrw(r9, r8, r5, Assembler::ASR, 22); // orr w9, w8, w5, ASR #22 __ eorw(r2, r28, r27, Assembler::ASR, 19); // eor w2, w28, w27, ASR #19 __ andsw(r24, r9, r7, Assembler::LSL, 14); // ands w24, w9, w7, LSL #14 __ bic(r11, r19, r25, Assembler::ASR, 32); // bic x11, x19, x25, ASR #32 __ orn(r24, r24, r29, Assembler::LSL, 28); // orn x24, x24, x29, LSL #28 __ eon(r11, r16, r17, Assembler::ASR, 27); // eon x11, x16, x17, ASR #27 __ bics(r5, r13, r10, Assembler::LSR, 58); // bics x5, x13, x10, LSR #58 __ bicw(r5, r10, r21, Assembler::LSL, 29); // bic w5, w10, w21, LSL #29 __ ornw(r4, r11, r21, Assembler::LSL, 19); // orn w4, w11, w21, LSL #19 __ eonw(r21, r28, r28, Assembler::LSR, 15); // eon w21, w28, w28, LSR #15 __ bicsw(r6, r10, r14, Assembler::LSL, 28); // bics w6, w10, w14, LSL #28 // AddSubImmOp __ addw(r10, r22, 945u); // add w10, w22, #945 __ addsw(r15, r11, 935u); // adds w15, w11, #935 __ subw(r5, r6, 703u); // sub w5, w6, #703 __ subsw(r19, r0, 568u); // subs w19, w0, #568 __ add(r20, r8, 608u); // add x20, x8, #608 __ adds(r16, r6, 269u); // adds x16, x6, #269 __ sub(r23, r0, 877u); // sub x23, x0, #877 __ subs(r26, r25, 801u); // subs x26, x25, #801 // LogicalImmOp __ andw(r12, r16, 4294459391ull); // and w12, w16, #0xfff83fff __ orrw(r1, r24, 4229955583ull); // orr w1, w24, #0xfc1fffff __ eorw(r19, r3, 16744448ull); // eor w19, w3, #0xff8000 __ andsw(r29, r9, 4290777087ull); // ands w29, w9, #0xffc00fff __ andr(r26, r5, 18446744073172942847ull); // and x26, x5, #0xffffffffe003ffff __ orr(r24, r14, 1150687262887383032ull); // orr x24, x14, #0xff80ff80ff80ff8 __ eor(r4, r0, 18446744073709289487ull); // eor x4, x0, #0xfffffffffffc000f __ ands(r28, r6, 536608768ull); // ands x28, x6, #0x1ffc0000 // AbsOp __ b(__ pc()); // b . __ b(back); // b back __ b(forth); // b forth __ bl(__ pc()); // bl . __ bl(back); // bl back __ bl(forth); // bl forth // RegAndAbsOp __ cbzw(r21, __ pc()); // cbz w21, . __ cbzw(r21, back); // cbz w21, back __ cbzw(r21, forth); // cbz w21, forth __ cbnzw(r12, __ pc()); // cbnz w12, . __ cbnzw(r12, back); // cbnz w12, back __ cbnzw(r12, forth); // cbnz w12, forth __ cbz(r14, __ pc()); // cbz x14, . __ cbz(r14, back); // cbz x14, back __ cbz(r14, forth); // cbz x14, forth __ cbnz(r27, __ pc()); // cbnz x27, . __ cbnz(r27, back); // cbnz x27, back __ cbnz(r27, forth); // cbnz x27, forth __ adr(r14, __ pc()); // adr x14, . __ adr(r14, back); // adr x14, back __ adr(r14, forth); // adr x14, forth __ _adrp(r22, __ pc()); // adrp x22, . // RegImmAbsOp __ tbz(r0, 5, __ pc()); // tbz x0, #5, . __ tbz(r0, 5, back); // tbz x0, #5, back __ tbz(r0, 5, forth); // tbz x0, #5, forth __ tbnz(r3, 11, __ pc()); // tbnz x3, #11, . __ tbnz(r3, 11, back); // tbnz x3, #11, back __ tbnz(r3, 11, forth); // tbnz x3, #11, forth // MoveWideImmOp __ movnw(r19, 6842, 0); // movn w19, #6842, lsl 0 __ movzw(r28, 5843, 16); // movz w28, #5843, lsl 16 __ movkw(r13, 20344, 16); // movk w13, #20344, lsl 16 __ movn(r1, 1215, 32); // movn x1, #1215, lsl 32 __ movz(r26, 28755, 0); // movz x26, #28755, lsl 0 __ movk(r27, 5762, 48); // movk x27, #5762, lsl 48 // BitfieldOp __ sbfm(r1, r24, 9, 24); // sbfm x1, x24, #9, #24 __ bfmw(r25, r0, 5, 16); // bfm w25, w0, #5, #16 __ ubfmw(r16, r27, 15, 7); // ubfm w16, w27, #15, #7 __ sbfm(r16, r14, 15, 28); // sbfm x16, x14, #15, #28 __ bfm(r24, r10, 0, 13); // bfm x24, x10, #0, #13 __ ubfm(r1, r14, 2, 22); // ubfm x1, x14, #2, #22 // ExtractOp __ extrw(r10, r0, r1, 21); // extr w10, w0, w1, #21 __ extr(r26, r26, r23, 61); // extr x26, x26, x23, #61 // CondBranchOp __ br(Assembler::EQ, __ pc()); // b.EQ . __ br(Assembler::EQ, back); // b.EQ back __ br(Assembler::EQ, forth); // b.EQ forth __ br(Assembler::NE, __ pc()); // b.NE . __ br(Assembler::NE, back); // b.NE back __ br(Assembler::NE, forth); // b.NE forth __ br(Assembler::HS, __ pc()); // b.HS . __ br(Assembler::HS, back); // b.HS back __ br(Assembler::HS, forth); // b.HS forth __ br(Assembler::CS, __ pc()); // b.CS . __ br(Assembler::CS, back); // b.CS back __ br(Assembler::CS, forth); // b.CS forth __ br(Assembler::LO, __ pc()); // b.LO . __ br(Assembler::LO, back); // b.LO back __ br(Assembler::LO, forth); // b.LO forth __ br(Assembler::CC, __ pc()); // b.CC . __ br(Assembler::CC, back); // b.CC back __ br(Assembler::CC, forth); // b.CC forth __ br(Assembler::MI, __ pc()); // b.MI . __ br(Assembler::MI, back); // b.MI back __ br(Assembler::MI, forth); // b.MI forth __ br(Assembler::PL, __ pc()); // b.PL . __ br(Assembler::PL, back); // b.PL back __ br(Assembler::PL, forth); // b.PL forth __ br(Assembler::VS, __ pc()); // b.VS . __ br(Assembler::VS, back); // b.VS back __ br(Assembler::VS, forth); // b.VS forth __ br(Assembler::VC, __ pc()); // b.VC . __ br(Assembler::VC, back); // b.VC back __ br(Assembler::VC, forth); // b.VC forth __ br(Assembler::HI, __ pc()); // b.HI . __ br(Assembler::HI, back); // b.HI back __ br(Assembler::HI, forth); // b.HI forth __ br(Assembler::LS, __ pc()); // b.LS . __ br(Assembler::LS, back); // b.LS back __ br(Assembler::LS, forth); // b.LS forth __ br(Assembler::GE, __ pc()); // b.GE . __ br(Assembler::GE, back); // b.GE back __ br(Assembler::GE, forth); // b.GE forth __ br(Assembler::LT, __ pc()); // b.LT . __ br(Assembler::LT, back); // b.LT back __ br(Assembler::LT, forth); // b.LT forth __ br(Assembler::GT, __ pc()); // b.GT . __ br(Assembler::GT, back); // b.GT back __ br(Assembler::GT, forth); // b.GT forth __ br(Assembler::LE, __ pc()); // b.LE . __ br(Assembler::LE, back); // b.LE back __ br(Assembler::LE, forth); // b.LE forth __ br(Assembler::AL, __ pc()); // b.AL . __ br(Assembler::AL, back); // b.AL back __ br(Assembler::AL, forth); // b.AL forth __ br(Assembler::NV, __ pc()); // b.NV . __ br(Assembler::NV, back); // b.NV back __ br(Assembler::NV, forth); // b.NV forth // ImmOp __ svc(15523); // svc #15523 __ hvc(3191); // hvc #3191 __ smc(18110); // smc #18110 __ brk(2818); // brk #2818 __ hlt(20860); // hlt #20860 // Op __ nop(); // nop __ eret(); // eret __ drps(); // drps __ isb(); // isb // SystemOp __ dsb(Assembler::OSHST); // dsb OSHST __ dmb(Assembler::ISHLD); // dmb ISHLD // OneRegOp __ br(r10); // br x10 __ blr(r22); // blr x22 // LoadStoreExclusiveOp __ stxr(r3, r21, r5); // stxr w3, x21, [x5] __ stlxr(r28, r9, r29); // stlxr w28, x9, [x29] __ ldxr(r28, r7); // ldxr x28, [x7] __ ldaxr(r10, r23); // ldaxr x10, [x23] __ stlr(r7, r26); // stlr x7, [x26] __ ldar(r16, r23); // ldar x16, [x23] // LoadStoreExclusiveOp __ stxrw(r11, r7, r12); // stxr w11, w7, [x12] __ stlxrw(r16, r13, r26); // stlxr w16, w13, [x26] __ ldxrw(r25, r21); // ldxr w25, [x21] __ ldaxrw(r14, r4); // ldaxr w14, [x4] __ stlrw(r26, r9); // stlr w26, [x9] __ ldarw(r0, r23); // ldar w0, [x23] // LoadStoreExclusiveOp __ stxrh(r8, r0, r10); // stxrh w8, w0, [x10] __ stlxrh(r11, r1, r4); // stlxrh w11, w1, [x4] __ ldxrh(r14, r26); // ldxrh w14, [x26] __ ldaxrh(r19, r7); // ldaxrh w19, [x7] __ stlrh(r17, r22); // stlrh w17, [x22] __ ldarh(r20, r6); // ldarh w20, [x6] // LoadStoreExclusiveOp __ stxrb(r25, r8, r6); // stxrb w25, w8, [x6] __ stlxrb(r5, r10, r25); // stlxrb w5, w10, [x25] __ ldxrb(r0, r22); // ldxrb w0, [x22] __ ldaxrb(r8, r3); // ldaxrb w8, [x3] __ stlrb(r5, r2); // stlrb w5, [x2] __ ldarb(r6, r28); // ldarb w6, [x28] // LoadStoreExclusiveOp __ ldxp(r17, r8, r14); // ldxp x17, x8, [x14] __ ldaxp(r14, r3, r2); // ldaxp x14, x3, [x2] __ stxp(r25, r17, r4, r19); // stxp w25, x17, x4, [x19] __ stlxp(r10, r16, r15, r8); // stlxp w10, x16, x15, [x8] // LoadStoreExclusiveOp __ ldxpw(r1, r11, r3); // ldxp w1, w11, [x3] __ ldaxpw(r0, r27, r12); // ldaxp w0, w27, [x12] __ stxpw(r4, r20, r21, r29); // stxp w4, w20, w21, [x29] __ stlxpw(r0, r9, r5, r29); // stlxp w0, w9, w5, [x29] // base_plus_unscaled_offset // LoadStoreOp __ str(r17, Address(r4, -227)); // str x17, [x4, -227] __ strw(r6, Address(r4, -33)); // str w6, [x4, -33] __ strb(r13, Address(r16, 11)); // strb w13, [x16, 11] __ strh(r23, Address(r22, -64)); // strh w23, [x22, -64] __ ldr(r2, Address(r3, 13)); // ldr x2, [x3, 13] __ ldrw(r5, Address(r20, 35)); // ldr w5, [x20, 35] __ ldrb(r2, Address(r10, -15)); // ldrb w2, [x10, -15] __ ldrh(r23, Address(r0, -8)); // ldrh w23, [x0, -8] __ ldrsb(r15, Address(r14, -3)); // ldrsb x15, [x14, -3] __ ldrsh(r3, Address(r3, -12)); // ldrsh x3, [x3, -12] __ ldrshw(r25, Address(r24, -7)); // ldrsh w25, [x24, -7] __ ldrsw(r17, Address(r0, -29)); // ldrsw x17, [x0, -29] __ ldrd(v7, Address(r9, -79)); // ldr d7, [x9, -79] __ ldrs(v11, Address(r11, -68)); // ldr s11, [x11, -68] __ strd(v16, Address(r2, -119)); // str d16, [x2, -119] __ strs(v25, Address(r28, -124)); // str s25, [x28, -124] // pre // LoadStoreOp __ str(r28, Address(__ pre(r19, 82))); // str x28, [x19, 82]! __ strw(r7, Address(__ pre(r13, 50))); // str w7, [x13, 50]! __ strb(r2, Address(__ pre(r19, -32))); // strb w2, [x19, -32]! __ strh(r24, Address(__ pre(r1, -58))); // strh w24, [x1, -58]! __ ldr(r23, Address(__ pre(r29, -143))); // ldr x23, [x29, -143]! __ ldrw(r13, Address(__ pre(r27, 0))); // ldr w13, [x27, 0]! __ ldrb(r11, Address(__ pre(r10, -26))); // ldrb w11, [x10, -26]! __ ldrh(r3, Address(__ pre(r6, -54))); // ldrh w3, [x6, -54]! __ ldrsb(r2, Address(__ pre(r9, 3))); // ldrsb x2, [x9, 3]! __ ldrsh(r28, Address(__ pre(r4, 30))); // ldrsh x28, [x4, 30]! __ ldrshw(r17, Address(__ pre(r0, -23))); // ldrsh w17, [x0, -23]! __ ldrsw(r29, Address(__ pre(r25, -117))); // ldrsw x29, [x25, -117]! __ ldrd(v21, Address(__ pre(r10, -142))); // ldr d21, [x10, -142]! __ ldrs(v11, Address(__ pre(r20, 35))); // ldr s11, [x20, 35]! __ strd(v1, Address(__ pre(r15, -214))); // str d1, [x15, -214]! __ strs(v19, Address(__ pre(r5, -55))); // str s19, [x5, -55]! // post // LoadStoreOp __ str(r28, Address(__ post(r17, -20))); // str x28, [x17], -20 __ strw(r8, Address(__ post(r13, -9))); // str w8, [x13], -9 __ strb(r14, Address(__ post(r24, -23))); // strb w14, [x24], -23 __ strh(r2, Address(__ post(r4, -60))); // strh w2, [x4], -60 __ ldr(r24, Address(__ post(r25, 34))); // ldr x24, [x25], 34 __ ldrw(r16, Address(__ post(r28, -27))); // ldr w16, [x28], -27 __ ldrb(r8, Address(__ post(r23, -27))); // ldrb w8, [x23], -27 __ ldrh(r3, Address(__ post(r0, -58))); // ldrh w3, [x0], -58 __ ldrsb(r14, Address(__ post(r15, -10))); // ldrsb x14, [x15], -10 __ ldrsh(r12, Address(__ post(r1, 13))); // ldrsh x12, [x1], 13 __ ldrshw(r9, Address(__ post(r1, -19))); // ldrsh w9, [x1], -19 __ ldrsw(r29, Address(__ post(r10, -61))); // ldrsw x29, [x10], -61 __ ldrd(v13, Address(__ post(r28, -9))); // ldr d13, [x28], -9 __ ldrs(v20, Address(__ post(r27, -88))); // ldr s20, [x27], -88 __ strd(v7, Address(__ post(r11, -199))); // str d7, [x11], -199 __ strs(v20, Address(__ post(r22, -61))); // str s20, [x22], -61 // base_plus_reg // LoadStoreOp __ str(r3, Address(r10, r16, Address::sxtw(0))); // str x3, [x10, w16, sxtw #0] __ strw(r1, Address(r29, r21, Address::lsl(2))); // str w1, [x29, x21, lsl #2] __ strb(r26, Address(r0, r23, Address::uxtw(0))); // strb w26, [x0, w23, uxtw #0] __ strh(r26, Address(r0, r21, Address::lsl(0))); // strh w26, [x0, x21, lsl #0] __ ldr(r3, Address(r25, r22, Address::lsl(0))); // ldr x3, [x25, x22, lsl #0] __ ldrw(r25, Address(r9, r24, Address::uxtw(2))); // ldr w25, [x9, w24, uxtw #2] __ ldrb(r10, Address(r0, r14, Address::sxtw(0))); // ldrb w10, [x0, w14, sxtw #0] __ ldrh(r2, Address(r21, r20, Address::lsl(1))); // ldrh w2, [x21, x20, lsl #1] __ ldrsb(r19, Address(r27, r28, Address::sxtx(0))); // ldrsb x19, [x27, x28, sxtx #0] __ ldrsh(r1, Address(r8, r3, Address::lsl(1))); // ldrsh x1, [x8, x3, lsl #1] __ ldrshw(r20, Address(r15, r16, Address::sxtx(0))); // ldrsh w20, [x15, x16, sxtx #0] __ ldrsw(r7, Address(r7, r12, Address::lsl(2))); // ldrsw x7, [x7, x12, lsl #2] __ ldrd(v15, Address(r4, r13, Address::sxtw(3))); // ldr d15, [x4, w13, sxtw #3] __ ldrs(v14, Address(r10, r3, Address::uxtw(0))); // ldr s14, [x10, w3, uxtw #0] __ strd(v24, Address(r23, r9, Address::sxtx(3))); // str d24, [x23, x9, sxtx #3] __ strs(v9, Address(r12, r26, Address::uxtw(2))); // str s9, [x12, w26, uxtw #2] // base_plus_scaled_offset // LoadStoreOp __ str(r14, Address(r24, 13472)); // str x14, [x24, 13472] __ strw(r0, Address(r14, 7392)); // str w0, [x14, 7392] __ strb(r23, Address(r19, 1536)); // strb w23, [x19, 1536] __ strh(r15, Address(r11, 3608)); // strh w15, [x11, 3608] __ ldr(r21, Address(r25, 13672)); // ldr x21, [x25, 13672] __ ldrw(r23, Address(r7, 6160)); // ldr w23, [x7, 6160] __ ldrb(r23, Address(r16, 1975)); // ldrb w23, [x16, 1975] __ ldrh(r24, Address(r24, 3850)); // ldrh w24, [x24, 3850] __ ldrsb(r12, Address(r9, 1613)); // ldrsb x12, [x9, 1613] __ ldrsh(r5, Address(r21, 3840)); // ldrsh x5, [x21, 3840] __ ldrshw(r14, Address(r0, 3590)); // ldrsh w14, [x0, 3590] __ ldrsw(r13, Address(r2, 7928)); // ldrsw x13, [x2, 7928] __ ldrd(v15, Address(r19, 15800)); // ldr d15, [x19, 15800] __ ldrs(v23, Address(r5, 6272)); // ldr s23, [x5, 6272] __ strd(v6, Address(r6, 15136)); // str d6, [x6, 15136] __ strs(v9, Address(r11, 6180)); // str s9, [x11, 6180] // pcrel // LoadStoreOp __ ldr(r7, forth); // ldr x7, forth __ ldrw(r29, __ pc()); // ldr w29, . // LoadStoreOp __ prfm(Address(r0, -215)); // prfm PLDL1KEEP, [x0, -215] // LoadStoreOp __ prfm(forth); // prfm PLDL1KEEP, forth // LoadStoreOp __ prfm(Address(r4, r3, Address::uxtw(0))); // prfm PLDL1KEEP, [x4, w3, uxtw #0] // LoadStoreOp __ prfm(Address(r14, 12360)); // prfm PLDL1KEEP, [x14, 12360] // AddSubCarryOp __ adcw(r7, r6, r4); // adc w7, w6, w4 __ adcsw(r27, r12, r5); // adcs w27, w12, w5 __ sbcw(r25, r24, r26); // sbc w25, w24, w26 __ sbcsw(r5, r7, r23); // sbcs w5, w7, w23 __ adc(r22, r11, r1); // adc x22, x11, x1 __ adcs(r13, r9, r29); // adcs x13, x9, x29 __ sbc(r4, r14, r26); // sbc x4, x14, x26 __ sbcs(r28, r29, r24); // sbcs x28, x29, x24 // AddSubExtendedOp __ addw(r17, r21, r21, ext::uxtw, 1); // add w17, w21, w21, uxtw #1 __ addsw(r12, r9, r26, ext::sxth, 3); // adds w12, w9, w26, sxth #3 __ sub(r14, r5, r3, ext::uxth, 1); // sub x14, x5, x3, uxth #1 __ subsw(r17, r26, r6, ext::uxtx, 4); // subs w17, w26, w6, uxtx #4 __ add(r17, r5, r20, ext::sxth, 3); // add x17, x5, x20, sxth #3 __ adds(r16, r1, r25, ext::sxtw, 3); // adds x16, x1, x25, sxtw #3 __ sub(r25, r1, r26, ext::sxtx, 3); // sub x25, x1, x26, sxtx #3 __ subs(r19, r1, r23, ext::sxth, 3); // subs x19, x1, x23, sxth #3 // ConditionalCompareOp __ ccmnw(r1, r24, 9u, Assembler::LS); // ccmn w1, w24, #9, LS __ ccmpw(r14, r10, 4u, Assembler::GT); // ccmp w14, w10, #4, GT __ ccmn(r9, r29, 0u, Assembler::CC); // ccmn x9, x29, #0, CC __ ccmp(r6, r6, 13u, Assembler::MI); // ccmp x6, x6, #13, MI // ConditionalCompareImmedOp __ ccmnw(r19, 11, 5, Assembler::NE); // ccmn w19, #11, #5, NE __ ccmpw(r11, 31, 15, Assembler::GE); // ccmp w11, #31, #15, GE __ ccmn(r12, 14, 5, Assembler::VS); // ccmn x12, #14, #5, VS __ ccmp(r1, 7, 10, Assembler::MI); // ccmp x1, #7, #10, MI // ConditionalSelectOp __ cselw(r6, r2, r22, Assembler::LO); // csel w6, w2, w22, LO __ csincw(r29, r22, r26, Assembler::VS); // csinc w29, w22, w26, VS __ csinvw(r26, r25, r11, Assembler::LS); // csinv w26, w25, w11, LS __ csnegw(r19, r14, r16, Assembler::GT); // csneg w19, w14, w16, GT __ csel(r13, r21, r20, Assembler::CS); // csel x13, x21, x20, CS __ csinc(r12, r11, r27, Assembler::HI); // csinc x12, x11, x27, HI __ csinv(r3, r17, r19, Assembler::LE); // csinv x3, x17, x19, LE __ csneg(r24, r1, r7, Assembler::VS); // csneg x24, x1, x7, VS // TwoRegOp __ rbitw(r23, r1); // rbit w23, w1 __ rev16w(r16, r16); // rev16 w16, w16 __ revw(r24, r25); // rev w24, w25 __ clzw(r25, r8); // clz w25, w8 __ clsw(r27, r12); // cls w27, w12 __ rbit(r21, r5); // rbit x21, x5 __ rev16(r20, r9); // rev16 x20, x9 __ rev32(r20, r9); // rev32 x20, x9 __ rev(r19, r10); // rev x19, x10 __ clz(r8, r2); // clz x8, x2 __ cls(r29, r3); // cls x29, x3 // ThreeRegOp __ udivw(r19, r7, r29); // udiv w19, w7, w29 __ sdivw(r26, r27, r10); // sdiv w26, w27, w10 __ lslvw(r0, r24, r16); // lslv w0, w24, w16 __ lsrvw(r22, r10, r24); // lsrv w22, w10, w24 __ asrvw(r0, r26, r16); // asrv w0, w26, w16 __ rorvw(r27, r25, r15); // rorv w27, w25, w15 __ udiv(r8, r28, r15); // udiv x8, x28, x15 __ sdiv(r20, r11, r5); // sdiv x20, x11, x5 __ lslv(r21, r25, r16); // lslv x21, x25, x16 __ lsrv(r7, r2, r14); // lsrv x7, x2, x14 __ asrv(r21, r8, r22); // asrv x21, x8, x22 __ rorv(r7, r5, r15); // rorv x7, x5, x15 __ umulh(r12, r21, r22); // umulh x12, x21, x22 __ smulh(r16, r10, r5); // smulh x16, x10, x5 // FourRegMulOp __ maddw(r2, r6, r26, r21); // madd w2, w6, w26, w21 __ msubw(r27, r19, r3, r27); // msub w27, w19, w3, w27 __ madd(r27, r5, r8, r3); // madd x27, x5, x8, x3 __ msub(r8, r13, r28, r13); // msub x8, x13, x28, x13 __ smaddl(r29, r9, r8, r0); // smaddl x29, w9, w8, x0 __ smsubl(r14, r9, r14, r23); // smsubl x14, w9, w14, x23 __ umaddl(r15, r4, r11, r13); // umaddl x15, w4, w11, x13 __ umsubl(r23, r3, r17, r24); // umsubl x23, w3, w17, x24 // ThreeRegFloatOp __ fmuls(v29, v1, v17); // fmul s29, s1, s17 __ fdivs(v23, v28, v9); // fdiv s23, s28, s9 __ fadds(v14, v19, v12); // fadd s14, s19, s12 __ fsubs(v27, v17, v0); // fsub s27, s17, s0 __ fmuls(v16, v24, v6); // fmul s16, s24, s6 __ fmuld(v4, v23, v10); // fmul d4, d23, d10 __ fdivd(v11, v9, v23); // fdiv d11, d9, d23 __ faddd(v7, v15, v7); // fadd d7, d15, d7 __ fsubd(v29, v21, v12); // fsub d29, d21, d12 __ fmuld(v27, v4, v9); // fmul d27, d4, d9 // FourRegFloatOp __ fmadds(v27, v14, v11, v25); // fmadd s27, s14, s11, s25 __ fmsubs(v11, v22, v15, v3); // fmsub s11, s22, s15, s3 __ fnmadds(v10, v27, v24, v4); // fnmadd s10, s27, s24, s4 __ fnmadds(v4, v6, v1, v1); // fnmadd s4, s6, s1, s1 __ fmaddd(v13, v28, v3, v2); // fmadd d13, d28, d3, d2 __ fmsubd(v26, v24, v7, v26); // fmsub d26, d24, d7, d26 __ fnmaddd(v21, v5, v12, v26); // fnmadd d21, d5, d12, d26 __ fnmaddd(v11, v16, v20, v3); // fnmadd d11, d16, d20, d3 // TwoRegFloatOp __ fmovs(v5, v17); // fmov s5, s17 __ fabss(v7, v9); // fabs s7, s9 __ fnegs(v25, v1); // fneg s25, s1 __ fsqrts(v24, v6); // fsqrt s24, s6 __ fcvts(v27, v17); // fcvt d27, s17 __ fmovd(v22, v2); // fmov d22, d2 __ fabsd(v14, v20); // fabs d14, d20 __ fnegd(v29, v11); // fneg d29, d11 __ fsqrtd(v28, v12); // fsqrt d28, d12 __ fcvtd(v4, v3); // fcvt s4, d3 // FloatConvertOp __ fcvtzsw(r28, v13); // fcvtzs w28, s13 __ fcvtzs(r7, v28); // fcvtzs x7, s28 __ fcvtzdw(r12, v15); // fcvtzs w12, d15 __ fcvtzd(r11, v6); // fcvtzs x11, d6 __ scvtfws(v22, r22); // scvtf s22, w22 __ scvtfs(v5, r16); // scvtf s5, x16 __ scvtfwd(v3, r15); // scvtf d3, w15 __ scvtfd(v6, r8); // scvtf d6, x8 __ fmovs(r26, v29); // fmov w26, s29 __ fmovd(r24, v17); // fmov x24, d17 __ fmovs(v2, r19); // fmov s2, w19 __ fmovd(v21, r5); // fmov d21, x5 // TwoRegFloatOp __ fcmps(v23, v8); // fcmp s23, s8 __ fcmpd(v12, v2); // fcmp d12, d2 __ fcmps(v14, 0.0); // fcmp s14, #0.0 __ fcmpd(v10, 0.0); // fcmp d10, #0.0 // LoadStorePairOp __ stpw(r8, r17, Address(r12, -96)); // stp w8, w17, [x12, #-96] __ ldpw(r1, r21, Address(r28, -192)); // ldp w1, w21, [x28, #-192] __ ldpsw(r25, r22, Address(r16, -64)); // ldpsw x25, x22, [x16, #-64] __ stp(r6, r8, Address(r23, -128)); // stp x6, x8, [x23, #-128] __ ldp(r25, r16, Address(r19, -112)); // ldp x25, x16, [x19, #-112] // LoadStorePairOp __ stpw(r29, r27, Address(__ pre(r13, -240))); // stp w29, w27, [x13, #-240]! __ ldpw(r12, r20, Address(__ pre(r21, -32))); // ldp w12, w20, [x21, #-32]! __ ldpsw(r0, r15, Address(__ pre(r4, -144))); // ldpsw x0, x15, [x4, #-144]! __ stp(r13, r12, Address(__ pre(r19, 128))); // stp x13, x12, [x19, #128]! __ ldp(r25, r2, Address(__ pre(r9, 96))); // ldp x25, x2, [x9, #96]! // LoadStorePairOp __ stpw(r11, r1, Address(__ post(r26, 128))); // stp w11, w1, [x26], #128 __ ldpw(r26, r25, Address(__ post(r3, 32))); // ldp w26, w25, [x3], #32 __ ldpsw(r10, r14, Address(__ post(r2, -240))); // ldpsw x10, x14, [x2], #-240 __ stp(r1, r3, Address(__ post(r10, 128))); // stp x1, x3, [x10], #128 __ ldp(r23, r12, Address(__ post(r25, -144))); // ldp x23, x12, [x25], #-144 // LoadStorePairOp __ stnpw(r5, r8, Address(r25, 64)); // stnp w5, w8, [x25, #64] __ ldnpw(r20, r19, Address(r22, -240)); // ldnp w20, w19, [x22, #-240] __ stnp(r23, r7, Address(r14, -176)); // stnp x23, x7, [x14, #-176] __ ldnp(r14, r28, Address(r21, 64)); // ldnp x14, x28, [x21, #64] // LdStSIMDOp __ ld1(v10, __ T8B, Address(r4)); // ld1 {v10.8B}, [x4] __ ld1(v25, v26, __ T16B, Address(__ post(r26, 32))); // ld1 {v25.16B, v26.16B}, [x26], 32 __ ld1(v27, v28, v29, __ T1D, Address(__ post(r4, r23))); // ld1 {v27.1D, v28.1D, v29.1D}, [x4], x23 __ ld1(v16, v17, v18, v19, __ T8H, Address(__ post(r6, 64))); // ld1 {v16.8H, v17.8H, v18.8H, v19.8H}, [x6], 64 __ ld1r(v1, __ T8B, Address(r27)); // ld1r {v1.8B}, [x27] __ ld1r(v4, __ T4S, Address(__ post(r2, 4))); // ld1r {v4.4S}, [x2], 4 __ ld1r(v21, __ T1D, Address(__ post(r29, r15))); // ld1r {v21.1D}, [x29], x15 __ ld2(v1, v2, __ T2D, Address(r22)); // ld2 {v1.2D, v2.2D}, [x22] __ ld2(v29, v30, __ T4H, Address(__ post(r8, 16))); // ld2 {v29.4H, v30.4H}, [x8], 16 __ ld2r(v24, v25, __ T16B, Address(r4)); // ld2r {v24.16B, v25.16B}, [x4] __ ld2r(v21, v22, __ T2S, Address(__ post(r19, 8))); // ld2r {v21.2S, v22.2S}, [x19], 8 __ ld2r(v13, v14, __ T2D, Address(__ post(r13, r6))); // ld2r {v13.2D, v14.2D}, [x13], x6 __ ld3(v1, v2, v3, __ T4S, Address(__ post(r4, r17))); // ld3 {v1.4S, v2.4S, v3.4S}, [x4], x17 __ ld3(v22, v23, v24, __ T2S, Address(r17)); // ld3 {v22.2S, v23.2S, v24.2S}, [x17] __ ld3r(v17, v18, v19, __ T8H, Address(r17)); // ld3r {v17.8H, v18.8H, v19.8H}, [x17] __ ld3r(v8, v9, v10, __ T4S, Address(__ post(r28, 12))); // ld3r {v8.4S, v9.4S, v10.4S}, [x28], 12 __ ld3r(v5, v6, v7, __ T1D, Address(__ post(r1, r19))); // ld3r {v5.1D, v6.1D, v7.1D}, [x1], x19 __ ld4(v1, v2, v3, v4, __ T8H, Address(__ post(r15, 64))); // ld4 {v1.8H, v2.8H, v3.8H, v4.8H}, [x15], 64 __ ld4(v17, v18, v19, v20, __ T8B, Address(__ post(r6, r26))); // ld4 {v17.8B, v18.8B, v19.8B, v20.8B}, [x6], x26 __ ld4r(v25, v26, v27, v28, __ T8B, Address(r7)); // ld4r {v25.8B, v26.8B, v27.8B, v28.8B}, [x7] __ ld4r(v12, v13, v14, v15, __ T4H, Address(__ post(r8, 8))); // ld4r {v12.4H, v13.4H, v14.4H, v15.4H}, [x8], 8 __ ld4r(v9, v10, v11, v12, __ T2S, Address(__ post(r13, r1))); // ld4r {v9.2S, v10.2S, v11.2S, v12.2S}, [x13], x1 // SpecialCases __ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE __ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ __ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE __ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT __ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0 __ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp] __ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3] __ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5] __ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp] __ dup(v0, __ T16B, zr); // dup v0.16b, wzr __ mov(v1, __ T1D, 0, zr); // mov v1.d[0], xzr __ mov(v1, __ T2S, 1, zr); // mov v1.s[1], wzr __ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr __ mov(v1, __ T8B, 3, zr); // mov v1.b[3], wzr __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0 // FloatImmediateOp __ fmovd(v0, 2.0); // fmov d0, #2.0 __ fmovd(v0, 2.125); // fmov d0, #2.125 __ fmovd(v0, 4.0); // fmov d0, #4.0 __ fmovd(v0, 4.25); // fmov d0, #4.25 __ fmovd(v0, 8.0); // fmov d0, #8.0 __ fmovd(v0, 8.5); // fmov d0, #8.5 __ fmovd(v0, 16.0); // fmov d0, #16.0 __ fmovd(v0, 17.0); // fmov d0, #17.0 __ fmovd(v0, 0.125); // fmov d0, #0.125 __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125 __ fmovd(v0, 0.25); // fmov d0, #0.25 __ fmovd(v0, 0.265625); // fmov d0, #0.265625 __ fmovd(v0, 0.5); // fmov d0, #0.5 __ fmovd(v0, 0.53125); // fmov d0, #0.53125 __ fmovd(v0, 1.0); // fmov d0, #1.0 __ fmovd(v0, 1.0625); // fmov d0, #1.0625 __ fmovd(v0, -2.0); // fmov d0, #-2.0 __ fmovd(v0, -2.125); // fmov d0, #-2.125 __ fmovd(v0, -4.0); // fmov d0, #-4.0 __ fmovd(v0, -4.25); // fmov d0, #-4.25 __ fmovd(v0, -8.0); // fmov d0, #-8.0 __ fmovd(v0, -8.5); // fmov d0, #-8.5 __ fmovd(v0, -16.0); // fmov d0, #-16.0 __ fmovd(v0, -17.0); // fmov d0, #-17.0 __ fmovd(v0, -0.125); // fmov d0, #-0.125 __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125 __ fmovd(v0, -0.25); // fmov d0, #-0.25 __ fmovd(v0, -0.265625); // fmov d0, #-0.265625 __ fmovd(v0, -0.5); // fmov d0, #-0.5 __ fmovd(v0, -0.53125); // fmov d0, #-0.53125 __ fmovd(v0, -1.0); // fmov d0, #-1.0 __ fmovd(v0, -1.0625); // fmov d0, #-1.0625 // LSEOp __ swp(Assembler::xword, r26, r3, r6); // swp x26, x3, [x6] __ ldadd(Assembler::xword, r20, r12, r4); // ldadd x20, x12, [x4] __ ldbic(Assembler::xword, r23, r4, r11); // ldclr x23, x4, [x11] __ ldeor(Assembler::xword, r15, r15, r24); // ldeor x15, x15, [x24] __ ldorr(Assembler::xword, r29, r2, r17); // ldset x29, x2, [x17] __ ldsmin(Assembler::xword, r25, r5, r1); // ldsmin x25, x5, [x1] __ ldsmax(Assembler::xword, r15, r15, r7); // ldsmax x15, x15, [x7] __ ldumin(Assembler::xword, r28, zr, r29); // ldumin x28, xzr, [x29] __ ldumax(Assembler::xword, r17, r17, sp); // ldumax x17, x17, [sp] // LSEOp __ swpa(Assembler::xword, r7, r16, r21); // swpa x7, x16, [x21] __ ldadda(Assembler::xword, r17, r10, r20); // ldadda x17, x10, [x20] __ ldbica(Assembler::xword, r25, r14, r29); // ldclra x25, x14, [x29] __ ldeora(Assembler::xword, r25, r13, r3); // ldeora x25, x13, [x3] __ ldorra(Assembler::xword, r13, r7, r28); // ldseta x13, x7, [x28] __ ldsmina(Assembler::xword, r20, r25, r7); // ldsmina x20, x25, [x7] __ ldsmaxa(Assembler::xword, r21, r4, r2); // ldsmaxa x21, x4, [x2] __ ldumina(Assembler::xword, r8, r5, r8); // ldumina x8, x5, [x8] __ ldumaxa(Assembler::xword, r10, r12, r6); // ldumaxa x10, x12, [x6] // LSEOp __ swpal(Assembler::xword, r25, r12, r10); // swpal x25, x12, [x10] __ ldaddal(Assembler::xword, r12, r1, r4); // ldaddal x12, x1, [x4] __ ldbical(Assembler::xword, r26, r6, r12); // ldclral x26, x6, [x12] __ ldeoral(Assembler::xword, r1, r14, r12); // ldeoral x1, x14, [x12] __ ldorral(Assembler::xword, r22, r6, r21); // ldsetal x22, x6, [x21] __ ldsminal(Assembler::xword, r15, r4, r6); // ldsminal x15, x4, [x6] __ ldsmaxal(Assembler::xword, r24, r16, r7); // ldsmaxal x24, x16, [x7] __ lduminal(Assembler::xword, r5, r3, r11); // lduminal x5, x3, [x11] __ ldumaxal(Assembler::xword, r22, r2, r25); // ldumaxal x22, x2, [x25] // LSEOp __ swpl(Assembler::xword, r6, r29, r0); // swpl x6, x29, [x0] __ ldaddl(Assembler::xword, r26, r6, r23); // ldaddl x26, x6, [x23] __ ldbicl(Assembler::xword, r4, r7, r9); // ldclrl x4, x7, [x9] __ ldeorl(Assembler::xword, r6, r11, r1); // ldeorl x6, x11, [x1] __ ldorrl(Assembler::xword, r11, r13, r29); // ldsetl x11, x13, [x29] __ ldsminl(Assembler::xword, r11, r3, r6); // ldsminl x11, x3, [x6] __ ldsmaxl(Assembler::xword, r21, r0, r11); // ldsmaxl x21, x0, [x11] __ lduminl(Assembler::xword, r11, r23, r9); // lduminl x11, x23, [x9] __ ldumaxl(Assembler::xword, r17, r16, r16); // ldumaxl x17, x16, [x16] // LSEOp __ swp(Assembler::word, r21, r5, sp); // swp w21, w5, [sp] __ ldadd(Assembler::word, r24, r11, r4); // ldadd w24, w11, [x4] __ ldbic(Assembler::word, r17, r29, r4); // ldclr w17, w29, [x4] __ ldeor(Assembler::word, r15, r11, r15); // ldeor w15, w11, [x15] __ ldorr(Assembler::word, r27, r26, r11); // ldset w27, w26, [x11] __ ldsmin(Assembler::word, r27, r12, r8); // ldsmin w27, w12, [x8] __ ldsmax(Assembler::word, r6, r20, r1); // ldsmax w6, w20, [x1] __ ldumin(Assembler::word, r14, r16, r29); // ldumin w14, w16, [x29] __ ldumax(Assembler::word, r24, r13, r26); // ldumax w24, w13, [x26] // LSEOp __ swpa(Assembler::word, r4, r2, r11); // swpa w4, w2, [x11] __ ldadda(Assembler::word, r20, r29, r4); // ldadda w20, w29, [x4] __ ldbica(Assembler::word, r20, zr, r29); // ldclra w20, wzr, [x29] __ ldeora(Assembler::word, r0, r15, r25); // ldeora w0, w15, [x25] __ ldorra(Assembler::word, r23, r5, r20); // ldseta w23, w5, [x20] __ ldsmina(Assembler::word, r29, r26, r19); // ldsmina w29, w26, [x19] __ ldsmaxa(Assembler::word, r21, r20, r22); // ldsmaxa w21, w20, [x22] __ ldumina(Assembler::word, r26, r21, r16); // ldumina w26, w21, [x16] __ ldumaxa(Assembler::word, r8, r21, r10); // ldumaxa w8, w21, [x10] // LSEOp __ swpal(Assembler::word, r27, r11, r11); // swpal w27, w11, [x11] __ ldaddal(Assembler::word, r5, r8, r28); // ldaddal w5, w8, [x28] __ ldbical(Assembler::word, r0, r5, r5); // ldclral w0, w5, [x5] __ ldeoral(Assembler::word, r2, r10, r24); // ldeoral w2, w10, [x24] __ ldorral(Assembler::word, r13, zr, sp); // ldsetal w13, wzr, [sp] __ ldsminal(Assembler::word, r26, r25, r24); // ldsminal w26, w25, [x24] __ ldsmaxal(Assembler::word, r8, r5, r6); // ldsmaxal w8, w5, [x6] __ lduminal(Assembler::word, r5, r27, r27); // lduminal w5, w27, [x27] __ ldumaxal(Assembler::word, r23, r20, r23); // ldumaxal w23, w20, [x23] // LSEOp __ swpl(Assembler::word, r25, r3, r28); // swpl w25, w3, [x28] __ ldaddl(Assembler::word, r10, r8, r13); // ldaddl w10, w8, [x13] __ ldbicl(Assembler::word, r21, r11, sp); // ldclrl w21, w11, [sp] __ ldeorl(Assembler::word, zr, r3, r28); // ldeorl wzr, w3, [x28] __ ldorrl(Assembler::word, r15, r0, r24); // ldsetl w15, w0, [x24] __ ldsminl(Assembler::word, r4, r9, r29); // ldsminl w4, w9, [x29] __ ldsmaxl(Assembler::word, r8, r6, r21); // ldsmaxl w8, w6, [x21] __ lduminl(Assembler::word, r9, r22, r3); // lduminl w9, w22, [x3] __ ldumaxl(Assembler::word, r26, r10, r28); // ldumaxl w26, w10, [x28] __ bind(forth); /* aarch64ops.o: file format elf64-littleaarch64 Disassembly of section .text: 0000000000000000 : 0: 8b1ad014 add x20, x0, x26, lsl #52 4: cb83db85 sub x5, x28, x3, asr #54 8: ab839ecb adds x11, x22, x3, asr #39 c: eb4c646b subs x11, x3, x12, lsr #25 10: 0b0d399b add w27, w12, w13, lsl #14 14: 4b9b1eaa sub w10, w21, w27, asr #7 18: 2b1011c3 adds w3, w14, w16, lsl #4 1c: 6b1d1661 subs w1, w19, w29, lsl #5 20: 8a5b1a30 and x16, x17, x27, lsr #6 24: aa1c8f96 orr x22, x28, x28, lsl #35 28: ca5ccd4b eor x11, x10, x28, lsr #51 2c: ea8ec10d ands x13, x8, x14, asr #48 30: 0a410c61 and w1, w3, w1, lsr #3 34: 2a855909 orr w9, w8, w5, asr #22 38: 4a9b4f82 eor w2, w28, w27, asr #19 3c: 6a073938 ands w24, w9, w7, lsl #14 40: 8ab9826b bic x11, x19, x25, asr #32 44: aa3d7318 orn x24, x24, x29, lsl #28 48: cab16e0b eon x11, x16, x17, asr #27 4c: ea6ae9a5 bics x5, x13, x10, lsr #58 50: 0a357545 bic w5, w10, w21, lsl #29 54: 2a354d64 orn w4, w11, w21, lsl #19 58: 4a7c3f95 eon w21, w28, w28, lsr #15 5c: 6a2e7146 bics w6, w10, w14, lsl #28 60: 110ec6ca add w10, w22, #0x3b1 64: 310e9d6f adds w15, w11, #0x3a7 68: 510afcc5 sub w5, w6, #0x2bf 6c: 7108e013 subs w19, w0, #0x238 70: 91098114 add x20, x8, #0x260 74: b10434d0 adds x16, x6, #0x10d 78: d10db417 sub x23, x0, #0x36d 7c: f10c873a subs x26, x25, #0x321 80: 120d6a0c and w12, w16, #0xfff83fff 84: 32066b01 orr w1, w24, #0xfc1fffff 88: 52112073 eor w19, w3, #0xff8000 8c: 720a553d ands w29, w9, #0xffc00fff 90: 9263d0ba and x26, x5, #0xffffffffe003ffff 94: b20da1d8 orr x24, x14, #0xff80ff80ff80ff8 98: d26ec404 eor x4, x0, #0xfffffffffffc000f 9c: f26e28dc ands x28, x6, #0x1ffc0000 a0: 14000000 b a0 a4: 17ffffd7 b 0 a8: 140001ee b 860 ac: 94000000 bl ac b0: 97ffffd4 bl 0 b4: 940001eb bl 860 b8: 34000015 cbz w21, b8 bc: 34fffa35 cbz w21, 0 c0: 34003d15 cbz w21, 860 c4: 3500000c cbnz w12, c4 c8: 35fff9cc cbnz w12, 0 cc: 35003cac cbnz w12, 860 d0: b400000e cbz x14, d0 d4: b4fff96e cbz x14, 0 d8: b4003c4e cbz x14, 860 dc: b500001b cbnz x27, dc e0: b5fff91b cbnz x27, 0 e4: b5003bfb cbnz x27, 860 e8: 1000000e adr x14, e8 ec: 10fff8ae adr x14, 0 f0: 10003b8e adr x14, 860 f4: 90000016 adrp x22, 0 f8: 36280000 tbz w0, #5, f8 fc: 362ff820 tbz w0, #5, 0 100: 36283b00 tbz w0, #5, 860 104: 37580003 tbnz w3, #11, 104 108: 375ff7c3 tbnz w3, #11, 0 10c: 37583aa3 tbnz w3, #11, 860 110: 12835753 mov w19, #0xffffe545 // #-6843 114: 52a2da7c mov w28, #0x16d30000 // #382926848 118: 72a9ef0d movk w13, #0x4f78, lsl #16 11c: 92c097e1 mov x1, #0xfffffb40ffffffff // #-5218385264641 120: d28e0a7a mov x26, #0x7053 // #28755 124: f2e2d05b movk x27, #0x1682, lsl #48 128: 93496301 sbfx x1, x24, #9, #16 12c: 33054019 bfxil w25, w0, #5, #12 130: 530f1f70 ubfiz w16, w27, #17, #8 134: 934f71d0 sbfx x16, x14, #15, #14 138: b3403558 bfxil x24, x10, #0, #14 13c: d34259c1 ubfx x1, x14, #2, #21 140: 1381540a extr w10, w0, w1, #21 144: 93d7f75a extr x26, x26, x23, #61 148: 54000000 b.eq 148 14c: 54fff5a0 b.eq 0 150: 54003880 b.eq 860 154: 54000001 b.ne 154 158: 54fff541 b.ne 0 15c: 54003821 b.ne 860 160: 54000002 b.cs 160 164: 54fff4e2 b.cs 0 168: 540037c2 b.cs 860 16c: 54000002 b.cs 16c 170: 54fff482 b.cs 0 174: 54003762 b.cs 860 178: 54000003 b.cc 178 17c: 54fff423 b.cc 0 180: 54003703 b.cc 860 184: 54000003 b.cc 184 188: 54fff3c3 b.cc 0 18c: 540036a3 b.cc 860 190: 54000004 b.mi 190 194: 54fff364 b.mi 0 198: 54003644 b.mi 860 19c: 54000005 b.pl 19c 1a0: 54fff305 b.pl 0 1a4: 540035e5 b.pl 860 1a8: 54000006 b.vs 1a8 1ac: 54fff2a6 b.vs 0 1b0: 54003586 b.vs 860 1b4: 54000007 b.vc 1b4 1b8: 54fff247 b.vc 0 1bc: 54003527 b.vc 860 1c0: 54000008 b.hi 1c0 1c4: 54fff1e8 b.hi 0 1c8: 540034c8 b.hi 860 1cc: 54000009 b.ls 1cc 1d0: 54fff189 b.ls 0 1d4: 54003469 b.ls 860 1d8: 5400000a b.ge 1d8 1dc: 54fff12a b.ge 0 1e0: 5400340a b.ge 860 1e4: 5400000b b.lt 1e4 1e8: 54fff0cb b.lt 0 1ec: 540033ab b.lt 860 1f0: 5400000c b.gt 1f0 1f4: 54fff06c b.gt 0 1f8: 5400334c b.gt 860 1fc: 5400000d b.le 1fc 200: 54fff00d b.le 0 204: 540032ed b.le 860 208: 5400000e b.al 208 20c: 54ffefae b.al 0 210: 5400328e b.al 860 214: 5400000f b.nv 214 218: 54ffef4f b.nv 0 21c: 5400322f b.nv 860 220: d4079461 svc #0x3ca3 224: d4018ee2 hvc #0xc77 228: d408d7c3 smc #0x46be 22c: d4216040 brk #0xb02 230: d44a2f80 hlt #0x517c 234: d503201f nop 238: d69f03e0 eret 23c: d6bf03e0 drps 240: d5033fdf isb 244: d503329f dsb oshst 248: d50339bf dmb ishld 24c: d61f0140 br x10 250: d63f02c0 blr x22 254: c8037cb5 stxr w3, x21, [x5] 258: c81cffa9 stlxr w28, x9, [x29] 25c: c85f7cfc ldxr x28, [x7] 260: c85ffeea ldaxr x10, [x23] 264: c89fff47 stlr x7, [x26] 268: c8dffef0 ldar x16, [x23] 26c: 880b7d87 stxr w11, w7, [x12] 270: 8810ff4d stlxr w16, w13, [x26] 274: 885f7eb9 ldxr w25, [x21] 278: 885ffc8e ldaxr w14, [x4] 27c: 889ffd3a stlr w26, [x9] 280: 88dffee0 ldar w0, [x23] 284: 48087d40 stxrh w8, w0, [x10] 288: 480bfc81 stlxrh w11, w1, [x4] 28c: 485f7f4e ldxrh w14, [x26] 290: 485ffcf3 ldaxrh w19, [x7] 294: 489ffed1 stlrh w17, [x22] 298: 48dffcd4 ldarh w20, [x6] 29c: 08197cc8 stxrb w25, w8, [x6] 2a0: 0805ff2a stlxrb w5, w10, [x25] 2a4: 085f7ec0 ldxrb w0, [x22] 2a8: 085ffc68 ldaxrb w8, [x3] 2ac: 089ffc45 stlrb w5, [x2] 2b0: 08dfff86 ldarb w6, [x28] 2b4: c87f21d1 ldxp x17, x8, [x14] 2b8: c87f8c4e ldaxp x14, x3, [x2] 2bc: c8391271 stxp w25, x17, x4, [x19] 2c0: c82abd10 stlxp w10, x16, x15, [x8] 2c4: 887f2c61 ldxp w1, w11, [x3] 2c8: 887fed80 ldaxp w0, w27, [x12] 2cc: 882457b4 stxp w4, w20, w21, [x29] 2d0: 882097a9 stlxp w0, w9, w5, [x29] 2d4: f811d091 stur x17, [x4,#-227] 2d8: b81df086 stur w6, [x4,#-33] 2dc: 39002e0d strb w13, [x16,#11] 2e0: 781c02d7 sturh w23, [x22,#-64] 2e4: f840d062 ldur x2, [x3,#13] 2e8: b8423285 ldur w5, [x20,#35] 2ec: 385f1142 ldurb w2, [x10,#-15] 2f0: 785f8017 ldurh w23, [x0,#-8] 2f4: 389fd1cf ldursb x15, [x14,#-3] 2f8: 789f4063 ldursh x3, [x3,#-12] 2fc: 78df9319 ldursh w25, [x24,#-7] 300: b89e3011 ldursw x17, [x0,#-29] 304: fc5b1127 ldur d7, [x9,#-79] 308: bc5bc16b ldur s11, [x11,#-68] 30c: fc189050 stur d16, [x2,#-119] 310: bc184399 stur s25, [x28,#-124] 314: f8052e7c str x28, [x19,#82]! 318: b8032da7 str w7, [x13,#50]! 31c: 381e0e62 strb w2, [x19,#-32]! 320: 781c6c38 strh w24, [x1,#-58]! 324: f8571fb7 ldr x23, [x29,#-143]! 328: b8400f6d ldr w13, [x27,#0]! 32c: 385e6d4b ldrb w11, [x10,#-26]! 330: 785cacc3 ldrh w3, [x6,#-54]! 334: 38803d22 ldrsb x2, [x9,#3]! 338: 7881ec9c ldrsh x28, [x4,#30]! 33c: 78de9c11 ldrsh w17, [x0,#-23]! 340: b898bf3d ldrsw x29, [x25,#-117]! 344: fc572d55 ldr d21, [x10,#-142]! 348: bc423e8b ldr s11, [x20,#35]! 34c: fc12ade1 str d1, [x15,#-214]! 350: bc1c9cb3 str s19, [x5,#-55]! 354: f81ec63c str x28, [x17],#-20 358: b81f75a8 str w8, [x13],#-9 35c: 381e970e strb w14, [x24],#-23 360: 781c4482 strh w2, [x4],#-60 364: f8422738 ldr x24, [x25],#34 368: b85e5790 ldr w16, [x28],#-27 36c: 385e56e8 ldrb w8, [x23],#-27 370: 785c6403 ldrh w3, [x0],#-58 374: 389f65ee ldrsb x14, [x15],#-10 378: 7880d42c ldrsh x12, [x1],#13 37c: 78ded429 ldrsh w9, [x1],#-19 380: b89c355d ldrsw x29, [x10],#-61 384: fc5f778d ldr d13, [x28],#-9 388: bc5a8774 ldr s20, [x27],#-88 38c: fc139567 str d7, [x11],#-199 390: bc1c36d4 str s20, [x22],#-61 394: f830c943 str x3, [x10,w16,sxtw] 398: b8357ba1 str w1, [x29,x21,lsl #2] 39c: 3837581a strb w26, [x0,w23,uxtw #0] 3a0: 7835681a strh w26, [x0,x21] 3a4: f8766b23 ldr x3, [x25,x22] 3a8: b8785939 ldr w25, [x9,w24,uxtw #2] 3ac: 386ed80a ldrb w10, [x0,w14,sxtw #0] 3b0: 78747aa2 ldrh w2, [x21,x20,lsl #1] 3b4: 38bcfb73 ldrsb x19, [x27,x28,sxtx #0] 3b8: 78a37901 ldrsh x1, [x8,x3,lsl #1] 3bc: 78f0e9f4 ldrsh w20, [x15,x16,sxtx] 3c0: b8ac78e7 ldrsw x7, [x7,x12,lsl #2] 3c4: fc6dd88f ldr d15, [x4,w13,sxtw #3] 3c8: bc63494e ldr s14, [x10,w3,uxtw] 3cc: fc29faf8 str d24, [x23,x9,sxtx #3] 3d0: bc3a5989 str s9, [x12,w26,uxtw #2] 3d4: f91a530e str x14, [x24,#13472] 3d8: b91ce1c0 str w0, [x14,#7392] 3dc: 39180277 strb w23, [x19,#1536] 3e0: 791c316f strh w15, [x11,#3608] 3e4: f95ab735 ldr x21, [x25,#13672] 3e8: b95810f7 ldr w23, [x7,#6160] 3ec: 395ede17 ldrb w23, [x16,#1975] 3f0: 795e1718 ldrh w24, [x24,#3850] 3f4: 3999352c ldrsb x12, [x9,#1613] 3f8: 799e02a5 ldrsh x5, [x21,#3840] 3fc: 79dc0c0e ldrsh w14, [x0,#3590] 400: b99ef84d ldrsw x13, [x2,#7928] 404: fd5ede6f ldr d15, [x19,#15800] 408: bd5880b7 ldr s23, [x5,#6272] 40c: fd1d90c6 str d6, [x6,#15136] 410: bd182569 str s9, [x11,#6180] 414: 58002267 ldr x7, 860 418: 1800001d ldr w29, 418 41c: f8929000 prfum pldl1keep, [x0,#-215] 420: d8002200 prfm pldl1keep, 860 424: f8a34880 prfm pldl1keep, [x4,w3,uxtw] 428: f99825c0 prfm pldl1keep, [x14,#12360] 42c: 1a0400c7 adc w7, w6, w4 430: 3a05019b adcs w27, w12, w5 434: 5a1a0319 sbc w25, w24, w26 438: 7a1700e5 sbcs w5, w7, w23 43c: 9a010176 adc x22, x11, x1 440: ba1d012d adcs x13, x9, x29 444: da1a01c4 sbc x4, x14, x26 448: fa1803bc sbcs x28, x29, x24 44c: 0b3546b1 add w17, w21, w21, uxtw #1 450: 2b3aad2c adds w12, w9, w26, sxth #3 454: cb2324ae sub x14, x5, w3, uxth #1 458: 6b267351 subs w17, w26, w6, uxtx #4 45c: 8b34acb1 add x17, x5, w20, sxth #3 460: ab39cc30 adds x16, x1, w25, sxtw #3 464: cb3aec39 sub x25, x1, x26, sxtx #3 468: eb37ac33 subs x19, x1, w23, sxth #3 46c: 3a589029 ccmn w1, w24, #0x9, ls 470: 7a4ac1c4 ccmp w14, w10, #0x4, gt 474: ba5d3120 ccmn x9, x29, #0x0, cc 478: fa4640cd ccmp x6, x6, #0xd, mi 47c: 3a4b1a65 ccmn w19, #0xb, #0x5, ne 480: 7a5fa96f ccmp w11, #0x1f, #0xf, ge 484: ba4e6985 ccmn x12, #0xe, #0x5, vs 488: fa47482a ccmp x1, #0x7, #0xa, mi 48c: 1a963046 csel w6, w2, w22, cc 490: 1a9a66dd csinc w29, w22, w26, vs 494: 5a8b933a csinv w26, w25, w11, ls 498: 5a90c5d3 csneg w19, w14, w16, gt 49c: 9a9422ad csel x13, x21, x20, cs 4a0: 9a9b856c csinc x12, x11, x27, hi 4a4: da93d223 csinv x3, x17, x19, le 4a8: da876438 csneg x24, x1, x7, vs 4ac: 5ac00037 rbit w23, w1 4b0: 5ac00610 rev16 w16, w16 4b4: 5ac00b38 rev w24, w25 4b8: 5ac01119 clz w25, w8 4bc: 5ac0159b cls w27, w12 4c0: dac000b5 rbit x21, x5 4c4: dac00534 rev16 x20, x9 4c8: dac00934 rev32 x20, x9 4cc: dac00d53 rev x19, x10 4d0: dac01048 clz x8, x2 4d4: dac0147d cls x29, x3 4d8: 1add08f3 udiv w19, w7, w29 4dc: 1aca0f7a sdiv w26, w27, w10 4e0: 1ad02300 lsl w0, w24, w16 4e4: 1ad82556 lsr w22, w10, w24 4e8: 1ad02b40 asr w0, w26, w16 4ec: 1acf2f3b ror w27, w25, w15 4f0: 9acf0b88 udiv x8, x28, x15 4f4: 9ac50d74 sdiv x20, x11, x5 4f8: 9ad02335 lsl x21, x25, x16 4fc: 9ace2447 lsr x7, x2, x14 500: 9ad62915 asr x21, x8, x22 504: 9acf2ca7 ror x7, x5, x15 508: 9bd67eac umulh x12, x21, x22 50c: 9b457d50 smulh x16, x10, x5 510: 1b1a54c2 madd w2, w6, w26, w21 514: 1b03ee7b msub w27, w19, w3, w27 518: 9b080cbb madd x27, x5, x8, x3 51c: 9b1cb5a8 msub x8, x13, x28, x13 520: 9b28013d smaddl x29, w9, w8, x0 524: 9b2edd2e smsubl x14, w9, w14, x23 528: 9bab348f umaddl x15, w4, w11, x13 52c: 9bb1e077 umsubl x23, w3, w17, x24 530: 1e31083d fmul s29, s1, s17 534: 1e291b97 fdiv s23, s28, s9 538: 1e2c2a6e fadd s14, s19, s12 53c: 1e203a3b fsub s27, s17, s0 540: 1e260b10 fmul s16, s24, s6 544: 1e6a0ae4 fmul d4, d23, d10 548: 1e77192b fdiv d11, d9, d23 54c: 1e6729e7 fadd d7, d15, d7 550: 1e6c3abd fsub d29, d21, d12 554: 1e69089b fmul d27, d4, d9 558: 1f0b65db fmadd s27, s14, s11, s25 55c: 1f0f8ecb fmsub s11, s22, s15, s3 560: 1f38136a fnmadd s10, s27, s24, s4 564: 1f2104c4 fnmadd s4, s6, s1, s1 568: 1f430b8d fmadd d13, d28, d3, d2 56c: 1f47eb1a fmsub d26, d24, d7, d26 570: 1f6c68b5 fnmadd d21, d5, d12, d26 574: 1f740e0b fnmadd d11, d16, d20, d3 578: 1e204225 fmov s5, s17 57c: 1e20c127 fabs s7, s9 580: 1e214039 fneg s25, s1 584: 1e21c0d8 fsqrt s24, s6 588: 1e22c23b fcvt d27, s17 58c: 1e604056 fmov d22, d2 590: 1e60c28e fabs d14, d20 594: 1e61417d fneg d29, d11 598: 1e61c19c fsqrt d28, d12 59c: 1e624064 fcvt s4, d3 5a0: 1e3801bc fcvtzs w28, s13 5a4: 9e380387 fcvtzs x7, s28 5a8: 1e7801ec fcvtzs w12, d15 5ac: 9e7800cb fcvtzs x11, d6 5b0: 1e2202d6 scvtf s22, w22 5b4: 9e220205 scvtf s5, x16 5b8: 1e6201e3 scvtf d3, w15 5bc: 9e620106 scvtf d6, x8 5c0: 1e2603ba fmov w26, s29 5c4: 9e660238 fmov x24, d17 5c8: 1e270262 fmov s2, w19 5cc: 9e6700b5 fmov d21, x5 5d0: 1e2822e0 fcmp s23, s8 5d4: 1e622180 fcmp d12, d2 5d8: 1e2021c8 fcmp s14, #0.0 5dc: 1e602148 fcmp d10, #0.0 5e0: 29344588 stp w8, w17, [x12,#-96] 5e4: 29685781 ldp w1, w21, [x28,#-192] 5e8: 69785a19 ldpsw x25, x22, [x16,#-64] 5ec: a93822e6 stp x6, x8, [x23,#-128] 5f0: a9794279 ldp x25, x16, [x19,#-112] 5f4: 29a26dbd stp w29, w27, [x13,#-240]! 5f8: 29fc52ac ldp w12, w20, [x21,#-32]! 5fc: 69ee3c80 ldpsw x0, x15, [x4,#-144]! 600: a988326d stp x13, x12, [x19,#128]! 604: a9c60939 ldp x25, x2, [x9,#96]! 608: 2890074b stp w11, w1, [x26],#128 60c: 28c4647a ldp w26, w25, [x3],#32 610: 68e2384a ldpsw x10, x14, [x2],#-240 614: a8880d41 stp x1, x3, [x10],#128 618: a8f73337 ldp x23, x12, [x25],#-144 61c: 28082325 stnp w5, w8, [x25,#64] 620: 28624ed4 ldnp w20, w19, [x22,#-240] 624: a8351dd7 stnp x23, x7, [x14,#-176] 628: a84472ae ldnp x14, x28, [x21,#64] 62c: 0c40708a ld1 {v10.8b}, [x4] 630: 4cdfa359 ld1 {v25.16b, v26.16b}, [x26], #32 634: 0cd76c9b ld1 {v27.1d-v29.1d}, [x4], x23 638: 4cdf24d0 ld1 {v16.8h-v19.8h}, [x6], #64 63c: 0d40c361 ld1r {v1.8b}, [x27] 640: 4ddfc844 ld1r {v4.4s}, [x2], #4 644: 0dcfcfb5 ld1r {v21.1d}, [x29], x15 648: 4c408ec1 ld2 {v1.2d, v2.2d}, [x22] 64c: 0cdf851d ld2 {v29.4h, v30.4h}, [x8], #16 650: 4d60c098 ld2r {v24.16b, v25.16b}, [x4] 654: 0dffca75 ld2r {v21.2s, v22.2s}, [x19], #8 658: 4de6cdad ld2r {v13.2d, v14.2d}, [x13], x6 65c: 4cd14881 ld3 {v1.4s-v3.4s}, [x4], x17 660: 0c404a36 ld3 {v22.2s-v24.2s}, [x17] 664: 4d40e631 ld3r {v17.8h-v19.8h}, [x17] 668: 4ddfeb88 ld3r {v8.4s-v10.4s}, [x28], #12 66c: 0dd3ec25 ld3r {v5.1d-v7.1d}, [x1], x19 670: 4cdf05e1 ld4 {v1.8h-v4.8h}, [x15], #64 674: 0cda00d1 ld4 {v17.8b-v20.8b}, [x6], x26 678: 0d60e0f9 ld4r {v25.8b-v28.8b}, [x7] 67c: 0dffe50c ld4r {v12.4h-v15.4h}, [x8], #8 680: 0de1e9a9 ld4r {v9.2s-v12.2s}, [x13], x1 684: ba5fd3e3 ccmn xzr, xzr, #0x3, le 688: 3a5f03e5 ccmn wzr, wzr, #0x5, eq 68c: fa411be4 ccmp xzr, #0x1, #0x4, ne 690: 7a42cbe2 ccmp wzr, #0x2, #0x2, gt 694: 93df03ff ror xzr, xzr, #0 698: c820ffff stlxp w0, xzr, xzr, [sp] 69c: 8822fc7f stlxp w2, wzr, wzr, [x3] 6a0: c8247cbf stxp w4, xzr, xzr, [x5] 6a4: 88267fff stxp w6, wzr, wzr, [sp] 6a8: 4e010fe0 dup v0.16b, wzr 6ac: 4e081fe1 mov v1.d[0], xzr 6b0: 4e0c1fe1 mov v1.s[1], wzr 6b4: 4e0a1fe1 mov v1.h[2], wzr 6b8: 4e071fe1 mov v1.b[3], wzr 6bc: 4cc0ac3f ld1 {v31.2d, v0.2d}, [x1], x0 6c0: 1e601000 fmov d0, #2.000000000000000000e+00 6c4: 1e603000 fmov d0, #2.125000000000000000e+00 6c8: 1e621000 fmov d0, #4.000000000000000000e+00 6cc: 1e623000 fmov d0, #4.250000000000000000e+00 6d0: 1e641000 fmov d0, #8.000000000000000000e+00 6d4: 1e643000 fmov d0, #8.500000000000000000e+00 6d8: 1e661000 fmov d0, #1.600000000000000000e+01 6dc: 1e663000 fmov d0, #1.700000000000000000e+01 6e0: 1e681000 fmov d0, #1.250000000000000000e-01 6e4: 1e683000 fmov d0, #1.328125000000000000e-01 6e8: 1e6a1000 fmov d0, #2.500000000000000000e-01 6ec: 1e6a3000 fmov d0, #2.656250000000000000e-01 6f0: 1e6c1000 fmov d0, #5.000000000000000000e-01 6f4: 1e6c3000 fmov d0, #5.312500000000000000e-01 6f8: 1e6e1000 fmov d0, #1.000000000000000000e+00 6fc: 1e6e3000 fmov d0, #1.062500000000000000e+00 700: 1e701000 fmov d0, #-2.000000000000000000e+00 704: 1e703000 fmov d0, #-2.125000000000000000e+00 708: 1e721000 fmov d0, #-4.000000000000000000e+00 70c: 1e723000 fmov d0, #-4.250000000000000000e+00 710: 1e741000 fmov d0, #-8.000000000000000000e+00 714: 1e743000 fmov d0, #-8.500000000000000000e+00 718: 1e761000 fmov d0, #-1.600000000000000000e+01 71c: 1e763000 fmov d0, #-1.700000000000000000e+01 720: 1e781000 fmov d0, #-1.250000000000000000e-01 724: 1e783000 fmov d0, #-1.328125000000000000e-01 728: 1e7a1000 fmov d0, #-2.500000000000000000e-01 72c: 1e7a3000 fmov d0, #-2.656250000000000000e-01 730: 1e7c1000 fmov d0, #-5.000000000000000000e-01 734: 1e7c3000 fmov d0, #-5.312500000000000000e-01 738: 1e7e1000 fmov d0, #-1.000000000000000000e+00 73c: 1e7e3000 fmov d0, #-1.062500000000000000e+00 740: f83a80c3 swp x26, x3, [x6] 744: f834008c ldadd x20, x12, [x4] 748: f8371164 ldclr x23, x4, [x11] 74c: f82f230f ldeor x15, x15, [x24] 750: f83d3222 ldset x29, x2, [x17] 754: f8395025 ldsmin x25, x5, [x1] 758: f82f40ef ldsmax x15, x15, [x7] 75c: f83c73bf stumin x28, [x29] 760: f83163f1 ldumax x17, x17, [sp] 764: f8a782b0 swpa x7, x16, [x21] 768: f8b1028a ldadda x17, x10, [x20] 76c: f8b913ae ldclra x25, x14, [x29] 770: f8b9206d ldeora x25, x13, [x3] 774: f8ad3387 ldseta x13, x7, [x28] 778: f8b450f9 ldsmina x20, x25, [x7] 77c: f8b54044 ldsmaxa x21, x4, [x2] 780: f8a87105 ldumina x8, x5, [x8] 784: f8aa60cc ldumaxa x10, x12, [x6] 788: f8f9814c swpal x25, x12, [x10] 78c: f8ec0081 ldaddal x12, x1, [x4] 790: f8fa1186 ldclral x26, x6, [x12] 794: f8e1218e ldeoral x1, x14, [x12] 798: f8f632a6 ldsetal x22, x6, [x21] 79c: f8ef50c4 ldsminal x15, x4, [x6] 7a0: f8f840f0 ldsmaxal x24, x16, [x7] 7a4: f8e57163 lduminal x5, x3, [x11] 7a8: f8f66322 ldumaxal x22, x2, [x25] 7ac: f866801d swpl x6, x29, [x0] 7b0: f87a02e6 ldaddl x26, x6, [x23] 7b4: f8641127 ldclrl x4, x7, [x9] 7b8: f866202b ldeorl x6, x11, [x1] 7bc: f86b33ad ldsetl x11, x13, [x29] 7c0: f86b50c3 ldsminl x11, x3, [x6] 7c4: f8754160 ldsmaxl x21, x0, [x11] 7c8: f86b7137 lduminl x11, x23, [x9] 7cc: f8716210 ldumaxl x17, x16, [x16] 7d0: b83583e5 swp w21, w5, [sp] 7d4: b838008b ldadd w24, w11, [x4] 7d8: b831109d ldclr w17, w29, [x4] 7dc: b82f21eb ldeor w15, w11, [x15] 7e0: b83b317a ldset w27, w26, [x11] 7e4: b83b510c ldsmin w27, w12, [x8] 7e8: b8264034 ldsmax w6, w20, [x1] 7ec: b82e73b0 ldumin w14, w16, [x29] 7f0: b838634d ldumax w24, w13, [x26] 7f4: b8a48162 swpa w4, w2, [x11] 7f8: b8b4009d ldadda w20, w29, [x4] 7fc: b8b413bf ldclra w20, wzr, [x29] 800: b8a0232f ldeora w0, w15, [x25] 804: b8b73285 ldseta w23, w5, [x20] 808: b8bd527a ldsmina w29, w26, [x19] 80c: b8b542d4 ldsmaxa w21, w20, [x22] 810: b8ba7215 ldumina w26, w21, [x16] 814: b8a86155 ldumaxa w8, w21, [x10] 818: b8fb816b swpal w27, w11, [x11] 81c: b8e50388 ldaddal w5, w8, [x28] 820: b8e010a5 ldclral w0, w5, [x5] 824: b8e2230a ldeoral w2, w10, [x24] 828: b8ed33ff ldsetal w13, wzr, [sp] 82c: b8fa5319 ldsminal w26, w25, [x24] 830: b8e840c5 ldsmaxal w8, w5, [x6] 834: b8e5737b lduminal w5, w27, [x27] 838: b8f762f4 ldumaxal w23, w20, [x23] 83c: b8798383 swpl w25, w3, [x28] 840: b86a01a8 ldaddl w10, w8, [x13] 844: b87513eb ldclrl w21, w11, [sp] 848: b87f2383 ldeorl wzr, w3, [x28] 84c: b86f3300 ldsetl w15, w0, [x24] 850: b86453a9 ldsminl w4, w9, [x29] 854: b86842a6 ldsmaxl w8, w6, [x21] 858: b8697076 lduminl w9, w22, [x3] 85c: b87a638a ldumaxl w26, w10, [x28] */ static const unsigned int insns[] = { 0x8b1ad014, 0xcb83db85, 0xab839ecb, 0xeb4c646b, 0x0b0d399b, 0x4b9b1eaa, 0x2b1011c3, 0x6b1d1661, 0x8a5b1a30, 0xaa1c8f96, 0xca5ccd4b, 0xea8ec10d, 0x0a410c61, 0x2a855909, 0x4a9b4f82, 0x6a073938, 0x8ab9826b, 0xaa3d7318, 0xcab16e0b, 0xea6ae9a5, 0x0a357545, 0x2a354d64, 0x4a7c3f95, 0x6a2e7146, 0x110ec6ca, 0x310e9d6f, 0x510afcc5, 0x7108e013, 0x91098114, 0xb10434d0, 0xd10db417, 0xf10c873a, 0x120d6a0c, 0x32066b01, 0x52112073, 0x720a553d, 0x9263d0ba, 0xb20da1d8, 0xd26ec404, 0xf26e28dc, 0x14000000, 0x17ffffd7, 0x140001ee, 0x94000000, 0x97ffffd4, 0x940001eb, 0x34000015, 0x34fffa35, 0x34003d15, 0x3500000c, 0x35fff9cc, 0x35003cac, 0xb400000e, 0xb4fff96e, 0xb4003c4e, 0xb500001b, 0xb5fff91b, 0xb5003bfb, 0x1000000e, 0x10fff8ae, 0x10003b8e, 0x90000016, 0x36280000, 0x362ff820, 0x36283b00, 0x37580003, 0x375ff7c3, 0x37583aa3, 0x12835753, 0x52a2da7c, 0x72a9ef0d, 0x92c097e1, 0xd28e0a7a, 0xf2e2d05b, 0x93496301, 0x33054019, 0x530f1f70, 0x934f71d0, 0xb3403558, 0xd34259c1, 0x1381540a, 0x93d7f75a, 0x54000000, 0x54fff5a0, 0x54003880, 0x54000001, 0x54fff541, 0x54003821, 0x54000002, 0x54fff4e2, 0x540037c2, 0x54000002, 0x54fff482, 0x54003762, 0x54000003, 0x54fff423, 0x54003703, 0x54000003, 0x54fff3c3, 0x540036a3, 0x54000004, 0x54fff364, 0x54003644, 0x54000005, 0x54fff305, 0x540035e5, 0x54000006, 0x54fff2a6, 0x54003586, 0x54000007, 0x54fff247, 0x54003527, 0x54000008, 0x54fff1e8, 0x540034c8, 0x54000009, 0x54fff189, 0x54003469, 0x5400000a, 0x54fff12a, 0x5400340a, 0x5400000b, 0x54fff0cb, 0x540033ab, 0x5400000c, 0x54fff06c, 0x5400334c, 0x5400000d, 0x54fff00d, 0x540032ed, 0x5400000e, 0x54ffefae, 0x5400328e, 0x5400000f, 0x54ffef4f, 0x5400322f, 0xd4079461, 0xd4018ee2, 0xd408d7c3, 0xd4216040, 0xd44a2f80, 0xd503201f, 0xd69f03e0, 0xd6bf03e0, 0xd5033fdf, 0xd503329f, 0xd50339bf, 0xd61f0140, 0xd63f02c0, 0xc8037cb5, 0xc81cffa9, 0xc85f7cfc, 0xc85ffeea, 0xc89fff47, 0xc8dffef0, 0x880b7d87, 0x8810ff4d, 0x885f7eb9, 0x885ffc8e, 0x889ffd3a, 0x88dffee0, 0x48087d40, 0x480bfc81, 0x485f7f4e, 0x485ffcf3, 0x489ffed1, 0x48dffcd4, 0x08197cc8, 0x0805ff2a, 0x085f7ec0, 0x085ffc68, 0x089ffc45, 0x08dfff86, 0xc87f21d1, 0xc87f8c4e, 0xc8391271, 0xc82abd10, 0x887f2c61, 0x887fed80, 0x882457b4, 0x882097a9, 0xf811d091, 0xb81df086, 0x39002e0d, 0x781c02d7, 0xf840d062, 0xb8423285, 0x385f1142, 0x785f8017, 0x389fd1cf, 0x789f4063, 0x78df9319, 0xb89e3011, 0xfc5b1127, 0xbc5bc16b, 0xfc189050, 0xbc184399, 0xf8052e7c, 0xb8032da7, 0x381e0e62, 0x781c6c38, 0xf8571fb7, 0xb8400f6d, 0x385e6d4b, 0x785cacc3, 0x38803d22, 0x7881ec9c, 0x78de9c11, 0xb898bf3d, 0xfc572d55, 0xbc423e8b, 0xfc12ade1, 0xbc1c9cb3, 0xf81ec63c, 0xb81f75a8, 0x381e970e, 0x781c4482, 0xf8422738, 0xb85e5790, 0x385e56e8, 0x785c6403, 0x389f65ee, 0x7880d42c, 0x78ded429, 0xb89c355d, 0xfc5f778d, 0xbc5a8774, 0xfc139567, 0xbc1c36d4, 0xf830c943, 0xb8357ba1, 0x3837581a, 0x7835681a, 0xf8766b23, 0xb8785939, 0x386ed80a, 0x78747aa2, 0x38bcfb73, 0x78a37901, 0x78f0e9f4, 0xb8ac78e7, 0xfc6dd88f, 0xbc63494e, 0xfc29faf8, 0xbc3a5989, 0xf91a530e, 0xb91ce1c0, 0x39180277, 0x791c316f, 0xf95ab735, 0xb95810f7, 0x395ede17, 0x795e1718, 0x3999352c, 0x799e02a5, 0x79dc0c0e, 0xb99ef84d, 0xfd5ede6f, 0xbd5880b7, 0xfd1d90c6, 0xbd182569, 0x58002267, 0x1800001d, 0xf8929000, 0xd8002200, 0xf8a34880, 0xf99825c0, 0x1a0400c7, 0x3a05019b, 0x5a1a0319, 0x7a1700e5, 0x9a010176, 0xba1d012d, 0xda1a01c4, 0xfa1803bc, 0x0b3546b1, 0x2b3aad2c, 0xcb2324ae, 0x6b267351, 0x8b34acb1, 0xab39cc30, 0xcb3aec39, 0xeb37ac33, 0x3a589029, 0x7a4ac1c4, 0xba5d3120, 0xfa4640cd, 0x3a4b1a65, 0x7a5fa96f, 0xba4e6985, 0xfa47482a, 0x1a963046, 0x1a9a66dd, 0x5a8b933a, 0x5a90c5d3, 0x9a9422ad, 0x9a9b856c, 0xda93d223, 0xda876438, 0x5ac00037, 0x5ac00610, 0x5ac00b38, 0x5ac01119, 0x5ac0159b, 0xdac000b5, 0xdac00534, 0xdac00934, 0xdac00d53, 0xdac01048, 0xdac0147d, 0x1add08f3, 0x1aca0f7a, 0x1ad02300, 0x1ad82556, 0x1ad02b40, 0x1acf2f3b, 0x9acf0b88, 0x9ac50d74, 0x9ad02335, 0x9ace2447, 0x9ad62915, 0x9acf2ca7, 0x9bd67eac, 0x9b457d50, 0x1b1a54c2, 0x1b03ee7b, 0x9b080cbb, 0x9b1cb5a8, 0x9b28013d, 0x9b2edd2e, 0x9bab348f, 0x9bb1e077, 0x1e31083d, 0x1e291b97, 0x1e2c2a6e, 0x1e203a3b, 0x1e260b10, 0x1e6a0ae4, 0x1e77192b, 0x1e6729e7, 0x1e6c3abd, 0x1e69089b, 0x1f0b65db, 0x1f0f8ecb, 0x1f38136a, 0x1f2104c4, 0x1f430b8d, 0x1f47eb1a, 0x1f6c68b5, 0x1f740e0b, 0x1e204225, 0x1e20c127, 0x1e214039, 0x1e21c0d8, 0x1e22c23b, 0x1e604056, 0x1e60c28e, 0x1e61417d, 0x1e61c19c, 0x1e624064, 0x1e3801bc, 0x9e380387, 0x1e7801ec, 0x9e7800cb, 0x1e2202d6, 0x9e220205, 0x1e6201e3, 0x9e620106, 0x1e2603ba, 0x9e660238, 0x1e270262, 0x9e6700b5, 0x1e2822e0, 0x1e622180, 0x1e2021c8, 0x1e602148, 0x29344588, 0x29685781, 0x69785a19, 0xa93822e6, 0xa9794279, 0x29a26dbd, 0x29fc52ac, 0x69ee3c80, 0xa988326d, 0xa9c60939, 0x2890074b, 0x28c4647a, 0x68e2384a, 0xa8880d41, 0xa8f73337, 0x28082325, 0x28624ed4, 0xa8351dd7, 0xa84472ae, 0x0c40708a, 0x4cdfa359, 0x0cd76c9b, 0x4cdf24d0, 0x0d40c361, 0x4ddfc844, 0x0dcfcfb5, 0x4c408ec1, 0x0cdf851d, 0x4d60c098, 0x0dffca75, 0x4de6cdad, 0x4cd14881, 0x0c404a36, 0x4d40e631, 0x4ddfeb88, 0x0dd3ec25, 0x4cdf05e1, 0x0cda00d1, 0x0d60e0f9, 0x0dffe50c, 0x0de1e9a9, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4, 0x7a42cbe2, 0x93df03ff, 0xc820ffff, 0x8822fc7f, 0xc8247cbf, 0x88267fff, 0x4e010fe0, 0x4e081fe1, 0x4e0c1fe1, 0x4e0a1fe1, 0x4e071fe1, 0x4cc0ac3f, 0x1e601000, 0x1e603000, 0x1e621000, 0x1e623000, 0x1e641000, 0x1e643000, 0x1e661000, 0x1e663000, 0x1e681000, 0x1e683000, 0x1e6a1000, 0x1e6a3000, 0x1e6c1000, 0x1e6c3000, 0x1e6e1000, 0x1e6e3000, 0x1e701000, 0x1e703000, 0x1e721000, 0x1e723000, 0x1e741000, 0x1e743000, 0x1e761000, 0x1e763000, 0x1e781000, 0x1e783000, 0x1e7a1000, 0x1e7a3000, 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, 0x1e7e3000, 0xf83a80c3, 0xf834008c, 0xf8371164, 0xf82f230f, 0xf83d3222, 0xf8395025, 0xf82f40ef, 0xf83c73bf, 0xf83163f1, 0xf8a782b0, 0xf8b1028a, 0xf8b913ae, 0xf8b9206d, 0xf8ad3387, 0xf8b450f9, 0xf8b54044, 0xf8a87105, 0xf8aa60cc, 0xf8f9814c, 0xf8ec0081, 0xf8fa1186, 0xf8e1218e, 0xf8f632a6, 0xf8ef50c4, 0xf8f840f0, 0xf8e57163, 0xf8f66322, 0xf866801d, 0xf87a02e6, 0xf8641127, 0xf866202b, 0xf86b33ad, 0xf86b50c3, 0xf8754160, 0xf86b7137, 0xf8716210, 0xb83583e5, 0xb838008b, 0xb831109d, 0xb82f21eb, 0xb83b317a, 0xb83b510c, 0xb8264034, 0xb82e73b0, 0xb838634d, 0xb8a48162, 0xb8b4009d, 0xb8b413bf, 0xb8a0232f, 0xb8b73285, 0xb8bd527a, 0xb8b542d4, 0xb8ba7215, 0xb8a86155, 0xb8fb816b, 0xb8e50388, 0xb8e010a5, 0xb8e2230a, 0xb8ed33ff, 0xb8fa5319, 0xb8e840c5, 0xb8e5737b, 0xb8f762f4, 0xb8798383, 0xb86a01a8, 0xb87513eb, 0xb87f2383, 0xb86f3300, 0xb86453a9, 0xb86842a6, 0xb8697076, 0xb87a638a, }; // END Generated code -- do not edit asm_check((unsigned int *)entry, insns, sizeof insns / sizeof insns[0]); { address PC = __ pc(); __ ld1(v0, __ T16B, Address(r16)); // No offset __ ld1(v0, __ T8H, __ post(r16, 16)); // Post-index __ ld2(v0, v1, __ T8H, __ post(r24, 16 * 2)); // Post-index __ ld1(v0, __ T16B, __ post(r16, r17)); // Register post-index static const unsigned int vector_insns[] = { 0x4c407200, // ld1 {v0.16b}, [x16] 0x4cdf7600, // ld1 {v0.8h}, [x16], #16 0x4cdf8700, // ld2 {v0.8h, v1.8h}, [x24], #32 0x4cd17200, // ld1 {v0.16b}, [x16], x17 }; asm_check((unsigned int *)PC, vector_insns, sizeof vector_insns / sizeof vector_insns[0]); } } #endif // ASSERT #undef __ void Assembler::emit_data64(jlong data, relocInfo::relocType rtype, int format) { if (rtype == relocInfo::none) { emit_int64(data); } else { emit_data64(data, Relocation::spec_simple(rtype), format); } } void Assembler::emit_data64(jlong data, RelocationHolder const& rspec, int format) { assert(inst_mark() != NULL, "must be inside InstructionMark"); // Do not use AbstractAssembler::relocate, which is not intended for // embedded words. Instead, relocate to the enclosing instruction. code_section()->relocate(inst_mark(), rspec, format); emit_int64(data); } extern "C" { void das(uint64_t start, int len) { ResourceMark rm; len <<= 2; if (len < 0) Disassembler::decode((address)start + len, (address)start); else Disassembler::decode((address)start, (address)start + len); } JNIEXPORT void das1(uintptr_t insn) { das(insn, 1); } } #define gas_assert(ARG1) assert(ARG1, #ARG1) #define __ as-> void Address::lea(MacroAssembler *as, Register r) const { Relocation* reloc = _rspec.reloc(); relocInfo::relocType rtype = (relocInfo::relocType) reloc->type(); switch(_mode) { case base_plus_offset: { if (_offset == 0 && _base == r) // it's a nop break; if (_offset > 0) __ add(r, _base, _offset); else __ sub(r, _base, -_offset); break; } case base_plus_offset_reg: { __ add(r, _base, _index, _ext.op(), MAX2(_ext.shift(), 0)); break; } case literal: { if (rtype == relocInfo::none) __ mov(r, target()); else __ movptr(r, (uint64_t)target()); break; } default: ShouldNotReachHere(); } } void Assembler::adrp(Register reg1, const Address &dest, uintptr_t &byte_offset) { ShouldNotReachHere(); } #undef __ #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use) void Assembler::adr(Register Rd, address adr) { intptr_t offset = adr - pc(); int offset_lo = offset & 3; offset >>= 2; starti; f(0, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5); rf(Rd, 0); } void Assembler::_adrp(Register Rd, address adr) { uint64_t pc_page = (uint64_t)pc() >> 12; uint64_t adr_page = (uint64_t)adr >> 12; intptr_t offset = adr_page - pc_page; int offset_lo = offset & 3; offset >>= 2; starti; f(1, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5); rf(Rd, 0); } #undef starti Address::Address(address target, relocInfo::relocType rtype) : _mode(literal){ _is_lval = false; _target = target; switch (rtype) { case relocInfo::oop_type: case relocInfo::metadata_type: // Oops are a special case. Normally they would be their own section // but in cases like icBuffer they are literals in the code stream that // we don't have a section for. We use none so that we get a literal address // which is always patchable. break; case relocInfo::external_word_type: _rspec = external_word_Relocation::spec(target); break; case relocInfo::internal_word_type: _rspec = internal_word_Relocation::spec(target); break; case relocInfo::opt_virtual_call_type: _rspec = opt_virtual_call_Relocation::spec(); break; case relocInfo::static_call_type: _rspec = static_call_Relocation::spec(); break; case relocInfo::runtime_call_type: _rspec = runtime_call_Relocation::spec(); break; case relocInfo::poll_type: case relocInfo::poll_return_type: _rspec = Relocation::spec_simple(rtype); break; case relocInfo::none: _rspec = RelocationHolder::none; break; default: ShouldNotReachHere(); break; } } void Assembler::b(const Address &dest) { code_section()->relocate(pc(), dest.rspec()); b(dest.target()); } void Assembler::bl(const Address &dest) { code_section()->relocate(pc(), dest.rspec()); bl(dest.target()); } void Assembler::adr(Register r, const Address &dest) { code_section()->relocate(pc(), dest.rspec()); adr(r, dest.target()); } void Assembler::br(Condition cc, Label &L) { if (L.is_bound()) { br(cc, target(L)); } else { L.add_patch_at(code(), locator()); br(cc, pc()); } } void Assembler::wrap_label(Label &L, Assembler::uncond_branch_insn insn) { if (L.is_bound()) { (this->*insn)(target(L)); } else { L.add_patch_at(code(), locator()); (this->*insn)(pc()); } } void Assembler::wrap_label(Register r, Label &L, compare_and_branch_insn insn) { if (L.is_bound()) { (this->*insn)(r, target(L)); } else { L.add_patch_at(code(), locator()); (this->*insn)(r, pc()); } } void Assembler::wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn) { if (L.is_bound()) { (this->*insn)(r, bitpos, target(L)); } else { L.add_patch_at(code(), locator()); (this->*insn)(r, bitpos, pc()); } } void Assembler::wrap_label(Label &L, prfop op, prefetch_insn insn) { if (L.is_bound()) { (this->*insn)(target(L), op); } else { L.add_patch_at(code(), locator()); (this->*insn)(pc(), op); } } // An "all-purpose" add/subtract immediate, per ARM documentation: // A "programmer-friendly" assembler may accept a negative immediate // between -(2^24 -1) and -1 inclusive, causing it to convert a // requested ADD operation to a SUB, or vice versa, and then encode // the absolute value of the immediate as for uimm24. void Assembler::add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op, int negated_op) { bool sets_flags = op & 1; // this op sets flags union { unsigned u; int imm; }; u = uimm; bool shift = false; bool neg = imm < 0; if (neg) { imm = -imm; op = negated_op; } assert(Rd != sp || imm % 16 == 0, "misaligned stack"); if (imm >= (1 << 11) && ((imm >> 12) << 12 == imm)) { imm >>= 12; shift = true; } f(op, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); // add/subtract immediate ops with the S bit set treat r31 as zr; // with S unset they use sp. if (sets_flags) zrf(Rd, 0); else srf(Rd, 0); srf(Rn, 5); } bool Assembler::operand_valid_for_add_sub_immediate(int64_t imm) { bool shift = false; uint64_t uimm = (uint64_t)uabs(imm); if (uimm < (1 << 12)) return true; if (uimm < (1 << 24) && ((uimm >> 12) << 12 == uimm)) { return true; } return false; } bool Assembler::operand_valid_for_logical_immediate(bool is32, uint64_t imm) { return encode_logical_immediate(is32, imm) != 0xffffffff; } static uint64_t doubleTo64Bits(jdouble d) { union { jdouble double_value; uint64_t double_bits; }; double_value = d; return double_bits; } bool Assembler::operand_valid_for_float_immediate(double imm) { // If imm is all zero bits we can use ZR as the source of a // floating-point value. if (doubleTo64Bits(imm) == 0) return true; // Otherwise try to encode imm then convert the encoded value back // and make sure it's the exact same bit pattern. unsigned result = encoding_for_fp_immediate(imm); return doubleTo64Bits(imm) == fp_immediate_for_encoding(result, true); } int AbstractAssembler::code_fill_byte() { return 0; } // n.b. this is implemented in subclass MacroAssembler void Assembler::bang_stack_with_offset(int offset) { Unimplemented(); } // and now the routines called by the assembler which encapsulate the // above encode and decode functions uint32_t asm_util::encode_logical_immediate(bool is32, uint64_t imm) { if (is32) { /* Allow all zeros or all ones in top 32-bits, so that constant expressions like ~1 are permitted. */ if (imm >> 32 != 0 && imm >> 32 != 0xffffffff) return 0xffffffff; /* Replicate the 32 lower bits to the 32 upper bits. */ imm &= 0xffffffff; imm |= imm << 32; } return encoding_for_logical_immediate(imm); } unsigned Assembler::pack(double value) { float val = (float)value; unsigned result = encoding_for_fp_immediate(val); guarantee(unpack(result) == value, "Invalid floating-point immediate operand"); return result; } // Packed operands for Floating-point Move (immediate) static float unpack(unsigned value) { union { unsigned ival; float val; }; ival = fp_immediate_for_encoding(value, 0); return val; } address Assembler::locate_next_instruction(address inst) { return inst + Assembler::instruction_size; }