1 /*
   2  * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2020 Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  */
  24 
  25 #include <stdio.h>
  26 #include <sys/types.h>
  27 
  28 #include "precompiled.hpp"
  29 #include "asm/assembler.hpp"
  30 #include "asm/assembler.inline.hpp"
  31 #include "interpreter/interpreter.hpp"
  32 
  33 #ifndef PRODUCT
  34 const uintptr_t Assembler::asm_bp = 0x00007fffee09ac88;
  35 #endif
  36 
  37 #include "compiler/disassembler.hpp"
  38 #include "memory/resourceArea.hpp"
  39 #include "runtime/interfaceSupport.inline.hpp"
  40 #include "runtime/sharedRuntime.hpp"
  41 #include "immediate_aarch64.hpp"
  42 
  43 extern "C" void entry(CodeBuffer *cb);
  44 
  45 #define __ _masm.
  46 #ifdef PRODUCT
  47 #define BLOCK_COMMENT(str) /* nothing */
  48 #else
  49 #define BLOCK_COMMENT(str) block_comment(str)
  50 #endif
  51 
  52 #define BIND(label) bind(label); __ BLOCK_COMMENT(#label ":")
  53 
  54 static float unpack(unsigned value);
  55 
  56 short Assembler::SIMD_Size_in_bytes[] = {
  57   // T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
  58        8,   16,   8,  16,   8,  16,   8,  16,  16
  59 };
  60 
  61 #ifdef ASSERT
  62 static void asm_check(const unsigned int *insns, const unsigned int *insns1, size_t len) {
  63     bool ok = true;
  64     for (unsigned int i = 0; i < len; i++) {
  65       if (insns[i] != insns1[i]) {
  66         ok = false;
  67         printf("Ours:\n");
  68         Disassembler::decode((address)&insns1[i], (address)&insns1[i+1]);
  69         printf("Theirs:\n");
  70         Disassembler::decode((address)&insns[i], (address)&insns[i+1]);
  71         printf("\n");
  72       }
  73     }
  74     assert(ok, "Assembler smoke test failed");
  75   }
  76 
  77 void entry(CodeBuffer *cb) {
  78 
  79   // {
  80   //   for (int i = 0; i < 256; i+=16)
  81   //     {
  82   //    printf("\"%20.20g\", ", unpack(i));
  83   //    printf("\"%20.20g\", ", unpack(i+1));
  84   //     }
  85   //   printf("\n");
  86   // }
  87 
  88   Assembler _masm(cb);
  89   address entry = __ pc();
  90 
  91   // Smoke test for assembler
  92 
  93 // BEGIN  Generated code -- do not edit
  94 // Generated by aarch64-asmtest.py
  95     Label back, forth;
  96     __ bind(back);
  97 
  98 // ArithOp
  99     __ add(r20, r0, r26, Assembler::LSL, 52);          //       add     x20, x0, x26, LSL #52
 100     __ sub(r5, r28, r3, Assembler::ASR, 54);           //       sub     x5, x28, x3, ASR #54
 101     __ adds(r11, r22, r3, Assembler::ASR, 39);         //       adds    x11, x22, x3, ASR #39
 102     __ subs(r11, r3, r12, Assembler::LSR, 25);         //       subs    x11, x3, x12, LSR #25
 103     __ addw(r27, r12, r13, Assembler::LSL, 14);        //       add     w27, w12, w13, LSL #14
 104     __ subw(r10, r21, r27, Assembler::ASR, 7);         //       sub     w10, w21, w27, ASR #7
 105     __ addsw(r3, r14, r16, Assembler::LSL, 4);         //       adds    w3, w14, w16, LSL #4
 106     __ subsw(r1, r19, r29, Assembler::LSL, 5);         //       subs    w1, w19, w29, LSL #5
 107     __ andr(r16, r17, r27, Assembler::LSR, 6);         //       and     x16, x17, x27, LSR #6
 108     __ orr(r22, r28, r28, Assembler::LSL, 35);         //       orr     x22, x28, x28, LSL #35
 109     __ eor(r11, r10, r28, Assembler::LSR, 51);         //       eor     x11, x10, x28, LSR #51
 110     __ ands(r13, r8, r14, Assembler::ASR, 48);         //       ands    x13, x8, x14, ASR #48
 111     __ andw(r1, r3, r1, Assembler::LSR, 3);            //       and     w1, w3, w1, LSR #3
 112     __ orrw(r9, r8, r5, Assembler::ASR, 22);           //       orr     w9, w8, w5, ASR #22
 113     __ eorw(r2, r28, r27, Assembler::ASR, 19);         //       eor     w2, w28, w27, ASR #19
 114     __ andsw(r24, r9, r7, Assembler::LSL, 14);         //       ands    w24, w9, w7, LSL #14
 115     __ bic(r11, r19, r25, Assembler::ASR, 32);         //       bic     x11, x19, x25, ASR #32
 116     __ orn(r24, r24, r29, Assembler::LSL, 28);         //       orn     x24, x24, x29, LSL #28
 117     __ eon(r11, r16, r17, Assembler::ASR, 27);         //       eon     x11, x16, x17, ASR #27
 118     __ bics(r5, r13, r10, Assembler::LSR, 58);         //       bics    x5, x13, x10, LSR #58
 119     __ bicw(r5, r10, r21, Assembler::LSL, 29);         //       bic     w5, w10, w21, LSL #29
 120     __ ornw(r4, r11, r21, Assembler::LSL, 19);         //       orn     w4, w11, w21, LSL #19
 121     __ eonw(r21, r28, r28, Assembler::LSR, 15);        //       eon     w21, w28, w28, LSR #15
 122     __ bicsw(r6, r10, r14, Assembler::LSL, 28);        //       bics    w6, w10, w14, LSL #28
 123 
 124 // AddSubImmOp
 125     __ addw(r10, r22, 945u);                           //       add     w10, w22, #945
 126     __ addsw(r15, r11, 935u);                          //       adds    w15, w11, #935
 127     __ subw(r5, r6, 703u);                             //       sub     w5, w6, #703
 128     __ subsw(r19, r0, 568u);                           //       subs    w19, w0, #568
 129     __ add(r20, r8, 608u);                             //       add     x20, x8, #608
 130     __ adds(r16, r6, 269u);                            //       adds    x16, x6, #269
 131     __ sub(r23, r0, 877u);                             //       sub     x23, x0, #877
 132     __ subs(r26, r25, 801u);                           //       subs    x26, x25, #801
 133 
 134 // LogicalImmOp
 135     __ andw(r12, r16, 4294459391ull);                  //       and     w12, w16, #0xfff83fff
 136     __ orrw(r1, r24, 4229955583ull);                   //       orr     w1, w24, #0xfc1fffff
 137     __ eorw(r19, r3, 16744448ull);                     //       eor     w19, w3, #0xff8000
 138     __ andsw(r29, r9, 4290777087ull);                  //       ands    w29, w9, #0xffc00fff
 139     __ andr(r26, r5, 18446744073172942847ull);         //       and     x26, x5, #0xffffffffe003ffff
 140     __ orr(r24, r14, 1150687262887383032ull);          //       orr     x24, x14, #0xff80ff80ff80ff8
 141     __ eor(r4, r0, 18446744073709289487ull);           //       eor     x4, x0, #0xfffffffffffc000f
 142     __ ands(r28, r6, 536608768ull);                    //       ands    x28, x6, #0x1ffc0000
 143 
 144 // AbsOp
 145     __ b(__ pc());                                     //       b       .
 146     __ b(back);                                        //       b       back
 147     __ b(forth);                                       //       b       forth
 148     __ bl(__ pc());                                    //       bl      .
 149     __ bl(back);                                       //       bl      back
 150     __ bl(forth);                                      //       bl      forth
 151 
 152 // RegAndAbsOp
 153     __ cbzw(r21, __ pc());                             //       cbz     w21, .
 154     __ cbzw(r21, back);                                //       cbz     w21, back
 155     __ cbzw(r21, forth);                               //       cbz     w21, forth
 156     __ cbnzw(r12, __ pc());                            //       cbnz    w12, .
 157     __ cbnzw(r12, back);                               //       cbnz    w12, back
 158     __ cbnzw(r12, forth);                              //       cbnz    w12, forth
 159     __ cbz(r14, __ pc());                              //       cbz     x14, .
 160     __ cbz(r14, back);                                 //       cbz     x14, back
 161     __ cbz(r14, forth);                                //       cbz     x14, forth
 162     __ cbnz(r27, __ pc());                             //       cbnz    x27, .
 163     __ cbnz(r27, back);                                //       cbnz    x27, back
 164     __ cbnz(r27, forth);                               //       cbnz    x27, forth
 165     __ adr(r14, __ pc());                              //       adr     x14, .
 166     __ adr(r14, back);                                 //       adr     x14, back
 167     __ adr(r14, forth);                                //       adr     x14, forth
 168     __ _adrp(r22, __ pc());                            //       adrp    x22, .
 169 
 170 // RegImmAbsOp
 171     __ tbz(r0, 5, __ pc());                            //       tbz     x0, #5, .
 172     __ tbz(r0, 5, back);                               //       tbz     x0, #5, back
 173     __ tbz(r0, 5, forth);                              //       tbz     x0, #5, forth
 174     __ tbnz(r3, 11, __ pc());                          //       tbnz    x3, #11, .
 175     __ tbnz(r3, 11, back);                             //       tbnz    x3, #11, back
 176     __ tbnz(r3, 11, forth);                            //       tbnz    x3, #11, forth
 177 
 178 // MoveWideImmOp
 179     __ movnw(r19, 6842, 0);                            //       movn    w19, #6842, lsl 0
 180     __ movzw(r28, 5843, 16);                           //       movz    w28, #5843, lsl 16
 181     __ movkw(r13, 20344, 16);                          //       movk    w13, #20344, lsl 16
 182     __ movn(r1, 1215, 32);                             //       movn    x1, #1215, lsl 32
 183     __ movz(r26, 28755, 0);                            //       movz    x26, #28755, lsl 0
 184     __ movk(r27, 5762, 48);                            //       movk    x27, #5762, lsl 48
 185 
 186 // BitfieldOp
 187     __ sbfm(r1, r24, 9, 24);                           //       sbfm    x1, x24, #9, #24
 188     __ bfmw(r25, r0, 5, 16);                           //       bfm     w25, w0, #5, #16
 189     __ ubfmw(r16, r27, 15, 7);                         //       ubfm    w16, w27, #15, #7
 190     __ sbfm(r16, r14, 15, 28);                         //       sbfm    x16, x14, #15, #28
 191     __ bfm(r24, r10, 0, 13);                           //       bfm     x24, x10, #0, #13
 192     __ ubfm(r1, r14, 2, 22);                           //       ubfm    x1, x14, #2, #22
 193 
 194 // ExtractOp
 195     __ extrw(r10, r0, r1, 21);                         //       extr    w10, w0, w1, #21
 196     __ extr(r26, r26, r23, 61);                        //       extr    x26, x26, x23, #61
 197 
 198 // CondBranchOp
 199     __ br(Assembler::EQ, __ pc());                     //       b.EQ    .
 200     __ br(Assembler::EQ, back);                        //       b.EQ    back
 201     __ br(Assembler::EQ, forth);                       //       b.EQ    forth
 202     __ br(Assembler::NE, __ pc());                     //       b.NE    .
 203     __ br(Assembler::NE, back);                        //       b.NE    back
 204     __ br(Assembler::NE, forth);                       //       b.NE    forth
 205     __ br(Assembler::HS, __ pc());                     //       b.HS    .
 206     __ br(Assembler::HS, back);                        //       b.HS    back
 207     __ br(Assembler::HS, forth);                       //       b.HS    forth
 208     __ br(Assembler::CS, __ pc());                     //       b.CS    .
 209     __ br(Assembler::CS, back);                        //       b.CS    back
 210     __ br(Assembler::CS, forth);                       //       b.CS    forth
 211     __ br(Assembler::LO, __ pc());                     //       b.LO    .
 212     __ br(Assembler::LO, back);                        //       b.LO    back
 213     __ br(Assembler::LO, forth);                       //       b.LO    forth
 214     __ br(Assembler::CC, __ pc());                     //       b.CC    .
 215     __ br(Assembler::CC, back);                        //       b.CC    back
 216     __ br(Assembler::CC, forth);                       //       b.CC    forth
 217     __ br(Assembler::MI, __ pc());                     //       b.MI    .
 218     __ br(Assembler::MI, back);                        //       b.MI    back
 219     __ br(Assembler::MI, forth);                       //       b.MI    forth
 220     __ br(Assembler::PL, __ pc());                     //       b.PL    .
 221     __ br(Assembler::PL, back);                        //       b.PL    back
 222     __ br(Assembler::PL, forth);                       //       b.PL    forth
 223     __ br(Assembler::VS, __ pc());                     //       b.VS    .
 224     __ br(Assembler::VS, back);                        //       b.VS    back
 225     __ br(Assembler::VS, forth);                       //       b.VS    forth
 226     __ br(Assembler::VC, __ pc());                     //       b.VC    .
 227     __ br(Assembler::VC, back);                        //       b.VC    back
 228     __ br(Assembler::VC, forth);                       //       b.VC    forth
 229     __ br(Assembler::HI, __ pc());                     //       b.HI    .
 230     __ br(Assembler::HI, back);                        //       b.HI    back
 231     __ br(Assembler::HI, forth);                       //       b.HI    forth
 232     __ br(Assembler::LS, __ pc());                     //       b.LS    .
 233     __ br(Assembler::LS, back);                        //       b.LS    back
 234     __ br(Assembler::LS, forth);                       //       b.LS    forth
 235     __ br(Assembler::GE, __ pc());                     //       b.GE    .
 236     __ br(Assembler::GE, back);                        //       b.GE    back
 237     __ br(Assembler::GE, forth);                       //       b.GE    forth
 238     __ br(Assembler::LT, __ pc());                     //       b.LT    .
 239     __ br(Assembler::LT, back);                        //       b.LT    back
 240     __ br(Assembler::LT, forth);                       //       b.LT    forth
 241     __ br(Assembler::GT, __ pc());                     //       b.GT    .
 242     __ br(Assembler::GT, back);                        //       b.GT    back
 243     __ br(Assembler::GT, forth);                       //       b.GT    forth
 244     __ br(Assembler::LE, __ pc());                     //       b.LE    .
 245     __ br(Assembler::LE, back);                        //       b.LE    back
 246     __ br(Assembler::LE, forth);                       //       b.LE    forth
 247     __ br(Assembler::AL, __ pc());                     //       b.AL    .
 248     __ br(Assembler::AL, back);                        //       b.AL    back
 249     __ br(Assembler::AL, forth);                       //       b.AL    forth
 250     __ br(Assembler::NV, __ pc());                     //       b.NV    .
 251     __ br(Assembler::NV, back);                        //       b.NV    back
 252     __ br(Assembler::NV, forth);                       //       b.NV    forth
 253 
 254 // ImmOp
 255     __ svc(15523);                                     //       svc     #15523
 256     __ hvc(3191);                                      //       hvc     #3191
 257     __ smc(18110);                                     //       smc     #18110
 258     __ brk(2818);                                      //       brk     #2818
 259     __ hlt(20860);                                     //       hlt     #20860
 260 
 261 // Op
 262     __ nop();                                          //       nop     
 263     __ eret();                                         //       eret    
 264     __ drps();                                         //       drps    
 265     __ isb();                                          //       isb     
 266 
 267 // SystemOp
 268     __ dsb(Assembler::OSHST);                          //       dsb     OSHST
 269     __ dmb(Assembler::ISHLD);                          //       dmb     ISHLD
 270 
 271 // OneRegOp
 272     __ br(r10);                                        //       br      x10
 273     __ blr(r22);                                       //       blr     x22
 274 
 275 // LoadStoreExclusiveOp
 276     __ stxr(r3, r21, r5);                              //       stxr    w3, x21, [x5]
 277     __ stlxr(r28, r9, r29);                            //       stlxr   w28, x9, [x29]
 278     __ ldxr(r28, r7);                                  //       ldxr    x28, [x7]
 279     __ ldaxr(r10, r23);                                //       ldaxr   x10, [x23]
 280     __ stlr(r7, r26);                                  //       stlr    x7, [x26]
 281     __ ldar(r16, r23);                                 //       ldar    x16, [x23]
 282 
 283 // LoadStoreExclusiveOp
 284     __ stxrw(r11, r7, r12);                            //       stxr    w11, w7, [x12]
 285     __ stlxrw(r16, r13, r26);                          //       stlxr   w16, w13, [x26]
 286     __ ldxrw(r25, r21);                                //       ldxr    w25, [x21]
 287     __ ldaxrw(r14, r4);                                //       ldaxr   w14, [x4]
 288     __ stlrw(r26, r9);                                 //       stlr    w26, [x9]
 289     __ ldarw(r0, r23);                                 //       ldar    w0, [x23]
 290 
 291 // LoadStoreExclusiveOp
 292     __ stxrh(r8, r0, r10);                             //       stxrh   w8, w0, [x10]
 293     __ stlxrh(r11, r1, r4);                            //       stlxrh  w11, w1, [x4]
 294     __ ldxrh(r14, r26);                                //       ldxrh   w14, [x26]
 295     __ ldaxrh(r19, r7);                                //       ldaxrh  w19, [x7]
 296     __ stlrh(r17, r22);                                //       stlrh   w17, [x22]
 297     __ ldarh(r20, r6);                                 //       ldarh   w20, [x6]
 298 
 299 // LoadStoreExclusiveOp
 300     __ stxrb(r25, r8, r6);                             //       stxrb   w25, w8, [x6]
 301     __ stlxrb(r5, r10, r25);                           //       stlxrb  w5, w10, [x25]
 302     __ ldxrb(r0, r22);                                 //       ldxrb   w0, [x22]
 303     __ ldaxrb(r8, r3);                                 //       ldaxrb  w8, [x3]
 304     __ stlrb(r5, r2);                                  //       stlrb   w5, [x2]
 305     __ ldarb(r6, r28);                                 //       ldarb   w6, [x28]
 306 
 307 // LoadStoreExclusiveOp
 308     __ ldxp(r17, r8, r14);                             //       ldxp    x17, x8, [x14]
 309     __ ldaxp(r14, r3, r2);                             //       ldaxp   x14, x3, [x2]
 310     __ stxp(r25, r17, r4, r19);                        //       stxp    w25, x17, x4, [x19]
 311     __ stlxp(r10, r16, r15, r8);                       //       stlxp   w10, x16, x15, [x8]
 312 
 313 // LoadStoreExclusiveOp
 314     __ ldxpw(r1, r11, r3);                             //       ldxp    w1, w11, [x3]
 315     __ ldaxpw(r0, r27, r12);                           //       ldaxp   w0, w27, [x12]
 316     __ stxpw(r4, r20, r21, r29);                       //       stxp    w4, w20, w21, [x29]
 317     __ stlxpw(r0, r9, r5, r29);                        //       stlxp   w0, w9, w5, [x29]
 318 
 319 // base_plus_unscaled_offset 
 320 // LoadStoreOp
 321     __ str(r17, Address(r4, -227));                    //       str     x17, [x4, -227]
 322     __ strw(r6, Address(r4, -33));                     //       str     w6, [x4, -33]
 323     __ strb(r13, Address(r16, 11));                    //       strb    w13, [x16, 11]
 324     __ strh(r23, Address(r22, -64));                   //       strh    w23, [x22, -64]
 325     __ ldr(r2, Address(r3, 13));                       //       ldr     x2, [x3, 13]
 326     __ ldrw(r5, Address(r20, 35));                     //       ldr     w5, [x20, 35]
 327     __ ldrb(r2, Address(r10, -15));                    //       ldrb    w2, [x10, -15]
 328     __ ldrh(r23, Address(r0, -8));                     //       ldrh    w23, [x0, -8]
 329     __ ldrsb(r15, Address(r14, -3));                   //       ldrsb   x15, [x14, -3]
 330     __ ldrsh(r3, Address(r3, -12));                    //       ldrsh   x3, [x3, -12]
 331     __ ldrshw(r25, Address(r24, -7));                  //       ldrsh   w25, [x24, -7]
 332     __ ldrsw(r17, Address(r0, -29));                   //       ldrsw   x17, [x0, -29]
 333     __ ldrd(v7, Address(r9, -79));                     //       ldr     d7, [x9, -79]
 334     __ ldrs(v11, Address(r11, -68));                   //       ldr     s11, [x11, -68]
 335     __ strd(v16, Address(r2, -119));                   //       str     d16, [x2, -119]
 336     __ strs(v25, Address(r28, -124));                  //       str     s25, [x28, -124]
 337 
 338 // pre 
 339 // LoadStoreOp
 340     __ str(r28, Address(__ pre(r19, 82)));             //       str     x28, [x19, 82]!
 341     __ strw(r7, Address(__ pre(r13, 50)));             //       str     w7, [x13, 50]!
 342     __ strb(r2, Address(__ pre(r19, -32)));            //       strb    w2, [x19, -32]!
 343     __ strh(r24, Address(__ pre(r1, -58)));            //       strh    w24, [x1, -58]!
 344     __ ldr(r23, Address(__ pre(r29, -143)));           //       ldr     x23, [x29, -143]!
 345     __ ldrw(r13, Address(__ pre(r27, 0)));             //       ldr     w13, [x27, 0]!
 346     __ ldrb(r11, Address(__ pre(r10, -26)));           //       ldrb    w11, [x10, -26]!
 347     __ ldrh(r3, Address(__ pre(r6, -54)));             //       ldrh    w3, [x6, -54]!
 348     __ ldrsb(r2, Address(__ pre(r9, 3)));              //       ldrsb   x2, [x9, 3]!
 349     __ ldrsh(r28, Address(__ pre(r4, 30)));            //       ldrsh   x28, [x4, 30]!
 350     __ ldrshw(r17, Address(__ pre(r0, -23)));          //       ldrsh   w17, [x0, -23]!
 351     __ ldrsw(r29, Address(__ pre(r25, -117)));         //       ldrsw   x29, [x25, -117]!
 352     __ ldrd(v21, Address(__ pre(r10, -142)));          //       ldr     d21, [x10, -142]!
 353     __ ldrs(v11, Address(__ pre(r20, 35)));            //       ldr     s11, [x20, 35]!
 354     __ strd(v1, Address(__ pre(r15, -214)));           //       str     d1, [x15, -214]!
 355     __ strs(v19, Address(__ pre(r5, -55)));            //       str     s19, [x5, -55]!
 356 
 357 // post 
 358 // LoadStoreOp
 359     __ str(r28, Address(__ post(r17, -20)));           //       str     x28, [x17], -20
 360     __ strw(r8, Address(__ post(r13, -9)));            //       str     w8, [x13], -9
 361     __ strb(r14, Address(__ post(r24, -23)));          //       strb    w14, [x24], -23
 362     __ strh(r2, Address(__ post(r4, -60)));            //       strh    w2, [x4], -60
 363     __ ldr(r24, Address(__ post(r25, 34)));            //       ldr     x24, [x25], 34
 364     __ ldrw(r16, Address(__ post(r28, -27)));          //       ldr     w16, [x28], -27
 365     __ ldrb(r8, Address(__ post(r23, -27)));           //       ldrb    w8, [x23], -27
 366     __ ldrh(r3, Address(__ post(r0, -58)));            //       ldrh    w3, [x0], -58
 367     __ ldrsb(r14, Address(__ post(r15, -10)));         //       ldrsb   x14, [x15], -10
 368     __ ldrsh(r12, Address(__ post(r1, 13)));           //       ldrsh   x12, [x1], 13
 369     __ ldrshw(r9, Address(__ post(r1, -19)));          //       ldrsh   w9, [x1], -19
 370     __ ldrsw(r29, Address(__ post(r10, -61)));         //       ldrsw   x29, [x10], -61
 371     __ ldrd(v13, Address(__ post(r28, -9)));           //       ldr     d13, [x28], -9
 372     __ ldrs(v20, Address(__ post(r27, -88)));          //       ldr     s20, [x27], -88
 373     __ strd(v7, Address(__ post(r11, -199)));          //       str     d7, [x11], -199
 374     __ strs(v20, Address(__ post(r22, -61)));          //       str     s20, [x22], -61
 375 
 376 // base_plus_reg 
 377 // LoadStoreOp
 378     __ str(r3, Address(r10, r16, Address::sxtw(0)));   //       str     x3, [x10, w16, sxtw #0]
 379     __ strw(r1, Address(r29, r21, Address::lsl(2)));   //       str     w1, [x29, x21, lsl #2]
 380     __ strb(r26, Address(r0, r23, Address::uxtw(0)));  //       strb    w26, [x0, w23, uxtw #0]
 381     __ strh(r26, Address(r0, r21, Address::lsl(0)));   //       strh    w26, [x0, x21, lsl #0]
 382     __ ldr(r3, Address(r25, r22, Address::lsl(0)));    //       ldr     x3, [x25, x22, lsl #0]
 383     __ ldrw(r25, Address(r9, r24, Address::uxtw(2)));  //       ldr     w25, [x9, w24, uxtw #2]
 384     __ ldrb(r10, Address(r0, r14, Address::sxtw(0)));  //       ldrb    w10, [x0, w14, sxtw #0]
 385     __ ldrh(r2, Address(r21, r20, Address::lsl(1)));   //       ldrh    w2, [x21, x20, lsl #1]
 386     __ ldrsb(r19, Address(r27, r28, Address::sxtx(0))); //      ldrsb   x19, [x27, x28, sxtx #0]
 387     __ ldrsh(r1, Address(r8, r3, Address::lsl(1)));    //       ldrsh   x1, [x8, x3, lsl #1]
 388     __ ldrshw(r20, Address(r15, r16, Address::sxtx(0))); //     ldrsh   w20, [x15, x16, sxtx #0]
 389     __ ldrsw(r7, Address(r7, r12, Address::lsl(2)));   //       ldrsw   x7, [x7, x12, lsl #2]
 390     __ ldrd(v15, Address(r4, r13, Address::sxtw(3)));  //       ldr     d15, [x4, w13, sxtw #3]
 391     __ ldrs(v14, Address(r10, r3, Address::uxtw(0)));  //       ldr     s14, [x10, w3, uxtw #0]
 392     __ strd(v24, Address(r23, r9, Address::sxtx(3)));  //       str     d24, [x23, x9, sxtx #3]
 393     __ strs(v9, Address(r12, r26, Address::uxtw(2)));  //       str     s9, [x12, w26, uxtw #2]
 394 
 395 // base_plus_scaled_offset 
 396 // LoadStoreOp
 397     __ str(r14, Address(r24, 13472));                  //       str     x14, [x24, 13472]
 398     __ strw(r0, Address(r14, 7392));                   //       str     w0, [x14, 7392]
 399     __ strb(r23, Address(r19, 1536));                  //       strb    w23, [x19, 1536]
 400     __ strh(r15, Address(r11, 3608));                  //       strh    w15, [x11, 3608]
 401     __ ldr(r21, Address(r25, 13672));                  //       ldr     x21, [x25, 13672]
 402     __ ldrw(r23, Address(r7, 6160));                   //       ldr     w23, [x7, 6160]
 403     __ ldrb(r23, Address(r16, 1975));                  //       ldrb    w23, [x16, 1975]
 404     __ ldrh(r24, Address(r24, 3850));                  //       ldrh    w24, [x24, 3850]
 405     __ ldrsb(r12, Address(r9, 1613));                  //       ldrsb   x12, [x9, 1613]
 406     __ ldrsh(r5, Address(r21, 3840));                  //       ldrsh   x5, [x21, 3840]
 407     __ ldrshw(r14, Address(r0, 3590));                 //       ldrsh   w14, [x0, 3590]
 408     __ ldrsw(r13, Address(r2, 7928));                  //       ldrsw   x13, [x2, 7928]
 409     __ ldrd(v15, Address(r19, 15800));                 //       ldr     d15, [x19, 15800]
 410     __ ldrs(v23, Address(r5, 6272));                   //       ldr     s23, [x5, 6272]
 411     __ strd(v6, Address(r6, 15136));                   //       str     d6, [x6, 15136]
 412     __ strs(v9, Address(r11, 6180));                   //       str     s9, [x11, 6180]
 413 
 414 // pcrel 
 415 // LoadStoreOp
 416     __ ldr(r7, forth);                                 //       ldr     x7, forth
 417     __ ldrw(r29, __ pc());                             //       ldr     w29, .
 418 
 419 // LoadStoreOp
 420     __ prfm(Address(r0, -215));                        //       prfm    PLDL1KEEP, [x0, -215]
 421 
 422 // LoadStoreOp
 423     __ prfm(forth);                                    //       prfm    PLDL1KEEP, forth
 424 
 425 // LoadStoreOp
 426     __ prfm(Address(r4, r3, Address::uxtw(0)));        //       prfm    PLDL1KEEP, [x4, w3, uxtw #0]
 427 
 428 // LoadStoreOp
 429     __ prfm(Address(r14, 12360));                      //       prfm    PLDL1KEEP, [x14, 12360]
 430 
 431 // AddSubCarryOp
 432     __ adcw(r7, r6, r4);                               //       adc     w7, w6, w4
 433     __ adcsw(r27, r12, r5);                            //       adcs    w27, w12, w5
 434     __ sbcw(r25, r24, r26);                            //       sbc     w25, w24, w26
 435     __ sbcsw(r5, r7, r23);                             //       sbcs    w5, w7, w23
 436     __ adc(r22, r11, r1);                              //       adc     x22, x11, x1
 437     __ adcs(r13, r9, r29);                             //       adcs    x13, x9, x29
 438     __ sbc(r4, r14, r26);                              //       sbc     x4, x14, x26
 439     __ sbcs(r28, r29, r24);                            //       sbcs    x28, x29, x24
 440 
 441 // AddSubExtendedOp
 442     __ addw(r17, r21, r21, ext::uxtw, 1);              //       add     w17, w21, w21, uxtw #1
 443     __ addsw(r12, r9, r26, ext::sxth, 3);              //       adds    w12, w9, w26, sxth #3
 444     __ sub(r14, r5, r3, ext::uxth, 1);                 //       sub     x14, x5, x3, uxth #1
 445     __ subsw(r17, r26, r6, ext::uxtx, 4);              //       subs    w17, w26, w6, uxtx #4
 446     __ add(r17, r5, r20, ext::sxth, 3);                //       add     x17, x5, x20, sxth #3
 447     __ adds(r16, r1, r25, ext::sxtw, 3);               //       adds    x16, x1, x25, sxtw #3
 448     __ sub(r25, r1, r26, ext::sxtx, 3);                //       sub     x25, x1, x26, sxtx #3
 449     __ subs(r19, r1, r23, ext::sxth, 3);               //       subs    x19, x1, x23, sxth #3
 450 
 451 // ConditionalCompareOp
 452     __ ccmnw(r1, r24, 9u, Assembler::LS);              //       ccmn    w1, w24, #9, LS
 453     __ ccmpw(r14, r10, 4u, Assembler::GT);             //       ccmp    w14, w10, #4, GT
 454     __ ccmn(r9, r29, 0u, Assembler::CC);               //       ccmn    x9, x29, #0, CC
 455     __ ccmp(r6, r6, 13u, Assembler::MI);               //       ccmp    x6, x6, #13, MI
 456 
 457 // ConditionalCompareImmedOp
 458     __ ccmnw(r19, 11, 5, Assembler::NE);               //       ccmn    w19, #11, #5, NE
 459     __ ccmpw(r11, 31, 15, Assembler::GE);              //       ccmp    w11, #31, #15, GE
 460     __ ccmn(r12, 14, 5, Assembler::VS);                //       ccmn    x12, #14, #5, VS
 461     __ ccmp(r1, 7, 10, Assembler::MI);                 //       ccmp    x1, #7, #10, MI
 462 
 463 // ConditionalSelectOp
 464     __ cselw(r6, r2, r22, Assembler::LO);              //       csel    w6, w2, w22, LO
 465     __ csincw(r29, r22, r26, Assembler::VS);           //       csinc   w29, w22, w26, VS
 466     __ csinvw(r26, r25, r11, Assembler::LS);           //       csinv   w26, w25, w11, LS
 467     __ csnegw(r19, r14, r16, Assembler::GT);           //       csneg   w19, w14, w16, GT
 468     __ csel(r13, r21, r20, Assembler::CS);             //       csel    x13, x21, x20, CS
 469     __ csinc(r12, r11, r27, Assembler::HI);            //       csinc   x12, x11, x27, HI
 470     __ csinv(r3, r17, r19, Assembler::LE);             //       csinv   x3, x17, x19, LE
 471     __ csneg(r24, r1, r7, Assembler::VS);              //       csneg   x24, x1, x7, VS
 472 
 473 // TwoRegOp
 474     __ rbitw(r23, r1);                                 //       rbit    w23, w1
 475     __ rev16w(r16, r16);                               //       rev16   w16, w16
 476     __ revw(r24, r25);                                 //       rev     w24, w25
 477     __ clzw(r25, r8);                                  //       clz     w25, w8
 478     __ clsw(r27, r12);                                 //       cls     w27, w12
 479     __ rbit(r21, r5);                                  //       rbit    x21, x5
 480     __ rev16(r20, r9);                                 //       rev16   x20, x9
 481     __ rev32(r20, r9);                                 //       rev32   x20, x9
 482     __ rev(r19, r10);                                  //       rev     x19, x10
 483     __ clz(r8, r2);                                    //       clz     x8, x2
 484     __ cls(r29, r3);                                   //       cls     x29, x3
 485 
 486 // ThreeRegOp
 487     __ udivw(r19, r7, r29);                            //       udiv    w19, w7, w29
 488     __ sdivw(r26, r27, r10);                           //       sdiv    w26, w27, w10
 489     __ lslvw(r0, r24, r16);                            //       lslv    w0, w24, w16
 490     __ lsrvw(r22, r10, r24);                           //       lsrv    w22, w10, w24
 491     __ asrvw(r0, r26, r16);                            //       asrv    w0, w26, w16
 492     __ rorvw(r27, r25, r15);                           //       rorv    w27, w25, w15
 493     __ udiv(r8, r28, r15);                             //       udiv    x8, x28, x15
 494     __ sdiv(r20, r11, r5);                             //       sdiv    x20, x11, x5
 495     __ lslv(r21, r25, r16);                            //       lslv    x21, x25, x16
 496     __ lsrv(r7, r2, r14);                              //       lsrv    x7, x2, x14
 497     __ asrv(r21, r8, r22);                             //       asrv    x21, x8, x22
 498     __ rorv(r7, r5, r15);                              //       rorv    x7, x5, x15
 499     __ umulh(r12, r21, r22);                           //       umulh   x12, x21, x22
 500     __ smulh(r16, r10, r5);                            //       smulh   x16, x10, x5
 501 
 502 // FourRegMulOp
 503     __ maddw(r2, r6, r26, r21);                        //       madd    w2, w6, w26, w21
 504     __ msubw(r27, r19, r3, r27);                       //       msub    w27, w19, w3, w27
 505     __ madd(r27, r5, r8, r3);                          //       madd    x27, x5, x8, x3
 506     __ msub(r8, r13, r28, r13);                        //       msub    x8, x13, x28, x13
 507     __ smaddl(r29, r9, r8, r0);                        //       smaddl  x29, w9, w8, x0
 508     __ smsubl(r14, r9, r14, r23);                      //       smsubl  x14, w9, w14, x23
 509     __ umaddl(r15, r4, r11, r13);                      //       umaddl  x15, w4, w11, x13
 510     __ umsubl(r23, r3, r17, r24);                      //       umsubl  x23, w3, w17, x24
 511 
 512 // ThreeRegFloatOp
 513     __ fmuls(v29, v1, v17);                            //       fmul    s29, s1, s17
 514     __ fdivs(v23, v28, v9);                            //       fdiv    s23, s28, s9
 515     __ fadds(v14, v19, v12);                           //       fadd    s14, s19, s12
 516     __ fsubs(v27, v17, v0);                            //       fsub    s27, s17, s0
 517     __ fmuls(v16, v24, v6);                            //       fmul    s16, s24, s6
 518     __ fmuld(v4, v23, v10);                            //       fmul    d4, d23, d10
 519     __ fdivd(v11, v9, v23);                            //       fdiv    d11, d9, d23
 520     __ faddd(v7, v15, v7);                             //       fadd    d7, d15, d7
 521     __ fsubd(v29, v21, v12);                           //       fsub    d29, d21, d12
 522     __ fmuld(v27, v4, v9);                             //       fmul    d27, d4, d9
 523 
 524 // FourRegFloatOp
 525     __ fmadds(v27, v14, v11, v25);                     //       fmadd   s27, s14, s11, s25
 526     __ fmsubs(v11, v22, v15, v3);                      //       fmsub   s11, s22, s15, s3
 527     __ fnmadds(v10, v27, v24, v4);                     //       fnmadd  s10, s27, s24, s4
 528     __ fnmadds(v4, v6, v1, v1);                        //       fnmadd  s4, s6, s1, s1
 529     __ fmaddd(v13, v28, v3, v2);                       //       fmadd   d13, d28, d3, d2
 530     __ fmsubd(v26, v24, v7, v26);                      //       fmsub   d26, d24, d7, d26
 531     __ fnmaddd(v21, v5, v12, v26);                     //       fnmadd  d21, d5, d12, d26
 532     __ fnmaddd(v11, v16, v20, v3);                     //       fnmadd  d11, d16, d20, d3
 533 
 534 // TwoRegFloatOp
 535     __ fmovs(v5, v17);                                 //       fmov    s5, s17
 536     __ fabss(v7, v9);                                  //       fabs    s7, s9
 537     __ fnegs(v25, v1);                                 //       fneg    s25, s1
 538     __ fsqrts(v24, v6);                                //       fsqrt   s24, s6
 539     __ fcvts(v27, v17);                                //       fcvt    d27, s17
 540     __ fmovd(v22, v2);                                 //       fmov    d22, d2
 541     __ fabsd(v14, v20);                                //       fabs    d14, d20
 542     __ fnegd(v29, v11);                                //       fneg    d29, d11
 543     __ fsqrtd(v28, v12);                               //       fsqrt   d28, d12
 544     __ fcvtd(v4, v3);                                  //       fcvt    s4, d3
 545 
 546 // FloatConvertOp
 547     __ fcvtzsw(r28, v13);                              //       fcvtzs  w28, s13
 548     __ fcvtzs(r7, v28);                                //       fcvtzs  x7, s28
 549     __ fcvtzdw(r12, v15);                              //       fcvtzs  w12, d15
 550     __ fcvtzd(r11, v6);                                //       fcvtzs  x11, d6
 551     __ scvtfws(v22, r22);                              //       scvtf   s22, w22
 552     __ scvtfs(v5, r16);                                //       scvtf   s5, x16
 553     __ scvtfwd(v3, r15);                               //       scvtf   d3, w15
 554     __ scvtfd(v6, r8);                                 //       scvtf   d6, x8
 555     __ fmovs(r26, v29);                                //       fmov    w26, s29
 556     __ fmovd(r24, v17);                                //       fmov    x24, d17
 557     __ fmovs(v2, r19);                                 //       fmov    s2, w19
 558     __ fmovd(v21, r5);                                 //       fmov    d21, x5
 559 
 560 // TwoRegFloatOp
 561     __ fcmps(v23, v8);                                 //       fcmp    s23, s8
 562     __ fcmpd(v12, v2);                                 //       fcmp    d12, d2
 563     __ fcmps(v14, 0.0);                                //       fcmp    s14, #0.0
 564     __ fcmpd(v10, 0.0);                                //       fcmp    d10, #0.0
 565 
 566 // LoadStorePairOp
 567     __ stpw(r8, r17, Address(r12, -96));               //       stp     w8, w17, [x12, #-96]
 568     __ ldpw(r1, r21, Address(r28, -192));              //       ldp     w1, w21, [x28, #-192]
 569     __ ldpsw(r25, r22, Address(r16, -64));             //       ldpsw   x25, x22, [x16, #-64]
 570     __ stp(r6, r8, Address(r23, -128));                //       stp     x6, x8, [x23, #-128]
 571     __ ldp(r25, r16, Address(r19, -112));              //       ldp     x25, x16, [x19, #-112]
 572 
 573 // LoadStorePairOp
 574     __ stpw(r29, r27, Address(__ pre(r13, -240)));     //       stp     w29, w27, [x13, #-240]!
 575     __ ldpw(r12, r20, Address(__ pre(r21, -32)));      //       ldp     w12, w20, [x21, #-32]!
 576     __ ldpsw(r0, r15, Address(__ pre(r4, -144)));      //       ldpsw   x0, x15, [x4, #-144]!
 577     __ stp(r13, r12, Address(__ pre(r19, 128)));       //       stp     x13, x12, [x19, #128]!
 578     __ ldp(r25, r2, Address(__ pre(r9, 96)));          //       ldp     x25, x2, [x9, #96]!
 579 
 580 // LoadStorePairOp
 581     __ stpw(r11, r1, Address(__ post(r26, 128)));      //       stp     w11, w1, [x26], #128
 582     __ ldpw(r26, r25, Address(__ post(r3, 32)));       //       ldp     w26, w25, [x3], #32
 583     __ ldpsw(r10, r14, Address(__ post(r2, -240)));    //       ldpsw   x10, x14, [x2], #-240
 584     __ stp(r1, r3, Address(__ post(r10, 128)));        //       stp     x1, x3, [x10], #128
 585     __ ldp(r23, r12, Address(__ post(r25, -144)));     //       ldp     x23, x12, [x25], #-144
 586 
 587 // LoadStorePairOp
 588     __ stnpw(r5, r8, Address(r25, 64));                //       stnp    w5, w8, [x25, #64]
 589     __ ldnpw(r20, r19, Address(r22, -240));            //       ldnp    w20, w19, [x22, #-240]
 590     __ stnp(r23, r7, Address(r14, -176));              //       stnp    x23, x7, [x14, #-176]
 591     __ ldnp(r14, r28, Address(r21, 64));               //       ldnp    x14, x28, [x21, #64]
 592 
 593 // LdStSIMDOp
 594     __ ld1(v10, __ T8B, Address(r4));                  //       ld1     {v10.8B}, [x4]
 595     __ ld1(v25, v26, __ T16B, Address(__ post(r26, 32))); //    ld1     {v25.16B, v26.16B}, [x26], 32
 596     __ ld1(v27, v28, v29, __ T1D, Address(__ post(r4, r23))); //        ld1     {v27.1D, v28.1D, v29.1D}, [x4], x23
 597     __ ld1(v16, v17, v18, v19, __ T8H, Address(__ post(r6, 64))); //    ld1     {v16.8H, v17.8H, v18.8H, v19.8H}, [x6], 64
 598     __ ld1r(v1, __ T8B, Address(r27));                 //       ld1r    {v1.8B}, [x27]
 599     __ ld1r(v4, __ T4S, Address(__ post(r2, 4)));      //       ld1r    {v4.4S}, [x2], 4
 600     __ ld1r(v21, __ T1D, Address(__ post(r29, r15)));  //       ld1r    {v21.1D}, [x29], x15
 601     __ ld2(v1, v2, __ T2D, Address(r22));              //       ld2     {v1.2D, v2.2D}, [x22]
 602     __ ld2(v29, v30, __ T4H, Address(__ post(r8, 16))); //      ld2     {v29.4H, v30.4H}, [x8], 16
 603     __ ld2r(v24, v25, __ T16B, Address(r4));           //       ld2r    {v24.16B, v25.16B}, [x4]
 604     __ ld2r(v21, v22, __ T2S, Address(__ post(r19, 8))); //     ld2r    {v21.2S, v22.2S}, [x19], 8
 605     __ ld2r(v13, v14, __ T2D, Address(__ post(r13, r6))); //    ld2r    {v13.2D, v14.2D}, [x13], x6
 606     __ ld3(v1, v2, v3, __ T4S, Address(__ post(r4, r17))); //   ld3     {v1.4S, v2.4S, v3.4S}, [x4], x17
 607     __ ld3(v22, v23, v24, __ T2S, Address(r17));       //       ld3     {v22.2S, v23.2S, v24.2S}, [x17]
 608     __ ld3r(v17, v18, v19, __ T8H, Address(r17));      //       ld3r    {v17.8H, v18.8H, v19.8H}, [x17]
 609     __ ld3r(v8, v9, v10, __ T4S, Address(__ post(r28, 12))); // ld3r    {v8.4S, v9.4S, v10.4S}, [x28], 12
 610     __ ld3r(v5, v6, v7, __ T1D, Address(__ post(r1, r19))); //  ld3r    {v5.1D, v6.1D, v7.1D}, [x1], x19
 611     __ ld4(v1, v2, v3, v4, __ T8H, Address(__ post(r15, 64))); //       ld4     {v1.8H, v2.8H, v3.8H, v4.8H}, [x15], 64
 612     __ ld4(v17, v18, v19, v20, __ T8B, Address(__ post(r6, r26))); //   ld4     {v17.8B, v18.8B, v19.8B, v20.8B}, [x6], x26
 613     __ ld4r(v25, v26, v27, v28, __ T8B, Address(r7));  //       ld4r    {v25.8B, v26.8B, v27.8B, v28.8B}, [x7]
 614     __ ld4r(v12, v13, v14, v15, __ T4H, Address(__ post(r8, 8))); //    ld4r    {v12.4H, v13.4H, v14.4H, v15.4H}, [x8], 8
 615     __ ld4r(v9, v10, v11, v12, __ T2S, Address(__ post(r13, r1))); //   ld4r    {v9.2S, v10.2S, v11.2S, v12.2S}, [x13], x1
 616 
 617 // SpecialCases
 618     __ ccmn(zr, zr, 3u, Assembler::LE);                //       ccmn    xzr, xzr, #3, LE
 619     __ ccmnw(zr, zr, 5u, Assembler::EQ);               //       ccmn    wzr, wzr, #5, EQ
 620     __ ccmp(zr, 1, 4u, Assembler::NE);                 //       ccmp    xzr, 1, #4, NE
 621     __ ccmpw(zr, 2, 2, Assembler::GT);                 //       ccmp    wzr, 2, #2, GT
 622     __ extr(zr, zr, zr, 0);                            //       extr    xzr, xzr, xzr, 0
 623     __ stlxp(r0, zr, zr, sp);                          //       stlxp   w0, xzr, xzr, [sp]
 624     __ stlxpw(r2, zr, zr, r3);                         //       stlxp   w2, wzr, wzr, [x3]
 625     __ stxp(r4, zr, zr, r5);                           //       stxp    w4, xzr, xzr, [x5]
 626     __ stxpw(r6, zr, zr, sp);                          //       stxp    w6, wzr, wzr, [sp]
 627     __ dup(v0, __ T16B, zr);                           //       dup     v0.16b, wzr
 628     __ mov(v1, __ T1D, 0, zr);                         //       mov     v1.d[0], xzr
 629     __ mov(v1, __ T2S, 1, zr);                         //       mov     v1.s[1], wzr
 630     __ mov(v1, __ T4H, 2, zr);                         //       mov     v1.h[2], wzr
 631     __ mov(v1, __ T8B, 3, zr);                         //       mov     v1.b[3], wzr
 632     __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); //       ld1     {v31.2d, v0.2d}, [x1], x0
 633 
 634 // FloatImmediateOp
 635     __ fmovd(v0, 2.0);                                 //       fmov d0, #2.0
 636     __ fmovd(v0, 2.125);                               //       fmov d0, #2.125
 637     __ fmovd(v0, 4.0);                                 //       fmov d0, #4.0
 638     __ fmovd(v0, 4.25);                                //       fmov d0, #4.25
 639     __ fmovd(v0, 8.0);                                 //       fmov d0, #8.0
 640     __ fmovd(v0, 8.5);                                 //       fmov d0, #8.5
 641     __ fmovd(v0, 16.0);                                //       fmov d0, #16.0
 642     __ fmovd(v0, 17.0);                                //       fmov d0, #17.0
 643     __ fmovd(v0, 0.125);                               //       fmov d0, #0.125
 644     __ fmovd(v0, 0.1328125);                           //       fmov d0, #0.1328125
 645     __ fmovd(v0, 0.25);                                //       fmov d0, #0.25
 646     __ fmovd(v0, 0.265625);                            //       fmov d0, #0.265625
 647     __ fmovd(v0, 0.5);                                 //       fmov d0, #0.5
 648     __ fmovd(v0, 0.53125);                             //       fmov d0, #0.53125
 649     __ fmovd(v0, 1.0);                                 //       fmov d0, #1.0
 650     __ fmovd(v0, 1.0625);                              //       fmov d0, #1.0625
 651     __ fmovd(v0, -2.0);                                //       fmov d0, #-2.0
 652     __ fmovd(v0, -2.125);                              //       fmov d0, #-2.125
 653     __ fmovd(v0, -4.0);                                //       fmov d0, #-4.0
 654     __ fmovd(v0, -4.25);                               //       fmov d0, #-4.25
 655     __ fmovd(v0, -8.0);                                //       fmov d0, #-8.0
 656     __ fmovd(v0, -8.5);                                //       fmov d0, #-8.5
 657     __ fmovd(v0, -16.0);                               //       fmov d0, #-16.0
 658     __ fmovd(v0, -17.0);                               //       fmov d0, #-17.0
 659     __ fmovd(v0, -0.125);                              //       fmov d0, #-0.125
 660     __ fmovd(v0, -0.1328125);                          //       fmov d0, #-0.1328125
 661     __ fmovd(v0, -0.25);                               //       fmov d0, #-0.25
 662     __ fmovd(v0, -0.265625);                           //       fmov d0, #-0.265625
 663     __ fmovd(v0, -0.5);                                //       fmov d0, #-0.5
 664     __ fmovd(v0, -0.53125);                            //       fmov d0, #-0.53125
 665     __ fmovd(v0, -1.0);                                //       fmov d0, #-1.0
 666     __ fmovd(v0, -1.0625);                             //       fmov d0, #-1.0625
 667 
 668 // LSEOp
 669     __ swp(Assembler::xword, r26, r3, r6);             //       swp     x26, x3, [x6]
 670     __ ldadd(Assembler::xword, r20, r12, r4);          //       ldadd   x20, x12, [x4]
 671     __ ldbic(Assembler::xword, r23, r4, r11);          //       ldclr   x23, x4, [x11]
 672     __ ldeor(Assembler::xword, r15, r15, r24);         //       ldeor   x15, x15, [x24]
 673     __ ldorr(Assembler::xword, r29, r2, r17);          //       ldset   x29, x2, [x17]
 674     __ ldsmin(Assembler::xword, r25, r5, r1);          //       ldsmin  x25, x5, [x1]
 675     __ ldsmax(Assembler::xword, r15, r15, r7);         //       ldsmax  x15, x15, [x7]
 676     __ ldumin(Assembler::xword, r28, zr, r29);         //       ldumin  x28, xzr, [x29]
 677     __ ldumax(Assembler::xword, r17, r17, sp);         //       ldumax  x17, x17, [sp]
 678 
 679 // LSEOp
 680     __ swpa(Assembler::xword, r7, r16, r21);           //       swpa    x7, x16, [x21]
 681     __ ldadda(Assembler::xword, r17, r10, r20);        //       ldadda  x17, x10, [x20]
 682     __ ldbica(Assembler::xword, r25, r14, r29);        //       ldclra  x25, x14, [x29]
 683     __ ldeora(Assembler::xword, r25, r13, r3);         //       ldeora  x25, x13, [x3]
 684     __ ldorra(Assembler::xword, r13, r7, r28);         //       ldseta  x13, x7, [x28]
 685     __ ldsmina(Assembler::xword, r20, r25, r7);        //       ldsmina x20, x25, [x7]
 686     __ ldsmaxa(Assembler::xword, r21, r4, r2);         //       ldsmaxa x21, x4, [x2]
 687     __ ldumina(Assembler::xword, r8, r5, r8);          //       ldumina x8, x5, [x8]
 688     __ ldumaxa(Assembler::xword, r10, r12, r6);        //       ldumaxa x10, x12, [x6]
 689 
 690 // LSEOp
 691     __ swpal(Assembler::xword, r25, r12, r10);         //       swpal   x25, x12, [x10]
 692     __ ldaddal(Assembler::xword, r12, r1, r4);         //       ldaddal x12, x1, [x4]
 693     __ ldbical(Assembler::xword, r26, r6, r12);        //       ldclral x26, x6, [x12]
 694     __ ldeoral(Assembler::xword, r1, r14, r12);        //       ldeoral x1, x14, [x12]
 695     __ ldorral(Assembler::xword, r22, r6, r21);        //       ldsetal x22, x6, [x21]
 696     __ ldsminal(Assembler::xword, r15, r4, r6);        //       ldsminal        x15, x4, [x6]
 697     __ ldsmaxal(Assembler::xword, r24, r16, r7);       //       ldsmaxal        x24, x16, [x7]
 698     __ lduminal(Assembler::xword, r5, r3, r11);        //       lduminal        x5, x3, [x11]
 699     __ ldumaxal(Assembler::xword, r22, r2, r25);       //       ldumaxal        x22, x2, [x25]
 700 
 701 // LSEOp
 702     __ swpl(Assembler::xword, r6, r29, r0);            //       swpl    x6, x29, [x0]
 703     __ ldaddl(Assembler::xword, r26, r6, r23);         //       ldaddl  x26, x6, [x23]
 704     __ ldbicl(Assembler::xword, r4, r7, r9);           //       ldclrl  x4, x7, [x9]
 705     __ ldeorl(Assembler::xword, r6, r11, r1);          //       ldeorl  x6, x11, [x1]
 706     __ ldorrl(Assembler::xword, r11, r13, r29);        //       ldsetl  x11, x13, [x29]
 707     __ ldsminl(Assembler::xword, r11, r3, r6);         //       ldsminl x11, x3, [x6]
 708     __ ldsmaxl(Assembler::xword, r21, r0, r11);        //       ldsmaxl x21, x0, [x11]
 709     __ lduminl(Assembler::xword, r11, r23, r9);        //       lduminl x11, x23, [x9]
 710     __ ldumaxl(Assembler::xword, r17, r16, r16);       //       ldumaxl x17, x16, [x16]
 711 
 712 // LSEOp
 713     __ swp(Assembler::word, r21, r5, sp);              //       swp     w21, w5, [sp]
 714     __ ldadd(Assembler::word, r24, r11, r4);           //       ldadd   w24, w11, [x4]
 715     __ ldbic(Assembler::word, r17, r29, r4);           //       ldclr   w17, w29, [x4]
 716     __ ldeor(Assembler::word, r15, r11, r15);          //       ldeor   w15, w11, [x15]
 717     __ ldorr(Assembler::word, r27, r26, r11);          //       ldset   w27, w26, [x11]
 718     __ ldsmin(Assembler::word, r27, r12, r8);          //       ldsmin  w27, w12, [x8]
 719     __ ldsmax(Assembler::word, r6, r20, r1);           //       ldsmax  w6, w20, [x1]
 720     __ ldumin(Assembler::word, r14, r16, r29);         //       ldumin  w14, w16, [x29]
 721     __ ldumax(Assembler::word, r24, r13, r26);         //       ldumax  w24, w13, [x26]
 722 
 723 // LSEOp
 724     __ swpa(Assembler::word, r4, r2, r11);             //       swpa    w4, w2, [x11]
 725     __ ldadda(Assembler::word, r20, r29, r4);          //       ldadda  w20, w29, [x4]
 726     __ ldbica(Assembler::word, r20, zr, r29);          //       ldclra  w20, wzr, [x29]
 727     __ ldeora(Assembler::word, r0, r15, r25);          //       ldeora  w0, w15, [x25]
 728     __ ldorra(Assembler::word, r23, r5, r20);          //       ldseta  w23, w5, [x20]
 729     __ ldsmina(Assembler::word, r29, r26, r19);        //       ldsmina w29, w26, [x19]
 730     __ ldsmaxa(Assembler::word, r21, r20, r22);        //       ldsmaxa w21, w20, [x22]
 731     __ ldumina(Assembler::word, r26, r21, r16);        //       ldumina w26, w21, [x16]
 732     __ ldumaxa(Assembler::word, r8, r21, r10);         //       ldumaxa w8, w21, [x10]
 733 
 734 // LSEOp
 735     __ swpal(Assembler::word, r27, r11, r11);          //       swpal   w27, w11, [x11]
 736     __ ldaddal(Assembler::word, r5, r8, r28);          //       ldaddal w5, w8, [x28]
 737     __ ldbical(Assembler::word, r0, r5, r5);           //       ldclral w0, w5, [x5]
 738     __ ldeoral(Assembler::word, r2, r10, r24);         //       ldeoral w2, w10, [x24]
 739     __ ldorral(Assembler::word, r13, zr, sp);          //       ldsetal w13, wzr, [sp]
 740     __ ldsminal(Assembler::word, r26, r25, r24);       //       ldsminal        w26, w25, [x24]
 741     __ ldsmaxal(Assembler::word, r8, r5, r6);          //       ldsmaxal        w8, w5, [x6]
 742     __ lduminal(Assembler::word, r5, r27, r27);        //       lduminal        w5, w27, [x27]
 743     __ ldumaxal(Assembler::word, r23, r20, r23);       //       ldumaxal        w23, w20, [x23]
 744 
 745 // LSEOp
 746     __ swpl(Assembler::word, r25, r3, r28);            //       swpl    w25, w3, [x28]
 747     __ ldaddl(Assembler::word, r10, r8, r13);          //       ldaddl  w10, w8, [x13]
 748     __ ldbicl(Assembler::word, r21, r11, sp);          //       ldclrl  w21, w11, [sp]
 749     __ ldeorl(Assembler::word, zr, r3, r28);           //       ldeorl  wzr, w3, [x28]
 750     __ ldorrl(Assembler::word, r15, r0, r24);          //       ldsetl  w15, w0, [x24]
 751     __ ldsminl(Assembler::word, r4, r9, r29);          //       ldsminl w4, w9, [x29]
 752     __ ldsmaxl(Assembler::word, r8, r6, r21);          //       ldsmaxl w8, w6, [x21]
 753     __ lduminl(Assembler::word, r9, r22, r3);          //       lduminl w9, w22, [x3]
 754     __ ldumaxl(Assembler::word, r26, r10, r28);        //       ldumaxl w26, w10, [x28]
 755 
 756     __ bind(forth);
 757 
 758 /*
 759 aarch64ops.o:     file format elf64-littleaarch64
 760 
 761 
 762 Disassembly of section .text:
 763 
 764 0000000000000000 <back>:
 765    0:   8b1ad014        add     x20, x0, x26, lsl #52
 766    4:   cb83db85        sub     x5, x28, x3, asr #54
 767    8:   ab839ecb        adds    x11, x22, x3, asr #39
 768    c:   eb4c646b        subs    x11, x3, x12, lsr #25
 769   10:   0b0d399b        add     w27, w12, w13, lsl #14
 770   14:   4b9b1eaa        sub     w10, w21, w27, asr #7
 771   18:   2b1011c3        adds    w3, w14, w16, lsl #4
 772   1c:   6b1d1661        subs    w1, w19, w29, lsl #5
 773   20:   8a5b1a30        and     x16, x17, x27, lsr #6
 774   24:   aa1c8f96        orr     x22, x28, x28, lsl #35
 775   28:   ca5ccd4b        eor     x11, x10, x28, lsr #51
 776   2c:   ea8ec10d        ands    x13, x8, x14, asr #48
 777   30:   0a410c61        and     w1, w3, w1, lsr #3
 778   34:   2a855909        orr     w9, w8, w5, asr #22
 779   38:   4a9b4f82        eor     w2, w28, w27, asr #19
 780   3c:   6a073938        ands    w24, w9, w7, lsl #14
 781   40:   8ab9826b        bic     x11, x19, x25, asr #32
 782   44:   aa3d7318        orn     x24, x24, x29, lsl #28
 783   48:   cab16e0b        eon     x11, x16, x17, asr #27
 784   4c:   ea6ae9a5        bics    x5, x13, x10, lsr #58
 785   50:   0a357545        bic     w5, w10, w21, lsl #29
 786   54:   2a354d64        orn     w4, w11, w21, lsl #19
 787   58:   4a7c3f95        eon     w21, w28, w28, lsr #15
 788   5c:   6a2e7146        bics    w6, w10, w14, lsl #28
 789   60:   110ec6ca        add     w10, w22, #0x3b1
 790   64:   310e9d6f        adds    w15, w11, #0x3a7
 791   68:   510afcc5        sub     w5, w6, #0x2bf
 792   6c:   7108e013        subs    w19, w0, #0x238
 793   70:   91098114        add     x20, x8, #0x260
 794   74:   b10434d0        adds    x16, x6, #0x10d
 795   78:   d10db417        sub     x23, x0, #0x36d
 796   7c:   f10c873a        subs    x26, x25, #0x321
 797   80:   120d6a0c        and     w12, w16, #0xfff83fff
 798   84:   32066b01        orr     w1, w24, #0xfc1fffff
 799   88:   52112073        eor     w19, w3, #0xff8000
 800   8c:   720a553d        ands    w29, w9, #0xffc00fff
 801   90:   9263d0ba        and     x26, x5, #0xffffffffe003ffff
 802   94:   b20da1d8        orr     x24, x14, #0xff80ff80ff80ff8
 803   98:   d26ec404        eor     x4, x0, #0xfffffffffffc000f
 804   9c:   f26e28dc        ands    x28, x6, #0x1ffc0000
 805   a0:   14000000        b       a0 <back+0xa0>
 806   a4:   17ffffd7        b       0 <back>
 807   a8:   140001ee        b       860 <forth>
 808   ac:   94000000        bl      ac <back+0xac>
 809   b0:   97ffffd4        bl      0 <back>
 810   b4:   940001eb        bl      860 <forth>
 811   b8:   34000015        cbz     w21, b8 <back+0xb8>
 812   bc:   34fffa35        cbz     w21, 0 <back>
 813   c0:   34003d15        cbz     w21, 860 <forth>
 814   c4:   3500000c        cbnz    w12, c4 <back+0xc4>
 815   c8:   35fff9cc        cbnz    w12, 0 <back>
 816   cc:   35003cac        cbnz    w12, 860 <forth>
 817   d0:   b400000e        cbz     x14, d0 <back+0xd0>
 818   d4:   b4fff96e        cbz     x14, 0 <back>
 819   d8:   b4003c4e        cbz     x14, 860 <forth>
 820   dc:   b500001b        cbnz    x27, dc <back+0xdc>
 821   e0:   b5fff91b        cbnz    x27, 0 <back>
 822   e4:   b5003bfb        cbnz    x27, 860 <forth>
 823   e8:   1000000e        adr     x14, e8 <back+0xe8>
 824   ec:   10fff8ae        adr     x14, 0 <back>
 825   f0:   10003b8e        adr     x14, 860 <forth>
 826   f4:   90000016        adrp    x22, 0 <back>
 827   f8:   36280000        tbz     w0, #5, f8 <back+0xf8>
 828   fc:   362ff820        tbz     w0, #5, 0 <back>
 829  100:   36283b00        tbz     w0, #5, 860 <forth>
 830  104:   37580003        tbnz    w3, #11, 104 <back+0x104>
 831  108:   375ff7c3        tbnz    w3, #11, 0 <back>
 832  10c:   37583aa3        tbnz    w3, #11, 860 <forth>
 833  110:   12835753        mov     w19, #0xffffe545                // #-6843
 834  114:   52a2da7c        mov     w28, #0x16d30000                // #382926848
 835  118:   72a9ef0d        movk    w13, #0x4f78, lsl #16
 836  11c:   92c097e1        mov     x1, #0xfffffb40ffffffff         // #-5218385264641
 837  120:   d28e0a7a        mov     x26, #0x7053                    // #28755
 838  124:   f2e2d05b        movk    x27, #0x1682, lsl #48
 839  128:   93496301        sbfx    x1, x24, #9, #16
 840  12c:   33054019        bfxil   w25, w0, #5, #12
 841  130:   530f1f70        ubfiz   w16, w27, #17, #8
 842  134:   934f71d0        sbfx    x16, x14, #15, #14
 843  138:   b3403558        bfxil   x24, x10, #0, #14
 844  13c:   d34259c1        ubfx    x1, x14, #2, #21
 845  140:   1381540a        extr    w10, w0, w1, #21
 846  144:   93d7f75a        extr    x26, x26, x23, #61
 847  148:   54000000        b.eq    148 <back+0x148>
 848  14c:   54fff5a0        b.eq    0 <back>
 849  150:   54003880        b.eq    860 <forth>
 850  154:   54000001        b.ne    154 <back+0x154>
 851  158:   54fff541        b.ne    0 <back>
 852  15c:   54003821        b.ne    860 <forth>
 853  160:   54000002        b.cs    160 <back+0x160>
 854  164:   54fff4e2        b.cs    0 <back>
 855  168:   540037c2        b.cs    860 <forth>
 856  16c:   54000002        b.cs    16c <back+0x16c>
 857  170:   54fff482        b.cs    0 <back>
 858  174:   54003762        b.cs    860 <forth>
 859  178:   54000003        b.cc    178 <back+0x178>
 860  17c:   54fff423        b.cc    0 <back>
 861  180:   54003703        b.cc    860 <forth>
 862  184:   54000003        b.cc    184 <back+0x184>
 863  188:   54fff3c3        b.cc    0 <back>
 864  18c:   540036a3        b.cc    860 <forth>
 865  190:   54000004        b.mi    190 <back+0x190>
 866  194:   54fff364        b.mi    0 <back>
 867  198:   54003644        b.mi    860 <forth>
 868  19c:   54000005        b.pl    19c <back+0x19c>
 869  1a0:   54fff305        b.pl    0 <back>
 870  1a4:   540035e5        b.pl    860 <forth>
 871  1a8:   54000006        b.vs    1a8 <back+0x1a8>
 872  1ac:   54fff2a6        b.vs    0 <back>
 873  1b0:   54003586        b.vs    860 <forth>
 874  1b4:   54000007        b.vc    1b4 <back+0x1b4>
 875  1b8:   54fff247        b.vc    0 <back>
 876  1bc:   54003527        b.vc    860 <forth>
 877  1c0:   54000008        b.hi    1c0 <back+0x1c0>
 878  1c4:   54fff1e8        b.hi    0 <back>
 879  1c8:   540034c8        b.hi    860 <forth>
 880  1cc:   54000009        b.ls    1cc <back+0x1cc>
 881  1d0:   54fff189        b.ls    0 <back>
 882  1d4:   54003469        b.ls    860 <forth>
 883  1d8:   5400000a        b.ge    1d8 <back+0x1d8>
 884  1dc:   54fff12a        b.ge    0 <back>
 885  1e0:   5400340a        b.ge    860 <forth>
 886  1e4:   5400000b        b.lt    1e4 <back+0x1e4>
 887  1e8:   54fff0cb        b.lt    0 <back>
 888  1ec:   540033ab        b.lt    860 <forth>
 889  1f0:   5400000c        b.gt    1f0 <back+0x1f0>
 890  1f4:   54fff06c        b.gt    0 <back>
 891  1f8:   5400334c        b.gt    860 <forth>
 892  1fc:   5400000d        b.le    1fc <back+0x1fc>
 893  200:   54fff00d        b.le    0 <back>
 894  204:   540032ed        b.le    860 <forth>
 895  208:   5400000e        b.al    208 <back+0x208>
 896  20c:   54ffefae        b.al    0 <back>
 897  210:   5400328e        b.al    860 <forth>
 898  214:   5400000f        b.nv    214 <back+0x214>
 899  218:   54ffef4f        b.nv    0 <back>
 900  21c:   5400322f        b.nv    860 <forth>
 901  220:   d4079461        svc     #0x3ca3
 902  224:   d4018ee2        hvc     #0xc77
 903  228:   d408d7c3        smc     #0x46be
 904  22c:   d4216040        brk     #0xb02
 905  230:   d44a2f80        hlt     #0x517c
 906  234:   d503201f        nop
 907  238:   d69f03e0        eret
 908  23c:   d6bf03e0        drps
 909  240:   d5033fdf        isb
 910  244:   d503329f        dsb     oshst
 911  248:   d50339bf        dmb     ishld
 912  24c:   d61f0140        br      x10
 913  250:   d63f02c0        blr     x22
 914  254:   c8037cb5        stxr    w3, x21, [x5]
 915  258:   c81cffa9        stlxr   w28, x9, [x29]
 916  25c:   c85f7cfc        ldxr    x28, [x7]
 917  260:   c85ffeea        ldaxr   x10, [x23]
 918  264:   c89fff47        stlr    x7, [x26]
 919  268:   c8dffef0        ldar    x16, [x23]
 920  26c:   880b7d87        stxr    w11, w7, [x12]
 921  270:   8810ff4d        stlxr   w16, w13, [x26]
 922  274:   885f7eb9        ldxr    w25, [x21]
 923  278:   885ffc8e        ldaxr   w14, [x4]
 924  27c:   889ffd3a        stlr    w26, [x9]
 925  280:   88dffee0        ldar    w0, [x23]
 926  284:   48087d40        stxrh   w8, w0, [x10]
 927  288:   480bfc81        stlxrh  w11, w1, [x4]
 928  28c:   485f7f4e        ldxrh   w14, [x26]
 929  290:   485ffcf3        ldaxrh  w19, [x7]
 930  294:   489ffed1        stlrh   w17, [x22]
 931  298:   48dffcd4        ldarh   w20, [x6]
 932  29c:   08197cc8        stxrb   w25, w8, [x6]
 933  2a0:   0805ff2a        stlxrb  w5, w10, [x25]
 934  2a4:   085f7ec0        ldxrb   w0, [x22]
 935  2a8:   085ffc68        ldaxrb  w8, [x3]
 936  2ac:   089ffc45        stlrb   w5, [x2]
 937  2b0:   08dfff86        ldarb   w6, [x28]
 938  2b4:   c87f21d1        ldxp    x17, x8, [x14]
 939  2b8:   c87f8c4e        ldaxp   x14, x3, [x2]
 940  2bc:   c8391271        stxp    w25, x17, x4, [x19]
 941  2c0:   c82abd10        stlxp   w10, x16, x15, [x8]
 942  2c4:   887f2c61        ldxp    w1, w11, [x3]
 943  2c8:   887fed80        ldaxp   w0, w27, [x12]
 944  2cc:   882457b4        stxp    w4, w20, w21, [x29]
 945  2d0:   882097a9        stlxp   w0, w9, w5, [x29]
 946  2d4:   f811d091        stur    x17, [x4,#-227]
 947  2d8:   b81df086        stur    w6, [x4,#-33]
 948  2dc:   39002e0d        strb    w13, [x16,#11]
 949  2e0:   781c02d7        sturh   w23, [x22,#-64]
 950  2e4:   f840d062        ldur    x2, [x3,#13]
 951  2e8:   b8423285        ldur    w5, [x20,#35]
 952  2ec:   385f1142        ldurb   w2, [x10,#-15]
 953  2f0:   785f8017        ldurh   w23, [x0,#-8]
 954  2f4:   389fd1cf        ldursb  x15, [x14,#-3]
 955  2f8:   789f4063        ldursh  x3, [x3,#-12]
 956  2fc:   78df9319        ldursh  w25, [x24,#-7]
 957  300:   b89e3011        ldursw  x17, [x0,#-29]
 958  304:   fc5b1127        ldur    d7, [x9,#-79]
 959  308:   bc5bc16b        ldur    s11, [x11,#-68]
 960  30c:   fc189050        stur    d16, [x2,#-119]
 961  310:   bc184399        stur    s25, [x28,#-124]
 962  314:   f8052e7c        str     x28, [x19,#82]!
 963  318:   b8032da7        str     w7, [x13,#50]!
 964  31c:   381e0e62        strb    w2, [x19,#-32]!
 965  320:   781c6c38        strh    w24, [x1,#-58]!
 966  324:   f8571fb7        ldr     x23, [x29,#-143]!
 967  328:   b8400f6d        ldr     w13, [x27,#0]!
 968  32c:   385e6d4b        ldrb    w11, [x10,#-26]!
 969  330:   785cacc3        ldrh    w3, [x6,#-54]!
 970  334:   38803d22        ldrsb   x2, [x9,#3]!
 971  338:   7881ec9c        ldrsh   x28, [x4,#30]!
 972  33c:   78de9c11        ldrsh   w17, [x0,#-23]!
 973  340:   b898bf3d        ldrsw   x29, [x25,#-117]!
 974  344:   fc572d55        ldr     d21, [x10,#-142]!
 975  348:   bc423e8b        ldr     s11, [x20,#35]!
 976  34c:   fc12ade1        str     d1, [x15,#-214]!
 977  350:   bc1c9cb3        str     s19, [x5,#-55]!
 978  354:   f81ec63c        str     x28, [x17],#-20
 979  358:   b81f75a8        str     w8, [x13],#-9
 980  35c:   381e970e        strb    w14, [x24],#-23
 981  360:   781c4482        strh    w2, [x4],#-60
 982  364:   f8422738        ldr     x24, [x25],#34
 983  368:   b85e5790        ldr     w16, [x28],#-27
 984  36c:   385e56e8        ldrb    w8, [x23],#-27
 985  370:   785c6403        ldrh    w3, [x0],#-58
 986  374:   389f65ee        ldrsb   x14, [x15],#-10
 987  378:   7880d42c        ldrsh   x12, [x1],#13
 988  37c:   78ded429        ldrsh   w9, [x1],#-19
 989  380:   b89c355d        ldrsw   x29, [x10],#-61
 990  384:   fc5f778d        ldr     d13, [x28],#-9
 991  388:   bc5a8774        ldr     s20, [x27],#-88
 992  38c:   fc139567        str     d7, [x11],#-199
 993  390:   bc1c36d4        str     s20, [x22],#-61
 994  394:   f830c943        str     x3, [x10,w16,sxtw]
 995  398:   b8357ba1        str     w1, [x29,x21,lsl #2]
 996  39c:   3837581a        strb    w26, [x0,w23,uxtw #0]
 997  3a0:   7835681a        strh    w26, [x0,x21]
 998  3a4:   f8766b23        ldr     x3, [x25,x22]
 999  3a8:   b8785939        ldr     w25, [x9,w24,uxtw #2]
1000  3ac:   386ed80a        ldrb    w10, [x0,w14,sxtw #0]
1001  3b0:   78747aa2        ldrh    w2, [x21,x20,lsl #1]
1002  3b4:   38bcfb73        ldrsb   x19, [x27,x28,sxtx #0]
1003  3b8:   78a37901        ldrsh   x1, [x8,x3,lsl #1]
1004  3bc:   78f0e9f4        ldrsh   w20, [x15,x16,sxtx]
1005  3c0:   b8ac78e7        ldrsw   x7, [x7,x12,lsl #2]
1006  3c4:   fc6dd88f        ldr     d15, [x4,w13,sxtw #3]
1007  3c8:   bc63494e        ldr     s14, [x10,w3,uxtw]
1008  3cc:   fc29faf8        str     d24, [x23,x9,sxtx #3]
1009  3d0:   bc3a5989        str     s9, [x12,w26,uxtw #2]
1010  3d4:   f91a530e        str     x14, [x24,#13472]
1011  3d8:   b91ce1c0        str     w0, [x14,#7392]
1012  3dc:   39180277        strb    w23, [x19,#1536]
1013  3e0:   791c316f        strh    w15, [x11,#3608]
1014  3e4:   f95ab735        ldr     x21, [x25,#13672]
1015  3e8:   b95810f7        ldr     w23, [x7,#6160]
1016  3ec:   395ede17        ldrb    w23, [x16,#1975]
1017  3f0:   795e1718        ldrh    w24, [x24,#3850]
1018  3f4:   3999352c        ldrsb   x12, [x9,#1613]
1019  3f8:   799e02a5        ldrsh   x5, [x21,#3840]
1020  3fc:   79dc0c0e        ldrsh   w14, [x0,#3590]
1021  400:   b99ef84d        ldrsw   x13, [x2,#7928]
1022  404:   fd5ede6f        ldr     d15, [x19,#15800]
1023  408:   bd5880b7        ldr     s23, [x5,#6272]
1024  40c:   fd1d90c6        str     d6, [x6,#15136]
1025  410:   bd182569        str     s9, [x11,#6180]
1026  414:   58002267        ldr     x7, 860 <forth>
1027  418:   1800001d        ldr     w29, 418 <back+0x418>
1028  41c:   f8929000        prfum   pldl1keep, [x0,#-215]
1029  420:   d8002200        prfm    pldl1keep, 860 <forth>
1030  424:   f8a34880        prfm    pldl1keep, [x4,w3,uxtw]
1031  428:   f99825c0        prfm    pldl1keep, [x14,#12360]
1032  42c:   1a0400c7        adc     w7, w6, w4
1033  430:   3a05019b        adcs    w27, w12, w5
1034  434:   5a1a0319        sbc     w25, w24, w26
1035  438:   7a1700e5        sbcs    w5, w7, w23
1036  43c:   9a010176        adc     x22, x11, x1
1037  440:   ba1d012d        adcs    x13, x9, x29
1038  444:   da1a01c4        sbc     x4, x14, x26
1039  448:   fa1803bc        sbcs    x28, x29, x24
1040  44c:   0b3546b1        add     w17, w21, w21, uxtw #1
1041  450:   2b3aad2c        adds    w12, w9, w26, sxth #3
1042  454:   cb2324ae        sub     x14, x5, w3, uxth #1
1043  458:   6b267351        subs    w17, w26, w6, uxtx #4
1044  45c:   8b34acb1        add     x17, x5, w20, sxth #3
1045  460:   ab39cc30        adds    x16, x1, w25, sxtw #3
1046  464:   cb3aec39        sub     x25, x1, x26, sxtx #3
1047  468:   eb37ac33        subs    x19, x1, w23, sxth #3
1048  46c:   3a589029        ccmn    w1, w24, #0x9, ls
1049  470:   7a4ac1c4        ccmp    w14, w10, #0x4, gt
1050  474:   ba5d3120        ccmn    x9, x29, #0x0, cc
1051  478:   fa4640cd        ccmp    x6, x6, #0xd, mi
1052  47c:   3a4b1a65        ccmn    w19, #0xb, #0x5, ne
1053  480:   7a5fa96f        ccmp    w11, #0x1f, #0xf, ge
1054  484:   ba4e6985        ccmn    x12, #0xe, #0x5, vs
1055  488:   fa47482a        ccmp    x1, #0x7, #0xa, mi
1056  48c:   1a963046        csel    w6, w2, w22, cc
1057  490:   1a9a66dd        csinc   w29, w22, w26, vs
1058  494:   5a8b933a        csinv   w26, w25, w11, ls
1059  498:   5a90c5d3        csneg   w19, w14, w16, gt
1060  49c:   9a9422ad        csel    x13, x21, x20, cs
1061  4a0:   9a9b856c        csinc   x12, x11, x27, hi
1062  4a4:   da93d223        csinv   x3, x17, x19, le
1063  4a8:   da876438        csneg   x24, x1, x7, vs
1064  4ac:   5ac00037        rbit    w23, w1
1065  4b0:   5ac00610        rev16   w16, w16
1066  4b4:   5ac00b38        rev     w24, w25
1067  4b8:   5ac01119        clz     w25, w8
1068  4bc:   5ac0159b        cls     w27, w12
1069  4c0:   dac000b5        rbit    x21, x5
1070  4c4:   dac00534        rev16   x20, x9
1071  4c8:   dac00934        rev32   x20, x9
1072  4cc:   dac00d53        rev     x19, x10
1073  4d0:   dac01048        clz     x8, x2
1074  4d4:   dac0147d        cls     x29, x3
1075  4d8:   1add08f3        udiv    w19, w7, w29
1076  4dc:   1aca0f7a        sdiv    w26, w27, w10
1077  4e0:   1ad02300        lsl     w0, w24, w16
1078  4e4:   1ad82556        lsr     w22, w10, w24
1079  4e8:   1ad02b40        asr     w0, w26, w16
1080  4ec:   1acf2f3b        ror     w27, w25, w15
1081  4f0:   9acf0b88        udiv    x8, x28, x15
1082  4f4:   9ac50d74        sdiv    x20, x11, x5
1083  4f8:   9ad02335        lsl     x21, x25, x16
1084  4fc:   9ace2447        lsr     x7, x2, x14
1085  500:   9ad62915        asr     x21, x8, x22
1086  504:   9acf2ca7        ror     x7, x5, x15
1087  508:   9bd67eac        umulh   x12, x21, x22
1088  50c:   9b457d50        smulh   x16, x10, x5
1089  510:   1b1a54c2        madd    w2, w6, w26, w21
1090  514:   1b03ee7b        msub    w27, w19, w3, w27
1091  518:   9b080cbb        madd    x27, x5, x8, x3
1092  51c:   9b1cb5a8        msub    x8, x13, x28, x13
1093  520:   9b28013d        smaddl  x29, w9, w8, x0
1094  524:   9b2edd2e        smsubl  x14, w9, w14, x23
1095  528:   9bab348f        umaddl  x15, w4, w11, x13
1096  52c:   9bb1e077        umsubl  x23, w3, w17, x24
1097  530:   1e31083d        fmul    s29, s1, s17
1098  534:   1e291b97        fdiv    s23, s28, s9
1099  538:   1e2c2a6e        fadd    s14, s19, s12
1100  53c:   1e203a3b        fsub    s27, s17, s0
1101  540:   1e260b10        fmul    s16, s24, s6
1102  544:   1e6a0ae4        fmul    d4, d23, d10
1103  548:   1e77192b        fdiv    d11, d9, d23
1104  54c:   1e6729e7        fadd    d7, d15, d7
1105  550:   1e6c3abd        fsub    d29, d21, d12
1106  554:   1e69089b        fmul    d27, d4, d9
1107  558:   1f0b65db        fmadd   s27, s14, s11, s25
1108  55c:   1f0f8ecb        fmsub   s11, s22, s15, s3
1109  560:   1f38136a        fnmadd  s10, s27, s24, s4
1110  564:   1f2104c4        fnmadd  s4, s6, s1, s1
1111  568:   1f430b8d        fmadd   d13, d28, d3, d2
1112  56c:   1f47eb1a        fmsub   d26, d24, d7, d26
1113  570:   1f6c68b5        fnmadd  d21, d5, d12, d26
1114  574:   1f740e0b        fnmadd  d11, d16, d20, d3
1115  578:   1e204225        fmov    s5, s17
1116  57c:   1e20c127        fabs    s7, s9
1117  580:   1e214039        fneg    s25, s1
1118  584:   1e21c0d8        fsqrt   s24, s6
1119  588:   1e22c23b        fcvt    d27, s17
1120  58c:   1e604056        fmov    d22, d2
1121  590:   1e60c28e        fabs    d14, d20
1122  594:   1e61417d        fneg    d29, d11
1123  598:   1e61c19c        fsqrt   d28, d12
1124  59c:   1e624064        fcvt    s4, d3
1125  5a0:   1e3801bc        fcvtzs  w28, s13
1126  5a4:   9e380387        fcvtzs  x7, s28
1127  5a8:   1e7801ec        fcvtzs  w12, d15
1128  5ac:   9e7800cb        fcvtzs  x11, d6
1129  5b0:   1e2202d6        scvtf   s22, w22
1130  5b4:   9e220205        scvtf   s5, x16
1131  5b8:   1e6201e3        scvtf   d3, w15
1132  5bc:   9e620106        scvtf   d6, x8
1133  5c0:   1e2603ba        fmov    w26, s29
1134  5c4:   9e660238        fmov    x24, d17
1135  5c8:   1e270262        fmov    s2, w19
1136  5cc:   9e6700b5        fmov    d21, x5
1137  5d0:   1e2822e0        fcmp    s23, s8
1138  5d4:   1e622180        fcmp    d12, d2
1139  5d8:   1e2021c8        fcmp    s14, #0.0
1140  5dc:   1e602148        fcmp    d10, #0.0
1141  5e0:   29344588        stp     w8, w17, [x12,#-96]
1142  5e4:   29685781        ldp     w1, w21, [x28,#-192]
1143  5e8:   69785a19        ldpsw   x25, x22, [x16,#-64]
1144  5ec:   a93822e6        stp     x6, x8, [x23,#-128]
1145  5f0:   a9794279        ldp     x25, x16, [x19,#-112]
1146  5f4:   29a26dbd        stp     w29, w27, [x13,#-240]!
1147  5f8:   29fc52ac        ldp     w12, w20, [x21,#-32]!
1148  5fc:   69ee3c80        ldpsw   x0, x15, [x4,#-144]!
1149  600:   a988326d        stp     x13, x12, [x19,#128]!
1150  604:   a9c60939        ldp     x25, x2, [x9,#96]!
1151  608:   2890074b        stp     w11, w1, [x26],#128
1152  60c:   28c4647a        ldp     w26, w25, [x3],#32
1153  610:   68e2384a        ldpsw   x10, x14, [x2],#-240
1154  614:   a8880d41        stp     x1, x3, [x10],#128
1155  618:   a8f73337        ldp     x23, x12, [x25],#-144
1156  61c:   28082325        stnp    w5, w8, [x25,#64]
1157  620:   28624ed4        ldnp    w20, w19, [x22,#-240]
1158  624:   a8351dd7        stnp    x23, x7, [x14,#-176]
1159  628:   a84472ae        ldnp    x14, x28, [x21,#64]
1160  62c:   0c40708a        ld1     {v10.8b}, [x4]
1161  630:   4cdfa359        ld1     {v25.16b, v26.16b}, [x26], #32
1162  634:   0cd76c9b        ld1     {v27.1d-v29.1d}, [x4], x23
1163  638:   4cdf24d0        ld1     {v16.8h-v19.8h}, [x6], #64
1164  63c:   0d40c361        ld1r    {v1.8b}, [x27]
1165  640:   4ddfc844        ld1r    {v4.4s}, [x2], #4
1166  644:   0dcfcfb5        ld1r    {v21.1d}, [x29], x15
1167  648:   4c408ec1        ld2     {v1.2d, v2.2d}, [x22]
1168  64c:   0cdf851d        ld2     {v29.4h, v30.4h}, [x8], #16
1169  650:   4d60c098        ld2r    {v24.16b, v25.16b}, [x4]
1170  654:   0dffca75        ld2r    {v21.2s, v22.2s}, [x19], #8
1171  658:   4de6cdad        ld2r    {v13.2d, v14.2d}, [x13], x6
1172  65c:   4cd14881        ld3     {v1.4s-v3.4s}, [x4], x17
1173  660:   0c404a36        ld3     {v22.2s-v24.2s}, [x17]
1174  664:   4d40e631        ld3r    {v17.8h-v19.8h}, [x17]
1175  668:   4ddfeb88        ld3r    {v8.4s-v10.4s}, [x28], #12
1176  66c:   0dd3ec25        ld3r    {v5.1d-v7.1d}, [x1], x19
1177  670:   4cdf05e1        ld4     {v1.8h-v4.8h}, [x15], #64
1178  674:   0cda00d1        ld4     {v17.8b-v20.8b}, [x6], x26
1179  678:   0d60e0f9        ld4r    {v25.8b-v28.8b}, [x7]
1180  67c:   0dffe50c        ld4r    {v12.4h-v15.4h}, [x8], #8
1181  680:   0de1e9a9        ld4r    {v9.2s-v12.2s}, [x13], x1
1182  684:   ba5fd3e3        ccmn    xzr, xzr, #0x3, le
1183  688:   3a5f03e5        ccmn    wzr, wzr, #0x5, eq
1184  68c:   fa411be4        ccmp    xzr, #0x1, #0x4, ne
1185  690:   7a42cbe2        ccmp    wzr, #0x2, #0x2, gt
1186  694:   93df03ff        ror     xzr, xzr, #0
1187  698:   c820ffff        stlxp   w0, xzr, xzr, [sp]
1188  69c:   8822fc7f        stlxp   w2, wzr, wzr, [x3]
1189  6a0:   c8247cbf        stxp    w4, xzr, xzr, [x5]
1190  6a4:   88267fff        stxp    w6, wzr, wzr, [sp]
1191  6a8:   4e010fe0        dup     v0.16b, wzr
1192  6ac:   4e081fe1        mov     v1.d[0], xzr
1193  6b0:   4e0c1fe1        mov     v1.s[1], wzr
1194  6b4:   4e0a1fe1        mov     v1.h[2], wzr
1195  6b8:   4e071fe1        mov     v1.b[3], wzr
1196  6bc:   4cc0ac3f        ld1     {v31.2d, v0.2d}, [x1], x0
1197  6c0:   1e601000        fmov    d0, #2.000000000000000000e+00
1198  6c4:   1e603000        fmov    d0, #2.125000000000000000e+00
1199  6c8:   1e621000        fmov    d0, #4.000000000000000000e+00
1200  6cc:   1e623000        fmov    d0, #4.250000000000000000e+00
1201  6d0:   1e641000        fmov    d0, #8.000000000000000000e+00
1202  6d4:   1e643000        fmov    d0, #8.500000000000000000e+00
1203  6d8:   1e661000        fmov    d0, #1.600000000000000000e+01
1204  6dc:   1e663000        fmov    d0, #1.700000000000000000e+01
1205  6e0:   1e681000        fmov    d0, #1.250000000000000000e-01
1206  6e4:   1e683000        fmov    d0, #1.328125000000000000e-01
1207  6e8:   1e6a1000        fmov    d0, #2.500000000000000000e-01
1208  6ec:   1e6a3000        fmov    d0, #2.656250000000000000e-01
1209  6f0:   1e6c1000        fmov    d0, #5.000000000000000000e-01
1210  6f4:   1e6c3000        fmov    d0, #5.312500000000000000e-01
1211  6f8:   1e6e1000        fmov    d0, #1.000000000000000000e+00
1212  6fc:   1e6e3000        fmov    d0, #1.062500000000000000e+00
1213  700:   1e701000        fmov    d0, #-2.000000000000000000e+00
1214  704:   1e703000        fmov    d0, #-2.125000000000000000e+00
1215  708:   1e721000        fmov    d0, #-4.000000000000000000e+00
1216  70c:   1e723000        fmov    d0, #-4.250000000000000000e+00
1217  710:   1e741000        fmov    d0, #-8.000000000000000000e+00
1218  714:   1e743000        fmov    d0, #-8.500000000000000000e+00
1219  718:   1e761000        fmov    d0, #-1.600000000000000000e+01
1220  71c:   1e763000        fmov    d0, #-1.700000000000000000e+01
1221  720:   1e781000        fmov    d0, #-1.250000000000000000e-01
1222  724:   1e783000        fmov    d0, #-1.328125000000000000e-01
1223  728:   1e7a1000        fmov    d0, #-2.500000000000000000e-01
1224  72c:   1e7a3000        fmov    d0, #-2.656250000000000000e-01
1225  730:   1e7c1000        fmov    d0, #-5.000000000000000000e-01
1226  734:   1e7c3000        fmov    d0, #-5.312500000000000000e-01
1227  738:   1e7e1000        fmov    d0, #-1.000000000000000000e+00
1228  73c:   1e7e3000        fmov    d0, #-1.062500000000000000e+00
1229  740:   f83a80c3        swp     x26, x3, [x6]
1230  744:   f834008c        ldadd   x20, x12, [x4]
1231  748:   f8371164        ldclr   x23, x4, [x11]
1232  74c:   f82f230f        ldeor   x15, x15, [x24]
1233  750:   f83d3222        ldset   x29, x2, [x17]
1234  754:   f8395025        ldsmin  x25, x5, [x1]
1235  758:   f82f40ef        ldsmax  x15, x15, [x7]
1236  75c:   f83c73bf        stumin  x28, [x29]
1237  760:   f83163f1        ldumax  x17, x17, [sp]
1238  764:   f8a782b0        swpa    x7, x16, [x21]
1239  768:   f8b1028a        ldadda  x17, x10, [x20]
1240  76c:   f8b913ae        ldclra  x25, x14, [x29]
1241  770:   f8b9206d        ldeora  x25, x13, [x3]
1242  774:   f8ad3387        ldseta  x13, x7, [x28]
1243  778:   f8b450f9        ldsmina x20, x25, [x7]
1244  77c:   f8b54044        ldsmaxa x21, x4, [x2]
1245  780:   f8a87105        ldumina x8, x5, [x8]
1246  784:   f8aa60cc        ldumaxa x10, x12, [x6]
1247  788:   f8f9814c        swpal   x25, x12, [x10]
1248  78c:   f8ec0081        ldaddal x12, x1, [x4]
1249  790:   f8fa1186        ldclral x26, x6, [x12]
1250  794:   f8e1218e        ldeoral x1, x14, [x12]
1251  798:   f8f632a6        ldsetal x22, x6, [x21]
1252  79c:   f8ef50c4        ldsminal        x15, x4, [x6]
1253  7a0:   f8f840f0        ldsmaxal        x24, x16, [x7]
1254  7a4:   f8e57163        lduminal        x5, x3, [x11]
1255  7a8:   f8f66322        ldumaxal        x22, x2, [x25]
1256  7ac:   f866801d        swpl    x6, x29, [x0]
1257  7b0:   f87a02e6        ldaddl  x26, x6, [x23]
1258  7b4:   f8641127        ldclrl  x4, x7, [x9]
1259  7b8:   f866202b        ldeorl  x6, x11, [x1]
1260  7bc:   f86b33ad        ldsetl  x11, x13, [x29]
1261  7c0:   f86b50c3        ldsminl x11, x3, [x6]
1262  7c4:   f8754160        ldsmaxl x21, x0, [x11]
1263  7c8:   f86b7137        lduminl x11, x23, [x9]
1264  7cc:   f8716210        ldumaxl x17, x16, [x16]
1265  7d0:   b83583e5        swp     w21, w5, [sp]
1266  7d4:   b838008b        ldadd   w24, w11, [x4]
1267  7d8:   b831109d        ldclr   w17, w29, [x4]
1268  7dc:   b82f21eb        ldeor   w15, w11, [x15]
1269  7e0:   b83b317a        ldset   w27, w26, [x11]
1270  7e4:   b83b510c        ldsmin  w27, w12, [x8]
1271  7e8:   b8264034        ldsmax  w6, w20, [x1]
1272  7ec:   b82e73b0        ldumin  w14, w16, [x29]
1273  7f0:   b838634d        ldumax  w24, w13, [x26]
1274  7f4:   b8a48162        swpa    w4, w2, [x11]
1275  7f8:   b8b4009d        ldadda  w20, w29, [x4]
1276  7fc:   b8b413bf        ldclra  w20, wzr, [x29]
1277  800:   b8a0232f        ldeora  w0, w15, [x25]
1278  804:   b8b73285        ldseta  w23, w5, [x20]
1279  808:   b8bd527a        ldsmina w29, w26, [x19]
1280  80c:   b8b542d4        ldsmaxa w21, w20, [x22]
1281  810:   b8ba7215        ldumina w26, w21, [x16]
1282  814:   b8a86155        ldumaxa w8, w21, [x10]
1283  818:   b8fb816b        swpal   w27, w11, [x11]
1284  81c:   b8e50388        ldaddal w5, w8, [x28]
1285  820:   b8e010a5        ldclral w0, w5, [x5]
1286  824:   b8e2230a        ldeoral w2, w10, [x24]
1287  828:   b8ed33ff        ldsetal w13, wzr, [sp]
1288  82c:   b8fa5319        ldsminal        w26, w25, [x24]
1289  830:   b8e840c5        ldsmaxal        w8, w5, [x6]
1290  834:   b8e5737b        lduminal        w5, w27, [x27]
1291  838:   b8f762f4        ldumaxal        w23, w20, [x23]
1292  83c:   b8798383        swpl    w25, w3, [x28]
1293  840:   b86a01a8        ldaddl  w10, w8, [x13]
1294  844:   b87513eb        ldclrl  w21, w11, [sp]
1295  848:   b87f2383        ldeorl  wzr, w3, [x28]
1296  84c:   b86f3300        ldsetl  w15, w0, [x24]
1297  850:   b86453a9        ldsminl w4, w9, [x29]
1298  854:   b86842a6        ldsmaxl w8, w6, [x21]
1299  858:   b8697076        lduminl w9, w22, [x3]
1300  85c:   b87a638a        ldumaxl w26, w10, [x28]
1301  */
1302 
1303   static const unsigned int insns[] =
1304   {
1305     0x8b1ad014,     0xcb83db85,     0xab839ecb,     0xeb4c646b,
1306     0x0b0d399b,     0x4b9b1eaa,     0x2b1011c3,     0x6b1d1661,
1307     0x8a5b1a30,     0xaa1c8f96,     0xca5ccd4b,     0xea8ec10d,
1308     0x0a410c61,     0x2a855909,     0x4a9b4f82,     0x6a073938,
1309     0x8ab9826b,     0xaa3d7318,     0xcab16e0b,     0xea6ae9a5,
1310     0x0a357545,     0x2a354d64,     0x4a7c3f95,     0x6a2e7146,
1311     0x110ec6ca,     0x310e9d6f,     0x510afcc5,     0x7108e013,
1312     0x91098114,     0xb10434d0,     0xd10db417,     0xf10c873a,
1313     0x120d6a0c,     0x32066b01,     0x52112073,     0x720a553d,
1314     0x9263d0ba,     0xb20da1d8,     0xd26ec404,     0xf26e28dc,
1315     0x14000000,     0x17ffffd7,     0x140001ee,     0x94000000,
1316     0x97ffffd4,     0x940001eb,     0x34000015,     0x34fffa35,
1317     0x34003d15,     0x3500000c,     0x35fff9cc,     0x35003cac,
1318     0xb400000e,     0xb4fff96e,     0xb4003c4e,     0xb500001b,
1319     0xb5fff91b,     0xb5003bfb,     0x1000000e,     0x10fff8ae,
1320     0x10003b8e,     0x90000016,     0x36280000,     0x362ff820,
1321     0x36283b00,     0x37580003,     0x375ff7c3,     0x37583aa3,
1322     0x12835753,     0x52a2da7c,     0x72a9ef0d,     0x92c097e1,
1323     0xd28e0a7a,     0xf2e2d05b,     0x93496301,     0x33054019,
1324     0x530f1f70,     0x934f71d0,     0xb3403558,     0xd34259c1,
1325     0x1381540a,     0x93d7f75a,     0x54000000,     0x54fff5a0,
1326     0x54003880,     0x54000001,     0x54fff541,     0x54003821,
1327     0x54000002,     0x54fff4e2,     0x540037c2,     0x54000002,
1328     0x54fff482,     0x54003762,     0x54000003,     0x54fff423,
1329     0x54003703,     0x54000003,     0x54fff3c3,     0x540036a3,
1330     0x54000004,     0x54fff364,     0x54003644,     0x54000005,
1331     0x54fff305,     0x540035e5,     0x54000006,     0x54fff2a6,
1332     0x54003586,     0x54000007,     0x54fff247,     0x54003527,
1333     0x54000008,     0x54fff1e8,     0x540034c8,     0x54000009,
1334     0x54fff189,     0x54003469,     0x5400000a,     0x54fff12a,
1335     0x5400340a,     0x5400000b,     0x54fff0cb,     0x540033ab,
1336     0x5400000c,     0x54fff06c,     0x5400334c,     0x5400000d,
1337     0x54fff00d,     0x540032ed,     0x5400000e,     0x54ffefae,
1338     0x5400328e,     0x5400000f,     0x54ffef4f,     0x5400322f,
1339     0xd4079461,     0xd4018ee2,     0xd408d7c3,     0xd4216040,
1340     0xd44a2f80,     0xd503201f,     0xd69f03e0,     0xd6bf03e0,
1341     0xd5033fdf,     0xd503329f,     0xd50339bf,     0xd61f0140,
1342     0xd63f02c0,     0xc8037cb5,     0xc81cffa9,     0xc85f7cfc,
1343     0xc85ffeea,     0xc89fff47,     0xc8dffef0,     0x880b7d87,
1344     0x8810ff4d,     0x885f7eb9,     0x885ffc8e,     0x889ffd3a,
1345     0x88dffee0,     0x48087d40,     0x480bfc81,     0x485f7f4e,
1346     0x485ffcf3,     0x489ffed1,     0x48dffcd4,     0x08197cc8,
1347     0x0805ff2a,     0x085f7ec0,     0x085ffc68,     0x089ffc45,
1348     0x08dfff86,     0xc87f21d1,     0xc87f8c4e,     0xc8391271,
1349     0xc82abd10,     0x887f2c61,     0x887fed80,     0x882457b4,
1350     0x882097a9,     0xf811d091,     0xb81df086,     0x39002e0d,
1351     0x781c02d7,     0xf840d062,     0xb8423285,     0x385f1142,
1352     0x785f8017,     0x389fd1cf,     0x789f4063,     0x78df9319,
1353     0xb89e3011,     0xfc5b1127,     0xbc5bc16b,     0xfc189050,
1354     0xbc184399,     0xf8052e7c,     0xb8032da7,     0x381e0e62,
1355     0x781c6c38,     0xf8571fb7,     0xb8400f6d,     0x385e6d4b,
1356     0x785cacc3,     0x38803d22,     0x7881ec9c,     0x78de9c11,
1357     0xb898bf3d,     0xfc572d55,     0xbc423e8b,     0xfc12ade1,
1358     0xbc1c9cb3,     0xf81ec63c,     0xb81f75a8,     0x381e970e,
1359     0x781c4482,     0xf8422738,     0xb85e5790,     0x385e56e8,
1360     0x785c6403,     0x389f65ee,     0x7880d42c,     0x78ded429,
1361     0xb89c355d,     0xfc5f778d,     0xbc5a8774,     0xfc139567,
1362     0xbc1c36d4,     0xf830c943,     0xb8357ba1,     0x3837581a,
1363     0x7835681a,     0xf8766b23,     0xb8785939,     0x386ed80a,
1364     0x78747aa2,     0x38bcfb73,     0x78a37901,     0x78f0e9f4,
1365     0xb8ac78e7,     0xfc6dd88f,     0xbc63494e,     0xfc29faf8,
1366     0xbc3a5989,     0xf91a530e,     0xb91ce1c0,     0x39180277,
1367     0x791c316f,     0xf95ab735,     0xb95810f7,     0x395ede17,
1368     0x795e1718,     0x3999352c,     0x799e02a5,     0x79dc0c0e,
1369     0xb99ef84d,     0xfd5ede6f,     0xbd5880b7,     0xfd1d90c6,
1370     0xbd182569,     0x58002267,     0x1800001d,     0xf8929000,
1371     0xd8002200,     0xf8a34880,     0xf99825c0,     0x1a0400c7,
1372     0x3a05019b,     0x5a1a0319,     0x7a1700e5,     0x9a010176,
1373     0xba1d012d,     0xda1a01c4,     0xfa1803bc,     0x0b3546b1,
1374     0x2b3aad2c,     0xcb2324ae,     0x6b267351,     0x8b34acb1,
1375     0xab39cc30,     0xcb3aec39,     0xeb37ac33,     0x3a589029,
1376     0x7a4ac1c4,     0xba5d3120,     0xfa4640cd,     0x3a4b1a65,
1377     0x7a5fa96f,     0xba4e6985,     0xfa47482a,     0x1a963046,
1378     0x1a9a66dd,     0x5a8b933a,     0x5a90c5d3,     0x9a9422ad,
1379     0x9a9b856c,     0xda93d223,     0xda876438,     0x5ac00037,
1380     0x5ac00610,     0x5ac00b38,     0x5ac01119,     0x5ac0159b,
1381     0xdac000b5,     0xdac00534,     0xdac00934,     0xdac00d53,
1382     0xdac01048,     0xdac0147d,     0x1add08f3,     0x1aca0f7a,
1383     0x1ad02300,     0x1ad82556,     0x1ad02b40,     0x1acf2f3b,
1384     0x9acf0b88,     0x9ac50d74,     0x9ad02335,     0x9ace2447,
1385     0x9ad62915,     0x9acf2ca7,     0x9bd67eac,     0x9b457d50,
1386     0x1b1a54c2,     0x1b03ee7b,     0x9b080cbb,     0x9b1cb5a8,
1387     0x9b28013d,     0x9b2edd2e,     0x9bab348f,     0x9bb1e077,
1388     0x1e31083d,     0x1e291b97,     0x1e2c2a6e,     0x1e203a3b,
1389     0x1e260b10,     0x1e6a0ae4,     0x1e77192b,     0x1e6729e7,
1390     0x1e6c3abd,     0x1e69089b,     0x1f0b65db,     0x1f0f8ecb,
1391     0x1f38136a,     0x1f2104c4,     0x1f430b8d,     0x1f47eb1a,
1392     0x1f6c68b5,     0x1f740e0b,     0x1e204225,     0x1e20c127,
1393     0x1e214039,     0x1e21c0d8,     0x1e22c23b,     0x1e604056,
1394     0x1e60c28e,     0x1e61417d,     0x1e61c19c,     0x1e624064,
1395     0x1e3801bc,     0x9e380387,     0x1e7801ec,     0x9e7800cb,
1396     0x1e2202d6,     0x9e220205,     0x1e6201e3,     0x9e620106,
1397     0x1e2603ba,     0x9e660238,     0x1e270262,     0x9e6700b5,
1398     0x1e2822e0,     0x1e622180,     0x1e2021c8,     0x1e602148,
1399     0x29344588,     0x29685781,     0x69785a19,     0xa93822e6,
1400     0xa9794279,     0x29a26dbd,     0x29fc52ac,     0x69ee3c80,
1401     0xa988326d,     0xa9c60939,     0x2890074b,     0x28c4647a,
1402     0x68e2384a,     0xa8880d41,     0xa8f73337,     0x28082325,
1403     0x28624ed4,     0xa8351dd7,     0xa84472ae,     0x0c40708a,
1404     0x4cdfa359,     0x0cd76c9b,     0x4cdf24d0,     0x0d40c361,
1405     0x4ddfc844,     0x0dcfcfb5,     0x4c408ec1,     0x0cdf851d,
1406     0x4d60c098,     0x0dffca75,     0x4de6cdad,     0x4cd14881,
1407     0x0c404a36,     0x4d40e631,     0x4ddfeb88,     0x0dd3ec25,
1408     0x4cdf05e1,     0x0cda00d1,     0x0d60e0f9,     0x0dffe50c,
1409     0x0de1e9a9,     0xba5fd3e3,     0x3a5f03e5,     0xfa411be4,
1410     0x7a42cbe2,     0x93df03ff,     0xc820ffff,     0x8822fc7f,
1411     0xc8247cbf,     0x88267fff,     0x4e010fe0,     0x4e081fe1,
1412     0x4e0c1fe1,     0x4e0a1fe1,     0x4e071fe1,     0x4cc0ac3f,
1413     0x1e601000,     0x1e603000,     0x1e621000,     0x1e623000,
1414     0x1e641000,     0x1e643000,     0x1e661000,     0x1e663000,
1415     0x1e681000,     0x1e683000,     0x1e6a1000,     0x1e6a3000,
1416     0x1e6c1000,     0x1e6c3000,     0x1e6e1000,     0x1e6e3000,
1417     0x1e701000,     0x1e703000,     0x1e721000,     0x1e723000,
1418     0x1e741000,     0x1e743000,     0x1e761000,     0x1e763000,
1419     0x1e781000,     0x1e783000,     0x1e7a1000,     0x1e7a3000,
1420     0x1e7c1000,     0x1e7c3000,     0x1e7e1000,     0x1e7e3000,
1421     0xf83a80c3,     0xf834008c,     0xf8371164,     0xf82f230f,
1422     0xf83d3222,     0xf8395025,     0xf82f40ef,     0xf83c73bf,
1423     0xf83163f1,     0xf8a782b0,     0xf8b1028a,     0xf8b913ae,
1424     0xf8b9206d,     0xf8ad3387,     0xf8b450f9,     0xf8b54044,
1425     0xf8a87105,     0xf8aa60cc,     0xf8f9814c,     0xf8ec0081,
1426     0xf8fa1186,     0xf8e1218e,     0xf8f632a6,     0xf8ef50c4,
1427     0xf8f840f0,     0xf8e57163,     0xf8f66322,     0xf866801d,
1428     0xf87a02e6,     0xf8641127,     0xf866202b,     0xf86b33ad,
1429     0xf86b50c3,     0xf8754160,     0xf86b7137,     0xf8716210,
1430     0xb83583e5,     0xb838008b,     0xb831109d,     0xb82f21eb,
1431     0xb83b317a,     0xb83b510c,     0xb8264034,     0xb82e73b0,
1432     0xb838634d,     0xb8a48162,     0xb8b4009d,     0xb8b413bf,
1433     0xb8a0232f,     0xb8b73285,     0xb8bd527a,     0xb8b542d4,
1434     0xb8ba7215,     0xb8a86155,     0xb8fb816b,     0xb8e50388,
1435     0xb8e010a5,     0xb8e2230a,     0xb8ed33ff,     0xb8fa5319,
1436     0xb8e840c5,     0xb8e5737b,     0xb8f762f4,     0xb8798383,
1437     0xb86a01a8,     0xb87513eb,     0xb87f2383,     0xb86f3300,
1438     0xb86453a9,     0xb86842a6,     0xb8697076,     0xb87a638a,
1439 
1440   };
1441 // END  Generated code -- do not edit
1442 
1443   asm_check((unsigned int *)entry, insns, sizeof insns / sizeof insns[0]);
1444 
1445   {
1446     address PC = __ pc();
1447     __ ld1(v0, __ T16B, Address(r16));      // No offset
1448     __ ld1(v0, __ T8H, __ post(r16, 16));   // Post-index
1449     __ ld2(v0, v1, __ T8H, __ post(r24, 16 * 2));   // Post-index
1450     __ ld1(v0, __ T16B, __ post(r16, r17)); // Register post-index
1451     static const unsigned int vector_insns[] = {
1452        0x4c407200, // ld1   {v0.16b}, [x16]
1453        0x4cdf7600, // ld1   {v0.8h}, [x16], #16
1454        0x4cdf8700, // ld2   {v0.8h, v1.8h}, [x24], #32
1455        0x4cd17200, // ld1   {v0.16b}, [x16], x17
1456       };
1457     asm_check((unsigned int *)PC, vector_insns,
1458               sizeof vector_insns / sizeof vector_insns[0]);
1459   }
1460 }
1461 #endif // ASSERT
1462 
1463 #undef __
1464 
1465 void Assembler::emit_data64(jlong data,
1466                             relocInfo::relocType rtype,
1467                             int format) {
1468   if (rtype == relocInfo::none) {
1469     emit_int64(data);
1470   } else {
1471     emit_data64(data, Relocation::spec_simple(rtype), format);
1472   }
1473 }
1474 
1475 void Assembler::emit_data64(jlong data,
1476                             RelocationHolder const& rspec,
1477                             int format) {
1478 
1479   assert(inst_mark() != NULL, "must be inside InstructionMark");
1480   // Do not use AbstractAssembler::relocate, which is not intended for
1481   // embedded words.  Instead, relocate to the enclosing instruction.
1482   code_section()->relocate(inst_mark(), rspec, format);
1483   emit_int64(data);
1484 }
1485 
1486 extern "C" {
1487   void das(uint64_t start, int len) {
1488     ResourceMark rm;
1489     len <<= 2;
1490     if (len < 0)
1491       Disassembler::decode((address)start + len, (address)start);
1492     else
1493       Disassembler::decode((address)start, (address)start + len);
1494   }
1495 
1496   JNIEXPORT void das1(uintptr_t insn) {
1497     das(insn, 1);
1498   }
1499 }
1500 
1501 #define gas_assert(ARG1) assert(ARG1, #ARG1)
1502 
1503 #define __ as->
1504 
1505 void Address::lea(MacroAssembler *as, Register r) const {
1506   Relocation* reloc = _rspec.reloc();
1507   relocInfo::relocType rtype = (relocInfo::relocType) reloc->type();
1508 
1509   switch(_mode) {
1510   case base_plus_offset: {
1511     if (_offset == 0 && _base == r) // it's a nop
1512       break;
1513     if (_offset > 0)
1514       __ add(r, _base, _offset);
1515     else
1516       __ sub(r, _base, -_offset);
1517       break;
1518   }
1519   case base_plus_offset_reg: {
1520     __ add(r, _base, _index, _ext.op(), MAX2(_ext.shift(), 0));
1521     break;
1522   }
1523   case literal: {
1524     if (rtype == relocInfo::none)
1525       __ mov(r, target());
1526     else
1527       __ movptr(r, (uint64_t)target());
1528     break;
1529   }
1530   default:
1531     ShouldNotReachHere();
1532   }
1533 }
1534 
1535 void Assembler::adrp(Register reg1, const Address &dest, uintptr_t &byte_offset) {
1536   ShouldNotReachHere();
1537 }
1538 
1539 #undef __
1540 
1541 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
1542 
1543   void Assembler::adr(Register Rd, address adr) {
1544     intptr_t offset = adr - pc();
1545     int offset_lo = offset & 3;
1546     offset >>= 2;
1547     starti;
1548     f(0, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1549     rf(Rd, 0);
1550   }
1551 
1552   void Assembler::_adrp(Register Rd, address adr) {
1553     uint64_t pc_page = (uint64_t)pc() >> 12;
1554     uint64_t adr_page = (uint64_t)adr >> 12;
1555     intptr_t offset = adr_page - pc_page;
1556     int offset_lo = offset & 3;
1557     offset >>= 2;
1558     starti;
1559     f(1, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1560     rf(Rd, 0);
1561   }
1562 
1563 #undef starti
1564 
1565 Address::Address(address target, relocInfo::relocType rtype) : _mode(literal){
1566   _is_lval = false;
1567   _target = target;
1568   switch (rtype) {
1569   case relocInfo::oop_type:
1570   case relocInfo::metadata_type:
1571     // Oops are a special case. Normally they would be their own section
1572     // but in cases like icBuffer they are literals in the code stream that
1573     // we don't have a section for. We use none so that we get a literal address
1574     // which is always patchable.
1575     break;
1576   case relocInfo::external_word_type:
1577     _rspec = external_word_Relocation::spec(target);
1578     break;
1579   case relocInfo::internal_word_type:
1580     _rspec = internal_word_Relocation::spec(target);
1581     break;
1582   case relocInfo::opt_virtual_call_type:
1583     _rspec = opt_virtual_call_Relocation::spec();
1584     break;
1585   case relocInfo::static_call_type:
1586     _rspec = static_call_Relocation::spec();
1587     break;
1588   case relocInfo::runtime_call_type:
1589     _rspec = runtime_call_Relocation::spec();
1590     break;
1591   case relocInfo::poll_type:
1592   case relocInfo::poll_return_type:
1593     _rspec = Relocation::spec_simple(rtype);
1594     break;
1595   case relocInfo::none:
1596     _rspec = RelocationHolder::none;
1597     break;
1598   default:
1599     ShouldNotReachHere();
1600     break;
1601   }
1602 }
1603 
1604 void Assembler::b(const Address &dest) {
1605   code_section()->relocate(pc(), dest.rspec());
1606   b(dest.target());
1607 }
1608 
1609 void Assembler::bl(const Address &dest) {
1610   code_section()->relocate(pc(), dest.rspec());
1611   bl(dest.target());
1612 }
1613 
1614 void Assembler::adr(Register r, const Address &dest) {
1615   code_section()->relocate(pc(), dest.rspec());
1616   adr(r, dest.target());
1617 }
1618 
1619 void Assembler::br(Condition cc, Label &L) {
1620   if (L.is_bound()) {
1621     br(cc, target(L));
1622   } else {
1623     L.add_patch_at(code(), locator());
1624     br(cc, pc());
1625   }
1626 }
1627 
1628 void Assembler::wrap_label(Label &L,
1629                                  Assembler::uncond_branch_insn insn) {
1630   if (L.is_bound()) {
1631     (this->*insn)(target(L));
1632   } else {
1633     L.add_patch_at(code(), locator());
1634     (this->*insn)(pc());
1635   }
1636 }
1637 
1638 void Assembler::wrap_label(Register r, Label &L,
1639                                  compare_and_branch_insn insn) {
1640   if (L.is_bound()) {
1641     (this->*insn)(r, target(L));
1642   } else {
1643     L.add_patch_at(code(), locator());
1644     (this->*insn)(r, pc());
1645   }
1646 }
1647 
1648 void Assembler::wrap_label(Register r, int bitpos, Label &L,
1649                                  test_and_branch_insn insn) {
1650   if (L.is_bound()) {
1651     (this->*insn)(r, bitpos, target(L));
1652   } else {
1653     L.add_patch_at(code(), locator());
1654     (this->*insn)(r, bitpos, pc());
1655   }
1656 }
1657 
1658 void Assembler::wrap_label(Label &L, prfop op, prefetch_insn insn) {
1659   if (L.is_bound()) {
1660     (this->*insn)(target(L), op);
1661   } else {
1662     L.add_patch_at(code(), locator());
1663     (this->*insn)(pc(), op);
1664   }
1665 }
1666 
1667 // An "all-purpose" add/subtract immediate, per ARM documentation:
1668 // A "programmer-friendly" assembler may accept a negative immediate
1669 // between -(2^24 -1) and -1 inclusive, causing it to convert a
1670 // requested ADD operation to a SUB, or vice versa, and then encode
1671 // the absolute value of the immediate as for uimm24.
1672 void Assembler::add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
1673                                   int negated_op) {
1674   bool sets_flags = op & 1;   // this op sets flags
1675   union {
1676     unsigned u;
1677     int imm;
1678   };
1679   u = uimm;
1680   bool shift = false;
1681   bool neg = imm < 0;
1682   if (neg) {
1683     imm = -imm;
1684     op = negated_op;
1685   }
1686   assert(Rd != sp || imm % 16 == 0, "misaligned stack");
1687   if (imm >= (1 << 11)
1688       && ((imm >> 12) << 12 == imm)) {
1689     imm >>= 12;
1690     shift = true;
1691   }
1692   f(op, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10);
1693 
1694   // add/subtract immediate ops with the S bit set treat r31 as zr;
1695   // with S unset they use sp.
1696   if (sets_flags)
1697     zrf(Rd, 0);
1698   else
1699     srf(Rd, 0);
1700 
1701   srf(Rn, 5);
1702 }
1703 
1704 bool Assembler::operand_valid_for_add_sub_immediate(int64_t imm) {
1705   bool shift = false;
1706   uint64_t uimm = (uint64_t)uabs(imm);
1707   if (uimm < (1 << 12))
1708     return true;
1709   if (uimm < (1 << 24)
1710       && ((uimm >> 12) << 12 == uimm)) {
1711     return true;
1712   }
1713   return false;
1714 }
1715 
1716 bool Assembler::operand_valid_for_logical_immediate(bool is32, uint64_t imm) {
1717   return encode_logical_immediate(is32, imm) != 0xffffffff;
1718 }
1719 
1720 static uint64_t doubleTo64Bits(jdouble d) {
1721   union {
1722     jdouble double_value;
1723     uint64_t double_bits;
1724   };
1725 
1726   double_value = d;
1727   return double_bits;
1728 }
1729 
1730 bool Assembler::operand_valid_for_float_immediate(double imm) {
1731   // If imm is all zero bits we can use ZR as the source of a
1732   // floating-point value.
1733   if (doubleTo64Bits(imm) == 0)
1734     return true;
1735 
1736   // Otherwise try to encode imm then convert the encoded value back
1737   // and make sure it's the exact same bit pattern.
1738   unsigned result = encoding_for_fp_immediate(imm);
1739   return doubleTo64Bits(imm) == fp_immediate_for_encoding(result, true);
1740 }
1741 
1742 int AbstractAssembler::code_fill_byte() {
1743   return 0;
1744 }
1745 
1746 // n.b. this is implemented in subclass MacroAssembler
1747 void Assembler::bang_stack_with_offset(int offset) { Unimplemented(); }
1748 
1749 
1750 // and now the routines called by the assembler which encapsulate the
1751 // above encode and decode functions
1752 
1753 uint32_t
1754 asm_util::encode_logical_immediate(bool is32, uint64_t imm)
1755 {
1756   if (is32) {
1757     /* Allow all zeros or all ones in top 32-bits, so that
1758        constant expressions like ~1 are permitted. */
1759     if (imm >> 32 != 0 && imm >> 32 != 0xffffffff)
1760       return 0xffffffff;
1761     /* Replicate the 32 lower bits to the 32 upper bits.  */
1762     imm &= 0xffffffff;
1763     imm |= imm << 32;
1764   }
1765 
1766   return encoding_for_logical_immediate(imm);
1767 }
1768 
1769 unsigned Assembler::pack(double value) {
1770   float val = (float)value;
1771   unsigned result = encoding_for_fp_immediate(val);
1772   guarantee(unpack(result) == value,
1773             "Invalid floating-point immediate operand");
1774   return result;
1775 }
1776 
1777 // Packed operands for  Floating-point Move (immediate)
1778 
1779 static float unpack(unsigned value) {
1780   union {
1781     unsigned ival;
1782     float val;
1783   };
1784   ival = fp_immediate_for_encoding(value, 0);
1785   return val;
1786 }
1787 
1788 address Assembler::locate_next_instruction(address inst) {
1789   return inst + Assembler::instruction_size;
1790 }