12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_VERSION_AARCH64_HPP
27 #define CPU_AARCH64_VM_VERSION_AARCH64_HPP
28
29 #include "runtime/abstract_vm_version.hpp"
30 #include "runtime/globals_extension.hpp"
31 #include "utilities/sizes.hpp"
32
33 class VM_Version : public Abstract_VM_Version {
34 friend class JVMCIVMStructs;
35
36 protected:
37 static int _cpu;
38 static int _model;
39 static int _model2;
40 static int _variant;
41 static int _revision;
42 static int _stepping;
43 static bool _dcpop;
44 struct PsrInfo {
45 uint32_t dczid_el0;
46 uint32_t ctr_el0;
47 };
48 static PsrInfo _psr_info;
49 static void get_processor_features();
50
51 public:
52 // Initialization
53 static void initialize();
54
55 // Asserts
56 static void assert_is_initialized() {
57 }
58
59 static bool expensive_load(int ld_size, int scale) {
60 if (cpu_family() == CPU_ARM) {
61 // Half-word load with index shift by 1 (aka scale is 2) has
62 // extra cycle latency, e.g. ldrsh w0, [x1,w2,sxtw #1].
63 if (ld_size == 2 && scale == 2) {
64 return true;
65 }
66 }
79 CPU_HISILICON = 'H',
80 CPU_INFINEON = 'I',
81 CPU_MOTOROLA = 'M',
82 CPU_NVIDIA = 'N',
83 CPU_AMCC = 'P',
84 CPU_QUALCOM = 'Q',
85 CPU_MARVELL = 'V',
86 CPU_INTEL = 'i',
87 };
88
89 enum Feature_Flag {
90 CPU_FP = (1<<0),
91 CPU_ASIMD = (1<<1),
92 CPU_EVTSTRM = (1<<2),
93 CPU_AES = (1<<3),
94 CPU_PMULL = (1<<4),
95 CPU_SHA1 = (1<<5),
96 CPU_SHA2 = (1<<6),
97 CPU_CRC32 = (1<<7),
98 CPU_LSE = (1<<8),
99 CPU_STXR_PREFETCH= (1 << 29),
100 CPU_A53MAC = (1 << 30),
101 };
102
103 static int cpu_family() { return _cpu; }
104 static int cpu_model() { return _model; }
105 static int cpu_model2() { return _model2; }
106 static int cpu_variant() { return _variant; }
107 static int cpu_revision() { return _revision; }
108 static bool supports_dcpop() { return _dcpop; }
109 static ByteSize dczid_el0_offset() { return byte_offset_of(PsrInfo, dczid_el0); }
110 static ByteSize ctr_el0_offset() { return byte_offset_of(PsrInfo, ctr_el0); }
111 static bool is_zva_enabled() {
112 // Check the DZP bit (bit 4) of dczid_el0 is zero
113 // and block size (bit 0~3) is not zero.
114 return ((_psr_info.dczid_el0 & 0x10) == 0 &&
115 (_psr_info.dczid_el0 & 0xf) != 0);
116 }
117 static int zva_length() {
118 assert(is_zva_enabled(), "ZVA not available");
119 return 4 << (_psr_info.dczid_el0 & 0xf);
120 }
121 static int icache_line_size() {
122 return (1 << (_psr_info.ctr_el0 & 0x0f)) * 4;
123 }
124 static int dcache_line_size() {
125 return (1 << ((_psr_info.ctr_el0 >> 16) & 0x0f)) * 4;
126 }
127 static bool supports_fast_class_init_checks() { return true; }
128 };
129
130 #endif // CPU_AARCH64_VM_VERSION_AARCH64_HPP
|
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_VERSION_AARCH64_HPP
27 #define CPU_AARCH64_VM_VERSION_AARCH64_HPP
28
29 #include "runtime/abstract_vm_version.hpp"
30 #include "runtime/globals_extension.hpp"
31 #include "utilities/sizes.hpp"
32 #include "runtime/java.hpp"
33
34 class VM_Version : public Abstract_VM_Version {
35 friend class JVMCIVMStructs;
36
37 protected:
38 static int _cpu;
39 static int _model;
40 static int _model2;
41 static int _variant;
42 static int _revision;
43 static int _stepping;
44 static bool _dcpop;
45 struct PsrInfo {
46 uint32_t dczid_el0;
47 #ifndef _WIN64
48 // On Windows-aarch64, this register is not accessible. We then need to
49 // access the cache line size in a different way. Instead, we get the cache
50 // line size in os::win32::get_cacheline_size.
51 uint32_t ctr_el0;
52 #endif
53 };
54 static PsrInfo _psr_info;
55 static void get_processor_features();
56
57 public:
58 // Initialization
59 static void initialize();
60
61 // Asserts
62 static void assert_is_initialized() {
63 }
64
65 static bool expensive_load(int ld_size, int scale) {
66 if (cpu_family() == CPU_ARM) {
67 // Half-word load with index shift by 1 (aka scale is 2) has
68 // extra cycle latency, e.g. ldrsh w0, [x1,w2,sxtw #1].
69 if (ld_size == 2 && scale == 2) {
70 return true;
71 }
72 }
85 CPU_HISILICON = 'H',
86 CPU_INFINEON = 'I',
87 CPU_MOTOROLA = 'M',
88 CPU_NVIDIA = 'N',
89 CPU_AMCC = 'P',
90 CPU_QUALCOM = 'Q',
91 CPU_MARVELL = 'V',
92 CPU_INTEL = 'i',
93 };
94
95 enum Feature_Flag {
96 CPU_FP = (1<<0),
97 CPU_ASIMD = (1<<1),
98 CPU_EVTSTRM = (1<<2),
99 CPU_AES = (1<<3),
100 CPU_PMULL = (1<<4),
101 CPU_SHA1 = (1<<5),
102 CPU_SHA2 = (1<<6),
103 CPU_CRC32 = (1<<7),
104 CPU_LSE = (1<<8),
105 CPU_SHA512 = (1 << 21),
106 CPU_STXR_PREFETCH= (1 << 29),
107 CPU_A53MAC = (1 << 30),
108 };
109
110 static int cpu_family() { return _cpu; }
111 static int cpu_model() { return _model; }
112 static int cpu_model2() { return _model2; }
113 static int cpu_variant() { return _variant; }
114 static int cpu_revision() { return _revision; }
115 static bool supports_dcpop() { return _dcpop; }
116
117 static ByteSize dczid_el0_offset() { return byte_offset_of(PsrInfo, dczid_el0); }
118 #ifndef _WIN64
119 static ByteSize ctr_el0_offset() { return byte_offset_of(PsrInfo, ctr_el0); }
120 #endif
121 static bool is_zva_enabled() {
122 // Check the DZP bit (bit 4) of dczid_el0 is zero
123 // and block size (bit 0~3) is not zero.
124 return ((_psr_info.dczid_el0 & 0x10) == 0 &&
125 (_psr_info.dczid_el0 & 0xf) != 0);
126 }
127 static int zva_length() {
128 assert(is_zva_enabled(), "ZVA not available");
129 return 4 << (_psr_info.dczid_el0 & 0xf);
130 }
131 static int icache_line_size() {
132 #ifndef _WIN64
133 return (1 << (_psr_info.ctr_el0 & 0x0f)) * 4;
134 #else
135 return os::win32::get_cacheline_size();
136 #endif
137 }
138 static int dcache_line_size() {
139 #ifndef _WIN64
140 return (1 << ((_psr_info.ctr_el0 >> 16) & 0x0f)) * 4;
141 #else
142 return os::win32::get_cacheline_size();
143 #endif
144 }
145 static bool supports_fast_class_init_checks() { return true; }
146 };
147
148 #endif // CPU_AARCH64_VM_VERSION_AARCH64_HPP
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