1 /*
   2  * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_REGISTER_AARCH64_HPP
  27 #define CPU_AARCH64_REGISTER_AARCH64_HPP
  28 
  29 #include "asm/register.hpp"
  30 
  31 class VMRegImpl;
  32 typedef VMRegImpl* VMReg;
  33 
  34 // Use Register as shortcut
  35 class RegisterImpl;
  36 typedef RegisterImpl* Register;
  37 
  38 inline Register as_Register(int encoding) {
  39   return (Register)(intptr_t) encoding;
  40 }
  41 
  42 class RegisterImpl: public AbstractRegisterImpl {
  43  public:
  44   enum {
  45     number_of_registers         =   32,
  46     number_of_byte_registers      = 32,
  47     number_of_registers_for_jvmci = 34,  // Including SP and ZR.
  48     max_slots_per_register = 2
  49   };
  50 
  51   // derived registers, offsets, and addresses
  52   Register successor() const                          { return as_Register(encoding() + 1); }
  53 
  54   // construction
  55   inline friend Register as_Register(int encoding);
  56 
  57   VMReg as_VMReg();
  58 
  59   // accessors
  60   int   encoding() const                         { assert(is_valid(), "invalid register"); return (intptr_t)this; }
  61   bool  is_valid() const                         { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
  62   bool  has_byte_register() const                { return 0 <= (intptr_t)this && (intptr_t)this < number_of_byte_registers; }
  63   const char* name() const;
  64   int   encoding_nocheck() const                 { return (intptr_t)this; }
  65 
  66   // Return the bit which represents this register.  This is intended
  67   // to be ORed into a bitmask: for usage see class RegSet below.
  68   uint64_t bit(bool should_set = true) const { return should_set ? 1 << encoding() : 0; }
  69 };
  70 
  71 // The integer registers of the aarch64 architecture
  72 
  73 CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1));
  74 
  75 
  76 CONSTANT_REGISTER_DECLARATION(Register, r0,    (0));
  77 CONSTANT_REGISTER_DECLARATION(Register, r1,    (1));
  78 CONSTANT_REGISTER_DECLARATION(Register, r2,    (2));
  79 CONSTANT_REGISTER_DECLARATION(Register, r3,    (3));
  80 CONSTANT_REGISTER_DECLARATION(Register, r4,    (4));
  81 CONSTANT_REGISTER_DECLARATION(Register, r5,    (5));
  82 CONSTANT_REGISTER_DECLARATION(Register, r6,    (6));
  83 CONSTANT_REGISTER_DECLARATION(Register, r7,    (7));
  84 CONSTANT_REGISTER_DECLARATION(Register, r8,    (8));
  85 CONSTANT_REGISTER_DECLARATION(Register, r9,    (9));
  86 CONSTANT_REGISTER_DECLARATION(Register, r10,  (10));
  87 CONSTANT_REGISTER_DECLARATION(Register, r11,  (11));
  88 CONSTANT_REGISTER_DECLARATION(Register, r12,  (12));
  89 CONSTANT_REGISTER_DECLARATION(Register, r13,  (13));
  90 CONSTANT_REGISTER_DECLARATION(Register, r14,  (14));
  91 CONSTANT_REGISTER_DECLARATION(Register, r15,  (15));
  92 CONSTANT_REGISTER_DECLARATION(Register, r16,  (16));
  93 CONSTANT_REGISTER_DECLARATION(Register, r17,  (17));
  94 CONSTANT_REGISTER_DECLARATION(Register, r18,  (18));
  95 CONSTANT_REGISTER_DECLARATION(Register, r19,  (19));
  96 CONSTANT_REGISTER_DECLARATION(Register, r20,  (20));
  97 CONSTANT_REGISTER_DECLARATION(Register, r21,  (21));
  98 CONSTANT_REGISTER_DECLARATION(Register, r22,  (22));
  99 CONSTANT_REGISTER_DECLARATION(Register, r23,  (23));
 100 CONSTANT_REGISTER_DECLARATION(Register, r24,  (24));
 101 CONSTANT_REGISTER_DECLARATION(Register, r25,  (25));
 102 CONSTANT_REGISTER_DECLARATION(Register, r26,  (26));
 103 CONSTANT_REGISTER_DECLARATION(Register, r27,  (27));
 104 CONSTANT_REGISTER_DECLARATION(Register, r28,  (28));
 105 CONSTANT_REGISTER_DECLARATION(Register, r29,  (29));
 106 CONSTANT_REGISTER_DECLARATION(Register, r30,  (30));
 107 
 108 
 109 // r31 is not a general purpose register, but represents either the
 110 // stack pointer or the zero/discard register depending on the
 111 // instruction.
 112 CONSTANT_REGISTER_DECLARATION(Register, r31_sp, (31));
 113 CONSTANT_REGISTER_DECLARATION(Register, zr,  (32));
 114 CONSTANT_REGISTER_DECLARATION(Register, sp,  (33));
 115 
 116 // Used as a filler in instructions where a register field is unused.
 117 const Register dummy_reg = r31_sp;
 118 
 119 // Use FloatRegister as shortcut
 120 class FloatRegisterImpl;
 121 typedef FloatRegisterImpl* FloatRegister;
 122 
 123 inline FloatRegister as_FloatRegister(int encoding) {
 124   return (FloatRegister)(intptr_t) encoding;
 125 }
 126 
 127 // The implementation of floating point registers for the architecture
 128 class FloatRegisterImpl: public AbstractRegisterImpl {
 129  public:
 130   enum {
 131     number_of_registers = 32,
 132     max_slots_per_register = 4,
 133     save_slots_per_register = 2,
 134     extra_save_slots_per_register = max_slots_per_register - save_slots_per_register
 135   };
 136 
 137   // construction
 138   inline friend FloatRegister as_FloatRegister(int encoding);
 139 
 140   VMReg as_VMReg();
 141 
 142   // derived registers, offsets, and addresses
 143   FloatRegister successor() const                          { return as_FloatRegister((encoding() + 1) % 32); }
 144 
 145   // accessors
 146   int   encoding() const                          { assert(is_valid(), "invalid register"); return (intptr_t)this; }
 147   int   encoding_nocheck() const                         { return (intptr_t)this; }
 148   bool  is_valid() const                          { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
 149   const char* name() const;
 150 
 151 };
 152 
 153 // The float registers of the AARCH64 architecture
 154 
 155 CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg , (-1));
 156 
 157 CONSTANT_REGISTER_DECLARATION(FloatRegister, v0     , ( 0));
 158 CONSTANT_REGISTER_DECLARATION(FloatRegister, v1     , ( 1));
 159 CONSTANT_REGISTER_DECLARATION(FloatRegister, v2     , ( 2));
 160 CONSTANT_REGISTER_DECLARATION(FloatRegister, v3     , ( 3));
 161 CONSTANT_REGISTER_DECLARATION(FloatRegister, v4     , ( 4));
 162 CONSTANT_REGISTER_DECLARATION(FloatRegister, v5     , ( 5));
 163 CONSTANT_REGISTER_DECLARATION(FloatRegister, v6     , ( 6));
 164 CONSTANT_REGISTER_DECLARATION(FloatRegister, v7     , ( 7));
 165 CONSTANT_REGISTER_DECLARATION(FloatRegister, v8     , ( 8));
 166 CONSTANT_REGISTER_DECLARATION(FloatRegister, v9     , ( 9));
 167 CONSTANT_REGISTER_DECLARATION(FloatRegister, v10    , (10));
 168 CONSTANT_REGISTER_DECLARATION(FloatRegister, v11    , (11));
 169 CONSTANT_REGISTER_DECLARATION(FloatRegister, v12    , (12));
 170 CONSTANT_REGISTER_DECLARATION(FloatRegister, v13    , (13));
 171 CONSTANT_REGISTER_DECLARATION(FloatRegister, v14    , (14));
 172 CONSTANT_REGISTER_DECLARATION(FloatRegister, v15    , (15));
 173 CONSTANT_REGISTER_DECLARATION(FloatRegister, v16    , (16));
 174 CONSTANT_REGISTER_DECLARATION(FloatRegister, v17    , (17));
 175 CONSTANT_REGISTER_DECLARATION(FloatRegister, v18    , (18));
 176 CONSTANT_REGISTER_DECLARATION(FloatRegister, v19    , (19));
 177 CONSTANT_REGISTER_DECLARATION(FloatRegister, v20    , (20));
 178 CONSTANT_REGISTER_DECLARATION(FloatRegister, v21    , (21));
 179 CONSTANT_REGISTER_DECLARATION(FloatRegister, v22    , (22));
 180 CONSTANT_REGISTER_DECLARATION(FloatRegister, v23    , (23));
 181 CONSTANT_REGISTER_DECLARATION(FloatRegister, v24    , (24));
 182 CONSTANT_REGISTER_DECLARATION(FloatRegister, v25    , (25));
 183 CONSTANT_REGISTER_DECLARATION(FloatRegister, v26    , (26));
 184 CONSTANT_REGISTER_DECLARATION(FloatRegister, v27    , (27));
 185 CONSTANT_REGISTER_DECLARATION(FloatRegister, v28    , (28));
 186 CONSTANT_REGISTER_DECLARATION(FloatRegister, v29    , (29));
 187 CONSTANT_REGISTER_DECLARATION(FloatRegister, v30    , (30));
 188 CONSTANT_REGISTER_DECLARATION(FloatRegister, v31    , (31));
 189 
 190 // Need to know the total number of registers of all sorts for SharedInfo.
 191 // Define a class that exports it.
 192 class ConcreteRegisterImpl : public AbstractRegisterImpl {
 193  public:
 194   enum {
 195   // A big enough number for C2: all the registers plus flags
 196   // This number must be large enough to cover REG_COUNT (defined by c2) registers.
 197   // There is no requirement that any ordering here matches any ordering c2 gives
 198   // it's optoregs.
 199 
 200     number_of_registers = (RegisterImpl::max_slots_per_register * RegisterImpl::number_of_registers +
 201                            FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers +
 202                            1) // flags
 203   };
 204 
 205   // added to make it compile
 206   static const int max_gpr;
 207   static const int max_fpr;
 208 };
 209 
 210 // A set of registers
 211 class RegSet {
 212   uint32_t _bitset;
 213 
 214   RegSet(uint32_t bitset) : _bitset(bitset) { }
 215 
 216 public:
 217 
 218   RegSet() : _bitset(0) { }
 219 
 220   RegSet(Register r1) : _bitset(r1->bit()) { }
 221 
 222   RegSet operator+(const RegSet aSet) const {
 223     RegSet result(_bitset | aSet._bitset);
 224     return result;
 225   }
 226 
 227   RegSet operator-(const RegSet aSet) const {
 228     RegSet result(_bitset & ~aSet._bitset);
 229     return result;
 230   }
 231 
 232   RegSet &operator+=(const RegSet aSet) {
 233     *this = *this + aSet;
 234     return *this;
 235   }
 236 
 237   RegSet &operator-=(const RegSet aSet) {
 238     *this = *this - aSet;
 239     return *this;
 240   }
 241 
 242   static RegSet of(Register r1) {
 243     return RegSet(r1);
 244   }
 245 
 246   static RegSet of(Register r1, Register r2) {
 247     return of(r1) + r2;
 248   }
 249 
 250   static RegSet of(Register r1, Register r2, Register r3) {
 251     return of(r1, r2) + r3;
 252   }
 253 
 254   static RegSet of(Register r1, Register r2, Register r3, Register r4) {
 255     return of(r1, r2, r3) + r4;
 256   }
 257 
 258   static RegSet range(Register start, Register end) {
 259     uint32_t bits = ~0;
 260     bits <<= start->encoding();
 261     bits <<= 31 - end->encoding();
 262     bits >>= 31 - end->encoding();
 263 
 264     return RegSet(bits);
 265   }
 266 
 267   uint32_t bits() const { return _bitset; }
 268 };
 269 
 270 #endif // CPU_AARCH64_REGISTER_AARCH64_HPP