src/hotspot/cpu/arm/macroAssembler_arm.hpp

rev 54101 : 8214512: ARM32: Jtreg test compiler/c2/Test8062950.java fails on ARM
Reviewed-by: dlong, enevill, bulasevich
Contributed-by: nick.gasson@arm.com, christoph.goettschkes@microdoc.com

@@ -374,14 +374,14 @@
 
   // Biased locking support
   // lock_reg and obj_reg must be loaded up with the appropriate values.
   // swap_reg must be supplied.
   // tmp_reg must be supplied.
-  // Optional slow case is for implementations (interpreter and C1) which branch to
-  // slow case directly. If slow_case is NULL, then leaves condition
-  // codes set (for C2's Fast_Lock node) and jumps to done label.
-  // Falls through for the fast locking attempt.
+  // Done label is branched to with condition code EQ set if the lock is
+  // biased and we acquired it. Slow case label is branched to with
+  // condition code NE set if the lock is biased but we failed to acquire
+  // it. Otherwise fall through.
   // Returns offset of first potentially-faulting instruction for null
   // check info (currently consumed only by C1). If
   // swap_reg_contains_mark is true then returns -1 as it is assumed
   // the calling code has already passed any potential faults.
   // Notes:

@@ -1346,16 +1346,15 @@
   }
 
   void restore_default_fp_mode();
 
 #ifdef COMPILER2
-#ifdef AARCH64
   // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
-  void fast_lock(Register obj, Register box, Register scratch, Register scratch2, Register scratch3);
+  void fast_lock(Register obj, Register box, Register scratch, Register scratch2, Register scratch3 = noreg);
+#ifdef AARCH64
   void fast_unlock(Register obj, Register box, Register scratch, Register scratch2, Register scratch3);
 #else
-  void fast_lock(Register obj, Register box, Register scratch, Register scratch2);
   void fast_unlock(Register obj, Register box, Register scratch, Register scratch2);
 #endif
 #endif
 
 #ifdef AARCH64