13200 format %{ "frint $dst, $src, $rmode" %}
13201 ins_encode %{
13202 switch ($rmode$$constant) {
13203 case RoundDoubleModeNode::rmode_rint:
13204 __ frintnd(as_FloatRegister($dst$$reg),
13205 as_FloatRegister($src$$reg));
13206 break;
13207 case RoundDoubleModeNode::rmode_floor:
13208 __ frintmd(as_FloatRegister($dst$$reg),
13209 as_FloatRegister($src$$reg));
13210 break;
13211 case RoundDoubleModeNode::rmode_ceil:
13212 __ frintpd(as_FloatRegister($dst$$reg),
13213 as_FloatRegister($src$$reg));
13214 break;
13215 }
13216 %}
13217 ins_pipe(fp_uop_d);
13218 %}
13219
13220 // ============================================================================
13221 // Logical Instructions
13222
13223 // Integer Logical Instructions
13224
13225 // And Instructions
13226
13227
13228 instruct andI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, rFlagsReg cr) %{
13229 match(Set dst (AndI src1 src2));
13230
13231 format %{ "andw $dst, $src1, $src2\t# int" %}
13232
13233 ins_cost(INSN_COST);
13234 ins_encode %{
13235 __ andw(as_Register($dst$$reg),
13236 as_Register($src1$$reg),
13237 as_Register($src2$$reg));
13238 %}
13239
|
13200 format %{ "frint $dst, $src, $rmode" %}
13201 ins_encode %{
13202 switch ($rmode$$constant) {
13203 case RoundDoubleModeNode::rmode_rint:
13204 __ frintnd(as_FloatRegister($dst$$reg),
13205 as_FloatRegister($src$$reg));
13206 break;
13207 case RoundDoubleModeNode::rmode_floor:
13208 __ frintmd(as_FloatRegister($dst$$reg),
13209 as_FloatRegister($src$$reg));
13210 break;
13211 case RoundDoubleModeNode::rmode_ceil:
13212 __ frintpd(as_FloatRegister($dst$$reg),
13213 as_FloatRegister($src$$reg));
13214 break;
13215 }
13216 %}
13217 ins_pipe(fp_uop_d);
13218 %}
13219
13220 instruct signumD_reg(vRegD dst, vRegD src, vRegD tmp, vRegD one) %{
13221 match(Set dst (SignumD src));
13222 effect(TEMP_DEF dst, TEMP tmp, TEMP one);
13223 format %{ "signumD $dst, $src" %}
13224 ins_encode %{
13225 FloatRegister src = as_FloatRegister($src$$reg),
13226 dst = as_FloatRegister($dst$$reg),
13227 tmp = as_FloatRegister($tmp$$reg),
13228 one = as_FloatRegister($one$$reg);
13229 __ fmovd(tmp, 0.0d);
13230 __ fmovd(one, 1.0d);
13231 __ facgtd(dst, src, tmp); // dst=0 for +-0.0 and NaN. 0xFFF..F otherwise
13232 __ ushrd(dst, dst, 1); // dst=0 for +-0.0 and NaN. 0x7FF..F otherwise
13233 // Bit selection instruction gets bit from "one" for each enabled bit in
13234 // "dst", otherwise gets a bit from "src". For "src" that contains +-0.0 or
13235 // NaN the whole "src" will be copied because "dst" is zero. For all other
13236 // "src" values dst is 0x7FF..F, which means only the sign bit is copied
13237 // from "src", and all other bits are copied from 1.0.
13238 __ bsl(dst, __ T8B, one, src);
13239 %}
13240 ins_pipe(fp_uop_d);
13241 %}
13242
13243 instruct signumF_reg(vRegF dst, vRegF src, vRegF tmp, vRegF one) %{
13244 match(Set dst (SignumF src));
13245 effect(TEMP_DEF dst, USE src, TEMP tmp, TEMP one);
13246 format %{ "signumF $dst, $src" %}
13247 ins_encode %{
13248 FloatRegister src = as_FloatRegister($src$$reg),
13249 dst = as_FloatRegister($dst$$reg),
13250 tmp = as_FloatRegister($tmp$$reg),
13251 one = as_FloatRegister($one$$reg);
13252 __ fmovs(tmp, 0.0f);
13253 __ fmovs(one, 1.0f);
13254 __ facgts(dst, src, tmp); // dst=0 for +-0.0 and NaN. 0xFFF..F otherwise
13255 __ ushr(dst, __ T2S, dst, 1); // dst=0 for +-0.0 and NaN. 0x7FF..F otherwise
13256 // Bit selection instruction gets bit from "one" for each enabled bit in
13257 // "dst", otherwise gets a bit from "src". For "src" that contains +-0.0 or
13258 // NaN the whole "src" will be copied because "dst" is zero. For all other
13259 // "src" values dst is 0x7FF..F, which means only the sign bit is copied
13260 // from "src", and all other bits are copied from 1.0.
13261 __ bsl(dst, __ T8B, one, src);
13262 %}
13263 ins_pipe(fp_uop_d);
13264 %}
13265
13266 // ============================================================================
13267 // Logical Instructions
13268
13269 // Integer Logical Instructions
13270
13271 // And Instructions
13272
13273
13274 instruct andI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, rFlagsReg cr) %{
13275 match(Set dst (AndI src1 src2));
13276
13277 format %{ "andw $dst, $src1, $src2\t# int" %}
13278
13279 ins_cost(INSN_COST);
13280 ins_encode %{
13281 __ andw(as_Register($dst$$reg),
13282 as_Register($src1$$reg),
13283 as_Register($src2$$reg));
13284 %}
13285
|