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src/hotspot/cpu/aarch64/aarch64.ad
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@@ -13215,10 +13215,56 @@
}
%}
ins_pipe(fp_uop_d);
%}
+instruct signumD_reg(vRegD dst, vRegD src, vRegD tmp, vRegD one) %{
+ match(Set dst (SignumD src));
+ effect(TEMP_DEF dst, TEMP tmp, TEMP one);
+ format %{ "signumD $dst, $src" %}
+ ins_encode %{
+ FloatRegister src = as_FloatRegister($src$$reg),
+ dst = as_FloatRegister($dst$$reg),
+ tmp = as_FloatRegister($tmp$$reg),
+ one = as_FloatRegister($one$$reg);
+ __ fmovd(tmp, 0.0d);
+ __ fmovd(one, 1.0d);
+ __ facgtd(dst, src, tmp); // dst=0 for +-0.0 and NaN. 0xFFF..F otherwise
+ __ ushrd(dst, dst, 1); // dst=0 for +-0.0 and NaN. 0x7FF..F otherwise
+ // Bit selection instruction gets bit from "one" for each enabled bit in
+ // "dst", otherwise gets a bit from "src". For "src" that contains +-0.0 or
+ // NaN the whole "src" will be copied because "dst" is zero. For all other
+ // "src" values dst is 0x7FF..F, which means only the sign bit is copied
+ // from "src", and all other bits are copied from 1.0.
+ __ bsl(dst, __ T8B, one, src);
+ %}
+ ins_pipe(fp_uop_d);
+%}
+
+instruct signumF_reg(vRegF dst, vRegF src, vRegF tmp, vRegF one) %{
+ match(Set dst (SignumF src));
+ effect(TEMP_DEF dst, USE src, TEMP tmp, TEMP one);
+ format %{ "signumF $dst, $src" %}
+ ins_encode %{
+ FloatRegister src = as_FloatRegister($src$$reg),
+ dst = as_FloatRegister($dst$$reg),
+ tmp = as_FloatRegister($tmp$$reg),
+ one = as_FloatRegister($one$$reg);
+ __ fmovs(tmp, 0.0f);
+ __ fmovs(one, 1.0f);
+ __ facgts(dst, src, tmp); // dst=0 for +-0.0 and NaN. 0xFFF..F otherwise
+ __ ushr(dst, __ T2S, dst, 1); // dst=0 for +-0.0 and NaN. 0x7FF..F otherwise
+ // Bit selection instruction gets bit from "one" for each enabled bit in
+ // "dst", otherwise gets a bit from "src". For "src" that contains +-0.0 or
+ // NaN the whole "src" will be copied because "dst" is zero. For all other
+ // "src" values dst is 0x7FF..F, which means only the sign bit is copied
+ // from "src", and all other bits are copied from 1.0.
+ __ bsl(dst, __ T8B, one, src);
+ %}
+ ins_pipe(fp_uop_d);
+%}
+
// ============================================================================
// Logical Instructions
// Integer Logical Instructions
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