12627 __ fsqrtd(as_FloatRegister($dst$$reg),
12628 as_FloatRegister($src$$reg));
12629 %}
12630
12631 ins_pipe(fp_div_s);
12632 %}
12633
12634 instruct sqrtF_reg(vRegF dst, vRegF src) %{
12635 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
12636
12637 ins_cost(INSN_COST * 50);
12638 format %{ "fsqrts $dst, $src" %}
12639 ins_encode %{
12640 __ fsqrts(as_FloatRegister($dst$$reg),
12641 as_FloatRegister($src$$reg));
12642 %}
12643
12644 ins_pipe(fp_div_d);
12645 %}
12646
12647 // ============================================================================
12648 // Logical Instructions
12649
12650 // Integer Logical Instructions
12651
12652 // And Instructions
12653
12654
12655 instruct andI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, rFlagsReg cr) %{
12656 match(Set dst (AndI src1 src2));
12657
12658 format %{ "andw $dst, $src1, $src2\t# int" %}
12659
12660 ins_cost(INSN_COST);
12661 ins_encode %{
12662 __ andw(as_Register($dst$$reg),
12663 as_Register($src1$$reg),
12664 as_Register($src2$$reg));
12665 %}
12666
|
12627 __ fsqrtd(as_FloatRegister($dst$$reg),
12628 as_FloatRegister($src$$reg));
12629 %}
12630
12631 ins_pipe(fp_div_s);
12632 %}
12633
12634 instruct sqrtF_reg(vRegF dst, vRegF src) %{
12635 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
12636
12637 ins_cost(INSN_COST * 50);
12638 format %{ "fsqrts $dst, $src" %}
12639 ins_encode %{
12640 __ fsqrts(as_FloatRegister($dst$$reg),
12641 as_FloatRegister($src$$reg));
12642 %}
12643
12644 ins_pipe(fp_div_d);
12645 %}
12646
12647 instruct copySignD_reg(vRegD dst, vRegD src1, vRegD src2, vRegD zero) %{
12648 match(Set dst (CopySignD src1 (Binary src2 zero)));
12649 effect(TEMP_DEF dst, USE src1, USE src2, USE zero);
12650 format %{ "CopySignD $dst $src1 $src2" %}
12651 ins_encode %{
12652 FloatRegister dst = as_FloatRegister($dst$$reg),
12653 src1 = as_FloatRegister($src1$$reg),
12654 src2 = as_FloatRegister($src2$$reg),
12655 zero = as_FloatRegister($zero$$reg);
12656 __ fnegd(dst, zero);
12657 __ bsl(dst, __ T8B, src2, src1);
12658 %}
12659 ins_pipe(fp_uop_d);
12660 %}
12661
12662 instruct copySignF_reg(vRegF dst, vRegF src1, vRegF src2) %{
12663 match(Set dst (CopySignF src1 src2));
12664 effect(TEMP_DEF dst, USE src1, USE src2);
12665 format %{ "CopySignF $dst $src1 $src2" %}
12666 ins_encode %{
12667 FloatRegister dst = as_FloatRegister($dst$$reg),
12668 src1 = as_FloatRegister($src1$$reg),
12669 src2 = as_FloatRegister($src2$$reg);
12670 __ movi(dst, __ T2S, 0x80, 24);
12671 __ bsl(dst, __ T8B, src2, src1);
12672 %}
12673 ins_pipe(fp_uop_d);
12674 %}
12675
12676 instruct signumD_reg(vRegD dst, vRegD src, vRegD zero, vRegD one) %{
12677 match(Set dst (SignumD src (Binary zero one)));
12678 effect(TEMP_DEF dst, USE src, USE zero, USE one);
12679 format %{ "signumD $dst, $src" %}
12680 ins_encode %{
12681 FloatRegister src = as_FloatRegister($src$$reg),
12682 dst = as_FloatRegister($dst$$reg),
12683 zero = as_FloatRegister($zero$$reg),
12684 one = as_FloatRegister($one$$reg);
12685 __ facgtd(dst, src, zero); // dst=0 for +-0.0 and NaN. 0xFFF..F otherwise
12686 __ ushrd(dst, dst, 1); // dst=0 for +-0.0 and NaN. 0x7FF..F otherwise
12687 // Bit selection instruction gets bit from "one" for each enabled bit in
12688 // "dst", otherwise gets a bit from "src". For "src" that contains +-0.0 or
12689 // NaN the whole "src" will be copied because "dst" is zero. For all other
12690 // "src" values dst is 0x7FF..F, which means only the sign bit is copied
12691 // from "src", and all other bits are copied from 1.0.
12692 __ bsl(dst, __ T8B, one, src);
12693 %}
12694 ins_pipe(fp_uop_d);
12695 %}
12696
12697 instruct signumF_reg(vRegF dst, vRegF src, vRegF zero, vRegF one) %{
12698 match(Set dst (SignumF src (Binary zero one)));
12699 effect(TEMP_DEF dst, USE src, USE zero, USE one);
12700 format %{ "signumF $dst, $src" %}
12701 ins_encode %{
12702 FloatRegister src = as_FloatRegister($src$$reg),
12703 dst = as_FloatRegister($dst$$reg),
12704 zero = as_FloatRegister($zero$$reg),
12705 one = as_FloatRegister($one$$reg);
12706 __ facgts(dst, src, zero); // dst=0 for +-0.0 and NaN. 0xFFF..F otherwise
12707 __ ushr(dst, __ T2S, dst, 1); // dst=0 for +-0.0 and NaN. 0x7FF..F otherwise
12708 // Bit selection instruction gets bit from "one" for each enabled bit in
12709 // "dst", otherwise gets a bit from "src". For "src" that contains +-0.0 or
12710 // NaN the whole "src" will be copied because "dst" is zero. For all other
12711 // "src" values dst is 0x7FF..F, which means only the sign bit is copied
12712 // from "src", and all other bits are copied from 1.0.
12713 __ bsl(dst, __ T8B, one, src);
12714 %}
12715 ins_pipe(fp_uop_d);
12716 %}
12717
12718 // ============================================================================
12719 // Logical Instructions
12720
12721 // Integer Logical Instructions
12722
12723 // And Instructions
12724
12725
12726 instruct andI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, rFlagsReg cr) %{
12727 match(Set dst (AndI src1 src2));
12728
12729 format %{ "andw $dst, $src1, $src2\t# int" %}
12730
12731 ins_cost(INSN_COST);
12732 ins_encode %{
12733 __ andw(as_Register($dst$$reg),
12734 as_Register($src1$$reg),
12735 as_Register($src2$$reg));
12736 %}
12737
|