1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP
28
29 #include "asm/register.hpp"
30
31 // definitions of various symbolic names for machine registers
32
33 // First intercalls between C and Java which use 8 general registers
34 // and 8 floating registers
35
36 // we also have to copy between x86 and ARM registers but that's a
37 // secondary complication -- not all code employing C call convention
38 // executes as x86 code though -- we generate some of it
39
40 class Argument {
41 public:
42 enum {
43 n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
44 n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... )
45
46 n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
47 n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ...
48 };
49 };
50
51 REGISTER_DECLARATION(Register, c_rarg0, r0);
52 REGISTER_DECLARATION(Register, c_rarg1, r1);
53 REGISTER_DECLARATION(Register, c_rarg2, r2);
54 REGISTER_DECLARATION(Register, c_rarg3, r3);
55 REGISTER_DECLARATION(Register, c_rarg4, r4);
56 REGISTER_DECLARATION(Register, c_rarg5, r5);
57 REGISTER_DECLARATION(Register, c_rarg6, r6);
58 REGISTER_DECLARATION(Register, c_rarg7, r7);
59
60 REGISTER_DECLARATION(FloatRegister, c_farg0, v0);
61 REGISTER_DECLARATION(FloatRegister, c_farg1, v1);
62 REGISTER_DECLARATION(FloatRegister, c_farg2, v2);
63 REGISTER_DECLARATION(FloatRegister, c_farg3, v3);
64 REGISTER_DECLARATION(FloatRegister, c_farg4, v4);
65 REGISTER_DECLARATION(FloatRegister, c_farg5, v5);
66 REGISTER_DECLARATION(FloatRegister, c_farg6, v6);
67 REGISTER_DECLARATION(FloatRegister, c_farg7, v7);
68
69 // Symbolically name the register arguments used by the Java calling convention.
70 // We have control over the convention for java so we can do what we please.
71 // What pleases us is to offset the java calling convention so that when
72 // we call a suitable jni method the arguments are lined up and we don't
73 // have to do much shuffling. A suitable jni method is non-static and a
74 // small number of arguments
75 //
76 // |--------------------------------------------------------------------|
77 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 |
78 // |--------------------------------------------------------------------|
79 // | r0 r1 r2 r3 r4 r5 r6 r7 |
80 // |--------------------------------------------------------------------|
81 // | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 |
82 // |--------------------------------------------------------------------|
83
84
85 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
86 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
87 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
88 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
89 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
90 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
91 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
92 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
93
94 // Java floating args are passed as per C
95
96 REGISTER_DECLARATION(FloatRegister, j_farg0, v0);
97 REGISTER_DECLARATION(FloatRegister, j_farg1, v1);
98 REGISTER_DECLARATION(FloatRegister, j_farg2, v2);
99 REGISTER_DECLARATION(FloatRegister, j_farg3, v3);
100 REGISTER_DECLARATION(FloatRegister, j_farg4, v4);
101 REGISTER_DECLARATION(FloatRegister, j_farg5, v5);
102 REGISTER_DECLARATION(FloatRegister, j_farg6, v6);
103 REGISTER_DECLARATION(FloatRegister, j_farg7, v7);
104
105 // registers used to hold VM data either temporarily within a method
106 // or across method calls
107
108 // volatile (caller-save) registers
109
110 // r8 is used for indirect result location return
111 // we use it and r9 as scratch registers
112 REGISTER_DECLARATION(Register, rscratch1, r8);
113 REGISTER_DECLARATION(Register, rscratch2, r9);
114
115 // current method -- must be in a call-clobbered register
116 REGISTER_DECLARATION(Register, rmethod, r12);
117
118 // non-volatile (callee-save) registers are r16-29
119 // of which the following are dedicated global state
120
121 // link register
122 REGISTER_DECLARATION(Register, lr, r30);
123 // frame pointer
124 REGISTER_DECLARATION(Register, rfp, r29);
125 // current thread
126 REGISTER_DECLARATION(Register, rthread, r28);
127 // base of heap
128 REGISTER_DECLARATION(Register, rheapbase, r27);
129 // constant pool cache
130 REGISTER_DECLARATION(Register, rcpool, r26);
131 // monitors allocated on stack
132 REGISTER_DECLARATION(Register, rmonitors, r25);
133 // locals on stack
134 REGISTER_DECLARATION(Register, rlocals, r24);
135 // bytecode pointer
136 REGISTER_DECLARATION(Register, rbcp, r22);
137 // Dispatch table base
138 REGISTER_DECLARATION(Register, rdispatch, r21);
139 // Java stack pointer
140 REGISTER_DECLARATION(Register, esp, r20);
141
142 #define assert_cond(ARG1) assert(ARG1, #ARG1)
143
144 namespace asm_util {
145 uint32_t encode_logical_immediate(bool is32, uint64_t imm);
146 };
147
148 using namespace asm_util;
149
150
151 class Assembler;
152
153 class Instruction_aarch64 {
154 unsigned insn;
155 #ifdef ASSERT
156 unsigned bits;
157 #endif
158 Assembler *assem;
159
160 public:
161
162 Instruction_aarch64(class Assembler *as) {
163 #ifdef ASSERT
164 bits = 0;
165 #endif
166 insn = 0;
167 assem = as;
168 }
169
170 inline ~Instruction_aarch64();
171
172 unsigned &get_insn() { return insn; }
173 #ifdef ASSERT
174 unsigned &get_bits() { return bits; }
175 #endif
176
177 static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
178 union {
179 unsigned u;
180 int n;
181 };
182
183 u = val << (31 - hi);
184 n = n >> (31 - hi + lo);
185 return n;
186 }
187
188 static inline uint32_t extract(uint32_t val, int msb, int lsb) {
189 int nbits = msb - lsb + 1;
190 assert_cond(msb >= lsb);
191 uint32_t mask = checked_cast<uint32_t>(right_n_bits(nbits));
192 uint32_t result = val >> lsb;
193 result &= mask;
194 return result;
195 }
196
197 static inline int32_t sextract(uint32_t val, int msb, int lsb) {
198 uint32_t uval = extract(val, msb, lsb);
199 return extend(uval, msb - lsb);
200 }
201
202 static void patch(address a, int msb, int lsb, unsigned long val) {
203 int nbits = msb - lsb + 1;
204 guarantee(val < (1U << nbits), "Field too big for insn");
205 assert_cond(msb >= lsb);
206 unsigned mask = checked_cast<unsigned>(right_n_bits(nbits));
207 val <<= lsb;
208 mask <<= lsb;
209 unsigned target = *(unsigned *)a;
210 target &= ~mask;
211 target |= val;
212 *(unsigned *)a = target;
213 }
214
215 static void spatch(address a, int msb, int lsb, long val) {
216 int nbits = msb - lsb + 1;
217 long chk = val >> (nbits - 1);
218 guarantee (chk == -1 || chk == 0, "Field too big for insn");
219 unsigned uval = val;
220 unsigned mask = checked_cast<unsigned>(right_n_bits(nbits));
221 uval &= mask;
222 uval <<= lsb;
223 mask <<= lsb;
224 unsigned target = *(unsigned *)a;
225 target &= ~mask;
226 target |= uval;
227 *(unsigned *)a = target;
228 }
229
230 void f(unsigned val, int msb, int lsb) {
231 int nbits = msb - lsb + 1;
232 guarantee(val < (1ULL << nbits), "Field too big for insn");
233 assert_cond(msb >= lsb);
234 unsigned mask = checked_cast<unsigned>(right_n_bits(nbits));
235 val <<= lsb;
236 mask <<= lsb;
237 insn |= val;
238 assert_cond((bits & mask) == 0);
239 #ifdef ASSERT
240 bits |= mask;
241 #endif
242 }
243
244 void f(unsigned val, int bit) {
245 f(val, bit, bit);
246 }
247
248 void sf(long val, int msb, int lsb) {
249 int nbits = msb - lsb + 1;
250 long chk = val >> (nbits - 1);
251 guarantee (chk == -1 || chk == 0, "Field too big for insn");
252 unsigned uval = val;
253 unsigned mask = checked_cast<unsigned>(right_n_bits(nbits));
254 uval &= mask;
255 f(uval, lsb + nbits - 1, lsb);
256 }
257
258 void rf(Register r, int lsb) {
259 f(r->encoding_nocheck(), lsb + 4, lsb);
260 }
261
262 // reg|ZR
263 void zrf(Register r, int lsb) {
264 f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);
265 }
266
267 // reg|SP
268 void srf(Register r, int lsb) {
269 f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);
270 }
271
272 void rf(FloatRegister r, int lsb) {
273 f(r->encoding_nocheck(), lsb + 4, lsb);
274 }
275
276 unsigned get(int msb = 31, int lsb = 0) {
277 int nbits = msb - lsb + 1;
278 unsigned mask = checked_cast<unsigned>(right_n_bits(nbits)) << lsb;
279 assert_cond((bits & mask) == mask);
280 return (insn & mask) >> lsb;
281 }
282
283 void fixed(unsigned value, unsigned mask) {
284 assert_cond ((mask & bits) == 0);
285 #ifdef ASSERT
286 bits |= mask;
287 #endif
288 insn |= value;
289 }
290 };
291
292 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
293
294 class PrePost {
295 int _offset;
296 Register _r;
297 public:
298 PrePost(Register reg, int o) : _offset(o), _r(reg) { }
299 int offset() { return _offset; }
300 Register reg() { return _r; }
301 };
302
303 class Pre : public PrePost {
304 public:
305 Pre(Register reg, int o) : PrePost(reg, o) { }
306 };
307 class Post : public PrePost {
308 Register _idx;
309 bool _is_postreg;
310 public:
311 Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; _is_postreg = false; }
312 Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; _is_postreg = true; }
313 Register idx_reg() { return _idx; }
314 bool is_postreg() {return _is_postreg; }
315 };
316
317 namespace ext
318 {
319 enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
320 };
321
322 // Addressing modes
323 class Address {
324 public:
325
326 enum mode { no_mode, base_plus_offset, pre, post, post_reg, pcrel,
327 base_plus_offset_reg, literal };
328
329 // Shift and extend for base reg + reg offset addressing
330 class extend {
331 int _option, _shift;
332 ext::operation _op;
333 public:
334 extend() { }
335 extend(int s, int o, ext::operation op) : _option(o), _shift(s), _op(op) { }
336 int option() const{ return _option; }
337 int shift() const { return _shift; }
338 ext::operation op() const { return _op; }
339 };
340 class uxtw : public extend {
341 public:
342 uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }
343 };
344 class lsl : public extend {
345 public:
346 lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }
347 };
348 class sxtw : public extend {
349 public:
350 sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }
351 };
352 class sxtx : public extend {
353 public:
354 sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }
355 };
356
357 private:
358 Register _base;
359 Register _index;
360 long _offset;
361 enum mode _mode;
362 extend _ext;
363
364 RelocationHolder _rspec;
365
366 // Typically we use AddressLiterals we want to use their rval
367 // However in some situations we want the lval (effect address) of
368 // the item. We provide a special factory for making those lvals.
369 bool _is_lval;
370
371 // If the target is far we'll need to load the ea of this to a
372 // register to reach it. Otherwise if near we can do PC-relative
373 // addressing.
374 address _target;
375
376 public:
377 Address()
378 : _mode(no_mode) { }
379 Address(Register r)
380 : _base(r), _index(noreg), _offset(0), _mode(base_plus_offset), _target(0) { }
381 Address(Register r, int o)
382 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
383 Address(Register r, long o)
384 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
385 Address(Register r, unsigned long o)
386 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
387 #ifdef ASSERT
388 Address(Register r, ByteSize disp)
389 : _base(r), _index(noreg), _offset(in_bytes(disp)), _mode(base_plus_offset), _target(0) { }
390 #endif
391 Address(Register r, Register r1, extend ext = lsl())
392 : _base(r), _index(r1), _offset(0), _mode(base_plus_offset_reg),
393 _ext(ext), _target(0) { }
394 Address(Pre p)
395 : _base(p.reg()), _offset(p.offset()), _mode(pre) { }
396 Address(Post p)
397 : _base(p.reg()), _index(p.idx_reg()), _offset(p.offset()),
398 _mode(p.is_postreg() ? post_reg : post), _target(0) { }
399 Address(address target, RelocationHolder const& rspec)
400 : _mode(literal),
401 _rspec(rspec),
402 _is_lval(false),
403 _target(target) { }
404 Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
405 Address(Register base, RegisterOrConstant index, extend ext = lsl())
406 : _base (base),
407 _offset(0), _ext(ext), _target(0) {
408 if (index.is_register()) {
409 _mode = base_plus_offset_reg;
410 _index = index.as_register();
411 } else {
412 guarantee(ext.option() == ext::uxtx, "should be");
413 assert(index.is_constant(), "should be");
414 _mode = base_plus_offset;
415 _offset = index.as_constant() << ext.shift();
416 }
417 }
418
419 Register base() const {
420 guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg
421 | _mode == post | _mode == post_reg),
422 "wrong mode");
423 return _base;
424 }
425 long offset() const {
426 return _offset;
427 }
428 Register index() const {
429 return _index;
430 }
431 mode getMode() const {
432 return _mode;
433 }
434 bool uses(Register reg) const { return _base == reg || _index == reg; }
435 address target() const { return _target; }
436 const RelocationHolder& rspec() const { return _rspec; }
437
438 void encode(Instruction_aarch64 *i) const {
439 i->f(0b111, 29, 27);
440 i->srf(_base, 5);
441
442 switch(_mode) {
443 case base_plus_offset:
444 {
445 unsigned size = i->get(31, 30);
446 if (i->get(26, 26) && i->get(23, 23)) {
447 // SIMD Q Type - Size = 128 bits
448 assert(size == 0, "bad size");
449 size = 0b100;
450 }
451 unsigned mask = (1 << size) - 1;
452 if (_offset < 0 || _offset & mask)
453 {
454 i->f(0b00, 25, 24);
455 i->f(0, 21), i->f(0b00, 11, 10);
456 i->sf(_offset, 20, 12);
457 } else {
458 i->f(0b01, 25, 24);
459 i->f(_offset >> size, 21, 10);
460 }
461 }
462 break;
463
464 case base_plus_offset_reg:
465 {
466 i->f(0b00, 25, 24);
467 i->f(1, 21);
468 i->rf(_index, 16);
469 i->f(_ext.option(), 15, 13);
470 unsigned size = i->get(31, 30);
471 if (i->get(26, 26) && i->get(23, 23)) {
472 // SIMD Q Type - Size = 128 bits
473 assert(size == 0, "bad size");
474 size = 0b100;
475 }
476 if (size == 0) // It's a byte
477 i->f(_ext.shift() >= 0, 12);
478 else {
479 assert(_ext.shift() <= 0 || _ext.shift() == (int)size, "bad shift");
480 i->f(_ext.shift() > 0, 12);
481 }
482 i->f(0b10, 11, 10);
483 }
484 break;
485
486 case pre:
487 i->f(0b00, 25, 24);
488 i->f(0, 21), i->f(0b11, 11, 10);
489 i->sf(_offset, 20, 12);
490 break;
491
492 case post:
493 i->f(0b00, 25, 24);
494 i->f(0, 21), i->f(0b01, 11, 10);
495 i->sf(_offset, 20, 12);
496 break;
497
498 default:
499 ShouldNotReachHere();
500 }
501 }
502
503 void encode_pair(Instruction_aarch64 *i) const {
504 switch(_mode) {
505 case base_plus_offset:
506 i->f(0b010, 25, 23);
507 break;
508 case pre:
509 i->f(0b011, 25, 23);
510 break;
511 case post:
512 i->f(0b001, 25, 23);
513 break;
514 default:
515 ShouldNotReachHere();
516 }
517
518 unsigned size; // Operand shift in 32-bit words
519
520 if (i->get(26, 26)) { // float
521 switch(i->get(31, 30)) {
522 case 0b10:
523 size = 2; break;
524 case 0b01:
525 size = 1; break;
526 case 0b00:
527 size = 0; break;
528 default:
529 ShouldNotReachHere();
530 size = 0; // unreachable
531 }
532 } else {
533 size = i->get(31, 31);
534 }
535
536 size = 4 << size;
537 guarantee(_offset % size == 0, "bad offset");
538 i->sf(_offset / size, 21, 15);
539 i->srf(_base, 5);
540 }
541
542 void encode_nontemporal_pair(Instruction_aarch64 *i) const {
543 // Only base + offset is allowed
544 i->f(0b000, 25, 23);
545 unsigned size = i->get(31, 31);
546 size = 4 << size;
547 guarantee(_offset % size == 0, "bad offset");
548 i->sf(_offset / size, 21, 15);
549 i->srf(_base, 5);
550 guarantee(_mode == Address::base_plus_offset,
551 "Bad addressing mode for non-temporal op");
552 }
553
554 void lea(MacroAssembler *, Register) const;
555
556 static bool offset_ok_for_immed(int64_t offset, uint shift = 0);
557 };
558
559 // Convience classes
560 class RuntimeAddress: public Address {
561
562 public:
563
564 RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
565
566 };
567
568 class OopAddress: public Address {
569
570 public:
571
572 OopAddress(address target) : Address(target, relocInfo::oop_type){}
573
574 };
575
576 class ExternalAddress: public Address {
577 private:
578 static relocInfo::relocType reloc_for_target(address target) {
579 // Sometimes ExternalAddress is used for values which aren't
580 // exactly addresses, like the card table base.
581 // external_word_type can't be used for values in the first page
582 // so just skip the reloc in that case.
583 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
584 }
585
586 public:
587
588 ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
589
590 };
591
592 class InternalAddress: public Address {
593
594 public:
595
596 InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
597 };
598
599 const int FPUStateSizeInWords = FloatRegisterImpl::number_of_registers *
600 FloatRegisterImpl::save_slots_per_register;
601
602 typedef enum {
603 PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
604 PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
605 PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
606 } prfop;
607
608 class Assembler : public AbstractAssembler {
609
610 #ifndef PRODUCT
611 static const unsigned long asm_bp;
612
613 void emit_long(jint x) {
614 if ((unsigned long)pc() == asm_bp)
615 asm volatile ("nop");
616 AbstractAssembler::emit_int32(x);
617 }
618 #else
619 void emit_long(jint x) {
620 AbstractAssembler::emit_int32(x);
621 }
622 #endif
623
624 public:
625
626 enum { instruction_size = 4 };
627
628 Address adjust(Register base, int offset, bool preIncrement) {
629 if (preIncrement)
630 return Address(Pre(base, offset));
631 else
632 return Address(Post(base, offset));
633 }
634
635 Address pre(Register base, int offset) {
636 return adjust(base, offset, true);
637 }
638
639 Address post(Register base, int offset) {
640 return adjust(base, offset, false);
641 }
642
643 Address post(Register base, Register idx) {
644 return Address(Post(base, idx));
645 }
646
647 Instruction_aarch64* current;
648
649 void set_current(Instruction_aarch64* i) { current = i; }
650
651 void f(unsigned val, int msb, int lsb) {
652 current->f(val, msb, lsb);
653 }
654 void f(unsigned val, int msb) {
655 current->f(val, msb, msb);
656 }
657 void sf(long val, int msb, int lsb) {
658 current->sf(val, msb, lsb);
659 }
660 void rf(Register reg, int lsb) {
661 current->rf(reg, lsb);
662 }
663 void srf(Register reg, int lsb) {
664 current->srf(reg, lsb);
665 }
666 void zrf(Register reg, int lsb) {
667 current->zrf(reg, lsb);
668 }
669 void rf(FloatRegister reg, int lsb) {
670 current->rf(reg, lsb);
671 }
672 void fixed(unsigned value, unsigned mask) {
673 current->fixed(value, mask);
674 }
675
676 void emit() {
677 emit_long(current->get_insn());
678 assert_cond(current->get_bits() == 0xffffffff);
679 current = NULL;
680 }
681
682 typedef void (Assembler::* uncond_branch_insn)(address dest);
683 typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
684 typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
685 typedef void (Assembler::* prefetch_insn)(address target, prfop);
686
687 void wrap_label(Label &L, uncond_branch_insn insn);
688 void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
689 void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
690 void wrap_label(Label &L, prfop, prefetch_insn insn);
691
692 // PC-rel. addressing
693
694 void adr(Register Rd, address dest);
695 void _adrp(Register Rd, address dest);
696
697 void adr(Register Rd, const Address &dest);
698 void _adrp(Register Rd, const Address &dest);
699
700 void adr(Register Rd, Label &L) {
701 wrap_label(Rd, L, &Assembler::Assembler::adr);
702 }
703 void _adrp(Register Rd, Label &L) {
704 wrap_label(Rd, L, &Assembler::_adrp);
705 }
706
707 void adrp(Register Rd, const Address &dest, unsigned long &offset);
708
709 #undef INSN
710
711 void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
712 int negated_op);
713
714 // Add/subtract (immediate)
715 #define INSN(NAME, decode, negated) \
716 void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \
717 starti; \
718 f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
719 zrf(Rd, 0), srf(Rn, 5); \
720 } \
721 \
722 void NAME(Register Rd, Register Rn, unsigned imm) { \
723 starti; \
724 add_sub_immediate(Rd, Rn, imm, decode, negated); \
725 }
726
727 INSN(addsw, 0b001, 0b011);
728 INSN(subsw, 0b011, 0b001);
729 INSN(adds, 0b101, 0b111);
730 INSN(subs, 0b111, 0b101);
731
732 #undef INSN
733
734 #define INSN(NAME, decode, negated) \
735 void NAME(Register Rd, Register Rn, unsigned imm) { \
736 starti; \
737 add_sub_immediate(Rd, Rn, imm, decode, negated); \
738 }
739
740 INSN(addw, 0b000, 0b010);
741 INSN(subw, 0b010, 0b000);
742 INSN(add, 0b100, 0b110);
743 INSN(sub, 0b110, 0b100);
744
745 #undef INSN
746
747 // Logical (immediate)
748 #define INSN(NAME, decode, is32) \
749 void NAME(Register Rd, Register Rn, uint64_t imm) { \
750 starti; \
751 uint32_t val = encode_logical_immediate(is32, imm); \
752 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
753 srf(Rd, 0), zrf(Rn, 5); \
754 }
755
756 INSN(andw, 0b000, true);
757 INSN(orrw, 0b001, true);
758 INSN(eorw, 0b010, true);
759 INSN(andr, 0b100, false);
760 INSN(orr, 0b101, false);
761 INSN(eor, 0b110, false);
762
763 #undef INSN
764
765 #define INSN(NAME, decode, is32) \
766 void NAME(Register Rd, Register Rn, uint64_t imm) { \
767 starti; \
768 uint32_t val = encode_logical_immediate(is32, imm); \
769 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
770 zrf(Rd, 0), zrf(Rn, 5); \
771 }
772
773 INSN(ands, 0b111, false);
774 INSN(andsw, 0b011, true);
775
776 #undef INSN
777
778 // Move wide (immediate)
779 #define INSN(NAME, opcode) \
780 void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \
781 assert_cond((shift/16)*16 == shift); \
782 starti; \
783 f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \
784 f(imm, 20, 5); \
785 rf(Rd, 0); \
786 }
787
788 INSN(movnw, 0b000);
789 INSN(movzw, 0b010);
790 INSN(movkw, 0b011);
791 INSN(movn, 0b100);
792 INSN(movz, 0b110);
793 INSN(movk, 0b111);
794
795 #undef INSN
796
797 // Bitfield
798 #define INSN(NAME, opcode, size) \
799 void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \
800 starti; \
801 guarantee(size == 1 || (immr < 32 && imms < 32), "incorrect immr/imms");\
802 f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \
803 zrf(Rn, 5), rf(Rd, 0); \
804 }
805
806 INSN(sbfmw, 0b0001001100, 0);
807 INSN(bfmw, 0b0011001100, 0);
808 INSN(ubfmw, 0b0101001100, 0);
809 INSN(sbfm, 0b1001001101, 1);
810 INSN(bfm, 0b1011001101, 1);
811 INSN(ubfm, 0b1101001101, 1);
812
813 #undef INSN
814
815 // Extract
816 #define INSN(NAME, opcode, size) \
817 void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \
818 starti; \
819 guarantee(size == 1 || imms < 32, "incorrect imms"); \
820 f(opcode, 31, 21), f(imms, 15, 10); \
821 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
822 }
823
824 INSN(extrw, 0b00010011100, 0);
825 INSN(extr, 0b10010011110, 1);
826
827 #undef INSN
828
829 // The maximum range of a branch is fixed for the AArch64
830 // architecture. In debug mode we shrink it in order to test
831 // trampolines, but not so small that branches in the interpreter
832 // are out of range.
833 static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
834
835 static bool reachable_from_branch_at(address branch, address target) {
836 return uabs(target - branch) < branch_range;
837 }
838
839 // Unconditional branch (immediate)
840 #define INSN(NAME, opcode) \
841 void NAME(address dest) { \
842 starti; \
843 long offset = (dest - pc()) >> 2; \
844 DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
845 f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \
846 } \
847 void NAME(Label &L) { \
848 wrap_label(L, &Assembler::NAME); \
849 } \
850 void NAME(const Address &dest);
851
852 INSN(b, 0);
853 INSN(bl, 1);
854
855 #undef INSN
856
857 // Compare & branch (immediate)
858 #define INSN(NAME, opcode) \
859 void NAME(Register Rt, address dest) { \
860 long offset = (dest - pc()) >> 2; \
861 starti; \
862 f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \
863 } \
864 void NAME(Register Rt, Label &L) { \
865 wrap_label(Rt, L, &Assembler::NAME); \
866 }
867
868 INSN(cbzw, 0b00110100);
869 INSN(cbnzw, 0b00110101);
870 INSN(cbz, 0b10110100);
871 INSN(cbnz, 0b10110101);
872
873 #undef INSN
874
875 // Test & branch (immediate)
876 #define INSN(NAME, opcode) \
877 void NAME(Register Rt, int bitpos, address dest) { \
878 long offset = (dest - pc()) >> 2; \
879 int b5 = bitpos >> 5; \
880 bitpos &= 0x1f; \
881 starti; \
882 f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
883 rf(Rt, 0); \
884 } \
885 void NAME(Register Rt, int bitpos, Label &L) { \
886 wrap_label(Rt, bitpos, L, &Assembler::NAME); \
887 }
888
889 INSN(tbz, 0b0110110);
890 INSN(tbnz, 0b0110111);
891
892 #undef INSN
893
894 // Conditional branch (immediate)
895 enum Condition
896 {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
897
898 void br(Condition cond, address dest) {
899 long offset = (dest - pc()) >> 2;
900 starti;
901 f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
902 }
903
904 #define INSN(NAME, cond) \
905 void NAME(address dest) { \
906 br(cond, dest); \
907 }
908
909 INSN(beq, EQ);
910 INSN(bne, NE);
911 INSN(bhs, HS);
912 INSN(bcs, CS);
913 INSN(blo, LO);
914 INSN(bcc, CC);
915 INSN(bmi, MI);
916 INSN(bpl, PL);
917 INSN(bvs, VS);
918 INSN(bvc, VC);
919 INSN(bhi, HI);
920 INSN(bls, LS);
921 INSN(bge, GE);
922 INSN(blt, LT);
923 INSN(bgt, GT);
924 INSN(ble, LE);
925 INSN(bal, AL);
926 INSN(bnv, NV);
927
928 void br(Condition cc, Label &L);
929
930 #undef INSN
931
932 // Exception generation
933 void generate_exception(int opc, int op2, int LL, unsigned imm) {
934 starti;
935 f(0b11010100, 31, 24);
936 f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
937 }
938
939 #define INSN(NAME, opc, op2, LL) \
940 void NAME(unsigned imm) { \
941 generate_exception(opc, op2, LL, imm); \
942 }
943
944 INSN(svc, 0b000, 0, 0b01);
945 INSN(hvc, 0b000, 0, 0b10);
946 INSN(smc, 0b000, 0, 0b11);
947 INSN(brk, 0b001, 0, 0b00);
948 INSN(hlt, 0b010, 0, 0b00);
949 INSN(dpcs1, 0b101, 0, 0b01);
950 INSN(dpcs2, 0b101, 0, 0b10);
951 INSN(dpcs3, 0b101, 0, 0b11);
952
953 #undef INSN
954
955 // System
956 void system(int op0, int op1, int CRn, int CRm, int op2,
957 Register rt = dummy_reg)
958 {
959 starti;
960 f(0b11010101000, 31, 21);
961 f(op0, 20, 19);
962 f(op1, 18, 16);
963 f(CRn, 15, 12);
964 f(CRm, 11, 8);
965 f(op2, 7, 5);
966 rf(rt, 0);
967 }
968
969 void hint(int imm) {
970 system(0b00, 0b011, 0b0010, 0b0000, imm);
971 }
972
973 void nop() {
974 hint(0);
975 }
976
977 void yield() {
978 hint(1);
979 }
980
981 void wfe() {
982 hint(2);
983 }
984
985 void wfi() {
986 hint(3);
987 }
988
989 void sev() {
990 hint(4);
991 }
992
993 void sevl() {
994 hint(5);
995 }
996
997 // we only provide mrs and msr for the special purpose system
998 // registers where op1 (instr[20:19]) == 11 and, (currently) only
999 // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
1000
1001 void msr(int op1, int CRn, int CRm, int op2, Register rt) {
1002 starti;
1003 f(0b1101010100011, 31, 19);
1004 f(op1, 18, 16);
1005 f(CRn, 15, 12);
1006 f(CRm, 11, 8);
1007 f(op2, 7, 5);
1008 // writing zr is ok
1009 zrf(rt, 0);
1010 }
1011
1012 void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1013 starti;
1014 f(0b1101010100111, 31, 19);
1015 f(op1, 18, 16);
1016 f(CRn, 15, 12);
1017 f(CRm, 11, 8);
1018 f(op2, 7, 5);
1019 // reading to zr is a mistake
1020 rf(rt, 0);
1021 }
1022
1023 enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1024 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1025
1026 void dsb(barrier imm) {
1027 system(0b00, 0b011, 0b00011, imm, 0b100);
1028 }
1029
1030 void dmb(barrier imm) {
1031 system(0b00, 0b011, 0b00011, imm, 0b101);
1032 }
1033
1034 void isb() {
1035 system(0b00, 0b011, 0b00011, SY, 0b110);
1036 }
1037
1038 void sys(int op1, int CRn, int CRm, int op2,
1039 Register rt = (Register)0b11111) {
1040 system(0b01, op1, CRn, CRm, op2, rt);
1041 }
1042
1043 // Only implement operations accessible from EL0 or higher, i.e.,
1044 // op1 CRn CRm op2
1045 // IC IVAU 3 7 5 1
1046 // DC CVAC 3 7 10 1
1047 // DC CVAU 3 7 11 1
1048 // DC CIVAC 3 7 14 1
1049 // DC ZVA 3 7 4 1
1050 // So only deal with the CRm field.
1051 enum icache_maintenance {IVAU = 0b0101};
1052 enum dcache_maintenance {CVAC = 0b1010, CVAU = 0b1011, CIVAC = 0b1110, ZVA = 0b100};
1053
1054 void dc(dcache_maintenance cm, Register Rt) {
1055 sys(0b011, 0b0111, cm, 0b001, Rt);
1056 }
1057
1058 void ic(icache_maintenance cm, Register Rt) {
1059 sys(0b011, 0b0111, cm, 0b001, Rt);
1060 }
1061
1062 // A more convenient access to dmb for our purposes
1063 enum Membar_mask_bits {
1064 // We can use ISH for a barrier because the ARM ARM says "This
1065 // architecture assumes that all Processing Elements that use the
1066 // same operating system or hypervisor are in the same Inner
1067 // Shareable shareability domain."
1068 StoreStore = ISHST,
1069 LoadStore = ISHLD,
1070 LoadLoad = ISHLD,
1071 StoreLoad = ISH,
1072 AnyAny = ISH
1073 };
1074
1075 void membar(Membar_mask_bits order_constraint) {
1076 dmb(Assembler::barrier(order_constraint));
1077 }
1078
1079 // Unconditional branch (register)
1080 void branch_reg(Register R, int opc) {
1081 starti;
1082 f(0b1101011, 31, 25);
1083 f(opc, 24, 21);
1084 f(0b11111000000, 20, 10);
1085 rf(R, 5);
1086 f(0b00000, 4, 0);
1087 }
1088
1089 #define INSN(NAME, opc) \
1090 void NAME(Register R) { \
1091 branch_reg(R, opc); \
1092 }
1093
1094 INSN(br, 0b0000);
1095 INSN(blr, 0b0001);
1096 INSN(ret, 0b0010);
1097
1098 void ret(void *p); // This forces a compile-time error for ret(0)
1099
1100 #undef INSN
1101
1102 #define INSN(NAME, opc) \
1103 void NAME() { \
1104 branch_reg(dummy_reg, opc); \
1105 }
1106
1107 INSN(eret, 0b0100);
1108 INSN(drps, 0b0101);
1109
1110 #undef INSN
1111
1112 // Load/store exclusive
1113 enum operand_size { byte, halfword, word, xword };
1114
1115 void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1116 Register Rn, enum operand_size sz, int op, bool ordered) {
1117 starti;
1118 f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1119 rf(Rs, 16), f(ordered, 15), zrf(Rt2, 10), srf(Rn, 5), zrf(Rt1, 0);
1120 }
1121
1122 void load_exclusive(Register dst, Register addr,
1123 enum operand_size sz, bool ordered) {
1124 load_store_exclusive(dummy_reg, dst, dummy_reg, addr,
1125 sz, 0b010, ordered);
1126 }
1127
1128 void store_exclusive(Register status, Register new_val, Register addr,
1129 enum operand_size sz, bool ordered) {
1130 load_store_exclusive(status, new_val, dummy_reg, addr,
1131 sz, 0b000, ordered);
1132 }
1133
1134 #define INSN4(NAME, sz, op, o0) /* Four registers */ \
1135 void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \
1136 guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \
1137 load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \
1138 }
1139
1140 #define INSN3(NAME, sz, op, o0) /* Three registers */ \
1141 void NAME(Register Rs, Register Rt, Register Rn) { \
1142 guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
1143 load_store_exclusive(Rs, Rt, dummy_reg, Rn, sz, op, o0); \
1144 }
1145
1146 #define INSN2(NAME, sz, op, o0) /* Two registers */ \
1147 void NAME(Register Rt, Register Rn) { \
1148 load_store_exclusive(dummy_reg, Rt, dummy_reg, \
1149 Rn, sz, op, o0); \
1150 }
1151
1152 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \
1153 void NAME(Register Rt1, Register Rt2, Register Rn) { \
1154 guarantee(Rt1 != Rt2, "unpredictable instruction"); \
1155 load_store_exclusive(dummy_reg, Rt1, Rt2, Rn, sz, op, o0); \
1156 }
1157
1158 // bytes
1159 INSN3(stxrb, byte, 0b000, 0);
1160 INSN3(stlxrb, byte, 0b000, 1);
1161 INSN2(ldxrb, byte, 0b010, 0);
1162 INSN2(ldaxrb, byte, 0b010, 1);
1163 INSN2(stlrb, byte, 0b100, 1);
1164 INSN2(ldarb, byte, 0b110, 1);
1165
1166 // halfwords
1167 INSN3(stxrh, halfword, 0b000, 0);
1168 INSN3(stlxrh, halfword, 0b000, 1);
1169 INSN2(ldxrh, halfword, 0b010, 0);
1170 INSN2(ldaxrh, halfword, 0b010, 1);
1171 INSN2(stlrh, halfword, 0b100, 1);
1172 INSN2(ldarh, halfword, 0b110, 1);
1173
1174 // words
1175 INSN3(stxrw, word, 0b000, 0);
1176 INSN3(stlxrw, word, 0b000, 1);
1177 INSN4(stxpw, word, 0b001, 0);
1178 INSN4(stlxpw, word, 0b001, 1);
1179 INSN2(ldxrw, word, 0b010, 0);
1180 INSN2(ldaxrw, word, 0b010, 1);
1181 INSN_FOO(ldxpw, word, 0b011, 0);
1182 INSN_FOO(ldaxpw, word, 0b011, 1);
1183 INSN2(stlrw, word, 0b100, 1);
1184 INSN2(ldarw, word, 0b110, 1);
1185
1186 // xwords
1187 INSN3(stxr, xword, 0b000, 0);
1188 INSN3(stlxr, xword, 0b000, 1);
1189 INSN4(stxp, xword, 0b001, 0);
1190 INSN4(stlxp, xword, 0b001, 1);
1191 INSN2(ldxr, xword, 0b010, 0);
1192 INSN2(ldaxr, xword, 0b010, 1);
1193 INSN_FOO(ldxp, xword, 0b011, 0);
1194 INSN_FOO(ldaxp, xword, 0b011, 1);
1195 INSN2(stlr, xword, 0b100, 1);
1196 INSN2(ldar, xword, 0b110, 1);
1197
1198 #undef INSN2
1199 #undef INSN3
1200 #undef INSN4
1201 #undef INSN_FOO
1202
1203 // 8.1 Compare and swap extensions
1204 void lse_cas(Register Rs, Register Rt, Register Rn,
1205 enum operand_size sz, bool a, bool r, bool not_pair) {
1206 starti;
1207 if (! not_pair) { // Pair
1208 assert(sz == word || sz == xword, "invalid size");
1209 /* The size bit is in bit 30, not 31 */
1210 sz = (operand_size)(sz == word ? 0b00:0b01);
1211 }
1212 f(sz, 31, 30), f(0b001000, 29, 24), f(not_pair ? 1 : 0, 23), f(a, 22), f(1, 21);
1213 zrf(Rs, 16), f(r, 15), f(0b11111, 14, 10), srf(Rn, 5), zrf(Rt, 0);
1214 }
1215
1216 // CAS
1217 #define INSN(NAME, a, r) \
1218 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1219 assert(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
1220 lse_cas(Rs, Rt, Rn, sz, a, r, true); \
1221 }
1222 INSN(cas, false, false)
1223 INSN(casa, true, false)
1224 INSN(casl, false, true)
1225 INSN(casal, true, true)
1226 #undef INSN
1227
1228 // CASP
1229 #define INSN(NAME, a, r) \
1230 void NAME(operand_size sz, Register Rs, Register Rs1, \
1231 Register Rt, Register Rt1, Register Rn) { \
1232 assert((Rs->encoding() & 1) == 0 && (Rt->encoding() & 1) == 0 && \
1233 Rs->successor() == Rs1 && Rt->successor() == Rt1 && \
1234 Rs != Rn && Rs1 != Rn && Rs != Rt, "invalid registers"); \
1235 lse_cas(Rs, Rt, Rn, sz, a, r, false); \
1236 }
1237 INSN(casp, false, false)
1238 INSN(caspa, true, false)
1239 INSN(caspl, false, true)
1240 INSN(caspal, true, true)
1241 #undef INSN
1242
1243 // 8.1 Atomic operations
1244 void lse_atomic(Register Rs, Register Rt, Register Rn,
1245 enum operand_size sz, int op1, int op2, bool a, bool r) {
1246 starti;
1247 f(sz, 31, 30), f(0b111000, 29, 24), f(a, 23), f(r, 22), f(1, 21);
1248 zrf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), srf(Rn, 5), zrf(Rt, 0);
1249 }
1250
1251 #define INSN(NAME, NAME_A, NAME_L, NAME_AL, op1, op2) \
1252 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1253 lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, false); \
1254 } \
1255 void NAME_A(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1256 lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, false); \
1257 } \
1258 void NAME_L(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1259 lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, true); \
1260 } \
1261 void NAME_AL(operand_size sz, Register Rs, Register Rt, Register Rn) {\
1262 lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, true); \
1263 }
1264 INSN(ldadd, ldadda, ldaddl, ldaddal, 0, 0b000);
1265 INSN(ldbic, ldbica, ldbicl, ldbical, 0, 0b001);
1266 INSN(ldeor, ldeora, ldeorl, ldeoral, 0, 0b010);
1267 INSN(ldorr, ldorra, ldorrl, ldorral, 0, 0b011);
1268 INSN(ldsmax, ldsmaxa, ldsmaxl, ldsmaxal, 0, 0b100);
1269 INSN(ldsmin, ldsmina, ldsminl, ldsminal, 0, 0b101);
1270 INSN(ldumax, ldumaxa, ldumaxl, ldumaxal, 0, 0b110);
1271 INSN(ldumin, ldumina, lduminl, lduminal, 0, 0b111);
1272 INSN(swp, swpa, swpl, swpal, 1, 0b000);
1273 #undef INSN
1274
1275 // Load register (literal)
1276 #define INSN(NAME, opc, V) \
1277 void NAME(Register Rt, address dest) { \
1278 long offset = (dest - pc()) >> 2; \
1279 starti; \
1280 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1281 sf(offset, 23, 5); \
1282 rf(Rt, 0); \
1283 } \
1284 void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \
1285 InstructionMark im(this); \
1286 guarantee(rtype == relocInfo::internal_word_type, \
1287 "only internal_word_type relocs make sense here"); \
1288 code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \
1289 NAME(Rt, dest); \
1290 } \
1291 void NAME(Register Rt, Label &L) { \
1292 wrap_label(Rt, L, &Assembler::NAME); \
1293 }
1294
1295 INSN(ldrw, 0b00, 0);
1296 INSN(ldr, 0b01, 0);
1297 INSN(ldrsw, 0b10, 0);
1298
1299 #undef INSN
1300
1301 #define INSN(NAME, opc, V) \
1302 void NAME(FloatRegister Rt, address dest) { \
1303 long offset = (dest - pc()) >> 2; \
1304 starti; \
1305 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1306 sf(offset, 23, 5); \
1307 rf((Register)Rt, 0); \
1308 }
1309
1310 INSN(ldrs, 0b00, 1);
1311 INSN(ldrd, 0b01, 1);
1312 INSN(ldrq, 0b10, 1);
1313
1314 #undef INSN
1315
1316 #define INSN(NAME, opc, V) \
1317 void NAME(address dest, prfop op = PLDL1KEEP) { \
1318 long offset = (dest - pc()) >> 2; \
1319 starti; \
1320 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1321 sf(offset, 23, 5); \
1322 f(op, 4, 0); \
1323 } \
1324 void NAME(Label &L, prfop op = PLDL1KEEP) { \
1325 wrap_label(L, op, &Assembler::NAME); \
1326 }
1327
1328 INSN(prfm, 0b11, 0);
1329
1330 #undef INSN
1331
1332 // Load/store
1333 void ld_st1(int opc, int p1, int V, int L,
1334 Register Rt1, Register Rt2, Address adr, bool no_allocate) {
1335 starti;
1336 f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
1337 zrf(Rt2, 10), zrf(Rt1, 0);
1338 if (no_allocate) {
1339 adr.encode_nontemporal_pair(current);
1340 } else {
1341 adr.encode_pair(current);
1342 }
1343 }
1344
1345 // Load/store register pair (offset)
1346 #define INSN(NAME, size, p1, V, L, no_allocate) \
1347 void NAME(Register Rt1, Register Rt2, Address adr) { \
1348 ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
1349 }
1350
1351 INSN(stpw, 0b00, 0b101, 0, 0, false);
1352 INSN(ldpw, 0b00, 0b101, 0, 1, false);
1353 INSN(ldpsw, 0b01, 0b101, 0, 1, false);
1354 INSN(stp, 0b10, 0b101, 0, 0, false);
1355 INSN(ldp, 0b10, 0b101, 0, 1, false);
1356
1357 // Load/store no-allocate pair (offset)
1358 INSN(stnpw, 0b00, 0b101, 0, 0, true);
1359 INSN(ldnpw, 0b00, 0b101, 0, 1, true);
1360 INSN(stnp, 0b10, 0b101, 0, 0, true);
1361 INSN(ldnp, 0b10, 0b101, 0, 1, true);
1362
1363 #undef INSN
1364
1365 #define INSN(NAME, size, p1, V, L, no_allocate) \
1366 void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \
1367 ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \
1368 }
1369
1370 INSN(stps, 0b00, 0b101, 1, 0, false);
1371 INSN(ldps, 0b00, 0b101, 1, 1, false);
1372 INSN(stpd, 0b01, 0b101, 1, 0, false);
1373 INSN(ldpd, 0b01, 0b101, 1, 1, false);
1374 INSN(stpq, 0b10, 0b101, 1, 0, false);
1375 INSN(ldpq, 0b10, 0b101, 1, 1, false);
1376
1377 #undef INSN
1378
1379 // Load/store register (all modes)
1380 void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) {
1381 starti;
1382
1383 f(V, 26); // general reg?
1384 zrf(Rt, 0);
1385
1386 // Encoding for literal loads is done here (rather than pushed
1387 // down into Address::encode) because the encoding of this
1388 // instruction is too different from all of the other forms to
1389 // make it worth sharing.
1390 if (adr.getMode() == Address::literal) {
1391 assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
1392 assert(op == 0b01, "literal form can only be used with loads");
1393 f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
1394 long offset = (adr.target() - pc()) >> 2;
1395 sf(offset, 23, 5);
1396 code_section()->relocate(pc(), adr.rspec());
1397 return;
1398 }
1399
1400 f(size, 31, 30);
1401 f(op, 23, 22); // str
1402 adr.encode(current);
1403 }
1404
1405 #define INSN(NAME, size, op) \
1406 void NAME(Register Rt, const Address &adr) { \
1407 ld_st2(Rt, adr, size, op); \
1408 } \
1409
1410 INSN(str, 0b11, 0b00);
1411 INSN(strw, 0b10, 0b00);
1412 INSN(strb, 0b00, 0b00);
1413 INSN(strh, 0b01, 0b00);
1414
1415 INSN(ldr, 0b11, 0b01);
1416 INSN(ldrw, 0b10, 0b01);
1417 INSN(ldrb, 0b00, 0b01);
1418 INSN(ldrh, 0b01, 0b01);
1419
1420 INSN(ldrsb, 0b00, 0b10);
1421 INSN(ldrsbw, 0b00, 0b11);
1422 INSN(ldrsh, 0b01, 0b10);
1423 INSN(ldrshw, 0b01, 0b11);
1424 INSN(ldrsw, 0b10, 0b10);
1425
1426 #undef INSN
1427
1428 #define INSN(NAME, size, op) \
1429 void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \
1430 ld_st2((Register)pfop, adr, size, op); \
1431 }
1432
1433 INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
1434 // writeback modes, but the assembler
1435 // doesn't enfore that.
1436
1437 #undef INSN
1438
1439 #define INSN(NAME, size, op) \
1440 void NAME(FloatRegister Rt, const Address &adr) { \
1441 ld_st2((Register)Rt, adr, size, op, 1); \
1442 }
1443
1444 INSN(strd, 0b11, 0b00);
1445 INSN(strs, 0b10, 0b00);
1446 INSN(ldrd, 0b11, 0b01);
1447 INSN(ldrs, 0b10, 0b01);
1448 INSN(strq, 0b00, 0b10);
1449 INSN(ldrq, 0x00, 0b11);
1450
1451 #undef INSN
1452
1453 enum shift_kind { LSL, LSR, ASR, ROR };
1454
1455 void op_shifted_reg(unsigned decode,
1456 enum shift_kind kind, unsigned shift,
1457 unsigned size, unsigned op) {
1458 f(size, 31);
1459 f(op, 30, 29);
1460 f(decode, 28, 24);
1461 f(shift, 15, 10);
1462 f(kind, 23, 22);
1463 }
1464
1465 // Logical (shifted register)
1466 #define INSN(NAME, size, op, N) \
1467 void NAME(Register Rd, Register Rn, Register Rm, \
1468 enum shift_kind kind = LSL, unsigned shift = 0) { \
1469 starti; \
1470 guarantee(size == 1 || shift < 32, "incorrect shift"); \
1471 f(N, 21); \
1472 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
1473 op_shifted_reg(0b01010, kind, shift, size, op); \
1474 }
1475
1476 INSN(andr, 1, 0b00, 0);
1477 INSN(orr, 1, 0b01, 0);
1478 INSN(eor, 1, 0b10, 0);
1479 INSN(ands, 1, 0b11, 0);
1480 INSN(andw, 0, 0b00, 0);
1481 INSN(orrw, 0, 0b01, 0);
1482 INSN(eorw, 0, 0b10, 0);
1483 INSN(andsw, 0, 0b11, 0);
1484
1485 #undef INSN
1486
1487 #define INSN(NAME, size, op, N) \
1488 void NAME(Register Rd, Register Rn, Register Rm, \
1489 enum shift_kind kind = LSL, unsigned shift = 0) { \
1490 starti; \
1491 f(N, 21); \
1492 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
1493 op_shifted_reg(0b01010, kind, shift, size, op); \
1494 } \
1495 \
1496 /* These instructions have no immediate form. Provide an overload so \
1497 that if anyone does try to use an immediate operand -- this has \
1498 happened! -- we'll get a compile-time error. */ \
1499 void NAME(Register Rd, Register Rn, unsigned imm, \
1500 enum shift_kind kind = LSL, unsigned shift = 0) { \
1501 assert(false, " can't be used with immediate operand"); \
1502 }
1503
1504 INSN(bic, 1, 0b00, 1);
1505 INSN(orn, 1, 0b01, 1);
1506 INSN(eon, 1, 0b10, 1);
1507 INSN(bics, 1, 0b11, 1);
1508 INSN(bicw, 0, 0b00, 1);
1509 INSN(ornw, 0, 0b01, 1);
1510 INSN(eonw, 0, 0b10, 1);
1511 INSN(bicsw, 0, 0b11, 1);
1512
1513 #undef INSN
1514
1515 // Aliases for short forms of orn
1516 void mvn(Register Rd, Register Rm,
1517 enum shift_kind kind = LSL, unsigned shift = 0) {
1518 orn(Rd, zr, Rm, kind, shift);
1519 }
1520
1521 void mvnw(Register Rd, Register Rm,
1522 enum shift_kind kind = LSL, unsigned shift = 0) {
1523 ornw(Rd, zr, Rm, kind, shift);
1524 }
1525
1526 // Add/subtract (shifted register)
1527 #define INSN(NAME, size, op) \
1528 void NAME(Register Rd, Register Rn, Register Rm, \
1529 enum shift_kind kind, unsigned shift = 0) { \
1530 starti; \
1531 f(0, 21); \
1532 assert_cond(kind != ROR); \
1533 guarantee(size == 1 || shift < 32, "incorrect shift");\
1534 zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \
1535 op_shifted_reg(0b01011, kind, shift, size, op); \
1536 }
1537
1538 INSN(add, 1, 0b000);
1539 INSN(sub, 1, 0b10);
1540 INSN(addw, 0, 0b000);
1541 INSN(subw, 0, 0b10);
1542
1543 INSN(adds, 1, 0b001);
1544 INSN(subs, 1, 0b11);
1545 INSN(addsw, 0, 0b001);
1546 INSN(subsw, 0, 0b11);
1547
1548 #undef INSN
1549
1550 // Add/subtract (extended register)
1551 #define INSN(NAME, op) \
1552 void NAME(Register Rd, Register Rn, Register Rm, \
1553 ext::operation option, int amount = 0) { \
1554 starti; \
1555 zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \
1556 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1557 }
1558
1559 void add_sub_extended_reg(unsigned op, unsigned decode,
1560 Register Rd, Register Rn, Register Rm,
1561 unsigned opt, ext::operation option, unsigned imm) {
1562 guarantee(imm <= 4, "shift amount must be <= 4");
1563 f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
1564 f(option, 15, 13), f(imm, 12, 10);
1565 }
1566
1567 INSN(addw, 0b000);
1568 INSN(subw, 0b010);
1569 INSN(add, 0b100);
1570 INSN(sub, 0b110);
1571
1572 #undef INSN
1573
1574 #define INSN(NAME, op) \
1575 void NAME(Register Rd, Register Rn, Register Rm, \
1576 ext::operation option, int amount = 0) { \
1577 starti; \
1578 zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \
1579 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1580 }
1581
1582 INSN(addsw, 0b001);
1583 INSN(subsw, 0b011);
1584 INSN(adds, 0b101);
1585 INSN(subs, 0b111);
1586
1587 #undef INSN
1588
1589 // Aliases for short forms of add and sub
1590 #define INSN(NAME) \
1591 void NAME(Register Rd, Register Rn, Register Rm) { \
1592 if (Rd == sp || Rn == sp) \
1593 NAME(Rd, Rn, Rm, ext::uxtx); \
1594 else \
1595 NAME(Rd, Rn, Rm, LSL); \
1596 }
1597
1598 INSN(addw);
1599 INSN(subw);
1600 INSN(add);
1601 INSN(sub);
1602
1603 INSN(addsw);
1604 INSN(subsw);
1605 INSN(adds);
1606 INSN(subs);
1607
1608 #undef INSN
1609
1610 // Add/subtract (with carry)
1611 void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) {
1612 starti;
1613 f(op, 31, 29);
1614 f(0b11010000, 28, 21);
1615 f(0b000000, 15, 10);
1616 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);
1617 }
1618
1619 #define INSN(NAME, op) \
1620 void NAME(Register Rd, Register Rn, Register Rm) { \
1621 add_sub_carry(op, Rd, Rn, Rm); \
1622 }
1623
1624 INSN(adcw, 0b000);
1625 INSN(adcsw, 0b001);
1626 INSN(sbcw, 0b010);
1627 INSN(sbcsw, 0b011);
1628 INSN(adc, 0b100);
1629 INSN(adcs, 0b101);
1630 INSN(sbc,0b110);
1631 INSN(sbcs, 0b111);
1632
1633 #undef INSN
1634
1635 // Conditional compare (both kinds)
1636 void conditional_compare(unsigned op, int o1, int o2, int o3,
1637 Register Rn, unsigned imm5, unsigned nzcv,
1638 unsigned cond) {
1639 starti;
1640 f(op, 31, 29);
1641 f(0b11010010, 28, 21);
1642 f(cond, 15, 12);
1643 f(o1, 11);
1644 f(o2, 10);
1645 f(o3, 4);
1646 f(nzcv, 3, 0);
1647 f(imm5, 20, 16), zrf(Rn, 5);
1648 }
1649
1650 #define INSN(NAME, op) \
1651 void NAME(Register Rn, Register Rm, int imm, Condition cond) { \
1652 int regNumber = (Rm == zr ? 31 : (uintptr_t)Rm); \
1653 conditional_compare(op, 0, 0, 0, Rn, regNumber, imm, cond); \
1654 } \
1655 \
1656 void NAME(Register Rn, int imm5, int imm, Condition cond) { \
1657 conditional_compare(op, 1, 0, 0, Rn, imm5, imm, cond); \
1658 }
1659
1660 INSN(ccmnw, 0b001);
1661 INSN(ccmpw, 0b011);
1662 INSN(ccmn, 0b101);
1663 INSN(ccmp, 0b111);
1664
1665 #undef INSN
1666
1667 // Conditional select
1668 void conditional_select(unsigned op, unsigned op2,
1669 Register Rd, Register Rn, Register Rm,
1670 unsigned cond) {
1671 starti;
1672 f(op, 31, 29);
1673 f(0b11010100, 28, 21);
1674 f(cond, 15, 12);
1675 f(op2, 11, 10);
1676 zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0);
1677 }
1678
1679 #define INSN(NAME, op, op2) \
1680 void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
1681 conditional_select(op, op2, Rd, Rn, Rm, cond); \
1682 }
1683
1684 INSN(cselw, 0b000, 0b00);
1685 INSN(csincw, 0b000, 0b01);
1686 INSN(csinvw, 0b010, 0b00);
1687 INSN(csnegw, 0b010, 0b01);
1688 INSN(csel, 0b100, 0b00);
1689 INSN(csinc, 0b100, 0b01);
1690 INSN(csinv, 0b110, 0b00);
1691 INSN(csneg, 0b110, 0b01);
1692
1693 #undef INSN
1694
1695 // Data processing
1696 void data_processing(unsigned op29, unsigned opcode,
1697 Register Rd, Register Rn) {
1698 f(op29, 31, 29), f(0b11010110, 28, 21);
1699 f(opcode, 15, 10);
1700 rf(Rn, 5), rf(Rd, 0);
1701 }
1702
1703 // (1 source)
1704 #define INSN(NAME, op29, opcode2, opcode) \
1705 void NAME(Register Rd, Register Rn) { \
1706 starti; \
1707 f(opcode2, 20, 16); \
1708 data_processing(op29, opcode, Rd, Rn); \
1709 }
1710
1711 INSN(rbitw, 0b010, 0b00000, 0b00000);
1712 INSN(rev16w, 0b010, 0b00000, 0b00001);
1713 INSN(revw, 0b010, 0b00000, 0b00010);
1714 INSN(clzw, 0b010, 0b00000, 0b00100);
1715 INSN(clsw, 0b010, 0b00000, 0b00101);
1716
1717 INSN(rbit, 0b110, 0b00000, 0b00000);
1718 INSN(rev16, 0b110, 0b00000, 0b00001);
1719 INSN(rev32, 0b110, 0b00000, 0b00010);
1720 INSN(rev, 0b110, 0b00000, 0b00011);
1721 INSN(clz, 0b110, 0b00000, 0b00100);
1722 INSN(cls, 0b110, 0b00000, 0b00101);
1723
1724 #undef INSN
1725
1726 // (2 sources)
1727 #define INSN(NAME, op29, opcode) \
1728 void NAME(Register Rd, Register Rn, Register Rm) { \
1729 starti; \
1730 rf(Rm, 16); \
1731 data_processing(op29, opcode, Rd, Rn); \
1732 }
1733
1734 INSN(udivw, 0b000, 0b000010);
1735 INSN(sdivw, 0b000, 0b000011);
1736 INSN(lslvw, 0b000, 0b001000);
1737 INSN(lsrvw, 0b000, 0b001001);
1738 INSN(asrvw, 0b000, 0b001010);
1739 INSN(rorvw, 0b000, 0b001011);
1740
1741 INSN(udiv, 0b100, 0b000010);
1742 INSN(sdiv, 0b100, 0b000011);
1743 INSN(lslv, 0b100, 0b001000);
1744 INSN(lsrv, 0b100, 0b001001);
1745 INSN(asrv, 0b100, 0b001010);
1746 INSN(rorv, 0b100, 0b001011);
1747
1748 #undef INSN
1749
1750 // (3 sources)
1751 void data_processing(unsigned op54, unsigned op31, unsigned o0,
1752 Register Rd, Register Rn, Register Rm,
1753 Register Ra) {
1754 starti;
1755 f(op54, 31, 29), f(0b11011, 28, 24);
1756 f(op31, 23, 21), f(o0, 15);
1757 zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0);
1758 }
1759
1760 #define INSN(NAME, op54, op31, o0) \
1761 void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \
1762 data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \
1763 }
1764
1765 INSN(maddw, 0b000, 0b000, 0);
1766 INSN(msubw, 0b000, 0b000, 1);
1767 INSN(madd, 0b100, 0b000, 0);
1768 INSN(msub, 0b100, 0b000, 1);
1769 INSN(smaddl, 0b100, 0b001, 0);
1770 INSN(smsubl, 0b100, 0b001, 1);
1771 INSN(umaddl, 0b100, 0b101, 0);
1772 INSN(umsubl, 0b100, 0b101, 1);
1773
1774 #undef INSN
1775
1776 #define INSN(NAME, op54, op31, o0) \
1777 void NAME(Register Rd, Register Rn, Register Rm) { \
1778 data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \
1779 }
1780
1781 INSN(smulh, 0b100, 0b010, 0);
1782 INSN(umulh, 0b100, 0b110, 0);
1783
1784 #undef INSN
1785
1786 // Floating-point data-processing (1 source)
1787 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1788 FloatRegister Vd, FloatRegister Vn) {
1789 starti;
1790 f(op31, 31, 29);
1791 f(0b11110, 28, 24);
1792 f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10);
1793 rf(Vn, 5), rf(Vd, 0);
1794 }
1795
1796 #define INSN(NAME, op31, type, opcode) \
1797 void NAME(FloatRegister Vd, FloatRegister Vn) { \
1798 data_processing(op31, type, opcode, Vd, Vn); \
1799 }
1800
1801 private:
1802 INSN(i_fmovs, 0b000, 0b00, 0b000000);
1803 public:
1804 INSN(fabss, 0b000, 0b00, 0b000001);
1805 INSN(fnegs, 0b000, 0b00, 0b000010);
1806 INSN(fsqrts, 0b000, 0b00, 0b000011);
1807 INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision
1808
1809 private:
1810 INSN(i_fmovd, 0b000, 0b01, 0b000000);
1811 public:
1812 INSN(fabsd, 0b000, 0b01, 0b000001);
1813 INSN(fnegd, 0b000, 0b01, 0b000010);
1814 INSN(fsqrtd, 0b000, 0b01, 0b000011);
1815 INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision
1816
1817 void fmovd(FloatRegister Vd, FloatRegister Vn) {
1818 assert(Vd != Vn, "should be");
1819 i_fmovd(Vd, Vn);
1820 }
1821
1822 void fmovs(FloatRegister Vd, FloatRegister Vn) {
1823 assert(Vd != Vn, "should be");
1824 i_fmovs(Vd, Vn);
1825 }
1826
1827 #undef INSN
1828
1829 // Floating-point data-processing (2 source)
1830 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1831 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1832 starti;
1833 f(op31, 31, 29);
1834 f(0b11110, 28, 24);
1835 f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1836 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1837 }
1838
1839 #define INSN(NAME, op31, type, opcode) \
1840 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \
1841 data_processing(op31, type, opcode, Vd, Vn, Vm); \
1842 }
1843
1844 INSN(fmuls, 0b000, 0b00, 0b0000);
1845 INSN(fdivs, 0b000, 0b00, 0b0001);
1846 INSN(fadds, 0b000, 0b00, 0b0010);
1847 INSN(fsubs, 0b000, 0b00, 0b0011);
1848 INSN(fmaxs, 0b000, 0b00, 0b0100);
1849 INSN(fmins, 0b000, 0b00, 0b0101);
1850 INSN(fnmuls, 0b000, 0b00, 0b1000);
1851
1852 INSN(fmuld, 0b000, 0b01, 0b0000);
1853 INSN(fdivd, 0b000, 0b01, 0b0001);
1854 INSN(faddd, 0b000, 0b01, 0b0010);
1855 INSN(fsubd, 0b000, 0b01, 0b0011);
1856 INSN(fmaxd, 0b000, 0b01, 0b0100);
1857 INSN(fmind, 0b000, 0b01, 0b0101);
1858 INSN(fnmuld, 0b000, 0b01, 0b1000);
1859
1860 #undef INSN
1861
1862 // Floating-point data-processing (3 source)
1863 void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1864 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1865 FloatRegister Va) {
1866 starti;
1867 f(op31, 31, 29);
1868 f(0b11111, 28, 24);
1869 f(type, 23, 22), f(o1, 21), f(o0, 15);
1870 rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1871 }
1872
1873 #define INSN(NAME, op31, type, o1, o0) \
1874 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \
1875 FloatRegister Va) { \
1876 data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \
1877 }
1878
1879 INSN(fmadds, 0b000, 0b00, 0, 0);
1880 INSN(fmsubs, 0b000, 0b00, 0, 1);
1881 INSN(fnmadds, 0b000, 0b00, 1, 0);
1882 INSN(fnmsubs, 0b000, 0b00, 1, 1);
1883
1884 INSN(fmaddd, 0b000, 0b01, 0, 0);
1885 INSN(fmsubd, 0b000, 0b01, 0, 1);
1886 INSN(fnmaddd, 0b000, 0b01, 1, 0);
1887 INSN(fnmsub, 0b000, 0b01, 1, 1);
1888
1889 #undef INSN
1890
1891 // Floating-point conditional select
1892 void fp_conditional_select(unsigned op31, unsigned type,
1893 unsigned op1, unsigned op2,
1894 Condition cond, FloatRegister Vd,
1895 FloatRegister Vn, FloatRegister Vm) {
1896 starti;
1897 f(op31, 31, 29);
1898 f(0b11110, 28, 24);
1899 f(type, 23, 22);
1900 f(op1, 21, 21);
1901 f(op2, 11, 10);
1902 f(cond, 15, 12);
1903 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1904 }
1905
1906 #define INSN(NAME, op31, type, op1, op2) \
1907 void NAME(FloatRegister Vd, FloatRegister Vn, \
1908 FloatRegister Vm, Condition cond) { \
1909 fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm); \
1910 }
1911
1912 INSN(fcsels, 0b000, 0b00, 0b1, 0b11);
1913 INSN(fcseld, 0b000, 0b01, 0b1, 0b11);
1914
1915 #undef INSN
1916
1917 // Floating-point<->integer conversions
1918 void float_int_convert(unsigned op31, unsigned type,
1919 unsigned rmode, unsigned opcode,
1920 Register Rd, Register Rn) {
1921 starti;
1922 f(op31, 31, 29);
1923 f(0b11110, 28, 24);
1924 f(type, 23, 22), f(1, 21), f(rmode, 20, 19);
1925 f(opcode, 18, 16), f(0b000000, 15, 10);
1926 zrf(Rn, 5), zrf(Rd, 0);
1927 }
1928
1929 #define INSN(NAME, op31, type, rmode, opcode) \
1930 void NAME(Register Rd, FloatRegister Vn) { \
1931 float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \
1932 }
1933
1934 INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000);
1935 INSN(fcvtzs, 0b100, 0b00, 0b11, 0b000);
1936 INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000);
1937 INSN(fcvtzd, 0b100, 0b01, 0b11, 0b000);
1938
1939 INSN(fmovs, 0b000, 0b00, 0b00, 0b110);
1940 INSN(fmovd, 0b100, 0b01, 0b00, 0b110);
1941
1942 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110);
1943
1944 #undef INSN
1945
1946 #define INSN(NAME, op31, type, rmode, opcode) \
1947 void NAME(FloatRegister Vd, Register Rn) { \
1948 float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \
1949 }
1950
1951 INSN(fmovs, 0b000, 0b00, 0b00, 0b111);
1952 INSN(fmovd, 0b100, 0b01, 0b00, 0b111);
1953
1954 INSN(scvtfws, 0b000, 0b00, 0b00, 0b010);
1955 INSN(scvtfs, 0b100, 0b00, 0b00, 0b010);
1956 INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010);
1957 INSN(scvtfd, 0b100, 0b01, 0b00, 0b010);
1958
1959 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111);
1960
1961 #undef INSN
1962
1963 // Floating-point compare
1964 void float_compare(unsigned op31, unsigned type,
1965 unsigned op, unsigned op2,
1966 FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) {
1967 starti;
1968 f(op31, 31, 29);
1969 f(0b11110, 28, 24);
1970 f(type, 23, 22), f(1, 21);
1971 f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0);
1972 rf(Vn, 5), rf(Vm, 16);
1973 }
1974
1975
1976 #define INSN(NAME, op31, type, op, op2) \
1977 void NAME(FloatRegister Vn, FloatRegister Vm) { \
1978 float_compare(op31, type, op, op2, Vn, Vm); \
1979 }
1980
1981 #define INSN1(NAME, op31, type, op, op2) \
1982 void NAME(FloatRegister Vn, double d) { \
1983 assert_cond(d == 0.0); \
1984 float_compare(op31, type, op, op2, Vn); \
1985 }
1986
1987 INSN(fcmps, 0b000, 0b00, 0b00, 0b00000);
1988 INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000);
1989 // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000);
1990 // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000);
1991
1992 INSN(fcmpd, 0b000, 0b01, 0b00, 0b00000);
1993 INSN1(fcmpd, 0b000, 0b01, 0b00, 0b01000);
1994 // INSN(fcmped, 0b000, 0b01, 0b00, 0b10000);
1995 // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000);
1996
1997 #undef INSN
1998 #undef INSN1
1999
2000 // Floating-point compare. 3-registers versions (scalar).
2001 #define INSN(NAME, sz, e) \
2002 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \
2003 starti; \
2004 f(0b01111110, 31, 24), f(e, 23), f(sz, 22), f(1, 21), rf(Vm, 16); \
2005 f(0b111011, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2006 } \
2007
2008 INSN(facged, 1, 0); // facge-double
2009 INSN(facges, 0, 0); // facge-single
2010 INSN(facgtd, 1, 1); // facgt-double
2011 INSN(facgts, 0, 1); // facgt-single
2012
2013 #undef INSN
2014
2015 // Floating-point Move (immediate)
2016 private:
2017 unsigned pack(double value);
2018
2019 void fmov_imm(FloatRegister Vn, double value, unsigned size) {
2020 starti;
2021 f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21);
2022 f(pack(value), 20, 13), f(0b10000000, 12, 5);
2023 rf(Vn, 0);
2024 }
2025
2026 public:
2027
2028 void fmovs(FloatRegister Vn, double value) {
2029 if (value)
2030 fmov_imm(Vn, value, 0b00);
2031 else
2032 fmovs(Vn, zr);
2033 }
2034 void fmovd(FloatRegister Vn, double value) {
2035 if (value)
2036 fmov_imm(Vn, value, 0b01);
2037 else
2038 fmovd(Vn, zr);
2039 }
2040
2041 // Floating-point rounding
2042 // type: half-precision = 11
2043 // single = 00
2044 // double = 01
2045 // rmode: A = Away = 100
2046 // I = current = 111
2047 // M = MinusInf = 010
2048 // N = eveN = 000
2049 // P = PlusInf = 001
2050 // X = eXact = 110
2051 // Z = Zero = 011
2052 void float_round(unsigned type, unsigned rmode, FloatRegister Rd, FloatRegister Rn) {
2053 starti;
2054 f(0b00011110, 31, 24);
2055 f(type, 23, 22);
2056 f(0b1001, 21, 18);
2057 f(rmode, 17, 15);
2058 f(0b10000, 14, 10);
2059 rf(Rn, 5), rf(Rd, 0);
2060 }
2061 #define INSN(NAME, type, rmode) \
2062 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2063 float_round(type, rmode, Vd, Vn); \
2064 }
2065
2066 public:
2067 INSN(frintah, 0b11, 0b100);
2068 INSN(frintih, 0b11, 0b111);
2069 INSN(frintmh, 0b11, 0b010);
2070 INSN(frintnh, 0b11, 0b000);
2071 INSN(frintph, 0b11, 0b001);
2072 INSN(frintxh, 0b11, 0b110);
2073 INSN(frintzh, 0b11, 0b011);
2074
2075 INSN(frintas, 0b00, 0b100);
2076 INSN(frintis, 0b00, 0b111);
2077 INSN(frintms, 0b00, 0b010);
2078 INSN(frintns, 0b00, 0b000);
2079 INSN(frintps, 0b00, 0b001);
2080 INSN(frintxs, 0b00, 0b110);
2081 INSN(frintzs, 0b00, 0b011);
2082
2083 INSN(frintad, 0b01, 0b100);
2084 INSN(frintid, 0b01, 0b111);
2085 INSN(frintmd, 0b01, 0b010);
2086 INSN(frintnd, 0b01, 0b000);
2087 INSN(frintpd, 0b01, 0b001);
2088 INSN(frintxd, 0b01, 0b110);
2089 INSN(frintzd, 0b01, 0b011);
2090 #undef INSN
2091
2092 /* SIMD extensions
2093 *
2094 * We just use FloatRegister in the following. They are exactly the same
2095 * as SIMD registers.
2096 */
2097 public:
2098
2099 enum SIMD_Arrangement {
2100 T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
2101 };
2102
2103 enum SIMD_RegVariant {
2104 B, H, S, D, Q
2105 };
2106
2107 private:
2108 static short SIMD_Size_in_bytes[];
2109
2110 public:
2111 #define INSN(NAME, op) \
2112 void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \
2113 ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
2114 } \
2115
2116 INSN(ldr, 1);
2117 INSN(str, 0);
2118
2119 #undef INSN
2120
2121 private:
2122
2123 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) {
2124 starti;
2125 f(0,31), f((int)T & 1, 30);
2126 f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
2127 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2128 }
2129 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2130 int imm, int op1, int op2, int regs) {
2131
2132 bool replicate = op2 >> 2 == 3;
2133 // post-index value (imm) is formed differently for replicate/non-replicate ld* instructions
2134 int expectedImmediate = replicate ? regs * (1 << (T >> 1)) : SIMD_Size_in_bytes[T] * regs;
2135 guarantee(T < T1Q , "incorrect arrangement");
2136 guarantee(imm == expectedImmediate, "bad offset");
2137 starti;
2138 f(0,31), f((int)T & 1, 30);
2139 f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
2140 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2141 }
2142 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2143 Register Xm, int op1, int op2) {
2144 starti;
2145 f(0,31), f((int)T & 1, 30);
2146 f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
2147 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2148 }
2149
2150 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2, int regs) {
2151 switch (a.getMode()) {
2152 case Address::base_plus_offset:
2153 guarantee(a.offset() == 0, "no offset allowed here");
2154 ld_st(Vt, T, a.base(), op1, op2);
2155 break;
2156 case Address::post:
2157 ld_st(Vt, T, a.base(), a.offset(), op1, op2, regs);
2158 break;
2159 case Address::post_reg:
2160 ld_st(Vt, T, a.base(), a.index(), op1, op2);
2161 break;
2162 default:
2163 ShouldNotReachHere();
2164 }
2165 }
2166
2167 public:
2168
2169 #define INSN1(NAME, op1, op2) \
2170 void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \
2171 ld_st(Vt, T, a, op1, op2, 1); \
2172 }
2173
2174 #define INSN2(NAME, op1, op2) \
2175 void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
2176 assert(Vt->successor() == Vt2, "Registers must be ordered"); \
2177 ld_st(Vt, T, a, op1, op2, 2); \
2178 }
2179
2180 #define INSN3(NAME, op1, op2) \
2181 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
2182 SIMD_Arrangement T, const Address &a) { \
2183 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \
2184 "Registers must be ordered"); \
2185 ld_st(Vt, T, a, op1, op2, 3); \
2186 }
2187
2188 #define INSN4(NAME, op1, op2) \
2189 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
2190 FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \
2191 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \
2192 Vt3->successor() == Vt4, "Registers must be ordered"); \
2193 ld_st(Vt, T, a, op1, op2, 4); \
2194 }
2195
2196 INSN1(ld1, 0b001100010, 0b0111);
2197 INSN2(ld1, 0b001100010, 0b1010);
2198 INSN3(ld1, 0b001100010, 0b0110);
2199 INSN4(ld1, 0b001100010, 0b0010);
2200
2201 INSN2(ld2, 0b001100010, 0b1000);
2202 INSN3(ld3, 0b001100010, 0b0100);
2203 INSN4(ld4, 0b001100010, 0b0000);
2204
2205 INSN1(st1, 0b001100000, 0b0111);
2206 INSN2(st1, 0b001100000, 0b1010);
2207 INSN3(st1, 0b001100000, 0b0110);
2208 INSN4(st1, 0b001100000, 0b0010);
2209
2210 INSN2(st2, 0b001100000, 0b1000);
2211 INSN3(st3, 0b001100000, 0b0100);
2212 INSN4(st4, 0b001100000, 0b0000);
2213
2214 INSN1(ld1r, 0b001101010, 0b1100);
2215 INSN2(ld2r, 0b001101011, 0b1100);
2216 INSN3(ld3r, 0b001101010, 0b1110);
2217 INSN4(ld4r, 0b001101011, 0b1110);
2218
2219 #undef INSN1
2220 #undef INSN2
2221 #undef INSN3
2222 #undef INSN4
2223
2224 #define INSN(NAME, opc) \
2225 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2226 starti; \
2227 assert(T == T8B || T == T16B, "must be T8B or T16B"); \
2228 f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \
2229 rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2230 }
2231
2232 INSN(eor, 0b101110001);
2233 INSN(orr, 0b001110101);
2234 INSN(andr, 0b001110001);
2235 INSN(bic, 0b001110011);
2236 INSN(bif, 0b101110111);
2237 INSN(bit, 0b101110101);
2238 INSN(bsl, 0b101110011);
2239 INSN(orn, 0b001110111);
2240
2241 #undef INSN
2242
2243 #define INSN(NAME, opc, opc2, acceptT2D) \
2244 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2245 guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \
2246 if (!acceptT2D) guarantee(T != T2D, "incorrect arrangement"); \
2247 starti; \
2248 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2249 f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \
2250 rf(Vn, 5), rf(Vd, 0); \
2251 }
2252
2253 INSN(addv, 0, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2254 INSN(subv, 1, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2255 INSN(mulv, 0, 0b100111, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2256 INSN(mlav, 0, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2257 INSN(mlsv, 1, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2258 INSN(sshl, 0, 0b010001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2259 INSN(ushl, 1, 0b010001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2260 INSN(umullv, 1, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2261 INSN(umlalv, 1, 0b100000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2262
2263 #undef INSN
2264
2265 #define INSN(NAME, opc, opc2, accepted) \
2266 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2267 guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \
2268 if (accepted < 3) guarantee(T != T2D, "incorrect arrangement"); \
2269 if (accepted < 2) guarantee(T != T2S, "incorrect arrangement"); \
2270 if (accepted < 1) guarantee(T == T8B || T == T16B, "incorrect arrangement"); \
2271 starti; \
2272 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2273 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \
2274 rf(Vn, 5), rf(Vd, 0); \
2275 }
2276
2277 INSN(absr, 0, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2278 INSN(negr, 1, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2279 INSN(notr, 1, 0b100000010110, 0); // accepted arrangements: T8B, T16B
2280 INSN(addv, 0, 0b110001101110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
2281 INSN(cls, 0, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2282 INSN(clz, 1, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2283 INSN(cnt, 0, 0b100000010110, 0); // accepted arrangements: T8B, T16B
2284 INSN(uaddlp, 1, 0b100000001010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2285 INSN(uaddlv, 1, 0b110000001110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
2286
2287 #undef INSN
2288
2289 #define INSN(NAME, opc) \
2290 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2291 starti; \
2292 assert(T == T4S, "arrangement must be T4S"); \
2293 f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24), f(opc, 23), \
2294 f(T == T4S ? 0 : 1, 22), f(0b110000111110, 21, 10); rf(Vn, 5), rf(Vd, 0); \
2295 }
2296
2297 INSN(fmaxv, 0);
2298 INSN(fminv, 1);
2299
2300 #undef INSN
2301
2302 #define INSN(NAME, op0, cmode0) \
2303 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \
2304 unsigned cmode = cmode0; \
2305 unsigned op = op0; \
2306 starti; \
2307 assert(lsl == 0 || \
2308 ((T == T4H || T == T8H) && lsl == 8) || \
2309 ((T == T2S || T == T4S) && ((lsl >> 3) < 4) && ((lsl & 7) == 0)), "invalid shift");\
2310 cmode |= lsl >> 2; \
2311 if (T == T4H || T == T8H) cmode |= 0b1000; \
2312 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \
2313 assert(op == 0 && cmode0 == 0, "must be MOVI"); \
2314 cmode = 0b1110; \
2315 if (T == T1D || T == T2D) op = 1; \
2316 } \
2317 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \
2318 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \
2319 rf(Vd, 0); \
2320 }
2321
2322 INSN(movi, 0, 0);
2323 INSN(orri, 0, 1);
2324 INSN(mvni, 1, 0);
2325 INSN(bici, 1, 1);
2326
2327 #undef INSN
2328
2329 #define INSN(NAME, op1, op2, op3) \
2330 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2331 starti; \
2332 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2333 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \
2334 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2335 }
2336
2337 INSN(fadd, 0, 0, 0b110101);
2338 INSN(fdiv, 1, 0, 0b111111);
2339 INSN(fmul, 1, 0, 0b110111);
2340 INSN(fsub, 0, 1, 0b110101);
2341 INSN(fmla, 0, 0, 0b110011);
2342 INSN(fmls, 0, 1, 0b110011);
2343 INSN(fmax, 0, 0, 0b111101);
2344 INSN(fmin, 0, 1, 0b111101);
2345
2346 #undef INSN
2347
2348 #define INSN(NAME, opc) \
2349 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2350 starti; \
2351 assert(T == T4S, "arrangement must be T4S"); \
2352 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2353 }
2354
2355 INSN(sha1c, 0b000000);
2356 INSN(sha1m, 0b001000);
2357 INSN(sha1p, 0b000100);
2358 INSN(sha1su0, 0b001100);
2359 INSN(sha256h2, 0b010100);
2360 INSN(sha256h, 0b010000);
2361 INSN(sha256su1, 0b011000);
2362
2363 #undef INSN
2364
2365 #define INSN(NAME, opc) \
2366 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2367 starti; \
2368 assert(T == T4S, "arrangement must be T4S"); \
2369 f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2370 }
2371
2372 INSN(sha1h, 0b000010);
2373 INSN(sha1su1, 0b000110);
2374 INSN(sha256su0, 0b001010);
2375
2376 #undef INSN
2377
2378 #define INSN(NAME, opc) \
2379 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2380 starti; \
2381 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2382 }
2383
2384 INSN(aese, 0b0100111000101000010010);
2385 INSN(aesd, 0b0100111000101000010110);
2386 INSN(aesmc, 0b0100111000101000011010);
2387 INSN(aesimc, 0b0100111000101000011110);
2388
2389 #undef INSN
2390
2391 #define INSN(NAME, op1, op2) \
2392 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index = 0) { \
2393 starti; \
2394 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2395 assert(index >= 0 && ((T == T2D && index <= 1) || (T != T2D && index <= 3)), "invalid index"); \
2396 f(0, 31), f((int)T & 1, 30), f(op1, 29); f(0b011111, 28, 23); \
2397 f(T == T2D ? 1 : 0, 22), f(T == T2D ? 0 : index & 1, 21), rf(Vm, 16); \
2398 f(op2, 15, 12), f(T == T2D ? index : (index >> 1), 11), f(0, 10); \
2399 rf(Vn, 5), rf(Vd, 0); \
2400 }
2401
2402 // FMLA/FMLS - Vector - Scalar
2403 INSN(fmlavs, 0, 0b0001);
2404 INSN(fmlsvs, 0, 0b0101);
2405 // FMULX - Vector - Scalar
2406 INSN(fmulxvs, 1, 0b1001);
2407
2408 #undef INSN
2409
2410 // Floating-point Reciprocal Estimate
2411 void frecpe(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) {
2412 assert(type == D || type == S, "Wrong type for frecpe");
2413 starti;
2414 f(0b010111101, 31, 23);
2415 f(type == D ? 1 : 0, 22);
2416 f(0b100001110110, 21, 10);
2417 rf(Vn, 5), rf(Vd, 0);
2418 }
2419
2420 // (double) {a, b} -> (a + b)
2421 void faddpd(FloatRegister Vd, FloatRegister Vn) {
2422 starti;
2423 f(0b0111111001110000110110, 31, 10);
2424 rf(Vn, 5), rf(Vd, 0);
2425 }
2426
2427 void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
2428 starti;
2429 assert(T != Q, "invalid register variant");
2430 f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
2431 f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
2432 }
2433
2434 void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {
2435 starti;
2436 f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21);
2437 f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10);
2438 rf(Vn, 5), rf(Rd, 0);
2439 }
2440
2441 #define INSN(NAME, opc, opc2, isSHR) \
2442 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \
2443 starti; \
2444 /* The encodings for the immh:immb fields (bits 22:16) in *SHR are \
2445 * 0001 xxx 8B/16B, shift = 16 - UInt(immh:immb) \
2446 * 001x xxx 4H/8H, shift = 32 - UInt(immh:immb) \
2447 * 01xx xxx 2S/4S, shift = 64 - UInt(immh:immb) \
2448 * 1xxx xxx 1D/2D, shift = 128 - UInt(immh:immb) \
2449 * (1D is RESERVED) \
2450 * for SHL shift is calculated as: \
2451 * 0001 xxx 8B/16B, shift = UInt(immh:immb) - 8 \
2452 * 001x xxx 4H/8H, shift = UInt(immh:immb) - 16 \
2453 * 01xx xxx 2S/4S, shift = UInt(immh:immb) - 32 \
2454 * 1xxx xxx 1D/2D, shift = UInt(immh:immb) - 64 \
2455 * (1D is RESERVED) \
2456 */ \
2457 assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \
2458 int cVal = (1 << (((T >> 1) + 3) + (isSHR ? 1 : 0))); \
2459 int encodedShift = isSHR ? cVal - shift : cVal + shift; \
2460 f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23), \
2461 f(encodedShift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2462 }
2463
2464 INSN(shl, 0, 0b010101, /* isSHR = */ false);
2465 INSN(sshr, 0, 0b000001, /* isSHR = */ true);
2466 INSN(ushr, 1, 0b000001, /* isSHR = */ true);
2467
2468 #undef INSN
2469
2470 #define INSN(NAME, opc, opc2, isSHR) \
2471 void NAME(FloatRegister Vd, FloatRegister Vn, int shift){ \
2472 starti; \
2473 int encodedShift = isSHR ? 128 - shift : 64 + shift; \
2474 f(0b01, 31, 30), f(opc, 29), f(0b111110, 28, 23), \
2475 f(encodedShift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2476 }
2477
2478 INSN(shld, 0, 0b010101, /* isSHR = */ false);
2479 INSN(sshrd, 0, 0b000001, /* isSHR = */ true);
2480 INSN(ushrd, 1, 0b000001, /* isSHR = */ true);
2481
2482 #undef INSN
2483
2484 private:
2485 void _ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2486 starti;
2487 /* The encodings for the immh:immb fields (bits 22:16) are
2488 * 0001 xxx 8H, 8B/16b shift = xxx
2489 * 001x xxx 4S, 4H/8H shift = xxxx
2490 * 01xx xxx 2D, 2S/4S shift = xxxxx
2491 * 1xxx xxx RESERVED
2492 */
2493 assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
2494 assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
2495 f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16);
2496 f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2497 }
2498
2499 public:
2500 void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2501 assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement");
2502 _ushll(Vd, Ta, Vn, Tb, shift);
2503 }
2504
2505 void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2506 assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement");
2507 _ushll(Vd, Ta, Vn, Tb, shift);
2508 }
2509
2510 // Move from general purpose register
2511 // mov Vd.T[index], Rn
2512 void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
2513 starti;
2514 f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2515 f(0b000111, 15, 10), zrf(Xn, 5), rf(Vd, 0);
2516 }
2517
2518 // Move to general purpose register
2519 // mov Rd, Vn.T[index]
2520 void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
2521 guarantee(T >= T2S && T < T1Q, "only D and S arrangements are supported");
2522 starti;
2523 f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
2524 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2525 f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
2526 }
2527
2528 private:
2529 void _pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2530 starti;
2531 assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
2532 (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
2533 int size = (Ta == T1Q) ? 0b11 : 0b00;
2534 f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
2535 f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0);
2536 }
2537
2538 public:
2539 void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2540 assert(Tb == T1D || Tb == T8B, "pmull assumes T1D or T8B as the second size specifier");
2541 _pmull(Vd, Ta, Vn, Vm, Tb);
2542 }
2543
2544 void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2545 assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
2546 _pmull(Vd, Ta, Vn, Vm, Tb);
2547 }
2548
2549 void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
2550 starti;
2551 int size_b = (int)Tb >> 1;
2552 int size_a = (int)Ta >> 1;
2553 assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
2554 f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
2555 f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
2556 }
2557
2558 void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
2559 {
2560 starti;
2561 assert(T != T1D, "reserved encoding");
2562 f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2563 f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), zrf(Xs, 5), rf(Vd, 0);
2564 }
2565
2566 void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
2567 {
2568 starti;
2569 assert(T != T1D, "reserved encoding");
2570 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2571 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2572 f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2573 }
2574
2575 // AdvSIMD ZIP/UZP/TRN
2576 #define INSN(NAME, opcode) \
2577 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2578 guarantee(T != T1D && T != T1Q, "invalid arrangement"); \
2579 starti; \
2580 f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0, 15); \
2581 f(opcode, 14, 12), f(0b10, 11, 10); \
2582 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); \
2583 f(T & 1, 30), f(T >> 1, 23, 22); \
2584 }
2585
2586 INSN(uzp1, 0b001);
2587 INSN(trn1, 0b010);
2588 INSN(zip1, 0b011);
2589 INSN(uzp2, 0b101);
2590 INSN(trn2, 0b110);
2591 INSN(zip2, 0b111);
2592
2593 #undef INSN
2594
2595 // CRC32 instructions
2596 #define INSN(NAME, c, sf, sz) \
2597 void NAME(Register Rd, Register Rn, Register Rm) { \
2598 starti; \
2599 f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12); \
2600 f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
2601 }
2602
2603 INSN(crc32b, 0, 0, 0b00);
2604 INSN(crc32h, 0, 0, 0b01);
2605 INSN(crc32w, 0, 0, 0b10);
2606 INSN(crc32x, 0, 1, 0b11);
2607 INSN(crc32cb, 1, 0, 0b00);
2608 INSN(crc32ch, 1, 0, 0b01);
2609 INSN(crc32cw, 1, 0, 0b10);
2610 INSN(crc32cx, 1, 1, 0b11);
2611
2612 #undef INSN
2613
2614 // Table vector lookup
2615 #define INSN(NAME, op) \
2616 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \
2617 starti; \
2618 assert(T == T8B || T == T16B, "invalid arrangement"); \
2619 assert(0 < registers && registers <= 4, "invalid number of registers"); \
2620 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \
2621 f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2622 }
2623
2624 INSN(tbl, 0);
2625 INSN(tbx, 1);
2626
2627 #undef INSN
2628
2629 // AdvSIMD two-reg misc
2630 #define INSN(NAME, U, opcode) \
2631 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2632 starti; \
2633 assert((ASSERTION), MSG); \
2634 f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24); \
2635 f((int)(T >> 1), 23, 22), f(0b10000, 21, 17), f(opcode, 16, 12); \
2636 f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2637 }
2638
2639 #define MSG "invalid arrangement"
2640
2641 #define ASSERTION (T == T2S || T == T4S || T == T2D)
2642 INSN(fsqrt, 1, 0b11111);
2643 INSN(fabs, 0, 0b01111);
2644 INSN(fneg, 1, 0b01111);
2645 #undef ASSERTION
2646
2647 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
2648 INSN(rev64, 0, 0b00000);
2649 #undef ASSERTION
2650
2651 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
2652 INSN(rev32, 1, 0b00000);
2653 private:
2654 INSN(_rbit, 1, 0b00101);
2655 public:
2656
2657 #undef ASSERTION
2658
2659 #define ASSERTION (T == T8B || T == T16B)
2660 INSN(rev16, 0, 0b00001);
2661 // RBIT only allows T8B and T16B but encodes them oddly. Argh...
2662 void rbit(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
2663 assert((ASSERTION), MSG);
2664 _rbit(Vd, SIMD_Arrangement((T & 1) | 0b010), Vn);
2665 }
2666 #undef ASSERTION
2667
2668 #undef MSG
2669
2670 #undef INSN
2671
2672 void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
2673 {
2674 starti;
2675 assert(T == T8B || T == T16B, "invalid arrangement");
2676 assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
2677 f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
2678 rf(Vm, 16), f(0, 15), f(index, 14, 11);
2679 f(0, 10), rf(Vn, 5), rf(Vd, 0);
2680 }
2681
2682 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2683 }
2684
2685 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2686 Register tmp,
2687 int offset) {
2688 ShouldNotCallThis();
2689 return RegisterOrConstant();
2690 }
2691
2692 // Stack overflow checking
2693 virtual void bang_stack_with_offset(int offset);
2694
2695 static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
2696 static bool operand_valid_for_add_sub_immediate(long imm);
2697 static bool operand_valid_for_float_immediate(double imm);
2698
2699 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
2700 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
2701 };
2702
2703 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
2704 Assembler::Membar_mask_bits b) {
2705 return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
2706 }
2707
2708 Instruction_aarch64::~Instruction_aarch64() {
2709 assem->emit();
2710 }
2711
2712 #undef starti
2713
2714 // Invert a condition
2715 inline const Assembler::Condition operator~(const Assembler::Condition cond) {
2716 return Assembler::Condition(int(cond) ^ 1);
2717 }
2718
2719 class BiasedLockingCounters;
2720
2721 extern "C" void das(uint64_t start, int len);
2722
2723 #endif // CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP