1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "gc/shared/barrierSet.hpp"
31 #include "gc/shared/barrierSetAssembler.hpp"
32 #include "gc/shared/collectedHeap.inline.hpp"
33 #include "interpreter/interpreter.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "memory/universe.hpp"
36 #include "oops/accessDecorators.hpp"
37 #include "oops/compressedOops.inline.hpp"
38 #include "oops/klass.inline.hpp"
39 #include "prims/methodHandles.hpp"
40 #include "runtime/biasedLocking.hpp"
41 #include "runtime/flags/flagSetting.hpp"
42 #include "runtime/interfaceSupport.inline.hpp"
43 #include "runtime/objectMonitor.hpp"
44 #include "runtime/os.hpp"
45 #include "runtime/safepoint.hpp"
46 #include "runtime/safepointMechanism.hpp"
47 #include "runtime/sharedRuntime.hpp"
48 #include "runtime/stubRoutines.hpp"
49 #include "runtime/thread.hpp"
50 #include "utilities/macros.hpp"
51 #include "crc32c.h"
52 #ifdef COMPILER2
53 #include "opto/intrinsicnode.hpp"
54 #endif
55
56 #ifdef PRODUCT
57 #define BLOCK_COMMENT(str) /* nothing */
58 #define STOP(error) stop(error)
59 #else
60 #define BLOCK_COMMENT(str) block_comment(str)
61 #define STOP(error) block_comment(error); stop(error)
62 #endif
63
64 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
65
66 #ifdef ASSERT
67 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
68 #endif
69
70 static Assembler::Condition reverse[] = {
71 Assembler::noOverflow /* overflow = 0x0 */ ,
72 Assembler::overflow /* noOverflow = 0x1 */ ,
73 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
74 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
75 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
76 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
77 Assembler::above /* belowEqual = 0x6 */ ,
78 Assembler::belowEqual /* above = 0x7 */ ,
79 Assembler::positive /* negative = 0x8 */ ,
80 Assembler::negative /* positive = 0x9 */ ,
81 Assembler::noParity /* parity = 0xa */ ,
82 Assembler::parity /* noParity = 0xb */ ,
83 Assembler::greaterEqual /* less = 0xc */ ,
84 Assembler::less /* greaterEqual = 0xd */ ,
85 Assembler::greater /* lessEqual = 0xe */ ,
86 Assembler::lessEqual /* greater = 0xf, */
87
88 };
89
90
91 // Implementation of MacroAssembler
92
93 // First all the versions that have distinct versions depending on 32/64 bit
94 // Unless the difference is trivial (1 line or so).
95
96 #ifndef _LP64
97
98 // 32bit versions
99
100 Address MacroAssembler::as_Address(AddressLiteral adr) {
101 return Address(adr.target(), adr.rspec());
102 }
103
104 Address MacroAssembler::as_Address(ArrayAddress adr) {
105 return Address::make_array(adr);
106 }
107
108 void MacroAssembler::call_VM_leaf_base(address entry_point,
109 int number_of_arguments) {
110 call(RuntimeAddress(entry_point));
111 increment(rsp, number_of_arguments * wordSize);
112 }
113
114 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
115 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
116 }
117
118 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
119 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
120 }
121
122 void MacroAssembler::cmpoop_raw(Address src1, jobject obj) {
123 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
124 }
125
126 void MacroAssembler::cmpoop_raw(Register src1, jobject obj) {
127 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
128 }
129
130 void MacroAssembler::cmpoop(Address src1, jobject obj) {
131 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
132 bs->obj_equals(this, src1, obj);
133 }
134
135 void MacroAssembler::cmpoop(Register src1, jobject obj) {
136 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
137 bs->obj_equals(this, src1, obj);
138 }
139
140 void MacroAssembler::extend_sign(Register hi, Register lo) {
141 // According to Intel Doc. AP-526, "Integer Divide", p.18.
142 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
143 cdql();
144 } else {
145 movl(hi, lo);
146 sarl(hi, 31);
147 }
148 }
149
150 void MacroAssembler::jC2(Register tmp, Label& L) {
151 // set parity bit if FPU flag C2 is set (via rax)
152 save_rax(tmp);
153 fwait(); fnstsw_ax();
154 sahf();
155 restore_rax(tmp);
156 // branch
157 jcc(Assembler::parity, L);
158 }
159
160 void MacroAssembler::jnC2(Register tmp, Label& L) {
161 // set parity bit if FPU flag C2 is set (via rax)
162 save_rax(tmp);
163 fwait(); fnstsw_ax();
164 sahf();
165 restore_rax(tmp);
166 // branch
167 jcc(Assembler::noParity, L);
168 }
169
170 // 32bit can do a case table jump in one instruction but we no longer allow the base
171 // to be installed in the Address class
172 void MacroAssembler::jump(ArrayAddress entry) {
173 jmp(as_Address(entry));
174 }
175
176 // Note: y_lo will be destroyed
177 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
178 // Long compare for Java (semantics as described in JVM spec.)
179 Label high, low, done;
180
181 cmpl(x_hi, y_hi);
182 jcc(Assembler::less, low);
183 jcc(Assembler::greater, high);
184 // x_hi is the return register
185 xorl(x_hi, x_hi);
186 cmpl(x_lo, y_lo);
187 jcc(Assembler::below, low);
188 jcc(Assembler::equal, done);
189
190 bind(high);
191 xorl(x_hi, x_hi);
192 increment(x_hi);
193 jmp(done);
194
195 bind(low);
196 xorl(x_hi, x_hi);
197 decrementl(x_hi);
198
199 bind(done);
200 }
201
202 void MacroAssembler::lea(Register dst, AddressLiteral src) {
203 mov_literal32(dst, (int32_t)src.target(), src.rspec());
204 }
205
206 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
207 // leal(dst, as_Address(adr));
208 // see note in movl as to why we must use a move
209 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
210 }
211
212 void MacroAssembler::leave() {
213 mov(rsp, rbp);
214 pop(rbp);
215 }
216
217 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
218 // Multiplication of two Java long values stored on the stack
219 // as illustrated below. Result is in rdx:rax.
220 //
221 // rsp ---> [ ?? ] \ \
222 // .... | y_rsp_offset |
223 // [ y_lo ] / (in bytes) | x_rsp_offset
224 // [ y_hi ] | (in bytes)
225 // .... |
226 // [ x_lo ] /
227 // [ x_hi ]
228 // ....
229 //
230 // Basic idea: lo(result) = lo(x_lo * y_lo)
231 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
232 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
233 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
234 Label quick;
235 // load x_hi, y_hi and check if quick
236 // multiplication is possible
237 movl(rbx, x_hi);
238 movl(rcx, y_hi);
239 movl(rax, rbx);
240 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
241 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
242 // do full multiplication
243 // 1st step
244 mull(y_lo); // x_hi * y_lo
245 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
246 // 2nd step
247 movl(rax, x_lo);
248 mull(rcx); // x_lo * y_hi
249 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
250 // 3rd step
251 bind(quick); // note: rbx, = 0 if quick multiply!
252 movl(rax, x_lo);
253 mull(y_lo); // x_lo * y_lo
254 addl(rdx, rbx); // correct hi(x_lo * y_lo)
255 }
256
257 void MacroAssembler::lneg(Register hi, Register lo) {
258 negl(lo);
259 adcl(hi, 0);
260 negl(hi);
261 }
262
263 void MacroAssembler::lshl(Register hi, Register lo) {
264 // Java shift left long support (semantics as described in JVM spec., p.305)
265 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
266 // shift value is in rcx !
267 assert(hi != rcx, "must not use rcx");
268 assert(lo != rcx, "must not use rcx");
269 const Register s = rcx; // shift count
270 const int n = BitsPerWord;
271 Label L;
272 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
273 cmpl(s, n); // if (s < n)
274 jcc(Assembler::less, L); // else (s >= n)
275 movl(hi, lo); // x := x << n
276 xorl(lo, lo);
277 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
278 bind(L); // s (mod n) < n
279 shldl(hi, lo); // x := x << s
280 shll(lo);
281 }
282
283
284 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
285 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
286 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
287 assert(hi != rcx, "must not use rcx");
288 assert(lo != rcx, "must not use rcx");
289 const Register s = rcx; // shift count
290 const int n = BitsPerWord;
291 Label L;
292 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
293 cmpl(s, n); // if (s < n)
294 jcc(Assembler::less, L); // else (s >= n)
295 movl(lo, hi); // x := x >> n
296 if (sign_extension) sarl(hi, 31);
297 else xorl(hi, hi);
298 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
299 bind(L); // s (mod n) < n
300 shrdl(lo, hi); // x := x >> s
301 if (sign_extension) sarl(hi);
302 else shrl(hi);
303 }
304
305 void MacroAssembler::movoop(Register dst, jobject obj) {
306 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
307 }
308
309 void MacroAssembler::movoop(Address dst, jobject obj) {
310 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
311 }
312
313 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
314 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
315 }
316
317 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
318 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
319 }
320
321 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
322 // scratch register is not used,
323 // it is defined to match parameters of 64-bit version of this method.
324 if (src.is_lval()) {
325 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
326 } else {
327 movl(dst, as_Address(src));
328 }
329 }
330
331 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
332 movl(as_Address(dst), src);
333 }
334
335 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
336 movl(dst, as_Address(src));
337 }
338
339 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
340 void MacroAssembler::movptr(Address dst, intptr_t src) {
341 movl(dst, src);
342 }
343
344
345 void MacroAssembler::pop_callee_saved_registers() {
346 pop(rcx);
347 pop(rdx);
348 pop(rdi);
349 pop(rsi);
350 }
351
352 void MacroAssembler::pop_fTOS() {
353 fld_d(Address(rsp, 0));
354 addl(rsp, 2 * wordSize);
355 }
356
357 void MacroAssembler::push_callee_saved_registers() {
358 push(rsi);
359 push(rdi);
360 push(rdx);
361 push(rcx);
362 }
363
364 void MacroAssembler::push_fTOS() {
365 subl(rsp, 2 * wordSize);
366 fstp_d(Address(rsp, 0));
367 }
368
369
370 void MacroAssembler::pushoop(jobject obj) {
371 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
372 }
373
374 void MacroAssembler::pushklass(Metadata* obj) {
375 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
376 }
377
378 void MacroAssembler::pushptr(AddressLiteral src) {
379 if (src.is_lval()) {
380 push_literal32((int32_t)src.target(), src.rspec());
381 } else {
382 pushl(as_Address(src));
383 }
384 }
385
386 void MacroAssembler::set_word_if_not_zero(Register dst) {
387 xorl(dst, dst);
388 set_byte_if_not_zero(dst);
389 }
390
391 static void pass_arg0(MacroAssembler* masm, Register arg) {
392 masm->push(arg);
393 }
394
395 static void pass_arg1(MacroAssembler* masm, Register arg) {
396 masm->push(arg);
397 }
398
399 static void pass_arg2(MacroAssembler* masm, Register arg) {
400 masm->push(arg);
401 }
402
403 static void pass_arg3(MacroAssembler* masm, Register arg) {
404 masm->push(arg);
405 }
406
407 #ifndef PRODUCT
408 extern "C" void findpc(intptr_t x);
409 #endif
410
411 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
412 // In order to get locks to work, we need to fake a in_VM state
413 JavaThread* thread = JavaThread::current();
414 JavaThreadState saved_state = thread->thread_state();
415 thread->set_thread_state(_thread_in_vm);
416 if (ShowMessageBoxOnError) {
417 JavaThread* thread = JavaThread::current();
418 JavaThreadState saved_state = thread->thread_state();
419 thread->set_thread_state(_thread_in_vm);
420 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
421 ttyLocker ttyl;
422 BytecodeCounter::print();
423 }
424 // To see where a verify_oop failed, get $ebx+40/X for this frame.
425 // This is the value of eip which points to where verify_oop will return.
426 if (os::message_box(msg, "Execution stopped, print registers?")) {
427 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
428 BREAKPOINT;
429 }
430 }
431 fatal("DEBUG MESSAGE: %s", msg);
432 }
433
434 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
435 ttyLocker ttyl;
436 FlagSetting fs(Debugging, true);
437 tty->print_cr("eip = 0x%08x", eip);
438 #ifndef PRODUCT
439 if ((WizardMode || Verbose) && PrintMiscellaneous) {
440 tty->cr();
441 findpc(eip);
442 tty->cr();
443 }
444 #endif
445 #define PRINT_REG(rax) \
446 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
447 PRINT_REG(rax);
448 PRINT_REG(rbx);
449 PRINT_REG(rcx);
450 PRINT_REG(rdx);
451 PRINT_REG(rdi);
452 PRINT_REG(rsi);
453 PRINT_REG(rbp);
454 PRINT_REG(rsp);
455 #undef PRINT_REG
456 // Print some words near top of staack.
457 int* dump_sp = (int*) rsp;
458 for (int col1 = 0; col1 < 8; col1++) {
459 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
460 os::print_location(tty, *dump_sp++);
461 }
462 for (int row = 0; row < 16; row++) {
463 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
464 for (int col = 0; col < 8; col++) {
465 tty->print(" 0x%08x", *dump_sp++);
466 }
467 tty->cr();
468 }
469 // Print some instructions around pc:
470 Disassembler::decode((address)eip-64, (address)eip);
471 tty->print_cr("--------");
472 Disassembler::decode((address)eip, (address)eip+32);
473 }
474
475 void MacroAssembler::stop(const char* msg) {
476 ExternalAddress message((address)msg);
477 // push address of message
478 pushptr(message.addr());
479 { Label L; call(L, relocInfo::none); bind(L); } // push eip
480 pusha(); // push registers
481 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
482 hlt();
483 }
484
485 void MacroAssembler::warn(const char* msg) {
486 push_CPU_state();
487
488 ExternalAddress message((address) msg);
489 // push address of message
490 pushptr(message.addr());
491
492 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
493 addl(rsp, wordSize); // discard argument
494 pop_CPU_state();
495 }
496
497 void MacroAssembler::print_state() {
498 { Label L; call(L, relocInfo::none); bind(L); } // push eip
499 pusha(); // push registers
500
501 push_CPU_state();
502 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
503 pop_CPU_state();
504
505 popa();
506 addl(rsp, wordSize);
507 }
508
509 #else // _LP64
510
511 // 64 bit versions
512
513 Address MacroAssembler::as_Address(AddressLiteral adr) {
514 // amd64 always does this as a pc-rel
515 // we can be absolute or disp based on the instruction type
516 // jmp/call are displacements others are absolute
517 assert(!adr.is_lval(), "must be rval");
518 assert(reachable(adr), "must be");
519 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
520
521 }
522
523 Address MacroAssembler::as_Address(ArrayAddress adr) {
524 AddressLiteral base = adr.base();
525 lea(rscratch1, base);
526 Address index = adr.index();
527 assert(index._disp == 0, "must not have disp"); // maybe it can?
528 Address array(rscratch1, index._index, index._scale, index._disp);
529 return array;
530 }
531
532 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
533 Label L, E;
534
535 #ifdef _WIN64
536 // Windows always allocates space for it's register args
537 assert(num_args <= 4, "only register arguments supported");
538 subq(rsp, frame::arg_reg_save_area_bytes);
539 #endif
540
541 // Align stack if necessary
542 testl(rsp, 15);
543 jcc(Assembler::zero, L);
544
545 subq(rsp, 8);
546 {
547 call(RuntimeAddress(entry_point));
548 }
549 addq(rsp, 8);
550 jmp(E);
551
552 bind(L);
553 {
554 call(RuntimeAddress(entry_point));
555 }
556
557 bind(E);
558
559 #ifdef _WIN64
560 // restore stack pointer
561 addq(rsp, frame::arg_reg_save_area_bytes);
562 #endif
563
564 }
565
566 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
567 assert(!src2.is_lval(), "should use cmpptr");
568
569 if (reachable(src2)) {
570 cmpq(src1, as_Address(src2));
571 } else {
572 lea(rscratch1, src2);
573 Assembler::cmpq(src1, Address(rscratch1, 0));
574 }
575 }
576
577 int MacroAssembler::corrected_idivq(Register reg) {
578 // Full implementation of Java ldiv and lrem; checks for special
579 // case as described in JVM spec., p.243 & p.271. The function
580 // returns the (pc) offset of the idivl instruction - may be needed
581 // for implicit exceptions.
582 //
583 // normal case special case
584 //
585 // input : rax: dividend min_long
586 // reg: divisor (may not be eax/edx) -1
587 //
588 // output: rax: quotient (= rax idiv reg) min_long
589 // rdx: remainder (= rax irem reg) 0
590 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
591 static const int64_t min_long = 0x8000000000000000;
592 Label normal_case, special_case;
593
594 // check for special case
595 cmp64(rax, ExternalAddress((address) &min_long));
596 jcc(Assembler::notEqual, normal_case);
597 xorl(rdx, rdx); // prepare rdx for possible special case (where
598 // remainder = 0)
599 cmpq(reg, -1);
600 jcc(Assembler::equal, special_case);
601
602 // handle normal case
603 bind(normal_case);
604 cdqq();
605 int idivq_offset = offset();
606 idivq(reg);
607
608 // normal and special case exit
609 bind(special_case);
610
611 return idivq_offset;
612 }
613
614 void MacroAssembler::decrementq(Register reg, int value) {
615 if (value == min_jint) { subq(reg, value); return; }
616 if (value < 0) { incrementq(reg, -value); return; }
617 if (value == 0) { ; return; }
618 if (value == 1 && UseIncDec) { decq(reg) ; return; }
619 /* else */ { subq(reg, value) ; return; }
620 }
621
622 void MacroAssembler::decrementq(Address dst, int value) {
623 if (value == min_jint) { subq(dst, value); return; }
624 if (value < 0) { incrementq(dst, -value); return; }
625 if (value == 0) { ; return; }
626 if (value == 1 && UseIncDec) { decq(dst) ; return; }
627 /* else */ { subq(dst, value) ; return; }
628 }
629
630 void MacroAssembler::incrementq(AddressLiteral dst) {
631 if (reachable(dst)) {
632 incrementq(as_Address(dst));
633 } else {
634 lea(rscratch1, dst);
635 incrementq(Address(rscratch1, 0));
636 }
637 }
638
639 void MacroAssembler::incrementq(Register reg, int value) {
640 if (value == min_jint) { addq(reg, value); return; }
641 if (value < 0) { decrementq(reg, -value); return; }
642 if (value == 0) { ; return; }
643 if (value == 1 && UseIncDec) { incq(reg) ; return; }
644 /* else */ { addq(reg, value) ; return; }
645 }
646
647 void MacroAssembler::incrementq(Address dst, int value) {
648 if (value == min_jint) { addq(dst, value); return; }
649 if (value < 0) { decrementq(dst, -value); return; }
650 if (value == 0) { ; return; }
651 if (value == 1 && UseIncDec) { incq(dst) ; return; }
652 /* else */ { addq(dst, value) ; return; }
653 }
654
655 // 32bit can do a case table jump in one instruction but we no longer allow the base
656 // to be installed in the Address class
657 void MacroAssembler::jump(ArrayAddress entry) {
658 lea(rscratch1, entry.base());
659 Address dispatch = entry.index();
660 assert(dispatch._base == noreg, "must be");
661 dispatch._base = rscratch1;
662 jmp(dispatch);
663 }
664
665 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
666 ShouldNotReachHere(); // 64bit doesn't use two regs
667 cmpq(x_lo, y_lo);
668 }
669
670 void MacroAssembler::lea(Register dst, AddressLiteral src) {
671 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
672 }
673
674 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
675 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
676 movptr(dst, rscratch1);
677 }
678
679 void MacroAssembler::leave() {
680 // %%% is this really better? Why not on 32bit too?
681 emit_int8((unsigned char)0xC9); // LEAVE
682 }
683
684 void MacroAssembler::lneg(Register hi, Register lo) {
685 ShouldNotReachHere(); // 64bit doesn't use two regs
686 negq(lo);
687 }
688
689 void MacroAssembler::movoop(Register dst, jobject obj) {
690 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
691 }
692
693 void MacroAssembler::movoop(Address dst, jobject obj) {
694 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
695 movq(dst, rscratch1);
696 }
697
698 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
699 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
700 }
701
702 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
703 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
704 movq(dst, rscratch1);
705 }
706
707 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
708 if (src.is_lval()) {
709 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
710 } else {
711 if (reachable(src)) {
712 movq(dst, as_Address(src));
713 } else {
714 lea(scratch, src);
715 movq(dst, Address(scratch, 0));
716 }
717 }
718 }
719
720 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
721 movq(as_Address(dst), src);
722 }
723
724 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
725 movq(dst, as_Address(src));
726 }
727
728 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
729 void MacroAssembler::movptr(Address dst, intptr_t src) {
730 mov64(rscratch1, src);
731 movq(dst, rscratch1);
732 }
733
734 // These are mostly for initializing NULL
735 void MacroAssembler::movptr(Address dst, int32_t src) {
736 movslq(dst, src);
737 }
738
739 void MacroAssembler::movptr(Register dst, int32_t src) {
740 mov64(dst, (intptr_t)src);
741 }
742
743 void MacroAssembler::pushoop(jobject obj) {
744 movoop(rscratch1, obj);
745 push(rscratch1);
746 }
747
748 void MacroAssembler::pushklass(Metadata* obj) {
749 mov_metadata(rscratch1, obj);
750 push(rscratch1);
751 }
752
753 void MacroAssembler::pushptr(AddressLiteral src) {
754 lea(rscratch1, src);
755 if (src.is_lval()) {
756 push(rscratch1);
757 } else {
758 pushq(Address(rscratch1, 0));
759 }
760 }
761
762 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
763 // we must set sp to zero to clear frame
764 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
765 // must clear fp, so that compiled frames are not confused; it is
766 // possible that we need it only for debugging
767 if (clear_fp) {
768 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
769 }
770
771 // Always clear the pc because it could have been set by make_walkable()
772 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
773 vzeroupper();
774 }
775
776 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
777 Register last_java_fp,
778 address last_java_pc) {
779 vzeroupper();
780 // determine last_java_sp register
781 if (!last_java_sp->is_valid()) {
782 last_java_sp = rsp;
783 }
784
785 // last_java_fp is optional
786 if (last_java_fp->is_valid()) {
787 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
788 last_java_fp);
789 }
790
791 // last_java_pc is optional
792 if (last_java_pc != NULL) {
793 Address java_pc(r15_thread,
794 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
795 lea(rscratch1, InternalAddress(last_java_pc));
796 movptr(java_pc, rscratch1);
797 }
798
799 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
800 }
801
802 static void pass_arg0(MacroAssembler* masm, Register arg) {
803 if (c_rarg0 != arg ) {
804 masm->mov(c_rarg0, arg);
805 }
806 }
807
808 static void pass_arg1(MacroAssembler* masm, Register arg) {
809 if (c_rarg1 != arg ) {
810 masm->mov(c_rarg1, arg);
811 }
812 }
813
814 static void pass_arg2(MacroAssembler* masm, Register arg) {
815 if (c_rarg2 != arg ) {
816 masm->mov(c_rarg2, arg);
817 }
818 }
819
820 static void pass_arg3(MacroAssembler* masm, Register arg) {
821 if (c_rarg3 != arg ) {
822 masm->mov(c_rarg3, arg);
823 }
824 }
825
826 void MacroAssembler::stop(const char* msg) {
827 if (ShowMessageBoxOnError) {
828 address rip = pc();
829 pusha(); // get regs on stack
830 lea(c_rarg1, InternalAddress(rip));
831 movq(c_rarg2, rsp); // pass pointer to regs array
832 }
833 lea(c_rarg0, ExternalAddress((address) msg));
834 andq(rsp, -16); // align stack as required by ABI
835 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
836 hlt();
837 }
838
839 void MacroAssembler::warn(const char* msg) {
840 push(rbp);
841 movq(rbp, rsp);
842 andq(rsp, -16); // align stack as required by push_CPU_state and call
843 push_CPU_state(); // keeps alignment at 16 bytes
844 lea(c_rarg0, ExternalAddress((address) msg));
845 lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
846 call(rax);
847 pop_CPU_state();
848 mov(rsp, rbp);
849 pop(rbp);
850 }
851
852 void MacroAssembler::print_state() {
853 address rip = pc();
854 pusha(); // get regs on stack
855 push(rbp);
856 movq(rbp, rsp);
857 andq(rsp, -16); // align stack as required by push_CPU_state and call
858 push_CPU_state(); // keeps alignment at 16 bytes
859
860 lea(c_rarg0, InternalAddress(rip));
861 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
862 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
863
864 pop_CPU_state();
865 mov(rsp, rbp);
866 pop(rbp);
867 popa();
868 }
869
870 #ifndef PRODUCT
871 extern "C" void findpc(intptr_t x);
872 #endif
873
874 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
875 // In order to get locks to work, we need to fake a in_VM state
876 if (ShowMessageBoxOnError) {
877 JavaThread* thread = JavaThread::current();
878 JavaThreadState saved_state = thread->thread_state();
879 thread->set_thread_state(_thread_in_vm);
880 #ifndef PRODUCT
881 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
882 ttyLocker ttyl;
883 BytecodeCounter::print();
884 }
885 #endif
886 // To see where a verify_oop failed, get $ebx+40/X for this frame.
887 // XXX correct this offset for amd64
888 // This is the value of eip which points to where verify_oop will return.
889 if (os::message_box(msg, "Execution stopped, print registers?")) {
890 print_state64(pc, regs);
891 BREAKPOINT;
892 }
893 }
894 fatal("DEBUG MESSAGE: %s", msg);
895 }
896
897 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
898 ttyLocker ttyl;
899 FlagSetting fs(Debugging, true);
900 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
901 #ifndef PRODUCT
902 tty->cr();
903 findpc(pc);
904 tty->cr();
905 #endif
906 #define PRINT_REG(rax, value) \
907 { tty->print("%s = ", #rax); os::print_location(tty, value); }
908 PRINT_REG(rax, regs[15]);
909 PRINT_REG(rbx, regs[12]);
910 PRINT_REG(rcx, regs[14]);
911 PRINT_REG(rdx, regs[13]);
912 PRINT_REG(rdi, regs[8]);
913 PRINT_REG(rsi, regs[9]);
914 PRINT_REG(rbp, regs[10]);
915 PRINT_REG(rsp, regs[11]);
916 PRINT_REG(r8 , regs[7]);
917 PRINT_REG(r9 , regs[6]);
918 PRINT_REG(r10, regs[5]);
919 PRINT_REG(r11, regs[4]);
920 PRINT_REG(r12, regs[3]);
921 PRINT_REG(r13, regs[2]);
922 PRINT_REG(r14, regs[1]);
923 PRINT_REG(r15, regs[0]);
924 #undef PRINT_REG
925 // Print some words near top of staack.
926 int64_t* rsp = (int64_t*) regs[11];
927 int64_t* dump_sp = rsp;
928 for (int col1 = 0; col1 < 8; col1++) {
929 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
930 os::print_location(tty, *dump_sp++);
931 }
932 for (int row = 0; row < 25; row++) {
933 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
934 for (int col = 0; col < 4; col++) {
935 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
936 }
937 tty->cr();
938 }
939 // Print some instructions around pc:
940 Disassembler::decode((address)pc-64, (address)pc);
941 tty->print_cr("--------");
942 Disassembler::decode((address)pc, (address)pc+32);
943 }
944
945 #endif // _LP64
946
947 // Now versions that are common to 32/64 bit
948
949 void MacroAssembler::addptr(Register dst, int32_t imm32) {
950 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
951 }
952
953 void MacroAssembler::addptr(Register dst, Register src) {
954 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
955 }
956
957 void MacroAssembler::addptr(Address dst, Register src) {
958 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
959 }
960
961 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
962 if (reachable(src)) {
963 Assembler::addsd(dst, as_Address(src));
964 } else {
965 lea(rscratch1, src);
966 Assembler::addsd(dst, Address(rscratch1, 0));
967 }
968 }
969
970 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
971 if (reachable(src)) {
972 addss(dst, as_Address(src));
973 } else {
974 lea(rscratch1, src);
975 addss(dst, Address(rscratch1, 0));
976 }
977 }
978
979 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
980 if (reachable(src)) {
981 Assembler::addpd(dst, as_Address(src));
982 } else {
983 lea(rscratch1, src);
984 Assembler::addpd(dst, Address(rscratch1, 0));
985 }
986 }
987
988 void MacroAssembler::align(int modulus) {
989 align(modulus, offset());
990 }
991
992 void MacroAssembler::align(int modulus, int target) {
993 if (target % modulus != 0) {
994 nop(modulus - (target % modulus));
995 }
996 }
997
998 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
999 // Used in sign-masking with aligned address.
1000 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1001 if (reachable(src)) {
1002 Assembler::andpd(dst, as_Address(src));
1003 } else {
1004 lea(scratch_reg, src);
1005 Assembler::andpd(dst, Address(scratch_reg, 0));
1006 }
1007 }
1008
1009 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1010 // Used in sign-masking with aligned address.
1011 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1012 if (reachable(src)) {
1013 Assembler::andps(dst, as_Address(src));
1014 } else {
1015 lea(scratch_reg, src);
1016 Assembler::andps(dst, Address(scratch_reg, 0));
1017 }
1018 }
1019
1020 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1021 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1022 }
1023
1024 void MacroAssembler::atomic_incl(Address counter_addr) {
1025 lock();
1026 incrementl(counter_addr);
1027 }
1028
1029 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1030 if (reachable(counter_addr)) {
1031 atomic_incl(as_Address(counter_addr));
1032 } else {
1033 lea(scr, counter_addr);
1034 atomic_incl(Address(scr, 0));
1035 }
1036 }
1037
1038 #ifdef _LP64
1039 void MacroAssembler::atomic_incq(Address counter_addr) {
1040 lock();
1041 incrementq(counter_addr);
1042 }
1043
1044 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1045 if (reachable(counter_addr)) {
1046 atomic_incq(as_Address(counter_addr));
1047 } else {
1048 lea(scr, counter_addr);
1049 atomic_incq(Address(scr, 0));
1050 }
1051 }
1052 #endif
1053
1054 // Writes to stack successive pages until offset reached to check for
1055 // stack overflow + shadow pages. This clobbers tmp.
1056 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1057 movptr(tmp, rsp);
1058 // Bang stack for total size given plus shadow page size.
1059 // Bang one page at a time because large size can bang beyond yellow and
1060 // red zones.
1061 Label loop;
1062 bind(loop);
1063 movl(Address(tmp, (-os::vm_page_size())), size );
1064 subptr(tmp, os::vm_page_size());
1065 subl(size, os::vm_page_size());
1066 jcc(Assembler::greater, loop);
1067
1068 // Bang down shadow pages too.
1069 // At this point, (tmp-0) is the last address touched, so don't
1070 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1071 // was post-decremented.) Skip this address by starting at i=1, and
1072 // touch a few more pages below. N.B. It is important to touch all
1073 // the way down including all pages in the shadow zone.
1074 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1075 // this could be any sized move but this is can be a debugging crumb
1076 // so the bigger the better.
1077 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1078 }
1079 }
1080
1081 void MacroAssembler::reserved_stack_check() {
1082 // testing if reserved zone needs to be enabled
1083 Label no_reserved_zone_enabling;
1084 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1085 NOT_LP64(get_thread(rsi);)
1086
1087 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1088 jcc(Assembler::below, no_reserved_zone_enabling);
1089
1090 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1091 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1092 should_not_reach_here();
1093
1094 bind(no_reserved_zone_enabling);
1095 }
1096
1097 int MacroAssembler::biased_locking_enter(Register lock_reg,
1098 Register obj_reg,
1099 Register swap_reg,
1100 Register tmp_reg,
1101 bool swap_reg_contains_mark,
1102 Label& done,
1103 Label* slow_case,
1104 BiasedLockingCounters* counters) {
1105 assert(UseBiasedLocking, "why call this otherwise?");
1106 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1107 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1108 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1109 assert(markWord::age_shift == markWord::lock_bits + markWord::biased_lock_bits, "biased locking makes assumptions about bit layout");
1110 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1111 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1112
1113 if (PrintBiasedLockingStatistics && counters == NULL) {
1114 counters = BiasedLocking::counters();
1115 }
1116 // Biased locking
1117 // See whether the lock is currently biased toward our thread and
1118 // whether the epoch is still valid
1119 // Note that the runtime guarantees sufficient alignment of JavaThread
1120 // pointers to allow age to be placed into low bits
1121 // First check to see whether biasing is even enabled for this object
1122 Label cas_label;
1123 int null_check_offset = -1;
1124 if (!swap_reg_contains_mark) {
1125 null_check_offset = offset();
1126 movptr(swap_reg, mark_addr);
1127 }
1128 movptr(tmp_reg, swap_reg);
1129 andptr(tmp_reg, markWord::biased_lock_mask_in_place);
1130 cmpptr(tmp_reg, markWord::biased_lock_pattern);
1131 jcc(Assembler::notEqual, cas_label);
1132 // The bias pattern is present in the object's header. Need to check
1133 // whether the bias owner and the epoch are both still current.
1134 #ifndef _LP64
1135 // Note that because there is no current thread register on x86_32 we
1136 // need to store off the mark word we read out of the object to
1137 // avoid reloading it and needing to recheck invariants below. This
1138 // store is unfortunate but it makes the overall code shorter and
1139 // simpler.
1140 movptr(saved_mark_addr, swap_reg);
1141 #endif
1142 if (swap_reg_contains_mark) {
1143 null_check_offset = offset();
1144 }
1145 load_prototype_header(tmp_reg, obj_reg);
1146 #ifdef _LP64
1147 orptr(tmp_reg, r15_thread);
1148 xorptr(tmp_reg, swap_reg);
1149 Register header_reg = tmp_reg;
1150 #else
1151 xorptr(tmp_reg, swap_reg);
1152 get_thread(swap_reg);
1153 xorptr(swap_reg, tmp_reg);
1154 Register header_reg = swap_reg;
1155 #endif
1156 andptr(header_reg, ~((int) markWord::age_mask_in_place));
1157 if (counters != NULL) {
1158 cond_inc32(Assembler::zero,
1159 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1160 }
1161 jcc(Assembler::equal, done);
1162
1163 Label try_revoke_bias;
1164 Label try_rebias;
1165
1166 // At this point we know that the header has the bias pattern and
1167 // that we are not the bias owner in the current epoch. We need to
1168 // figure out more details about the state of the header in order to
1169 // know what operations can be legally performed on the object's
1170 // header.
1171
1172 // If the low three bits in the xor result aren't clear, that means
1173 // the prototype header is no longer biased and we have to revoke
1174 // the bias on this object.
1175 testptr(header_reg, markWord::biased_lock_mask_in_place);
1176 jccb(Assembler::notZero, try_revoke_bias);
1177
1178 // Biasing is still enabled for this data type. See whether the
1179 // epoch of the current bias is still valid, meaning that the epoch
1180 // bits of the mark word are equal to the epoch bits of the
1181 // prototype header. (Note that the prototype header's epoch bits
1182 // only change at a safepoint.) If not, attempt to rebias the object
1183 // toward the current thread. Note that we must be absolutely sure
1184 // that the current epoch is invalid in order to do this because
1185 // otherwise the manipulations it performs on the mark word are
1186 // illegal.
1187 testptr(header_reg, markWord::epoch_mask_in_place);
1188 jccb(Assembler::notZero, try_rebias);
1189
1190 // The epoch of the current bias is still valid but we know nothing
1191 // about the owner; it might be set or it might be clear. Try to
1192 // acquire the bias of the object using an atomic operation. If this
1193 // fails we will go in to the runtime to revoke the object's bias.
1194 // Note that we first construct the presumed unbiased header so we
1195 // don't accidentally blow away another thread's valid bias.
1196 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1197 andptr(swap_reg,
1198 markWord::biased_lock_mask_in_place | markWord::age_mask_in_place | markWord::epoch_mask_in_place);
1199 #ifdef _LP64
1200 movptr(tmp_reg, swap_reg);
1201 orptr(tmp_reg, r15_thread);
1202 #else
1203 get_thread(tmp_reg);
1204 orptr(tmp_reg, swap_reg);
1205 #endif
1206 lock();
1207 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1208 // If the biasing toward our thread failed, this means that
1209 // another thread succeeded in biasing it toward itself and we
1210 // need to revoke that bias. The revocation will occur in the
1211 // interpreter runtime in the slow case.
1212 if (counters != NULL) {
1213 cond_inc32(Assembler::zero,
1214 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1215 }
1216 if (slow_case != NULL) {
1217 jcc(Assembler::notZero, *slow_case);
1218 }
1219 jmp(done);
1220
1221 bind(try_rebias);
1222 // At this point we know the epoch has expired, meaning that the
1223 // current "bias owner", if any, is actually invalid. Under these
1224 // circumstances _only_, we are allowed to use the current header's
1225 // value as the comparison value when doing the cas to acquire the
1226 // bias in the current epoch. In other words, we allow transfer of
1227 // the bias from one thread to another directly in this situation.
1228 //
1229 // FIXME: due to a lack of registers we currently blow away the age
1230 // bits in this situation. Should attempt to preserve them.
1231 load_prototype_header(tmp_reg, obj_reg);
1232 #ifdef _LP64
1233 orptr(tmp_reg, r15_thread);
1234 #else
1235 get_thread(swap_reg);
1236 orptr(tmp_reg, swap_reg);
1237 movptr(swap_reg, saved_mark_addr);
1238 #endif
1239 lock();
1240 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1241 // If the biasing toward our thread failed, then another thread
1242 // succeeded in biasing it toward itself and we need to revoke that
1243 // bias. The revocation will occur in the runtime in the slow case.
1244 if (counters != NULL) {
1245 cond_inc32(Assembler::zero,
1246 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1247 }
1248 if (slow_case != NULL) {
1249 jcc(Assembler::notZero, *slow_case);
1250 }
1251 jmp(done);
1252
1253 bind(try_revoke_bias);
1254 // The prototype mark in the klass doesn't have the bias bit set any
1255 // more, indicating that objects of this data type are not supposed
1256 // to be biased any more. We are going to try to reset the mark of
1257 // this object to the prototype value and fall through to the
1258 // CAS-based locking scheme. Note that if our CAS fails, it means
1259 // that another thread raced us for the privilege of revoking the
1260 // bias of this particular object, so it's okay to continue in the
1261 // normal locking code.
1262 //
1263 // FIXME: due to a lack of registers we currently blow away the age
1264 // bits in this situation. Should attempt to preserve them.
1265 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1266 load_prototype_header(tmp_reg, obj_reg);
1267 lock();
1268 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1269 // Fall through to the normal CAS-based lock, because no matter what
1270 // the result of the above CAS, some thread must have succeeded in
1271 // removing the bias bit from the object's header.
1272 if (counters != NULL) {
1273 cond_inc32(Assembler::zero,
1274 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1275 }
1276
1277 bind(cas_label);
1278
1279 return null_check_offset;
1280 }
1281
1282 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1283 assert(UseBiasedLocking, "why call this otherwise?");
1284
1285 // Check for biased locking unlock case, which is a no-op
1286 // Note: we do not have to check the thread ID for two reasons.
1287 // First, the interpreter checks for IllegalMonitorStateException at
1288 // a higher level. Second, if the bias was revoked while we held the
1289 // lock, the object could not be rebiased toward another thread, so
1290 // the bias bit would be clear.
1291 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1292 andptr(temp_reg, markWord::biased_lock_mask_in_place);
1293 cmpptr(temp_reg, markWord::biased_lock_pattern);
1294 jcc(Assembler::equal, done);
1295 }
1296
1297 #ifdef COMPILER2
1298
1299 #if INCLUDE_RTM_OPT
1300
1301 // Update rtm_counters based on abort status
1302 // input: abort_status
1303 // rtm_counters (RTMLockingCounters*)
1304 // flags are killed
1305 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1306
1307 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1308 if (PrintPreciseRTMLockingStatistics) {
1309 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1310 Label check_abort;
1311 testl(abort_status, (1<<i));
1312 jccb(Assembler::equal, check_abort);
1313 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1314 bind(check_abort);
1315 }
1316 }
1317 }
1318
1319 // Branch if (random & (count-1) != 0), count is 2^n
1320 // tmp, scr and flags are killed
1321 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1322 assert(tmp == rax, "");
1323 assert(scr == rdx, "");
1324 rdtsc(); // modifies EDX:EAX
1325 andptr(tmp, count-1);
1326 jccb(Assembler::notZero, brLabel);
1327 }
1328
1329 // Perform abort ratio calculation, set no_rtm bit if high ratio
1330 // input: rtm_counters_Reg (RTMLockingCounters* address)
1331 // tmpReg, rtm_counters_Reg and flags are killed
1332 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1333 Register rtm_counters_Reg,
1334 RTMLockingCounters* rtm_counters,
1335 Metadata* method_data) {
1336 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1337
1338 if (RTMLockingCalculationDelay > 0) {
1339 // Delay calculation
1340 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1341 testptr(tmpReg, tmpReg);
1342 jccb(Assembler::equal, L_done);
1343 }
1344 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1345 // Aborted transactions = abort_count * 100
1346 // All transactions = total_count * RTMTotalCountIncrRate
1347 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1348
1349 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1350 cmpptr(tmpReg, RTMAbortThreshold);
1351 jccb(Assembler::below, L_check_always_rtm2);
1352 imulptr(tmpReg, tmpReg, 100);
1353
1354 Register scrReg = rtm_counters_Reg;
1355 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1356 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1357 imulptr(scrReg, scrReg, RTMAbortRatio);
1358 cmpptr(tmpReg, scrReg);
1359 jccb(Assembler::below, L_check_always_rtm1);
1360 if (method_data != NULL) {
1361 // set rtm_state to "no rtm" in MDO
1362 mov_metadata(tmpReg, method_data);
1363 lock();
1364 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1365 }
1366 jmpb(L_done);
1367 bind(L_check_always_rtm1);
1368 // Reload RTMLockingCounters* address
1369 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1370 bind(L_check_always_rtm2);
1371 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1372 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1373 jccb(Assembler::below, L_done);
1374 if (method_data != NULL) {
1375 // set rtm_state to "always rtm" in MDO
1376 mov_metadata(tmpReg, method_data);
1377 lock();
1378 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1379 }
1380 bind(L_done);
1381 }
1382
1383 // Update counters and perform abort ratio calculation
1384 // input: abort_status_Reg
1385 // rtm_counters_Reg, flags are killed
1386 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1387 Register rtm_counters_Reg,
1388 RTMLockingCounters* rtm_counters,
1389 Metadata* method_data,
1390 bool profile_rtm) {
1391
1392 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1393 // update rtm counters based on rax value at abort
1394 // reads abort_status_Reg, updates flags
1395 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1396 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1397 if (profile_rtm) {
1398 // Save abort status because abort_status_Reg is used by following code.
1399 if (RTMRetryCount > 0) {
1400 push(abort_status_Reg);
1401 }
1402 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1403 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1404 // restore abort status
1405 if (RTMRetryCount > 0) {
1406 pop(abort_status_Reg);
1407 }
1408 }
1409 }
1410
1411 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1412 // inputs: retry_count_Reg
1413 // : abort_status_Reg
1414 // output: retry_count_Reg decremented by 1
1415 // flags are killed
1416 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1417 Label doneRetry;
1418 assert(abort_status_Reg == rax, "");
1419 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1420 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1421 // if reason is in 0x6 and retry count != 0 then retry
1422 andptr(abort_status_Reg, 0x6);
1423 jccb(Assembler::zero, doneRetry);
1424 testl(retry_count_Reg, retry_count_Reg);
1425 jccb(Assembler::zero, doneRetry);
1426 pause();
1427 decrementl(retry_count_Reg);
1428 jmp(retryLabel);
1429 bind(doneRetry);
1430 }
1431
1432 // Spin and retry if lock is busy,
1433 // inputs: box_Reg (monitor address)
1434 // : retry_count_Reg
1435 // output: retry_count_Reg decremented by 1
1436 // : clear z flag if retry count exceeded
1437 // tmp_Reg, scr_Reg, flags are killed
1438 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1439 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1440 Label SpinLoop, SpinExit, doneRetry;
1441 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1442
1443 testl(retry_count_Reg, retry_count_Reg);
1444 jccb(Assembler::zero, doneRetry);
1445 decrementl(retry_count_Reg);
1446 movptr(scr_Reg, RTMSpinLoopCount);
1447
1448 bind(SpinLoop);
1449 pause();
1450 decrementl(scr_Reg);
1451 jccb(Assembler::lessEqual, SpinExit);
1452 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1453 testptr(tmp_Reg, tmp_Reg);
1454 jccb(Assembler::notZero, SpinLoop);
1455
1456 bind(SpinExit);
1457 jmp(retryLabel);
1458 bind(doneRetry);
1459 incrementl(retry_count_Reg); // clear z flag
1460 }
1461
1462 // Use RTM for normal stack locks
1463 // Input: objReg (object to lock)
1464 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1465 Register retry_on_abort_count_Reg,
1466 RTMLockingCounters* stack_rtm_counters,
1467 Metadata* method_data, bool profile_rtm,
1468 Label& DONE_LABEL, Label& IsInflated) {
1469 assert(UseRTMForStackLocks, "why call this otherwise?");
1470 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1471 assert(tmpReg == rax, "");
1472 assert(scrReg == rdx, "");
1473 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1474
1475 if (RTMRetryCount > 0) {
1476 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1477 bind(L_rtm_retry);
1478 }
1479 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1480 testptr(tmpReg, markWord::monitor_value); // inflated vs stack-locked|neutral|biased
1481 jcc(Assembler::notZero, IsInflated);
1482
1483 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1484 Label L_noincrement;
1485 if (RTMTotalCountIncrRate > 1) {
1486 // tmpReg, scrReg and flags are killed
1487 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1488 }
1489 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1490 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1491 bind(L_noincrement);
1492 }
1493 xbegin(L_on_abort);
1494 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1495 andptr(tmpReg, markWord::biased_lock_mask_in_place); // look at 3 lock bits
1496 cmpptr(tmpReg, markWord::unlocked_value); // bits = 001 unlocked
1497 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1498
1499 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1500 if (UseRTMXendForLockBusy) {
1501 xend();
1502 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1503 jmp(L_decrement_retry);
1504 }
1505 else {
1506 xabort(0);
1507 }
1508 bind(L_on_abort);
1509 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1510 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1511 }
1512 bind(L_decrement_retry);
1513 if (RTMRetryCount > 0) {
1514 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1515 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1516 }
1517 }
1518
1519 // Use RTM for inflating locks
1520 // inputs: objReg (object to lock)
1521 // boxReg (on-stack box address (displaced header location) - KILLED)
1522 // tmpReg (ObjectMonitor address + markWord::monitor_value)
1523 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1524 Register scrReg, Register retry_on_busy_count_Reg,
1525 Register retry_on_abort_count_Reg,
1526 RTMLockingCounters* rtm_counters,
1527 Metadata* method_data, bool profile_rtm,
1528 Label& DONE_LABEL) {
1529 assert(UseRTMLocking, "why call this otherwise?");
1530 assert(tmpReg == rax, "");
1531 assert(scrReg == rdx, "");
1532 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1533 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1534
1535 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1536 movptr(Address(boxReg, 0), (int32_t)intptr_t(markWord::unused_mark().value()));
1537 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1538
1539 if (RTMRetryCount > 0) {
1540 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1541 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1542 bind(L_rtm_retry);
1543 }
1544 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1545 Label L_noincrement;
1546 if (RTMTotalCountIncrRate > 1) {
1547 // tmpReg, scrReg and flags are killed
1548 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1549 }
1550 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1551 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1552 bind(L_noincrement);
1553 }
1554 xbegin(L_on_abort);
1555 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1556 movptr(tmpReg, Address(tmpReg, owner_offset));
1557 testptr(tmpReg, tmpReg);
1558 jcc(Assembler::zero, DONE_LABEL);
1559 if (UseRTMXendForLockBusy) {
1560 xend();
1561 jmp(L_decrement_retry);
1562 }
1563 else {
1564 xabort(0);
1565 }
1566 bind(L_on_abort);
1567 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1568 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1569 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1570 }
1571 if (RTMRetryCount > 0) {
1572 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1573 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1574 }
1575
1576 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1577 testptr(tmpReg, tmpReg) ;
1578 jccb(Assembler::notZero, L_decrement_retry) ;
1579
1580 // Appears unlocked - try to swing _owner from null to non-null.
1581 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1582 #ifdef _LP64
1583 Register threadReg = r15_thread;
1584 #else
1585 get_thread(scrReg);
1586 Register threadReg = scrReg;
1587 #endif
1588 lock();
1589 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1590
1591 if (RTMRetryCount > 0) {
1592 // success done else retry
1593 jccb(Assembler::equal, DONE_LABEL) ;
1594 bind(L_decrement_retry);
1595 // Spin and retry if lock is busy.
1596 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1597 }
1598 else {
1599 bind(L_decrement_retry);
1600 }
1601 }
1602
1603 #endif // INCLUDE_RTM_OPT
1604
1605 // Fast_Lock and Fast_Unlock used by C2
1606
1607 // Because the transitions from emitted code to the runtime
1608 // monitorenter/exit helper stubs are so slow it's critical that
1609 // we inline both the stack-locking fast-path and the inflated fast path.
1610 //
1611 // See also: cmpFastLock and cmpFastUnlock.
1612 //
1613 // What follows is a specialized inline transliteration of the code
1614 // in enter() and exit(). If we're concerned about I$ bloat another
1615 // option would be to emit TrySlowEnter and TrySlowExit methods
1616 // at startup-time. These methods would accept arguments as
1617 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1618 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1619 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1620 // In practice, however, the # of lock sites is bounded and is usually small.
1621 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1622 // if the processor uses simple bimodal branch predictors keyed by EIP
1623 // Since the helper routines would be called from multiple synchronization
1624 // sites.
1625 //
1626 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1627 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1628 // to those specialized methods. That'd give us a mostly platform-independent
1629 // implementation that the JITs could optimize and inline at their pleasure.
1630 // Done correctly, the only time we'd need to cross to native could would be
1631 // to park() or unpark() threads. We'd also need a few more unsafe operators
1632 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1633 // (b) explicit barriers or fence operations.
1634 //
1635 // TODO:
1636 //
1637 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1638 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1639 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1640 // the lock operators would typically be faster than reifying Self.
1641 //
1642 // * Ideally I'd define the primitives as:
1643 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1644 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1645 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1646 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1647 // Furthermore the register assignments are overconstrained, possibly resulting in
1648 // sub-optimal code near the synchronization site.
1649 //
1650 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1651 // Alternately, use a better sp-proximity test.
1652 //
1653 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1654 // Either one is sufficient to uniquely identify a thread.
1655 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1656 //
1657 // * Intrinsify notify() and notifyAll() for the common cases where the
1658 // object is locked by the calling thread but the waitlist is empty.
1659 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1660 //
1661 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1662 // But beware of excessive branch density on AMD Opterons.
1663 //
1664 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1665 // or failure of the fast-path. If the fast-path fails then we pass
1666 // control to the slow-path, typically in C. In Fast_Lock and
1667 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1668 // will emit a conditional branch immediately after the node.
1669 // So we have branches to branches and lots of ICC.ZF games.
1670 // Instead, it might be better to have C2 pass a "FailureLabel"
1671 // into Fast_Lock and Fast_Unlock. In the case of success, control
1672 // will drop through the node. ICC.ZF is undefined at exit.
1673 // In the case of failure, the node will branch directly to the
1674 // FailureLabel
1675
1676
1677 // obj: object to lock
1678 // box: on-stack box address (displaced header location) - KILLED
1679 // rax,: tmp -- KILLED
1680 // scr: tmp -- KILLED
1681 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1682 Register scrReg, Register cx1Reg, Register cx2Reg,
1683 BiasedLockingCounters* counters,
1684 RTMLockingCounters* rtm_counters,
1685 RTMLockingCounters* stack_rtm_counters,
1686 Metadata* method_data,
1687 bool use_rtm, bool profile_rtm) {
1688 // Ensure the register assignments are disjoint
1689 assert(tmpReg == rax, "");
1690
1691 if (use_rtm) {
1692 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1693 } else {
1694 assert(cx1Reg == noreg, "");
1695 assert(cx2Reg == noreg, "");
1696 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1697 }
1698
1699 if (counters != NULL) {
1700 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1701 }
1702
1703 // Possible cases that we'll encounter in fast_lock
1704 // ------------------------------------------------
1705 // * Inflated
1706 // -- unlocked
1707 // -- Locked
1708 // = by self
1709 // = by other
1710 // * biased
1711 // -- by Self
1712 // -- by other
1713 // * neutral
1714 // * stack-locked
1715 // -- by self
1716 // = sp-proximity test hits
1717 // = sp-proximity test generates false-negative
1718 // -- by other
1719 //
1720
1721 Label IsInflated, DONE_LABEL;
1722
1723 // it's stack-locked, biased or neutral
1724 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1725 // order to reduce the number of conditional branches in the most common cases.
1726 // Beware -- there's a subtle invariant that fetch of the markword
1727 // at [FETCH], below, will never observe a biased encoding (*101b).
1728 // If this invariant is not held we risk exclusion (safety) failure.
1729 if (UseBiasedLocking && !UseOptoBiasInlining) {
1730 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1731 }
1732
1733 #if INCLUDE_RTM_OPT
1734 if (UseRTMForStackLocks && use_rtm) {
1735 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1736 stack_rtm_counters, method_data, profile_rtm,
1737 DONE_LABEL, IsInflated);
1738 }
1739 #endif // INCLUDE_RTM_OPT
1740
1741 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH]
1742 testptr(tmpReg, markWord::monitor_value); // inflated vs stack-locked|neutral|biased
1743 jccb(Assembler::notZero, IsInflated);
1744
1745 // Attempt stack-locking ...
1746 orptr (tmpReg, markWord::unlocked_value);
1747 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1748 lock();
1749 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg
1750 if (counters != NULL) {
1751 cond_inc32(Assembler::equal,
1752 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1753 }
1754 jcc(Assembler::equal, DONE_LABEL); // Success
1755
1756 // Recursive locking.
1757 // The object is stack-locked: markword contains stack pointer to BasicLock.
1758 // Locked by current thread if difference with current SP is less than one page.
1759 subptr(tmpReg, rsp);
1760 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1761 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1762 movptr(Address(boxReg, 0), tmpReg);
1763 if (counters != NULL) {
1764 cond_inc32(Assembler::equal,
1765 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1766 }
1767 jmp(DONE_LABEL);
1768
1769 bind(IsInflated);
1770 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markWord::monitor_value
1771
1772 #if INCLUDE_RTM_OPT
1773 // Use the same RTM locking code in 32- and 64-bit VM.
1774 if (use_rtm) {
1775 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1776 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1777 } else {
1778 #endif // INCLUDE_RTM_OPT
1779
1780 #ifndef _LP64
1781 // The object is inflated.
1782
1783 // boxReg refers to the on-stack BasicLock in the current frame.
1784 // We'd like to write:
1785 // set box->_displaced_header = markWord::unused_mark(). Any non-0 value suffices.
1786 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1787 // additional latency as we have another ST in the store buffer that must drain.
1788
1789 // avoid ST-before-CAS
1790 // register juggle because we need tmpReg for cmpxchgptr below
1791 movptr(scrReg, boxReg);
1792 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1793
1794 // Optimistic form: consider XORL tmpReg,tmpReg
1795 movptr(tmpReg, NULL_WORD);
1796
1797 // Appears unlocked - try to swing _owner from null to non-null.
1798 // Ideally, I'd manifest "Self" with get_thread and then attempt
1799 // to CAS the register containing Self into m->Owner.
1800 // But we don't have enough registers, so instead we can either try to CAS
1801 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1802 // we later store "Self" into m->Owner. Transiently storing a stack address
1803 // (rsp or the address of the box) into m->owner is harmless.
1804 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1805 lock();
1806 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1807 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1808 // If we weren't able to swing _owner from NULL to the BasicLock
1809 // then take the slow path.
1810 jccb (Assembler::notZero, DONE_LABEL);
1811 // update _owner from BasicLock to thread
1812 get_thread (scrReg); // beware: clobbers ICCs
1813 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1814 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1815
1816 // If the CAS fails we can either retry or pass control to the slow-path.
1817 // We use the latter tactic.
1818 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1819 // If the CAS was successful ...
1820 // Self has acquired the lock
1821 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1822 // Intentional fall-through into DONE_LABEL ...
1823 #else // _LP64
1824 // It's inflated
1825 movq(scrReg, tmpReg);
1826 xorq(tmpReg, tmpReg);
1827
1828 lock();
1829 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1830 // Unconditionally set box->_displaced_header = markWord::unused_mark().
1831 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1832 movptr(Address(boxReg, 0), (int32_t)intptr_t(markWord::unused_mark().value()));
1833 // The following code to verify that the object field still refers
1834 // to the object we are trying to lock is not needed with safepoint
1835 // based deflation. It is also not needed with async deflation when
1836 // the DEFLATER_MARKER is allowed to linger in the owner field in an
1837 // async deflated ObjectMonitor until replaced by the next owner value.
1838 // We keep this code as a sanity check against bugs in other parts
1839 // of the async deflation mechanism.
1840 //
1841 // If we weren't able to swing _owner from NULL to r15_thread
1842 // then take the slow path.
1843 jccb(Assembler::notZero, DONE_LABEL);
1844 // r15_thread is now the owner so verify that the ObjectMonitor
1845 // still refers to the same object.
1846 cmpptr(objReg, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(object)));
1847 // The ObjectMonitor still refers to the same object so
1848 // r15_thread's ownership is valid.
1849 jccb(Assembler::zero, DONE_LABEL);
1850 // The ObjectMonitor does not refer to the same object so
1851 // drop ownership.
1852 movptr(Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
1853 // Intentional fall-through into DONE_LABEL ...
1854 // Propagate ICC.ZF from cmpptr() above into DONE_LABEL.
1855 #endif // _LP64
1856 #if INCLUDE_RTM_OPT
1857 } // use_rtm()
1858 #endif
1859 // DONE_LABEL is a hot target - we'd really like to place it at the
1860 // start of cache line by padding with NOPs.
1861 // See the AMD and Intel software optimization manuals for the
1862 // most efficient "long" NOP encodings.
1863 // Unfortunately none of our alignment mechanisms suffice.
1864 bind(DONE_LABEL);
1865
1866 // At DONE_LABEL the icc ZFlag is set as follows ...
1867 // Fast_Unlock uses the same protocol.
1868 // ZFlag == 1 -> Success
1869 // ZFlag == 0 -> Failure - force control through the slow-path
1870 }
1871
1872 // obj: object to unlock
1873 // box: box address (displaced header location), killed. Must be EAX.
1874 // tmp: killed, cannot be obj nor box.
1875 //
1876 // Some commentary on balanced locking:
1877 //
1878 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1879 // Methods that don't have provably balanced locking are forced to run in the
1880 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1881 // The interpreter provides two properties:
1882 // I1: At return-time the interpreter automatically and quietly unlocks any
1883 // objects acquired the current activation (frame). Recall that the
1884 // interpreter maintains an on-stack list of locks currently held by
1885 // a frame.
1886 // I2: If a method attempts to unlock an object that is not held by the
1887 // the frame the interpreter throws IMSX.
1888 //
1889 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1890 // B() doesn't have provably balanced locking so it runs in the interpreter.
1891 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1892 // is still locked by A().
1893 //
1894 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1895 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1896 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1897 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1898 // Arguably given that the spec legislates the JNI case as undefined our implementation
1899 // could reasonably *avoid* checking owner in Fast_Unlock().
1900 // In the interest of performance we elide m->Owner==Self check in unlock.
1901 // A perfectly viable alternative is to elide the owner check except when
1902 // Xcheck:jni is enabled.
1903
1904 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1905 assert(boxReg == rax, "");
1906 assert_different_registers(objReg, boxReg, tmpReg);
1907
1908 Label DONE_LABEL, Stacked, CheckSucc;
1909
1910 // Critically, the biased locking test must have precedence over
1911 // and appear before the (box->dhw == 0) recursive stack-lock test.
1912 if (UseBiasedLocking && !UseOptoBiasInlining) {
1913 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1914 }
1915
1916 #if INCLUDE_RTM_OPT
1917 if (UseRTMForStackLocks && use_rtm) {
1918 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1919 Label L_regular_unlock;
1920 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1921 andptr(tmpReg, markWord::biased_lock_mask_in_place); // look at 3 lock bits
1922 cmpptr(tmpReg, markWord::unlocked_value); // bits = 001 unlocked
1923 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1924 xend(); // otherwise end...
1925 jmp(DONE_LABEL); // ... and we're done
1926 bind(L_regular_unlock);
1927 }
1928 #endif
1929
1930 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1931 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
1932 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword
1933 testptr(tmpReg, markWord::monitor_value); // Inflated?
1934 jccb (Assembler::zero, Stacked);
1935
1936 // It's inflated.
1937 #if INCLUDE_RTM_OPT
1938 if (use_rtm) {
1939 Label L_regular_inflated_unlock;
1940 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1941 movptr(boxReg, Address(tmpReg, owner_offset));
1942 testptr(boxReg, boxReg);
1943 jccb(Assembler::notZero, L_regular_inflated_unlock);
1944 xend();
1945 jmpb(DONE_LABEL);
1946 bind(L_regular_inflated_unlock);
1947 }
1948 #endif
1949
1950 // Despite our balanced locking property we still check that m->_owner == Self
1951 // as java routines or native JNI code called by this thread might
1952 // have released the lock.
1953 // Refer to the comments in synchronizer.cpp for how we might encode extra
1954 // state in _succ so we can avoid fetching EntryList|cxq.
1955 //
1956 // I'd like to add more cases in fast_lock() and fast_unlock() --
1957 // such as recursive enter and exit -- but we have to be wary of
1958 // I$ bloat, T$ effects and BP$ effects.
1959 //
1960 // If there's no contention try a 1-0 exit. That is, exit without
1961 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
1962 // we detect and recover from the race that the 1-0 exit admits.
1963 //
1964 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
1965 // before it STs null into _owner, releasing the lock. Updates
1966 // to data protected by the critical section must be visible before
1967 // we drop the lock (and thus before any other thread could acquire
1968 // the lock and observe the fields protected by the lock).
1969 // IA32's memory-model is SPO, so STs are ordered with respect to
1970 // each other and there's no need for an explicit barrier (fence).
1971 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
1972 #ifndef _LP64
1973 get_thread (boxReg);
1974
1975 // Note that we could employ various encoding schemes to reduce
1976 // the number of loads below (currently 4) to just 2 or 3.
1977 // Refer to the comments in synchronizer.cpp.
1978 // In practice the chain of fetches doesn't seem to impact performance, however.
1979 xorptr(boxReg, boxReg);
1980 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
1981 jccb (Assembler::notZero, DONE_LABEL);
1982 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
1983 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
1984 jccb (Assembler::notZero, CheckSucc);
1985 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
1986 jmpb (DONE_LABEL);
1987
1988 bind (Stacked);
1989 // It's not inflated and it's not recursively stack-locked and it's not biased.
1990 // It must be stack-locked.
1991 // Try to reset the header to displaced header.
1992 // The "box" value on the stack is stable, so we can reload
1993 // and be assured we observe the same value as above.
1994 movptr(tmpReg, Address(boxReg, 0));
1995 lock();
1996 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
1997 // Intention fall-thru into DONE_LABEL
1998
1999 // DONE_LABEL is a hot target - we'd really like to place it at the
2000 // start of cache line by padding with NOPs.
2001 // See the AMD and Intel software optimization manuals for the
2002 // most efficient "long" NOP encodings.
2003 // Unfortunately none of our alignment mechanisms suffice.
2004 bind (CheckSucc);
2005 #else // _LP64
2006 // It's inflated
2007 xorptr(boxReg, boxReg);
2008 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2009 jccb (Assembler::notZero, DONE_LABEL);
2010 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2011 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2012 jccb (Assembler::notZero, CheckSucc);
2013 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2014 jmpb (DONE_LABEL);
2015
2016 // Try to avoid passing control into the slow_path ...
2017 Label LSuccess, LGoSlowPath ;
2018 bind (CheckSucc);
2019
2020 // The following optional optimization can be elided if necessary
2021 // Effectively: if (succ == null) goto SlowPath
2022 // The code reduces the window for a race, however,
2023 // and thus benefits performance.
2024 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2025 jccb (Assembler::zero, LGoSlowPath);
2026
2027 xorptr(boxReg, boxReg);
2028 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2029
2030 // Memory barrier/fence
2031 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2032 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2033 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2034 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2035 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2036 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2037 lock(); addl(Address(rsp, 0), 0);
2038
2039 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2040 jccb (Assembler::notZero, LSuccess);
2041
2042 // Rare inopportune interleaving - race.
2043 // The successor vanished in the small window above.
2044 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2045 // We need to ensure progress and succession.
2046 // Try to reacquire the lock.
2047 // If that fails then the new owner is responsible for succession and this
2048 // thread needs to take no further action and can exit via the fast path (success).
2049 // If the re-acquire succeeds then pass control into the slow path.
2050 // As implemented, this latter mode is horrible because we generated more
2051 // coherence traffic on the lock *and* artifically extended the critical section
2052 // length while by virtue of passing control into the slow path.
2053
2054 // box is really RAX -- the following CMPXCHG depends on that binding
2055 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2056 lock();
2057 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2058 // There's no successor so we tried to regrab the lock.
2059 // If that didn't work, then another thread grabbed the
2060 // lock so we're done (and exit was a success).
2061 jccb (Assembler::notEqual, LSuccess);
2062 // Intentional fall-through into slow-path
2063
2064 bind (LGoSlowPath);
2065 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2066 jmpb (DONE_LABEL);
2067
2068 bind (LSuccess);
2069 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2070 jmpb (DONE_LABEL);
2071
2072 bind (Stacked);
2073 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2074 lock();
2075 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2076
2077 #endif
2078 bind(DONE_LABEL);
2079 }
2080 #endif // COMPILER2
2081
2082 void MacroAssembler::c2bool(Register x) {
2083 // implements x == 0 ? 0 : 1
2084 // note: must only look at least-significant byte of x
2085 // since C-style booleans are stored in one byte
2086 // only! (was bug)
2087 andl(x, 0xFF);
2088 setb(Assembler::notZero, x);
2089 }
2090
2091 // Wouldn't need if AddressLiteral version had new name
2092 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2093 Assembler::call(L, rtype);
2094 }
2095
2096 void MacroAssembler::call(Register entry) {
2097 Assembler::call(entry);
2098 }
2099
2100 void MacroAssembler::call(AddressLiteral entry) {
2101 if (reachable(entry)) {
2102 Assembler::call_literal(entry.target(), entry.rspec());
2103 } else {
2104 lea(rscratch1, entry);
2105 Assembler::call(rscratch1);
2106 }
2107 }
2108
2109 void MacroAssembler::ic_call(address entry, jint method_index) {
2110 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2111 movptr(rax, (intptr_t)Universe::non_oop_word());
2112 call(AddressLiteral(entry, rh));
2113 }
2114
2115 // Implementation of call_VM versions
2116
2117 void MacroAssembler::call_VM(Register oop_result,
2118 address entry_point,
2119 bool check_exceptions) {
2120 Label C, E;
2121 call(C, relocInfo::none);
2122 jmp(E);
2123
2124 bind(C);
2125 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2126 ret(0);
2127
2128 bind(E);
2129 }
2130
2131 void MacroAssembler::call_VM(Register oop_result,
2132 address entry_point,
2133 Register arg_1,
2134 bool check_exceptions) {
2135 Label C, E;
2136 call(C, relocInfo::none);
2137 jmp(E);
2138
2139 bind(C);
2140 pass_arg1(this, arg_1);
2141 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2142 ret(0);
2143
2144 bind(E);
2145 }
2146
2147 void MacroAssembler::call_VM(Register oop_result,
2148 address entry_point,
2149 Register arg_1,
2150 Register arg_2,
2151 bool check_exceptions) {
2152 Label C, E;
2153 call(C, relocInfo::none);
2154 jmp(E);
2155
2156 bind(C);
2157
2158 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2159
2160 pass_arg2(this, arg_2);
2161 pass_arg1(this, arg_1);
2162 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2163 ret(0);
2164
2165 bind(E);
2166 }
2167
2168 void MacroAssembler::call_VM(Register oop_result,
2169 address entry_point,
2170 Register arg_1,
2171 Register arg_2,
2172 Register arg_3,
2173 bool check_exceptions) {
2174 Label C, E;
2175 call(C, relocInfo::none);
2176 jmp(E);
2177
2178 bind(C);
2179
2180 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2181 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2182 pass_arg3(this, arg_3);
2183
2184 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2185 pass_arg2(this, arg_2);
2186
2187 pass_arg1(this, arg_1);
2188 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2189 ret(0);
2190
2191 bind(E);
2192 }
2193
2194 void MacroAssembler::call_VM(Register oop_result,
2195 Register last_java_sp,
2196 address entry_point,
2197 int number_of_arguments,
2198 bool check_exceptions) {
2199 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2200 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2201 }
2202
2203 void MacroAssembler::call_VM(Register oop_result,
2204 Register last_java_sp,
2205 address entry_point,
2206 Register arg_1,
2207 bool check_exceptions) {
2208 pass_arg1(this, arg_1);
2209 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2210 }
2211
2212 void MacroAssembler::call_VM(Register oop_result,
2213 Register last_java_sp,
2214 address entry_point,
2215 Register arg_1,
2216 Register arg_2,
2217 bool check_exceptions) {
2218
2219 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2220 pass_arg2(this, arg_2);
2221 pass_arg1(this, arg_1);
2222 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2223 }
2224
2225 void MacroAssembler::call_VM(Register oop_result,
2226 Register last_java_sp,
2227 address entry_point,
2228 Register arg_1,
2229 Register arg_2,
2230 Register arg_3,
2231 bool check_exceptions) {
2232 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2233 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2234 pass_arg3(this, arg_3);
2235 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2236 pass_arg2(this, arg_2);
2237 pass_arg1(this, arg_1);
2238 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2239 }
2240
2241 void MacroAssembler::super_call_VM(Register oop_result,
2242 Register last_java_sp,
2243 address entry_point,
2244 int number_of_arguments,
2245 bool check_exceptions) {
2246 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2247 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2248 }
2249
2250 void MacroAssembler::super_call_VM(Register oop_result,
2251 Register last_java_sp,
2252 address entry_point,
2253 Register arg_1,
2254 bool check_exceptions) {
2255 pass_arg1(this, arg_1);
2256 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2257 }
2258
2259 void MacroAssembler::super_call_VM(Register oop_result,
2260 Register last_java_sp,
2261 address entry_point,
2262 Register arg_1,
2263 Register arg_2,
2264 bool check_exceptions) {
2265
2266 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2267 pass_arg2(this, arg_2);
2268 pass_arg1(this, arg_1);
2269 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2270 }
2271
2272 void MacroAssembler::super_call_VM(Register oop_result,
2273 Register last_java_sp,
2274 address entry_point,
2275 Register arg_1,
2276 Register arg_2,
2277 Register arg_3,
2278 bool check_exceptions) {
2279 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2280 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2281 pass_arg3(this, arg_3);
2282 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2283 pass_arg2(this, arg_2);
2284 pass_arg1(this, arg_1);
2285 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2286 }
2287
2288 void MacroAssembler::call_VM_base(Register oop_result,
2289 Register java_thread,
2290 Register last_java_sp,
2291 address entry_point,
2292 int number_of_arguments,
2293 bool check_exceptions) {
2294 // determine java_thread register
2295 if (!java_thread->is_valid()) {
2296 #ifdef _LP64
2297 java_thread = r15_thread;
2298 #else
2299 java_thread = rdi;
2300 get_thread(java_thread);
2301 #endif // LP64
2302 }
2303 // determine last_java_sp register
2304 if (!last_java_sp->is_valid()) {
2305 last_java_sp = rsp;
2306 }
2307 // debugging support
2308 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2309 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2310 #ifdef ASSERT
2311 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2312 // r12 is the heapbase.
2313 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2314 #endif // ASSERT
2315
2316 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2317 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2318
2319 // push java thread (becomes first argument of C function)
2320
2321 NOT_LP64(push(java_thread); number_of_arguments++);
2322 LP64_ONLY(mov(c_rarg0, r15_thread));
2323
2324 // set last Java frame before call
2325 assert(last_java_sp != rbp, "can't use ebp/rbp");
2326
2327 // Only interpreter should have to set fp
2328 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2329
2330 // do the call, remove parameters
2331 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2332
2333 // restore the thread (cannot use the pushed argument since arguments
2334 // may be overwritten by C code generated by an optimizing compiler);
2335 // however can use the register value directly if it is callee saved.
2336 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2337 // rdi & rsi (also r15) are callee saved -> nothing to do
2338 #ifdef ASSERT
2339 guarantee(java_thread != rax, "change this code");
2340 push(rax);
2341 { Label L;
2342 get_thread(rax);
2343 cmpptr(java_thread, rax);
2344 jcc(Assembler::equal, L);
2345 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2346 bind(L);
2347 }
2348 pop(rax);
2349 #endif
2350 } else {
2351 get_thread(java_thread);
2352 }
2353 // reset last Java frame
2354 // Only interpreter should have to clear fp
2355 reset_last_Java_frame(java_thread, true);
2356
2357 // C++ interp handles this in the interpreter
2358 check_and_handle_popframe(java_thread);
2359 check_and_handle_earlyret(java_thread);
2360
2361 if (check_exceptions) {
2362 // check for pending exceptions (java_thread is set upon return)
2363 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2364 #ifndef _LP64
2365 jump_cc(Assembler::notEqual,
2366 RuntimeAddress(StubRoutines::forward_exception_entry()));
2367 #else
2368 // This used to conditionally jump to forward_exception however it is
2369 // possible if we relocate that the branch will not reach. So we must jump
2370 // around so we can always reach
2371
2372 Label ok;
2373 jcc(Assembler::equal, ok);
2374 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2375 bind(ok);
2376 #endif // LP64
2377 }
2378
2379 // get oop result if there is one and reset the value in the thread
2380 if (oop_result->is_valid()) {
2381 get_vm_result(oop_result, java_thread);
2382 }
2383 }
2384
2385 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2386
2387 // Calculate the value for last_Java_sp
2388 // somewhat subtle. call_VM does an intermediate call
2389 // which places a return address on the stack just under the
2390 // stack pointer as the user finsihed with it. This allows
2391 // use to retrieve last_Java_pc from last_Java_sp[-1].
2392 // On 32bit we then have to push additional args on the stack to accomplish
2393 // the actual requested call. On 64bit call_VM only can use register args
2394 // so the only extra space is the return address that call_VM created.
2395 // This hopefully explains the calculations here.
2396
2397 #ifdef _LP64
2398 // We've pushed one address, correct last_Java_sp
2399 lea(rax, Address(rsp, wordSize));
2400 #else
2401 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2402 #endif // LP64
2403
2404 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2405
2406 }
2407
2408 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2409 void MacroAssembler::call_VM_leaf0(address entry_point) {
2410 MacroAssembler::call_VM_leaf_base(entry_point, 0);
2411 }
2412
2413 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2414 call_VM_leaf_base(entry_point, number_of_arguments);
2415 }
2416
2417 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2418 pass_arg0(this, arg_0);
2419 call_VM_leaf(entry_point, 1);
2420 }
2421
2422 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2423
2424 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2425 pass_arg1(this, arg_1);
2426 pass_arg0(this, arg_0);
2427 call_VM_leaf(entry_point, 2);
2428 }
2429
2430 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2431 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2432 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2433 pass_arg2(this, arg_2);
2434 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2435 pass_arg1(this, arg_1);
2436 pass_arg0(this, arg_0);
2437 call_VM_leaf(entry_point, 3);
2438 }
2439
2440 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2441 pass_arg0(this, arg_0);
2442 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2443 }
2444
2445 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2446
2447 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2448 pass_arg1(this, arg_1);
2449 pass_arg0(this, arg_0);
2450 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2451 }
2452
2453 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2454 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2455 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2456 pass_arg2(this, arg_2);
2457 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2458 pass_arg1(this, arg_1);
2459 pass_arg0(this, arg_0);
2460 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2461 }
2462
2463 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2464 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2465 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2466 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2467 pass_arg3(this, arg_3);
2468 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2469 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2470 pass_arg2(this, arg_2);
2471 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2472 pass_arg1(this, arg_1);
2473 pass_arg0(this, arg_0);
2474 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2475 }
2476
2477 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2478 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2479 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2480 verify_oop(oop_result, "broken oop in call_VM_base");
2481 }
2482
2483 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2484 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2485 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2486 }
2487
2488 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2489 }
2490
2491 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2492 }
2493
2494 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2495 if (reachable(src1)) {
2496 cmpl(as_Address(src1), imm);
2497 } else {
2498 lea(rscratch1, src1);
2499 cmpl(Address(rscratch1, 0), imm);
2500 }
2501 }
2502
2503 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2504 assert(!src2.is_lval(), "use cmpptr");
2505 if (reachable(src2)) {
2506 cmpl(src1, as_Address(src2));
2507 } else {
2508 lea(rscratch1, src2);
2509 cmpl(src1, Address(rscratch1, 0));
2510 }
2511 }
2512
2513 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2514 Assembler::cmpl(src1, imm);
2515 }
2516
2517 void MacroAssembler::cmp32(Register src1, Address src2) {
2518 Assembler::cmpl(src1, src2);
2519 }
2520
2521 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2522 ucomisd(opr1, opr2);
2523
2524 Label L;
2525 if (unordered_is_less) {
2526 movl(dst, -1);
2527 jcc(Assembler::parity, L);
2528 jcc(Assembler::below , L);
2529 movl(dst, 0);
2530 jcc(Assembler::equal , L);
2531 increment(dst);
2532 } else { // unordered is greater
2533 movl(dst, 1);
2534 jcc(Assembler::parity, L);
2535 jcc(Assembler::above , L);
2536 movl(dst, 0);
2537 jcc(Assembler::equal , L);
2538 decrementl(dst);
2539 }
2540 bind(L);
2541 }
2542
2543 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2544 ucomiss(opr1, opr2);
2545
2546 Label L;
2547 if (unordered_is_less) {
2548 movl(dst, -1);
2549 jcc(Assembler::parity, L);
2550 jcc(Assembler::below , L);
2551 movl(dst, 0);
2552 jcc(Assembler::equal , L);
2553 increment(dst);
2554 } else { // unordered is greater
2555 movl(dst, 1);
2556 jcc(Assembler::parity, L);
2557 jcc(Assembler::above , L);
2558 movl(dst, 0);
2559 jcc(Assembler::equal , L);
2560 decrementl(dst);
2561 }
2562 bind(L);
2563 }
2564
2565
2566 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2567 if (reachable(src1)) {
2568 cmpb(as_Address(src1), imm);
2569 } else {
2570 lea(rscratch1, src1);
2571 cmpb(Address(rscratch1, 0), imm);
2572 }
2573 }
2574
2575 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2576 #ifdef _LP64
2577 if (src2.is_lval()) {
2578 movptr(rscratch1, src2);
2579 Assembler::cmpq(src1, rscratch1);
2580 } else if (reachable(src2)) {
2581 cmpq(src1, as_Address(src2));
2582 } else {
2583 lea(rscratch1, src2);
2584 Assembler::cmpq(src1, Address(rscratch1, 0));
2585 }
2586 #else
2587 if (src2.is_lval()) {
2588 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2589 } else {
2590 cmpl(src1, as_Address(src2));
2591 }
2592 #endif // _LP64
2593 }
2594
2595 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2596 assert(src2.is_lval(), "not a mem-mem compare");
2597 #ifdef _LP64
2598 // moves src2's literal address
2599 movptr(rscratch1, src2);
2600 Assembler::cmpq(src1, rscratch1);
2601 #else
2602 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2603 #endif // _LP64
2604 }
2605
2606 void MacroAssembler::cmpoop(Register src1, Register src2) {
2607 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2608 bs->obj_equals(this, src1, src2);
2609 }
2610
2611 void MacroAssembler::cmpoop(Register src1, Address src2) {
2612 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2613 bs->obj_equals(this, src1, src2);
2614 }
2615
2616 #ifdef _LP64
2617 void MacroAssembler::cmpoop(Register src1, jobject src2) {
2618 movoop(rscratch1, src2);
2619 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2620 bs->obj_equals(this, src1, rscratch1);
2621 }
2622 #endif
2623
2624 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2625 if (reachable(adr)) {
2626 lock();
2627 cmpxchgptr(reg, as_Address(adr));
2628 } else {
2629 lea(rscratch1, adr);
2630 lock();
2631 cmpxchgptr(reg, Address(rscratch1, 0));
2632 }
2633 }
2634
2635 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2636 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2637 }
2638
2639 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2640 if (reachable(src)) {
2641 Assembler::comisd(dst, as_Address(src));
2642 } else {
2643 lea(rscratch1, src);
2644 Assembler::comisd(dst, Address(rscratch1, 0));
2645 }
2646 }
2647
2648 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2649 if (reachable(src)) {
2650 Assembler::comiss(dst, as_Address(src));
2651 } else {
2652 lea(rscratch1, src);
2653 Assembler::comiss(dst, Address(rscratch1, 0));
2654 }
2655 }
2656
2657
2658 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2659 Condition negated_cond = negate_condition(cond);
2660 Label L;
2661 jcc(negated_cond, L);
2662 pushf(); // Preserve flags
2663 atomic_incl(counter_addr);
2664 popf();
2665 bind(L);
2666 }
2667
2668 int MacroAssembler::corrected_idivl(Register reg) {
2669 // Full implementation of Java idiv and irem; checks for
2670 // special case as described in JVM spec., p.243 & p.271.
2671 // The function returns the (pc) offset of the idivl
2672 // instruction - may be needed for implicit exceptions.
2673 //
2674 // normal case special case
2675 //
2676 // input : rax,: dividend min_int
2677 // reg: divisor (may not be rax,/rdx) -1
2678 //
2679 // output: rax,: quotient (= rax, idiv reg) min_int
2680 // rdx: remainder (= rax, irem reg) 0
2681 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2682 const int min_int = 0x80000000;
2683 Label normal_case, special_case;
2684
2685 // check for special case
2686 cmpl(rax, min_int);
2687 jcc(Assembler::notEqual, normal_case);
2688 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2689 cmpl(reg, -1);
2690 jcc(Assembler::equal, special_case);
2691
2692 // handle normal case
2693 bind(normal_case);
2694 cdql();
2695 int idivl_offset = offset();
2696 idivl(reg);
2697
2698 // normal and special case exit
2699 bind(special_case);
2700
2701 return idivl_offset;
2702 }
2703
2704
2705
2706 void MacroAssembler::decrementl(Register reg, int value) {
2707 if (value == min_jint) {subl(reg, value) ; return; }
2708 if (value < 0) { incrementl(reg, -value); return; }
2709 if (value == 0) { ; return; }
2710 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2711 /* else */ { subl(reg, value) ; return; }
2712 }
2713
2714 void MacroAssembler::decrementl(Address dst, int value) {
2715 if (value == min_jint) {subl(dst, value) ; return; }
2716 if (value < 0) { incrementl(dst, -value); return; }
2717 if (value == 0) { ; return; }
2718 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2719 /* else */ { subl(dst, value) ; return; }
2720 }
2721
2722 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2723 assert (shift_value > 0, "illegal shift value");
2724 Label _is_positive;
2725 testl (reg, reg);
2726 jcc (Assembler::positive, _is_positive);
2727 int offset = (1 << shift_value) - 1 ;
2728
2729 if (offset == 1) {
2730 incrementl(reg);
2731 } else {
2732 addl(reg, offset);
2733 }
2734
2735 bind (_is_positive);
2736 sarl(reg, shift_value);
2737 }
2738
2739 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2740 if (reachable(src)) {
2741 Assembler::divsd(dst, as_Address(src));
2742 } else {
2743 lea(rscratch1, src);
2744 Assembler::divsd(dst, Address(rscratch1, 0));
2745 }
2746 }
2747
2748 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2749 if (reachable(src)) {
2750 Assembler::divss(dst, as_Address(src));
2751 } else {
2752 lea(rscratch1, src);
2753 Assembler::divss(dst, Address(rscratch1, 0));
2754 }
2755 }
2756
2757 // !defined(COMPILER2) is because of stupid core builds
2758 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2759 void MacroAssembler::empty_FPU_stack() {
2760 if (VM_Version::supports_mmx()) {
2761 emms();
2762 } else {
2763 for (int i = 8; i-- > 0; ) ffree(i);
2764 }
2765 }
2766 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2767
2768
2769 void MacroAssembler::enter() {
2770 push(rbp);
2771 mov(rbp, rsp);
2772 }
2773
2774 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2775 void MacroAssembler::fat_nop() {
2776 if (UseAddressNop) {
2777 addr_nop_5();
2778 } else {
2779 emit_int8(0x26); // es:
2780 emit_int8(0x2e); // cs:
2781 emit_int8(0x64); // fs:
2782 emit_int8(0x65); // gs:
2783 emit_int8((unsigned char)0x90);
2784 }
2785 }
2786
2787 void MacroAssembler::fcmp(Register tmp) {
2788 fcmp(tmp, 1, true, true);
2789 }
2790
2791 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2792 assert(!pop_right || pop_left, "usage error");
2793 if (VM_Version::supports_cmov()) {
2794 assert(tmp == noreg, "unneeded temp");
2795 if (pop_left) {
2796 fucomip(index);
2797 } else {
2798 fucomi(index);
2799 }
2800 if (pop_right) {
2801 fpop();
2802 }
2803 } else {
2804 assert(tmp != noreg, "need temp");
2805 if (pop_left) {
2806 if (pop_right) {
2807 fcompp();
2808 } else {
2809 fcomp(index);
2810 }
2811 } else {
2812 fcom(index);
2813 }
2814 // convert FPU condition into eflags condition via rax,
2815 save_rax(tmp);
2816 fwait(); fnstsw_ax();
2817 sahf();
2818 restore_rax(tmp);
2819 }
2820 // condition codes set as follows:
2821 //
2822 // CF (corresponds to C0) if x < y
2823 // PF (corresponds to C2) if unordered
2824 // ZF (corresponds to C3) if x = y
2825 }
2826
2827 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2828 fcmp2int(dst, unordered_is_less, 1, true, true);
2829 }
2830
2831 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2832 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2833 Label L;
2834 if (unordered_is_less) {
2835 movl(dst, -1);
2836 jcc(Assembler::parity, L);
2837 jcc(Assembler::below , L);
2838 movl(dst, 0);
2839 jcc(Assembler::equal , L);
2840 increment(dst);
2841 } else { // unordered is greater
2842 movl(dst, 1);
2843 jcc(Assembler::parity, L);
2844 jcc(Assembler::above , L);
2845 movl(dst, 0);
2846 jcc(Assembler::equal , L);
2847 decrementl(dst);
2848 }
2849 bind(L);
2850 }
2851
2852 void MacroAssembler::fld_d(AddressLiteral src) {
2853 fld_d(as_Address(src));
2854 }
2855
2856 void MacroAssembler::fld_s(AddressLiteral src) {
2857 fld_s(as_Address(src));
2858 }
2859
2860 void MacroAssembler::fld_x(AddressLiteral src) {
2861 Assembler::fld_x(as_Address(src));
2862 }
2863
2864 void MacroAssembler::fldcw(AddressLiteral src) {
2865 Assembler::fldcw(as_Address(src));
2866 }
2867
2868 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
2869 if (reachable(src)) {
2870 Assembler::mulpd(dst, as_Address(src));
2871 } else {
2872 lea(rscratch1, src);
2873 Assembler::mulpd(dst, Address(rscratch1, 0));
2874 }
2875 }
2876
2877 void MacroAssembler::increase_precision() {
2878 subptr(rsp, BytesPerWord);
2879 fnstcw(Address(rsp, 0));
2880 movl(rax, Address(rsp, 0));
2881 orl(rax, 0x300);
2882 push(rax);
2883 fldcw(Address(rsp, 0));
2884 pop(rax);
2885 }
2886
2887 void MacroAssembler::restore_precision() {
2888 fldcw(Address(rsp, 0));
2889 addptr(rsp, BytesPerWord);
2890 }
2891
2892 void MacroAssembler::fpop() {
2893 ffree();
2894 fincstp();
2895 }
2896
2897 void MacroAssembler::load_float(Address src) {
2898 if (UseSSE >= 1) {
2899 movflt(xmm0, src);
2900 } else {
2901 LP64_ONLY(ShouldNotReachHere());
2902 NOT_LP64(fld_s(src));
2903 }
2904 }
2905
2906 void MacroAssembler::store_float(Address dst) {
2907 if (UseSSE >= 1) {
2908 movflt(dst, xmm0);
2909 } else {
2910 LP64_ONLY(ShouldNotReachHere());
2911 NOT_LP64(fstp_s(dst));
2912 }
2913 }
2914
2915 void MacroAssembler::load_double(Address src) {
2916 if (UseSSE >= 2) {
2917 movdbl(xmm0, src);
2918 } else {
2919 LP64_ONLY(ShouldNotReachHere());
2920 NOT_LP64(fld_d(src));
2921 }
2922 }
2923
2924 void MacroAssembler::store_double(Address dst) {
2925 if (UseSSE >= 2) {
2926 movdbl(dst, xmm0);
2927 } else {
2928 LP64_ONLY(ShouldNotReachHere());
2929 NOT_LP64(fstp_d(dst));
2930 }
2931 }
2932
2933 void MacroAssembler::fremr(Register tmp) {
2934 save_rax(tmp);
2935 { Label L;
2936 bind(L);
2937 fprem();
2938 fwait(); fnstsw_ax();
2939 #ifdef _LP64
2940 testl(rax, 0x400);
2941 jcc(Assembler::notEqual, L);
2942 #else
2943 sahf();
2944 jcc(Assembler::parity, L);
2945 #endif // _LP64
2946 }
2947 restore_rax(tmp);
2948 // Result is in ST0.
2949 // Note: fxch & fpop to get rid of ST1
2950 // (otherwise FPU stack could overflow eventually)
2951 fxch(1);
2952 fpop();
2953 }
2954
2955 // dst = c = a * b + c
2956 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2957 Assembler::vfmadd231sd(c, a, b);
2958 if (dst != c) {
2959 movdbl(dst, c);
2960 }
2961 }
2962
2963 // dst = c = a * b + c
2964 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2965 Assembler::vfmadd231ss(c, a, b);
2966 if (dst != c) {
2967 movflt(dst, c);
2968 }
2969 }
2970
2971 // dst = c = a * b + c
2972 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2973 Assembler::vfmadd231pd(c, a, b, vector_len);
2974 if (dst != c) {
2975 vmovdqu(dst, c);
2976 }
2977 }
2978
2979 // dst = c = a * b + c
2980 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2981 Assembler::vfmadd231ps(c, a, b, vector_len);
2982 if (dst != c) {
2983 vmovdqu(dst, c);
2984 }
2985 }
2986
2987 // dst = c = a * b + c
2988 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2989 Assembler::vfmadd231pd(c, a, b, vector_len);
2990 if (dst != c) {
2991 vmovdqu(dst, c);
2992 }
2993 }
2994
2995 // dst = c = a * b + c
2996 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2997 Assembler::vfmadd231ps(c, a, b, vector_len);
2998 if (dst != c) {
2999 vmovdqu(dst, c);
3000 }
3001 }
3002
3003 void MacroAssembler::incrementl(AddressLiteral dst) {
3004 if (reachable(dst)) {
3005 incrementl(as_Address(dst));
3006 } else {
3007 lea(rscratch1, dst);
3008 incrementl(Address(rscratch1, 0));
3009 }
3010 }
3011
3012 void MacroAssembler::incrementl(ArrayAddress dst) {
3013 incrementl(as_Address(dst));
3014 }
3015
3016 void MacroAssembler::incrementl(Register reg, int value) {
3017 if (value == min_jint) {addl(reg, value) ; return; }
3018 if (value < 0) { decrementl(reg, -value); return; }
3019 if (value == 0) { ; return; }
3020 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3021 /* else */ { addl(reg, value) ; return; }
3022 }
3023
3024 void MacroAssembler::incrementl(Address dst, int value) {
3025 if (value == min_jint) {addl(dst, value) ; return; }
3026 if (value < 0) { decrementl(dst, -value); return; }
3027 if (value == 0) { ; return; }
3028 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3029 /* else */ { addl(dst, value) ; return; }
3030 }
3031
3032 void MacroAssembler::jump(AddressLiteral dst) {
3033 if (reachable(dst)) {
3034 jmp_literal(dst.target(), dst.rspec());
3035 } else {
3036 lea(rscratch1, dst);
3037 jmp(rscratch1);
3038 }
3039 }
3040
3041 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3042 if (reachable(dst)) {
3043 InstructionMark im(this);
3044 relocate(dst.reloc());
3045 const int short_size = 2;
3046 const int long_size = 6;
3047 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3048 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3049 // 0111 tttn #8-bit disp
3050 emit_int8(0x70 | cc);
3051 emit_int8((offs - short_size) & 0xFF);
3052 } else {
3053 // 0000 1111 1000 tttn #32-bit disp
3054 emit_int8(0x0F);
3055 emit_int8((unsigned char)(0x80 | cc));
3056 emit_int32(offs - long_size);
3057 }
3058 } else {
3059 #ifdef ASSERT
3060 warning("reversing conditional branch");
3061 #endif /* ASSERT */
3062 Label skip;
3063 jccb(reverse[cc], skip);
3064 lea(rscratch1, dst);
3065 Assembler::jmp(rscratch1);
3066 bind(skip);
3067 }
3068 }
3069
3070 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3071 if (reachable(src)) {
3072 Assembler::ldmxcsr(as_Address(src));
3073 } else {
3074 lea(rscratch1, src);
3075 Assembler::ldmxcsr(Address(rscratch1, 0));
3076 }
3077 }
3078
3079 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3080 int off;
3081 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3082 off = offset();
3083 movsbl(dst, src); // movsxb
3084 } else {
3085 off = load_unsigned_byte(dst, src);
3086 shll(dst, 24);
3087 sarl(dst, 24);
3088 }
3089 return off;
3090 }
3091
3092 // Note: load_signed_short used to be called load_signed_word.
3093 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3094 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3095 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3096 int MacroAssembler::load_signed_short(Register dst, Address src) {
3097 int off;
3098 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3099 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3100 // version but this is what 64bit has always done. This seems to imply
3101 // that users are only using 32bits worth.
3102 off = offset();
3103 movswl(dst, src); // movsxw
3104 } else {
3105 off = load_unsigned_short(dst, src);
3106 shll(dst, 16);
3107 sarl(dst, 16);
3108 }
3109 return off;
3110 }
3111
3112 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3113 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3114 // and "3.9 Partial Register Penalties", p. 22).
3115 int off;
3116 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3117 off = offset();
3118 movzbl(dst, src); // movzxb
3119 } else {
3120 xorl(dst, dst);
3121 off = offset();
3122 movb(dst, src);
3123 }
3124 return off;
3125 }
3126
3127 // Note: load_unsigned_short used to be called load_unsigned_word.
3128 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3129 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3130 // and "3.9 Partial Register Penalties", p. 22).
3131 int off;
3132 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3133 off = offset();
3134 movzwl(dst, src); // movzxw
3135 } else {
3136 xorl(dst, dst);
3137 off = offset();
3138 movw(dst, src);
3139 }
3140 return off;
3141 }
3142
3143 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3144 switch (size_in_bytes) {
3145 #ifndef _LP64
3146 case 8:
3147 assert(dst2 != noreg, "second dest register required");
3148 movl(dst, src);
3149 movl(dst2, src.plus_disp(BytesPerInt));
3150 break;
3151 #else
3152 case 8: movq(dst, src); break;
3153 #endif
3154 case 4: movl(dst, src); break;
3155 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3156 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3157 default: ShouldNotReachHere();
3158 }
3159 }
3160
3161 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3162 switch (size_in_bytes) {
3163 #ifndef _LP64
3164 case 8:
3165 assert(src2 != noreg, "second source register required");
3166 movl(dst, src);
3167 movl(dst.plus_disp(BytesPerInt), src2);
3168 break;
3169 #else
3170 case 8: movq(dst, src); break;
3171 #endif
3172 case 4: movl(dst, src); break;
3173 case 2: movw(dst, src); break;
3174 case 1: movb(dst, src); break;
3175 default: ShouldNotReachHere();
3176 }
3177 }
3178
3179 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3180 if (reachable(dst)) {
3181 movl(as_Address(dst), src);
3182 } else {
3183 lea(rscratch1, dst);
3184 movl(Address(rscratch1, 0), src);
3185 }
3186 }
3187
3188 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3189 if (reachable(src)) {
3190 movl(dst, as_Address(src));
3191 } else {
3192 lea(rscratch1, src);
3193 movl(dst, Address(rscratch1, 0));
3194 }
3195 }
3196
3197 // C++ bool manipulation
3198
3199 void MacroAssembler::movbool(Register dst, Address src) {
3200 if(sizeof(bool) == 1)
3201 movb(dst, src);
3202 else if(sizeof(bool) == 2)
3203 movw(dst, src);
3204 else if(sizeof(bool) == 4)
3205 movl(dst, src);
3206 else
3207 // unsupported
3208 ShouldNotReachHere();
3209 }
3210
3211 void MacroAssembler::movbool(Address dst, bool boolconst) {
3212 if(sizeof(bool) == 1)
3213 movb(dst, (int) boolconst);
3214 else if(sizeof(bool) == 2)
3215 movw(dst, (int) boolconst);
3216 else if(sizeof(bool) == 4)
3217 movl(dst, (int) boolconst);
3218 else
3219 // unsupported
3220 ShouldNotReachHere();
3221 }
3222
3223 void MacroAssembler::movbool(Address dst, Register src) {
3224 if(sizeof(bool) == 1)
3225 movb(dst, src);
3226 else if(sizeof(bool) == 2)
3227 movw(dst, src);
3228 else if(sizeof(bool) == 4)
3229 movl(dst, src);
3230 else
3231 // unsupported
3232 ShouldNotReachHere();
3233 }
3234
3235 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3236 movb(as_Address(dst), src);
3237 }
3238
3239 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3240 if (reachable(src)) {
3241 movdl(dst, as_Address(src));
3242 } else {
3243 lea(rscratch1, src);
3244 movdl(dst, Address(rscratch1, 0));
3245 }
3246 }
3247
3248 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3249 if (reachable(src)) {
3250 movq(dst, as_Address(src));
3251 } else {
3252 lea(rscratch1, src);
3253 movq(dst, Address(rscratch1, 0));
3254 }
3255 }
3256
3257 #ifdef COMPILER2
3258 void MacroAssembler::setvectmask(Register dst, Register src) {
3259 guarantee(PostLoopMultiversioning, "must be");
3260 Assembler::movl(dst, 1);
3261 Assembler::shlxl(dst, dst, src);
3262 Assembler::decl(dst);
3263 Assembler::kmovdl(k1, dst);
3264 Assembler::movl(dst, src);
3265 }
3266
3267 void MacroAssembler::restorevectmask() {
3268 guarantee(PostLoopMultiversioning, "must be");
3269 Assembler::knotwl(k1, k0);
3270 }
3271 #endif // COMPILER2
3272
3273 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3274 if (reachable(src)) {
3275 if (UseXmmLoadAndClearUpper) {
3276 movsd (dst, as_Address(src));
3277 } else {
3278 movlpd(dst, as_Address(src));
3279 }
3280 } else {
3281 lea(rscratch1, src);
3282 if (UseXmmLoadAndClearUpper) {
3283 movsd (dst, Address(rscratch1, 0));
3284 } else {
3285 movlpd(dst, Address(rscratch1, 0));
3286 }
3287 }
3288 }
3289
3290 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3291 if (reachable(src)) {
3292 movss(dst, as_Address(src));
3293 } else {
3294 lea(rscratch1, src);
3295 movss(dst, Address(rscratch1, 0));
3296 }
3297 }
3298
3299 void MacroAssembler::movptr(Register dst, Register src) {
3300 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3301 }
3302
3303 void MacroAssembler::movptr(Register dst, Address src) {
3304 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3305 }
3306
3307 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3308 void MacroAssembler::movptr(Register dst, intptr_t src) {
3309 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3310 }
3311
3312 void MacroAssembler::movptr(Address dst, Register src) {
3313 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3314 }
3315
3316 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3317 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3318 Assembler::movdqu(dst, src);
3319 }
3320
3321 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3322 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3323 Assembler::movdqu(dst, src);
3324 }
3325
3326 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3327 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3328 Assembler::movdqu(dst, src);
3329 }
3330
3331 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3332 if (reachable(src)) {
3333 movdqu(dst, as_Address(src));
3334 } else {
3335 lea(scratchReg, src);
3336 movdqu(dst, Address(scratchReg, 0));
3337 }
3338 }
3339
3340 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3341 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3342 Assembler::vmovdqu(dst, src);
3343 }
3344
3345 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3346 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3347 Assembler::vmovdqu(dst, src);
3348 }
3349
3350 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3351 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3352 Assembler::vmovdqu(dst, src);
3353 }
3354
3355 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3356 if (reachable(src)) {
3357 vmovdqu(dst, as_Address(src));
3358 }
3359 else {
3360 lea(scratch_reg, src);
3361 vmovdqu(dst, Address(scratch_reg, 0));
3362 }
3363 }
3364
3365 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3366 if (reachable(src)) {
3367 Assembler::evmovdquq(dst, as_Address(src), vector_len);
3368 } else {
3369 lea(rscratch, src);
3370 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
3371 }
3372 }
3373
3374 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3375 if (reachable(src)) {
3376 Assembler::movdqa(dst, as_Address(src));
3377 } else {
3378 lea(rscratch1, src);
3379 Assembler::movdqa(dst, Address(rscratch1, 0));
3380 }
3381 }
3382
3383 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3384 if (reachable(src)) {
3385 Assembler::movsd(dst, as_Address(src));
3386 } else {
3387 lea(rscratch1, src);
3388 Assembler::movsd(dst, Address(rscratch1, 0));
3389 }
3390 }
3391
3392 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3393 if (reachable(src)) {
3394 Assembler::movss(dst, as_Address(src));
3395 } else {
3396 lea(rscratch1, src);
3397 Assembler::movss(dst, Address(rscratch1, 0));
3398 }
3399 }
3400
3401 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3402 if (reachable(src)) {
3403 Assembler::mulsd(dst, as_Address(src));
3404 } else {
3405 lea(rscratch1, src);
3406 Assembler::mulsd(dst, Address(rscratch1, 0));
3407 }
3408 }
3409
3410 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3411 if (reachable(src)) {
3412 Assembler::mulss(dst, as_Address(src));
3413 } else {
3414 lea(rscratch1, src);
3415 Assembler::mulss(dst, Address(rscratch1, 0));
3416 }
3417 }
3418
3419 void MacroAssembler::null_check(Register reg, int offset) {
3420 if (needs_explicit_null_check(offset)) {
3421 // provoke OS NULL exception if reg = NULL by
3422 // accessing M[reg] w/o changing any (non-CC) registers
3423 // NOTE: cmpl is plenty here to provoke a segv
3424 cmpptr(rax, Address(reg, 0));
3425 // Note: should probably use testl(rax, Address(reg, 0));
3426 // may be shorter code (however, this version of
3427 // testl needs to be implemented first)
3428 } else {
3429 // nothing to do, (later) access of M[reg + offset]
3430 // will provoke OS NULL exception if reg = NULL
3431 }
3432 }
3433
3434 void MacroAssembler::os_breakpoint() {
3435 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3436 // (e.g., MSVC can't call ps() otherwise)
3437 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3438 }
3439
3440 void MacroAssembler::unimplemented(const char* what) {
3441 const char* buf = NULL;
3442 {
3443 ResourceMark rm;
3444 stringStream ss;
3445 ss.print("unimplemented: %s", what);
3446 buf = code_string(ss.as_string());
3447 }
3448 stop(buf);
3449 }
3450
3451 #ifdef _LP64
3452 #define XSTATE_BV 0x200
3453 #endif
3454
3455 void MacroAssembler::pop_CPU_state() {
3456 pop_FPU_state();
3457 pop_IU_state();
3458 }
3459
3460 void MacroAssembler::pop_FPU_state() {
3461 #ifndef _LP64
3462 frstor(Address(rsp, 0));
3463 #else
3464 fxrstor(Address(rsp, 0));
3465 #endif
3466 addptr(rsp, FPUStateSizeInWords * wordSize);
3467 }
3468
3469 void MacroAssembler::pop_IU_state() {
3470 popa();
3471 LP64_ONLY(addq(rsp, 8));
3472 popf();
3473 }
3474
3475 // Save Integer and Float state
3476 // Warning: Stack must be 16 byte aligned (64bit)
3477 void MacroAssembler::push_CPU_state() {
3478 push_IU_state();
3479 push_FPU_state();
3480 }
3481
3482 void MacroAssembler::push_FPU_state() {
3483 subptr(rsp, FPUStateSizeInWords * wordSize);
3484 #ifndef _LP64
3485 fnsave(Address(rsp, 0));
3486 fwait();
3487 #else
3488 fxsave(Address(rsp, 0));
3489 #endif // LP64
3490 }
3491
3492 void MacroAssembler::push_IU_state() {
3493 // Push flags first because pusha kills them
3494 pushf();
3495 // Make sure rsp stays 16-byte aligned
3496 LP64_ONLY(subq(rsp, 8));
3497 pusha();
3498 }
3499
3500 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3501 if (!java_thread->is_valid()) {
3502 java_thread = rdi;
3503 get_thread(java_thread);
3504 }
3505 // we must set sp to zero to clear frame
3506 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3507 if (clear_fp) {
3508 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3509 }
3510
3511 // Always clear the pc because it could have been set by make_walkable()
3512 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3513
3514 vzeroupper();
3515 }
3516
3517 void MacroAssembler::restore_rax(Register tmp) {
3518 if (tmp == noreg) pop(rax);
3519 else if (tmp != rax) mov(rax, tmp);
3520 }
3521
3522 void MacroAssembler::round_to(Register reg, int modulus) {
3523 addptr(reg, modulus - 1);
3524 andptr(reg, -modulus);
3525 }
3526
3527 void MacroAssembler::save_rax(Register tmp) {
3528 if (tmp == noreg) push(rax);
3529 else if (tmp != rax) mov(tmp, rax);
3530 }
3531
3532 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) {
3533 if (SafepointMechanism::uses_thread_local_poll()) {
3534 #ifdef _LP64
3535 assert(thread_reg == r15_thread, "should be");
3536 #else
3537 if (thread_reg == noreg) {
3538 thread_reg = temp_reg;
3539 get_thread(thread_reg);
3540 }
3541 #endif
3542 testb(Address(thread_reg, Thread::polling_page_offset()), SafepointMechanism::poll_bit());
3543 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3544 } else {
3545 cmp32(ExternalAddress(SafepointSynchronize::address_of_state()),
3546 SafepointSynchronize::_not_synchronized);
3547 jcc(Assembler::notEqual, slow_path);
3548 }
3549 }
3550
3551 // Calls to C land
3552 //
3553 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3554 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3555 // has to be reset to 0. This is required to allow proper stack traversal.
3556 void MacroAssembler::set_last_Java_frame(Register java_thread,
3557 Register last_java_sp,
3558 Register last_java_fp,
3559 address last_java_pc) {
3560 vzeroupper();
3561 // determine java_thread register
3562 if (!java_thread->is_valid()) {
3563 java_thread = rdi;
3564 get_thread(java_thread);
3565 }
3566 // determine last_java_sp register
3567 if (!last_java_sp->is_valid()) {
3568 last_java_sp = rsp;
3569 }
3570
3571 // last_java_fp is optional
3572
3573 if (last_java_fp->is_valid()) {
3574 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3575 }
3576
3577 // last_java_pc is optional
3578
3579 if (last_java_pc != NULL) {
3580 lea(Address(java_thread,
3581 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3582 InternalAddress(last_java_pc));
3583
3584 }
3585 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3586 }
3587
3588 void MacroAssembler::shlptr(Register dst, int imm8) {
3589 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3590 }
3591
3592 void MacroAssembler::shrptr(Register dst, int imm8) {
3593 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3594 }
3595
3596 void MacroAssembler::sign_extend_byte(Register reg) {
3597 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3598 movsbl(reg, reg); // movsxb
3599 } else {
3600 shll(reg, 24);
3601 sarl(reg, 24);
3602 }
3603 }
3604
3605 void MacroAssembler::sign_extend_short(Register reg) {
3606 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3607 movswl(reg, reg); // movsxw
3608 } else {
3609 shll(reg, 16);
3610 sarl(reg, 16);
3611 }
3612 }
3613
3614 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3615 assert(reachable(src), "Address should be reachable");
3616 testl(dst, as_Address(src));
3617 }
3618
3619 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3620 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3621 Assembler::pcmpeqb(dst, src);
3622 }
3623
3624 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3625 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3626 Assembler::pcmpeqw(dst, src);
3627 }
3628
3629 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3630 assert((dst->encoding() < 16),"XMM register should be 0-15");
3631 Assembler::pcmpestri(dst, src, imm8);
3632 }
3633
3634 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3635 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3636 Assembler::pcmpestri(dst, src, imm8);
3637 }
3638
3639 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3640 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3641 Assembler::pmovzxbw(dst, src);
3642 }
3643
3644 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3645 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3646 Assembler::pmovzxbw(dst, src);
3647 }
3648
3649 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3650 assert((src->encoding() < 16),"XMM register should be 0-15");
3651 Assembler::pmovmskb(dst, src);
3652 }
3653
3654 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3655 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3656 Assembler::ptest(dst, src);
3657 }
3658
3659 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3660 if (reachable(src)) {
3661 Assembler::sqrtsd(dst, as_Address(src));
3662 } else {
3663 lea(rscratch1, src);
3664 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3665 }
3666 }
3667
3668 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3669 if (reachable(src)) {
3670 Assembler::sqrtss(dst, as_Address(src));
3671 } else {
3672 lea(rscratch1, src);
3673 Assembler::sqrtss(dst, Address(rscratch1, 0));
3674 }
3675 }
3676
3677 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3678 if (reachable(src)) {
3679 Assembler::subsd(dst, as_Address(src));
3680 } else {
3681 lea(rscratch1, src);
3682 Assembler::subsd(dst, Address(rscratch1, 0));
3683 }
3684 }
3685
3686 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg) {
3687 if (reachable(src)) {
3688 Assembler::roundsd(dst, as_Address(src), rmode);
3689 } else {
3690 lea(scratch_reg, src);
3691 Assembler::roundsd(dst, Address(scratch_reg, 0), rmode);
3692 }
3693 }
3694
3695 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3696 if (reachable(src)) {
3697 Assembler::subss(dst, as_Address(src));
3698 } else {
3699 lea(rscratch1, src);
3700 Assembler::subss(dst, Address(rscratch1, 0));
3701 }
3702 }
3703
3704 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3705 if (reachable(src)) {
3706 Assembler::ucomisd(dst, as_Address(src));
3707 } else {
3708 lea(rscratch1, src);
3709 Assembler::ucomisd(dst, Address(rscratch1, 0));
3710 }
3711 }
3712
3713 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3714 if (reachable(src)) {
3715 Assembler::ucomiss(dst, as_Address(src));
3716 } else {
3717 lea(rscratch1, src);
3718 Assembler::ucomiss(dst, Address(rscratch1, 0));
3719 }
3720 }
3721
3722 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3723 // Used in sign-bit flipping with aligned address.
3724 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3725 if (reachable(src)) {
3726 Assembler::xorpd(dst, as_Address(src));
3727 } else {
3728 lea(scratch_reg, src);
3729 Assembler::xorpd(dst, Address(scratch_reg, 0));
3730 }
3731 }
3732
3733 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3734 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3735 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3736 }
3737 else {
3738 Assembler::xorpd(dst, src);
3739 }
3740 }
3741
3742 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3743 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3744 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3745 } else {
3746 Assembler::xorps(dst, src);
3747 }
3748 }
3749
3750 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3751 // Used in sign-bit flipping with aligned address.
3752 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3753 if (reachable(src)) {
3754 Assembler::xorps(dst, as_Address(src));
3755 } else {
3756 lea(scratch_reg, src);
3757 Assembler::xorps(dst, Address(scratch_reg, 0));
3758 }
3759 }
3760
3761 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3762 // Used in sign-bit flipping with aligned address.
3763 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3764 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3765 if (reachable(src)) {
3766 Assembler::pshufb(dst, as_Address(src));
3767 } else {
3768 lea(rscratch1, src);
3769 Assembler::pshufb(dst, Address(rscratch1, 0));
3770 }
3771 }
3772
3773 // AVX 3-operands instructions
3774
3775 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3776 if (reachable(src)) {
3777 vaddsd(dst, nds, as_Address(src));
3778 } else {
3779 lea(rscratch1, src);
3780 vaddsd(dst, nds, Address(rscratch1, 0));
3781 }
3782 }
3783
3784 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3785 if (reachable(src)) {
3786 vaddss(dst, nds, as_Address(src));
3787 } else {
3788 lea(rscratch1, src);
3789 vaddss(dst, nds, Address(rscratch1, 0));
3790 }
3791 }
3792
3793 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3794 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3795 vandps(dst, nds, negate_field, vector_len);
3796 }
3797
3798 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3799 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3800 vandpd(dst, nds, negate_field, vector_len);
3801 }
3802
3803 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3804 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3805 Assembler::vpaddb(dst, nds, src, vector_len);
3806 }
3807
3808 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3809 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3810 Assembler::vpaddb(dst, nds, src, vector_len);
3811 }
3812
3813 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3814 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3815 Assembler::vpaddw(dst, nds, src, vector_len);
3816 }
3817
3818 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3819 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3820 Assembler::vpaddw(dst, nds, src, vector_len);
3821 }
3822
3823 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3824 if (reachable(src)) {
3825 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3826 } else {
3827 lea(scratch_reg, src);
3828 Assembler::vpand(dst, nds, Address(scratch_reg, 0), vector_len);
3829 }
3830 }
3831
3832 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
3833 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3834 Assembler::vpbroadcastw(dst, src, vector_len);
3835 }
3836
3837 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3838 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3839 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3840 }
3841
3842 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3843 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3844 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3845 }
3846
3847 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3848 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3849 Assembler::vpmovzxbw(dst, src, vector_len);
3850 }
3851
3852 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
3853 assert((src->encoding() < 16),"XMM register should be 0-15");
3854 Assembler::vpmovmskb(dst, src);
3855 }
3856
3857 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3858 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3859 Assembler::vpmullw(dst, nds, src, vector_len);
3860 }
3861
3862 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3863 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3864 Assembler::vpmullw(dst, nds, src, vector_len);
3865 }
3866
3867 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3868 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3869 Assembler::vpsubb(dst, nds, src, vector_len);
3870 }
3871
3872 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3873 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3874 Assembler::vpsubb(dst, nds, src, vector_len);
3875 }
3876
3877 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3878 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3879 Assembler::vpsubw(dst, nds, src, vector_len);
3880 }
3881
3882 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3883 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3884 Assembler::vpsubw(dst, nds, src, vector_len);
3885 }
3886
3887 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3888 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3889 Assembler::vpsraw(dst, nds, shift, vector_len);
3890 }
3891
3892 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3893 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3894 Assembler::vpsraw(dst, nds, shift, vector_len);
3895 }
3896
3897 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3898 assert(UseAVX > 2,"");
3899 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3900 vector_len = 2;
3901 }
3902 Assembler::evpsraq(dst, nds, shift, vector_len);
3903 }
3904
3905 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3906 assert(UseAVX > 2,"");
3907 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3908 vector_len = 2;
3909 }
3910 Assembler::evpsraq(dst, nds, shift, vector_len);
3911 }
3912
3913 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3914 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3915 Assembler::vpsrlw(dst, nds, shift, vector_len);
3916 }
3917
3918 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3919 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3920 Assembler::vpsrlw(dst, nds, shift, vector_len);
3921 }
3922
3923 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3924 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3925 Assembler::vpsllw(dst, nds, shift, vector_len);
3926 }
3927
3928 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3929 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3930 Assembler::vpsllw(dst, nds, shift, vector_len);
3931 }
3932
3933 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3934 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3935 Assembler::vptest(dst, src);
3936 }
3937
3938 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3939 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3940 Assembler::punpcklbw(dst, src);
3941 }
3942
3943 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3944 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3945 Assembler::pshufd(dst, src, mode);
3946 }
3947
3948 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3949 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3950 Assembler::pshuflw(dst, src, mode);
3951 }
3952
3953 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3954 if (reachable(src)) {
3955 vandpd(dst, nds, as_Address(src), vector_len);
3956 } else {
3957 lea(scratch_reg, src);
3958 vandpd(dst, nds, Address(scratch_reg, 0), vector_len);
3959 }
3960 }
3961
3962 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3963 if (reachable(src)) {
3964 vandps(dst, nds, as_Address(src), vector_len);
3965 } else {
3966 lea(scratch_reg, src);
3967 vandps(dst, nds, Address(scratch_reg, 0), vector_len);
3968 }
3969 }
3970
3971 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3972 if (reachable(src)) {
3973 vdivsd(dst, nds, as_Address(src));
3974 } else {
3975 lea(rscratch1, src);
3976 vdivsd(dst, nds, Address(rscratch1, 0));
3977 }
3978 }
3979
3980 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3981 if (reachable(src)) {
3982 vdivss(dst, nds, as_Address(src));
3983 } else {
3984 lea(rscratch1, src);
3985 vdivss(dst, nds, Address(rscratch1, 0));
3986 }
3987 }
3988
3989 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3990 if (reachable(src)) {
3991 vmulsd(dst, nds, as_Address(src));
3992 } else {
3993 lea(rscratch1, src);
3994 vmulsd(dst, nds, Address(rscratch1, 0));
3995 }
3996 }
3997
3998 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3999 if (reachable(src)) {
4000 vmulss(dst, nds, as_Address(src));
4001 } else {
4002 lea(rscratch1, src);
4003 vmulss(dst, nds, Address(rscratch1, 0));
4004 }
4005 }
4006
4007 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4008 if (reachable(src)) {
4009 vsubsd(dst, nds, as_Address(src));
4010 } else {
4011 lea(rscratch1, src);
4012 vsubsd(dst, nds, Address(rscratch1, 0));
4013 }
4014 }
4015
4016 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4017 if (reachable(src)) {
4018 vsubss(dst, nds, as_Address(src));
4019 } else {
4020 lea(rscratch1, src);
4021 vsubss(dst, nds, Address(rscratch1, 0));
4022 }
4023 }
4024
4025 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4026 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4027 vxorps(dst, nds, src, Assembler::AVX_128bit);
4028 }
4029
4030 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4031 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4032 vxorpd(dst, nds, src, Assembler::AVX_128bit);
4033 }
4034
4035 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4036 if (reachable(src)) {
4037 vxorpd(dst, nds, as_Address(src), vector_len);
4038 } else {
4039 lea(scratch_reg, src);
4040 vxorpd(dst, nds, Address(scratch_reg, 0), vector_len);
4041 }
4042 }
4043
4044 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4045 if (reachable(src)) {
4046 vxorps(dst, nds, as_Address(src), vector_len);
4047 } else {
4048 lea(scratch_reg, src);
4049 vxorps(dst, nds, Address(scratch_reg, 0), vector_len);
4050 }
4051 }
4052
4053 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4054 if (UseAVX > 1 || (vector_len < 1)) {
4055 if (reachable(src)) {
4056 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
4057 } else {
4058 lea(scratch_reg, src);
4059 Assembler::vpxor(dst, nds, Address(scratch_reg, 0), vector_len);
4060 }
4061 }
4062 else {
4063 MacroAssembler::vxorpd(dst, nds, src, vector_len, scratch_reg);
4064 }
4065 }
4066
4067 //-------------------------------------------------------------------------------------------
4068 #ifdef COMPILER2
4069 // Generic instructions support for use in .ad files C2 code generation
4070
4071 void MacroAssembler::vabsnegd(int opcode, XMMRegister dst, Register scr) {
4072 if (opcode == Op_AbsVD) {
4073 andpd(dst, ExternalAddress(StubRoutines::x86::vector_double_sign_mask()), scr);
4074 } else {
4075 assert((opcode == Op_NegVD),"opcode should be Op_NegD");
4076 xorpd(dst, ExternalAddress(StubRoutines::x86::vector_double_sign_flip()), scr);
4077 }
4078 }
4079
4080 void MacroAssembler::vabsnegd(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr) {
4081 if (opcode == Op_AbsVD) {
4082 vandpd(dst, src, ExternalAddress(StubRoutines::x86::vector_double_sign_mask()), vector_len, scr);
4083 } else {
4084 assert((opcode == Op_NegVD),"opcode should be Op_NegD");
4085 vxorpd(dst, src, ExternalAddress(StubRoutines::x86::vector_double_sign_flip()), vector_len, scr);
4086 }
4087 }
4088
4089 void MacroAssembler::vabsnegf(int opcode, XMMRegister dst, Register scr) {
4090 if (opcode == Op_AbsVF) {
4091 andps(dst, ExternalAddress(StubRoutines::x86::vector_float_sign_mask()), scr);
4092 } else {
4093 assert((opcode == Op_NegVF),"opcode should be Op_NegF");
4094 xorps(dst, ExternalAddress(StubRoutines::x86::vector_float_sign_flip()), scr);
4095 }
4096 }
4097
4098 void MacroAssembler::vabsnegf(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr) {
4099 if (opcode == Op_AbsVF) {
4100 vandps(dst, src, ExternalAddress(StubRoutines::x86::vector_float_sign_mask()), vector_len, scr);
4101 } else {
4102 assert((opcode == Op_NegVF),"opcode should be Op_NegF");
4103 vxorps(dst, src, ExternalAddress(StubRoutines::x86::vector_float_sign_flip()), vector_len, scr);
4104 }
4105 }
4106
4107 void MacroAssembler::vextendbw(bool sign, XMMRegister dst, XMMRegister src) {
4108 if (sign) {
4109 pmovsxbw(dst, src);
4110 } else {
4111 pmovzxbw(dst, src);
4112 }
4113 }
4114
4115 void MacroAssembler::vextendbw(bool sign, XMMRegister dst, XMMRegister src, int vector_len) {
4116 if (sign) {
4117 vpmovsxbw(dst, src, vector_len);
4118 } else {
4119 vpmovzxbw(dst, src, vector_len);
4120 }
4121 }
4122
4123 void MacroAssembler::vshiftd(int opcode, XMMRegister dst, XMMRegister src) {
4124 if (opcode == Op_RShiftVI) {
4125 psrad(dst, src);
4126 } else if (opcode == Op_LShiftVI) {
4127 pslld(dst, src);
4128 } else {
4129 assert((opcode == Op_URShiftVI),"opcode should be Op_URShiftVI");
4130 psrld(dst, src);
4131 }
4132 }
4133
4134 void MacroAssembler::vshiftd(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4135 if (opcode == Op_RShiftVI) {
4136 vpsrad(dst, nds, src, vector_len);
4137 } else if (opcode == Op_LShiftVI) {
4138 vpslld(dst, nds, src, vector_len);
4139 } else {
4140 assert((opcode == Op_URShiftVI),"opcode should be Op_URShiftVI");
4141 vpsrld(dst, nds, src, vector_len);
4142 }
4143 }
4144
4145 void MacroAssembler::vshiftw(int opcode, XMMRegister dst, XMMRegister src) {
4146 if ((opcode == Op_RShiftVS) || (opcode == Op_RShiftVB)) {
4147 psraw(dst, src);
4148 } else if ((opcode == Op_LShiftVS) || (opcode == Op_LShiftVB)) {
4149 psllw(dst, src);
4150 } else {
4151 assert(((opcode == Op_URShiftVS) || (opcode == Op_URShiftVB)),"opcode should be one of Op_URShiftVS or Op_URShiftVB");
4152 psrlw(dst, src);
4153 }
4154 }
4155
4156 void MacroAssembler::vshiftw(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4157 if ((opcode == Op_RShiftVS) || (opcode == Op_RShiftVB)) {
4158 vpsraw(dst, nds, src, vector_len);
4159 } else if ((opcode == Op_LShiftVS) || (opcode == Op_LShiftVB)) {
4160 vpsllw(dst, nds, src, vector_len);
4161 } else {
4162 assert(((opcode == Op_URShiftVS) || (opcode == Op_URShiftVB)),"opcode should be one of Op_URShiftVS or Op_URShiftVB");
4163 vpsrlw(dst, nds, src, vector_len);
4164 }
4165 }
4166
4167 void MacroAssembler::vshiftq(int opcode, XMMRegister dst, XMMRegister src) {
4168 if (opcode == Op_RShiftVL) {
4169 psrlq(dst, src); // using srl to implement sra on pre-avs512 systems
4170 } else if (opcode == Op_LShiftVL) {
4171 psllq(dst, src);
4172 } else {
4173 assert((opcode == Op_URShiftVL),"opcode should be Op_URShiftVL");
4174 psrlq(dst, src);
4175 }
4176 }
4177
4178 void MacroAssembler::vshiftq(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4179 if (opcode == Op_RShiftVL) {
4180 evpsraq(dst, nds, src, vector_len);
4181 } else if (opcode == Op_LShiftVL) {
4182 vpsllq(dst, nds, src, vector_len);
4183 } else {
4184 assert((opcode == Op_URShiftVL),"opcode should be Op_URShiftVL");
4185 vpsrlq(dst, nds, src, vector_len);
4186 }
4187 }
4188 #endif
4189 //-------------------------------------------------------------------------------------------
4190
4191 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
4192 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
4193 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
4194 // The inverted mask is sign-extended
4195 andptr(possibly_jweak, inverted_jweak_mask);
4196 }
4197
4198 void MacroAssembler::resolve_jobject(Register value,
4199 Register thread,
4200 Register tmp) {
4201 assert_different_registers(value, thread, tmp);
4202 Label done, not_weak;
4203 testptr(value, value);
4204 jcc(Assembler::zero, done); // Use NULL as-is.
4205 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
4206 jcc(Assembler::zero, not_weak);
4207 // Resolve jweak.
4208 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4209 value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
4210 verify_oop(value);
4211 jmp(done);
4212 bind(not_weak);
4213 // Resolve (untagged) jobject.
4214 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
4215 verify_oop(value);
4216 bind(done);
4217 }
4218
4219 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4220 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4221 }
4222
4223 // Force generation of a 4 byte immediate value even if it fits into 8bit
4224 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4225 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4226 }
4227
4228 void MacroAssembler::subptr(Register dst, Register src) {
4229 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4230 }
4231
4232 // C++ bool manipulation
4233 void MacroAssembler::testbool(Register dst) {
4234 if(sizeof(bool) == 1)
4235 testb(dst, 0xff);
4236 else if(sizeof(bool) == 2) {
4237 // testw implementation needed for two byte bools
4238 ShouldNotReachHere();
4239 } else if(sizeof(bool) == 4)
4240 testl(dst, dst);
4241 else
4242 // unsupported
4243 ShouldNotReachHere();
4244 }
4245
4246 void MacroAssembler::testptr(Register dst, Register src) {
4247 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4248 }
4249
4250 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4251 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4252 Register var_size_in_bytes,
4253 int con_size_in_bytes,
4254 Register t1,
4255 Register t2,
4256 Label& slow_case) {
4257 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4258 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4259 }
4260
4261 // Defines obj, preserves var_size_in_bytes
4262 void MacroAssembler::eden_allocate(Register thread, Register obj,
4263 Register var_size_in_bytes,
4264 int con_size_in_bytes,
4265 Register t1,
4266 Label& slow_case) {
4267 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4268 bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
4269 }
4270
4271 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4272 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4273 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4274 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4275 Label done;
4276
4277 testptr(length_in_bytes, length_in_bytes);
4278 jcc(Assembler::zero, done);
4279
4280 // initialize topmost word, divide index by 2, check if odd and test if zero
4281 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4282 #ifdef ASSERT
4283 {
4284 Label L;
4285 testptr(length_in_bytes, BytesPerWord - 1);
4286 jcc(Assembler::zero, L);
4287 stop("length must be a multiple of BytesPerWord");
4288 bind(L);
4289 }
4290 #endif
4291 Register index = length_in_bytes;
4292 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4293 if (UseIncDec) {
4294 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4295 } else {
4296 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4297 shrptr(index, 1);
4298 }
4299 #ifndef _LP64
4300 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4301 {
4302 Label even;
4303 // note: if index was a multiple of 8, then it cannot
4304 // be 0 now otherwise it must have been 0 before
4305 // => if it is even, we don't need to check for 0 again
4306 jcc(Assembler::carryClear, even);
4307 // clear topmost word (no jump would be needed if conditional assignment worked here)
4308 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4309 // index could be 0 now, must check again
4310 jcc(Assembler::zero, done);
4311 bind(even);
4312 }
4313 #endif // !_LP64
4314 // initialize remaining object fields: index is a multiple of 2 now
4315 {
4316 Label loop;
4317 bind(loop);
4318 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4319 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4320 decrement(index);
4321 jcc(Assembler::notZero, loop);
4322 }
4323
4324 bind(done);
4325 }
4326
4327 // Look up the method for a megamorphic invokeinterface call.
4328 // The target method is determined by <intf_klass, itable_index>.
4329 // The receiver klass is in recv_klass.
4330 // On success, the result will be in method_result, and execution falls through.
4331 // On failure, execution transfers to the given label.
4332 void MacroAssembler::lookup_interface_method(Register recv_klass,
4333 Register intf_klass,
4334 RegisterOrConstant itable_index,
4335 Register method_result,
4336 Register scan_temp,
4337 Label& L_no_such_interface,
4338 bool return_method) {
4339 assert_different_registers(recv_klass, intf_klass, scan_temp);
4340 assert_different_registers(method_result, intf_klass, scan_temp);
4341 assert(recv_klass != method_result || !return_method,
4342 "recv_klass can be destroyed when method isn't needed");
4343
4344 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4345 "caller must use same register for non-constant itable index as for method");
4346
4347 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4348 int vtable_base = in_bytes(Klass::vtable_start_offset());
4349 int itentry_off = itableMethodEntry::method_offset_in_bytes();
4350 int scan_step = itableOffsetEntry::size() * wordSize;
4351 int vte_size = vtableEntry::size_in_bytes();
4352 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4353 assert(vte_size == wordSize, "else adjust times_vte_scale");
4354
4355 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4356
4357 // %%% Could store the aligned, prescaled offset in the klassoop.
4358 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4359
4360 if (return_method) {
4361 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4362 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4363 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4364 }
4365
4366 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4367 // if (scan->interface() == intf) {
4368 // result = (klass + scan->offset() + itable_index);
4369 // }
4370 // }
4371 Label search, found_method;
4372
4373 for (int peel = 1; peel >= 0; peel--) {
4374 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4375 cmpptr(intf_klass, method_result);
4376
4377 if (peel) {
4378 jccb(Assembler::equal, found_method);
4379 } else {
4380 jccb(Assembler::notEqual, search);
4381 // (invert the test to fall through to found_method...)
4382 }
4383
4384 if (!peel) break;
4385
4386 bind(search);
4387
4388 // Check that the previous entry is non-null. A null entry means that
4389 // the receiver class doesn't implement the interface, and wasn't the
4390 // same as when the caller was compiled.
4391 testptr(method_result, method_result);
4392 jcc(Assembler::zero, L_no_such_interface);
4393 addptr(scan_temp, scan_step);
4394 }
4395
4396 bind(found_method);
4397
4398 if (return_method) {
4399 // Got a hit.
4400 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4401 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4402 }
4403 }
4404
4405
4406 // virtual method calling
4407 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4408 RegisterOrConstant vtable_index,
4409 Register method_result) {
4410 const int base = in_bytes(Klass::vtable_start_offset());
4411 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4412 Address vtable_entry_addr(recv_klass,
4413 vtable_index, Address::times_ptr,
4414 base + vtableEntry::method_offset_in_bytes());
4415 movptr(method_result, vtable_entry_addr);
4416 }
4417
4418
4419 void MacroAssembler::check_klass_subtype(Register sub_klass,
4420 Register super_klass,
4421 Register temp_reg,
4422 Label& L_success) {
4423 Label L_failure;
4424 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
4425 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4426 bind(L_failure);
4427 }
4428
4429
4430 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4431 Register super_klass,
4432 Register temp_reg,
4433 Label* L_success,
4434 Label* L_failure,
4435 Label* L_slow_path,
4436 RegisterOrConstant super_check_offset) {
4437 assert_different_registers(sub_klass, super_klass, temp_reg);
4438 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4439 if (super_check_offset.is_register()) {
4440 assert_different_registers(sub_klass, super_klass,
4441 super_check_offset.as_register());
4442 } else if (must_load_sco) {
4443 assert(temp_reg != noreg, "supply either a temp or a register offset");
4444 }
4445
4446 Label L_fallthrough;
4447 int label_nulls = 0;
4448 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4449 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4450 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4451 assert(label_nulls <= 1, "at most one NULL in the batch");
4452
4453 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4454 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4455 Address super_check_offset_addr(super_klass, sco_offset);
4456
4457 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4458 // range of a jccb. If this routine grows larger, reconsider at
4459 // least some of these.
4460 #define local_jcc(assembler_cond, label) \
4461 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4462 else jcc( assembler_cond, label) /*omit semi*/
4463
4464 // Hacked jmp, which may only be used just before L_fallthrough.
4465 #define final_jmp(label) \
4466 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4467 else jmp(label) /*omit semi*/
4468
4469 // If the pointers are equal, we are done (e.g., String[] elements).
4470 // This self-check enables sharing of secondary supertype arrays among
4471 // non-primary types such as array-of-interface. Otherwise, each such
4472 // type would need its own customized SSA.
4473 // We move this check to the front of the fast path because many
4474 // type checks are in fact trivially successful in this manner,
4475 // so we get a nicely predicted branch right at the start of the check.
4476 cmpptr(sub_klass, super_klass);
4477 local_jcc(Assembler::equal, *L_success);
4478
4479 // Check the supertype display:
4480 if (must_load_sco) {
4481 // Positive movl does right thing on LP64.
4482 movl(temp_reg, super_check_offset_addr);
4483 super_check_offset = RegisterOrConstant(temp_reg);
4484 }
4485 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4486 cmpptr(super_klass, super_check_addr); // load displayed supertype
4487
4488 // This check has worked decisively for primary supers.
4489 // Secondary supers are sought in the super_cache ('super_cache_addr').
4490 // (Secondary supers are interfaces and very deeply nested subtypes.)
4491 // This works in the same check above because of a tricky aliasing
4492 // between the super_cache and the primary super display elements.
4493 // (The 'super_check_addr' can address either, as the case requires.)
4494 // Note that the cache is updated below if it does not help us find
4495 // what we need immediately.
4496 // So if it was a primary super, we can just fail immediately.
4497 // Otherwise, it's the slow path for us (no success at this point).
4498
4499 if (super_check_offset.is_register()) {
4500 local_jcc(Assembler::equal, *L_success);
4501 cmpl(super_check_offset.as_register(), sc_offset);
4502 if (L_failure == &L_fallthrough) {
4503 local_jcc(Assembler::equal, *L_slow_path);
4504 } else {
4505 local_jcc(Assembler::notEqual, *L_failure);
4506 final_jmp(*L_slow_path);
4507 }
4508 } else if (super_check_offset.as_constant() == sc_offset) {
4509 // Need a slow path; fast failure is impossible.
4510 if (L_slow_path == &L_fallthrough) {
4511 local_jcc(Assembler::equal, *L_success);
4512 } else {
4513 local_jcc(Assembler::notEqual, *L_slow_path);
4514 final_jmp(*L_success);
4515 }
4516 } else {
4517 // No slow path; it's a fast decision.
4518 if (L_failure == &L_fallthrough) {
4519 local_jcc(Assembler::equal, *L_success);
4520 } else {
4521 local_jcc(Assembler::notEqual, *L_failure);
4522 final_jmp(*L_success);
4523 }
4524 }
4525
4526 bind(L_fallthrough);
4527
4528 #undef local_jcc
4529 #undef final_jmp
4530 }
4531
4532
4533 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4534 Register super_klass,
4535 Register temp_reg,
4536 Register temp2_reg,
4537 Label* L_success,
4538 Label* L_failure,
4539 bool set_cond_codes) {
4540 assert_different_registers(sub_klass, super_klass, temp_reg);
4541 if (temp2_reg != noreg)
4542 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4543 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4544
4545 Label L_fallthrough;
4546 int label_nulls = 0;
4547 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4548 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4549 assert(label_nulls <= 1, "at most one NULL in the batch");
4550
4551 // a couple of useful fields in sub_klass:
4552 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4553 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4554 Address secondary_supers_addr(sub_klass, ss_offset);
4555 Address super_cache_addr( sub_klass, sc_offset);
4556
4557 // Do a linear scan of the secondary super-klass chain.
4558 // This code is rarely used, so simplicity is a virtue here.
4559 // The repne_scan instruction uses fixed registers, which we must spill.
4560 // Don't worry too much about pre-existing connections with the input regs.
4561
4562 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4563 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4564
4565 // Get super_klass value into rax (even if it was in rdi or rcx).
4566 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4567 if (super_klass != rax || UseCompressedOops) {
4568 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4569 mov(rax, super_klass);
4570 }
4571 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4572 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4573
4574 #ifndef PRODUCT
4575 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4576 ExternalAddress pst_counter_addr((address) pst_counter);
4577 NOT_LP64( incrementl(pst_counter_addr) );
4578 LP64_ONLY( lea(rcx, pst_counter_addr) );
4579 LP64_ONLY( incrementl(Address(rcx, 0)) );
4580 #endif //PRODUCT
4581
4582 // We will consult the secondary-super array.
4583 movptr(rdi, secondary_supers_addr);
4584 // Load the array length. (Positive movl does right thing on LP64.)
4585 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4586 // Skip to start of data.
4587 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4588
4589 // Scan RCX words at [RDI] for an occurrence of RAX.
4590 // Set NZ/Z based on last compare.
4591 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4592 // not change flags (only scas instruction which is repeated sets flags).
4593 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4594
4595 testptr(rax,rax); // Set Z = 0
4596 repne_scan();
4597
4598 // Unspill the temp. registers:
4599 if (pushed_rdi) pop(rdi);
4600 if (pushed_rcx) pop(rcx);
4601 if (pushed_rax) pop(rax);
4602
4603 if (set_cond_codes) {
4604 // Special hack for the AD files: rdi is guaranteed non-zero.
4605 assert(!pushed_rdi, "rdi must be left non-NULL");
4606 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4607 }
4608
4609 if (L_failure == &L_fallthrough)
4610 jccb(Assembler::notEqual, *L_failure);
4611 else jcc(Assembler::notEqual, *L_failure);
4612
4613 // Success. Cache the super we found and proceed in triumph.
4614 movptr(super_cache_addr, super_klass);
4615
4616 if (L_success != &L_fallthrough) {
4617 jmp(*L_success);
4618 }
4619
4620 #undef IS_A_TEMP
4621
4622 bind(L_fallthrough);
4623 }
4624
4625 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
4626 assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required");
4627
4628 Label L_fallthrough;
4629 if (L_fast_path == NULL) {
4630 L_fast_path = &L_fallthrough;
4631 } else if (L_slow_path == NULL) {
4632 L_slow_path = &L_fallthrough;
4633 }
4634
4635 // Fast path check: class is fully initialized
4636 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4637 jcc(Assembler::equal, *L_fast_path);
4638
4639 // Fast path check: current thread is initializer thread
4640 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
4641 if (L_slow_path == &L_fallthrough) {
4642 jcc(Assembler::equal, *L_fast_path);
4643 bind(*L_slow_path);
4644 } else if (L_fast_path == &L_fallthrough) {
4645 jcc(Assembler::notEqual, *L_slow_path);
4646 bind(*L_fast_path);
4647 } else {
4648 Unimplemented();
4649 }
4650 }
4651
4652 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4653 if (VM_Version::supports_cmov()) {
4654 cmovl(cc, dst, src);
4655 } else {
4656 Label L;
4657 jccb(negate_condition(cc), L);
4658 movl(dst, src);
4659 bind(L);
4660 }
4661 }
4662
4663 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4664 if (VM_Version::supports_cmov()) {
4665 cmovl(cc, dst, src);
4666 } else {
4667 Label L;
4668 jccb(negate_condition(cc), L);
4669 movl(dst, src);
4670 bind(L);
4671 }
4672 }
4673
4674 void MacroAssembler::verify_oop(Register reg, const char* s) {
4675 if (!VerifyOops) return;
4676
4677 // Pass register number to verify_oop_subroutine
4678 const char* b = NULL;
4679 {
4680 ResourceMark rm;
4681 stringStream ss;
4682 ss.print("verify_oop: %s: %s", reg->name(), s);
4683 b = code_string(ss.as_string());
4684 }
4685 BLOCK_COMMENT("verify_oop {");
4686 #ifdef _LP64
4687 push(rscratch1); // save r10, trashed by movptr()
4688 #endif
4689 push(rax); // save rax,
4690 push(reg); // pass register argument
4691 ExternalAddress buffer((address) b);
4692 // avoid using pushptr, as it modifies scratch registers
4693 // and our contract is not to modify anything
4694 movptr(rax, buffer.addr());
4695 push(rax);
4696 // call indirectly to solve generation ordering problem
4697 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4698 call(rax);
4699 // Caller pops the arguments (oop, message) and restores rax, r10
4700 BLOCK_COMMENT("} verify_oop");
4701 }
4702
4703
4704 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
4705 Register tmp,
4706 int offset) {
4707 intptr_t value = *delayed_value_addr;
4708 if (value != 0)
4709 return RegisterOrConstant(value + offset);
4710
4711 // load indirectly to solve generation ordering problem
4712 movptr(tmp, ExternalAddress((address) delayed_value_addr));
4713
4714 #ifdef ASSERT
4715 { Label L;
4716 testptr(tmp, tmp);
4717 if (WizardMode) {
4718 const char* buf = NULL;
4719 {
4720 ResourceMark rm;
4721 stringStream ss;
4722 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
4723 buf = code_string(ss.as_string());
4724 }
4725 jcc(Assembler::notZero, L);
4726 STOP(buf);
4727 } else {
4728 jccb(Assembler::notZero, L);
4729 hlt();
4730 }
4731 bind(L);
4732 }
4733 #endif
4734
4735 if (offset != 0)
4736 addptr(tmp, offset);
4737
4738 return RegisterOrConstant(tmp);
4739 }
4740
4741
4742 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4743 int extra_slot_offset) {
4744 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4745 int stackElementSize = Interpreter::stackElementSize;
4746 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4747 #ifdef ASSERT
4748 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4749 assert(offset1 - offset == stackElementSize, "correct arithmetic");
4750 #endif
4751 Register scale_reg = noreg;
4752 Address::ScaleFactor scale_factor = Address::no_scale;
4753 if (arg_slot.is_constant()) {
4754 offset += arg_slot.as_constant() * stackElementSize;
4755 } else {
4756 scale_reg = arg_slot.as_register();
4757 scale_factor = Address::times(stackElementSize);
4758 }
4759 offset += wordSize; // return PC is on stack
4760 return Address(rsp, scale_reg, scale_factor, offset);
4761 }
4762
4763
4764 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
4765 if (!VerifyOops) return;
4766
4767 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
4768 // Pass register number to verify_oop_subroutine
4769 const char* b = NULL;
4770 {
4771 ResourceMark rm;
4772 stringStream ss;
4773 ss.print("verify_oop_addr: %s", s);
4774 b = code_string(ss.as_string());
4775 }
4776 #ifdef _LP64
4777 push(rscratch1); // save r10, trashed by movptr()
4778 #endif
4779 push(rax); // save rax,
4780 // addr may contain rsp so we will have to adjust it based on the push
4781 // we just did (and on 64 bit we do two pushes)
4782 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4783 // stores rax into addr which is backwards of what was intended.
4784 if (addr.uses(rsp)) {
4785 lea(rax, addr);
4786 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
4787 } else {
4788 pushptr(addr);
4789 }
4790
4791 ExternalAddress buffer((address) b);
4792 // pass msg argument
4793 // avoid using pushptr, as it modifies scratch registers
4794 // and our contract is not to modify anything
4795 movptr(rax, buffer.addr());
4796 push(rax);
4797
4798 // call indirectly to solve generation ordering problem
4799 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4800 call(rax);
4801 // Caller pops the arguments (addr, message) and restores rax, r10.
4802 }
4803
4804 void MacroAssembler::verify_tlab() {
4805 #ifdef ASSERT
4806 if (UseTLAB && VerifyOops) {
4807 Label next, ok;
4808 Register t1 = rsi;
4809 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
4810
4811 push(t1);
4812 NOT_LP64(push(thread_reg));
4813 NOT_LP64(get_thread(thread_reg));
4814
4815 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4816 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4817 jcc(Assembler::aboveEqual, next);
4818 STOP("assert(top >= start)");
4819 should_not_reach_here();
4820
4821 bind(next);
4822 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4823 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4824 jcc(Assembler::aboveEqual, ok);
4825 STOP("assert(top <= end)");
4826 should_not_reach_here();
4827
4828 bind(ok);
4829 NOT_LP64(pop(thread_reg));
4830 pop(t1);
4831 }
4832 #endif
4833 }
4834
4835 class ControlWord {
4836 public:
4837 int32_t _value;
4838
4839 int rounding_control() const { return (_value >> 10) & 3 ; }
4840 int precision_control() const { return (_value >> 8) & 3 ; }
4841 bool precision() const { return ((_value >> 5) & 1) != 0; }
4842 bool underflow() const { return ((_value >> 4) & 1) != 0; }
4843 bool overflow() const { return ((_value >> 3) & 1) != 0; }
4844 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
4845 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
4846 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4847
4848 void print() const {
4849 // rounding control
4850 const char* rc;
4851 switch (rounding_control()) {
4852 case 0: rc = "round near"; break;
4853 case 1: rc = "round down"; break;
4854 case 2: rc = "round up "; break;
4855 case 3: rc = "chop "; break;
4856 };
4857 // precision control
4858 const char* pc;
4859 switch (precision_control()) {
4860 case 0: pc = "24 bits "; break;
4861 case 1: pc = "reserved"; break;
4862 case 2: pc = "53 bits "; break;
4863 case 3: pc = "64 bits "; break;
4864 };
4865 // flags
4866 char f[9];
4867 f[0] = ' ';
4868 f[1] = ' ';
4869 f[2] = (precision ()) ? 'P' : 'p';
4870 f[3] = (underflow ()) ? 'U' : 'u';
4871 f[4] = (overflow ()) ? 'O' : 'o';
4872 f[5] = (zero_divide ()) ? 'Z' : 'z';
4873 f[6] = (denormalized()) ? 'D' : 'd';
4874 f[7] = (invalid ()) ? 'I' : 'i';
4875 f[8] = '\x0';
4876 // output
4877 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4878 }
4879
4880 };
4881
4882 class StatusWord {
4883 public:
4884 int32_t _value;
4885
4886 bool busy() const { return ((_value >> 15) & 1) != 0; }
4887 bool C3() const { return ((_value >> 14) & 1) != 0; }
4888 bool C2() const { return ((_value >> 10) & 1) != 0; }
4889 bool C1() const { return ((_value >> 9) & 1) != 0; }
4890 bool C0() const { return ((_value >> 8) & 1) != 0; }
4891 int top() const { return (_value >> 11) & 7 ; }
4892 bool error_status() const { return ((_value >> 7) & 1) != 0; }
4893 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
4894 bool precision() const { return ((_value >> 5) & 1) != 0; }
4895 bool underflow() const { return ((_value >> 4) & 1) != 0; }
4896 bool overflow() const { return ((_value >> 3) & 1) != 0; }
4897 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
4898 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
4899 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4900
4901 void print() const {
4902 // condition codes
4903 char c[5];
4904 c[0] = (C3()) ? '3' : '-';
4905 c[1] = (C2()) ? '2' : '-';
4906 c[2] = (C1()) ? '1' : '-';
4907 c[3] = (C0()) ? '0' : '-';
4908 c[4] = '\x0';
4909 // flags
4910 char f[9];
4911 f[0] = (error_status()) ? 'E' : '-';
4912 f[1] = (stack_fault ()) ? 'S' : '-';
4913 f[2] = (precision ()) ? 'P' : '-';
4914 f[3] = (underflow ()) ? 'U' : '-';
4915 f[4] = (overflow ()) ? 'O' : '-';
4916 f[5] = (zero_divide ()) ? 'Z' : '-';
4917 f[6] = (denormalized()) ? 'D' : '-';
4918 f[7] = (invalid ()) ? 'I' : '-';
4919 f[8] = '\x0';
4920 // output
4921 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
4922 }
4923
4924 };
4925
4926 class TagWord {
4927 public:
4928 int32_t _value;
4929
4930 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
4931
4932 void print() const {
4933 printf("%04x", _value & 0xFFFF);
4934 }
4935
4936 };
4937
4938 class FPU_Register {
4939 public:
4940 int32_t _m0;
4941 int32_t _m1;
4942 int16_t _ex;
4943
4944 bool is_indefinite() const {
4945 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
4946 }
4947
4948 void print() const {
4949 char sign = (_ex < 0) ? '-' : '+';
4950 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
4951 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
4952 };
4953
4954 };
4955
4956 class FPU_State {
4957 public:
4958 enum {
4959 register_size = 10,
4960 number_of_registers = 8,
4961 register_mask = 7
4962 };
4963
4964 ControlWord _control_word;
4965 StatusWord _status_word;
4966 TagWord _tag_word;
4967 int32_t _error_offset;
4968 int32_t _error_selector;
4969 int32_t _data_offset;
4970 int32_t _data_selector;
4971 int8_t _register[register_size * number_of_registers];
4972
4973 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
4974 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
4975
4976 const char* tag_as_string(int tag) const {
4977 switch (tag) {
4978 case 0: return "valid";
4979 case 1: return "zero";
4980 case 2: return "special";
4981 case 3: return "empty";
4982 }
4983 ShouldNotReachHere();
4984 return NULL;
4985 }
4986
4987 void print() const {
4988 // print computation registers
4989 { int t = _status_word.top();
4990 for (int i = 0; i < number_of_registers; i++) {
4991 int j = (i - t) & register_mask;
4992 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
4993 st(j)->print();
4994 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
4995 }
4996 }
4997 printf("\n");
4998 // print control registers
4999 printf("ctrl = "); _control_word.print(); printf("\n");
5000 printf("stat = "); _status_word .print(); printf("\n");
5001 printf("tags = "); _tag_word .print(); printf("\n");
5002 }
5003
5004 };
5005
5006 class Flag_Register {
5007 public:
5008 int32_t _value;
5009
5010 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5011 bool direction() const { return ((_value >> 10) & 1) != 0; }
5012 bool sign() const { return ((_value >> 7) & 1) != 0; }
5013 bool zero() const { return ((_value >> 6) & 1) != 0; }
5014 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5015 bool parity() const { return ((_value >> 2) & 1) != 0; }
5016 bool carry() const { return ((_value >> 0) & 1) != 0; }
5017
5018 void print() const {
5019 // flags
5020 char f[8];
5021 f[0] = (overflow ()) ? 'O' : '-';
5022 f[1] = (direction ()) ? 'D' : '-';
5023 f[2] = (sign ()) ? 'S' : '-';
5024 f[3] = (zero ()) ? 'Z' : '-';
5025 f[4] = (auxiliary_carry()) ? 'A' : '-';
5026 f[5] = (parity ()) ? 'P' : '-';
5027 f[6] = (carry ()) ? 'C' : '-';
5028 f[7] = '\x0';
5029 // output
5030 printf("%08x flags = %s", _value, f);
5031 }
5032
5033 };
5034
5035 class IU_Register {
5036 public:
5037 int32_t _value;
5038
5039 void print() const {
5040 printf("%08x %11d", _value, _value);
5041 }
5042
5043 };
5044
5045 class IU_State {
5046 public:
5047 Flag_Register _eflags;
5048 IU_Register _rdi;
5049 IU_Register _rsi;
5050 IU_Register _rbp;
5051 IU_Register _rsp;
5052 IU_Register _rbx;
5053 IU_Register _rdx;
5054 IU_Register _rcx;
5055 IU_Register _rax;
5056
5057 void print() const {
5058 // computation registers
5059 printf("rax, = "); _rax.print(); printf("\n");
5060 printf("rbx, = "); _rbx.print(); printf("\n");
5061 printf("rcx = "); _rcx.print(); printf("\n");
5062 printf("rdx = "); _rdx.print(); printf("\n");
5063 printf("rdi = "); _rdi.print(); printf("\n");
5064 printf("rsi = "); _rsi.print(); printf("\n");
5065 printf("rbp, = "); _rbp.print(); printf("\n");
5066 printf("rsp = "); _rsp.print(); printf("\n");
5067 printf("\n");
5068 // control registers
5069 printf("flgs = "); _eflags.print(); printf("\n");
5070 }
5071 };
5072
5073
5074 class CPU_State {
5075 public:
5076 FPU_State _fpu_state;
5077 IU_State _iu_state;
5078
5079 void print() const {
5080 printf("--------------------------------------------------\n");
5081 _iu_state .print();
5082 printf("\n");
5083 _fpu_state.print();
5084 printf("--------------------------------------------------\n");
5085 }
5086
5087 };
5088
5089
5090 static void _print_CPU_state(CPU_State* state) {
5091 state->print();
5092 };
5093
5094
5095 void MacroAssembler::print_CPU_state() {
5096 push_CPU_state();
5097 push(rsp); // pass CPU state
5098 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5099 addptr(rsp, wordSize); // discard argument
5100 pop_CPU_state();
5101 }
5102
5103
5104 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5105 static int counter = 0;
5106 FPU_State* fs = &state->_fpu_state;
5107 counter++;
5108 // For leaf calls, only verify that the top few elements remain empty.
5109 // We only need 1 empty at the top for C2 code.
5110 if( stack_depth < 0 ) {
5111 if( fs->tag_for_st(7) != 3 ) {
5112 printf("FPR7 not empty\n");
5113 state->print();
5114 assert(false, "error");
5115 return false;
5116 }
5117 return true; // All other stack states do not matter
5118 }
5119
5120 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5121 "bad FPU control word");
5122
5123 // compute stack depth
5124 int i = 0;
5125 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5126 int d = i;
5127 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5128 // verify findings
5129 if (i != FPU_State::number_of_registers) {
5130 // stack not contiguous
5131 printf("%s: stack not contiguous at ST%d\n", s, i);
5132 state->print();
5133 assert(false, "error");
5134 return false;
5135 }
5136 // check if computed stack depth corresponds to expected stack depth
5137 if (stack_depth < 0) {
5138 // expected stack depth is -stack_depth or less
5139 if (d > -stack_depth) {
5140 // too many elements on the stack
5141 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5142 state->print();
5143 assert(false, "error");
5144 return false;
5145 }
5146 } else {
5147 // expected stack depth is stack_depth
5148 if (d != stack_depth) {
5149 // wrong stack depth
5150 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5151 state->print();
5152 assert(false, "error");
5153 return false;
5154 }
5155 }
5156 // everything is cool
5157 return true;
5158 }
5159
5160
5161 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5162 if (!VerifyFPU) return;
5163 push_CPU_state();
5164 push(rsp); // pass CPU state
5165 ExternalAddress msg((address) s);
5166 // pass message string s
5167 pushptr(msg.addr());
5168 push(stack_depth); // pass stack depth
5169 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5170 addptr(rsp, 3 * wordSize); // discard arguments
5171 // check for error
5172 { Label L;
5173 testl(rax, rax);
5174 jcc(Assembler::notZero, L);
5175 int3(); // break if error condition
5176 bind(L);
5177 }
5178 pop_CPU_state();
5179 }
5180
5181 void MacroAssembler::restore_cpu_control_state_after_jni() {
5182 // Either restore the MXCSR register after returning from the JNI Call
5183 // or verify that it wasn't changed (with -Xcheck:jni flag).
5184 if (VM_Version::supports_sse()) {
5185 if (RestoreMXCSROnJNICalls) {
5186 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5187 } else if (CheckJNICalls) {
5188 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5189 }
5190 }
5191 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5192 vzeroupper();
5193 // Reset k1 to 0xffff.
5194
5195 #ifdef COMPILER2
5196 if (PostLoopMultiversioning && VM_Version::supports_evex()) {
5197 push(rcx);
5198 movl(rcx, 0xffff);
5199 kmovwl(k1, rcx);
5200 pop(rcx);
5201 }
5202 #endif // COMPILER2
5203
5204 #ifndef _LP64
5205 // Either restore the x87 floating pointer control word after returning
5206 // from the JNI call or verify that it wasn't changed.
5207 if (CheckJNICalls) {
5208 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5209 }
5210 #endif // _LP64
5211 }
5212
5213 // ((OopHandle)result).resolve();
5214 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5215 assert_different_registers(result, tmp);
5216
5217 // Only 64 bit platforms support GCs that require a tmp register
5218 // Only IN_HEAP loads require a thread_tmp register
5219 // OopHandle::resolve is an indirection like jobject.
5220 access_load_at(T_OBJECT, IN_NATIVE,
5221 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5222 }
5223
5224 // ((WeakHandle)result).resolve();
5225 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5226 assert_different_registers(rresult, rtmp);
5227 Label resolved;
5228
5229 // A null weak handle resolves to null.
5230 cmpptr(rresult, 0);
5231 jcc(Assembler::equal, resolved);
5232
5233 // Only 64 bit platforms support GCs that require a tmp register
5234 // Only IN_HEAP loads require a thread_tmp register
5235 // WeakHandle::resolve is an indirection like jweak.
5236 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5237 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
5238 bind(resolved);
5239 }
5240
5241 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5242 // get mirror
5243 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5244 load_method_holder(mirror, method);
5245 movptr(mirror, Address(mirror, mirror_offset));
5246 resolve_oop_handle(mirror, tmp);
5247 }
5248
5249 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5250 load_method_holder(rresult, rmethod);
5251 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5252 }
5253
5254 void MacroAssembler::load_method_holder(Register holder, Register method) {
5255 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5256 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5257 movptr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass*
5258 }
5259
5260 void MacroAssembler::load_klass(Register dst, Register src) {
5261 #ifdef _LP64
5262 if (UseCompressedClassPointers) {
5263 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5264 decode_klass_not_null(dst);
5265 } else
5266 #endif
5267 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5268 }
5269
5270 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5271 load_klass(dst, src);
5272 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5273 }
5274
5275 void MacroAssembler::store_klass(Register dst, Register src) {
5276 #ifdef _LP64
5277 if (UseCompressedClassPointers) {
5278 encode_klass_not_null(src);
5279 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5280 } else
5281 #endif
5282 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5283 }
5284
5285 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5286 Register tmp1, Register thread_tmp) {
5287 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5288 decorators = AccessInternal::decorator_fixup(decorators);
5289 bool as_raw = (decorators & AS_RAW) != 0;
5290 if (as_raw) {
5291 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5292 } else {
5293 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5294 }
5295 }
5296
5297 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
5298 Register tmp1, Register tmp2) {
5299 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5300 decorators = AccessInternal::decorator_fixup(decorators);
5301 bool as_raw = (decorators & AS_RAW) != 0;
5302 if (as_raw) {
5303 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2);
5304 } else {
5305 bs->store_at(this, decorators, type, dst, src, tmp1, tmp2);
5306 }
5307 }
5308
5309 void MacroAssembler::resolve(DecoratorSet decorators, Register obj) {
5310 // Use stronger ACCESS_WRITE|ACCESS_READ by default.
5311 if ((decorators & (ACCESS_READ | ACCESS_WRITE)) == 0) {
5312 decorators |= ACCESS_READ | ACCESS_WRITE;
5313 }
5314 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5315 return bs->resolve(this, decorators, obj);
5316 }
5317
5318 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5319 Register thread_tmp, DecoratorSet decorators) {
5320 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
5321 }
5322
5323 // Doesn't do verfication, generates fixed size code
5324 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5325 Register thread_tmp, DecoratorSet decorators) {
5326 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
5327 }
5328
5329 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
5330 Register tmp2, DecoratorSet decorators) {
5331 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5332 }
5333
5334 // Used for storing NULLs.
5335 void MacroAssembler::store_heap_oop_null(Address dst) {
5336 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
5337 }
5338
5339 #ifdef _LP64
5340 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5341 if (UseCompressedClassPointers) {
5342 // Store to klass gap in destination
5343 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5344 }
5345 }
5346
5347 #ifdef ASSERT
5348 void MacroAssembler::verify_heapbase(const char* msg) {
5349 assert (UseCompressedOops, "should be compressed");
5350 assert (Universe::heap() != NULL, "java heap should be initialized");
5351 if (CheckCompressedOops) {
5352 Label ok;
5353 push(rscratch1); // cmpptr trashes rscratch1
5354 cmpptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
5355 jcc(Assembler::equal, ok);
5356 STOP(msg);
5357 bind(ok);
5358 pop(rscratch1);
5359 }
5360 }
5361 #endif
5362
5363 // Algorithm must match oop.inline.hpp encode_heap_oop.
5364 void MacroAssembler::encode_heap_oop(Register r) {
5365 #ifdef ASSERT
5366 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5367 #endif
5368 verify_oop(r, "broken oop in encode_heap_oop");
5369 if (CompressedOops::base() == NULL) {
5370 if (CompressedOops::shift() != 0) {
5371 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5372 shrq(r, LogMinObjAlignmentInBytes);
5373 }
5374 return;
5375 }
5376 testq(r, r);
5377 cmovq(Assembler::equal, r, r12_heapbase);
5378 subq(r, r12_heapbase);
5379 shrq(r, LogMinObjAlignmentInBytes);
5380 }
5381
5382 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5383 #ifdef ASSERT
5384 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5385 if (CheckCompressedOops) {
5386 Label ok;
5387 testq(r, r);
5388 jcc(Assembler::notEqual, ok);
5389 STOP("null oop passed to encode_heap_oop_not_null");
5390 bind(ok);
5391 }
5392 #endif
5393 verify_oop(r, "broken oop in encode_heap_oop_not_null");
5394 if (CompressedOops::base() != NULL) {
5395 subq(r, r12_heapbase);
5396 }
5397 if (CompressedOops::shift() != 0) {
5398 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5399 shrq(r, LogMinObjAlignmentInBytes);
5400 }
5401 }
5402
5403 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5404 #ifdef ASSERT
5405 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5406 if (CheckCompressedOops) {
5407 Label ok;
5408 testq(src, src);
5409 jcc(Assembler::notEqual, ok);
5410 STOP("null oop passed to encode_heap_oop_not_null2");
5411 bind(ok);
5412 }
5413 #endif
5414 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5415 if (dst != src) {
5416 movq(dst, src);
5417 }
5418 if (CompressedOops::base() != NULL) {
5419 subq(dst, r12_heapbase);
5420 }
5421 if (CompressedOops::shift() != 0) {
5422 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5423 shrq(dst, LogMinObjAlignmentInBytes);
5424 }
5425 }
5426
5427 void MacroAssembler::decode_heap_oop(Register r) {
5428 #ifdef ASSERT
5429 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5430 #endif
5431 if (CompressedOops::base() == NULL) {
5432 if (CompressedOops::shift() != 0) {
5433 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5434 shlq(r, LogMinObjAlignmentInBytes);
5435 }
5436 } else {
5437 Label done;
5438 shlq(r, LogMinObjAlignmentInBytes);
5439 jccb(Assembler::equal, done);
5440 addq(r, r12_heapbase);
5441 bind(done);
5442 }
5443 verify_oop(r, "broken oop in decode_heap_oop");
5444 }
5445
5446 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5447 // Note: it will change flags
5448 assert (UseCompressedOops, "should only be used for compressed headers");
5449 assert (Universe::heap() != NULL, "java heap should be initialized");
5450 // Cannot assert, unverified entry point counts instructions (see .ad file)
5451 // vtableStubs also counts instructions in pd_code_size_limit.
5452 // Also do not verify_oop as this is called by verify_oop.
5453 if (CompressedOops::shift() != 0) {
5454 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5455 shlq(r, LogMinObjAlignmentInBytes);
5456 if (CompressedOops::base() != NULL) {
5457 addq(r, r12_heapbase);
5458 }
5459 } else {
5460 assert (CompressedOops::base() == NULL, "sanity");
5461 }
5462 }
5463
5464 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5465 // Note: it will change flags
5466 assert (UseCompressedOops, "should only be used for compressed headers");
5467 assert (Universe::heap() != NULL, "java heap should be initialized");
5468 // Cannot assert, unverified entry point counts instructions (see .ad file)
5469 // vtableStubs also counts instructions in pd_code_size_limit.
5470 // Also do not verify_oop as this is called by verify_oop.
5471 if (CompressedOops::shift() != 0) {
5472 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5473 if (LogMinObjAlignmentInBytes == Address::times_8) {
5474 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5475 } else {
5476 if (dst != src) {
5477 movq(dst, src);
5478 }
5479 shlq(dst, LogMinObjAlignmentInBytes);
5480 if (CompressedOops::base() != NULL) {
5481 addq(dst, r12_heapbase);
5482 }
5483 }
5484 } else {
5485 assert (CompressedOops::base() == NULL, "sanity");
5486 if (dst != src) {
5487 movq(dst, src);
5488 }
5489 }
5490 }
5491
5492 void MacroAssembler::encode_klass_not_null(Register r) {
5493 if (CompressedKlassPointers::base() != NULL) {
5494 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5495 assert(r != r12_heapbase, "Encoding a klass in r12");
5496 mov64(r12_heapbase, (int64_t)CompressedKlassPointers::base());
5497 subq(r, r12_heapbase);
5498 }
5499 if (CompressedKlassPointers::shift() != 0) {
5500 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5501 shrq(r, LogKlassAlignmentInBytes);
5502 }
5503 if (CompressedKlassPointers::base() != NULL) {
5504 reinit_heapbase();
5505 }
5506 }
5507
5508 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5509 if (dst == src) {
5510 encode_klass_not_null(src);
5511 } else {
5512 if (CompressedKlassPointers::base() != NULL) {
5513 mov64(dst, (int64_t)CompressedKlassPointers::base());
5514 negq(dst);
5515 addq(dst, src);
5516 } else {
5517 movptr(dst, src);
5518 }
5519 if (CompressedKlassPointers::shift() != 0) {
5520 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5521 shrq(dst, LogKlassAlignmentInBytes);
5522 }
5523 }
5524 }
5525
5526 // Function instr_size_for_decode_klass_not_null() counts the instructions
5527 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5528 // when (Universe::heap() != NULL). Hence, if the instructions they
5529 // generate change, then this method needs to be updated.
5530 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5531 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5532 if (CompressedKlassPointers::base() != NULL) {
5533 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
5534 return (CompressedKlassPointers::shift() == 0 ? 20 : 24);
5535 } else {
5536 // longest load decode klass function, mov64, leaq
5537 return 16;
5538 }
5539 }
5540
5541 // !!! If the instructions that get generated here change then function
5542 // instr_size_for_decode_klass_not_null() needs to get updated.
5543 void MacroAssembler::decode_klass_not_null(Register r) {
5544 // Note: it will change flags
5545 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5546 assert(r != r12_heapbase, "Decoding a klass in r12");
5547 // Cannot assert, unverified entry point counts instructions (see .ad file)
5548 // vtableStubs also counts instructions in pd_code_size_limit.
5549 // Also do not verify_oop as this is called by verify_oop.
5550 if (CompressedKlassPointers::shift() != 0) {
5551 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5552 shlq(r, LogKlassAlignmentInBytes);
5553 }
5554 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5555 if (CompressedKlassPointers::base() != NULL) {
5556 mov64(r12_heapbase, (int64_t)CompressedKlassPointers::base());
5557 addq(r, r12_heapbase);
5558 reinit_heapbase();
5559 }
5560 }
5561
5562 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5563 // Note: it will change flags
5564 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5565 if (dst == src) {
5566 decode_klass_not_null(dst);
5567 } else {
5568 // Cannot assert, unverified entry point counts instructions (see .ad file)
5569 // vtableStubs also counts instructions in pd_code_size_limit.
5570 // Also do not verify_oop as this is called by verify_oop.
5571 mov64(dst, (int64_t)CompressedKlassPointers::base());
5572 if (CompressedKlassPointers::shift() != 0) {
5573 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5574 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
5575 leaq(dst, Address(dst, src, Address::times_8, 0));
5576 } else {
5577 addq(dst, src);
5578 }
5579 }
5580 }
5581
5582 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5583 assert (UseCompressedOops, "should only be used for compressed headers");
5584 assert (Universe::heap() != NULL, "java heap should be initialized");
5585 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5586 int oop_index = oop_recorder()->find_index(obj);
5587 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5588 mov_narrow_oop(dst, oop_index, rspec);
5589 }
5590
5591 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5592 assert (UseCompressedOops, "should only be used for compressed headers");
5593 assert (Universe::heap() != NULL, "java heap should be initialized");
5594 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5595 int oop_index = oop_recorder()->find_index(obj);
5596 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5597 mov_narrow_oop(dst, oop_index, rspec);
5598 }
5599
5600 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5601 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5602 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5603 int klass_index = oop_recorder()->find_index(k);
5604 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5605 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5606 }
5607
5608 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5609 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5610 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5611 int klass_index = oop_recorder()->find_index(k);
5612 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5613 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5614 }
5615
5616 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5617 assert (UseCompressedOops, "should only be used for compressed headers");
5618 assert (Universe::heap() != NULL, "java heap should be initialized");
5619 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5620 int oop_index = oop_recorder()->find_index(obj);
5621 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5622 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5623 }
5624
5625 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5626 assert (UseCompressedOops, "should only be used for compressed headers");
5627 assert (Universe::heap() != NULL, "java heap should be initialized");
5628 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5629 int oop_index = oop_recorder()->find_index(obj);
5630 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5631 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5632 }
5633
5634 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5635 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5636 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5637 int klass_index = oop_recorder()->find_index(k);
5638 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5639 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5640 }
5641
5642 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5643 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5644 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5645 int klass_index = oop_recorder()->find_index(k);
5646 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5647 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5648 }
5649
5650 void MacroAssembler::reinit_heapbase() {
5651 if (UseCompressedOops || UseCompressedClassPointers) {
5652 if (Universe::heap() != NULL) {
5653 if (CompressedOops::base() == NULL) {
5654 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5655 } else {
5656 mov64(r12_heapbase, (int64_t)CompressedOops::ptrs_base());
5657 }
5658 } else {
5659 movptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
5660 }
5661 }
5662 }
5663
5664 #endif // _LP64
5665
5666 // C2 compiled method's prolog code.
5667 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub) {
5668
5669 // WARNING: Initial instruction MUST be 5 bytes or longer so that
5670 // NativeJump::patch_verified_entry will be able to patch out the entry
5671 // code safely. The push to verify stack depth is ok at 5 bytes,
5672 // the frame allocation can be either 3 or 6 bytes. So if we don't do
5673 // stack bang then we must use the 6 byte frame allocation even if
5674 // we have no frame. :-(
5675 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
5676
5677 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5678 // Remove word for return addr
5679 framesize -= wordSize;
5680 stack_bang_size -= wordSize;
5681
5682 // Calls to C2R adapters often do not accept exceptional returns.
5683 // We require that their callers must bang for them. But be careful, because
5684 // some VM calls (such as call site linkage) can use several kilobytes of
5685 // stack. But the stack safety zone should account for that.
5686 // See bugs 4446381, 4468289, 4497237.
5687 if (stack_bang_size > 0) {
5688 generate_stack_overflow_check(stack_bang_size);
5689
5690 // We always push rbp, so that on return to interpreter rbp, will be
5691 // restored correctly and we can correct the stack.
5692 push(rbp);
5693 // Save caller's stack pointer into RBP if the frame pointer is preserved.
5694 if (PreserveFramePointer) {
5695 mov(rbp, rsp);
5696 }
5697 // Remove word for ebp
5698 framesize -= wordSize;
5699
5700 // Create frame
5701 if (framesize) {
5702 subptr(rsp, framesize);
5703 }
5704 } else {
5705 // Create frame (force generation of a 4 byte immediate value)
5706 subptr_imm32(rsp, framesize);
5707
5708 // Save RBP register now.
5709 framesize -= wordSize;
5710 movptr(Address(rsp, framesize), rbp);
5711 // Save caller's stack pointer into RBP if the frame pointer is preserved.
5712 if (PreserveFramePointer) {
5713 movptr(rbp, rsp);
5714 if (framesize > 0) {
5715 addptr(rbp, framesize);
5716 }
5717 }
5718 }
5719
5720 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
5721 framesize -= wordSize;
5722 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
5723 }
5724
5725 #ifndef _LP64
5726 // If method sets FPU control word do it now
5727 if (fp_mode_24b) {
5728 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
5729 }
5730 if (UseSSE >= 2 && VerifyFPU) {
5731 verify_FPU(0, "FPU stack must be clean on entry");
5732 }
5733 #endif
5734
5735 #ifdef ASSERT
5736 if (VerifyStackAtCalls) {
5737 Label L;
5738 push(rax);
5739 mov(rax, rsp);
5740 andptr(rax, StackAlignmentInBytes-1);
5741 cmpptr(rax, StackAlignmentInBytes-wordSize);
5742 pop(rax);
5743 jcc(Assembler::equal, L);
5744 STOP("Stack is not properly aligned!");
5745 bind(L);
5746 }
5747 #endif
5748
5749 if (!is_stub) {
5750 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5751 bs->nmethod_entry_barrier(this);
5752 }
5753 }
5754
5755 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
5756 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp) {
5757 // cnt - number of qwords (8-byte words).
5758 // base - start address, qword aligned.
5759 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5760 if (UseAVX >= 2) {
5761 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5762 } else {
5763 pxor(xtmp, xtmp);
5764 }
5765 jmp(L_zero_64_bytes);
5766
5767 BIND(L_loop);
5768 if (UseAVX >= 2) {
5769 vmovdqu(Address(base, 0), xtmp);
5770 vmovdqu(Address(base, 32), xtmp);
5771 } else {
5772 movdqu(Address(base, 0), xtmp);
5773 movdqu(Address(base, 16), xtmp);
5774 movdqu(Address(base, 32), xtmp);
5775 movdqu(Address(base, 48), xtmp);
5776 }
5777 addptr(base, 64);
5778
5779 BIND(L_zero_64_bytes);
5780 subptr(cnt, 8);
5781 jccb(Assembler::greaterEqual, L_loop);
5782 addptr(cnt, 4);
5783 jccb(Assembler::less, L_tail);
5784 // Copy trailing 32 bytes
5785 if (UseAVX >= 2) {
5786 vmovdqu(Address(base, 0), xtmp);
5787 } else {
5788 movdqu(Address(base, 0), xtmp);
5789 movdqu(Address(base, 16), xtmp);
5790 }
5791 addptr(base, 32);
5792 subptr(cnt, 4);
5793
5794 BIND(L_tail);
5795 addptr(cnt, 4);
5796 jccb(Assembler::lessEqual, L_end);
5797 decrement(cnt);
5798
5799 BIND(L_sloop);
5800 movq(Address(base, 0), xtmp);
5801 addptr(base, 8);
5802 decrement(cnt);
5803 jccb(Assembler::greaterEqual, L_sloop);
5804 BIND(L_end);
5805 }
5806
5807 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp, bool is_large) {
5808 // cnt - number of qwords (8-byte words).
5809 // base - start address, qword aligned.
5810 // is_large - if optimizers know cnt is larger than InitArrayShortSize
5811 assert(base==rdi, "base register must be edi for rep stos");
5812 assert(tmp==rax, "tmp register must be eax for rep stos");
5813 assert(cnt==rcx, "cnt register must be ecx for rep stos");
5814 assert(InitArrayShortSize % BytesPerLong == 0,
5815 "InitArrayShortSize should be the multiple of BytesPerLong");
5816
5817 Label DONE;
5818
5819 if (!is_large || !UseXMMForObjInit) {
5820 xorptr(tmp, tmp);
5821 }
5822
5823 if (!is_large) {
5824 Label LOOP, LONG;
5825 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
5826 jccb(Assembler::greater, LONG);
5827
5828 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5829
5830 decrement(cnt);
5831 jccb(Assembler::negative, DONE); // Zero length
5832
5833 // Use individual pointer-sized stores for small counts:
5834 BIND(LOOP);
5835 movptr(Address(base, cnt, Address::times_ptr), tmp);
5836 decrement(cnt);
5837 jccb(Assembler::greaterEqual, LOOP);
5838 jmpb(DONE);
5839
5840 BIND(LONG);
5841 }
5842
5843 // Use longer rep-prefixed ops for non-small counts:
5844 if (UseFastStosb) {
5845 shlptr(cnt, 3); // convert to number of bytes
5846 rep_stosb();
5847 } else if (UseXMMForObjInit) {
5848 movptr(tmp, base);
5849 xmm_clear_mem(tmp, cnt, xtmp);
5850 } else {
5851 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5852 rep_stos();
5853 }
5854
5855 BIND(DONE);
5856 }
5857
5858 #ifdef COMPILER2
5859
5860 // IndexOf for constant substrings with size >= 8 chars
5861 // which don't need to be loaded through stack.
5862 void MacroAssembler::string_indexofC8(Register str1, Register str2,
5863 Register cnt1, Register cnt2,
5864 int int_cnt2, Register result,
5865 XMMRegister vec, Register tmp,
5866 int ae) {
5867 ShortBranchVerifier sbv(this);
5868 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
5869 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
5870
5871 // This method uses the pcmpestri instruction with bound registers
5872 // inputs:
5873 // xmm - substring
5874 // rax - substring length (elements count)
5875 // mem - scanned string
5876 // rdx - string length (elements count)
5877 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
5878 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
5879 // outputs:
5880 // rcx - matched index in string
5881 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
5882 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
5883 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
5884 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
5885 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
5886
5887 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
5888 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
5889 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
5890
5891 // Note, inline_string_indexOf() generates checks:
5892 // if (substr.count > string.count) return -1;
5893 // if (substr.count == 0) return 0;
5894 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
5895
5896 // Load substring.
5897 if (ae == StrIntrinsicNode::UL) {
5898 pmovzxbw(vec, Address(str2, 0));
5899 } else {
5900 movdqu(vec, Address(str2, 0));
5901 }
5902 movl(cnt2, int_cnt2);
5903 movptr(result, str1); // string addr
5904
5905 if (int_cnt2 > stride) {
5906 jmpb(SCAN_TO_SUBSTR);
5907
5908 // Reload substr for rescan, this code
5909 // is executed only for large substrings (> 8 chars)
5910 bind(RELOAD_SUBSTR);
5911 if (ae == StrIntrinsicNode::UL) {
5912 pmovzxbw(vec, Address(str2, 0));
5913 } else {
5914 movdqu(vec, Address(str2, 0));
5915 }
5916 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
5917
5918 bind(RELOAD_STR);
5919 // We came here after the beginning of the substring was
5920 // matched but the rest of it was not so we need to search
5921 // again. Start from the next element after the previous match.
5922
5923 // cnt2 is number of substring reminding elements and
5924 // cnt1 is number of string reminding elements when cmp failed.
5925 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
5926 subl(cnt1, cnt2);
5927 addl(cnt1, int_cnt2);
5928 movl(cnt2, int_cnt2); // Now restore cnt2
5929
5930 decrementl(cnt1); // Shift to next element
5931 cmpl(cnt1, cnt2);
5932 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
5933
5934 addptr(result, (1<<scale1));
5935
5936 } // (int_cnt2 > 8)
5937
5938 // Scan string for start of substr in 16-byte vectors
5939 bind(SCAN_TO_SUBSTR);
5940 pcmpestri(vec, Address(result, 0), mode);
5941 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
5942 subl(cnt1, stride);
5943 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
5944 cmpl(cnt1, cnt2);
5945 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
5946 addptr(result, 16);
5947 jmpb(SCAN_TO_SUBSTR);
5948
5949 // Found a potential substr
5950 bind(FOUND_CANDIDATE);
5951 // Matched whole vector if first element matched (tmp(rcx) == 0).
5952 if (int_cnt2 == stride) {
5953 jccb(Assembler::overflow, RET_FOUND); // OF == 1
5954 } else { // int_cnt2 > 8
5955 jccb(Assembler::overflow, FOUND_SUBSTR);
5956 }
5957 // After pcmpestri tmp(rcx) contains matched element index
5958 // Compute start addr of substr
5959 lea(result, Address(result, tmp, scale1));
5960
5961 // Make sure string is still long enough
5962 subl(cnt1, tmp);
5963 cmpl(cnt1, cnt2);
5964 if (int_cnt2 == stride) {
5965 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
5966 } else { // int_cnt2 > 8
5967 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
5968 }
5969 // Left less then substring.
5970
5971 bind(RET_NOT_FOUND);
5972 movl(result, -1);
5973 jmp(EXIT);
5974
5975 if (int_cnt2 > stride) {
5976 // This code is optimized for the case when whole substring
5977 // is matched if its head is matched.
5978 bind(MATCH_SUBSTR_HEAD);
5979 pcmpestri(vec, Address(result, 0), mode);
5980 // Reload only string if does not match
5981 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
5982
5983 Label CONT_SCAN_SUBSTR;
5984 // Compare the rest of substring (> 8 chars).
5985 bind(FOUND_SUBSTR);
5986 // First 8 chars are already matched.
5987 negptr(cnt2);
5988 addptr(cnt2, stride);
5989
5990 bind(SCAN_SUBSTR);
5991 subl(cnt1, stride);
5992 cmpl(cnt2, -stride); // Do not read beyond substring
5993 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
5994 // Back-up strings to avoid reading beyond substring:
5995 // cnt1 = cnt1 - cnt2 + 8
5996 addl(cnt1, cnt2); // cnt2 is negative
5997 addl(cnt1, stride);
5998 movl(cnt2, stride); negptr(cnt2);
5999 bind(CONT_SCAN_SUBSTR);
6000 if (int_cnt2 < (int)G) {
6001 int tail_off1 = int_cnt2<<scale1;
6002 int tail_off2 = int_cnt2<<scale2;
6003 if (ae == StrIntrinsicNode::UL) {
6004 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
6005 } else {
6006 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
6007 }
6008 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
6009 } else {
6010 // calculate index in register to avoid integer overflow (int_cnt2*2)
6011 movl(tmp, int_cnt2);
6012 addptr(tmp, cnt2);
6013 if (ae == StrIntrinsicNode::UL) {
6014 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
6015 } else {
6016 movdqu(vec, Address(str2, tmp, scale2, 0));
6017 }
6018 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
6019 }
6020 // Need to reload strings pointers if not matched whole vector
6021 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6022 addptr(cnt2, stride);
6023 jcc(Assembler::negative, SCAN_SUBSTR);
6024 // Fall through if found full substring
6025
6026 } // (int_cnt2 > 8)
6027
6028 bind(RET_FOUND);
6029 // Found result if we matched full small substring.
6030 // Compute substr offset
6031 subptr(result, str1);
6032 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6033 shrl(result, 1); // index
6034 }
6035 bind(EXIT);
6036
6037 } // string_indexofC8
6038
6039 // Small strings are loaded through stack if they cross page boundary.
6040 void MacroAssembler::string_indexof(Register str1, Register str2,
6041 Register cnt1, Register cnt2,
6042 int int_cnt2, Register result,
6043 XMMRegister vec, Register tmp,
6044 int ae) {
6045 ShortBranchVerifier sbv(this);
6046 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6047 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
6048
6049 //
6050 // int_cnt2 is length of small (< 8 chars) constant substring
6051 // or (-1) for non constant substring in which case its length
6052 // is in cnt2 register.
6053 //
6054 // Note, inline_string_indexOf() generates checks:
6055 // if (substr.count > string.count) return -1;
6056 // if (substr.count == 0) return 0;
6057 //
6058 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
6059 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
6060 // This method uses the pcmpestri instruction with bound registers
6061 // inputs:
6062 // xmm - substring
6063 // rax - substring length (elements count)
6064 // mem - scanned string
6065 // rdx - string length (elements count)
6066 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6067 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
6068 // outputs:
6069 // rcx - matched index in string
6070 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6071 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
6072 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
6073 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
6074
6075 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6076 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6077 FOUND_CANDIDATE;
6078
6079 { //========================================================
6080 // We don't know where these strings are located
6081 // and we can't read beyond them. Load them through stack.
6082 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6083
6084 movptr(tmp, rsp); // save old SP
6085
6086 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6087 if (int_cnt2 == (1>>scale2)) { // One byte
6088 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
6089 load_unsigned_byte(result, Address(str2, 0));
6090 movdl(vec, result); // move 32 bits
6091 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
6092 // Not enough header space in 32-bit VM: 12+3 = 15.
6093 movl(result, Address(str2, -1));
6094 shrl(result, 8);
6095 movdl(vec, result); // move 32 bits
6096 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
6097 load_unsigned_short(result, Address(str2, 0));
6098 movdl(vec, result); // move 32 bits
6099 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
6100 movdl(vec, Address(str2, 0)); // move 32 bits
6101 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
6102 movq(vec, Address(str2, 0)); // move 64 bits
6103 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
6104 // Array header size is 12 bytes in 32-bit VM
6105 // + 6 bytes for 3 chars == 18 bytes,
6106 // enough space to load vec and shift.
6107 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6108 if (ae == StrIntrinsicNode::UL) {
6109 int tail_off = int_cnt2-8;
6110 pmovzxbw(vec, Address(str2, tail_off));
6111 psrldq(vec, -2*tail_off);
6112 }
6113 else {
6114 int tail_off = int_cnt2*(1<<scale2);
6115 movdqu(vec, Address(str2, tail_off-16));
6116 psrldq(vec, 16-tail_off);
6117 }
6118 }
6119 } else { // not constant substring
6120 cmpl(cnt2, stride);
6121 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6122
6123 // We can read beyond string if srt+16 does not cross page boundary
6124 // since heaps are aligned and mapped by pages.
6125 assert(os::vm_page_size() < (int)G, "default page should be small");
6126 movl(result, str2); // We need only low 32 bits
6127 andl(result, (os::vm_page_size()-1));
6128 cmpl(result, (os::vm_page_size()-16));
6129 jccb(Assembler::belowEqual, CHECK_STR);
6130
6131 // Move small strings to stack to allow load 16 bytes into vec.
6132 subptr(rsp, 16);
6133 int stk_offset = wordSize-(1<<scale2);
6134 push(cnt2);
6135
6136 bind(COPY_SUBSTR);
6137 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
6138 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
6139 movb(Address(rsp, cnt2, scale2, stk_offset), result);
6140 } else if (ae == StrIntrinsicNode::UU) {
6141 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
6142 movw(Address(rsp, cnt2, scale2, stk_offset), result);
6143 }
6144 decrement(cnt2);
6145 jccb(Assembler::notZero, COPY_SUBSTR);
6146
6147 pop(cnt2);
6148 movptr(str2, rsp); // New substring address
6149 } // non constant
6150
6151 bind(CHECK_STR);
6152 cmpl(cnt1, stride);
6153 jccb(Assembler::aboveEqual, BIG_STRINGS);
6154
6155 // Check cross page boundary.
6156 movl(result, str1); // We need only low 32 bits
6157 andl(result, (os::vm_page_size()-1));
6158 cmpl(result, (os::vm_page_size()-16));
6159 jccb(Assembler::belowEqual, BIG_STRINGS);
6160
6161 subptr(rsp, 16);
6162 int stk_offset = -(1<<scale1);
6163 if (int_cnt2 < 0) { // not constant
6164 push(cnt2);
6165 stk_offset += wordSize;
6166 }
6167 movl(cnt2, cnt1);
6168
6169 bind(COPY_STR);
6170 if (ae == StrIntrinsicNode::LL) {
6171 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
6172 movb(Address(rsp, cnt2, scale1, stk_offset), result);
6173 } else {
6174 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
6175 movw(Address(rsp, cnt2, scale1, stk_offset), result);
6176 }
6177 decrement(cnt2);
6178 jccb(Assembler::notZero, COPY_STR);
6179
6180 if (int_cnt2 < 0) { // not constant
6181 pop(cnt2);
6182 }
6183 movptr(str1, rsp); // New string address
6184
6185 bind(BIG_STRINGS);
6186 // Load substring.
6187 if (int_cnt2 < 0) { // -1
6188 if (ae == StrIntrinsicNode::UL) {
6189 pmovzxbw(vec, Address(str2, 0));
6190 } else {
6191 movdqu(vec, Address(str2, 0));
6192 }
6193 push(cnt2); // substr count
6194 push(str2); // substr addr
6195 push(str1); // string addr
6196 } else {
6197 // Small (< 8 chars) constant substrings are loaded already.
6198 movl(cnt2, int_cnt2);
6199 }
6200 push(tmp); // original SP
6201
6202 } // Finished loading
6203
6204 //========================================================
6205 // Start search
6206 //
6207
6208 movptr(result, str1); // string addr
6209
6210 if (int_cnt2 < 0) { // Only for non constant substring
6211 jmpb(SCAN_TO_SUBSTR);
6212
6213 // SP saved at sp+0
6214 // String saved at sp+1*wordSize
6215 // Substr saved at sp+2*wordSize
6216 // Substr count saved at sp+3*wordSize
6217
6218 // Reload substr for rescan, this code
6219 // is executed only for large substrings (> 8 chars)
6220 bind(RELOAD_SUBSTR);
6221 movptr(str2, Address(rsp, 2*wordSize));
6222 movl(cnt2, Address(rsp, 3*wordSize));
6223 if (ae == StrIntrinsicNode::UL) {
6224 pmovzxbw(vec, Address(str2, 0));
6225 } else {
6226 movdqu(vec, Address(str2, 0));
6227 }
6228 // We came here after the beginning of the substring was
6229 // matched but the rest of it was not so we need to search
6230 // again. Start from the next element after the previous match.
6231 subptr(str1, result); // Restore counter
6232 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6233 shrl(str1, 1);
6234 }
6235 addl(cnt1, str1);
6236 decrementl(cnt1); // Shift to next element
6237 cmpl(cnt1, cnt2);
6238 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6239
6240 addptr(result, (1<<scale1));
6241 } // non constant
6242
6243 // Scan string for start of substr in 16-byte vectors
6244 bind(SCAN_TO_SUBSTR);
6245 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6246 pcmpestri(vec, Address(result, 0), mode);
6247 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6248 subl(cnt1, stride);
6249 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6250 cmpl(cnt1, cnt2);
6251 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6252 addptr(result, 16);
6253
6254 bind(ADJUST_STR);
6255 cmpl(cnt1, stride); // Do not read beyond string
6256 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6257 // Back-up string to avoid reading beyond string.
6258 lea(result, Address(result, cnt1, scale1, -16));
6259 movl(cnt1, stride);
6260 jmpb(SCAN_TO_SUBSTR);
6261
6262 // Found a potential substr
6263 bind(FOUND_CANDIDATE);
6264 // After pcmpestri tmp(rcx) contains matched element index
6265
6266 // Make sure string is still long enough
6267 subl(cnt1, tmp);
6268 cmpl(cnt1, cnt2);
6269 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6270 // Left less then substring.
6271
6272 bind(RET_NOT_FOUND);
6273 movl(result, -1);
6274 jmp(CLEANUP);
6275
6276 bind(FOUND_SUBSTR);
6277 // Compute start addr of substr
6278 lea(result, Address(result, tmp, scale1));
6279 if (int_cnt2 > 0) { // Constant substring
6280 // Repeat search for small substring (< 8 chars)
6281 // from new point without reloading substring.
6282 // Have to check that we don't read beyond string.
6283 cmpl(tmp, stride-int_cnt2);
6284 jccb(Assembler::greater, ADJUST_STR);
6285 // Fall through if matched whole substring.
6286 } else { // non constant
6287 assert(int_cnt2 == -1, "should be != 0");
6288
6289 addl(tmp, cnt2);
6290 // Found result if we matched whole substring.
6291 cmpl(tmp, stride);
6292 jcc(Assembler::lessEqual, RET_FOUND);
6293
6294 // Repeat search for small substring (<= 8 chars)
6295 // from new point 'str1' without reloading substring.
6296 cmpl(cnt2, stride);
6297 // Have to check that we don't read beyond string.
6298 jccb(Assembler::lessEqual, ADJUST_STR);
6299
6300 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6301 // Compare the rest of substring (> 8 chars).
6302 movptr(str1, result);
6303
6304 cmpl(tmp, cnt2);
6305 // First 8 chars are already matched.
6306 jccb(Assembler::equal, CHECK_NEXT);
6307
6308 bind(SCAN_SUBSTR);
6309 pcmpestri(vec, Address(str1, 0), mode);
6310 // Need to reload strings pointers if not matched whole vector
6311 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6312
6313 bind(CHECK_NEXT);
6314 subl(cnt2, stride);
6315 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6316 addptr(str1, 16);
6317 if (ae == StrIntrinsicNode::UL) {
6318 addptr(str2, 8);
6319 } else {
6320 addptr(str2, 16);
6321 }
6322 subl(cnt1, stride);
6323 cmpl(cnt2, stride); // Do not read beyond substring
6324 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6325 // Back-up strings to avoid reading beyond substring.
6326
6327 if (ae == StrIntrinsicNode::UL) {
6328 lea(str2, Address(str2, cnt2, scale2, -8));
6329 lea(str1, Address(str1, cnt2, scale1, -16));
6330 } else {
6331 lea(str2, Address(str2, cnt2, scale2, -16));
6332 lea(str1, Address(str1, cnt2, scale1, -16));
6333 }
6334 subl(cnt1, cnt2);
6335 movl(cnt2, stride);
6336 addl(cnt1, stride);
6337 bind(CONT_SCAN_SUBSTR);
6338 if (ae == StrIntrinsicNode::UL) {
6339 pmovzxbw(vec, Address(str2, 0));
6340 } else {
6341 movdqu(vec, Address(str2, 0));
6342 }
6343 jmp(SCAN_SUBSTR);
6344
6345 bind(RET_FOUND_LONG);
6346 movptr(str1, Address(rsp, wordSize));
6347 } // non constant
6348
6349 bind(RET_FOUND);
6350 // Compute substr offset
6351 subptr(result, str1);
6352 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6353 shrl(result, 1); // index
6354 }
6355 bind(CLEANUP);
6356 pop(rsp); // restore SP
6357
6358 } // string_indexof
6359
6360 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
6361 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
6362 ShortBranchVerifier sbv(this);
6363 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6364
6365 int stride = 8;
6366
6367 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
6368 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
6369 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
6370 FOUND_SEQ_CHAR, DONE_LABEL;
6371
6372 movptr(result, str1);
6373 if (UseAVX >= 2) {
6374 cmpl(cnt1, stride);
6375 jcc(Assembler::less, SCAN_TO_CHAR);
6376 cmpl(cnt1, 2*stride);
6377 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
6378 movdl(vec1, ch);
6379 vpbroadcastw(vec1, vec1, Assembler::AVX_256bit);
6380 vpxor(vec2, vec2);
6381 movl(tmp, cnt1);
6382 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
6383 andl(cnt1,0x0000000F); //tail count (in chars)
6384
6385 bind(SCAN_TO_16_CHAR_LOOP);
6386 vmovdqu(vec3, Address(result, 0));
6387 vpcmpeqw(vec3, vec3, vec1, 1);
6388 vptest(vec2, vec3);
6389 jcc(Assembler::carryClear, FOUND_CHAR);
6390 addptr(result, 32);
6391 subl(tmp, 2*stride);
6392 jcc(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
6393 jmp(SCAN_TO_8_CHAR);
6394 bind(SCAN_TO_8_CHAR_INIT);
6395 movdl(vec1, ch);
6396 pshuflw(vec1, vec1, 0x00);
6397 pshufd(vec1, vec1, 0);
6398 pxor(vec2, vec2);
6399 }
6400 bind(SCAN_TO_8_CHAR);
6401 cmpl(cnt1, stride);
6402 jcc(Assembler::less, SCAN_TO_CHAR);
6403 if (UseAVX < 2) {
6404 movdl(vec1, ch);
6405 pshuflw(vec1, vec1, 0x00);
6406 pshufd(vec1, vec1, 0);
6407 pxor(vec2, vec2);
6408 }
6409 movl(tmp, cnt1);
6410 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
6411 andl(cnt1,0x00000007); //tail count (in chars)
6412
6413 bind(SCAN_TO_8_CHAR_LOOP);
6414 movdqu(vec3, Address(result, 0));
6415 pcmpeqw(vec3, vec1);
6416 ptest(vec2, vec3);
6417 jcc(Assembler::carryClear, FOUND_CHAR);
6418 addptr(result, 16);
6419 subl(tmp, stride);
6420 jcc(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
6421 bind(SCAN_TO_CHAR);
6422 testl(cnt1, cnt1);
6423 jcc(Assembler::zero, RET_NOT_FOUND);
6424 bind(SCAN_TO_CHAR_LOOP);
6425 load_unsigned_short(tmp, Address(result, 0));
6426 cmpl(ch, tmp);
6427 jccb(Assembler::equal, FOUND_SEQ_CHAR);
6428 addptr(result, 2);
6429 subl(cnt1, 1);
6430 jccb(Assembler::zero, RET_NOT_FOUND);
6431 jmp(SCAN_TO_CHAR_LOOP);
6432
6433 bind(RET_NOT_FOUND);
6434 movl(result, -1);
6435 jmpb(DONE_LABEL);
6436
6437 bind(FOUND_CHAR);
6438 if (UseAVX >= 2) {
6439 vpmovmskb(tmp, vec3);
6440 } else {
6441 pmovmskb(tmp, vec3);
6442 }
6443 bsfl(ch, tmp);
6444 addl(result, ch);
6445
6446 bind(FOUND_SEQ_CHAR);
6447 subptr(result, str1);
6448 shrl(result, 1);
6449
6450 bind(DONE_LABEL);
6451 } // string_indexof_char
6452
6453 // helper function for string_compare
6454 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
6455 Address::ScaleFactor scale, Address::ScaleFactor scale1,
6456 Address::ScaleFactor scale2, Register index, int ae) {
6457 if (ae == StrIntrinsicNode::LL) {
6458 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
6459 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
6460 } else if (ae == StrIntrinsicNode::UU) {
6461 load_unsigned_short(elem1, Address(str1, index, scale, 0));
6462 load_unsigned_short(elem2, Address(str2, index, scale, 0));
6463 } else {
6464 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
6465 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
6466 }
6467 }
6468
6469 // Compare strings, used for char[] and byte[].
6470 void MacroAssembler::string_compare(Register str1, Register str2,
6471 Register cnt1, Register cnt2, Register result,
6472 XMMRegister vec1, int ae) {
6473 ShortBranchVerifier sbv(this);
6474 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6475 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
6476 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
6477 int stride2x2 = 0x40;
6478 Address::ScaleFactor scale = Address::no_scale;
6479 Address::ScaleFactor scale1 = Address::no_scale;
6480 Address::ScaleFactor scale2 = Address::no_scale;
6481
6482 if (ae != StrIntrinsicNode::LL) {
6483 stride2x2 = 0x20;
6484 }
6485
6486 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
6487 shrl(cnt2, 1);
6488 }
6489 // Compute the minimum of the string lengths and the
6490 // difference of the string lengths (stack).
6491 // Do the conditional move stuff
6492 movl(result, cnt1);
6493 subl(cnt1, cnt2);
6494 push(cnt1);
6495 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
6496
6497 // Is the minimum length zero?
6498 testl(cnt2, cnt2);
6499 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6500 if (ae == StrIntrinsicNode::LL) {
6501 // Load first bytes
6502 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
6503 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
6504 } else if (ae == StrIntrinsicNode::UU) {
6505 // Load first characters
6506 load_unsigned_short(result, Address(str1, 0));
6507 load_unsigned_short(cnt1, Address(str2, 0));
6508 } else {
6509 load_unsigned_byte(result, Address(str1, 0));
6510 load_unsigned_short(cnt1, Address(str2, 0));
6511 }
6512 subl(result, cnt1);
6513 jcc(Assembler::notZero, POP_LABEL);
6514
6515 if (ae == StrIntrinsicNode::UU) {
6516 // Divide length by 2 to get number of chars
6517 shrl(cnt2, 1);
6518 }
6519 cmpl(cnt2, 1);
6520 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6521
6522 // Check if the strings start at the same location and setup scale and stride
6523 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6524 cmpptr(str1, str2);
6525 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6526 if (ae == StrIntrinsicNode::LL) {
6527 scale = Address::times_1;
6528 stride = 16;
6529 } else {
6530 scale = Address::times_2;
6531 stride = 8;
6532 }
6533 } else {
6534 scale1 = Address::times_1;
6535 scale2 = Address::times_2;
6536 // scale not used
6537 stride = 8;
6538 }
6539
6540 if (UseAVX >= 2 && UseSSE42Intrinsics) {
6541 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6542 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6543 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
6544 Label COMPARE_TAIL_LONG;
6545 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
6546
6547 int pcmpmask = 0x19;
6548 if (ae == StrIntrinsicNode::LL) {
6549 pcmpmask &= ~0x01;
6550 }
6551
6552 // Setup to compare 16-chars (32-bytes) vectors,
6553 // start from first character again because it has aligned address.
6554 if (ae == StrIntrinsicNode::LL) {
6555 stride2 = 32;
6556 } else {
6557 stride2 = 16;
6558 }
6559 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6560 adr_stride = stride << scale;
6561 } else {
6562 adr_stride1 = 8; //stride << scale1;
6563 adr_stride2 = 16; //stride << scale2;
6564 }
6565
6566 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6567 // rax and rdx are used by pcmpestri as elements counters
6568 movl(result, cnt2);
6569 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
6570 jcc(Assembler::zero, COMPARE_TAIL_LONG);
6571
6572 // fast path : compare first 2 8-char vectors.
6573 bind(COMPARE_16_CHARS);
6574 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6575 movdqu(vec1, Address(str1, 0));
6576 } else {
6577 pmovzxbw(vec1, Address(str1, 0));
6578 }
6579 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6580 jccb(Assembler::below, COMPARE_INDEX_CHAR);
6581
6582 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6583 movdqu(vec1, Address(str1, adr_stride));
6584 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6585 } else {
6586 pmovzxbw(vec1, Address(str1, adr_stride1));
6587 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
6588 }
6589 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6590 addl(cnt1, stride);
6591
6592 // Compare the characters at index in cnt1
6593 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
6594 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
6595 subl(result, cnt2);
6596 jmp(POP_LABEL);
6597
6598 // Setup the registers to start vector comparison loop
6599 bind(COMPARE_WIDE_VECTORS);
6600 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6601 lea(str1, Address(str1, result, scale));
6602 lea(str2, Address(str2, result, scale));
6603 } else {
6604 lea(str1, Address(str1, result, scale1));
6605 lea(str2, Address(str2, result, scale2));
6606 }
6607 subl(result, stride2);
6608 subl(cnt2, stride2);
6609 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
6610 negptr(result);
6611
6612 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6613 bind(COMPARE_WIDE_VECTORS_LOOP);
6614
6615 #ifdef _LP64
6616 if ((AVX3Threshold == 0) && VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
6617 cmpl(cnt2, stride2x2);
6618 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
6619 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
6620 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
6621
6622 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
6623 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6624 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
6625 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
6626 } else {
6627 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
6628 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
6629 }
6630 kortestql(k7, k7);
6631 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
6632 addptr(result, stride2x2); // update since we already compared at this addr
6633 subl(cnt2, stride2x2); // and sub the size too
6634 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
6635
6636 vpxor(vec1, vec1);
6637 jmpb(COMPARE_WIDE_TAIL);
6638 }//if (VM_Version::supports_avx512vlbw())
6639 #endif // _LP64
6640
6641
6642 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6643 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6644 vmovdqu(vec1, Address(str1, result, scale));
6645 vpxor(vec1, Address(str2, result, scale));
6646 } else {
6647 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
6648 vpxor(vec1, Address(str2, result, scale2));
6649 }
6650 vptest(vec1, vec1);
6651 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
6652 addptr(result, stride2);
6653 subl(cnt2, stride2);
6654 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6655 // clean upper bits of YMM registers
6656 vpxor(vec1, vec1);
6657
6658 // compare wide vectors tail
6659 bind(COMPARE_WIDE_TAIL);
6660 testptr(result, result);
6661 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6662
6663 movl(result, stride2);
6664 movl(cnt2, result);
6665 negptr(result);
6666 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6667
6668 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6669 bind(VECTOR_NOT_EQUAL);
6670 // clean upper bits of YMM registers
6671 vpxor(vec1, vec1);
6672 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6673 lea(str1, Address(str1, result, scale));
6674 lea(str2, Address(str2, result, scale));
6675 } else {
6676 lea(str1, Address(str1, result, scale1));
6677 lea(str2, Address(str2, result, scale2));
6678 }
6679 jmp(COMPARE_16_CHARS);
6680
6681 // Compare tail chars, length between 1 to 15 chars
6682 bind(COMPARE_TAIL_LONG);
6683 movl(cnt2, result);
6684 cmpl(cnt2, stride);
6685 jcc(Assembler::less, COMPARE_SMALL_STR);
6686
6687 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6688 movdqu(vec1, Address(str1, 0));
6689 } else {
6690 pmovzxbw(vec1, Address(str1, 0));
6691 }
6692 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6693 jcc(Assembler::below, COMPARE_INDEX_CHAR);
6694 subptr(cnt2, stride);
6695 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6696 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6697 lea(str1, Address(str1, result, scale));
6698 lea(str2, Address(str2, result, scale));
6699 } else {
6700 lea(str1, Address(str1, result, scale1));
6701 lea(str2, Address(str2, result, scale2));
6702 }
6703 negptr(cnt2);
6704 jmpb(WHILE_HEAD_LABEL);
6705
6706 bind(COMPARE_SMALL_STR);
6707 } else if (UseSSE42Intrinsics) {
6708 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6709 int pcmpmask = 0x19;
6710 // Setup to compare 8-char (16-byte) vectors,
6711 // start from first character again because it has aligned address.
6712 movl(result, cnt2);
6713 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
6714 if (ae == StrIntrinsicNode::LL) {
6715 pcmpmask &= ~0x01;
6716 }
6717 jcc(Assembler::zero, COMPARE_TAIL);
6718 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6719 lea(str1, Address(str1, result, scale));
6720 lea(str2, Address(str2, result, scale));
6721 } else {
6722 lea(str1, Address(str1, result, scale1));
6723 lea(str2, Address(str2, result, scale2));
6724 }
6725 negptr(result);
6726
6727 // pcmpestri
6728 // inputs:
6729 // vec1- substring
6730 // rax - negative string length (elements count)
6731 // mem - scanned string
6732 // rdx - string length (elements count)
6733 // pcmpmask - cmp mode: 11000 (string compare with negated result)
6734 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
6735 // outputs:
6736 // rcx - first mismatched element index
6737 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6738
6739 bind(COMPARE_WIDE_VECTORS);
6740 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6741 movdqu(vec1, Address(str1, result, scale));
6742 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6743 } else {
6744 pmovzxbw(vec1, Address(str1, result, scale1));
6745 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
6746 }
6747 // After pcmpestri cnt1(rcx) contains mismatched element index
6748
6749 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
6750 addptr(result, stride);
6751 subptr(cnt2, stride);
6752 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6753
6754 // compare wide vectors tail
6755 testptr(result, result);
6756 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6757
6758 movl(cnt2, stride);
6759 movl(result, stride);
6760 negptr(result);
6761 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6762 movdqu(vec1, Address(str1, result, scale));
6763 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6764 } else {
6765 pmovzxbw(vec1, Address(str1, result, scale1));
6766 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
6767 }
6768 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6769
6770 // Mismatched characters in the vectors
6771 bind(VECTOR_NOT_EQUAL);
6772 addptr(cnt1, result);
6773 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
6774 subl(result, cnt2);
6775 jmpb(POP_LABEL);
6776
6777 bind(COMPARE_TAIL); // limit is zero
6778 movl(cnt2, result);
6779 // Fallthru to tail compare
6780 }
6781 // Shift str2 and str1 to the end of the arrays, negate min
6782 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6783 lea(str1, Address(str1, cnt2, scale));
6784 lea(str2, Address(str2, cnt2, scale));
6785 } else {
6786 lea(str1, Address(str1, cnt2, scale1));
6787 lea(str2, Address(str2, cnt2, scale2));
6788 }
6789 decrementl(cnt2); // first character was compared already
6790 negptr(cnt2);
6791
6792 // Compare the rest of the elements
6793 bind(WHILE_HEAD_LABEL);
6794 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
6795 subl(result, cnt1);
6796 jccb(Assembler::notZero, POP_LABEL);
6797 increment(cnt2);
6798 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6799
6800 // Strings are equal up to min length. Return the length difference.
6801 bind(LENGTH_DIFF_LABEL);
6802 pop(result);
6803 if (ae == StrIntrinsicNode::UU) {
6804 // Divide diff by 2 to get number of chars
6805 sarl(result, 1);
6806 }
6807 jmpb(DONE_LABEL);
6808
6809 #ifdef _LP64
6810 if (VM_Version::supports_avx512vlbw()) {
6811
6812 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
6813
6814 kmovql(cnt1, k7);
6815 notq(cnt1);
6816 bsfq(cnt2, cnt1);
6817 if (ae != StrIntrinsicNode::LL) {
6818 // Divide diff by 2 to get number of chars
6819 sarl(cnt2, 1);
6820 }
6821 addq(result, cnt2);
6822 if (ae == StrIntrinsicNode::LL) {
6823 load_unsigned_byte(cnt1, Address(str2, result));
6824 load_unsigned_byte(result, Address(str1, result));
6825 } else if (ae == StrIntrinsicNode::UU) {
6826 load_unsigned_short(cnt1, Address(str2, result, scale));
6827 load_unsigned_short(result, Address(str1, result, scale));
6828 } else {
6829 load_unsigned_short(cnt1, Address(str2, result, scale2));
6830 load_unsigned_byte(result, Address(str1, result, scale1));
6831 }
6832 subl(result, cnt1);
6833 jmpb(POP_LABEL);
6834 }//if (VM_Version::supports_avx512vlbw())
6835 #endif // _LP64
6836
6837 // Discard the stored length difference
6838 bind(POP_LABEL);
6839 pop(cnt1);
6840
6841 // That's it
6842 bind(DONE_LABEL);
6843 if(ae == StrIntrinsicNode::UL) {
6844 negl(result);
6845 }
6846
6847 }
6848
6849 // Search for Non-ASCII character (Negative byte value) in a byte array,
6850 // return true if it has any and false otherwise.
6851 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
6852 // @HotSpotIntrinsicCandidate
6853 // private static boolean hasNegatives(byte[] ba, int off, int len) {
6854 // for (int i = off; i < off + len; i++) {
6855 // if (ba[i] < 0) {
6856 // return true;
6857 // }
6858 // }
6859 // return false;
6860 // }
6861 void MacroAssembler::has_negatives(Register ary1, Register len,
6862 Register result, Register tmp1,
6863 XMMRegister vec1, XMMRegister vec2) {
6864 // rsi: byte array
6865 // rcx: len
6866 // rax: result
6867 ShortBranchVerifier sbv(this);
6868 assert_different_registers(ary1, len, result, tmp1);
6869 assert_different_registers(vec1, vec2);
6870 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
6871
6872 // len == 0
6873 testl(len, len);
6874 jcc(Assembler::zero, FALSE_LABEL);
6875
6876 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
6877 VM_Version::supports_avx512vlbw() &&
6878 VM_Version::supports_bmi2()) {
6879
6880 Label test_64_loop, test_tail;
6881 Register tmp3_aliased = len;
6882
6883 movl(tmp1, len);
6884 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
6885
6886 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
6887 andl(len, ~(64 - 1)); // vector count (in chars)
6888 jccb(Assembler::zero, test_tail);
6889
6890 lea(ary1, Address(ary1, len, Address::times_1));
6891 negptr(len);
6892
6893 bind(test_64_loop);
6894 // Check whether our 64 elements of size byte contain negatives
6895 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
6896 kortestql(k2, k2);
6897 jcc(Assembler::notZero, TRUE_LABEL);
6898
6899 addptr(len, 64);
6900 jccb(Assembler::notZero, test_64_loop);
6901
6902
6903 bind(test_tail);
6904 // bail out when there is nothing to be done
6905 testl(tmp1, -1);
6906 jcc(Assembler::zero, FALSE_LABEL);
6907
6908 // ~(~0 << len) applied up to two times (for 32-bit scenario)
6909 #ifdef _LP64
6910 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
6911 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
6912 notq(tmp3_aliased);
6913 kmovql(k3, tmp3_aliased);
6914 #else
6915 Label k_init;
6916 jmp(k_init);
6917
6918 // We could not read 64-bits from a general purpose register thus we move
6919 // data required to compose 64 1's to the instruction stream
6920 // We emit 64 byte wide series of elements from 0..63 which later on would
6921 // be used as a compare targets with tail count contained in tmp1 register.
6922 // Result would be a k register having tmp1 consecutive number or 1
6923 // counting from least significant bit.
6924 address tmp = pc();
6925 emit_int64(0x0706050403020100);
6926 emit_int64(0x0F0E0D0C0B0A0908);
6927 emit_int64(0x1716151413121110);
6928 emit_int64(0x1F1E1D1C1B1A1918);
6929 emit_int64(0x2726252423222120);
6930 emit_int64(0x2F2E2D2C2B2A2928);
6931 emit_int64(0x3736353433323130);
6932 emit_int64(0x3F3E3D3C3B3A3938);
6933
6934 bind(k_init);
6935 lea(len, InternalAddress(tmp));
6936 // create mask to test for negative byte inside a vector
6937 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
6938 evpcmpgtb(k3, vec1, Address(len, 0), Assembler::AVX_512bit);
6939
6940 #endif
6941 evpcmpgtb(k2, k3, vec2, Address(ary1, 0), Assembler::AVX_512bit);
6942 ktestq(k2, k3);
6943 jcc(Assembler::notZero, TRUE_LABEL);
6944
6945 jmp(FALSE_LABEL);
6946 } else {
6947 movl(result, len); // copy
6948
6949 if (UseAVX >= 2 && UseSSE >= 2) {
6950 // With AVX2, use 32-byte vector compare
6951 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6952
6953 // Compare 32-byte vectors
6954 andl(result, 0x0000001f); // tail count (in bytes)
6955 andl(len, 0xffffffe0); // vector count (in bytes)
6956 jccb(Assembler::zero, COMPARE_TAIL);
6957
6958 lea(ary1, Address(ary1, len, Address::times_1));
6959 negptr(len);
6960
6961 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
6962 movdl(vec2, tmp1);
6963 vpbroadcastd(vec2, vec2, Assembler::AVX_256bit);
6964
6965 bind(COMPARE_WIDE_VECTORS);
6966 vmovdqu(vec1, Address(ary1, len, Address::times_1));
6967 vptest(vec1, vec2);
6968 jccb(Assembler::notZero, TRUE_LABEL);
6969 addptr(len, 32);
6970 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6971
6972 testl(result, result);
6973 jccb(Assembler::zero, FALSE_LABEL);
6974
6975 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6976 vptest(vec1, vec2);
6977 jccb(Assembler::notZero, TRUE_LABEL);
6978 jmpb(FALSE_LABEL);
6979
6980 bind(COMPARE_TAIL); // len is zero
6981 movl(len, result);
6982 // Fallthru to tail compare
6983 } else if (UseSSE42Intrinsics) {
6984 // With SSE4.2, use double quad vector compare
6985 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6986
6987 // Compare 16-byte vectors
6988 andl(result, 0x0000000f); // tail count (in bytes)
6989 andl(len, 0xfffffff0); // vector count (in bytes)
6990 jcc(Assembler::zero, COMPARE_TAIL);
6991
6992 lea(ary1, Address(ary1, len, Address::times_1));
6993 negptr(len);
6994
6995 movl(tmp1, 0x80808080);
6996 movdl(vec2, tmp1);
6997 pshufd(vec2, vec2, 0);
6998
6999 bind(COMPARE_WIDE_VECTORS);
7000 movdqu(vec1, Address(ary1, len, Address::times_1));
7001 ptest(vec1, vec2);
7002 jcc(Assembler::notZero, TRUE_LABEL);
7003 addptr(len, 16);
7004 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7005
7006 testl(result, result);
7007 jcc(Assembler::zero, FALSE_LABEL);
7008
7009 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7010 ptest(vec1, vec2);
7011 jccb(Assembler::notZero, TRUE_LABEL);
7012 jmpb(FALSE_LABEL);
7013
7014 bind(COMPARE_TAIL); // len is zero
7015 movl(len, result);
7016 // Fallthru to tail compare
7017 }
7018 }
7019 // Compare 4-byte vectors
7020 andl(len, 0xfffffffc); // vector count (in bytes)
7021 jccb(Assembler::zero, COMPARE_CHAR);
7022
7023 lea(ary1, Address(ary1, len, Address::times_1));
7024 negptr(len);
7025
7026 bind(COMPARE_VECTORS);
7027 movl(tmp1, Address(ary1, len, Address::times_1));
7028 andl(tmp1, 0x80808080);
7029 jccb(Assembler::notZero, TRUE_LABEL);
7030 addptr(len, 4);
7031 jcc(Assembler::notZero, COMPARE_VECTORS);
7032
7033 // Compare trailing char (final 2 bytes), if any
7034 bind(COMPARE_CHAR);
7035 testl(result, 0x2); // tail char
7036 jccb(Assembler::zero, COMPARE_BYTE);
7037 load_unsigned_short(tmp1, Address(ary1, 0));
7038 andl(tmp1, 0x00008080);
7039 jccb(Assembler::notZero, TRUE_LABEL);
7040 subptr(result, 2);
7041 lea(ary1, Address(ary1, 2));
7042
7043 bind(COMPARE_BYTE);
7044 testl(result, 0x1); // tail byte
7045 jccb(Assembler::zero, FALSE_LABEL);
7046 load_unsigned_byte(tmp1, Address(ary1, 0));
7047 andl(tmp1, 0x00000080);
7048 jccb(Assembler::notEqual, TRUE_LABEL);
7049 jmpb(FALSE_LABEL);
7050
7051 bind(TRUE_LABEL);
7052 movl(result, 1); // return true
7053 jmpb(DONE);
7054
7055 bind(FALSE_LABEL);
7056 xorl(result, result); // return false
7057
7058 // That's it
7059 bind(DONE);
7060 if (UseAVX >= 2 && UseSSE >= 2) {
7061 // clean upper bits of YMM registers
7062 vpxor(vec1, vec1);
7063 vpxor(vec2, vec2);
7064 }
7065 }
7066 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
7067 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
7068 Register limit, Register result, Register chr,
7069 XMMRegister vec1, XMMRegister vec2, bool is_char) {
7070 ShortBranchVerifier sbv(this);
7071 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
7072
7073 int length_offset = arrayOopDesc::length_offset_in_bytes();
7074 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
7075
7076 if (is_array_equ) {
7077 // Check the input args
7078 cmpoop(ary1, ary2);
7079 jcc(Assembler::equal, TRUE_LABEL);
7080
7081 // Need additional checks for arrays_equals.
7082 testptr(ary1, ary1);
7083 jcc(Assembler::zero, FALSE_LABEL);
7084 testptr(ary2, ary2);
7085 jcc(Assembler::zero, FALSE_LABEL);
7086
7087 // Check the lengths
7088 movl(limit, Address(ary1, length_offset));
7089 cmpl(limit, Address(ary2, length_offset));
7090 jcc(Assembler::notEqual, FALSE_LABEL);
7091 }
7092
7093 // count == 0
7094 testl(limit, limit);
7095 jcc(Assembler::zero, TRUE_LABEL);
7096
7097 if (is_array_equ) {
7098 // Load array address
7099 lea(ary1, Address(ary1, base_offset));
7100 lea(ary2, Address(ary2, base_offset));
7101 }
7102
7103 if (is_array_equ && is_char) {
7104 // arrays_equals when used for char[].
7105 shll(limit, 1); // byte count != 0
7106 }
7107 movl(result, limit); // copy
7108
7109 if (UseAVX >= 2) {
7110 // With AVX2, use 32-byte vector compare
7111 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7112
7113 // Compare 32-byte vectors
7114 andl(result, 0x0000001f); // tail count (in bytes)
7115 andl(limit, 0xffffffe0); // vector count (in bytes)
7116 jcc(Assembler::zero, COMPARE_TAIL);
7117
7118 lea(ary1, Address(ary1, limit, Address::times_1));
7119 lea(ary2, Address(ary2, limit, Address::times_1));
7120 negptr(limit);
7121
7122 #ifdef _LP64
7123 if ((AVX3Threshold == 0) && VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7124 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
7125
7126 cmpl(limit, -64);
7127 jcc(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7128
7129 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7130
7131 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
7132 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
7133 kortestql(k7, k7);
7134 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
7135 addptr(limit, 64); // update since we already compared at this addr
7136 cmpl(limit, -64);
7137 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7138
7139 // At this point we may still need to compare -limit+result bytes.
7140 // We could execute the next two instruction and just continue via non-wide path:
7141 // cmpl(limit, 0);
7142 // jcc(Assembler::equal, COMPARE_TAIL); // true
7143 // But since we stopped at the points ary{1,2}+limit which are
7144 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
7145 // (|limit| <= 32 and result < 32),
7146 // we may just compare the last 64 bytes.
7147 //
7148 addptr(result, -64); // it is safe, bc we just came from this area
7149 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
7150 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
7151 kortestql(k7, k7);
7152 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
7153
7154 jmp(TRUE_LABEL);
7155
7156 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7157
7158 }//if (VM_Version::supports_avx512vlbw())
7159 #endif //_LP64
7160 bind(COMPARE_WIDE_VECTORS);
7161 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
7162 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
7163 vpxor(vec1, vec2);
7164
7165 vptest(vec1, vec1);
7166 jcc(Assembler::notZero, FALSE_LABEL);
7167 addptr(limit, 32);
7168 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7169
7170 testl(result, result);
7171 jcc(Assembler::zero, TRUE_LABEL);
7172
7173 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
7174 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
7175 vpxor(vec1, vec2);
7176
7177 vptest(vec1, vec1);
7178 jccb(Assembler::notZero, FALSE_LABEL);
7179 jmpb(TRUE_LABEL);
7180
7181 bind(COMPARE_TAIL); // limit is zero
7182 movl(limit, result);
7183 // Fallthru to tail compare
7184 } else if (UseSSE42Intrinsics) {
7185 // With SSE4.2, use double quad vector compare
7186 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7187
7188 // Compare 16-byte vectors
7189 andl(result, 0x0000000f); // tail count (in bytes)
7190 andl(limit, 0xfffffff0); // vector count (in bytes)
7191 jcc(Assembler::zero, COMPARE_TAIL);
7192
7193 lea(ary1, Address(ary1, limit, Address::times_1));
7194 lea(ary2, Address(ary2, limit, Address::times_1));
7195 negptr(limit);
7196
7197 bind(COMPARE_WIDE_VECTORS);
7198 movdqu(vec1, Address(ary1, limit, Address::times_1));
7199 movdqu(vec2, Address(ary2, limit, Address::times_1));
7200 pxor(vec1, vec2);
7201
7202 ptest(vec1, vec1);
7203 jcc(Assembler::notZero, FALSE_LABEL);
7204 addptr(limit, 16);
7205 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7206
7207 testl(result, result);
7208 jcc(Assembler::zero, TRUE_LABEL);
7209
7210 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7211 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
7212 pxor(vec1, vec2);
7213
7214 ptest(vec1, vec1);
7215 jccb(Assembler::notZero, FALSE_LABEL);
7216 jmpb(TRUE_LABEL);
7217
7218 bind(COMPARE_TAIL); // limit is zero
7219 movl(limit, result);
7220 // Fallthru to tail compare
7221 }
7222
7223 // Compare 4-byte vectors
7224 andl(limit, 0xfffffffc); // vector count (in bytes)
7225 jccb(Assembler::zero, COMPARE_CHAR);
7226
7227 lea(ary1, Address(ary1, limit, Address::times_1));
7228 lea(ary2, Address(ary2, limit, Address::times_1));
7229 negptr(limit);
7230
7231 bind(COMPARE_VECTORS);
7232 movl(chr, Address(ary1, limit, Address::times_1));
7233 cmpl(chr, Address(ary2, limit, Address::times_1));
7234 jccb(Assembler::notEqual, FALSE_LABEL);
7235 addptr(limit, 4);
7236 jcc(Assembler::notZero, COMPARE_VECTORS);
7237
7238 // Compare trailing char (final 2 bytes), if any
7239 bind(COMPARE_CHAR);
7240 testl(result, 0x2); // tail char
7241 jccb(Assembler::zero, COMPARE_BYTE);
7242 load_unsigned_short(chr, Address(ary1, 0));
7243 load_unsigned_short(limit, Address(ary2, 0));
7244 cmpl(chr, limit);
7245 jccb(Assembler::notEqual, FALSE_LABEL);
7246
7247 if (is_array_equ && is_char) {
7248 bind(COMPARE_BYTE);
7249 } else {
7250 lea(ary1, Address(ary1, 2));
7251 lea(ary2, Address(ary2, 2));
7252
7253 bind(COMPARE_BYTE);
7254 testl(result, 0x1); // tail byte
7255 jccb(Assembler::zero, TRUE_LABEL);
7256 load_unsigned_byte(chr, Address(ary1, 0));
7257 load_unsigned_byte(limit, Address(ary2, 0));
7258 cmpl(chr, limit);
7259 jccb(Assembler::notEqual, FALSE_LABEL);
7260 }
7261 bind(TRUE_LABEL);
7262 movl(result, 1); // return true
7263 jmpb(DONE);
7264
7265 bind(FALSE_LABEL);
7266 xorl(result, result); // return false
7267
7268 // That's it
7269 bind(DONE);
7270 if (UseAVX >= 2) {
7271 // clean upper bits of YMM registers
7272 vpxor(vec1, vec1);
7273 vpxor(vec2, vec2);
7274 }
7275 }
7276
7277 #endif
7278
7279 void MacroAssembler::generate_fill(BasicType t, bool aligned,
7280 Register to, Register value, Register count,
7281 Register rtmp, XMMRegister xtmp) {
7282 ShortBranchVerifier sbv(this);
7283 assert_different_registers(to, value, count, rtmp);
7284 Label L_exit;
7285 Label L_fill_2_bytes, L_fill_4_bytes;
7286
7287 int shift = -1;
7288 switch (t) {
7289 case T_BYTE:
7290 shift = 2;
7291 break;
7292 case T_SHORT:
7293 shift = 1;
7294 break;
7295 case T_INT:
7296 shift = 0;
7297 break;
7298 default: ShouldNotReachHere();
7299 }
7300
7301 if (t == T_BYTE) {
7302 andl(value, 0xff);
7303 movl(rtmp, value);
7304 shll(rtmp, 8);
7305 orl(value, rtmp);
7306 }
7307 if (t == T_SHORT) {
7308 andl(value, 0xffff);
7309 }
7310 if (t == T_BYTE || t == T_SHORT) {
7311 movl(rtmp, value);
7312 shll(rtmp, 16);
7313 orl(value, rtmp);
7314 }
7315
7316 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7317 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7318 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7319 Label L_skip_align2;
7320 // align source address at 4 bytes address boundary
7321 if (t == T_BYTE) {
7322 Label L_skip_align1;
7323 // One byte misalignment happens only for byte arrays
7324 testptr(to, 1);
7325 jccb(Assembler::zero, L_skip_align1);
7326 movb(Address(to, 0), value);
7327 increment(to);
7328 decrement(count);
7329 BIND(L_skip_align1);
7330 }
7331 // Two bytes misalignment happens only for byte and short (char) arrays
7332 testptr(to, 2);
7333 jccb(Assembler::zero, L_skip_align2);
7334 movw(Address(to, 0), value);
7335 addptr(to, 2);
7336 subl(count, 1<<(shift-1));
7337 BIND(L_skip_align2);
7338 }
7339 if (UseSSE < 2) {
7340 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7341 // Fill 32-byte chunks
7342 subl(count, 8 << shift);
7343 jcc(Assembler::less, L_check_fill_8_bytes);
7344 align(16);
7345
7346 BIND(L_fill_32_bytes_loop);
7347
7348 for (int i = 0; i < 32; i += 4) {
7349 movl(Address(to, i), value);
7350 }
7351
7352 addptr(to, 32);
7353 subl(count, 8 << shift);
7354 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7355 BIND(L_check_fill_8_bytes);
7356 addl(count, 8 << shift);
7357 jccb(Assembler::zero, L_exit);
7358 jmpb(L_fill_8_bytes);
7359
7360 //
7361 // length is too short, just fill qwords
7362 //
7363 BIND(L_fill_8_bytes_loop);
7364 movl(Address(to, 0), value);
7365 movl(Address(to, 4), value);
7366 addptr(to, 8);
7367 BIND(L_fill_8_bytes);
7368 subl(count, 1 << (shift + 1));
7369 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7370 // fall through to fill 4 bytes
7371 } else {
7372 Label L_fill_32_bytes;
7373 if (!UseUnalignedLoadStores) {
7374 // align to 8 bytes, we know we are 4 byte aligned to start
7375 testptr(to, 4);
7376 jccb(Assembler::zero, L_fill_32_bytes);
7377 movl(Address(to, 0), value);
7378 addptr(to, 4);
7379 subl(count, 1<<shift);
7380 }
7381 BIND(L_fill_32_bytes);
7382 {
7383 assert( UseSSE >= 2, "supported cpu only" );
7384 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7385 movdl(xtmp, value);
7386 if (UseAVX >= 2 && UseUnalignedLoadStores) {
7387 Label L_check_fill_32_bytes;
7388 if (UseAVX > 2) {
7389 // Fill 64-byte chunks
7390 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
7391
7392 // If number of bytes to fill < AVX3Threshold, perform fill using AVX2
7393 cmpl(count, AVX3Threshold);
7394 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
7395
7396 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
7397
7398 subl(count, 16 << shift);
7399 jccb(Assembler::less, L_check_fill_32_bytes);
7400 align(16);
7401
7402 BIND(L_fill_64_bytes_loop_avx3);
7403 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
7404 addptr(to, 64);
7405 subl(count, 16 << shift);
7406 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
7407 jmpb(L_check_fill_32_bytes);
7408
7409 BIND(L_check_fill_64_bytes_avx2);
7410 }
7411 // Fill 64-byte chunks
7412 Label L_fill_64_bytes_loop;
7413 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
7414
7415 subl(count, 16 << shift);
7416 jcc(Assembler::less, L_check_fill_32_bytes);
7417 align(16);
7418
7419 BIND(L_fill_64_bytes_loop);
7420 vmovdqu(Address(to, 0), xtmp);
7421 vmovdqu(Address(to, 32), xtmp);
7422 addptr(to, 64);
7423 subl(count, 16 << shift);
7424 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7425
7426 BIND(L_check_fill_32_bytes);
7427 addl(count, 8 << shift);
7428 jccb(Assembler::less, L_check_fill_8_bytes);
7429 vmovdqu(Address(to, 0), xtmp);
7430 addptr(to, 32);
7431 subl(count, 8 << shift);
7432
7433 BIND(L_check_fill_8_bytes);
7434 // clean upper bits of YMM registers
7435 movdl(xtmp, value);
7436 pshufd(xtmp, xtmp, 0);
7437 } else {
7438 // Fill 32-byte chunks
7439 pshufd(xtmp, xtmp, 0);
7440
7441 subl(count, 8 << shift);
7442 jcc(Assembler::less, L_check_fill_8_bytes);
7443 align(16);
7444
7445 BIND(L_fill_32_bytes_loop);
7446
7447 if (UseUnalignedLoadStores) {
7448 movdqu(Address(to, 0), xtmp);
7449 movdqu(Address(to, 16), xtmp);
7450 } else {
7451 movq(Address(to, 0), xtmp);
7452 movq(Address(to, 8), xtmp);
7453 movq(Address(to, 16), xtmp);
7454 movq(Address(to, 24), xtmp);
7455 }
7456
7457 addptr(to, 32);
7458 subl(count, 8 << shift);
7459 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7460
7461 BIND(L_check_fill_8_bytes);
7462 }
7463 addl(count, 8 << shift);
7464 jccb(Assembler::zero, L_exit);
7465 jmpb(L_fill_8_bytes);
7466
7467 //
7468 // length is too short, just fill qwords
7469 //
7470 BIND(L_fill_8_bytes_loop);
7471 movq(Address(to, 0), xtmp);
7472 addptr(to, 8);
7473 BIND(L_fill_8_bytes);
7474 subl(count, 1 << (shift + 1));
7475 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7476 }
7477 }
7478 // fill trailing 4 bytes
7479 BIND(L_fill_4_bytes);
7480 testl(count, 1<<shift);
7481 jccb(Assembler::zero, L_fill_2_bytes);
7482 movl(Address(to, 0), value);
7483 if (t == T_BYTE || t == T_SHORT) {
7484 Label L_fill_byte;
7485 addptr(to, 4);
7486 BIND(L_fill_2_bytes);
7487 // fill trailing 2 bytes
7488 testl(count, 1<<(shift-1));
7489 jccb(Assembler::zero, L_fill_byte);
7490 movw(Address(to, 0), value);
7491 if (t == T_BYTE) {
7492 addptr(to, 2);
7493 BIND(L_fill_byte);
7494 // fill trailing byte
7495 testl(count, 1);
7496 jccb(Assembler::zero, L_exit);
7497 movb(Address(to, 0), value);
7498 } else {
7499 BIND(L_fill_byte);
7500 }
7501 } else {
7502 BIND(L_fill_2_bytes);
7503 }
7504 BIND(L_exit);
7505 }
7506
7507 // encode char[] to byte[] in ISO_8859_1
7508 //@HotSpotIntrinsicCandidate
7509 //private static int implEncodeISOArray(byte[] sa, int sp,
7510 //byte[] da, int dp, int len) {
7511 // int i = 0;
7512 // for (; i < len; i++) {
7513 // char c = StringUTF16.getChar(sa, sp++);
7514 // if (c > '\u00FF')
7515 // break;
7516 // da[dp++] = (byte)c;
7517 // }
7518 // return i;
7519 //}
7520 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7521 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7522 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7523 Register tmp5, Register result) {
7524
7525 // rsi: src
7526 // rdi: dst
7527 // rdx: len
7528 // rcx: tmp5
7529 // rax: result
7530 ShortBranchVerifier sbv(this);
7531 assert_different_registers(src, dst, len, tmp5, result);
7532 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7533
7534 // set result
7535 xorl(result, result);
7536 // check for zero length
7537 testl(len, len);
7538 jcc(Assembler::zero, L_done);
7539
7540 movl(result, len);
7541
7542 // Setup pointers
7543 lea(src, Address(src, len, Address::times_2)); // char[]
7544 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7545 negptr(len);
7546
7547 if (UseSSE42Intrinsics || UseAVX >= 2) {
7548 Label L_copy_8_chars, L_copy_8_chars_exit;
7549 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7550
7551 if (UseAVX >= 2) {
7552 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7553 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7554 movdl(tmp1Reg, tmp5);
7555 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7556 jmp(L_chars_32_check);
7557
7558 bind(L_copy_32_chars);
7559 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7560 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7561 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7562 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7563 jccb(Assembler::notZero, L_copy_32_chars_exit);
7564 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7565 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7566 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7567
7568 bind(L_chars_32_check);
7569 addptr(len, 32);
7570 jcc(Assembler::lessEqual, L_copy_32_chars);
7571
7572 bind(L_copy_32_chars_exit);
7573 subptr(len, 16);
7574 jccb(Assembler::greater, L_copy_16_chars_exit);
7575
7576 } else if (UseSSE42Intrinsics) {
7577 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7578 movdl(tmp1Reg, tmp5);
7579 pshufd(tmp1Reg, tmp1Reg, 0);
7580 jmpb(L_chars_16_check);
7581 }
7582
7583 bind(L_copy_16_chars);
7584 if (UseAVX >= 2) {
7585 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7586 vptest(tmp2Reg, tmp1Reg);
7587 jcc(Assembler::notZero, L_copy_16_chars_exit);
7588 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7589 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7590 } else {
7591 if (UseAVX > 0) {
7592 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7593 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7594 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7595 } else {
7596 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7597 por(tmp2Reg, tmp3Reg);
7598 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7599 por(tmp2Reg, tmp4Reg);
7600 }
7601 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7602 jccb(Assembler::notZero, L_copy_16_chars_exit);
7603 packuswb(tmp3Reg, tmp4Reg);
7604 }
7605 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7606
7607 bind(L_chars_16_check);
7608 addptr(len, 16);
7609 jcc(Assembler::lessEqual, L_copy_16_chars);
7610
7611 bind(L_copy_16_chars_exit);
7612 if (UseAVX >= 2) {
7613 // clean upper bits of YMM registers
7614 vpxor(tmp2Reg, tmp2Reg);
7615 vpxor(tmp3Reg, tmp3Reg);
7616 vpxor(tmp4Reg, tmp4Reg);
7617 movdl(tmp1Reg, tmp5);
7618 pshufd(tmp1Reg, tmp1Reg, 0);
7619 }
7620 subptr(len, 8);
7621 jccb(Assembler::greater, L_copy_8_chars_exit);
7622
7623 bind(L_copy_8_chars);
7624 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7625 ptest(tmp3Reg, tmp1Reg);
7626 jccb(Assembler::notZero, L_copy_8_chars_exit);
7627 packuswb(tmp3Reg, tmp1Reg);
7628 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7629 addptr(len, 8);
7630 jccb(Assembler::lessEqual, L_copy_8_chars);
7631
7632 bind(L_copy_8_chars_exit);
7633 subptr(len, 8);
7634 jccb(Assembler::zero, L_done);
7635 }
7636
7637 bind(L_copy_1_char);
7638 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7639 testl(tmp5, 0xff00); // check if Unicode char
7640 jccb(Assembler::notZero, L_copy_1_char_exit);
7641 movb(Address(dst, len, Address::times_1, 0), tmp5);
7642 addptr(len, 1);
7643 jccb(Assembler::less, L_copy_1_char);
7644
7645 bind(L_copy_1_char_exit);
7646 addptr(result, len); // len is negative count of not processed elements
7647
7648 bind(L_done);
7649 }
7650
7651 #ifdef _LP64
7652 /**
7653 * Helper for multiply_to_len().
7654 */
7655 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7656 addq(dest_lo, src1);
7657 adcq(dest_hi, 0);
7658 addq(dest_lo, src2);
7659 adcq(dest_hi, 0);
7660 }
7661
7662 /**
7663 * Multiply 64 bit by 64 bit first loop.
7664 */
7665 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7666 Register y, Register y_idx, Register z,
7667 Register carry, Register product,
7668 Register idx, Register kdx) {
7669 //
7670 // jlong carry, x[], y[], z[];
7671 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7672 // huge_128 product = y[idx] * x[xstart] + carry;
7673 // z[kdx] = (jlong)product;
7674 // carry = (jlong)(product >>> 64);
7675 // }
7676 // z[xstart] = carry;
7677 //
7678
7679 Label L_first_loop, L_first_loop_exit;
7680 Label L_one_x, L_one_y, L_multiply;
7681
7682 decrementl(xstart);
7683 jcc(Assembler::negative, L_one_x);
7684
7685 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7686 rorq(x_xstart, 32); // convert big-endian to little-endian
7687
7688 bind(L_first_loop);
7689 decrementl(idx);
7690 jcc(Assembler::negative, L_first_loop_exit);
7691 decrementl(idx);
7692 jcc(Assembler::negative, L_one_y);
7693 movq(y_idx, Address(y, idx, Address::times_4, 0));
7694 rorq(y_idx, 32); // convert big-endian to little-endian
7695 bind(L_multiply);
7696 movq(product, x_xstart);
7697 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7698 addq(product, carry);
7699 adcq(rdx, 0);
7700 subl(kdx, 2);
7701 movl(Address(z, kdx, Address::times_4, 4), product);
7702 shrq(product, 32);
7703 movl(Address(z, kdx, Address::times_4, 0), product);
7704 movq(carry, rdx);
7705 jmp(L_first_loop);
7706
7707 bind(L_one_y);
7708 movl(y_idx, Address(y, 0));
7709 jmp(L_multiply);
7710
7711 bind(L_one_x);
7712 movl(x_xstart, Address(x, 0));
7713 jmp(L_first_loop);
7714
7715 bind(L_first_loop_exit);
7716 }
7717
7718 /**
7719 * Multiply 64 bit by 64 bit and add 128 bit.
7720 */
7721 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7722 Register yz_idx, Register idx,
7723 Register carry, Register product, int offset) {
7724 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7725 // z[kdx] = (jlong)product;
7726
7727 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7728 rorq(yz_idx, 32); // convert big-endian to little-endian
7729 movq(product, x_xstart);
7730 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7731 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7732 rorq(yz_idx, 32); // convert big-endian to little-endian
7733
7734 add2_with_carry(rdx, product, carry, yz_idx);
7735
7736 movl(Address(z, idx, Address::times_4, offset+4), product);
7737 shrq(product, 32);
7738 movl(Address(z, idx, Address::times_4, offset), product);
7739
7740 }
7741
7742 /**
7743 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7744 */
7745 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7746 Register yz_idx, Register idx, Register jdx,
7747 Register carry, Register product,
7748 Register carry2) {
7749 // jlong carry, x[], y[], z[];
7750 // int kdx = ystart+1;
7751 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7752 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7753 // z[kdx+idx+1] = (jlong)product;
7754 // jlong carry2 = (jlong)(product >>> 64);
7755 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7756 // z[kdx+idx] = (jlong)product;
7757 // carry = (jlong)(product >>> 64);
7758 // }
7759 // idx += 2;
7760 // if (idx > 0) {
7761 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7762 // z[kdx+idx] = (jlong)product;
7763 // carry = (jlong)(product >>> 64);
7764 // }
7765 //
7766
7767 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7768
7769 movl(jdx, idx);
7770 andl(jdx, 0xFFFFFFFC);
7771 shrl(jdx, 2);
7772
7773 bind(L_third_loop);
7774 subl(jdx, 1);
7775 jcc(Assembler::negative, L_third_loop_exit);
7776 subl(idx, 4);
7777
7778 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7779 movq(carry2, rdx);
7780
7781 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7782 movq(carry, rdx);
7783 jmp(L_third_loop);
7784
7785 bind (L_third_loop_exit);
7786
7787 andl (idx, 0x3);
7788 jcc(Assembler::zero, L_post_third_loop_done);
7789
7790 Label L_check_1;
7791 subl(idx, 2);
7792 jcc(Assembler::negative, L_check_1);
7793
7794 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7795 movq(carry, rdx);
7796
7797 bind (L_check_1);
7798 addl (idx, 0x2);
7799 andl (idx, 0x1);
7800 subl(idx, 1);
7801 jcc(Assembler::negative, L_post_third_loop_done);
7802
7803 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7804 movq(product, x_xstart);
7805 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7806 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7807
7808 add2_with_carry(rdx, product, yz_idx, carry);
7809
7810 movl(Address(z, idx, Address::times_4, 0), product);
7811 shrq(product, 32);
7812
7813 shlq(rdx, 32);
7814 orq(product, rdx);
7815 movq(carry, product);
7816
7817 bind(L_post_third_loop_done);
7818 }
7819
7820 /**
7821 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7822 *
7823 */
7824 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7825 Register carry, Register carry2,
7826 Register idx, Register jdx,
7827 Register yz_idx1, Register yz_idx2,
7828 Register tmp, Register tmp3, Register tmp4) {
7829 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7830
7831 // jlong carry, x[], y[], z[];
7832 // int kdx = ystart+1;
7833 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7834 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7835 // jlong carry2 = (jlong)(tmp3 >>> 64);
7836 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7837 // carry = (jlong)(tmp4 >>> 64);
7838 // z[kdx+idx+1] = (jlong)tmp3;
7839 // z[kdx+idx] = (jlong)tmp4;
7840 // }
7841 // idx += 2;
7842 // if (idx > 0) {
7843 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7844 // z[kdx+idx] = (jlong)yz_idx1;
7845 // carry = (jlong)(yz_idx1 >>> 64);
7846 // }
7847 //
7848
7849 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7850
7851 movl(jdx, idx);
7852 andl(jdx, 0xFFFFFFFC);
7853 shrl(jdx, 2);
7854
7855 bind(L_third_loop);
7856 subl(jdx, 1);
7857 jcc(Assembler::negative, L_third_loop_exit);
7858 subl(idx, 4);
7859
7860 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7861 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7862 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7863 rorxq(yz_idx2, yz_idx2, 32);
7864
7865 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7866 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7867
7868 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7869 rorxq(yz_idx1, yz_idx1, 32);
7870 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7871 rorxq(yz_idx2, yz_idx2, 32);
7872
7873 if (VM_Version::supports_adx()) {
7874 adcxq(tmp3, carry);
7875 adoxq(tmp3, yz_idx1);
7876
7877 adcxq(tmp4, tmp);
7878 adoxq(tmp4, yz_idx2);
7879
7880 movl(carry, 0); // does not affect flags
7881 adcxq(carry2, carry);
7882 adoxq(carry2, carry);
7883 } else {
7884 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7885 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7886 }
7887 movq(carry, carry2);
7888
7889 movl(Address(z, idx, Address::times_4, 12), tmp3);
7890 shrq(tmp3, 32);
7891 movl(Address(z, idx, Address::times_4, 8), tmp3);
7892
7893 movl(Address(z, idx, Address::times_4, 4), tmp4);
7894 shrq(tmp4, 32);
7895 movl(Address(z, idx, Address::times_4, 0), tmp4);
7896
7897 jmp(L_third_loop);
7898
7899 bind (L_third_loop_exit);
7900
7901 andl (idx, 0x3);
7902 jcc(Assembler::zero, L_post_third_loop_done);
7903
7904 Label L_check_1;
7905 subl(idx, 2);
7906 jcc(Assembler::negative, L_check_1);
7907
7908 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7909 rorxq(yz_idx1, yz_idx1, 32);
7910 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7911 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7912 rorxq(yz_idx2, yz_idx2, 32);
7913
7914 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7915
7916 movl(Address(z, idx, Address::times_4, 4), tmp3);
7917 shrq(tmp3, 32);
7918 movl(Address(z, idx, Address::times_4, 0), tmp3);
7919 movq(carry, tmp4);
7920
7921 bind (L_check_1);
7922 addl (idx, 0x2);
7923 andl (idx, 0x1);
7924 subl(idx, 1);
7925 jcc(Assembler::negative, L_post_third_loop_done);
7926 movl(tmp4, Address(y, idx, Address::times_4, 0));
7927 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7928 movl(tmp4, Address(z, idx, Address::times_4, 0));
7929
7930 add2_with_carry(carry2, tmp3, tmp4, carry);
7931
7932 movl(Address(z, idx, Address::times_4, 0), tmp3);
7933 shrq(tmp3, 32);
7934
7935 shlq(carry2, 32);
7936 orq(tmp3, carry2);
7937 movq(carry, tmp3);
7938
7939 bind(L_post_third_loop_done);
7940 }
7941
7942 /**
7943 * Code for BigInteger::multiplyToLen() instrinsic.
7944 *
7945 * rdi: x
7946 * rax: xlen
7947 * rsi: y
7948 * rcx: ylen
7949 * r8: z
7950 * r11: zlen
7951 * r12: tmp1
7952 * r13: tmp2
7953 * r14: tmp3
7954 * r15: tmp4
7955 * rbx: tmp5
7956 *
7957 */
7958 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
7959 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7960 ShortBranchVerifier sbv(this);
7961 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7962
7963 push(tmp1);
7964 push(tmp2);
7965 push(tmp3);
7966 push(tmp4);
7967 push(tmp5);
7968
7969 push(xlen);
7970 push(zlen);
7971
7972 const Register idx = tmp1;
7973 const Register kdx = tmp2;
7974 const Register xstart = tmp3;
7975
7976 const Register y_idx = tmp4;
7977 const Register carry = tmp5;
7978 const Register product = xlen;
7979 const Register x_xstart = zlen; // reuse register
7980
7981 // First Loop.
7982 //
7983 // final static long LONG_MASK = 0xffffffffL;
7984 // int xstart = xlen - 1;
7985 // int ystart = ylen - 1;
7986 // long carry = 0;
7987 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7988 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7989 // z[kdx] = (int)product;
7990 // carry = product >>> 32;
7991 // }
7992 // z[xstart] = (int)carry;
7993 //
7994
7995 movl(idx, ylen); // idx = ylen;
7996 movl(kdx, zlen); // kdx = xlen+ylen;
7997 xorq(carry, carry); // carry = 0;
7998
7999 Label L_done;
8000
8001 movl(xstart, xlen);
8002 decrementl(xstart);
8003 jcc(Assembler::negative, L_done);
8004
8005 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
8006
8007 Label L_second_loop;
8008 testl(kdx, kdx);
8009 jcc(Assembler::zero, L_second_loop);
8010
8011 Label L_carry;
8012 subl(kdx, 1);
8013 jcc(Assembler::zero, L_carry);
8014
8015 movl(Address(z, kdx, Address::times_4, 0), carry);
8016 shrq(carry, 32);
8017 subl(kdx, 1);
8018
8019 bind(L_carry);
8020 movl(Address(z, kdx, Address::times_4, 0), carry);
8021
8022 // Second and third (nested) loops.
8023 //
8024 // for (int i = xstart-1; i >= 0; i--) { // Second loop
8025 // carry = 0;
8026 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
8027 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
8028 // (z[k] & LONG_MASK) + carry;
8029 // z[k] = (int)product;
8030 // carry = product >>> 32;
8031 // }
8032 // z[i] = (int)carry;
8033 // }
8034 //
8035 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
8036
8037 const Register jdx = tmp1;
8038
8039 bind(L_second_loop);
8040 xorl(carry, carry); // carry = 0;
8041 movl(jdx, ylen); // j = ystart+1
8042
8043 subl(xstart, 1); // i = xstart-1;
8044 jcc(Assembler::negative, L_done);
8045
8046 push (z);
8047
8048 Label L_last_x;
8049 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
8050 subl(xstart, 1); // i = xstart-1;
8051 jcc(Assembler::negative, L_last_x);
8052
8053 if (UseBMI2Instructions) {
8054 movq(rdx, Address(x, xstart, Address::times_4, 0));
8055 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
8056 } else {
8057 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8058 rorq(x_xstart, 32); // convert big-endian to little-endian
8059 }
8060
8061 Label L_third_loop_prologue;
8062 bind(L_third_loop_prologue);
8063
8064 push (x);
8065 push (xstart);
8066 push (ylen);
8067
8068
8069 if (UseBMI2Instructions) {
8070 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
8071 } else { // !UseBMI2Instructions
8072 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
8073 }
8074
8075 pop(ylen);
8076 pop(xlen);
8077 pop(x);
8078 pop(z);
8079
8080 movl(tmp3, xlen);
8081 addl(tmp3, 1);
8082 movl(Address(z, tmp3, Address::times_4, 0), carry);
8083 subl(tmp3, 1);
8084 jccb(Assembler::negative, L_done);
8085
8086 shrq(carry, 32);
8087 movl(Address(z, tmp3, Address::times_4, 0), carry);
8088 jmp(L_second_loop);
8089
8090 // Next infrequent code is moved outside loops.
8091 bind(L_last_x);
8092 if (UseBMI2Instructions) {
8093 movl(rdx, Address(x, 0));
8094 } else {
8095 movl(x_xstart, Address(x, 0));
8096 }
8097 jmp(L_third_loop_prologue);
8098
8099 bind(L_done);
8100
8101 pop(zlen);
8102 pop(xlen);
8103
8104 pop(tmp5);
8105 pop(tmp4);
8106 pop(tmp3);
8107 pop(tmp2);
8108 pop(tmp1);
8109 }
8110
8111 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
8112 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
8113 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
8114 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
8115 Label VECTOR8_TAIL, VECTOR4_TAIL;
8116 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
8117 Label SAME_TILL_END, DONE;
8118 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
8119
8120 //scale is in rcx in both Win64 and Unix
8121 ShortBranchVerifier sbv(this);
8122
8123 shlq(length);
8124 xorq(result, result);
8125
8126 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
8127 VM_Version::supports_avx512vlbw()) {
8128 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
8129
8130 cmpq(length, 64);
8131 jcc(Assembler::less, VECTOR32_TAIL);
8132
8133 movq(tmp1, length);
8134 andq(tmp1, 0x3F); // tail count
8135 andq(length, ~(0x3F)); //vector count
8136
8137 bind(VECTOR64_LOOP);
8138 // AVX512 code to compare 64 byte vectors.
8139 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
8140 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
8141 kortestql(k7, k7);
8142 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
8143 addq(result, 64);
8144 subq(length, 64);
8145 jccb(Assembler::notZero, VECTOR64_LOOP);
8146
8147 //bind(VECTOR64_TAIL);
8148 testq(tmp1, tmp1);
8149 jcc(Assembler::zero, SAME_TILL_END);
8150
8151 //bind(VECTOR64_TAIL);
8152 // AVX512 code to compare upto 63 byte vectors.
8153 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
8154 shlxq(tmp2, tmp2, tmp1);
8155 notq(tmp2);
8156 kmovql(k3, tmp2);
8157
8158 evmovdqub(rymm0, k3, Address(obja, result), Assembler::AVX_512bit);
8159 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
8160
8161 ktestql(k7, k3);
8162 jcc(Assembler::below, SAME_TILL_END); // not mismatch
8163
8164 bind(VECTOR64_NOT_EQUAL);
8165 kmovql(tmp1, k7);
8166 notq(tmp1);
8167 tzcntq(tmp1, tmp1);
8168 addq(result, tmp1);
8169 shrq(result);
8170 jmp(DONE);
8171 bind(VECTOR32_TAIL);
8172 }
8173
8174 cmpq(length, 8);
8175 jcc(Assembler::equal, VECTOR8_LOOP);
8176 jcc(Assembler::less, VECTOR4_TAIL);
8177
8178 if (UseAVX >= 2) {
8179 Label VECTOR16_TAIL, VECTOR32_LOOP;
8180
8181 cmpq(length, 16);
8182 jcc(Assembler::equal, VECTOR16_LOOP);
8183 jcc(Assembler::less, VECTOR8_LOOP);
8184
8185 cmpq(length, 32);
8186 jccb(Assembler::less, VECTOR16_TAIL);
8187
8188 subq(length, 32);
8189 bind(VECTOR32_LOOP);
8190 vmovdqu(rymm0, Address(obja, result));
8191 vmovdqu(rymm1, Address(objb, result));
8192 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
8193 vptest(rymm2, rymm2);
8194 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
8195 addq(result, 32);
8196 subq(length, 32);
8197 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
8198 addq(length, 32);
8199 jcc(Assembler::equal, SAME_TILL_END);
8200 //falling through if less than 32 bytes left //close the branch here.
8201
8202 bind(VECTOR16_TAIL);
8203 cmpq(length, 16);
8204 jccb(Assembler::less, VECTOR8_TAIL);
8205 bind(VECTOR16_LOOP);
8206 movdqu(rymm0, Address(obja, result));
8207 movdqu(rymm1, Address(objb, result));
8208 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
8209 ptest(rymm2, rymm2);
8210 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8211 addq(result, 16);
8212 subq(length, 16);
8213 jcc(Assembler::equal, SAME_TILL_END);
8214 //falling through if less than 16 bytes left
8215 } else {//regular intrinsics
8216
8217 cmpq(length, 16);
8218 jccb(Assembler::less, VECTOR8_TAIL);
8219
8220 subq(length, 16);
8221 bind(VECTOR16_LOOP);
8222 movdqu(rymm0, Address(obja, result));
8223 movdqu(rymm1, Address(objb, result));
8224 pxor(rymm0, rymm1);
8225 ptest(rymm0, rymm0);
8226 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8227 addq(result, 16);
8228 subq(length, 16);
8229 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
8230 addq(length, 16);
8231 jcc(Assembler::equal, SAME_TILL_END);
8232 //falling through if less than 16 bytes left
8233 }
8234
8235 bind(VECTOR8_TAIL);
8236 cmpq(length, 8);
8237 jccb(Assembler::less, VECTOR4_TAIL);
8238 bind(VECTOR8_LOOP);
8239 movq(tmp1, Address(obja, result));
8240 movq(tmp2, Address(objb, result));
8241 xorq(tmp1, tmp2);
8242 testq(tmp1, tmp1);
8243 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
8244 addq(result, 8);
8245 subq(length, 8);
8246 jcc(Assembler::equal, SAME_TILL_END);
8247 //falling through if less than 8 bytes left
8248
8249 bind(VECTOR4_TAIL);
8250 cmpq(length, 4);
8251 jccb(Assembler::less, BYTES_TAIL);
8252 bind(VECTOR4_LOOP);
8253 movl(tmp1, Address(obja, result));
8254 xorl(tmp1, Address(objb, result));
8255 testl(tmp1, tmp1);
8256 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
8257 addq(result, 4);
8258 subq(length, 4);
8259 jcc(Assembler::equal, SAME_TILL_END);
8260 //falling through if less than 4 bytes left
8261
8262 bind(BYTES_TAIL);
8263 bind(BYTES_LOOP);
8264 load_unsigned_byte(tmp1, Address(obja, result));
8265 load_unsigned_byte(tmp2, Address(objb, result));
8266 xorl(tmp1, tmp2);
8267 testl(tmp1, tmp1);
8268 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8269 decq(length);
8270 jcc(Assembler::zero, SAME_TILL_END);
8271 incq(result);
8272 load_unsigned_byte(tmp1, Address(obja, result));
8273 load_unsigned_byte(tmp2, Address(objb, result));
8274 xorl(tmp1, tmp2);
8275 testl(tmp1, tmp1);
8276 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8277 decq(length);
8278 jcc(Assembler::zero, SAME_TILL_END);
8279 incq(result);
8280 load_unsigned_byte(tmp1, Address(obja, result));
8281 load_unsigned_byte(tmp2, Address(objb, result));
8282 xorl(tmp1, tmp2);
8283 testl(tmp1, tmp1);
8284 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8285 jmp(SAME_TILL_END);
8286
8287 if (UseAVX >= 2) {
8288 bind(VECTOR32_NOT_EQUAL);
8289 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
8290 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
8291 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
8292 vpmovmskb(tmp1, rymm0);
8293 bsfq(tmp1, tmp1);
8294 addq(result, tmp1);
8295 shrq(result);
8296 jmp(DONE);
8297 }
8298
8299 bind(VECTOR16_NOT_EQUAL);
8300 if (UseAVX >= 2) {
8301 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
8302 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
8303 pxor(rymm0, rymm2);
8304 } else {
8305 pcmpeqb(rymm2, rymm2);
8306 pxor(rymm0, rymm1);
8307 pcmpeqb(rymm0, rymm1);
8308 pxor(rymm0, rymm2);
8309 }
8310 pmovmskb(tmp1, rymm0);
8311 bsfq(tmp1, tmp1);
8312 addq(result, tmp1);
8313 shrq(result);
8314 jmpb(DONE);
8315
8316 bind(VECTOR8_NOT_EQUAL);
8317 bind(VECTOR4_NOT_EQUAL);
8318 bsfq(tmp1, tmp1);
8319 shrq(tmp1, 3);
8320 addq(result, tmp1);
8321 bind(BYTES_NOT_EQUAL);
8322 shrq(result);
8323 jmpb(DONE);
8324
8325 bind(SAME_TILL_END);
8326 mov64(result, -1);
8327
8328 bind(DONE);
8329 }
8330
8331 //Helper functions for square_to_len()
8332
8333 /**
8334 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
8335 * Preserves x and z and modifies rest of the registers.
8336 */
8337 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8338 // Perform square and right shift by 1
8339 // Handle odd xlen case first, then for even xlen do the following
8340 // jlong carry = 0;
8341 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
8342 // huge_128 product = x[j:j+1] * x[j:j+1];
8343 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
8344 // z[i+2:i+3] = (jlong)(product >>> 1);
8345 // carry = (jlong)product;
8346 // }
8347
8348 xorq(tmp5, tmp5); // carry
8349 xorq(rdxReg, rdxReg);
8350 xorl(tmp1, tmp1); // index for x
8351 xorl(tmp4, tmp4); // index for z
8352
8353 Label L_first_loop, L_first_loop_exit;
8354
8355 testl(xlen, 1);
8356 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
8357
8358 // Square and right shift by 1 the odd element using 32 bit multiply
8359 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
8360 imulq(raxReg, raxReg);
8361 shrq(raxReg, 1);
8362 adcq(tmp5, 0);
8363 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
8364 incrementl(tmp1);
8365 addl(tmp4, 2);
8366
8367 // Square and right shift by 1 the rest using 64 bit multiply
8368 bind(L_first_loop);
8369 cmpptr(tmp1, xlen);
8370 jccb(Assembler::equal, L_first_loop_exit);
8371
8372 // Square
8373 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
8374 rorq(raxReg, 32); // convert big-endian to little-endian
8375 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
8376
8377 // Right shift by 1 and save carry
8378 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
8379 rcrq(rdxReg, 1);
8380 rcrq(raxReg, 1);
8381 adcq(tmp5, 0);
8382
8383 // Store result in z
8384 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
8385 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
8386
8387 // Update indices for x and z
8388 addl(tmp1, 2);
8389 addl(tmp4, 4);
8390 jmp(L_first_loop);
8391
8392 bind(L_first_loop_exit);
8393 }
8394
8395
8396 /**
8397 * Perform the following multiply add operation using BMI2 instructions
8398 * carry:sum = sum + op1*op2 + carry
8399 * op2 should be in rdx
8400 * op2 is preserved, all other registers are modified
8401 */
8402 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
8403 // assert op2 is rdx
8404 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
8405 addq(sum, carry);
8406 adcq(tmp2, 0);
8407 addq(sum, op1);
8408 adcq(tmp2, 0);
8409 movq(carry, tmp2);
8410 }
8411
8412 /**
8413 * Perform the following multiply add operation:
8414 * carry:sum = sum + op1*op2 + carry
8415 * Preserves op1, op2 and modifies rest of registers
8416 */
8417 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
8418 // rdx:rax = op1 * op2
8419 movq(raxReg, op2);
8420 mulq(op1);
8421
8422 // rdx:rax = sum + carry + rdx:rax
8423 addq(sum, carry);
8424 adcq(rdxReg, 0);
8425 addq(sum, raxReg);
8426 adcq(rdxReg, 0);
8427
8428 // carry:sum = rdx:sum
8429 movq(carry, rdxReg);
8430 }
8431
8432 /**
8433 * Add 64 bit long carry into z[] with carry propogation.
8434 * Preserves z and carry register values and modifies rest of registers.
8435 *
8436 */
8437 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
8438 Label L_fourth_loop, L_fourth_loop_exit;
8439
8440 movl(tmp1, 1);
8441 subl(zlen, 2);
8442 addq(Address(z, zlen, Address::times_4, 0), carry);
8443
8444 bind(L_fourth_loop);
8445 jccb(Assembler::carryClear, L_fourth_loop_exit);
8446 subl(zlen, 2);
8447 jccb(Assembler::negative, L_fourth_loop_exit);
8448 addq(Address(z, zlen, Address::times_4, 0), tmp1);
8449 jmp(L_fourth_loop);
8450 bind(L_fourth_loop_exit);
8451 }
8452
8453 /**
8454 * Shift z[] left by 1 bit.
8455 * Preserves x, len, z and zlen registers and modifies rest of the registers.
8456 *
8457 */
8458 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
8459
8460 Label L_fifth_loop, L_fifth_loop_exit;
8461
8462 // Fifth loop
8463 // Perform primitiveLeftShift(z, zlen, 1)
8464
8465 const Register prev_carry = tmp1;
8466 const Register new_carry = tmp4;
8467 const Register value = tmp2;
8468 const Register zidx = tmp3;
8469
8470 // int zidx, carry;
8471 // long value;
8472 // carry = 0;
8473 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
8474 // (carry:value) = (z[i] << 1) | carry ;
8475 // z[i] = value;
8476 // }
8477
8478 movl(zidx, zlen);
8479 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
8480
8481 bind(L_fifth_loop);
8482 decl(zidx); // Use decl to preserve carry flag
8483 decl(zidx);
8484 jccb(Assembler::negative, L_fifth_loop_exit);
8485
8486 if (UseBMI2Instructions) {
8487 movq(value, Address(z, zidx, Address::times_4, 0));
8488 rclq(value, 1);
8489 rorxq(value, value, 32);
8490 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8491 }
8492 else {
8493 // clear new_carry
8494 xorl(new_carry, new_carry);
8495
8496 // Shift z[i] by 1, or in previous carry and save new carry
8497 movq(value, Address(z, zidx, Address::times_4, 0));
8498 shlq(value, 1);
8499 adcl(new_carry, 0);
8500
8501 orq(value, prev_carry);
8502 rorq(value, 0x20);
8503 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8504
8505 // Set previous carry = new carry
8506 movl(prev_carry, new_carry);
8507 }
8508 jmp(L_fifth_loop);
8509
8510 bind(L_fifth_loop_exit);
8511 }
8512
8513
8514 /**
8515 * Code for BigInteger::squareToLen() intrinsic
8516 *
8517 * rdi: x
8518 * rsi: len
8519 * r8: z
8520 * rcx: zlen
8521 * r12: tmp1
8522 * r13: tmp2
8523 * r14: tmp3
8524 * r15: tmp4
8525 * rbx: tmp5
8526 *
8527 */
8528 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8529
8530 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
8531 push(tmp1);
8532 push(tmp2);
8533 push(tmp3);
8534 push(tmp4);
8535 push(tmp5);
8536
8537 // First loop
8538 // Store the squares, right shifted one bit (i.e., divided by 2).
8539 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8540
8541 // Add in off-diagonal sums.
8542 //
8543 // Second, third (nested) and fourth loops.
8544 // zlen +=2;
8545 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8546 // carry = 0;
8547 // long op2 = x[xidx:xidx+1];
8548 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8549 // k -= 2;
8550 // long op1 = x[j:j+1];
8551 // long sum = z[k:k+1];
8552 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8553 // z[k:k+1] = sum;
8554 // }
8555 // add_one_64(z, k, carry, tmp_regs);
8556 // }
8557
8558 const Register carry = tmp5;
8559 const Register sum = tmp3;
8560 const Register op1 = tmp4;
8561 Register op2 = tmp2;
8562
8563 push(zlen);
8564 push(len);
8565 addl(zlen,2);
8566 bind(L_second_loop);
8567 xorq(carry, carry);
8568 subl(zlen, 4);
8569 subl(len, 2);
8570 push(zlen);
8571 push(len);
8572 cmpl(len, 0);
8573 jccb(Assembler::lessEqual, L_second_loop_exit);
8574
8575 // Multiply an array by one 64 bit long.
8576 if (UseBMI2Instructions) {
8577 op2 = rdxReg;
8578 movq(op2, Address(x, len, Address::times_4, 0));
8579 rorxq(op2, op2, 32);
8580 }
8581 else {
8582 movq(op2, Address(x, len, Address::times_4, 0));
8583 rorq(op2, 32);
8584 }
8585
8586 bind(L_third_loop);
8587 decrementl(len);
8588 jccb(Assembler::negative, L_third_loop_exit);
8589 decrementl(len);
8590 jccb(Assembler::negative, L_last_x);
8591
8592 movq(op1, Address(x, len, Address::times_4, 0));
8593 rorq(op1, 32);
8594
8595 bind(L_multiply);
8596 subl(zlen, 2);
8597 movq(sum, Address(z, zlen, Address::times_4, 0));
8598
8599 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8600 if (UseBMI2Instructions) {
8601 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8602 }
8603 else {
8604 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8605 }
8606
8607 movq(Address(z, zlen, Address::times_4, 0), sum);
8608
8609 jmp(L_third_loop);
8610 bind(L_third_loop_exit);
8611
8612 // Fourth loop
8613 // Add 64 bit long carry into z with carry propogation.
8614 // Uses offsetted zlen.
8615 add_one_64(z, zlen, carry, tmp1);
8616
8617 pop(len);
8618 pop(zlen);
8619 jmp(L_second_loop);
8620
8621 // Next infrequent code is moved outside loops.
8622 bind(L_last_x);
8623 movl(op1, Address(x, 0));
8624 jmp(L_multiply);
8625
8626 bind(L_second_loop_exit);
8627 pop(len);
8628 pop(zlen);
8629 pop(len);
8630 pop(zlen);
8631
8632 // Fifth loop
8633 // Shift z left 1 bit.
8634 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8635
8636 // z[zlen-1] |= x[len-1] & 1;
8637 movl(tmp3, Address(x, len, Address::times_4, -4));
8638 andl(tmp3, 1);
8639 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8640
8641 pop(tmp5);
8642 pop(tmp4);
8643 pop(tmp3);
8644 pop(tmp2);
8645 pop(tmp1);
8646 }
8647
8648 /**
8649 * Helper function for mul_add()
8650 * Multiply the in[] by int k and add to out[] starting at offset offs using
8651 * 128 bit by 32 bit multiply and return the carry in tmp5.
8652 * Only quad int aligned length of in[] is operated on in this function.
8653 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8654 * This function preserves out, in and k registers.
8655 * len and offset point to the appropriate index in "in" & "out" correspondingly
8656 * tmp5 has the carry.
8657 * other registers are temporary and are modified.
8658 *
8659 */
8660 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8661 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8662 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8663
8664 Label L_first_loop, L_first_loop_exit;
8665
8666 movl(tmp1, len);
8667 shrl(tmp1, 2);
8668
8669 bind(L_first_loop);
8670 subl(tmp1, 1);
8671 jccb(Assembler::negative, L_first_loop_exit);
8672
8673 subl(len, 4);
8674 subl(offset, 4);
8675
8676 Register op2 = tmp2;
8677 const Register sum = tmp3;
8678 const Register op1 = tmp4;
8679 const Register carry = tmp5;
8680
8681 if (UseBMI2Instructions) {
8682 op2 = rdxReg;
8683 }
8684
8685 movq(op1, Address(in, len, Address::times_4, 8));
8686 rorq(op1, 32);
8687 movq(sum, Address(out, offset, Address::times_4, 8));
8688 rorq(sum, 32);
8689 if (UseBMI2Instructions) {
8690 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8691 }
8692 else {
8693 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8694 }
8695 // Store back in big endian from little endian
8696 rorq(sum, 0x20);
8697 movq(Address(out, offset, Address::times_4, 8), sum);
8698
8699 movq(op1, Address(in, len, Address::times_4, 0));
8700 rorq(op1, 32);
8701 movq(sum, Address(out, offset, Address::times_4, 0));
8702 rorq(sum, 32);
8703 if (UseBMI2Instructions) {
8704 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8705 }
8706 else {
8707 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8708 }
8709 // Store back in big endian from little endian
8710 rorq(sum, 0x20);
8711 movq(Address(out, offset, Address::times_4, 0), sum);
8712
8713 jmp(L_first_loop);
8714 bind(L_first_loop_exit);
8715 }
8716
8717 /**
8718 * Code for BigInteger::mulAdd() intrinsic
8719 *
8720 * rdi: out
8721 * rsi: in
8722 * r11: offs (out.length - offset)
8723 * rcx: len
8724 * r8: k
8725 * r12: tmp1
8726 * r13: tmp2
8727 * r14: tmp3
8728 * r15: tmp4
8729 * rbx: tmp5
8730 * Multiply the in[] by word k and add to out[], return the carry in rax
8731 */
8732 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8733 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8734 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8735
8736 Label L_carry, L_last_in, L_done;
8737
8738 // carry = 0;
8739 // for (int j=len-1; j >= 0; j--) {
8740 // long product = (in[j] & LONG_MASK) * kLong +
8741 // (out[offs] & LONG_MASK) + carry;
8742 // out[offs--] = (int)product;
8743 // carry = product >>> 32;
8744 // }
8745 //
8746 push(tmp1);
8747 push(tmp2);
8748 push(tmp3);
8749 push(tmp4);
8750 push(tmp5);
8751
8752 Register op2 = tmp2;
8753 const Register sum = tmp3;
8754 const Register op1 = tmp4;
8755 const Register carry = tmp5;
8756
8757 if (UseBMI2Instructions) {
8758 op2 = rdxReg;
8759 movl(op2, k);
8760 }
8761 else {
8762 movl(op2, k);
8763 }
8764
8765 xorq(carry, carry);
8766
8767 //First loop
8768
8769 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8770 //The carry is in tmp5
8771 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8772
8773 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8774 decrementl(len);
8775 jccb(Assembler::negative, L_carry);
8776 decrementl(len);
8777 jccb(Assembler::negative, L_last_in);
8778
8779 movq(op1, Address(in, len, Address::times_4, 0));
8780 rorq(op1, 32);
8781
8782 subl(offs, 2);
8783 movq(sum, Address(out, offs, Address::times_4, 0));
8784 rorq(sum, 32);
8785
8786 if (UseBMI2Instructions) {
8787 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8788 }
8789 else {
8790 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8791 }
8792
8793 // Store back in big endian from little endian
8794 rorq(sum, 0x20);
8795 movq(Address(out, offs, Address::times_4, 0), sum);
8796
8797 testl(len, len);
8798 jccb(Assembler::zero, L_carry);
8799
8800 //Multiply the last in[] entry, if any
8801 bind(L_last_in);
8802 movl(op1, Address(in, 0));
8803 movl(sum, Address(out, offs, Address::times_4, -4));
8804
8805 movl(raxReg, k);
8806 mull(op1); //tmp4 * eax -> edx:eax
8807 addl(sum, carry);
8808 adcl(rdxReg, 0);
8809 addl(sum, raxReg);
8810 adcl(rdxReg, 0);
8811 movl(carry, rdxReg);
8812
8813 movl(Address(out, offs, Address::times_4, -4), sum);
8814
8815 bind(L_carry);
8816 //return tmp5/carry as carry in rax
8817 movl(rax, carry);
8818
8819 bind(L_done);
8820 pop(tmp5);
8821 pop(tmp4);
8822 pop(tmp3);
8823 pop(tmp2);
8824 pop(tmp1);
8825 }
8826 #endif
8827
8828 /**
8829 * Emits code to update CRC-32 with a byte value according to constants in table
8830 *
8831 * @param [in,out]crc Register containing the crc.
8832 * @param [in]val Register containing the byte to fold into the CRC.
8833 * @param [in]table Register containing the table of crc constants.
8834 *
8835 * uint32_t crc;
8836 * val = crc_table[(val ^ crc) & 0xFF];
8837 * crc = val ^ (crc >> 8);
8838 *
8839 */
8840 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8841 xorl(val, crc);
8842 andl(val, 0xFF);
8843 shrl(crc, 8); // unsigned shift
8844 xorl(crc, Address(table, val, Address::times_4, 0));
8845 }
8846
8847 /**
8848 * Fold four 128-bit data chunks
8849 */
8850 void MacroAssembler::fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8851 evpclmulhdq(xtmp, xK, xcrc, Assembler::AVX_512bit); // [123:64]
8852 evpclmulldq(xcrc, xK, xcrc, Assembler::AVX_512bit); // [63:0]
8853 evpxorq(xcrc, xcrc, Address(buf, offset), Assembler::AVX_512bit /* vector_len */);
8854 evpxorq(xcrc, xcrc, xtmp, Assembler::AVX_512bit /* vector_len */);
8855 }
8856
8857 /**
8858 * Fold 128-bit data chunk
8859 */
8860 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8861 if (UseAVX > 0) {
8862 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8863 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8864 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8865 pxor(xcrc, xtmp);
8866 } else {
8867 movdqa(xtmp, xcrc);
8868 pclmulhdq(xtmp, xK); // [123:64]
8869 pclmulldq(xcrc, xK); // [63:0]
8870 pxor(xcrc, xtmp);
8871 movdqu(xtmp, Address(buf, offset));
8872 pxor(xcrc, xtmp);
8873 }
8874 }
8875
8876 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8877 if (UseAVX > 0) {
8878 vpclmulhdq(xtmp, xK, xcrc);
8879 vpclmulldq(xcrc, xK, xcrc);
8880 pxor(xcrc, xbuf);
8881 pxor(xcrc, xtmp);
8882 } else {
8883 movdqa(xtmp, xcrc);
8884 pclmulhdq(xtmp, xK);
8885 pclmulldq(xcrc, xK);
8886 pxor(xcrc, xbuf);
8887 pxor(xcrc, xtmp);
8888 }
8889 }
8890
8891 /**
8892 * 8-bit folds to compute 32-bit CRC
8893 *
8894 * uint64_t xcrc;
8895 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8896 */
8897 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8898 movdl(tmp, xcrc);
8899 andl(tmp, 0xFF);
8900 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8901 psrldq(xcrc, 1); // unsigned shift one byte
8902 pxor(xcrc, xtmp);
8903 }
8904
8905 /**
8906 * uint32_t crc;
8907 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8908 */
8909 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8910 movl(tmp, crc);
8911 andl(tmp, 0xFF);
8912 shrl(crc, 8);
8913 xorl(crc, Address(table, tmp, Address::times_4, 0));
8914 }
8915
8916 /**
8917 * @param crc register containing existing CRC (32-bit)
8918 * @param buf register pointing to input byte buffer (byte*)
8919 * @param len register containing number of bytes
8920 * @param table register that will contain address of CRC table
8921 * @param tmp scratch register
8922 */
8923 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8924 assert_different_registers(crc, buf, len, table, tmp, rax);
8925
8926 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8927 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8928
8929 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8930 // context for the registers used, where all instructions below are using 128-bit mode
8931 // On EVEX without VL and BW, these instructions will all be AVX.
8932 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8933 notl(crc); // ~crc
8934 cmpl(len, 16);
8935 jcc(Assembler::less, L_tail);
8936
8937 // Align buffer to 16 bytes
8938 movl(tmp, buf);
8939 andl(tmp, 0xF);
8940 jccb(Assembler::zero, L_aligned);
8941 subl(tmp, 16);
8942 addl(len, tmp);
8943
8944 align(4);
8945 BIND(L_align_loop);
8946 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8947 update_byte_crc32(crc, rax, table);
8948 increment(buf);
8949 incrementl(tmp);
8950 jccb(Assembler::less, L_align_loop);
8951
8952 BIND(L_aligned);
8953 movl(tmp, len); // save
8954 shrl(len, 4);
8955 jcc(Assembler::zero, L_tail_restore);
8956
8957 // Fold total 512 bits of polynomial on each iteration
8958 if (VM_Version::supports_vpclmulqdq()) {
8959 Label Parallel_loop, L_No_Parallel;
8960
8961 cmpl(len, 8);
8962 jccb(Assembler::less, L_No_Parallel);
8963
8964 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
8965 evmovdquq(xmm1, Address(buf, 0), Assembler::AVX_512bit);
8966 movdl(xmm5, crc);
8967 evpxorq(xmm1, xmm1, xmm5, Assembler::AVX_512bit);
8968 addptr(buf, 64);
8969 subl(len, 7);
8970 evshufi64x2(xmm0, xmm0, xmm0, 0x00, Assembler::AVX_512bit); //propagate the mask from 128 bits to 512 bits
8971
8972 BIND(Parallel_loop);
8973 fold_128bit_crc32_avx512(xmm1, xmm0, xmm5, buf, 0);
8974 addptr(buf, 64);
8975 subl(len, 4);
8976 jcc(Assembler::greater, Parallel_loop);
8977
8978 vextracti64x2(xmm2, xmm1, 0x01);
8979 vextracti64x2(xmm3, xmm1, 0x02);
8980 vextracti64x2(xmm4, xmm1, 0x03);
8981 jmp(L_fold_512b);
8982
8983 BIND(L_No_Parallel);
8984 }
8985 // Fold crc into first bytes of vector
8986 movdqa(xmm1, Address(buf, 0));
8987 movdl(rax, xmm1);
8988 xorl(crc, rax);
8989 if (VM_Version::supports_sse4_1()) {
8990 pinsrd(xmm1, crc, 0);
8991 } else {
8992 pinsrw(xmm1, crc, 0);
8993 shrl(crc, 16);
8994 pinsrw(xmm1, crc, 1);
8995 }
8996 addptr(buf, 16);
8997 subl(len, 4); // len > 0
8998 jcc(Assembler::less, L_fold_tail);
8999
9000 movdqa(xmm2, Address(buf, 0));
9001 movdqa(xmm3, Address(buf, 16));
9002 movdqa(xmm4, Address(buf, 32));
9003 addptr(buf, 48);
9004 subl(len, 3);
9005 jcc(Assembler::lessEqual, L_fold_512b);
9006
9007 // Fold total 512 bits of polynomial on each iteration,
9008 // 128 bits per each of 4 parallel streams.
9009 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
9010
9011 align(32);
9012 BIND(L_fold_512b_loop);
9013 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
9014 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
9015 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
9016 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
9017 addptr(buf, 64);
9018 subl(len, 4);
9019 jcc(Assembler::greater, L_fold_512b_loop);
9020
9021 // Fold 512 bits to 128 bits.
9022 BIND(L_fold_512b);
9023 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
9024 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
9025 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
9026 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
9027
9028 // Fold the rest of 128 bits data chunks
9029 BIND(L_fold_tail);
9030 addl(len, 3);
9031 jccb(Assembler::lessEqual, L_fold_128b);
9032 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
9033
9034 BIND(L_fold_tail_loop);
9035 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
9036 addptr(buf, 16);
9037 decrementl(len);
9038 jccb(Assembler::greater, L_fold_tail_loop);
9039
9040 // Fold 128 bits in xmm1 down into 32 bits in crc register.
9041 BIND(L_fold_128b);
9042 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
9043 if (UseAVX > 0) {
9044 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
9045 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
9046 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
9047 } else {
9048 movdqa(xmm2, xmm0);
9049 pclmulqdq(xmm2, xmm1, 0x1);
9050 movdqa(xmm3, xmm0);
9051 pand(xmm3, xmm2);
9052 pclmulqdq(xmm0, xmm3, 0x1);
9053 }
9054 psrldq(xmm1, 8);
9055 psrldq(xmm2, 4);
9056 pxor(xmm0, xmm1);
9057 pxor(xmm0, xmm2);
9058
9059 // 8 8-bit folds to compute 32-bit CRC.
9060 for (int j = 0; j < 4; j++) {
9061 fold_8bit_crc32(xmm0, table, xmm1, rax);
9062 }
9063 movdl(crc, xmm0); // mov 32 bits to general register
9064 for (int j = 0; j < 4; j++) {
9065 fold_8bit_crc32(crc, table, rax);
9066 }
9067
9068 BIND(L_tail_restore);
9069 movl(len, tmp); // restore
9070 BIND(L_tail);
9071 andl(len, 0xf);
9072 jccb(Assembler::zero, L_exit);
9073
9074 // Fold the rest of bytes
9075 align(4);
9076 BIND(L_tail_loop);
9077 movsbl(rax, Address(buf, 0)); // load byte with sign extension
9078 update_byte_crc32(crc, rax, table);
9079 increment(buf);
9080 decrementl(len);
9081 jccb(Assembler::greater, L_tail_loop);
9082
9083 BIND(L_exit);
9084 notl(crc); // ~c
9085 }
9086
9087 #ifdef _LP64
9088 // S. Gueron / Information Processing Letters 112 (2012) 184
9089 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
9090 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
9091 // Output: the 64-bit carry-less product of B * CONST
9092 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
9093 Register tmp1, Register tmp2, Register tmp3) {
9094 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9095 if (n > 0) {
9096 addq(tmp3, n * 256 * 8);
9097 }
9098 // Q1 = TABLEExt[n][B & 0xFF];
9099 movl(tmp1, in);
9100 andl(tmp1, 0x000000FF);
9101 shll(tmp1, 3);
9102 addq(tmp1, tmp3);
9103 movq(tmp1, Address(tmp1, 0));
9104
9105 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9106 movl(tmp2, in);
9107 shrl(tmp2, 8);
9108 andl(tmp2, 0x000000FF);
9109 shll(tmp2, 3);
9110 addq(tmp2, tmp3);
9111 movq(tmp2, Address(tmp2, 0));
9112
9113 shlq(tmp2, 8);
9114 xorq(tmp1, tmp2);
9115
9116 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9117 movl(tmp2, in);
9118 shrl(tmp2, 16);
9119 andl(tmp2, 0x000000FF);
9120 shll(tmp2, 3);
9121 addq(tmp2, tmp3);
9122 movq(tmp2, Address(tmp2, 0));
9123
9124 shlq(tmp2, 16);
9125 xorq(tmp1, tmp2);
9126
9127 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9128 shrl(in, 24);
9129 andl(in, 0x000000FF);
9130 shll(in, 3);
9131 addq(in, tmp3);
9132 movq(in, Address(in, 0));
9133
9134 shlq(in, 24);
9135 xorq(in, tmp1);
9136 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9137 }
9138
9139 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9140 Register in_out,
9141 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9142 XMMRegister w_xtmp2,
9143 Register tmp1,
9144 Register n_tmp2, Register n_tmp3) {
9145 if (is_pclmulqdq_supported) {
9146 movdl(w_xtmp1, in_out); // modified blindly
9147
9148 movl(tmp1, const_or_pre_comp_const_index);
9149 movdl(w_xtmp2, tmp1);
9150 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9151
9152 movdq(in_out, w_xtmp1);
9153 } else {
9154 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
9155 }
9156 }
9157
9158 // Recombination Alternative 2: No bit-reflections
9159 // T1 = (CRC_A * U1) << 1
9160 // T2 = (CRC_B * U2) << 1
9161 // C1 = T1 >> 32
9162 // C2 = T2 >> 32
9163 // T1 = T1 & 0xFFFFFFFF
9164 // T2 = T2 & 0xFFFFFFFF
9165 // T1 = CRC32(0, T1)
9166 // T2 = CRC32(0, T2)
9167 // C1 = C1 ^ T1
9168 // C2 = C2 ^ T2
9169 // CRC = C1 ^ C2 ^ CRC_C
9170 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9171 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9172 Register tmp1, Register tmp2,
9173 Register n_tmp3) {
9174 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9175 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9176 shlq(in_out, 1);
9177 movl(tmp1, in_out);
9178 shrq(in_out, 32);
9179 xorl(tmp2, tmp2);
9180 crc32(tmp2, tmp1, 4);
9181 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
9182 shlq(in1, 1);
9183 movl(tmp1, in1);
9184 shrq(in1, 32);
9185 xorl(tmp2, tmp2);
9186 crc32(tmp2, tmp1, 4);
9187 xorl(in1, tmp2);
9188 xorl(in_out, in1);
9189 xorl(in_out, in2);
9190 }
9191
9192 // Set N to predefined value
9193 // Subtract from a lenght of a buffer
9194 // execute in a loop:
9195 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
9196 // for i = 1 to N do
9197 // CRC_A = CRC32(CRC_A, A[i])
9198 // CRC_B = CRC32(CRC_B, B[i])
9199 // CRC_C = CRC32(CRC_C, C[i])
9200 // end for
9201 // Recombine
9202 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9203 Register in_out1, Register in_out2, Register in_out3,
9204 Register tmp1, Register tmp2, Register tmp3,
9205 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9206 Register tmp4, Register tmp5,
9207 Register n_tmp6) {
9208 Label L_processPartitions;
9209 Label L_processPartition;
9210 Label L_exit;
9211
9212 bind(L_processPartitions);
9213 cmpl(in_out1, 3 * size);
9214 jcc(Assembler::less, L_exit);
9215 xorl(tmp1, tmp1);
9216 xorl(tmp2, tmp2);
9217 movq(tmp3, in_out2);
9218 addq(tmp3, size);
9219
9220 bind(L_processPartition);
9221 crc32(in_out3, Address(in_out2, 0), 8);
9222 crc32(tmp1, Address(in_out2, size), 8);
9223 crc32(tmp2, Address(in_out2, size * 2), 8);
9224 addq(in_out2, 8);
9225 cmpq(in_out2, tmp3);
9226 jcc(Assembler::less, L_processPartition);
9227 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9228 w_xtmp1, w_xtmp2, w_xtmp3,
9229 tmp4, tmp5,
9230 n_tmp6);
9231 addq(in_out2, 2 * size);
9232 subl(in_out1, 3 * size);
9233 jmp(L_processPartitions);
9234
9235 bind(L_exit);
9236 }
9237 #else
9238 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
9239 Register tmp1, Register tmp2, Register tmp3,
9240 XMMRegister xtmp1, XMMRegister xtmp2) {
9241 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9242 if (n > 0) {
9243 addl(tmp3, n * 256 * 8);
9244 }
9245 // Q1 = TABLEExt[n][B & 0xFF];
9246 movl(tmp1, in_out);
9247 andl(tmp1, 0x000000FF);
9248 shll(tmp1, 3);
9249 addl(tmp1, tmp3);
9250 movq(xtmp1, Address(tmp1, 0));
9251
9252 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9253 movl(tmp2, in_out);
9254 shrl(tmp2, 8);
9255 andl(tmp2, 0x000000FF);
9256 shll(tmp2, 3);
9257 addl(tmp2, tmp3);
9258 movq(xtmp2, Address(tmp2, 0));
9259
9260 psllq(xtmp2, 8);
9261 pxor(xtmp1, xtmp2);
9262
9263 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9264 movl(tmp2, in_out);
9265 shrl(tmp2, 16);
9266 andl(tmp2, 0x000000FF);
9267 shll(tmp2, 3);
9268 addl(tmp2, tmp3);
9269 movq(xtmp2, Address(tmp2, 0));
9270
9271 psllq(xtmp2, 16);
9272 pxor(xtmp1, xtmp2);
9273
9274 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9275 shrl(in_out, 24);
9276 andl(in_out, 0x000000FF);
9277 shll(in_out, 3);
9278 addl(in_out, tmp3);
9279 movq(xtmp2, Address(in_out, 0));
9280
9281 psllq(xtmp2, 24);
9282 pxor(xtmp1, xtmp2); // Result in CXMM
9283 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9284 }
9285
9286 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9287 Register in_out,
9288 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9289 XMMRegister w_xtmp2,
9290 Register tmp1,
9291 Register n_tmp2, Register n_tmp3) {
9292 if (is_pclmulqdq_supported) {
9293 movdl(w_xtmp1, in_out);
9294
9295 movl(tmp1, const_or_pre_comp_const_index);
9296 movdl(w_xtmp2, tmp1);
9297 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9298 // Keep result in XMM since GPR is 32 bit in length
9299 } else {
9300 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
9301 }
9302 }
9303
9304 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9305 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9306 Register tmp1, Register tmp2,
9307 Register n_tmp3) {
9308 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9309 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9310
9311 psllq(w_xtmp1, 1);
9312 movdl(tmp1, w_xtmp1);
9313 psrlq(w_xtmp1, 32);
9314 movdl(in_out, w_xtmp1);
9315
9316 xorl(tmp2, tmp2);
9317 crc32(tmp2, tmp1, 4);
9318 xorl(in_out, tmp2);
9319
9320 psllq(w_xtmp2, 1);
9321 movdl(tmp1, w_xtmp2);
9322 psrlq(w_xtmp2, 32);
9323 movdl(in1, w_xtmp2);
9324
9325 xorl(tmp2, tmp2);
9326 crc32(tmp2, tmp1, 4);
9327 xorl(in1, tmp2);
9328 xorl(in_out, in1);
9329 xorl(in_out, in2);
9330 }
9331
9332 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9333 Register in_out1, Register in_out2, Register in_out3,
9334 Register tmp1, Register tmp2, Register tmp3,
9335 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9336 Register tmp4, Register tmp5,
9337 Register n_tmp6) {
9338 Label L_processPartitions;
9339 Label L_processPartition;
9340 Label L_exit;
9341
9342 bind(L_processPartitions);
9343 cmpl(in_out1, 3 * size);
9344 jcc(Assembler::less, L_exit);
9345 xorl(tmp1, tmp1);
9346 xorl(tmp2, tmp2);
9347 movl(tmp3, in_out2);
9348 addl(tmp3, size);
9349
9350 bind(L_processPartition);
9351 crc32(in_out3, Address(in_out2, 0), 4);
9352 crc32(tmp1, Address(in_out2, size), 4);
9353 crc32(tmp2, Address(in_out2, size*2), 4);
9354 crc32(in_out3, Address(in_out2, 0+4), 4);
9355 crc32(tmp1, Address(in_out2, size+4), 4);
9356 crc32(tmp2, Address(in_out2, size*2+4), 4);
9357 addl(in_out2, 8);
9358 cmpl(in_out2, tmp3);
9359 jcc(Assembler::less, L_processPartition);
9360
9361 push(tmp3);
9362 push(in_out1);
9363 push(in_out2);
9364 tmp4 = tmp3;
9365 tmp5 = in_out1;
9366 n_tmp6 = in_out2;
9367
9368 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9369 w_xtmp1, w_xtmp2, w_xtmp3,
9370 tmp4, tmp5,
9371 n_tmp6);
9372
9373 pop(in_out2);
9374 pop(in_out1);
9375 pop(tmp3);
9376
9377 addl(in_out2, 2 * size);
9378 subl(in_out1, 3 * size);
9379 jmp(L_processPartitions);
9380
9381 bind(L_exit);
9382 }
9383 #endif //LP64
9384
9385 #ifdef _LP64
9386 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9387 // Input: A buffer I of L bytes.
9388 // Output: the CRC32C value of the buffer.
9389 // Notations:
9390 // Write L = 24N + r, with N = floor (L/24).
9391 // r = L mod 24 (0 <= r < 24).
9392 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9393 // N quadwords, and R consists of r bytes.
9394 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9395 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9396 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9397 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9398 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9399 Register tmp1, Register tmp2, Register tmp3,
9400 Register tmp4, Register tmp5, Register tmp6,
9401 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9402 bool is_pclmulqdq_supported) {
9403 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9404 Label L_wordByWord;
9405 Label L_byteByByteProlog;
9406 Label L_byteByByte;
9407 Label L_exit;
9408
9409 if (is_pclmulqdq_supported ) {
9410 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9411 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
9412
9413 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9414 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9415
9416 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9417 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9418 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9419 } else {
9420 const_or_pre_comp_const_index[0] = 1;
9421 const_or_pre_comp_const_index[1] = 0;
9422
9423 const_or_pre_comp_const_index[2] = 3;
9424 const_or_pre_comp_const_index[3] = 2;
9425
9426 const_or_pre_comp_const_index[4] = 5;
9427 const_or_pre_comp_const_index[5] = 4;
9428 }
9429 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9430 in2, in1, in_out,
9431 tmp1, tmp2, tmp3,
9432 w_xtmp1, w_xtmp2, w_xtmp3,
9433 tmp4, tmp5,
9434 tmp6);
9435 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9436 in2, in1, in_out,
9437 tmp1, tmp2, tmp3,
9438 w_xtmp1, w_xtmp2, w_xtmp3,
9439 tmp4, tmp5,
9440 tmp6);
9441 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9442 in2, in1, in_out,
9443 tmp1, tmp2, tmp3,
9444 w_xtmp1, w_xtmp2, w_xtmp3,
9445 tmp4, tmp5,
9446 tmp6);
9447 movl(tmp1, in2);
9448 andl(tmp1, 0x00000007);
9449 negl(tmp1);
9450 addl(tmp1, in2);
9451 addq(tmp1, in1);
9452
9453 BIND(L_wordByWord);
9454 cmpq(in1, tmp1);
9455 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9456 crc32(in_out, Address(in1, 0), 4);
9457 addq(in1, 4);
9458 jmp(L_wordByWord);
9459
9460 BIND(L_byteByByteProlog);
9461 andl(in2, 0x00000007);
9462 movl(tmp2, 1);
9463
9464 BIND(L_byteByByte);
9465 cmpl(tmp2, in2);
9466 jccb(Assembler::greater, L_exit);
9467 crc32(in_out, Address(in1, 0), 1);
9468 incq(in1);
9469 incl(tmp2);
9470 jmp(L_byteByByte);
9471
9472 BIND(L_exit);
9473 }
9474 #else
9475 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9476 Register tmp1, Register tmp2, Register tmp3,
9477 Register tmp4, Register tmp5, Register tmp6,
9478 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9479 bool is_pclmulqdq_supported) {
9480 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9481 Label L_wordByWord;
9482 Label L_byteByByteProlog;
9483 Label L_byteByByte;
9484 Label L_exit;
9485
9486 if (is_pclmulqdq_supported) {
9487 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9488 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
9489
9490 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9491 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9492
9493 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9494 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9495 } else {
9496 const_or_pre_comp_const_index[0] = 1;
9497 const_or_pre_comp_const_index[1] = 0;
9498
9499 const_or_pre_comp_const_index[2] = 3;
9500 const_or_pre_comp_const_index[3] = 2;
9501
9502 const_or_pre_comp_const_index[4] = 5;
9503 const_or_pre_comp_const_index[5] = 4;
9504 }
9505 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9506 in2, in1, in_out,
9507 tmp1, tmp2, tmp3,
9508 w_xtmp1, w_xtmp2, w_xtmp3,
9509 tmp4, tmp5,
9510 tmp6);
9511 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9512 in2, in1, in_out,
9513 tmp1, tmp2, tmp3,
9514 w_xtmp1, w_xtmp2, w_xtmp3,
9515 tmp4, tmp5,
9516 tmp6);
9517 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9518 in2, in1, in_out,
9519 tmp1, tmp2, tmp3,
9520 w_xtmp1, w_xtmp2, w_xtmp3,
9521 tmp4, tmp5,
9522 tmp6);
9523 movl(tmp1, in2);
9524 andl(tmp1, 0x00000007);
9525 negl(tmp1);
9526 addl(tmp1, in2);
9527 addl(tmp1, in1);
9528
9529 BIND(L_wordByWord);
9530 cmpl(in1, tmp1);
9531 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9532 crc32(in_out, Address(in1,0), 4);
9533 addl(in1, 4);
9534 jmp(L_wordByWord);
9535
9536 BIND(L_byteByByteProlog);
9537 andl(in2, 0x00000007);
9538 movl(tmp2, 1);
9539
9540 BIND(L_byteByByte);
9541 cmpl(tmp2, in2);
9542 jccb(Assembler::greater, L_exit);
9543 movb(tmp1, Address(in1, 0));
9544 crc32(in_out, tmp1, 1);
9545 incl(in1);
9546 incl(tmp2);
9547 jmp(L_byteByByte);
9548
9549 BIND(L_exit);
9550 }
9551 #endif // LP64
9552 #undef BIND
9553 #undef BLOCK_COMMENT
9554
9555 // Compress char[] array to byte[].
9556 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
9557 // @HotSpotIntrinsicCandidate
9558 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9559 // for (int i = 0; i < len; i++) {
9560 // int c = src[srcOff++];
9561 // if (c >>> 8 != 0) {
9562 // return 0;
9563 // }
9564 // dst[dstOff++] = (byte)c;
9565 // }
9566 // return len;
9567 // }
9568 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9569 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9570 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9571 Register tmp5, Register result) {
9572 Label copy_chars_loop, return_length, return_zero, done;
9573
9574 // rsi: src
9575 // rdi: dst
9576 // rdx: len
9577 // rcx: tmp5
9578 // rax: result
9579
9580 // rsi holds start addr of source char[] to be compressed
9581 // rdi holds start addr of destination byte[]
9582 // rdx holds length
9583
9584 assert(len != result, "");
9585
9586 // save length for return
9587 push(len);
9588
9589 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9590 VM_Version::supports_avx512vlbw() &&
9591 VM_Version::supports_bmi2()) {
9592
9593 Label copy_32_loop, copy_loop_tail, below_threshold;
9594
9595 // alignment
9596 Label post_alignment;
9597
9598 // if length of the string is less than 16, handle it in an old fashioned way
9599 testl(len, -32);
9600 jcc(Assembler::zero, below_threshold);
9601
9602 // First check whether a character is compressable ( <= 0xFF).
9603 // Create mask to test for Unicode chars inside zmm vector
9604 movl(result, 0x00FF);
9605 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
9606
9607 testl(len, -64);
9608 jcc(Assembler::zero, post_alignment);
9609
9610 movl(tmp5, dst);
9611 andl(tmp5, (32 - 1));
9612 negl(tmp5);
9613 andl(tmp5, (32 - 1));
9614
9615 // bail out when there is nothing to be done
9616 testl(tmp5, 0xFFFFFFFF);
9617 jcc(Assembler::zero, post_alignment);
9618
9619 // ~(~0 << len), where len is the # of remaining elements to process
9620 movl(result, 0xFFFFFFFF);
9621 shlxl(result, result, tmp5);
9622 notl(result);
9623 kmovdl(k3, result);
9624
9625 evmovdquw(tmp1Reg, k3, Address(src, 0), Assembler::AVX_512bit);
9626 evpcmpuw(k2, k3, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9627 ktestd(k2, k3);
9628 jcc(Assembler::carryClear, return_zero);
9629
9630 evpmovwb(Address(dst, 0), k3, tmp1Reg, Assembler::AVX_512bit);
9631
9632 addptr(src, tmp5);
9633 addptr(src, tmp5);
9634 addptr(dst, tmp5);
9635 subl(len, tmp5);
9636
9637 bind(post_alignment);
9638 // end of alignment
9639
9640 movl(tmp5, len);
9641 andl(tmp5, (32 - 1)); // tail count (in chars)
9642 andl(len, ~(32 - 1)); // vector count (in chars)
9643 jcc(Assembler::zero, copy_loop_tail);
9644
9645 lea(src, Address(src, len, Address::times_2));
9646 lea(dst, Address(dst, len, Address::times_1));
9647 negptr(len);
9648
9649 bind(copy_32_loop);
9650 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9651 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9652 kortestdl(k2, k2);
9653 jcc(Assembler::carryClear, return_zero);
9654
9655 // All elements in current processed chunk are valid candidates for
9656 // compression. Write a truncated byte elements to the memory.
9657 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9658 addptr(len, 32);
9659 jcc(Assembler::notZero, copy_32_loop);
9660
9661 bind(copy_loop_tail);
9662 // bail out when there is nothing to be done
9663 testl(tmp5, 0xFFFFFFFF);
9664 jcc(Assembler::zero, return_length);
9665
9666 movl(len, tmp5);
9667
9668 // ~(~0 << len), where len is the # of remaining elements to process
9669 movl(result, 0xFFFFFFFF);
9670 shlxl(result, result, len);
9671 notl(result);
9672
9673 kmovdl(k3, result);
9674
9675 evmovdquw(tmp1Reg, k3, Address(src, 0), Assembler::AVX_512bit);
9676 evpcmpuw(k2, k3, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9677 ktestd(k2, k3);
9678 jcc(Assembler::carryClear, return_zero);
9679
9680 evpmovwb(Address(dst, 0), k3, tmp1Reg, Assembler::AVX_512bit);
9681 jmp(return_length);
9682
9683 bind(below_threshold);
9684 }
9685
9686 if (UseSSE42Intrinsics) {
9687 Label copy_32_loop, copy_16, copy_tail;
9688
9689 movl(result, len);
9690
9691 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9692
9693 // vectored compression
9694 andl(len, 0xfffffff0); // vector count (in chars)
9695 andl(result, 0x0000000f); // tail count (in chars)
9696 testl(len, len);
9697 jcc(Assembler::zero, copy_16);
9698
9699 // compress 16 chars per iter
9700 movdl(tmp1Reg, tmp5);
9701 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9702 pxor(tmp4Reg, tmp4Reg);
9703
9704 lea(src, Address(src, len, Address::times_2));
9705 lea(dst, Address(dst, len, Address::times_1));
9706 negptr(len);
9707
9708 bind(copy_32_loop);
9709 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9710 por(tmp4Reg, tmp2Reg);
9711 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9712 por(tmp4Reg, tmp3Reg);
9713 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9714 jcc(Assembler::notZero, return_zero);
9715 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9716 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9717 addptr(len, 16);
9718 jcc(Assembler::notZero, copy_32_loop);
9719
9720 // compress next vector of 8 chars (if any)
9721 bind(copy_16);
9722 movl(len, result);
9723 andl(len, 0xfffffff8); // vector count (in chars)
9724 andl(result, 0x00000007); // tail count (in chars)
9725 testl(len, len);
9726 jccb(Assembler::zero, copy_tail);
9727
9728 movdl(tmp1Reg, tmp5);
9729 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9730 pxor(tmp3Reg, tmp3Reg);
9731
9732 movdqu(tmp2Reg, Address(src, 0));
9733 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9734 jccb(Assembler::notZero, return_zero);
9735 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9736 movq(Address(dst, 0), tmp2Reg);
9737 addptr(src, 16);
9738 addptr(dst, 8);
9739
9740 bind(copy_tail);
9741 movl(len, result);
9742 }
9743 // compress 1 char per iter
9744 testl(len, len);
9745 jccb(Assembler::zero, return_length);
9746 lea(src, Address(src, len, Address::times_2));
9747 lea(dst, Address(dst, len, Address::times_1));
9748 negptr(len);
9749
9750 bind(copy_chars_loop);
9751 load_unsigned_short(result, Address(src, len, Address::times_2));
9752 testl(result, 0xff00); // check if Unicode char
9753 jccb(Assembler::notZero, return_zero);
9754 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
9755 increment(len);
9756 jcc(Assembler::notZero, copy_chars_loop);
9757
9758 // if compression succeeded, return length
9759 bind(return_length);
9760 pop(result);
9761 jmpb(done);
9762
9763 // if compression failed, return 0
9764 bind(return_zero);
9765 xorl(result, result);
9766 addptr(rsp, wordSize);
9767
9768 bind(done);
9769 }
9770
9771 // Inflate byte[] array to char[].
9772 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9773 // @HotSpotIntrinsicCandidate
9774 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9775 // for (int i = 0; i < len; i++) {
9776 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9777 // }
9778 // }
9779 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9780 XMMRegister tmp1, Register tmp2) {
9781 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9782 // rsi: src
9783 // rdi: dst
9784 // rdx: len
9785 // rcx: tmp2
9786
9787 // rsi holds start addr of source byte[] to be inflated
9788 // rdi holds start addr of destination char[]
9789 // rdx holds length
9790 assert_different_registers(src, dst, len, tmp2);
9791 movl(tmp2, len);
9792 if ((UseAVX > 2) && // AVX512
9793 VM_Version::supports_avx512vlbw() &&
9794 VM_Version::supports_bmi2()) {
9795
9796 Label copy_32_loop, copy_tail;
9797 Register tmp3_aliased = len;
9798
9799 // if length of the string is less than 16, handle it in an old fashioned way
9800 testl(len, -16);
9801 jcc(Assembler::zero, below_threshold);
9802
9803 testl(len, -1 * AVX3Threshold);
9804 jcc(Assembler::zero, avx3_threshold);
9805
9806 // In order to use only one arithmetic operation for the main loop we use
9807 // this pre-calculation
9808 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9809 andl(len, -32); // vector count
9810 jccb(Assembler::zero, copy_tail);
9811
9812 lea(src, Address(src, len, Address::times_1));
9813 lea(dst, Address(dst, len, Address::times_2));
9814 negptr(len);
9815
9816
9817 // inflate 32 chars per iter
9818 bind(copy_32_loop);
9819 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9820 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9821 addptr(len, 32);
9822 jcc(Assembler::notZero, copy_32_loop);
9823
9824 bind(copy_tail);
9825 // bail out when there is nothing to be done
9826 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9827 jcc(Assembler::zero, done);
9828
9829 // ~(~0 << length), where length is the # of remaining elements to process
9830 movl(tmp3_aliased, -1);
9831 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9832 notl(tmp3_aliased);
9833 kmovdl(k2, tmp3_aliased);
9834 evpmovzxbw(tmp1, k2, Address(src, 0), Assembler::AVX_512bit);
9835 evmovdquw(Address(dst, 0), k2, tmp1, Assembler::AVX_512bit);
9836
9837 jmp(done);
9838 bind(avx3_threshold);
9839 }
9840 if (UseSSE42Intrinsics) {
9841 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9842
9843 if (UseAVX > 1) {
9844 andl(tmp2, (16 - 1));
9845 andl(len, -16);
9846 jccb(Assembler::zero, copy_new_tail);
9847 } else {
9848 andl(tmp2, 0x00000007); // tail count (in chars)
9849 andl(len, 0xfffffff8); // vector count (in chars)
9850 jccb(Assembler::zero, copy_tail);
9851 }
9852
9853 // vectored inflation
9854 lea(src, Address(src, len, Address::times_1));
9855 lea(dst, Address(dst, len, Address::times_2));
9856 negptr(len);
9857
9858 if (UseAVX > 1) {
9859 bind(copy_16_loop);
9860 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9861 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9862 addptr(len, 16);
9863 jcc(Assembler::notZero, copy_16_loop);
9864
9865 bind(below_threshold);
9866 bind(copy_new_tail);
9867 movl(len, tmp2);
9868 andl(tmp2, 0x00000007);
9869 andl(len, 0xFFFFFFF8);
9870 jccb(Assembler::zero, copy_tail);
9871
9872 pmovzxbw(tmp1, Address(src, 0));
9873 movdqu(Address(dst, 0), tmp1);
9874 addptr(src, 8);
9875 addptr(dst, 2 * 8);
9876
9877 jmp(copy_tail, true);
9878 }
9879
9880 // inflate 8 chars per iter
9881 bind(copy_8_loop);
9882 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9883 movdqu(Address(dst, len, Address::times_2), tmp1);
9884 addptr(len, 8);
9885 jcc(Assembler::notZero, copy_8_loop);
9886
9887 bind(copy_tail);
9888 movl(len, tmp2);
9889
9890 cmpl(len, 4);
9891 jccb(Assembler::less, copy_bytes);
9892
9893 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9894 pmovzxbw(tmp1, tmp1);
9895 movq(Address(dst, 0), tmp1);
9896 subptr(len, 4);
9897 addptr(src, 4);
9898 addptr(dst, 8);
9899
9900 bind(copy_bytes);
9901 } else {
9902 bind(below_threshold);
9903 }
9904
9905 testl(len, len);
9906 jccb(Assembler::zero, done);
9907 lea(src, Address(src, len, Address::times_1));
9908 lea(dst, Address(dst, len, Address::times_2));
9909 negptr(len);
9910
9911 // inflate 1 char per iter
9912 bind(copy_chars_loop);
9913 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9914 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9915 increment(len);
9916 jcc(Assembler::notZero, copy_chars_loop);
9917
9918 bind(done);
9919 }
9920
9921 #ifdef _LP64
9922 void MacroAssembler::cache_wb(Address line)
9923 {
9924 // 64 bit cpus always support clflush
9925 assert(VM_Version::supports_clflush(), "clflush should be available");
9926 bool optimized = VM_Version::supports_clflushopt();
9927 bool no_evict = VM_Version::supports_clwb();
9928
9929 // prefer clwb (writeback without evict) otherwise
9930 // prefer clflushopt (potentially parallel writeback with evict)
9931 // otherwise fallback on clflush (serial writeback with evict)
9932
9933 if (optimized) {
9934 if (no_evict) {
9935 clwb(line);
9936 } else {
9937 clflushopt(line);
9938 }
9939 } else {
9940 // no need for fence when using CLFLUSH
9941 clflush(line);
9942 }
9943 }
9944
9945 void MacroAssembler::cache_wbsync(bool is_pre)
9946 {
9947 assert(VM_Version::supports_clflush(), "clflush should be available");
9948 bool optimized = VM_Version::supports_clflushopt();
9949 bool no_evict = VM_Version::supports_clwb();
9950
9951 // pick the correct implementation
9952
9953 if (!is_pre && (optimized || no_evict)) {
9954 // need an sfence for post flush when using clflushopt or clwb
9955 // otherwise no no need for any synchroniaztion
9956
9957 sfence();
9958 }
9959 }
9960 #endif // _LP64
9961
9962 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
9963 switch (cond) {
9964 // Note some conditions are synonyms for others
9965 case Assembler::zero: return Assembler::notZero;
9966 case Assembler::notZero: return Assembler::zero;
9967 case Assembler::less: return Assembler::greaterEqual;
9968 case Assembler::lessEqual: return Assembler::greater;
9969 case Assembler::greater: return Assembler::lessEqual;
9970 case Assembler::greaterEqual: return Assembler::less;
9971 case Assembler::below: return Assembler::aboveEqual;
9972 case Assembler::belowEqual: return Assembler::above;
9973 case Assembler::above: return Assembler::belowEqual;
9974 case Assembler::aboveEqual: return Assembler::below;
9975 case Assembler::overflow: return Assembler::noOverflow;
9976 case Assembler::noOverflow: return Assembler::overflow;
9977 case Assembler::negative: return Assembler::positive;
9978 case Assembler::positive: return Assembler::negative;
9979 case Assembler::parity: return Assembler::noParity;
9980 case Assembler::noParity: return Assembler::parity;
9981 }
9982 ShouldNotReachHere(); return Assembler::overflow;
9983 }
9984
9985 SkipIfEqual::SkipIfEqual(
9986 MacroAssembler* masm, const bool* flag_addr, bool value) {
9987 _masm = masm;
9988 _masm->cmp8(ExternalAddress((address)flag_addr), value);
9989 _masm->jcc(Assembler::equal, _label);
9990 }
9991
9992 SkipIfEqual::~SkipIfEqual() {
9993 _masm->bind(_label);
9994 }
9995
9996 // 32-bit Windows has its own fast-path implementation
9997 // of get_thread
9998 #if !defined(WIN32) || defined(_LP64)
9999
10000 // This is simply a call to Thread::current()
10001 void MacroAssembler::get_thread(Register thread) {
10002 if (thread != rax) {
10003 push(rax);
10004 }
10005 LP64_ONLY(push(rdi);)
10006 LP64_ONLY(push(rsi);)
10007 push(rdx);
10008 push(rcx);
10009 #ifdef _LP64
10010 push(r8);
10011 push(r9);
10012 push(r10);
10013 push(r11);
10014 #endif
10015
10016 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10017
10018 #ifdef _LP64
10019 pop(r11);
10020 pop(r10);
10021 pop(r9);
10022 pop(r8);
10023 #endif
10024 pop(rcx);
10025 pop(rdx);
10026 LP64_ONLY(pop(rsi);)
10027 LP64_ONLY(pop(rdi);)
10028 if (thread != rax) {
10029 mov(thread, rax);
10030 pop(rax);
10031 }
10032 }
10033
10034 #endif