1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "gc/shared/barrierSet.hpp"
31 #include "gc/shared/barrierSetAssembler.hpp"
32 #include "gc/shared/collectedHeap.inline.hpp"
33 #include "interpreter/interpreter.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "memory/universe.hpp"
36 #include "oops/accessDecorators.hpp"
37 #include "oops/compressedOops.inline.hpp"
38 #include "oops/klass.inline.hpp"
39 #include "prims/methodHandles.hpp"
40 #include "runtime/biasedLocking.hpp"
41 #include "runtime/flags/flagSetting.hpp"
42 #include "runtime/interfaceSupport.inline.hpp"
43 #include "runtime/objectMonitor.hpp"
44 #include "runtime/os.hpp"
45 #include "runtime/safepoint.hpp"
46 #include "runtime/safepointMechanism.hpp"
47 #include "runtime/sharedRuntime.hpp"
48 #include "runtime/stubRoutines.hpp"
49 #include "runtime/thread.hpp"
50 #include "utilities/macros.hpp"
51 #include "crc32c.h"
52 #ifdef COMPILER2
53 #include "opto/intrinsicnode.hpp"
54 #endif
55
56 #ifdef PRODUCT
57 #define BLOCK_COMMENT(str) /* nothing */
58 #define STOP(error) stop(error)
59 #else
60 #define BLOCK_COMMENT(str) block_comment(str)
61 #define STOP(error) block_comment(error); stop(error)
62 #endif
63
64 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
65
66 #ifdef ASSERT
67 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
68 #endif
69
70 static Assembler::Condition reverse[] = {
71 Assembler::noOverflow /* overflow = 0x0 */ ,
72 Assembler::overflow /* noOverflow = 0x1 */ ,
73 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
74 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
75 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
76 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
77 Assembler::above /* belowEqual = 0x6 */ ,
78 Assembler::belowEqual /* above = 0x7 */ ,
79 Assembler::positive /* negative = 0x8 */ ,
80 Assembler::negative /* positive = 0x9 */ ,
81 Assembler::noParity /* parity = 0xa */ ,
82 Assembler::parity /* noParity = 0xb */ ,
83 Assembler::greaterEqual /* less = 0xc */ ,
84 Assembler::less /* greaterEqual = 0xd */ ,
85 Assembler::greater /* lessEqual = 0xe */ ,
86 Assembler::lessEqual /* greater = 0xf, */
87
88 };
89
90
91 // Implementation of MacroAssembler
92
93 // First all the versions that have distinct versions depending on 32/64 bit
94 // Unless the difference is trivial (1 line or so).
95
96 #ifndef _LP64
97
98 // 32bit versions
99
100 Address MacroAssembler::as_Address(AddressLiteral adr) {
101 return Address(adr.target(), adr.rspec());
102 }
103
104 Address MacroAssembler::as_Address(ArrayAddress adr) {
105 return Address::make_array(adr);
106 }
107
108 void MacroAssembler::call_VM_leaf_base(address entry_point,
109 int number_of_arguments) {
110 call(RuntimeAddress(entry_point));
111 increment(rsp, number_of_arguments * wordSize);
112 }
113
114 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
115 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
116 }
117
118 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
119 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
120 }
121
122 void MacroAssembler::cmpoop_raw(Address src1, jobject obj) {
123 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
124 }
125
126 void MacroAssembler::cmpoop_raw(Register src1, jobject obj) {
127 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
128 }
129
130 void MacroAssembler::cmpoop(Address src1, jobject obj) {
131 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
132 bs->obj_equals(this, src1, obj);
133 }
134
135 void MacroAssembler::cmpoop(Register src1, jobject obj) {
136 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
137 bs->obj_equals(this, src1, obj);
138 }
139
140 void MacroAssembler::extend_sign(Register hi, Register lo) {
141 // According to Intel Doc. AP-526, "Integer Divide", p.18.
142 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
143 cdql();
144 } else {
145 movl(hi, lo);
146 sarl(hi, 31);
147 }
148 }
149
150 void MacroAssembler::jC2(Register tmp, Label& L) {
151 // set parity bit if FPU flag C2 is set (via rax)
152 save_rax(tmp);
153 fwait(); fnstsw_ax();
154 sahf();
155 restore_rax(tmp);
156 // branch
157 jcc(Assembler::parity, L);
158 }
159
160 void MacroAssembler::jnC2(Register tmp, Label& L) {
161 // set parity bit if FPU flag C2 is set (via rax)
162 save_rax(tmp);
163 fwait(); fnstsw_ax();
164 sahf();
165 restore_rax(tmp);
166 // branch
167 jcc(Assembler::noParity, L);
168 }
169
170 // 32bit can do a case table jump in one instruction but we no longer allow the base
171 // to be installed in the Address class
172 void MacroAssembler::jump(ArrayAddress entry) {
173 jmp(as_Address(entry));
174 }
175
176 // Note: y_lo will be destroyed
177 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
178 // Long compare for Java (semantics as described in JVM spec.)
179 Label high, low, done;
180
181 cmpl(x_hi, y_hi);
182 jcc(Assembler::less, low);
183 jcc(Assembler::greater, high);
184 // x_hi is the return register
185 xorl(x_hi, x_hi);
186 cmpl(x_lo, y_lo);
187 jcc(Assembler::below, low);
188 jcc(Assembler::equal, done);
189
190 bind(high);
191 xorl(x_hi, x_hi);
192 increment(x_hi);
193 jmp(done);
194
195 bind(low);
196 xorl(x_hi, x_hi);
197 decrementl(x_hi);
198
199 bind(done);
200 }
201
202 void MacroAssembler::lea(Register dst, AddressLiteral src) {
203 mov_literal32(dst, (int32_t)src.target(), src.rspec());
204 }
205
206 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
207 // leal(dst, as_Address(adr));
208 // see note in movl as to why we must use a move
209 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
210 }
211
212 void MacroAssembler::leave() {
213 mov(rsp, rbp);
214 pop(rbp);
215 }
216
217 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
218 // Multiplication of two Java long values stored on the stack
219 // as illustrated below. Result is in rdx:rax.
220 //
221 // rsp ---> [ ?? ] \ \
222 // .... | y_rsp_offset |
223 // [ y_lo ] / (in bytes) | x_rsp_offset
224 // [ y_hi ] | (in bytes)
225 // .... |
226 // [ x_lo ] /
227 // [ x_hi ]
228 // ....
229 //
230 // Basic idea: lo(result) = lo(x_lo * y_lo)
231 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
232 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
233 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
234 Label quick;
235 // load x_hi, y_hi and check if quick
236 // multiplication is possible
237 movl(rbx, x_hi);
238 movl(rcx, y_hi);
239 movl(rax, rbx);
240 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
241 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
242 // do full multiplication
243 // 1st step
244 mull(y_lo); // x_hi * y_lo
245 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
246 // 2nd step
247 movl(rax, x_lo);
248 mull(rcx); // x_lo * y_hi
249 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
250 // 3rd step
251 bind(quick); // note: rbx, = 0 if quick multiply!
252 movl(rax, x_lo);
253 mull(y_lo); // x_lo * y_lo
254 addl(rdx, rbx); // correct hi(x_lo * y_lo)
255 }
256
257 void MacroAssembler::lneg(Register hi, Register lo) {
258 negl(lo);
259 adcl(hi, 0);
260 negl(hi);
261 }
262
263 void MacroAssembler::lshl(Register hi, Register lo) {
264 // Java shift left long support (semantics as described in JVM spec., p.305)
265 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
266 // shift value is in rcx !
267 assert(hi != rcx, "must not use rcx");
268 assert(lo != rcx, "must not use rcx");
269 const Register s = rcx; // shift count
270 const int n = BitsPerWord;
271 Label L;
272 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
273 cmpl(s, n); // if (s < n)
274 jcc(Assembler::less, L); // else (s >= n)
275 movl(hi, lo); // x := x << n
276 xorl(lo, lo);
277 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
278 bind(L); // s (mod n) < n
279 shldl(hi, lo); // x := x << s
280 shll(lo);
281 }
282
283
284 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
285 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
286 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
287 assert(hi != rcx, "must not use rcx");
288 assert(lo != rcx, "must not use rcx");
289 const Register s = rcx; // shift count
290 const int n = BitsPerWord;
291 Label L;
292 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
293 cmpl(s, n); // if (s < n)
294 jcc(Assembler::less, L); // else (s >= n)
295 movl(lo, hi); // x := x >> n
296 if (sign_extension) sarl(hi, 31);
297 else xorl(hi, hi);
298 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
299 bind(L); // s (mod n) < n
300 shrdl(lo, hi); // x := x >> s
301 if (sign_extension) sarl(hi);
302 else shrl(hi);
303 }
304
305 void MacroAssembler::movoop(Register dst, jobject obj) {
306 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
307 }
308
309 void MacroAssembler::movoop(Address dst, jobject obj) {
310 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
311 }
312
313 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
314 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
315 }
316
317 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
318 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
319 }
320
321 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
322 // scratch register is not used,
323 // it is defined to match parameters of 64-bit version of this method.
324 if (src.is_lval()) {
325 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
326 } else {
327 movl(dst, as_Address(src));
328 }
329 }
330
331 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
332 movl(as_Address(dst), src);
333 }
334
335 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
336 movl(dst, as_Address(src));
337 }
338
339 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
340 void MacroAssembler::movptr(Address dst, intptr_t src) {
341 movl(dst, src);
342 }
343
344
345 void MacroAssembler::pop_callee_saved_registers() {
346 pop(rcx);
347 pop(rdx);
348 pop(rdi);
349 pop(rsi);
350 }
351
352 void MacroAssembler::pop_fTOS() {
353 fld_d(Address(rsp, 0));
354 addl(rsp, 2 * wordSize);
355 }
356
357 void MacroAssembler::push_callee_saved_registers() {
358 push(rsi);
359 push(rdi);
360 push(rdx);
361 push(rcx);
362 }
363
364 void MacroAssembler::push_fTOS() {
365 subl(rsp, 2 * wordSize);
366 fstp_d(Address(rsp, 0));
367 }
368
369
370 void MacroAssembler::pushoop(jobject obj) {
371 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
372 }
373
374 void MacroAssembler::pushklass(Metadata* obj) {
375 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
376 }
377
378 void MacroAssembler::pushptr(AddressLiteral src) {
379 if (src.is_lval()) {
380 push_literal32((int32_t)src.target(), src.rspec());
381 } else {
382 pushl(as_Address(src));
383 }
384 }
385
386 void MacroAssembler::set_word_if_not_zero(Register dst) {
387 xorl(dst, dst);
388 set_byte_if_not_zero(dst);
389 }
390
391 static void pass_arg0(MacroAssembler* masm, Register arg) {
392 masm->push(arg);
393 }
394
395 static void pass_arg1(MacroAssembler* masm, Register arg) {
396 masm->push(arg);
397 }
398
399 static void pass_arg2(MacroAssembler* masm, Register arg) {
400 masm->push(arg);
401 }
402
403 static void pass_arg3(MacroAssembler* masm, Register arg) {
404 masm->push(arg);
405 }
406
407 #ifndef PRODUCT
408 extern "C" void findpc(intptr_t x);
409 #endif
410
411 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
412 // In order to get locks to work, we need to fake a in_VM state
413 JavaThread* thread = JavaThread::current();
414 JavaThreadState saved_state = thread->thread_state();
415 thread->set_thread_state(_thread_in_vm);
416 if (ShowMessageBoxOnError) {
417 JavaThread* thread = JavaThread::current();
418 JavaThreadState saved_state = thread->thread_state();
419 thread->set_thread_state(_thread_in_vm);
420 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
421 ttyLocker ttyl;
422 BytecodeCounter::print();
423 }
424 // To see where a verify_oop failed, get $ebx+40/X for this frame.
425 // This is the value of eip which points to where verify_oop will return.
426 if (os::message_box(msg, "Execution stopped, print registers?")) {
427 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
428 BREAKPOINT;
429 }
430 }
431 fatal("DEBUG MESSAGE: %s", msg);
432 }
433
434 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
435 ttyLocker ttyl;
436 FlagSetting fs(Debugging, true);
437 tty->print_cr("eip = 0x%08x", eip);
438 #ifndef PRODUCT
439 if ((WizardMode || Verbose) && PrintMiscellaneous) {
440 tty->cr();
441 findpc(eip);
442 tty->cr();
443 }
444 #endif
445 #define PRINT_REG(rax) \
446 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
447 PRINT_REG(rax);
448 PRINT_REG(rbx);
449 PRINT_REG(rcx);
450 PRINT_REG(rdx);
451 PRINT_REG(rdi);
452 PRINT_REG(rsi);
453 PRINT_REG(rbp);
454 PRINT_REG(rsp);
455 #undef PRINT_REG
456 // Print some words near top of staack.
457 int* dump_sp = (int*) rsp;
458 for (int col1 = 0; col1 < 8; col1++) {
459 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
460 os::print_location(tty, *dump_sp++);
461 }
462 for (int row = 0; row < 16; row++) {
463 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
464 for (int col = 0; col < 8; col++) {
465 tty->print(" 0x%08x", *dump_sp++);
466 }
467 tty->cr();
468 }
469 // Print some instructions around pc:
470 Disassembler::decode((address)eip-64, (address)eip);
471 tty->print_cr("--------");
472 Disassembler::decode((address)eip, (address)eip+32);
473 }
474
475 void MacroAssembler::stop(const char* msg) {
476 ExternalAddress message((address)msg);
477 // push address of message
478 pushptr(message.addr());
479 { Label L; call(L, relocInfo::none); bind(L); } // push eip
480 pusha(); // push registers
481 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
482 hlt();
483 }
484
485 void MacroAssembler::warn(const char* msg) {
486 push_CPU_state();
487
488 ExternalAddress message((address) msg);
489 // push address of message
490 pushptr(message.addr());
491
492 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
493 addl(rsp, wordSize); // discard argument
494 pop_CPU_state();
495 }
496
497 void MacroAssembler::print_state() {
498 { Label L; call(L, relocInfo::none); bind(L); } // push eip
499 pusha(); // push registers
500
501 push_CPU_state();
502 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
503 pop_CPU_state();
504
505 popa();
506 addl(rsp, wordSize);
507 }
508
509 #else // _LP64
510
511 // 64 bit versions
512
513 Address MacroAssembler::as_Address(AddressLiteral adr) {
514 // amd64 always does this as a pc-rel
515 // we can be absolute or disp based on the instruction type
516 // jmp/call are displacements others are absolute
517 assert(!adr.is_lval(), "must be rval");
518 assert(reachable(adr), "must be");
519 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
520
521 }
522
523 Address MacroAssembler::as_Address(ArrayAddress adr) {
524 AddressLiteral base = adr.base();
525 lea(rscratch1, base);
526 Address index = adr.index();
527 assert(index._disp == 0, "must not have disp"); // maybe it can?
528 Address array(rscratch1, index._index, index._scale, index._disp);
529 return array;
530 }
531
532 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
533 Label L, E;
534
535 #ifdef _WIN64
536 // Windows always allocates space for it's register args
537 assert(num_args <= 4, "only register arguments supported");
538 subq(rsp, frame::arg_reg_save_area_bytes);
539 #endif
540
541 // Align stack if necessary
542 testl(rsp, 15);
543 jcc(Assembler::zero, L);
544
545 subq(rsp, 8);
546 {
547 call(RuntimeAddress(entry_point));
548 }
549 addq(rsp, 8);
550 jmp(E);
551
552 bind(L);
553 {
554 call(RuntimeAddress(entry_point));
555 }
556
557 bind(E);
558
559 #ifdef _WIN64
560 // restore stack pointer
561 addq(rsp, frame::arg_reg_save_area_bytes);
562 #endif
563
564 }
565
566 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
567 assert(!src2.is_lval(), "should use cmpptr");
568
569 if (reachable(src2)) {
570 cmpq(src1, as_Address(src2));
571 } else {
572 lea(rscratch1, src2);
573 Assembler::cmpq(src1, Address(rscratch1, 0));
574 }
575 }
576
577 int MacroAssembler::corrected_idivq(Register reg) {
578 // Full implementation of Java ldiv and lrem; checks for special
579 // case as described in JVM spec., p.243 & p.271. The function
580 // returns the (pc) offset of the idivl instruction - may be needed
581 // for implicit exceptions.
582 //
583 // normal case special case
584 //
585 // input : rax: dividend min_long
586 // reg: divisor (may not be eax/edx) -1
587 //
588 // output: rax: quotient (= rax idiv reg) min_long
589 // rdx: remainder (= rax irem reg) 0
590 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
591 static const int64_t min_long = 0x8000000000000000;
592 Label normal_case, special_case;
593
594 // check for special case
595 cmp64(rax, ExternalAddress((address) &min_long));
596 jcc(Assembler::notEqual, normal_case);
597 xorl(rdx, rdx); // prepare rdx for possible special case (where
598 // remainder = 0)
599 cmpq(reg, -1);
600 jcc(Assembler::equal, special_case);
601
602 // handle normal case
603 bind(normal_case);
604 cdqq();
605 int idivq_offset = offset();
606 idivq(reg);
607
608 // normal and special case exit
609 bind(special_case);
610
611 return idivq_offset;
612 }
613
614 void MacroAssembler::decrementq(Register reg, int value) {
615 if (value == min_jint) { subq(reg, value); return; }
616 if (value < 0) { incrementq(reg, -value); return; }
617 if (value == 0) { ; return; }
618 if (value == 1 && UseIncDec) { decq(reg) ; return; }
619 /* else */ { subq(reg, value) ; return; }
620 }
621
622 void MacroAssembler::decrementq(Address dst, int value) {
623 if (value == min_jint) { subq(dst, value); return; }
624 if (value < 0) { incrementq(dst, -value); return; }
625 if (value == 0) { ; return; }
626 if (value == 1 && UseIncDec) { decq(dst) ; return; }
627 /* else */ { subq(dst, value) ; return; }
628 }
629
630 void MacroAssembler::incrementq(AddressLiteral dst) {
631 if (reachable(dst)) {
632 incrementq(as_Address(dst));
633 } else {
634 lea(rscratch1, dst);
635 incrementq(Address(rscratch1, 0));
636 }
637 }
638
639 void MacroAssembler::incrementq(Register reg, int value) {
640 if (value == min_jint) { addq(reg, value); return; }
641 if (value < 0) { decrementq(reg, -value); return; }
642 if (value == 0) { ; return; }
643 if (value == 1 && UseIncDec) { incq(reg) ; return; }
644 /* else */ { addq(reg, value) ; return; }
645 }
646
647 void MacroAssembler::incrementq(Address dst, int value) {
648 if (value == min_jint) { addq(dst, value); return; }
649 if (value < 0) { decrementq(dst, -value); return; }
650 if (value == 0) { ; return; }
651 if (value == 1 && UseIncDec) { incq(dst) ; return; }
652 /* else */ { addq(dst, value) ; return; }
653 }
654
655 // 32bit can do a case table jump in one instruction but we no longer allow the base
656 // to be installed in the Address class
657 void MacroAssembler::jump(ArrayAddress entry) {
658 lea(rscratch1, entry.base());
659 Address dispatch = entry.index();
660 assert(dispatch._base == noreg, "must be");
661 dispatch._base = rscratch1;
662 jmp(dispatch);
663 }
664
665 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
666 ShouldNotReachHere(); // 64bit doesn't use two regs
667 cmpq(x_lo, y_lo);
668 }
669
670 void MacroAssembler::lea(Register dst, AddressLiteral src) {
671 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
672 }
673
674 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
675 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
676 movptr(dst, rscratch1);
677 }
678
679 void MacroAssembler::leave() {
680 // %%% is this really better? Why not on 32bit too?
681 emit_int8((unsigned char)0xC9); // LEAVE
682 }
683
684 void MacroAssembler::lneg(Register hi, Register lo) {
685 ShouldNotReachHere(); // 64bit doesn't use two regs
686 negq(lo);
687 }
688
689 void MacroAssembler::movoop(Register dst, jobject obj) {
690 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
691 }
692
693 void MacroAssembler::movoop(Address dst, jobject obj) {
694 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
695 movq(dst, rscratch1);
696 }
697
698 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
699 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
700 }
701
702 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
703 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
704 movq(dst, rscratch1);
705 }
706
707 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
708 if (src.is_lval()) {
709 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
710 } else {
711 if (reachable(src)) {
712 movq(dst, as_Address(src));
713 } else {
714 lea(scratch, src);
715 movq(dst, Address(scratch, 0));
716 }
717 }
718 }
719
720 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
721 movq(as_Address(dst), src);
722 }
723
724 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
725 movq(dst, as_Address(src));
726 }
727
728 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
729 void MacroAssembler::movptr(Address dst, intptr_t src) {
730 mov64(rscratch1, src);
731 movq(dst, rscratch1);
732 }
733
734 // These are mostly for initializing NULL
735 void MacroAssembler::movptr(Address dst, int32_t src) {
736 movslq(dst, src);
737 }
738
739 void MacroAssembler::movptr(Register dst, int32_t src) {
740 mov64(dst, (intptr_t)src);
741 }
742
743 void MacroAssembler::pushoop(jobject obj) {
744 movoop(rscratch1, obj);
745 push(rscratch1);
746 }
747
748 void MacroAssembler::pushklass(Metadata* obj) {
749 mov_metadata(rscratch1, obj);
750 push(rscratch1);
751 }
752
753 void MacroAssembler::pushptr(AddressLiteral src) {
754 lea(rscratch1, src);
755 if (src.is_lval()) {
756 push(rscratch1);
757 } else {
758 pushq(Address(rscratch1, 0));
759 }
760 }
761
762 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
763 // we must set sp to zero to clear frame
764 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
765 // must clear fp, so that compiled frames are not confused; it is
766 // possible that we need it only for debugging
767 if (clear_fp) {
768 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
769 }
770
771 // Always clear the pc because it could have been set by make_walkable()
772 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
773 vzeroupper();
774 }
775
776 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
777 Register last_java_fp,
778 address last_java_pc) {
779 vzeroupper();
780 // determine last_java_sp register
781 if (!last_java_sp->is_valid()) {
782 last_java_sp = rsp;
783 }
784
785 // last_java_fp is optional
786 if (last_java_fp->is_valid()) {
787 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
788 last_java_fp);
789 }
790
791 // last_java_pc is optional
792 if (last_java_pc != NULL) {
793 Address java_pc(r15_thread,
794 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
795 lea(rscratch1, InternalAddress(last_java_pc));
796 movptr(java_pc, rscratch1);
797 }
798
799 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
800 }
801
802 static void pass_arg0(MacroAssembler* masm, Register arg) {
803 if (c_rarg0 != arg ) {
804 masm->mov(c_rarg0, arg);
805 }
806 }
807
808 static void pass_arg1(MacroAssembler* masm, Register arg) {
809 if (c_rarg1 != arg ) {
810 masm->mov(c_rarg1, arg);
811 }
812 }
813
814 static void pass_arg2(MacroAssembler* masm, Register arg) {
815 if (c_rarg2 != arg ) {
816 masm->mov(c_rarg2, arg);
817 }
818 }
819
820 static void pass_arg3(MacroAssembler* masm, Register arg) {
821 if (c_rarg3 != arg ) {
822 masm->mov(c_rarg3, arg);
823 }
824 }
825
826 void MacroAssembler::stop(const char* msg) {
827 if (ShowMessageBoxOnError) {
828 address rip = pc();
829 pusha(); // get regs on stack
830 lea(c_rarg1, InternalAddress(rip));
831 movq(c_rarg2, rsp); // pass pointer to regs array
832 }
833 lea(c_rarg0, ExternalAddress((address) msg));
834 andq(rsp, -16); // align stack as required by ABI
835 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
836 hlt();
837 }
838
839 void MacroAssembler::warn(const char* msg) {
840 push(rbp);
841 movq(rbp, rsp);
842 andq(rsp, -16); // align stack as required by push_CPU_state and call
843 push_CPU_state(); // keeps alignment at 16 bytes
844 lea(c_rarg0, ExternalAddress((address) msg));
845 lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
846 call(rax);
847 pop_CPU_state();
848 mov(rsp, rbp);
849 pop(rbp);
850 }
851
852 void MacroAssembler::print_state() {
853 address rip = pc();
854 pusha(); // get regs on stack
855 push(rbp);
856 movq(rbp, rsp);
857 andq(rsp, -16); // align stack as required by push_CPU_state and call
858 push_CPU_state(); // keeps alignment at 16 bytes
859
860 lea(c_rarg0, InternalAddress(rip));
861 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
862 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
863
864 pop_CPU_state();
865 mov(rsp, rbp);
866 pop(rbp);
867 popa();
868 }
869
870 #ifndef PRODUCT
871 extern "C" void findpc(intptr_t x);
872 #endif
873
874 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
875 // In order to get locks to work, we need to fake a in_VM state
876 if (ShowMessageBoxOnError) {
877 JavaThread* thread = JavaThread::current();
878 JavaThreadState saved_state = thread->thread_state();
879 thread->set_thread_state(_thread_in_vm);
880 #ifndef PRODUCT
881 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
882 ttyLocker ttyl;
883 BytecodeCounter::print();
884 }
885 #endif
886 // To see where a verify_oop failed, get $ebx+40/X for this frame.
887 // XXX correct this offset for amd64
888 // This is the value of eip which points to where verify_oop will return.
889 if (os::message_box(msg, "Execution stopped, print registers?")) {
890 print_state64(pc, regs);
891 BREAKPOINT;
892 }
893 }
894 fatal("DEBUG MESSAGE: %s", msg);
895 }
896
897 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
898 ttyLocker ttyl;
899 FlagSetting fs(Debugging, true);
900 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
901 #ifndef PRODUCT
902 tty->cr();
903 findpc(pc);
904 tty->cr();
905 #endif
906 #define PRINT_REG(rax, value) \
907 { tty->print("%s = ", #rax); os::print_location(tty, value); }
908 PRINT_REG(rax, regs[15]);
909 PRINT_REG(rbx, regs[12]);
910 PRINT_REG(rcx, regs[14]);
911 PRINT_REG(rdx, regs[13]);
912 PRINT_REG(rdi, regs[8]);
913 PRINT_REG(rsi, regs[9]);
914 PRINT_REG(rbp, regs[10]);
915 PRINT_REG(rsp, regs[11]);
916 PRINT_REG(r8 , regs[7]);
917 PRINT_REG(r9 , regs[6]);
918 PRINT_REG(r10, regs[5]);
919 PRINT_REG(r11, regs[4]);
920 PRINT_REG(r12, regs[3]);
921 PRINT_REG(r13, regs[2]);
922 PRINT_REG(r14, regs[1]);
923 PRINT_REG(r15, regs[0]);
924 #undef PRINT_REG
925 // Print some words near top of staack.
926 int64_t* rsp = (int64_t*) regs[11];
927 int64_t* dump_sp = rsp;
928 for (int col1 = 0; col1 < 8; col1++) {
929 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
930 os::print_location(tty, *dump_sp++);
931 }
932 for (int row = 0; row < 25; row++) {
933 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
934 for (int col = 0; col < 4; col++) {
935 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
936 }
937 tty->cr();
938 }
939 // Print some instructions around pc:
940 Disassembler::decode((address)pc-64, (address)pc);
941 tty->print_cr("--------");
942 Disassembler::decode((address)pc, (address)pc+32);
943 }
944
945 #endif // _LP64
946
947 // Now versions that are common to 32/64 bit
948
949 void MacroAssembler::addptr(Register dst, int32_t imm32) {
950 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
951 }
952
953 void MacroAssembler::addptr(Register dst, Register src) {
954 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
955 }
956
957 void MacroAssembler::addptr(Address dst, Register src) {
958 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
959 }
960
961 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
962 if (reachable(src)) {
963 Assembler::addsd(dst, as_Address(src));
964 } else {
965 lea(rscratch1, src);
966 Assembler::addsd(dst, Address(rscratch1, 0));
967 }
968 }
969
970 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
971 if (reachable(src)) {
972 addss(dst, as_Address(src));
973 } else {
974 lea(rscratch1, src);
975 addss(dst, Address(rscratch1, 0));
976 }
977 }
978
979 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
980 if (reachable(src)) {
981 Assembler::addpd(dst, as_Address(src));
982 } else {
983 lea(rscratch1, src);
984 Assembler::addpd(dst, Address(rscratch1, 0));
985 }
986 }
987
988 void MacroAssembler::align(int modulus) {
989 align(modulus, offset());
990 }
991
992 void MacroAssembler::align(int modulus, int target) {
993 if (target % modulus != 0) {
994 nop(modulus - (target % modulus));
995 }
996 }
997
998 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
999 // Used in sign-masking with aligned address.
1000 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1001 if (reachable(src)) {
1002 Assembler::andpd(dst, as_Address(src));
1003 } else {
1004 lea(scratch_reg, src);
1005 Assembler::andpd(dst, Address(scratch_reg, 0));
1006 }
1007 }
1008
1009 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1010 // Used in sign-masking with aligned address.
1011 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1012 if (reachable(src)) {
1013 Assembler::andps(dst, as_Address(src));
1014 } else {
1015 lea(scratch_reg, src);
1016 Assembler::andps(dst, Address(scratch_reg, 0));
1017 }
1018 }
1019
1020 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1021 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1022 }
1023
1024 void MacroAssembler::atomic_incl(Address counter_addr) {
1025 lock();
1026 incrementl(counter_addr);
1027 }
1028
1029 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1030 if (reachable(counter_addr)) {
1031 atomic_incl(as_Address(counter_addr));
1032 } else {
1033 lea(scr, counter_addr);
1034 atomic_incl(Address(scr, 0));
1035 }
1036 }
1037
1038 #ifdef _LP64
1039 void MacroAssembler::atomic_incq(Address counter_addr) {
1040 lock();
1041 incrementq(counter_addr);
1042 }
1043
1044 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1045 if (reachable(counter_addr)) {
1046 atomic_incq(as_Address(counter_addr));
1047 } else {
1048 lea(scr, counter_addr);
1049 atomic_incq(Address(scr, 0));
1050 }
1051 }
1052 #endif
1053
1054 // Writes to stack successive pages until offset reached to check for
1055 // stack overflow + shadow pages. This clobbers tmp.
1056 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1057 movptr(tmp, rsp);
1058 // Bang stack for total size given plus shadow page size.
1059 // Bang one page at a time because large size can bang beyond yellow and
1060 // red zones.
1061 Label loop;
1062 bind(loop);
1063 movl(Address(tmp, (-os::vm_page_size())), size );
1064 subptr(tmp, os::vm_page_size());
1065 subl(size, os::vm_page_size());
1066 jcc(Assembler::greater, loop);
1067
1068 // Bang down shadow pages too.
1069 // At this point, (tmp-0) is the last address touched, so don't
1070 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1071 // was post-decremented.) Skip this address by starting at i=1, and
1072 // touch a few more pages below. N.B. It is important to touch all
1073 // the way down including all pages in the shadow zone.
1074 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1075 // this could be any sized move but this is can be a debugging crumb
1076 // so the bigger the better.
1077 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1078 }
1079 }
1080
1081 void MacroAssembler::reserved_stack_check() {
1082 // testing if reserved zone needs to be enabled
1083 Label no_reserved_zone_enabling;
1084 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1085 NOT_LP64(get_thread(rsi);)
1086
1087 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1088 jcc(Assembler::below, no_reserved_zone_enabling);
1089
1090 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1091 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1092 should_not_reach_here();
1093
1094 bind(no_reserved_zone_enabling);
1095 }
1096
1097 int MacroAssembler::biased_locking_enter(Register lock_reg,
1098 Register obj_reg,
1099 Register swap_reg,
1100 Register tmp_reg,
1101 bool swap_reg_contains_mark,
1102 Label& done,
1103 Label* slow_case,
1104 BiasedLockingCounters* counters) {
1105 assert(UseBiasedLocking, "why call this otherwise?");
1106 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1107 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1108 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1109 assert(markWord::age_shift == markWord::lock_bits + markWord::biased_lock_bits, "biased locking makes assumptions about bit layout");
1110 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1111 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1112
1113 if (PrintBiasedLockingStatistics && counters == NULL) {
1114 counters = BiasedLocking::counters();
1115 }
1116 // Biased locking
1117 // See whether the lock is currently biased toward our thread and
1118 // whether the epoch is still valid
1119 // Note that the runtime guarantees sufficient alignment of JavaThread
1120 // pointers to allow age to be placed into low bits
1121 // First check to see whether biasing is even enabled for this object
1122 Label cas_label;
1123 int null_check_offset = -1;
1124 if (!swap_reg_contains_mark) {
1125 null_check_offset = offset();
1126 movptr(swap_reg, mark_addr);
1127 }
1128 movptr(tmp_reg, swap_reg);
1129 andptr(tmp_reg, markWord::biased_lock_mask_in_place);
1130 cmpptr(tmp_reg, markWord::biased_lock_pattern);
1131 jcc(Assembler::notEqual, cas_label);
1132 // The bias pattern is present in the object's header. Need to check
1133 // whether the bias owner and the epoch are both still current.
1134 #ifndef _LP64
1135 // Note that because there is no current thread register on x86_32 we
1136 // need to store off the mark word we read out of the object to
1137 // avoid reloading it and needing to recheck invariants below. This
1138 // store is unfortunate but it makes the overall code shorter and
1139 // simpler.
1140 movptr(saved_mark_addr, swap_reg);
1141 #endif
1142 if (swap_reg_contains_mark) {
1143 null_check_offset = offset();
1144 }
1145 load_prototype_header(tmp_reg, obj_reg);
1146 #ifdef _LP64
1147 orptr(tmp_reg, r15_thread);
1148 xorptr(tmp_reg, swap_reg);
1149 Register header_reg = tmp_reg;
1150 #else
1151 xorptr(tmp_reg, swap_reg);
1152 get_thread(swap_reg);
1153 xorptr(swap_reg, tmp_reg);
1154 Register header_reg = swap_reg;
1155 #endif
1156 andptr(header_reg, ~((int) markWord::age_mask_in_place));
1157 if (counters != NULL) {
1158 cond_inc32(Assembler::zero,
1159 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1160 }
1161 jcc(Assembler::equal, done);
1162
1163 Label try_revoke_bias;
1164 Label try_rebias;
1165
1166 // At this point we know that the header has the bias pattern and
1167 // that we are not the bias owner in the current epoch. We need to
1168 // figure out more details about the state of the header in order to
1169 // know what operations can be legally performed on the object's
1170 // header.
1171
1172 // If the low three bits in the xor result aren't clear, that means
1173 // the prototype header is no longer biased and we have to revoke
1174 // the bias on this object.
1175 testptr(header_reg, markWord::biased_lock_mask_in_place);
1176 jccb(Assembler::notZero, try_revoke_bias);
1177
1178 // Biasing is still enabled for this data type. See whether the
1179 // epoch of the current bias is still valid, meaning that the epoch
1180 // bits of the mark word are equal to the epoch bits of the
1181 // prototype header. (Note that the prototype header's epoch bits
1182 // only change at a safepoint.) If not, attempt to rebias the object
1183 // toward the current thread. Note that we must be absolutely sure
1184 // that the current epoch is invalid in order to do this because
1185 // otherwise the manipulations it performs on the mark word are
1186 // illegal.
1187 testptr(header_reg, markWord::epoch_mask_in_place);
1188 jccb(Assembler::notZero, try_rebias);
1189
1190 // The epoch of the current bias is still valid but we know nothing
1191 // about the owner; it might be set or it might be clear. Try to
1192 // acquire the bias of the object using an atomic operation. If this
1193 // fails we will go in to the runtime to revoke the object's bias.
1194 // Note that we first construct the presumed unbiased header so we
1195 // don't accidentally blow away another thread's valid bias.
1196 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1197 andptr(swap_reg,
1198 markWord::biased_lock_mask_in_place | markWord::age_mask_in_place | markWord::epoch_mask_in_place);
1199 #ifdef _LP64
1200 movptr(tmp_reg, swap_reg);
1201 orptr(tmp_reg, r15_thread);
1202 #else
1203 get_thread(tmp_reg);
1204 orptr(tmp_reg, swap_reg);
1205 #endif
1206 lock();
1207 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1208 // If the biasing toward our thread failed, this means that
1209 // another thread succeeded in biasing it toward itself and we
1210 // need to revoke that bias. The revocation will occur in the
1211 // interpreter runtime in the slow case.
1212 if (counters != NULL) {
1213 cond_inc32(Assembler::zero,
1214 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1215 }
1216 if (slow_case != NULL) {
1217 jcc(Assembler::notZero, *slow_case);
1218 }
1219 jmp(done);
1220
1221 bind(try_rebias);
1222 // At this point we know the epoch has expired, meaning that the
1223 // current "bias owner", if any, is actually invalid. Under these
1224 // circumstances _only_, we are allowed to use the current header's
1225 // value as the comparison value when doing the cas to acquire the
1226 // bias in the current epoch. In other words, we allow transfer of
1227 // the bias from one thread to another directly in this situation.
1228 //
1229 // FIXME: due to a lack of registers we currently blow away the age
1230 // bits in this situation. Should attempt to preserve them.
1231 load_prototype_header(tmp_reg, obj_reg);
1232 #ifdef _LP64
1233 orptr(tmp_reg, r15_thread);
1234 #else
1235 get_thread(swap_reg);
1236 orptr(tmp_reg, swap_reg);
1237 movptr(swap_reg, saved_mark_addr);
1238 #endif
1239 lock();
1240 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1241 // If the biasing toward our thread failed, then another thread
1242 // succeeded in biasing it toward itself and we need to revoke that
1243 // bias. The revocation will occur in the runtime in the slow case.
1244 if (counters != NULL) {
1245 cond_inc32(Assembler::zero,
1246 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1247 }
1248 if (slow_case != NULL) {
1249 jcc(Assembler::notZero, *slow_case);
1250 }
1251 jmp(done);
1252
1253 bind(try_revoke_bias);
1254 // The prototype mark in the klass doesn't have the bias bit set any
1255 // more, indicating that objects of this data type are not supposed
1256 // to be biased any more. We are going to try to reset the mark of
1257 // this object to the prototype value and fall through to the
1258 // CAS-based locking scheme. Note that if our CAS fails, it means
1259 // that another thread raced us for the privilege of revoking the
1260 // bias of this particular object, so it's okay to continue in the
1261 // normal locking code.
1262 //
1263 // FIXME: due to a lack of registers we currently blow away the age
1264 // bits in this situation. Should attempt to preserve them.
1265 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1266 load_prototype_header(tmp_reg, obj_reg);
1267 lock();
1268 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1269 // Fall through to the normal CAS-based lock, because no matter what
1270 // the result of the above CAS, some thread must have succeeded in
1271 // removing the bias bit from the object's header.
1272 if (counters != NULL) {
1273 cond_inc32(Assembler::zero,
1274 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1275 }
1276
1277 bind(cas_label);
1278
1279 return null_check_offset;
1280 }
1281
1282 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1283 assert(UseBiasedLocking, "why call this otherwise?");
1284
1285 // Check for biased locking unlock case, which is a no-op
1286 // Note: we do not have to check the thread ID for two reasons.
1287 // First, the interpreter checks for IllegalMonitorStateException at
1288 // a higher level. Second, if the bias was revoked while we held the
1289 // lock, the object could not be rebiased toward another thread, so
1290 // the bias bit would be clear.
1291 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1292 andptr(temp_reg, markWord::biased_lock_mask_in_place);
1293 cmpptr(temp_reg, markWord::biased_lock_pattern);
1294 jcc(Assembler::equal, done);
1295 }
1296
1297 #ifdef COMPILER2
1298
1299 // Increment the ObjectMonitor's ref_count for safety or force a branch
1300 // to 'done' with ICC.ZF=0 to indicate failure/take the slow path.
1301 void MacroAssembler::inc_om_ref_count(Register obj_reg, Register om_reg, Register tmp_reg, Label& done) {
1302 atomic_incl(Address(om_reg, OM_OFFSET_NO_MONITOR_VALUE_TAG(ref_count)));
1303
1304 Label LGoSlowPath;
1305 if (AsyncDeflateIdleMonitors) {
1306 // Race here if monitor is not owned! The above ref_count bump
1307 // will cause subsequent async deflation to skip it. However,
1308 // previous or concurrent async deflation is a race.
1309
1310 // First check: if the owner field == DEFLATER_MARKER:
1311 movptr(tmp_reg, Address(om_reg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1312 // DEFLATER_MARKER == reinterpret_cast<void*>(-1) so the compiler
1313 // doesn't like to use the define here:
1314 cmpptr(tmp_reg, -1);
1315 // If marked for async deflation, then take the slow path. This is a
1316 // simpler check than what ObjectMonitorHandle::save_om_ptr() does
1317 // so ObjectMonitor::install_displaced_markword_in_object() doesn't
1318 // have to be implemented in macro assembler.
1319 jccb(Assembler::equal, LGoSlowPath);
1320
1321 // Second check: if ref_count field <= 0:
1322 movptr(tmp_reg, Address(om_reg, OM_OFFSET_NO_MONITOR_VALUE_TAG(ref_count)));
1323 cmpptr(tmp_reg, 0);
1324 // If async deflation is in the process of bailing out, but has not
1325 // yet restored the ref_count field, then we take the slow path. We
1326 // want a stable ref_count value for the fast path.
1327 jccb(Assembler::lessEqual, LGoSlowPath);
1328
1329 // Final check: if object field == obj_reg:
1330 cmpptr(obj_reg, Address(om_reg, OM_OFFSET_NO_MONITOR_VALUE_TAG(object)));
1331 // If the ObjectMonitor has been deflated and recycled, then take
1332 // the slow path.
1333 jccb(Assembler::notEqual, LGoSlowPath);
1334 }
1335
1336 Label LRetToCaller;
1337 // We leave the ref_count incremented to protect the caller's code
1338 // paths against async deflation.
1339 jmpb(LRetToCaller);
1340
1341 bind(LGoSlowPath);
1342 lock();
1343 decrementl(Address(om_reg, OM_OFFSET_NO_MONITOR_VALUE_TAG(ref_count)));
1344 // Jump to 'done' with ICC.ZF=0 to indicate failure/take the slow path.
1345 orl(tmp_reg, 1);
1346 jmp(done);
1347
1348 bind(LRetToCaller);
1349 }
1350
1351 #if INCLUDE_RTM_OPT
1352
1353 // Update rtm_counters based on abort status
1354 // input: abort_status
1355 // rtm_counters (RTMLockingCounters*)
1356 // flags are killed
1357 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1358
1359 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1360 if (PrintPreciseRTMLockingStatistics) {
1361 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1362 Label check_abort;
1363 testl(abort_status, (1<<i));
1364 jccb(Assembler::equal, check_abort);
1365 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1366 bind(check_abort);
1367 }
1368 }
1369 }
1370
1371 // Branch if (random & (count-1) != 0), count is 2^n
1372 // tmp, scr and flags are killed
1373 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1374 assert(tmp == rax, "");
1375 assert(scr == rdx, "");
1376 rdtsc(); // modifies EDX:EAX
1377 andptr(tmp, count-1);
1378 jccb(Assembler::notZero, brLabel);
1379 }
1380
1381 // Perform abort ratio calculation, set no_rtm bit if high ratio
1382 // input: rtm_counters_Reg (RTMLockingCounters* address)
1383 // tmpReg, rtm_counters_Reg and flags are killed
1384 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1385 Register rtm_counters_Reg,
1386 RTMLockingCounters* rtm_counters,
1387 Metadata* method_data) {
1388 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1389
1390 if (RTMLockingCalculationDelay > 0) {
1391 // Delay calculation
1392 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1393 testptr(tmpReg, tmpReg);
1394 jccb(Assembler::equal, L_done);
1395 }
1396 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1397 // Aborted transactions = abort_count * 100
1398 // All transactions = total_count * RTMTotalCountIncrRate
1399 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1400
1401 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1402 cmpptr(tmpReg, RTMAbortThreshold);
1403 jccb(Assembler::below, L_check_always_rtm2);
1404 imulptr(tmpReg, tmpReg, 100);
1405
1406 Register scrReg = rtm_counters_Reg;
1407 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1408 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1409 imulptr(scrReg, scrReg, RTMAbortRatio);
1410 cmpptr(tmpReg, scrReg);
1411 jccb(Assembler::below, L_check_always_rtm1);
1412 if (method_data != NULL) {
1413 // set rtm_state to "no rtm" in MDO
1414 mov_metadata(tmpReg, method_data);
1415 lock();
1416 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1417 }
1418 jmpb(L_done);
1419 bind(L_check_always_rtm1);
1420 // Reload RTMLockingCounters* address
1421 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1422 bind(L_check_always_rtm2);
1423 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1424 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1425 jccb(Assembler::below, L_done);
1426 if (method_data != NULL) {
1427 // set rtm_state to "always rtm" in MDO
1428 mov_metadata(tmpReg, method_data);
1429 lock();
1430 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1431 }
1432 bind(L_done);
1433 }
1434
1435 // Update counters and perform abort ratio calculation
1436 // input: abort_status_Reg
1437 // rtm_counters_Reg, flags are killed
1438 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1439 Register rtm_counters_Reg,
1440 RTMLockingCounters* rtm_counters,
1441 Metadata* method_data,
1442 bool profile_rtm) {
1443
1444 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1445 // update rtm counters based on rax value at abort
1446 // reads abort_status_Reg, updates flags
1447 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1448 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1449 if (profile_rtm) {
1450 // Save abort status because abort_status_Reg is used by following code.
1451 if (RTMRetryCount > 0) {
1452 push(abort_status_Reg);
1453 }
1454 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1455 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1456 // restore abort status
1457 if (RTMRetryCount > 0) {
1458 pop(abort_status_Reg);
1459 }
1460 }
1461 }
1462
1463 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1464 // inputs: retry_count_Reg
1465 // : abort_status_Reg
1466 // output: retry_count_Reg decremented by 1
1467 // flags are killed
1468 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1469 Label doneRetry;
1470 assert(abort_status_Reg == rax, "");
1471 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1472 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1473 // if reason is in 0x6 and retry count != 0 then retry
1474 andptr(abort_status_Reg, 0x6);
1475 jccb(Assembler::zero, doneRetry);
1476 testl(retry_count_Reg, retry_count_Reg);
1477 jccb(Assembler::zero, doneRetry);
1478 pause();
1479 decrementl(retry_count_Reg);
1480 jmp(retryLabel);
1481 bind(doneRetry);
1482 }
1483
1484 // Spin and retry if lock is busy,
1485 // inputs: box_Reg (monitor address)
1486 // : retry_count_Reg
1487 // output: retry_count_Reg decremented by 1
1488 // : clear z flag if retry count exceeded
1489 // tmp_Reg, scr_Reg, flags are killed
1490 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1491 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1492 Label SpinLoop, SpinExit, doneRetry;
1493 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1494
1495 testl(retry_count_Reg, retry_count_Reg);
1496 jccb(Assembler::zero, doneRetry);
1497 decrementl(retry_count_Reg);
1498 movptr(scr_Reg, RTMSpinLoopCount);
1499
1500 bind(SpinLoop);
1501 pause();
1502 decrementl(scr_Reg);
1503 jccb(Assembler::lessEqual, SpinExit);
1504 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1505 testptr(tmp_Reg, tmp_Reg);
1506 jccb(Assembler::notZero, SpinLoop);
1507
1508 bind(SpinExit);
1509 jmp(retryLabel);
1510 bind(doneRetry);
1511 incrementl(retry_count_Reg); // clear z flag
1512 }
1513
1514 // Use RTM for normal stack locks
1515 // Input: objReg (object to lock)
1516 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1517 Register retry_on_abort_count_Reg,
1518 RTMLockingCounters* stack_rtm_counters,
1519 Metadata* method_data, bool profile_rtm,
1520 Label& DONE_LABEL, Label& IsInflated) {
1521 assert(UseRTMForStackLocks, "why call this otherwise?");
1522 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1523 assert(tmpReg == rax, "");
1524 assert(scrReg == rdx, "");
1525 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1526
1527 if (RTMRetryCount > 0) {
1528 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1529 bind(L_rtm_retry);
1530 }
1531 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1532 testptr(tmpReg, markWord::monitor_value); // inflated vs stack-locked|neutral|biased
1533 jcc(Assembler::notZero, IsInflated);
1534
1535 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1536 Label L_noincrement;
1537 if (RTMTotalCountIncrRate > 1) {
1538 // tmpReg, scrReg and flags are killed
1539 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1540 }
1541 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1542 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1543 bind(L_noincrement);
1544 }
1545 xbegin(L_on_abort);
1546 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1547 andptr(tmpReg, markWord::biased_lock_mask_in_place); // look at 3 lock bits
1548 cmpptr(tmpReg, markWord::unlocked_value); // bits = 001 unlocked
1549 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1550
1551 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1552 if (UseRTMXendForLockBusy) {
1553 xend();
1554 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1555 jmp(L_decrement_retry);
1556 }
1557 else {
1558 xabort(0);
1559 }
1560 bind(L_on_abort);
1561 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1562 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1563 }
1564 bind(L_decrement_retry);
1565 if (RTMRetryCount > 0) {
1566 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1567 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1568 }
1569 }
1570
1571 // Use RTM for inflating locks
1572 // inputs: objReg (object to lock)
1573 // boxReg (on-stack box address (displaced header location) - KILLED)
1574 // tmpReg (ObjectMonitor address + markWord::monitor_value)
1575 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1576 Register scrReg, Register retry_on_busy_count_Reg,
1577 Register retry_on_abort_count_Reg,
1578 RTMLockingCounters* rtm_counters,
1579 Metadata* method_data, bool profile_rtm,
1580 Label& DONE_LABEL) {
1581 assert(UseRTMLocking, "why call this otherwise?");
1582 assert(tmpReg == rax, "");
1583 assert(scrReg == rdx, "");
1584 Label L_rtm_retry, L_decrement_retry, L_on_abort, L_local_done;
1585 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1586
1587 // Without cast to int32_t this style of movptr will destroy r10 which is typically obj.
1588 movptr(Address(boxReg, 0), (int32_t)intptr_t(markWord::unused_mark().value()));
1589
1590 if (!HandshakeAfterDeflateIdleMonitors) {
1591 // Increment the ObjectMonitor's ref_count for safety or force the
1592 // enter slow path via DONE_LABEL.
1593 // In rtm_inflated_locking(), initially tmpReg contains the object's
1594 // mark word which, in this case, is the (ObjectMonitor* | monitor_value).
1595 // Also this code uses scrReg as its temporary register.
1596 inc_om_ref_count(objReg, tmpReg /* om_reg */, scrReg /* tmp_reg */, DONE_LABEL);
1597 }
1598
1599 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1600
1601 if (RTMRetryCount > 0) {
1602 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1603 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1604 bind(L_rtm_retry);
1605 }
1606 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1607 Label L_noincrement;
1608 if (RTMTotalCountIncrRate > 1) {
1609 // tmpReg, scrReg and flags are killed
1610 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1611 }
1612 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1613 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1614 bind(L_noincrement);
1615 }
1616 xbegin(L_on_abort);
1617 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1618 movptr(tmpReg, Address(tmpReg, owner_offset));
1619 testptr(tmpReg, tmpReg);
1620 jcc(Assembler::zero, L_local_done);
1621 if (UseRTMXendForLockBusy) {
1622 xend();
1623 jmp(L_decrement_retry);
1624 }
1625 else {
1626 xabort(0);
1627 }
1628 bind(L_on_abort);
1629 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1630 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1631 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1632 }
1633 if (RTMRetryCount > 0) {
1634 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1635 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1636 }
1637
1638 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1639 testptr(tmpReg, tmpReg) ;
1640 jccb(Assembler::notZero, L_decrement_retry) ;
1641
1642 // Appears unlocked - try to swing _owner from null to non-null.
1643 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1644 #ifdef _LP64
1645 Register threadReg = r15_thread;
1646 #else
1647 get_thread(scrReg);
1648 Register threadReg = scrReg;
1649 #endif
1650 lock();
1651 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1652
1653 if (RTMRetryCount > 0) {
1654 // success done else retry
1655 jccb(Assembler::equal, L_local_done);
1656 bind(L_decrement_retry);
1657 // Spin and retry if lock is busy.
1658 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1659 }
1660 else {
1661 bind(L_decrement_retry);
1662 }
1663
1664 // rtm_inflated_locking() exit paths come here except for a failed
1665 // inc_om_ref_count() which goes directly to DONE_LABEL.
1666 bind(L_local_done);
1667 if (!HandshakeAfterDeflateIdleMonitors) {
1668 pushf(); // Preserve flags.
1669 // Decrement the ObjectMonitor's ref_count.
1670 lock();
1671 decrementl(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(ref_count)));
1672 popf(); // Restore flags so we have the proper ICC.ZF value.
1673 }
1674
1675 jmp(DONE_LABEL) ;
1676 }
1677
1678 #endif // INCLUDE_RTM_OPT
1679
1680 // fast_lock and fast_unlock used by C2
1681
1682 // Because the transitions from emitted code to the runtime
1683 // monitorenter/exit helper stubs are so slow it's critical that
1684 // we inline both the stack-locking fast path and the inflated fast path.
1685 //
1686 // See also: cmpFastLock and cmpFastUnlock.
1687 //
1688 // What follows is a specialized inline transliteration of the code
1689 // in enter() and exit(). If we're concerned about I$ bloat another
1690 // option would be to emit TrySlowEnter and TrySlowExit methods
1691 // at startup-time. These methods would accept arguments as
1692 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1693 // indications in the icc.ZFlag. fast_lock and fast_unlock would simply
1694 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1695 // In practice, however, the # of lock sites is bounded and is usually small.
1696 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1697 // if the processor uses simple bimodal branch predictors keyed by EIP
1698 // Since the helper routines would be called from multiple synchronization
1699 // sites.
1700 //
1701 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1702 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1703 // to those specialized methods. That'd give us a mostly platform-independent
1704 // implementation that the JITs could optimize and inline at their pleasure.
1705 // Done correctly, the only time we'd need to cross to native could would be
1706 // to park() or unpark() threads. We'd also need a few more unsafe operators
1707 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1708 // (b) explicit barriers or fence operations.
1709 //
1710 // TODO:
1711 //
1712 // * Arrange for C2 to pass "Self" into fast_lock and fast_unlock in one of the registers (scr).
1713 // This avoids manifesting the Self pointer in the fast_lock and fast_unlock terminals.
1714 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1715 // the lock operators would typically be faster than reifying Self.
1716 //
1717 // * Ideally I'd define the primitives as:
1718 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1719 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1720 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1721 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1722 // Furthermore the register assignments are overconstrained, possibly resulting in
1723 // sub-optimal code near the synchronization site.
1724 //
1725 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1726 // Alternately, use a better sp-proximity test.
1727 //
1728 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1729 // Either one is sufficient to uniquely identify a thread.
1730 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1731 //
1732 // * Intrinsify notify() and notifyAll() for the common cases where the
1733 // object is locked by the calling thread but the waitlist is empty.
1734 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1735 //
1736 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1737 // But beware of excessive branch density on AMD Opterons.
1738 //
1739 // * Both fast_lock and fast_unlock set the ICC.ZF to indicate success
1740 // or failure of the fast path. If the fast path fails then we pass
1741 // control to the slow path, typically in C. In fast_lock and
1742 // fast_unlock we often branch to DONE_LABEL, just to find that C2
1743 // will emit a conditional branch immediately after the node.
1744 // So we have branches to branches and lots of ICC.ZF games.
1745 // Instead, it might be better to have C2 pass a "FailureLabel"
1746 // into fast_lock and fast_unlock. In the case of success, control
1747 // will drop through the node. ICC.ZF is undefined at exit.
1748 // In the case of failure, the node will branch directly to the
1749 // FailureLabel
1750
1751
1752 // obj: object to lock
1753 // box: on-stack box address (displaced header location) - KILLED
1754 // rax,: tmp -- KILLED
1755 // scr: tmp -- KILLED
1756 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1757 Register scrReg, Register cx1Reg, Register cx2Reg,
1758 BiasedLockingCounters* counters,
1759 RTMLockingCounters* rtm_counters,
1760 RTMLockingCounters* stack_rtm_counters,
1761 Metadata* method_data,
1762 bool use_rtm, bool profile_rtm) {
1763 // Ensure the register assignments are disjoint
1764 assert(tmpReg == rax, "");
1765
1766 if (use_rtm) {
1767 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1768 } else {
1769 assert(cx1Reg == noreg, "");
1770 assert(cx2Reg == noreg, "");
1771 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1772 }
1773
1774 if (counters != NULL) {
1775 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1776 }
1777
1778 // Possible cases that we'll encounter in fast_lock
1779 // ------------------------------------------------
1780 // * Inflated
1781 // -- unlocked
1782 // -- Locked
1783 // = by self
1784 // = by other
1785 // * biased
1786 // -- by Self
1787 // -- by other
1788 // * neutral
1789 // * stack-locked
1790 // -- by self
1791 // = sp-proximity test hits
1792 // = sp-proximity test generates false-negative
1793 // -- by other
1794 //
1795
1796 Label IsInflated, DONE_LABEL;
1797
1798 // it's stack-locked, biased or neutral
1799 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1800 // order to reduce the number of conditional branches in the most common cases.
1801 // Beware -- there's a subtle invariant that fetch of the markword
1802 // at [FETCH], below, will never observe a biased encoding (*101b).
1803 // If this invariant is not held we risk exclusion (safety) failure.
1804 if (UseBiasedLocking && !UseOptoBiasInlining) {
1805 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1806 }
1807
1808 #if INCLUDE_RTM_OPT
1809 if (UseRTMForStackLocks && use_rtm) {
1810 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1811 stack_rtm_counters, method_data, profile_rtm,
1812 DONE_LABEL, IsInflated);
1813 }
1814 #endif // INCLUDE_RTM_OPT
1815
1816 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH]
1817 testptr(tmpReg, markWord::monitor_value); // inflated vs stack-locked|neutral|biased
1818 jccb(Assembler::notZero, IsInflated);
1819
1820 // Attempt stack-locking ...
1821 orptr (tmpReg, markWord::unlocked_value);
1822 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1823 lock();
1824 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg
1825 if (counters != NULL) {
1826 cond_inc32(Assembler::equal,
1827 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1828 }
1829 jcc(Assembler::equal, DONE_LABEL); // Success
1830
1831 // Recursive locking.
1832 // The object is stack-locked: markword contains stack pointer to BasicLock.
1833 // Locked by current thread if difference with current SP is less than one page.
1834 subptr(tmpReg, rsp);
1835 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1836 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1837 movptr(Address(boxReg, 0), tmpReg);
1838 if (counters != NULL) {
1839 cond_inc32(Assembler::equal,
1840 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1841 }
1842 jmp(DONE_LABEL);
1843
1844 bind(IsInflated);
1845 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markWord::monitor_value
1846
1847 #if INCLUDE_RTM_OPT
1848 // Use the same RTM locking code in 32- and 64-bit VM.
1849 if (use_rtm) {
1850 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1851 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1852 } else {
1853 #endif // INCLUDE_RTM_OPT
1854
1855 #ifndef _LP64
1856 // The object is inflated.
1857
1858 // boxReg refers to the on-stack BasicLock in the current frame.
1859 // We'd like to write:
1860 // set box->_displaced_header = markWord::unused_mark(). Any non-0 value suffices.
1861 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1862 // additional latency as we have another ST in the store buffer that must drain.
1863
1864 // avoid ST-before-CAS
1865 // register juggle because we need tmpReg for cmpxchgptr below
1866 movptr(scrReg, boxReg);
1867 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1868
1869 // Optimistic form: consider XORL tmpReg,tmpReg
1870 movptr(tmpReg, NULL_WORD);
1871
1872 // Appears unlocked - try to swing _owner from null to non-null.
1873 // Ideally, I'd manifest "Self" with get_thread and then attempt
1874 // to CAS the register containing Self into m->Owner.
1875 // But we don't have enough registers, so instead we can either try to CAS
1876 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1877 // we later store "Self" into m->Owner. Transiently storing a stack address
1878 // (rsp or the address of the box) into m->owner is harmless.
1879 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1880 lock();
1881 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1882 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1883 // If we weren't able to swing _owner from NULL to the BasicLock
1884 // then take the slow path.
1885 jccb (Assembler::notZero, DONE_LABEL);
1886 // update _owner from BasicLock to thread
1887 get_thread (scrReg); // beware: clobbers ICCs
1888 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1889 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1890
1891 // If the CAS fails we can either retry or pass control to the slow path.
1892 // We use the latter tactic.
1893 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1894 // If the CAS was successful ...
1895 // Self has acquired the lock
1896 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1897 // Intentional fall-through into DONE_LABEL ...
1898 #else // _LP64
1899 // It's inflated and we use scrReg for ObjectMonitor* in this section.
1900 movq(scrReg, tmpReg);
1901
1902 // Unconditionally set box->_displaced_header = markWord::unused_mark().
1903 // Without cast to int32_t this style of movptr will destroy r10 which is typically obj.
1904 movptr(Address(boxReg, 0), (int32_t)intptr_t(markWord::unused_mark().value()));
1905
1906 if (!HandshakeAfterDeflateIdleMonitors) {
1907 // Increment the ObjectMonitor's ref_count for safety or force the
1908 // enter slow path via DONE_LABEL.
1909 // In fast_lock(), scrReg contains the object's mark word which,
1910 // in this case, is the (ObjectMonitor* | monitor_value). Also this
1911 // code uses tmpReg as its temporary register.
1912 inc_om_ref_count(objReg, scrReg /* om_reg */, tmpReg /* tmp_reg */, DONE_LABEL);
1913 }
1914
1915 xorq(tmpReg, tmpReg);
1916 lock();
1917 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1918 // Intentional fall-through into DONE_LABEL ...
1919 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1920
1921 if (!HandshakeAfterDeflateIdleMonitors) {
1922 pushf(); // Preserve flags.
1923 // Decrement the ObjectMonitor's ref_count.
1924 lock();
1925 decrementl(Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(ref_count)));
1926 popf(); // Restore flags so we have the proper ICC.ZF value.
1927 }
1928 #endif // _LP64
1929 #if INCLUDE_RTM_OPT
1930 } // use_rtm()
1931 #endif
1932 // DONE_LABEL is a hot target - we'd really like to place it at the
1933 // start of cache line by padding with NOPs.
1934 // See the AMD and Intel software optimization manuals for the
1935 // most efficient "long" NOP encodings.
1936 // Unfortunately none of our alignment mechanisms suffice.
1937 bind(DONE_LABEL);
1938
1939 // At DONE_LABEL the icc ZFlag is set as follows ...
1940 // fast_unlock uses the same protocol.
1941 // ZFlag == 1 -> Success
1942 // ZFlag == 0 -> Failure - force control through the slow path
1943 }
1944
1945 // obj: object to unlock
1946 // box: box address (displaced header location), killed. Must be EAX.
1947 // tmp: killed, cannot be obj nor box.
1948 //
1949 // Some commentary on balanced locking:
1950 //
1951 // fast_lock and fast_unlock are emitted only for provably balanced lock sites.
1952 // Methods that don't have provably balanced locking are forced to run in the
1953 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1954 // The interpreter provides two properties:
1955 // I1: At return-time the interpreter automatically and quietly unlocks any
1956 // objects acquired the current activation (frame). Recall that the
1957 // interpreter maintains an on-stack list of locks currently held by
1958 // a frame.
1959 // I2: If a method attempts to unlock an object that is not held by the
1960 // the frame the interpreter throws IMSX.
1961 //
1962 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1963 // B() doesn't have provably balanced locking so it runs in the interpreter.
1964 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1965 // is still locked by A().
1966 //
1967 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1968 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1969 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1970 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1971 // Arguably given that the spec legislates the JNI case as undefined our implementation
1972 // could reasonably *avoid* checking owner in fast_unlock().
1973 // In the interest of performance we elide m->Owner==Self check in unlock.
1974 // A perfectly viable alternative is to elide the owner check except when
1975 // Xcheck:jni is enabled.
1976
1977 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1978 assert(boxReg == rax, "");
1979 assert_different_registers(objReg, boxReg, tmpReg);
1980
1981 Label DONE_LABEL, Stacked, CheckSucc;
1982
1983 // Critically, the biased locking test must have precedence over
1984 // and appear before the (box->dhw == 0) recursive stack-lock test.
1985 if (UseBiasedLocking && !UseOptoBiasInlining) {
1986 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1987 }
1988
1989 #if INCLUDE_RTM_OPT
1990 if (UseRTMForStackLocks && use_rtm) {
1991 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1992 Label L_regular_unlock;
1993 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1994 andptr(tmpReg, markWord::biased_lock_mask_in_place); // look at 3 lock bits
1995 cmpptr(tmpReg, markWord::unlocked_value); // bits = 001 unlocked
1996 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1997 xend(); // otherwise end...
1998 jmp(DONE_LABEL); // ... and we're done
1999 bind(L_regular_unlock);
2000 }
2001 #endif
2002
2003 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
2004 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
2005 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword
2006 testptr(tmpReg, markWord::monitor_value); // Inflated?
2007 jcc (Assembler::zero, Stacked);
2008
2009 // It's inflated.
2010 #if INCLUDE_RTM_OPT
2011 if (use_rtm) {
2012 Label L_regular_inflated_unlock;
2013 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2014 movptr(boxReg, Address(tmpReg, owner_offset));
2015 testptr(boxReg, boxReg);
2016 jccb(Assembler::notZero, L_regular_inflated_unlock);
2017 xend();
2018 jmp(DONE_LABEL);
2019 bind(L_regular_inflated_unlock);
2020 }
2021 #endif
2022
2023 // Despite our balanced locking property we still check that m->_owner == Self
2024 // as java routines or native JNI code called by this thread might
2025 // have released the lock.
2026 // Refer to the comments in synchronizer.cpp for how we might encode extra
2027 // state in _succ so we can avoid fetching EntryList|cxq.
2028 //
2029 // I'd like to add more cases in fast_lock() and fast_unlock() --
2030 // such as recursive enter and exit -- but we have to be wary of
2031 // I$ bloat, T$ effects and BP$ effects.
2032 //
2033 // If there's no contention try a 1-0 exit. That is, exit without
2034 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2035 // we detect and recover from the race that the 1-0 exit admits.
2036 //
2037 // Conceptually fast_unlock() must execute a STST|LDST "release" barrier
2038 // before it STs null into _owner, releasing the lock. Updates
2039 // to data protected by the critical section must be visible before
2040 // we drop the lock (and thus before any other thread could acquire
2041 // the lock and observe the fields protected by the lock).
2042 // IA32's memory-model is SPO, so STs are ordered with respect to
2043 // each other and there's no need for an explicit barrier (fence).
2044 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2045 #ifndef _LP64
2046 get_thread (boxReg);
2047
2048 // Note that we could employ various encoding schemes to reduce
2049 // the number of loads below (currently 4) to just 2 or 3.
2050 // Refer to the comments in synchronizer.cpp.
2051 // In practice the chain of fetches doesn't seem to impact performance, however.
2052 xorptr(boxReg, boxReg);
2053 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2054 jccb (Assembler::notZero, DONE_LABEL);
2055 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2056 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2057 jccb (Assembler::notZero, CheckSucc);
2058 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2059 jmpb (DONE_LABEL);
2060
2061 bind (Stacked);
2062 // It's not inflated and it's not recursively stack-locked and it's not biased.
2063 // It must be stack-locked.
2064 // Try to reset the header to displaced header.
2065 // The "box" value on the stack is stable, so we can reload
2066 // and be assured we observe the same value as above.
2067 movptr(tmpReg, Address(boxReg, 0));
2068 lock();
2069 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2070 // Intention fall-thru into DONE_LABEL
2071
2072 // DONE_LABEL is a hot target - we'd really like to place it at the
2073 // start of cache line by padding with NOPs.
2074 // See the AMD and Intel software optimization manuals for the
2075 // most efficient "long" NOP encodings.
2076 // Unfortunately none of our alignment mechanisms suffice.
2077 bind (CheckSucc);
2078 #else // _LP64
2079 // It's inflated
2080
2081 if (!HandshakeAfterDeflateIdleMonitors) {
2082 // Increment the ObjectMonitor's ref_count for safety or force the
2083 // exit slow path via DONE_LABEL.
2084 // In fast_unlock(), tmpReg contains the object's mark word which,
2085 // in this case, is the (ObjectMonitor* | monitor_value). Also this
2086 // code uses boxReg as its temporary register.
2087 inc_om_ref_count(objReg, tmpReg /* om_reg */, boxReg /* tmp_reg */, DONE_LABEL);
2088 }
2089
2090 // Try to avoid passing control into the slow path ...
2091 Label LSuccess, LGoSlowPath;
2092 xorptr(boxReg, boxReg);
2093 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2094 jccb(Assembler::notZero, LGoSlowPath);
2095 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2096 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2097 jccb (Assembler::notZero, CheckSucc);
2098 // Without cast to int32_t this style of movptr will destroy r10 which is typically obj.
2099 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2100 jmpb(LSuccess);
2101
2102 bind (CheckSucc);
2103
2104 // The following optional optimization can be elided if necessary
2105 // Effectively: if (succ == null) goto slow path
2106 // The code reduces the window for a race, however,
2107 // and thus benefits performance.
2108 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2109 jccb (Assembler::zero, LGoSlowPath);
2110
2111 xorptr(boxReg, boxReg);
2112 // Without cast to int32_t this style of movptr will destroy r10 which is typically obj.
2113 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2114
2115 // Memory barrier/fence
2116 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2117 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2118 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2119 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2120 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2121 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2122 lock(); addl(Address(rsp, 0), 0);
2123
2124 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2125 jccb (Assembler::notZero, LSuccess);
2126
2127 // Rare inopportune interleaving - race.
2128 // The successor vanished in the small window above.
2129 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2130 // We need to ensure progress and succession.
2131 // Try to reacquire the lock.
2132 // If that fails then the new owner is responsible for succession and this
2133 // thread needs to take no further action and can exit via the fast path (success).
2134 // If the re-acquire succeeds then pass control into the slow path.
2135 // As implemented, this latter mode is horrible because we generated more
2136 // coherence traffic on the lock *and* artifically extended the critical section
2137 // length while by virtue of passing control into the slow path.
2138
2139 // box is really RAX -- the following CMPXCHG depends on that binding
2140 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2141 lock();
2142 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2143 // There's no successor so we tried to regrab the lock.
2144 // If that didn't work, then another thread grabbed the
2145 // lock so we're done (and exit was a success).
2146 jccb (Assembler::notEqual, LSuccess);
2147 // Intentional fall-through into slow path
2148
2149 bind (LGoSlowPath);
2150 if (!HandshakeAfterDeflateIdleMonitors) {
2151 lock();
2152 decrementl(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(ref_count)));
2153 }
2154 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2155 jmpb (DONE_LABEL);
2156
2157 bind (LSuccess);
2158 if (!HandshakeAfterDeflateIdleMonitors) {
2159 lock();
2160 decrementl(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(ref_count)));
2161 }
2162 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2163 jmpb (DONE_LABEL);
2164
2165 bind (Stacked);
2166 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2167 lock();
2168 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2169
2170 #endif
2171 bind(DONE_LABEL);
2172 }
2173 #endif // COMPILER2
2174
2175 void MacroAssembler::c2bool(Register x) {
2176 // implements x == 0 ? 0 : 1
2177 // note: must only look at least-significant byte of x
2178 // since C-style booleans are stored in one byte
2179 // only! (was bug)
2180 andl(x, 0xFF);
2181 setb(Assembler::notZero, x);
2182 }
2183
2184 // Wouldn't need if AddressLiteral version had new name
2185 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2186 Assembler::call(L, rtype);
2187 }
2188
2189 void MacroAssembler::call(Register entry) {
2190 Assembler::call(entry);
2191 }
2192
2193 void MacroAssembler::call(AddressLiteral entry) {
2194 if (reachable(entry)) {
2195 Assembler::call_literal(entry.target(), entry.rspec());
2196 } else {
2197 lea(rscratch1, entry);
2198 Assembler::call(rscratch1);
2199 }
2200 }
2201
2202 void MacroAssembler::ic_call(address entry, jint method_index) {
2203 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2204 movptr(rax, (intptr_t)Universe::non_oop_word());
2205 call(AddressLiteral(entry, rh));
2206 }
2207
2208 // Implementation of call_VM versions
2209
2210 void MacroAssembler::call_VM(Register oop_result,
2211 address entry_point,
2212 bool check_exceptions) {
2213 Label C, E;
2214 call(C, relocInfo::none);
2215 jmp(E);
2216
2217 bind(C);
2218 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2219 ret(0);
2220
2221 bind(E);
2222 }
2223
2224 void MacroAssembler::call_VM(Register oop_result,
2225 address entry_point,
2226 Register arg_1,
2227 bool check_exceptions) {
2228 Label C, E;
2229 call(C, relocInfo::none);
2230 jmp(E);
2231
2232 bind(C);
2233 pass_arg1(this, arg_1);
2234 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2235 ret(0);
2236
2237 bind(E);
2238 }
2239
2240 void MacroAssembler::call_VM(Register oop_result,
2241 address entry_point,
2242 Register arg_1,
2243 Register arg_2,
2244 bool check_exceptions) {
2245 Label C, E;
2246 call(C, relocInfo::none);
2247 jmp(E);
2248
2249 bind(C);
2250
2251 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2252
2253 pass_arg2(this, arg_2);
2254 pass_arg1(this, arg_1);
2255 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2256 ret(0);
2257
2258 bind(E);
2259 }
2260
2261 void MacroAssembler::call_VM(Register oop_result,
2262 address entry_point,
2263 Register arg_1,
2264 Register arg_2,
2265 Register arg_3,
2266 bool check_exceptions) {
2267 Label C, E;
2268 call(C, relocInfo::none);
2269 jmp(E);
2270
2271 bind(C);
2272
2273 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2274 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2275 pass_arg3(this, arg_3);
2276
2277 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2278 pass_arg2(this, arg_2);
2279
2280 pass_arg1(this, arg_1);
2281 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2282 ret(0);
2283
2284 bind(E);
2285 }
2286
2287 void MacroAssembler::call_VM(Register oop_result,
2288 Register last_java_sp,
2289 address entry_point,
2290 int number_of_arguments,
2291 bool check_exceptions) {
2292 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2293 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2294 }
2295
2296 void MacroAssembler::call_VM(Register oop_result,
2297 Register last_java_sp,
2298 address entry_point,
2299 Register arg_1,
2300 bool check_exceptions) {
2301 pass_arg1(this, arg_1);
2302 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2303 }
2304
2305 void MacroAssembler::call_VM(Register oop_result,
2306 Register last_java_sp,
2307 address entry_point,
2308 Register arg_1,
2309 Register arg_2,
2310 bool check_exceptions) {
2311
2312 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2313 pass_arg2(this, arg_2);
2314 pass_arg1(this, arg_1);
2315 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2316 }
2317
2318 void MacroAssembler::call_VM(Register oop_result,
2319 Register last_java_sp,
2320 address entry_point,
2321 Register arg_1,
2322 Register arg_2,
2323 Register arg_3,
2324 bool check_exceptions) {
2325 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2326 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2327 pass_arg3(this, arg_3);
2328 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2329 pass_arg2(this, arg_2);
2330 pass_arg1(this, arg_1);
2331 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2332 }
2333
2334 void MacroAssembler::super_call_VM(Register oop_result,
2335 Register last_java_sp,
2336 address entry_point,
2337 int number_of_arguments,
2338 bool check_exceptions) {
2339 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2340 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2341 }
2342
2343 void MacroAssembler::super_call_VM(Register oop_result,
2344 Register last_java_sp,
2345 address entry_point,
2346 Register arg_1,
2347 bool check_exceptions) {
2348 pass_arg1(this, arg_1);
2349 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2350 }
2351
2352 void MacroAssembler::super_call_VM(Register oop_result,
2353 Register last_java_sp,
2354 address entry_point,
2355 Register arg_1,
2356 Register arg_2,
2357 bool check_exceptions) {
2358
2359 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2360 pass_arg2(this, arg_2);
2361 pass_arg1(this, arg_1);
2362 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2363 }
2364
2365 void MacroAssembler::super_call_VM(Register oop_result,
2366 Register last_java_sp,
2367 address entry_point,
2368 Register arg_1,
2369 Register arg_2,
2370 Register arg_3,
2371 bool check_exceptions) {
2372 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2373 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2374 pass_arg3(this, arg_3);
2375 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2376 pass_arg2(this, arg_2);
2377 pass_arg1(this, arg_1);
2378 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2379 }
2380
2381 void MacroAssembler::call_VM_base(Register oop_result,
2382 Register java_thread,
2383 Register last_java_sp,
2384 address entry_point,
2385 int number_of_arguments,
2386 bool check_exceptions) {
2387 // determine java_thread register
2388 if (!java_thread->is_valid()) {
2389 #ifdef _LP64
2390 java_thread = r15_thread;
2391 #else
2392 java_thread = rdi;
2393 get_thread(java_thread);
2394 #endif // LP64
2395 }
2396 // determine last_java_sp register
2397 if (!last_java_sp->is_valid()) {
2398 last_java_sp = rsp;
2399 }
2400 // debugging support
2401 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2402 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2403 #ifdef ASSERT
2404 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2405 // r12 is the heapbase.
2406 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2407 #endif // ASSERT
2408
2409 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2410 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2411
2412 // push java thread (becomes first argument of C function)
2413
2414 NOT_LP64(push(java_thread); number_of_arguments++);
2415 LP64_ONLY(mov(c_rarg0, r15_thread));
2416
2417 // set last Java frame before call
2418 assert(last_java_sp != rbp, "can't use ebp/rbp");
2419
2420 // Only interpreter should have to set fp
2421 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2422
2423 // do the call, remove parameters
2424 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2425
2426 // restore the thread (cannot use the pushed argument since arguments
2427 // may be overwritten by C code generated by an optimizing compiler);
2428 // however can use the register value directly if it is callee saved.
2429 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2430 // rdi & rsi (also r15) are callee saved -> nothing to do
2431 #ifdef ASSERT
2432 guarantee(java_thread != rax, "change this code");
2433 push(rax);
2434 { Label L;
2435 get_thread(rax);
2436 cmpptr(java_thread, rax);
2437 jcc(Assembler::equal, L);
2438 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2439 bind(L);
2440 }
2441 pop(rax);
2442 #endif
2443 } else {
2444 get_thread(java_thread);
2445 }
2446 // reset last Java frame
2447 // Only interpreter should have to clear fp
2448 reset_last_Java_frame(java_thread, true);
2449
2450 // C++ interp handles this in the interpreter
2451 check_and_handle_popframe(java_thread);
2452 check_and_handle_earlyret(java_thread);
2453
2454 if (check_exceptions) {
2455 // check for pending exceptions (java_thread is set upon return)
2456 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2457 #ifndef _LP64
2458 jump_cc(Assembler::notEqual,
2459 RuntimeAddress(StubRoutines::forward_exception_entry()));
2460 #else
2461 // This used to conditionally jump to forward_exception however it is
2462 // possible if we relocate that the branch will not reach. So we must jump
2463 // around so we can always reach
2464
2465 Label ok;
2466 jcc(Assembler::equal, ok);
2467 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2468 bind(ok);
2469 #endif // LP64
2470 }
2471
2472 // get oop result if there is one and reset the value in the thread
2473 if (oop_result->is_valid()) {
2474 get_vm_result(oop_result, java_thread);
2475 }
2476 }
2477
2478 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2479
2480 // Calculate the value for last_Java_sp
2481 // somewhat subtle. call_VM does an intermediate call
2482 // which places a return address on the stack just under the
2483 // stack pointer as the user finsihed with it. This allows
2484 // use to retrieve last_Java_pc from last_Java_sp[-1].
2485 // On 32bit we then have to push additional args on the stack to accomplish
2486 // the actual requested call. On 64bit call_VM only can use register args
2487 // so the only extra space is the return address that call_VM created.
2488 // This hopefully explains the calculations here.
2489
2490 #ifdef _LP64
2491 // We've pushed one address, correct last_Java_sp
2492 lea(rax, Address(rsp, wordSize));
2493 #else
2494 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2495 #endif // LP64
2496
2497 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2498
2499 }
2500
2501 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2502 void MacroAssembler::call_VM_leaf0(address entry_point) {
2503 MacroAssembler::call_VM_leaf_base(entry_point, 0);
2504 }
2505
2506 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2507 call_VM_leaf_base(entry_point, number_of_arguments);
2508 }
2509
2510 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2511 pass_arg0(this, arg_0);
2512 call_VM_leaf(entry_point, 1);
2513 }
2514
2515 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2516
2517 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2518 pass_arg1(this, arg_1);
2519 pass_arg0(this, arg_0);
2520 call_VM_leaf(entry_point, 2);
2521 }
2522
2523 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2524 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2525 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2526 pass_arg2(this, arg_2);
2527 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2528 pass_arg1(this, arg_1);
2529 pass_arg0(this, arg_0);
2530 call_VM_leaf(entry_point, 3);
2531 }
2532
2533 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2534 pass_arg0(this, arg_0);
2535 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2536 }
2537
2538 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2539
2540 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2541 pass_arg1(this, arg_1);
2542 pass_arg0(this, arg_0);
2543 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2544 }
2545
2546 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2547 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2548 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2549 pass_arg2(this, arg_2);
2550 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2551 pass_arg1(this, arg_1);
2552 pass_arg0(this, arg_0);
2553 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2554 }
2555
2556 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2557 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2558 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2559 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2560 pass_arg3(this, arg_3);
2561 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2562 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2563 pass_arg2(this, arg_2);
2564 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2565 pass_arg1(this, arg_1);
2566 pass_arg0(this, arg_0);
2567 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2568 }
2569
2570 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2571 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2572 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2573 verify_oop(oop_result, "broken oop in call_VM_base");
2574 }
2575
2576 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2577 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2578 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2579 }
2580
2581 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2582 }
2583
2584 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2585 }
2586
2587 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2588 if (reachable(src1)) {
2589 cmpl(as_Address(src1), imm);
2590 } else {
2591 lea(rscratch1, src1);
2592 cmpl(Address(rscratch1, 0), imm);
2593 }
2594 }
2595
2596 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2597 assert(!src2.is_lval(), "use cmpptr");
2598 if (reachable(src2)) {
2599 cmpl(src1, as_Address(src2));
2600 } else {
2601 lea(rscratch1, src2);
2602 cmpl(src1, Address(rscratch1, 0));
2603 }
2604 }
2605
2606 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2607 Assembler::cmpl(src1, imm);
2608 }
2609
2610 void MacroAssembler::cmp32(Register src1, Address src2) {
2611 Assembler::cmpl(src1, src2);
2612 }
2613
2614 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2615 ucomisd(opr1, opr2);
2616
2617 Label L;
2618 if (unordered_is_less) {
2619 movl(dst, -1);
2620 jcc(Assembler::parity, L);
2621 jcc(Assembler::below , L);
2622 movl(dst, 0);
2623 jcc(Assembler::equal , L);
2624 increment(dst);
2625 } else { // unordered is greater
2626 movl(dst, 1);
2627 jcc(Assembler::parity, L);
2628 jcc(Assembler::above , L);
2629 movl(dst, 0);
2630 jcc(Assembler::equal , L);
2631 decrementl(dst);
2632 }
2633 bind(L);
2634 }
2635
2636 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2637 ucomiss(opr1, opr2);
2638
2639 Label L;
2640 if (unordered_is_less) {
2641 movl(dst, -1);
2642 jcc(Assembler::parity, L);
2643 jcc(Assembler::below , L);
2644 movl(dst, 0);
2645 jcc(Assembler::equal , L);
2646 increment(dst);
2647 } else { // unordered is greater
2648 movl(dst, 1);
2649 jcc(Assembler::parity, L);
2650 jcc(Assembler::above , L);
2651 movl(dst, 0);
2652 jcc(Assembler::equal , L);
2653 decrementl(dst);
2654 }
2655 bind(L);
2656 }
2657
2658
2659 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2660 if (reachable(src1)) {
2661 cmpb(as_Address(src1), imm);
2662 } else {
2663 lea(rscratch1, src1);
2664 cmpb(Address(rscratch1, 0), imm);
2665 }
2666 }
2667
2668 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2669 #ifdef _LP64
2670 if (src2.is_lval()) {
2671 movptr(rscratch1, src2);
2672 Assembler::cmpq(src1, rscratch1);
2673 } else if (reachable(src2)) {
2674 cmpq(src1, as_Address(src2));
2675 } else {
2676 lea(rscratch1, src2);
2677 Assembler::cmpq(src1, Address(rscratch1, 0));
2678 }
2679 #else
2680 if (src2.is_lval()) {
2681 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2682 } else {
2683 cmpl(src1, as_Address(src2));
2684 }
2685 #endif // _LP64
2686 }
2687
2688 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2689 assert(src2.is_lval(), "not a mem-mem compare");
2690 #ifdef _LP64
2691 // moves src2's literal address
2692 movptr(rscratch1, src2);
2693 Assembler::cmpq(src1, rscratch1);
2694 #else
2695 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2696 #endif // _LP64
2697 }
2698
2699 void MacroAssembler::cmpoop(Register src1, Register src2) {
2700 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2701 bs->obj_equals(this, src1, src2);
2702 }
2703
2704 void MacroAssembler::cmpoop(Register src1, Address src2) {
2705 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2706 bs->obj_equals(this, src1, src2);
2707 }
2708
2709 #ifdef _LP64
2710 void MacroAssembler::cmpoop(Register src1, jobject src2) {
2711 movoop(rscratch1, src2);
2712 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2713 bs->obj_equals(this, src1, rscratch1);
2714 }
2715 #endif
2716
2717 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2718 if (reachable(adr)) {
2719 lock();
2720 cmpxchgptr(reg, as_Address(adr));
2721 } else {
2722 lea(rscratch1, adr);
2723 lock();
2724 cmpxchgptr(reg, Address(rscratch1, 0));
2725 }
2726 }
2727
2728 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2729 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2730 }
2731
2732 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2733 if (reachable(src)) {
2734 Assembler::comisd(dst, as_Address(src));
2735 } else {
2736 lea(rscratch1, src);
2737 Assembler::comisd(dst, Address(rscratch1, 0));
2738 }
2739 }
2740
2741 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2742 if (reachable(src)) {
2743 Assembler::comiss(dst, as_Address(src));
2744 } else {
2745 lea(rscratch1, src);
2746 Assembler::comiss(dst, Address(rscratch1, 0));
2747 }
2748 }
2749
2750
2751 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2752 Condition negated_cond = negate_condition(cond);
2753 Label L;
2754 jcc(negated_cond, L);
2755 pushf(); // Preserve flags
2756 atomic_incl(counter_addr);
2757 popf();
2758 bind(L);
2759 }
2760
2761 int MacroAssembler::corrected_idivl(Register reg) {
2762 // Full implementation of Java idiv and irem; checks for
2763 // special case as described in JVM spec., p.243 & p.271.
2764 // The function returns the (pc) offset of the idivl
2765 // instruction - may be needed for implicit exceptions.
2766 //
2767 // normal case special case
2768 //
2769 // input : rax,: dividend min_int
2770 // reg: divisor (may not be rax,/rdx) -1
2771 //
2772 // output: rax,: quotient (= rax, idiv reg) min_int
2773 // rdx: remainder (= rax, irem reg) 0
2774 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2775 const int min_int = 0x80000000;
2776 Label normal_case, special_case;
2777
2778 // check for special case
2779 cmpl(rax, min_int);
2780 jcc(Assembler::notEqual, normal_case);
2781 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2782 cmpl(reg, -1);
2783 jcc(Assembler::equal, special_case);
2784
2785 // handle normal case
2786 bind(normal_case);
2787 cdql();
2788 int idivl_offset = offset();
2789 idivl(reg);
2790
2791 // normal and special case exit
2792 bind(special_case);
2793
2794 return idivl_offset;
2795 }
2796
2797
2798
2799 void MacroAssembler::decrementl(Register reg, int value) {
2800 if (value == min_jint) {subl(reg, value) ; return; }
2801 if (value < 0) { incrementl(reg, -value); return; }
2802 if (value == 0) { ; return; }
2803 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2804 /* else */ { subl(reg, value) ; return; }
2805 }
2806
2807 void MacroAssembler::decrementl(Address dst, int value) {
2808 if (value == min_jint) {subl(dst, value) ; return; }
2809 if (value < 0) { incrementl(dst, -value); return; }
2810 if (value == 0) { ; return; }
2811 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2812 /* else */ { subl(dst, value) ; return; }
2813 }
2814
2815 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2816 assert (shift_value > 0, "illegal shift value");
2817 Label _is_positive;
2818 testl (reg, reg);
2819 jcc (Assembler::positive, _is_positive);
2820 int offset = (1 << shift_value) - 1 ;
2821
2822 if (offset == 1) {
2823 incrementl(reg);
2824 } else {
2825 addl(reg, offset);
2826 }
2827
2828 bind (_is_positive);
2829 sarl(reg, shift_value);
2830 }
2831
2832 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2833 if (reachable(src)) {
2834 Assembler::divsd(dst, as_Address(src));
2835 } else {
2836 lea(rscratch1, src);
2837 Assembler::divsd(dst, Address(rscratch1, 0));
2838 }
2839 }
2840
2841 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2842 if (reachable(src)) {
2843 Assembler::divss(dst, as_Address(src));
2844 } else {
2845 lea(rscratch1, src);
2846 Assembler::divss(dst, Address(rscratch1, 0));
2847 }
2848 }
2849
2850 // !defined(COMPILER2) is because of stupid core builds
2851 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2852 void MacroAssembler::empty_FPU_stack() {
2853 if (VM_Version::supports_mmx()) {
2854 emms();
2855 } else {
2856 for (int i = 8; i-- > 0; ) ffree(i);
2857 }
2858 }
2859 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2860
2861
2862 void MacroAssembler::enter() {
2863 push(rbp);
2864 mov(rbp, rsp);
2865 }
2866
2867 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2868 void MacroAssembler::fat_nop() {
2869 if (UseAddressNop) {
2870 addr_nop_5();
2871 } else {
2872 emit_int8(0x26); // es:
2873 emit_int8(0x2e); // cs:
2874 emit_int8(0x64); // fs:
2875 emit_int8(0x65); // gs:
2876 emit_int8((unsigned char)0x90);
2877 }
2878 }
2879
2880 void MacroAssembler::fcmp(Register tmp) {
2881 fcmp(tmp, 1, true, true);
2882 }
2883
2884 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2885 assert(!pop_right || pop_left, "usage error");
2886 if (VM_Version::supports_cmov()) {
2887 assert(tmp == noreg, "unneeded temp");
2888 if (pop_left) {
2889 fucomip(index);
2890 } else {
2891 fucomi(index);
2892 }
2893 if (pop_right) {
2894 fpop();
2895 }
2896 } else {
2897 assert(tmp != noreg, "need temp");
2898 if (pop_left) {
2899 if (pop_right) {
2900 fcompp();
2901 } else {
2902 fcomp(index);
2903 }
2904 } else {
2905 fcom(index);
2906 }
2907 // convert FPU condition into eflags condition via rax,
2908 save_rax(tmp);
2909 fwait(); fnstsw_ax();
2910 sahf();
2911 restore_rax(tmp);
2912 }
2913 // condition codes set as follows:
2914 //
2915 // CF (corresponds to C0) if x < y
2916 // PF (corresponds to C2) if unordered
2917 // ZF (corresponds to C3) if x = y
2918 }
2919
2920 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2921 fcmp2int(dst, unordered_is_less, 1, true, true);
2922 }
2923
2924 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2925 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2926 Label L;
2927 if (unordered_is_less) {
2928 movl(dst, -1);
2929 jcc(Assembler::parity, L);
2930 jcc(Assembler::below , L);
2931 movl(dst, 0);
2932 jcc(Assembler::equal , L);
2933 increment(dst);
2934 } else { // unordered is greater
2935 movl(dst, 1);
2936 jcc(Assembler::parity, L);
2937 jcc(Assembler::above , L);
2938 movl(dst, 0);
2939 jcc(Assembler::equal , L);
2940 decrementl(dst);
2941 }
2942 bind(L);
2943 }
2944
2945 void MacroAssembler::fld_d(AddressLiteral src) {
2946 fld_d(as_Address(src));
2947 }
2948
2949 void MacroAssembler::fld_s(AddressLiteral src) {
2950 fld_s(as_Address(src));
2951 }
2952
2953 void MacroAssembler::fld_x(AddressLiteral src) {
2954 Assembler::fld_x(as_Address(src));
2955 }
2956
2957 void MacroAssembler::fldcw(AddressLiteral src) {
2958 Assembler::fldcw(as_Address(src));
2959 }
2960
2961 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
2962 if (reachable(src)) {
2963 Assembler::mulpd(dst, as_Address(src));
2964 } else {
2965 lea(rscratch1, src);
2966 Assembler::mulpd(dst, Address(rscratch1, 0));
2967 }
2968 }
2969
2970 void MacroAssembler::increase_precision() {
2971 subptr(rsp, BytesPerWord);
2972 fnstcw(Address(rsp, 0));
2973 movl(rax, Address(rsp, 0));
2974 orl(rax, 0x300);
2975 push(rax);
2976 fldcw(Address(rsp, 0));
2977 pop(rax);
2978 }
2979
2980 void MacroAssembler::restore_precision() {
2981 fldcw(Address(rsp, 0));
2982 addptr(rsp, BytesPerWord);
2983 }
2984
2985 void MacroAssembler::fpop() {
2986 ffree();
2987 fincstp();
2988 }
2989
2990 void MacroAssembler::load_float(Address src) {
2991 if (UseSSE >= 1) {
2992 movflt(xmm0, src);
2993 } else {
2994 LP64_ONLY(ShouldNotReachHere());
2995 NOT_LP64(fld_s(src));
2996 }
2997 }
2998
2999 void MacroAssembler::store_float(Address dst) {
3000 if (UseSSE >= 1) {
3001 movflt(dst, xmm0);
3002 } else {
3003 LP64_ONLY(ShouldNotReachHere());
3004 NOT_LP64(fstp_s(dst));
3005 }
3006 }
3007
3008 void MacroAssembler::load_double(Address src) {
3009 if (UseSSE >= 2) {
3010 movdbl(xmm0, src);
3011 } else {
3012 LP64_ONLY(ShouldNotReachHere());
3013 NOT_LP64(fld_d(src));
3014 }
3015 }
3016
3017 void MacroAssembler::store_double(Address dst) {
3018 if (UseSSE >= 2) {
3019 movdbl(dst, xmm0);
3020 } else {
3021 LP64_ONLY(ShouldNotReachHere());
3022 NOT_LP64(fstp_d(dst));
3023 }
3024 }
3025
3026 void MacroAssembler::fremr(Register tmp) {
3027 save_rax(tmp);
3028 { Label L;
3029 bind(L);
3030 fprem();
3031 fwait(); fnstsw_ax();
3032 #ifdef _LP64
3033 testl(rax, 0x400);
3034 jcc(Assembler::notEqual, L);
3035 #else
3036 sahf();
3037 jcc(Assembler::parity, L);
3038 #endif // _LP64
3039 }
3040 restore_rax(tmp);
3041 // Result is in ST0.
3042 // Note: fxch & fpop to get rid of ST1
3043 // (otherwise FPU stack could overflow eventually)
3044 fxch(1);
3045 fpop();
3046 }
3047
3048 // dst = c = a * b + c
3049 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3050 Assembler::vfmadd231sd(c, a, b);
3051 if (dst != c) {
3052 movdbl(dst, c);
3053 }
3054 }
3055
3056 // dst = c = a * b + c
3057 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3058 Assembler::vfmadd231ss(c, a, b);
3059 if (dst != c) {
3060 movflt(dst, c);
3061 }
3062 }
3063
3064 // dst = c = a * b + c
3065 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3066 Assembler::vfmadd231pd(c, a, b, vector_len);
3067 if (dst != c) {
3068 vmovdqu(dst, c);
3069 }
3070 }
3071
3072 // dst = c = a * b + c
3073 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3074 Assembler::vfmadd231ps(c, a, b, vector_len);
3075 if (dst != c) {
3076 vmovdqu(dst, c);
3077 }
3078 }
3079
3080 // dst = c = a * b + c
3081 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3082 Assembler::vfmadd231pd(c, a, b, vector_len);
3083 if (dst != c) {
3084 vmovdqu(dst, c);
3085 }
3086 }
3087
3088 // dst = c = a * b + c
3089 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3090 Assembler::vfmadd231ps(c, a, b, vector_len);
3091 if (dst != c) {
3092 vmovdqu(dst, c);
3093 }
3094 }
3095
3096 void MacroAssembler::incrementl(AddressLiteral dst) {
3097 if (reachable(dst)) {
3098 incrementl(as_Address(dst));
3099 } else {
3100 lea(rscratch1, dst);
3101 incrementl(Address(rscratch1, 0));
3102 }
3103 }
3104
3105 void MacroAssembler::incrementl(ArrayAddress dst) {
3106 incrementl(as_Address(dst));
3107 }
3108
3109 void MacroAssembler::incrementl(Register reg, int value) {
3110 if (value == min_jint) {addl(reg, value) ; return; }
3111 if (value < 0) { decrementl(reg, -value); return; }
3112 if (value == 0) { ; return; }
3113 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3114 /* else */ { addl(reg, value) ; return; }
3115 }
3116
3117 void MacroAssembler::incrementl(Address dst, int value) {
3118 if (value == min_jint) {addl(dst, value) ; return; }
3119 if (value < 0) { decrementl(dst, -value); return; }
3120 if (value == 0) { ; return; }
3121 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3122 /* else */ { addl(dst, value) ; return; }
3123 }
3124
3125 void MacroAssembler::jump(AddressLiteral dst) {
3126 if (reachable(dst)) {
3127 jmp_literal(dst.target(), dst.rspec());
3128 } else {
3129 lea(rscratch1, dst);
3130 jmp(rscratch1);
3131 }
3132 }
3133
3134 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3135 if (reachable(dst)) {
3136 InstructionMark im(this);
3137 relocate(dst.reloc());
3138 const int short_size = 2;
3139 const int long_size = 6;
3140 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3141 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3142 // 0111 tttn #8-bit disp
3143 emit_int8(0x70 | cc);
3144 emit_int8((offs - short_size) & 0xFF);
3145 } else {
3146 // 0000 1111 1000 tttn #32-bit disp
3147 emit_int8(0x0F);
3148 emit_int8((unsigned char)(0x80 | cc));
3149 emit_int32(offs - long_size);
3150 }
3151 } else {
3152 #ifdef ASSERT
3153 warning("reversing conditional branch");
3154 #endif /* ASSERT */
3155 Label skip;
3156 jccb(reverse[cc], skip);
3157 lea(rscratch1, dst);
3158 Assembler::jmp(rscratch1);
3159 bind(skip);
3160 }
3161 }
3162
3163 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3164 if (reachable(src)) {
3165 Assembler::ldmxcsr(as_Address(src));
3166 } else {
3167 lea(rscratch1, src);
3168 Assembler::ldmxcsr(Address(rscratch1, 0));
3169 }
3170 }
3171
3172 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3173 int off;
3174 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3175 off = offset();
3176 movsbl(dst, src); // movsxb
3177 } else {
3178 off = load_unsigned_byte(dst, src);
3179 shll(dst, 24);
3180 sarl(dst, 24);
3181 }
3182 return off;
3183 }
3184
3185 // Note: load_signed_short used to be called load_signed_word.
3186 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3187 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3188 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3189 int MacroAssembler::load_signed_short(Register dst, Address src) {
3190 int off;
3191 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3192 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3193 // version but this is what 64bit has always done. This seems to imply
3194 // that users are only using 32bits worth.
3195 off = offset();
3196 movswl(dst, src); // movsxw
3197 } else {
3198 off = load_unsigned_short(dst, src);
3199 shll(dst, 16);
3200 sarl(dst, 16);
3201 }
3202 return off;
3203 }
3204
3205 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3206 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3207 // and "3.9 Partial Register Penalties", p. 22).
3208 int off;
3209 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3210 off = offset();
3211 movzbl(dst, src); // movzxb
3212 } else {
3213 xorl(dst, dst);
3214 off = offset();
3215 movb(dst, src);
3216 }
3217 return off;
3218 }
3219
3220 // Note: load_unsigned_short used to be called load_unsigned_word.
3221 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3222 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3223 // and "3.9 Partial Register Penalties", p. 22).
3224 int off;
3225 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3226 off = offset();
3227 movzwl(dst, src); // movzxw
3228 } else {
3229 xorl(dst, dst);
3230 off = offset();
3231 movw(dst, src);
3232 }
3233 return off;
3234 }
3235
3236 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3237 switch (size_in_bytes) {
3238 #ifndef _LP64
3239 case 8:
3240 assert(dst2 != noreg, "second dest register required");
3241 movl(dst, src);
3242 movl(dst2, src.plus_disp(BytesPerInt));
3243 break;
3244 #else
3245 case 8: movq(dst, src); break;
3246 #endif
3247 case 4: movl(dst, src); break;
3248 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3249 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3250 default: ShouldNotReachHere();
3251 }
3252 }
3253
3254 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3255 switch (size_in_bytes) {
3256 #ifndef _LP64
3257 case 8:
3258 assert(src2 != noreg, "second source register required");
3259 movl(dst, src);
3260 movl(dst.plus_disp(BytesPerInt), src2);
3261 break;
3262 #else
3263 case 8: movq(dst, src); break;
3264 #endif
3265 case 4: movl(dst, src); break;
3266 case 2: movw(dst, src); break;
3267 case 1: movb(dst, src); break;
3268 default: ShouldNotReachHere();
3269 }
3270 }
3271
3272 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3273 if (reachable(dst)) {
3274 movl(as_Address(dst), src);
3275 } else {
3276 lea(rscratch1, dst);
3277 movl(Address(rscratch1, 0), src);
3278 }
3279 }
3280
3281 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3282 if (reachable(src)) {
3283 movl(dst, as_Address(src));
3284 } else {
3285 lea(rscratch1, src);
3286 movl(dst, Address(rscratch1, 0));
3287 }
3288 }
3289
3290 // C++ bool manipulation
3291
3292 void MacroAssembler::movbool(Register dst, Address src) {
3293 if(sizeof(bool) == 1)
3294 movb(dst, src);
3295 else if(sizeof(bool) == 2)
3296 movw(dst, src);
3297 else if(sizeof(bool) == 4)
3298 movl(dst, src);
3299 else
3300 // unsupported
3301 ShouldNotReachHere();
3302 }
3303
3304 void MacroAssembler::movbool(Address dst, bool boolconst) {
3305 if(sizeof(bool) == 1)
3306 movb(dst, (int) boolconst);
3307 else if(sizeof(bool) == 2)
3308 movw(dst, (int) boolconst);
3309 else if(sizeof(bool) == 4)
3310 movl(dst, (int) boolconst);
3311 else
3312 // unsupported
3313 ShouldNotReachHere();
3314 }
3315
3316 void MacroAssembler::movbool(Address dst, Register src) {
3317 if(sizeof(bool) == 1)
3318 movb(dst, src);
3319 else if(sizeof(bool) == 2)
3320 movw(dst, src);
3321 else if(sizeof(bool) == 4)
3322 movl(dst, src);
3323 else
3324 // unsupported
3325 ShouldNotReachHere();
3326 }
3327
3328 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3329 movb(as_Address(dst), src);
3330 }
3331
3332 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3333 if (reachable(src)) {
3334 movdl(dst, as_Address(src));
3335 } else {
3336 lea(rscratch1, src);
3337 movdl(dst, Address(rscratch1, 0));
3338 }
3339 }
3340
3341 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3342 if (reachable(src)) {
3343 movq(dst, as_Address(src));
3344 } else {
3345 lea(rscratch1, src);
3346 movq(dst, Address(rscratch1, 0));
3347 }
3348 }
3349
3350 #ifdef COMPILER2
3351 void MacroAssembler::setvectmask(Register dst, Register src) {
3352 guarantee(PostLoopMultiversioning, "must be");
3353 Assembler::movl(dst, 1);
3354 Assembler::shlxl(dst, dst, src);
3355 Assembler::decl(dst);
3356 Assembler::kmovdl(k1, dst);
3357 Assembler::movl(dst, src);
3358 }
3359
3360 void MacroAssembler::restorevectmask() {
3361 guarantee(PostLoopMultiversioning, "must be");
3362 Assembler::knotwl(k1, k0);
3363 }
3364 #endif // COMPILER2
3365
3366 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3367 if (reachable(src)) {
3368 if (UseXmmLoadAndClearUpper) {
3369 movsd (dst, as_Address(src));
3370 } else {
3371 movlpd(dst, as_Address(src));
3372 }
3373 } else {
3374 lea(rscratch1, src);
3375 if (UseXmmLoadAndClearUpper) {
3376 movsd (dst, Address(rscratch1, 0));
3377 } else {
3378 movlpd(dst, Address(rscratch1, 0));
3379 }
3380 }
3381 }
3382
3383 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3384 if (reachable(src)) {
3385 movss(dst, as_Address(src));
3386 } else {
3387 lea(rscratch1, src);
3388 movss(dst, Address(rscratch1, 0));
3389 }
3390 }
3391
3392 void MacroAssembler::movptr(Register dst, Register src) {
3393 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3394 }
3395
3396 void MacroAssembler::movptr(Register dst, Address src) {
3397 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3398 }
3399
3400 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3401 void MacroAssembler::movptr(Register dst, intptr_t src) {
3402 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3403 }
3404
3405 void MacroAssembler::movptr(Address dst, Register src) {
3406 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3407 }
3408
3409 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3410 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3411 Assembler::movdqu(dst, src);
3412 }
3413
3414 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3415 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3416 Assembler::movdqu(dst, src);
3417 }
3418
3419 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3420 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3421 Assembler::movdqu(dst, src);
3422 }
3423
3424 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3425 if (reachable(src)) {
3426 movdqu(dst, as_Address(src));
3427 } else {
3428 lea(scratchReg, src);
3429 movdqu(dst, Address(scratchReg, 0));
3430 }
3431 }
3432
3433 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3434 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3435 Assembler::vmovdqu(dst, src);
3436 }
3437
3438 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3439 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3440 Assembler::vmovdqu(dst, src);
3441 }
3442
3443 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3444 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3445 Assembler::vmovdqu(dst, src);
3446 }
3447
3448 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3449 if (reachable(src)) {
3450 vmovdqu(dst, as_Address(src));
3451 }
3452 else {
3453 lea(scratch_reg, src);
3454 vmovdqu(dst, Address(scratch_reg, 0));
3455 }
3456 }
3457
3458 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3459 if (reachable(src)) {
3460 Assembler::evmovdquq(dst, as_Address(src), vector_len);
3461 } else {
3462 lea(rscratch, src);
3463 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
3464 }
3465 }
3466
3467 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3468 if (reachable(src)) {
3469 Assembler::movdqa(dst, as_Address(src));
3470 } else {
3471 lea(rscratch1, src);
3472 Assembler::movdqa(dst, Address(rscratch1, 0));
3473 }
3474 }
3475
3476 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3477 if (reachable(src)) {
3478 Assembler::movsd(dst, as_Address(src));
3479 } else {
3480 lea(rscratch1, src);
3481 Assembler::movsd(dst, Address(rscratch1, 0));
3482 }
3483 }
3484
3485 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3486 if (reachable(src)) {
3487 Assembler::movss(dst, as_Address(src));
3488 } else {
3489 lea(rscratch1, src);
3490 Assembler::movss(dst, Address(rscratch1, 0));
3491 }
3492 }
3493
3494 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3495 if (reachable(src)) {
3496 Assembler::mulsd(dst, as_Address(src));
3497 } else {
3498 lea(rscratch1, src);
3499 Assembler::mulsd(dst, Address(rscratch1, 0));
3500 }
3501 }
3502
3503 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3504 if (reachable(src)) {
3505 Assembler::mulss(dst, as_Address(src));
3506 } else {
3507 lea(rscratch1, src);
3508 Assembler::mulss(dst, Address(rscratch1, 0));
3509 }
3510 }
3511
3512 void MacroAssembler::null_check(Register reg, int offset) {
3513 if (needs_explicit_null_check(offset)) {
3514 // provoke OS NULL exception if reg = NULL by
3515 // accessing M[reg] w/o changing any (non-CC) registers
3516 // NOTE: cmpl is plenty here to provoke a segv
3517 cmpptr(rax, Address(reg, 0));
3518 // Note: should probably use testl(rax, Address(reg, 0));
3519 // may be shorter code (however, this version of
3520 // testl needs to be implemented first)
3521 } else {
3522 // nothing to do, (later) access of M[reg + offset]
3523 // will provoke OS NULL exception if reg = NULL
3524 }
3525 }
3526
3527 void MacroAssembler::os_breakpoint() {
3528 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3529 // (e.g., MSVC can't call ps() otherwise)
3530 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3531 }
3532
3533 void MacroAssembler::unimplemented(const char* what) {
3534 const char* buf = NULL;
3535 {
3536 ResourceMark rm;
3537 stringStream ss;
3538 ss.print("unimplemented: %s", what);
3539 buf = code_string(ss.as_string());
3540 }
3541 stop(buf);
3542 }
3543
3544 #ifdef _LP64
3545 #define XSTATE_BV 0x200
3546 #endif
3547
3548 void MacroAssembler::pop_CPU_state() {
3549 pop_FPU_state();
3550 pop_IU_state();
3551 }
3552
3553 void MacroAssembler::pop_FPU_state() {
3554 #ifndef _LP64
3555 frstor(Address(rsp, 0));
3556 #else
3557 fxrstor(Address(rsp, 0));
3558 #endif
3559 addptr(rsp, FPUStateSizeInWords * wordSize);
3560 }
3561
3562 void MacroAssembler::pop_IU_state() {
3563 popa();
3564 LP64_ONLY(addq(rsp, 8));
3565 popf();
3566 }
3567
3568 // Save Integer and Float state
3569 // Warning: Stack must be 16 byte aligned (64bit)
3570 void MacroAssembler::push_CPU_state() {
3571 push_IU_state();
3572 push_FPU_state();
3573 }
3574
3575 void MacroAssembler::push_FPU_state() {
3576 subptr(rsp, FPUStateSizeInWords * wordSize);
3577 #ifndef _LP64
3578 fnsave(Address(rsp, 0));
3579 fwait();
3580 #else
3581 fxsave(Address(rsp, 0));
3582 #endif // LP64
3583 }
3584
3585 void MacroAssembler::push_IU_state() {
3586 // Push flags first because pusha kills them
3587 pushf();
3588 // Make sure rsp stays 16-byte aligned
3589 LP64_ONLY(subq(rsp, 8));
3590 pusha();
3591 }
3592
3593 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3594 if (!java_thread->is_valid()) {
3595 java_thread = rdi;
3596 get_thread(java_thread);
3597 }
3598 // we must set sp to zero to clear frame
3599 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3600 if (clear_fp) {
3601 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3602 }
3603
3604 // Always clear the pc because it could have been set by make_walkable()
3605 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3606
3607 vzeroupper();
3608 }
3609
3610 void MacroAssembler::restore_rax(Register tmp) {
3611 if (tmp == noreg) pop(rax);
3612 else if (tmp != rax) mov(rax, tmp);
3613 }
3614
3615 void MacroAssembler::round_to(Register reg, int modulus) {
3616 addptr(reg, modulus - 1);
3617 andptr(reg, -modulus);
3618 }
3619
3620 void MacroAssembler::save_rax(Register tmp) {
3621 if (tmp == noreg) push(rax);
3622 else if (tmp != rax) mov(tmp, rax);
3623 }
3624
3625 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) {
3626 if (SafepointMechanism::uses_thread_local_poll()) {
3627 #ifdef _LP64
3628 assert(thread_reg == r15_thread, "should be");
3629 #else
3630 if (thread_reg == noreg) {
3631 thread_reg = temp_reg;
3632 get_thread(thread_reg);
3633 }
3634 #endif
3635 testb(Address(thread_reg, Thread::polling_page_offset()), SafepointMechanism::poll_bit());
3636 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3637 } else {
3638 cmp32(ExternalAddress(SafepointSynchronize::address_of_state()),
3639 SafepointSynchronize::_not_synchronized);
3640 jcc(Assembler::notEqual, slow_path);
3641 }
3642 }
3643
3644 // Calls to C land
3645 //
3646 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3647 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3648 // has to be reset to 0. This is required to allow proper stack traversal.
3649 void MacroAssembler::set_last_Java_frame(Register java_thread,
3650 Register last_java_sp,
3651 Register last_java_fp,
3652 address last_java_pc) {
3653 vzeroupper();
3654 // determine java_thread register
3655 if (!java_thread->is_valid()) {
3656 java_thread = rdi;
3657 get_thread(java_thread);
3658 }
3659 // determine last_java_sp register
3660 if (!last_java_sp->is_valid()) {
3661 last_java_sp = rsp;
3662 }
3663
3664 // last_java_fp is optional
3665
3666 if (last_java_fp->is_valid()) {
3667 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3668 }
3669
3670 // last_java_pc is optional
3671
3672 if (last_java_pc != NULL) {
3673 lea(Address(java_thread,
3674 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3675 InternalAddress(last_java_pc));
3676
3677 }
3678 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3679 }
3680
3681 void MacroAssembler::shlptr(Register dst, int imm8) {
3682 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3683 }
3684
3685 void MacroAssembler::shrptr(Register dst, int imm8) {
3686 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3687 }
3688
3689 void MacroAssembler::sign_extend_byte(Register reg) {
3690 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3691 movsbl(reg, reg); // movsxb
3692 } else {
3693 shll(reg, 24);
3694 sarl(reg, 24);
3695 }
3696 }
3697
3698 void MacroAssembler::sign_extend_short(Register reg) {
3699 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3700 movswl(reg, reg); // movsxw
3701 } else {
3702 shll(reg, 16);
3703 sarl(reg, 16);
3704 }
3705 }
3706
3707 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3708 assert(reachable(src), "Address should be reachable");
3709 testl(dst, as_Address(src));
3710 }
3711
3712 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3713 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3714 Assembler::pcmpeqb(dst, src);
3715 }
3716
3717 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3718 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3719 Assembler::pcmpeqw(dst, src);
3720 }
3721
3722 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3723 assert((dst->encoding() < 16),"XMM register should be 0-15");
3724 Assembler::pcmpestri(dst, src, imm8);
3725 }
3726
3727 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3728 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3729 Assembler::pcmpestri(dst, src, imm8);
3730 }
3731
3732 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3733 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3734 Assembler::pmovzxbw(dst, src);
3735 }
3736
3737 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3738 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3739 Assembler::pmovzxbw(dst, src);
3740 }
3741
3742 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3743 assert((src->encoding() < 16),"XMM register should be 0-15");
3744 Assembler::pmovmskb(dst, src);
3745 }
3746
3747 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3748 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3749 Assembler::ptest(dst, src);
3750 }
3751
3752 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3753 if (reachable(src)) {
3754 Assembler::sqrtsd(dst, as_Address(src));
3755 } else {
3756 lea(rscratch1, src);
3757 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3758 }
3759 }
3760
3761 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3762 if (reachable(src)) {
3763 Assembler::sqrtss(dst, as_Address(src));
3764 } else {
3765 lea(rscratch1, src);
3766 Assembler::sqrtss(dst, Address(rscratch1, 0));
3767 }
3768 }
3769
3770 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3771 if (reachable(src)) {
3772 Assembler::subsd(dst, as_Address(src));
3773 } else {
3774 lea(rscratch1, src);
3775 Assembler::subsd(dst, Address(rscratch1, 0));
3776 }
3777 }
3778
3779 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg) {
3780 if (reachable(src)) {
3781 Assembler::roundsd(dst, as_Address(src), rmode);
3782 } else {
3783 lea(scratch_reg, src);
3784 Assembler::roundsd(dst, Address(scratch_reg, 0), rmode);
3785 }
3786 }
3787
3788 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3789 if (reachable(src)) {
3790 Assembler::subss(dst, as_Address(src));
3791 } else {
3792 lea(rscratch1, src);
3793 Assembler::subss(dst, Address(rscratch1, 0));
3794 }
3795 }
3796
3797 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3798 if (reachable(src)) {
3799 Assembler::ucomisd(dst, as_Address(src));
3800 } else {
3801 lea(rscratch1, src);
3802 Assembler::ucomisd(dst, Address(rscratch1, 0));
3803 }
3804 }
3805
3806 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3807 if (reachable(src)) {
3808 Assembler::ucomiss(dst, as_Address(src));
3809 } else {
3810 lea(rscratch1, src);
3811 Assembler::ucomiss(dst, Address(rscratch1, 0));
3812 }
3813 }
3814
3815 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3816 // Used in sign-bit flipping with aligned address.
3817 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3818 if (reachable(src)) {
3819 Assembler::xorpd(dst, as_Address(src));
3820 } else {
3821 lea(scratch_reg, src);
3822 Assembler::xorpd(dst, Address(scratch_reg, 0));
3823 }
3824 }
3825
3826 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3827 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3828 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3829 }
3830 else {
3831 Assembler::xorpd(dst, src);
3832 }
3833 }
3834
3835 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3836 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3837 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3838 } else {
3839 Assembler::xorps(dst, src);
3840 }
3841 }
3842
3843 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3844 // Used in sign-bit flipping with aligned address.
3845 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3846 if (reachable(src)) {
3847 Assembler::xorps(dst, as_Address(src));
3848 } else {
3849 lea(scratch_reg, src);
3850 Assembler::xorps(dst, Address(scratch_reg, 0));
3851 }
3852 }
3853
3854 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3855 // Used in sign-bit flipping with aligned address.
3856 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3857 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3858 if (reachable(src)) {
3859 Assembler::pshufb(dst, as_Address(src));
3860 } else {
3861 lea(rscratch1, src);
3862 Assembler::pshufb(dst, Address(rscratch1, 0));
3863 }
3864 }
3865
3866 // AVX 3-operands instructions
3867
3868 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3869 if (reachable(src)) {
3870 vaddsd(dst, nds, as_Address(src));
3871 } else {
3872 lea(rscratch1, src);
3873 vaddsd(dst, nds, Address(rscratch1, 0));
3874 }
3875 }
3876
3877 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3878 if (reachable(src)) {
3879 vaddss(dst, nds, as_Address(src));
3880 } else {
3881 lea(rscratch1, src);
3882 vaddss(dst, nds, Address(rscratch1, 0));
3883 }
3884 }
3885
3886 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3887 assert(UseAVX > 0, "requires some form of AVX");
3888 if (reachable(src)) {
3889 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3890 } else {
3891 lea(rscratch, src);
3892 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3893 }
3894 }
3895
3896 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3897 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3898 vandps(dst, nds, negate_field, vector_len);
3899 }
3900
3901 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3902 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3903 vandpd(dst, nds, negate_field, vector_len);
3904 }
3905
3906 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3907 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3908 Assembler::vpaddb(dst, nds, src, vector_len);
3909 }
3910
3911 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3912 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3913 Assembler::vpaddb(dst, nds, src, vector_len);
3914 }
3915
3916 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3917 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3918 Assembler::vpaddw(dst, nds, src, vector_len);
3919 }
3920
3921 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3922 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3923 Assembler::vpaddw(dst, nds, src, vector_len);
3924 }
3925
3926 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3927 if (reachable(src)) {
3928 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3929 } else {
3930 lea(scratch_reg, src);
3931 Assembler::vpand(dst, nds, Address(scratch_reg, 0), vector_len);
3932 }
3933 }
3934
3935 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
3936 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3937 Assembler::vpbroadcastw(dst, src, vector_len);
3938 }
3939
3940 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3941 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3942 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3943 }
3944
3945 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3946 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3947 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3948 }
3949
3950 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3951 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3952 Assembler::vpmovzxbw(dst, src, vector_len);
3953 }
3954
3955 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
3956 assert((src->encoding() < 16),"XMM register should be 0-15");
3957 Assembler::vpmovmskb(dst, src);
3958 }
3959
3960 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3961 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3962 Assembler::vpmullw(dst, nds, src, vector_len);
3963 }
3964
3965 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3966 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3967 Assembler::vpmullw(dst, nds, src, vector_len);
3968 }
3969
3970 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3971 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3972 Assembler::vpsubb(dst, nds, src, vector_len);
3973 }
3974
3975 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3976 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3977 Assembler::vpsubb(dst, nds, src, vector_len);
3978 }
3979
3980 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3981 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3982 Assembler::vpsubw(dst, nds, src, vector_len);
3983 }
3984
3985 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3986 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3987 Assembler::vpsubw(dst, nds, src, vector_len);
3988 }
3989
3990 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3991 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3992 Assembler::vpsraw(dst, nds, shift, vector_len);
3993 }
3994
3995 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3996 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3997 Assembler::vpsraw(dst, nds, shift, vector_len);
3998 }
3999
4000 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4001 assert(UseAVX > 2,"");
4002 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
4003 vector_len = 2;
4004 }
4005 Assembler::evpsraq(dst, nds, shift, vector_len);
4006 }
4007
4008 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4009 assert(UseAVX > 2,"");
4010 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
4011 vector_len = 2;
4012 }
4013 Assembler::evpsraq(dst, nds, shift, vector_len);
4014 }
4015
4016 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4017 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4018 Assembler::vpsrlw(dst, nds, shift, vector_len);
4019 }
4020
4021 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4022 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4023 Assembler::vpsrlw(dst, nds, shift, vector_len);
4024 }
4025
4026 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4027 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4028 Assembler::vpsllw(dst, nds, shift, vector_len);
4029 }
4030
4031 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4032 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4033 Assembler::vpsllw(dst, nds, shift, vector_len);
4034 }
4035
4036 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4037 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
4038 Assembler::vptest(dst, src);
4039 }
4040
4041 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4042 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4043 Assembler::punpcklbw(dst, src);
4044 }
4045
4046 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
4047 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
4048 Assembler::pshufd(dst, src, mode);
4049 }
4050
4051 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4052 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4053 Assembler::pshuflw(dst, src, mode);
4054 }
4055
4056 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4057 if (reachable(src)) {
4058 vandpd(dst, nds, as_Address(src), vector_len);
4059 } else {
4060 lea(scratch_reg, src);
4061 vandpd(dst, nds, Address(scratch_reg, 0), vector_len);
4062 }
4063 }
4064
4065 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4066 if (reachable(src)) {
4067 vandps(dst, nds, as_Address(src), vector_len);
4068 } else {
4069 lea(scratch_reg, src);
4070 vandps(dst, nds, Address(scratch_reg, 0), vector_len);
4071 }
4072 }
4073
4074 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4075 if (reachable(src)) {
4076 vdivsd(dst, nds, as_Address(src));
4077 } else {
4078 lea(rscratch1, src);
4079 vdivsd(dst, nds, Address(rscratch1, 0));
4080 }
4081 }
4082
4083 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4084 if (reachable(src)) {
4085 vdivss(dst, nds, as_Address(src));
4086 } else {
4087 lea(rscratch1, src);
4088 vdivss(dst, nds, Address(rscratch1, 0));
4089 }
4090 }
4091
4092 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4093 if (reachable(src)) {
4094 vmulsd(dst, nds, as_Address(src));
4095 } else {
4096 lea(rscratch1, src);
4097 vmulsd(dst, nds, Address(rscratch1, 0));
4098 }
4099 }
4100
4101 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4102 if (reachable(src)) {
4103 vmulss(dst, nds, as_Address(src));
4104 } else {
4105 lea(rscratch1, src);
4106 vmulss(dst, nds, Address(rscratch1, 0));
4107 }
4108 }
4109
4110 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4111 if (reachable(src)) {
4112 vsubsd(dst, nds, as_Address(src));
4113 } else {
4114 lea(rscratch1, src);
4115 vsubsd(dst, nds, Address(rscratch1, 0));
4116 }
4117 }
4118
4119 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4120 if (reachable(src)) {
4121 vsubss(dst, nds, as_Address(src));
4122 } else {
4123 lea(rscratch1, src);
4124 vsubss(dst, nds, Address(rscratch1, 0));
4125 }
4126 }
4127
4128 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4129 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4130 vxorps(dst, nds, src, Assembler::AVX_128bit);
4131 }
4132
4133 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4134 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4135 vxorpd(dst, nds, src, Assembler::AVX_128bit);
4136 }
4137
4138 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4139 if (reachable(src)) {
4140 vxorpd(dst, nds, as_Address(src), vector_len);
4141 } else {
4142 lea(scratch_reg, src);
4143 vxorpd(dst, nds, Address(scratch_reg, 0), vector_len);
4144 }
4145 }
4146
4147 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4148 if (reachable(src)) {
4149 vxorps(dst, nds, as_Address(src), vector_len);
4150 } else {
4151 lea(scratch_reg, src);
4152 vxorps(dst, nds, Address(scratch_reg, 0), vector_len);
4153 }
4154 }
4155
4156 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4157 if (UseAVX > 1 || (vector_len < 1)) {
4158 if (reachable(src)) {
4159 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
4160 } else {
4161 lea(scratch_reg, src);
4162 Assembler::vpxor(dst, nds, Address(scratch_reg, 0), vector_len);
4163 }
4164 }
4165 else {
4166 MacroAssembler::vxorpd(dst, nds, src, vector_len, scratch_reg);
4167 }
4168 }
4169
4170 //-------------------------------------------------------------------------------------------
4171 #ifdef COMPILER2
4172 // Generic instructions support for use in .ad files C2 code generation
4173
4174 void MacroAssembler::vabsnegd(int opcode, XMMRegister dst, XMMRegister src, Register scr) {
4175 if (dst != src) {
4176 movdqu(dst, src);
4177 }
4178 if (opcode == Op_AbsVD) {
4179 andpd(dst, ExternalAddress(StubRoutines::x86::vector_double_sign_mask()), scr);
4180 } else {
4181 assert((opcode == Op_NegVD),"opcode should be Op_NegD");
4182 xorpd(dst, ExternalAddress(StubRoutines::x86::vector_double_sign_flip()), scr);
4183 }
4184 }
4185
4186 void MacroAssembler::vabsnegd(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr) {
4187 if (opcode == Op_AbsVD) {
4188 vandpd(dst, src, ExternalAddress(StubRoutines::x86::vector_double_sign_mask()), vector_len, scr);
4189 } else {
4190 assert((opcode == Op_NegVD),"opcode should be Op_NegD");
4191 vxorpd(dst, src, ExternalAddress(StubRoutines::x86::vector_double_sign_flip()), vector_len, scr);
4192 }
4193 }
4194
4195 void MacroAssembler::vabsnegf(int opcode, XMMRegister dst, XMMRegister src, Register scr) {
4196 if (dst != src) {
4197 movdqu(dst, src);
4198 }
4199 if (opcode == Op_AbsVF) {
4200 andps(dst, ExternalAddress(StubRoutines::x86::vector_float_sign_mask()), scr);
4201 } else {
4202 assert((opcode == Op_NegVF),"opcode should be Op_NegF");
4203 xorps(dst, ExternalAddress(StubRoutines::x86::vector_float_sign_flip()), scr);
4204 }
4205 }
4206
4207 void MacroAssembler::vabsnegf(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr) {
4208 if (opcode == Op_AbsVF) {
4209 vandps(dst, src, ExternalAddress(StubRoutines::x86::vector_float_sign_mask()), vector_len, scr);
4210 } else {
4211 assert((opcode == Op_NegVF),"opcode should be Op_NegF");
4212 vxorps(dst, src, ExternalAddress(StubRoutines::x86::vector_float_sign_flip()), vector_len, scr);
4213 }
4214 }
4215
4216 void MacroAssembler::vextendbw(bool sign, XMMRegister dst, XMMRegister src) {
4217 if (sign) {
4218 pmovsxbw(dst, src);
4219 } else {
4220 pmovzxbw(dst, src);
4221 }
4222 }
4223
4224 void MacroAssembler::vextendbw(bool sign, XMMRegister dst, XMMRegister src, int vector_len) {
4225 if (sign) {
4226 vpmovsxbw(dst, src, vector_len);
4227 } else {
4228 vpmovzxbw(dst, src, vector_len);
4229 }
4230 }
4231
4232 void MacroAssembler::vshiftd(int opcode, XMMRegister dst, XMMRegister src) {
4233 if (opcode == Op_RShiftVI) {
4234 psrad(dst, src);
4235 } else if (opcode == Op_LShiftVI) {
4236 pslld(dst, src);
4237 } else {
4238 assert((opcode == Op_URShiftVI),"opcode should be Op_URShiftVI");
4239 psrld(dst, src);
4240 }
4241 }
4242
4243 void MacroAssembler::vshiftd(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4244 if (opcode == Op_RShiftVI) {
4245 vpsrad(dst, nds, src, vector_len);
4246 } else if (opcode == Op_LShiftVI) {
4247 vpslld(dst, nds, src, vector_len);
4248 } else {
4249 assert((opcode == Op_URShiftVI),"opcode should be Op_URShiftVI");
4250 vpsrld(dst, nds, src, vector_len);
4251 }
4252 }
4253
4254 void MacroAssembler::vshiftw(int opcode, XMMRegister dst, XMMRegister src) {
4255 if ((opcode == Op_RShiftVS) || (opcode == Op_RShiftVB)) {
4256 psraw(dst, src);
4257 } else if ((opcode == Op_LShiftVS) || (opcode == Op_LShiftVB)) {
4258 psllw(dst, src);
4259 } else {
4260 assert(((opcode == Op_URShiftVS) || (opcode == Op_URShiftVB)),"opcode should be one of Op_URShiftVS or Op_URShiftVB");
4261 psrlw(dst, src);
4262 }
4263 }
4264
4265 void MacroAssembler::vshiftw(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4266 if ((opcode == Op_RShiftVS) || (opcode == Op_RShiftVB)) {
4267 vpsraw(dst, nds, src, vector_len);
4268 } else if ((opcode == Op_LShiftVS) || (opcode == Op_LShiftVB)) {
4269 vpsllw(dst, nds, src, vector_len);
4270 } else {
4271 assert(((opcode == Op_URShiftVS) || (opcode == Op_URShiftVB)),"opcode should be one of Op_URShiftVS or Op_URShiftVB");
4272 vpsrlw(dst, nds, src, vector_len);
4273 }
4274 }
4275
4276 void MacroAssembler::vshiftq(int opcode, XMMRegister dst, XMMRegister src) {
4277 if (opcode == Op_RShiftVL) {
4278 psrlq(dst, src); // using srl to implement sra on pre-avs512 systems
4279 } else if (opcode == Op_LShiftVL) {
4280 psllq(dst, src);
4281 } else {
4282 assert((opcode == Op_URShiftVL),"opcode should be Op_URShiftVL");
4283 psrlq(dst, src);
4284 }
4285 }
4286
4287 void MacroAssembler::vshiftq(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4288 if (opcode == Op_RShiftVL) {
4289 evpsraq(dst, nds, src, vector_len);
4290 } else if (opcode == Op_LShiftVL) {
4291 vpsllq(dst, nds, src, vector_len);
4292 } else {
4293 assert((opcode == Op_URShiftVL),"opcode should be Op_URShiftVL");
4294 vpsrlq(dst, nds, src, vector_len);
4295 }
4296 }
4297 #endif
4298 //-------------------------------------------------------------------------------------------
4299
4300 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
4301 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
4302 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
4303 // The inverted mask is sign-extended
4304 andptr(possibly_jweak, inverted_jweak_mask);
4305 }
4306
4307 void MacroAssembler::resolve_jobject(Register value,
4308 Register thread,
4309 Register tmp) {
4310 assert_different_registers(value, thread, tmp);
4311 Label done, not_weak;
4312 testptr(value, value);
4313 jcc(Assembler::zero, done); // Use NULL as-is.
4314 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
4315 jcc(Assembler::zero, not_weak);
4316 // Resolve jweak.
4317 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4318 value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
4319 verify_oop(value);
4320 jmp(done);
4321 bind(not_weak);
4322 // Resolve (untagged) jobject.
4323 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
4324 verify_oop(value);
4325 bind(done);
4326 }
4327
4328 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4329 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4330 }
4331
4332 // Force generation of a 4 byte immediate value even if it fits into 8bit
4333 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4334 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4335 }
4336
4337 void MacroAssembler::subptr(Register dst, Register src) {
4338 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4339 }
4340
4341 // C++ bool manipulation
4342 void MacroAssembler::testbool(Register dst) {
4343 if(sizeof(bool) == 1)
4344 testb(dst, 0xff);
4345 else if(sizeof(bool) == 2) {
4346 // testw implementation needed for two byte bools
4347 ShouldNotReachHere();
4348 } else if(sizeof(bool) == 4)
4349 testl(dst, dst);
4350 else
4351 // unsupported
4352 ShouldNotReachHere();
4353 }
4354
4355 void MacroAssembler::testptr(Register dst, Register src) {
4356 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4357 }
4358
4359 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4360 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4361 Register var_size_in_bytes,
4362 int con_size_in_bytes,
4363 Register t1,
4364 Register t2,
4365 Label& slow_case) {
4366 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4367 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4368 }
4369
4370 // Defines obj, preserves var_size_in_bytes
4371 void MacroAssembler::eden_allocate(Register thread, Register obj,
4372 Register var_size_in_bytes,
4373 int con_size_in_bytes,
4374 Register t1,
4375 Label& slow_case) {
4376 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4377 bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
4378 }
4379
4380 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4381 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4382 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4383 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4384 Label done;
4385
4386 testptr(length_in_bytes, length_in_bytes);
4387 jcc(Assembler::zero, done);
4388
4389 // initialize topmost word, divide index by 2, check if odd and test if zero
4390 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4391 #ifdef ASSERT
4392 {
4393 Label L;
4394 testptr(length_in_bytes, BytesPerWord - 1);
4395 jcc(Assembler::zero, L);
4396 stop("length must be a multiple of BytesPerWord");
4397 bind(L);
4398 }
4399 #endif
4400 Register index = length_in_bytes;
4401 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4402 if (UseIncDec) {
4403 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4404 } else {
4405 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4406 shrptr(index, 1);
4407 }
4408 #ifndef _LP64
4409 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4410 {
4411 Label even;
4412 // note: if index was a multiple of 8, then it cannot
4413 // be 0 now otherwise it must have been 0 before
4414 // => if it is even, we don't need to check for 0 again
4415 jcc(Assembler::carryClear, even);
4416 // clear topmost word (no jump would be needed if conditional assignment worked here)
4417 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4418 // index could be 0 now, must check again
4419 jcc(Assembler::zero, done);
4420 bind(even);
4421 }
4422 #endif // !_LP64
4423 // initialize remaining object fields: index is a multiple of 2 now
4424 {
4425 Label loop;
4426 bind(loop);
4427 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4428 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4429 decrement(index);
4430 jcc(Assembler::notZero, loop);
4431 }
4432
4433 bind(done);
4434 }
4435
4436 // Look up the method for a megamorphic invokeinterface call.
4437 // The target method is determined by <intf_klass, itable_index>.
4438 // The receiver klass is in recv_klass.
4439 // On success, the result will be in method_result, and execution falls through.
4440 // On failure, execution transfers to the given label.
4441 void MacroAssembler::lookup_interface_method(Register recv_klass,
4442 Register intf_klass,
4443 RegisterOrConstant itable_index,
4444 Register method_result,
4445 Register scan_temp,
4446 Label& L_no_such_interface,
4447 bool return_method) {
4448 assert_different_registers(recv_klass, intf_klass, scan_temp);
4449 assert_different_registers(method_result, intf_klass, scan_temp);
4450 assert(recv_klass != method_result || !return_method,
4451 "recv_klass can be destroyed when method isn't needed");
4452
4453 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4454 "caller must use same register for non-constant itable index as for method");
4455
4456 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4457 int vtable_base = in_bytes(Klass::vtable_start_offset());
4458 int itentry_off = itableMethodEntry::method_offset_in_bytes();
4459 int scan_step = itableOffsetEntry::size() * wordSize;
4460 int vte_size = vtableEntry::size_in_bytes();
4461 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4462 assert(vte_size == wordSize, "else adjust times_vte_scale");
4463
4464 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4465
4466 // %%% Could store the aligned, prescaled offset in the klassoop.
4467 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4468
4469 if (return_method) {
4470 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4471 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4472 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4473 }
4474
4475 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4476 // if (scan->interface() == intf) {
4477 // result = (klass + scan->offset() + itable_index);
4478 // }
4479 // }
4480 Label search, found_method;
4481
4482 for (int peel = 1; peel >= 0; peel--) {
4483 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4484 cmpptr(intf_klass, method_result);
4485
4486 if (peel) {
4487 jccb(Assembler::equal, found_method);
4488 } else {
4489 jccb(Assembler::notEqual, search);
4490 // (invert the test to fall through to found_method...)
4491 }
4492
4493 if (!peel) break;
4494
4495 bind(search);
4496
4497 // Check that the previous entry is non-null. A null entry means that
4498 // the receiver class doesn't implement the interface, and wasn't the
4499 // same as when the caller was compiled.
4500 testptr(method_result, method_result);
4501 jcc(Assembler::zero, L_no_such_interface);
4502 addptr(scan_temp, scan_step);
4503 }
4504
4505 bind(found_method);
4506
4507 if (return_method) {
4508 // Got a hit.
4509 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4510 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4511 }
4512 }
4513
4514
4515 // virtual method calling
4516 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4517 RegisterOrConstant vtable_index,
4518 Register method_result) {
4519 const int base = in_bytes(Klass::vtable_start_offset());
4520 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4521 Address vtable_entry_addr(recv_klass,
4522 vtable_index, Address::times_ptr,
4523 base + vtableEntry::method_offset_in_bytes());
4524 movptr(method_result, vtable_entry_addr);
4525 }
4526
4527
4528 void MacroAssembler::check_klass_subtype(Register sub_klass,
4529 Register super_klass,
4530 Register temp_reg,
4531 Label& L_success) {
4532 Label L_failure;
4533 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
4534 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4535 bind(L_failure);
4536 }
4537
4538
4539 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4540 Register super_klass,
4541 Register temp_reg,
4542 Label* L_success,
4543 Label* L_failure,
4544 Label* L_slow_path,
4545 RegisterOrConstant super_check_offset) {
4546 assert_different_registers(sub_klass, super_klass, temp_reg);
4547 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4548 if (super_check_offset.is_register()) {
4549 assert_different_registers(sub_klass, super_klass,
4550 super_check_offset.as_register());
4551 } else if (must_load_sco) {
4552 assert(temp_reg != noreg, "supply either a temp or a register offset");
4553 }
4554
4555 Label L_fallthrough;
4556 int label_nulls = 0;
4557 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4558 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4559 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4560 assert(label_nulls <= 1, "at most one NULL in the batch");
4561
4562 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4563 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4564 Address super_check_offset_addr(super_klass, sco_offset);
4565
4566 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4567 // range of a jccb. If this routine grows larger, reconsider at
4568 // least some of these.
4569 #define local_jcc(assembler_cond, label) \
4570 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4571 else jcc( assembler_cond, label) /*omit semi*/
4572
4573 // Hacked jmp, which may only be used just before L_fallthrough.
4574 #define final_jmp(label) \
4575 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4576 else jmp(label) /*omit semi*/
4577
4578 // If the pointers are equal, we are done (e.g., String[] elements).
4579 // This self-check enables sharing of secondary supertype arrays among
4580 // non-primary types such as array-of-interface. Otherwise, each such
4581 // type would need its own customized SSA.
4582 // We move this check to the front of the fast path because many
4583 // type checks are in fact trivially successful in this manner,
4584 // so we get a nicely predicted branch right at the start of the check.
4585 cmpptr(sub_klass, super_klass);
4586 local_jcc(Assembler::equal, *L_success);
4587
4588 // Check the supertype display:
4589 if (must_load_sco) {
4590 // Positive movl does right thing on LP64.
4591 movl(temp_reg, super_check_offset_addr);
4592 super_check_offset = RegisterOrConstant(temp_reg);
4593 }
4594 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4595 cmpptr(super_klass, super_check_addr); // load displayed supertype
4596
4597 // This check has worked decisively for primary supers.
4598 // Secondary supers are sought in the super_cache ('super_cache_addr').
4599 // (Secondary supers are interfaces and very deeply nested subtypes.)
4600 // This works in the same check above because of a tricky aliasing
4601 // between the super_cache and the primary super display elements.
4602 // (The 'super_check_addr' can address either, as the case requires.)
4603 // Note that the cache is updated below if it does not help us find
4604 // what we need immediately.
4605 // So if it was a primary super, we can just fail immediately.
4606 // Otherwise, it's the slow path for us (no success at this point).
4607
4608 if (super_check_offset.is_register()) {
4609 local_jcc(Assembler::equal, *L_success);
4610 cmpl(super_check_offset.as_register(), sc_offset);
4611 if (L_failure == &L_fallthrough) {
4612 local_jcc(Assembler::equal, *L_slow_path);
4613 } else {
4614 local_jcc(Assembler::notEqual, *L_failure);
4615 final_jmp(*L_slow_path);
4616 }
4617 } else if (super_check_offset.as_constant() == sc_offset) {
4618 // Need a slow path; fast failure is impossible.
4619 if (L_slow_path == &L_fallthrough) {
4620 local_jcc(Assembler::equal, *L_success);
4621 } else {
4622 local_jcc(Assembler::notEqual, *L_slow_path);
4623 final_jmp(*L_success);
4624 }
4625 } else {
4626 // No slow path; it's a fast decision.
4627 if (L_failure == &L_fallthrough) {
4628 local_jcc(Assembler::equal, *L_success);
4629 } else {
4630 local_jcc(Assembler::notEqual, *L_failure);
4631 final_jmp(*L_success);
4632 }
4633 }
4634
4635 bind(L_fallthrough);
4636
4637 #undef local_jcc
4638 #undef final_jmp
4639 }
4640
4641
4642 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4643 Register super_klass,
4644 Register temp_reg,
4645 Register temp2_reg,
4646 Label* L_success,
4647 Label* L_failure,
4648 bool set_cond_codes) {
4649 assert_different_registers(sub_klass, super_klass, temp_reg);
4650 if (temp2_reg != noreg)
4651 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4652 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4653
4654 Label L_fallthrough;
4655 int label_nulls = 0;
4656 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4657 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4658 assert(label_nulls <= 1, "at most one NULL in the batch");
4659
4660 // a couple of useful fields in sub_klass:
4661 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4662 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4663 Address secondary_supers_addr(sub_klass, ss_offset);
4664 Address super_cache_addr( sub_klass, sc_offset);
4665
4666 // Do a linear scan of the secondary super-klass chain.
4667 // This code is rarely used, so simplicity is a virtue here.
4668 // The repne_scan instruction uses fixed registers, which we must spill.
4669 // Don't worry too much about pre-existing connections with the input regs.
4670
4671 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4672 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4673
4674 // Get super_klass value into rax (even if it was in rdi or rcx).
4675 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4676 if (super_klass != rax || UseCompressedOops) {
4677 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4678 mov(rax, super_klass);
4679 }
4680 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4681 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4682
4683 #ifndef PRODUCT
4684 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4685 ExternalAddress pst_counter_addr((address) pst_counter);
4686 NOT_LP64( incrementl(pst_counter_addr) );
4687 LP64_ONLY( lea(rcx, pst_counter_addr) );
4688 LP64_ONLY( incrementl(Address(rcx, 0)) );
4689 #endif //PRODUCT
4690
4691 // We will consult the secondary-super array.
4692 movptr(rdi, secondary_supers_addr);
4693 // Load the array length. (Positive movl does right thing on LP64.)
4694 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4695 // Skip to start of data.
4696 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4697
4698 // Scan RCX words at [RDI] for an occurrence of RAX.
4699 // Set NZ/Z based on last compare.
4700 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4701 // not change flags (only scas instruction which is repeated sets flags).
4702 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4703
4704 testptr(rax,rax); // Set Z = 0
4705 repne_scan();
4706
4707 // Unspill the temp. registers:
4708 if (pushed_rdi) pop(rdi);
4709 if (pushed_rcx) pop(rcx);
4710 if (pushed_rax) pop(rax);
4711
4712 if (set_cond_codes) {
4713 // Special hack for the AD files: rdi is guaranteed non-zero.
4714 assert(!pushed_rdi, "rdi must be left non-NULL");
4715 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4716 }
4717
4718 if (L_failure == &L_fallthrough)
4719 jccb(Assembler::notEqual, *L_failure);
4720 else jcc(Assembler::notEqual, *L_failure);
4721
4722 // Success. Cache the super we found and proceed in triumph.
4723 movptr(super_cache_addr, super_klass);
4724
4725 if (L_success != &L_fallthrough) {
4726 jmp(*L_success);
4727 }
4728
4729 #undef IS_A_TEMP
4730
4731 bind(L_fallthrough);
4732 }
4733
4734 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
4735 assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required");
4736
4737 Label L_fallthrough;
4738 if (L_fast_path == NULL) {
4739 L_fast_path = &L_fallthrough;
4740 } else if (L_slow_path == NULL) {
4741 L_slow_path = &L_fallthrough;
4742 }
4743
4744 // Fast path check: class is fully initialized
4745 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4746 jcc(Assembler::equal, *L_fast_path);
4747
4748 // Fast path check: current thread is initializer thread
4749 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
4750 if (L_slow_path == &L_fallthrough) {
4751 jcc(Assembler::equal, *L_fast_path);
4752 bind(*L_slow_path);
4753 } else if (L_fast_path == &L_fallthrough) {
4754 jcc(Assembler::notEqual, *L_slow_path);
4755 bind(*L_fast_path);
4756 } else {
4757 Unimplemented();
4758 }
4759 }
4760
4761 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4762 if (VM_Version::supports_cmov()) {
4763 cmovl(cc, dst, src);
4764 } else {
4765 Label L;
4766 jccb(negate_condition(cc), L);
4767 movl(dst, src);
4768 bind(L);
4769 }
4770 }
4771
4772 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4773 if (VM_Version::supports_cmov()) {
4774 cmovl(cc, dst, src);
4775 } else {
4776 Label L;
4777 jccb(negate_condition(cc), L);
4778 movl(dst, src);
4779 bind(L);
4780 }
4781 }
4782
4783 void MacroAssembler::verify_oop(Register reg, const char* s) {
4784 if (!VerifyOops) return;
4785
4786 // Pass register number to verify_oop_subroutine
4787 const char* b = NULL;
4788 {
4789 ResourceMark rm;
4790 stringStream ss;
4791 ss.print("verify_oop: %s: %s", reg->name(), s);
4792 b = code_string(ss.as_string());
4793 }
4794 BLOCK_COMMENT("verify_oop {");
4795 #ifdef _LP64
4796 push(rscratch1); // save r10, trashed by movptr()
4797 #endif
4798 push(rax); // save rax,
4799 push(reg); // pass register argument
4800 ExternalAddress buffer((address) b);
4801 // avoid using pushptr, as it modifies scratch registers
4802 // and our contract is not to modify anything
4803 movptr(rax, buffer.addr());
4804 push(rax);
4805 // call indirectly to solve generation ordering problem
4806 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4807 call(rax);
4808 // Caller pops the arguments (oop, message) and restores rax, r10
4809 BLOCK_COMMENT("} verify_oop");
4810 }
4811
4812
4813 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
4814 Register tmp,
4815 int offset) {
4816 intptr_t value = *delayed_value_addr;
4817 if (value != 0)
4818 return RegisterOrConstant(value + offset);
4819
4820 // load indirectly to solve generation ordering problem
4821 movptr(tmp, ExternalAddress((address) delayed_value_addr));
4822
4823 #ifdef ASSERT
4824 { Label L;
4825 testptr(tmp, tmp);
4826 if (WizardMode) {
4827 const char* buf = NULL;
4828 {
4829 ResourceMark rm;
4830 stringStream ss;
4831 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
4832 buf = code_string(ss.as_string());
4833 }
4834 jcc(Assembler::notZero, L);
4835 STOP(buf);
4836 } else {
4837 jccb(Assembler::notZero, L);
4838 hlt();
4839 }
4840 bind(L);
4841 }
4842 #endif
4843
4844 if (offset != 0)
4845 addptr(tmp, offset);
4846
4847 return RegisterOrConstant(tmp);
4848 }
4849
4850
4851 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4852 int extra_slot_offset) {
4853 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4854 int stackElementSize = Interpreter::stackElementSize;
4855 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4856 #ifdef ASSERT
4857 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4858 assert(offset1 - offset == stackElementSize, "correct arithmetic");
4859 #endif
4860 Register scale_reg = noreg;
4861 Address::ScaleFactor scale_factor = Address::no_scale;
4862 if (arg_slot.is_constant()) {
4863 offset += arg_slot.as_constant() * stackElementSize;
4864 } else {
4865 scale_reg = arg_slot.as_register();
4866 scale_factor = Address::times(stackElementSize);
4867 }
4868 offset += wordSize; // return PC is on stack
4869 return Address(rsp, scale_reg, scale_factor, offset);
4870 }
4871
4872
4873 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
4874 if (!VerifyOops) return;
4875
4876 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
4877 // Pass register number to verify_oop_subroutine
4878 const char* b = NULL;
4879 {
4880 ResourceMark rm;
4881 stringStream ss;
4882 ss.print("verify_oop_addr: %s", s);
4883 b = code_string(ss.as_string());
4884 }
4885 #ifdef _LP64
4886 push(rscratch1); // save r10, trashed by movptr()
4887 #endif
4888 push(rax); // save rax,
4889 // addr may contain rsp so we will have to adjust it based on the push
4890 // we just did (and on 64 bit we do two pushes)
4891 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4892 // stores rax into addr which is backwards of what was intended.
4893 if (addr.uses(rsp)) {
4894 lea(rax, addr);
4895 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
4896 } else {
4897 pushptr(addr);
4898 }
4899
4900 ExternalAddress buffer((address) b);
4901 // pass msg argument
4902 // avoid using pushptr, as it modifies scratch registers
4903 // and our contract is not to modify anything
4904 movptr(rax, buffer.addr());
4905 push(rax);
4906
4907 // call indirectly to solve generation ordering problem
4908 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4909 call(rax);
4910 // Caller pops the arguments (addr, message) and restores rax, r10.
4911 }
4912
4913 void MacroAssembler::verify_tlab() {
4914 #ifdef ASSERT
4915 if (UseTLAB && VerifyOops) {
4916 Label next, ok;
4917 Register t1 = rsi;
4918 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
4919
4920 push(t1);
4921 NOT_LP64(push(thread_reg));
4922 NOT_LP64(get_thread(thread_reg));
4923
4924 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4925 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4926 jcc(Assembler::aboveEqual, next);
4927 STOP("assert(top >= start)");
4928 should_not_reach_here();
4929
4930 bind(next);
4931 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4932 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4933 jcc(Assembler::aboveEqual, ok);
4934 STOP("assert(top <= end)");
4935 should_not_reach_here();
4936
4937 bind(ok);
4938 NOT_LP64(pop(thread_reg));
4939 pop(t1);
4940 }
4941 #endif
4942 }
4943
4944 class ControlWord {
4945 public:
4946 int32_t _value;
4947
4948 int rounding_control() const { return (_value >> 10) & 3 ; }
4949 int precision_control() const { return (_value >> 8) & 3 ; }
4950 bool precision() const { return ((_value >> 5) & 1) != 0; }
4951 bool underflow() const { return ((_value >> 4) & 1) != 0; }
4952 bool overflow() const { return ((_value >> 3) & 1) != 0; }
4953 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
4954 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
4955 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4956
4957 void print() const {
4958 // rounding control
4959 const char* rc;
4960 switch (rounding_control()) {
4961 case 0: rc = "round near"; break;
4962 case 1: rc = "round down"; break;
4963 case 2: rc = "round up "; break;
4964 case 3: rc = "chop "; break;
4965 };
4966 // precision control
4967 const char* pc;
4968 switch (precision_control()) {
4969 case 0: pc = "24 bits "; break;
4970 case 1: pc = "reserved"; break;
4971 case 2: pc = "53 bits "; break;
4972 case 3: pc = "64 bits "; break;
4973 };
4974 // flags
4975 char f[9];
4976 f[0] = ' ';
4977 f[1] = ' ';
4978 f[2] = (precision ()) ? 'P' : 'p';
4979 f[3] = (underflow ()) ? 'U' : 'u';
4980 f[4] = (overflow ()) ? 'O' : 'o';
4981 f[5] = (zero_divide ()) ? 'Z' : 'z';
4982 f[6] = (denormalized()) ? 'D' : 'd';
4983 f[7] = (invalid ()) ? 'I' : 'i';
4984 f[8] = '\x0';
4985 // output
4986 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4987 }
4988
4989 };
4990
4991 class StatusWord {
4992 public:
4993 int32_t _value;
4994
4995 bool busy() const { return ((_value >> 15) & 1) != 0; }
4996 bool C3() const { return ((_value >> 14) & 1) != 0; }
4997 bool C2() const { return ((_value >> 10) & 1) != 0; }
4998 bool C1() const { return ((_value >> 9) & 1) != 0; }
4999 bool C0() const { return ((_value >> 8) & 1) != 0; }
5000 int top() const { return (_value >> 11) & 7 ; }
5001 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5002 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5003 bool precision() const { return ((_value >> 5) & 1) != 0; }
5004 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5005 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5006 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5007 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5008 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5009
5010 void print() const {
5011 // condition codes
5012 char c[5];
5013 c[0] = (C3()) ? '3' : '-';
5014 c[1] = (C2()) ? '2' : '-';
5015 c[2] = (C1()) ? '1' : '-';
5016 c[3] = (C0()) ? '0' : '-';
5017 c[4] = '\x0';
5018 // flags
5019 char f[9];
5020 f[0] = (error_status()) ? 'E' : '-';
5021 f[1] = (stack_fault ()) ? 'S' : '-';
5022 f[2] = (precision ()) ? 'P' : '-';
5023 f[3] = (underflow ()) ? 'U' : '-';
5024 f[4] = (overflow ()) ? 'O' : '-';
5025 f[5] = (zero_divide ()) ? 'Z' : '-';
5026 f[6] = (denormalized()) ? 'D' : '-';
5027 f[7] = (invalid ()) ? 'I' : '-';
5028 f[8] = '\x0';
5029 // output
5030 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5031 }
5032
5033 };
5034
5035 class TagWord {
5036 public:
5037 int32_t _value;
5038
5039 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5040
5041 void print() const {
5042 printf("%04x", _value & 0xFFFF);
5043 }
5044
5045 };
5046
5047 class FPU_Register {
5048 public:
5049 int32_t _m0;
5050 int32_t _m1;
5051 int16_t _ex;
5052
5053 bool is_indefinite() const {
5054 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5055 }
5056
5057 void print() const {
5058 char sign = (_ex < 0) ? '-' : '+';
5059 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5060 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5061 };
5062
5063 };
5064
5065 class FPU_State {
5066 public:
5067 enum {
5068 register_size = 10,
5069 number_of_registers = 8,
5070 register_mask = 7
5071 };
5072
5073 ControlWord _control_word;
5074 StatusWord _status_word;
5075 TagWord _tag_word;
5076 int32_t _error_offset;
5077 int32_t _error_selector;
5078 int32_t _data_offset;
5079 int32_t _data_selector;
5080 int8_t _register[register_size * number_of_registers];
5081
5082 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5083 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5084
5085 const char* tag_as_string(int tag) const {
5086 switch (tag) {
5087 case 0: return "valid";
5088 case 1: return "zero";
5089 case 2: return "special";
5090 case 3: return "empty";
5091 }
5092 ShouldNotReachHere();
5093 return NULL;
5094 }
5095
5096 void print() const {
5097 // print computation registers
5098 { int t = _status_word.top();
5099 for (int i = 0; i < number_of_registers; i++) {
5100 int j = (i - t) & register_mask;
5101 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5102 st(j)->print();
5103 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5104 }
5105 }
5106 printf("\n");
5107 // print control registers
5108 printf("ctrl = "); _control_word.print(); printf("\n");
5109 printf("stat = "); _status_word .print(); printf("\n");
5110 printf("tags = "); _tag_word .print(); printf("\n");
5111 }
5112
5113 };
5114
5115 class Flag_Register {
5116 public:
5117 int32_t _value;
5118
5119 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5120 bool direction() const { return ((_value >> 10) & 1) != 0; }
5121 bool sign() const { return ((_value >> 7) & 1) != 0; }
5122 bool zero() const { return ((_value >> 6) & 1) != 0; }
5123 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5124 bool parity() const { return ((_value >> 2) & 1) != 0; }
5125 bool carry() const { return ((_value >> 0) & 1) != 0; }
5126
5127 void print() const {
5128 // flags
5129 char f[8];
5130 f[0] = (overflow ()) ? 'O' : '-';
5131 f[1] = (direction ()) ? 'D' : '-';
5132 f[2] = (sign ()) ? 'S' : '-';
5133 f[3] = (zero ()) ? 'Z' : '-';
5134 f[4] = (auxiliary_carry()) ? 'A' : '-';
5135 f[5] = (parity ()) ? 'P' : '-';
5136 f[6] = (carry ()) ? 'C' : '-';
5137 f[7] = '\x0';
5138 // output
5139 printf("%08x flags = %s", _value, f);
5140 }
5141
5142 };
5143
5144 class IU_Register {
5145 public:
5146 int32_t _value;
5147
5148 void print() const {
5149 printf("%08x %11d", _value, _value);
5150 }
5151
5152 };
5153
5154 class IU_State {
5155 public:
5156 Flag_Register _eflags;
5157 IU_Register _rdi;
5158 IU_Register _rsi;
5159 IU_Register _rbp;
5160 IU_Register _rsp;
5161 IU_Register _rbx;
5162 IU_Register _rdx;
5163 IU_Register _rcx;
5164 IU_Register _rax;
5165
5166 void print() const {
5167 // computation registers
5168 printf("rax, = "); _rax.print(); printf("\n");
5169 printf("rbx, = "); _rbx.print(); printf("\n");
5170 printf("rcx = "); _rcx.print(); printf("\n");
5171 printf("rdx = "); _rdx.print(); printf("\n");
5172 printf("rdi = "); _rdi.print(); printf("\n");
5173 printf("rsi = "); _rsi.print(); printf("\n");
5174 printf("rbp, = "); _rbp.print(); printf("\n");
5175 printf("rsp = "); _rsp.print(); printf("\n");
5176 printf("\n");
5177 // control registers
5178 printf("flgs = "); _eflags.print(); printf("\n");
5179 }
5180 };
5181
5182
5183 class CPU_State {
5184 public:
5185 FPU_State _fpu_state;
5186 IU_State _iu_state;
5187
5188 void print() const {
5189 printf("--------------------------------------------------\n");
5190 _iu_state .print();
5191 printf("\n");
5192 _fpu_state.print();
5193 printf("--------------------------------------------------\n");
5194 }
5195
5196 };
5197
5198
5199 static void _print_CPU_state(CPU_State* state) {
5200 state->print();
5201 };
5202
5203
5204 void MacroAssembler::print_CPU_state() {
5205 push_CPU_state();
5206 push(rsp); // pass CPU state
5207 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5208 addptr(rsp, wordSize); // discard argument
5209 pop_CPU_state();
5210 }
5211
5212
5213 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5214 static int counter = 0;
5215 FPU_State* fs = &state->_fpu_state;
5216 counter++;
5217 // For leaf calls, only verify that the top few elements remain empty.
5218 // We only need 1 empty at the top for C2 code.
5219 if( stack_depth < 0 ) {
5220 if( fs->tag_for_st(7) != 3 ) {
5221 printf("FPR7 not empty\n");
5222 state->print();
5223 assert(false, "error");
5224 return false;
5225 }
5226 return true; // All other stack states do not matter
5227 }
5228
5229 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5230 "bad FPU control word");
5231
5232 // compute stack depth
5233 int i = 0;
5234 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5235 int d = i;
5236 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5237 // verify findings
5238 if (i != FPU_State::number_of_registers) {
5239 // stack not contiguous
5240 printf("%s: stack not contiguous at ST%d\n", s, i);
5241 state->print();
5242 assert(false, "error");
5243 return false;
5244 }
5245 // check if computed stack depth corresponds to expected stack depth
5246 if (stack_depth < 0) {
5247 // expected stack depth is -stack_depth or less
5248 if (d > -stack_depth) {
5249 // too many elements on the stack
5250 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5251 state->print();
5252 assert(false, "error");
5253 return false;
5254 }
5255 } else {
5256 // expected stack depth is stack_depth
5257 if (d != stack_depth) {
5258 // wrong stack depth
5259 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5260 state->print();
5261 assert(false, "error");
5262 return false;
5263 }
5264 }
5265 // everything is cool
5266 return true;
5267 }
5268
5269
5270 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5271 if (!VerifyFPU) return;
5272 push_CPU_state();
5273 push(rsp); // pass CPU state
5274 ExternalAddress msg((address) s);
5275 // pass message string s
5276 pushptr(msg.addr());
5277 push(stack_depth); // pass stack depth
5278 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5279 addptr(rsp, 3 * wordSize); // discard arguments
5280 // check for error
5281 { Label L;
5282 testl(rax, rax);
5283 jcc(Assembler::notZero, L);
5284 int3(); // break if error condition
5285 bind(L);
5286 }
5287 pop_CPU_state();
5288 }
5289
5290 void MacroAssembler::restore_cpu_control_state_after_jni() {
5291 // Either restore the MXCSR register after returning from the JNI Call
5292 // or verify that it wasn't changed (with -Xcheck:jni flag).
5293 if (VM_Version::supports_sse()) {
5294 if (RestoreMXCSROnJNICalls) {
5295 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5296 } else if (CheckJNICalls) {
5297 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5298 }
5299 }
5300 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5301 vzeroupper();
5302 // Reset k1 to 0xffff.
5303
5304 #ifdef COMPILER2
5305 if (PostLoopMultiversioning && VM_Version::supports_evex()) {
5306 push(rcx);
5307 movl(rcx, 0xffff);
5308 kmovwl(k1, rcx);
5309 pop(rcx);
5310 }
5311 #endif // COMPILER2
5312
5313 #ifndef _LP64
5314 // Either restore the x87 floating pointer control word after returning
5315 // from the JNI call or verify that it wasn't changed.
5316 if (CheckJNICalls) {
5317 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5318 }
5319 #endif // _LP64
5320 }
5321
5322 // ((OopHandle)result).resolve();
5323 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5324 assert_different_registers(result, tmp);
5325
5326 // Only 64 bit platforms support GCs that require a tmp register
5327 // Only IN_HEAP loads require a thread_tmp register
5328 // OopHandle::resolve is an indirection like jobject.
5329 access_load_at(T_OBJECT, IN_NATIVE,
5330 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5331 }
5332
5333 // ((WeakHandle)result).resolve();
5334 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5335 assert_different_registers(rresult, rtmp);
5336 Label resolved;
5337
5338 // A null weak handle resolves to null.
5339 cmpptr(rresult, 0);
5340 jcc(Assembler::equal, resolved);
5341
5342 // Only 64 bit platforms support GCs that require a tmp register
5343 // Only IN_HEAP loads require a thread_tmp register
5344 // WeakHandle::resolve is an indirection like jweak.
5345 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5346 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
5347 bind(resolved);
5348 }
5349
5350 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5351 // get mirror
5352 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5353 load_method_holder(mirror, method);
5354 movptr(mirror, Address(mirror, mirror_offset));
5355 resolve_oop_handle(mirror, tmp);
5356 }
5357
5358 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5359 load_method_holder(rresult, rmethod);
5360 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5361 }
5362
5363 void MacroAssembler::load_method_holder(Register holder, Register method) {
5364 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5365 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5366 movptr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass*
5367 }
5368
5369 void MacroAssembler::load_klass(Register dst, Register src) {
5370 #ifdef _LP64
5371 if (UseCompressedClassPointers) {
5372 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5373 decode_klass_not_null(dst);
5374 } else
5375 #endif
5376 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5377 }
5378
5379 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5380 load_klass(dst, src);
5381 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5382 }
5383
5384 void MacroAssembler::store_klass(Register dst, Register src) {
5385 #ifdef _LP64
5386 if (UseCompressedClassPointers) {
5387 encode_klass_not_null(src);
5388 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5389 } else
5390 #endif
5391 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5392 }
5393
5394 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5395 Register tmp1, Register thread_tmp) {
5396 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5397 decorators = AccessInternal::decorator_fixup(decorators);
5398 bool as_raw = (decorators & AS_RAW) != 0;
5399 if (as_raw) {
5400 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5401 } else {
5402 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5403 }
5404 }
5405
5406 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
5407 Register tmp1, Register tmp2) {
5408 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5409 decorators = AccessInternal::decorator_fixup(decorators);
5410 bool as_raw = (decorators & AS_RAW) != 0;
5411 if (as_raw) {
5412 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2);
5413 } else {
5414 bs->store_at(this, decorators, type, dst, src, tmp1, tmp2);
5415 }
5416 }
5417
5418 void MacroAssembler::resolve(DecoratorSet decorators, Register obj) {
5419 // Use stronger ACCESS_WRITE|ACCESS_READ by default.
5420 if ((decorators & (ACCESS_READ | ACCESS_WRITE)) == 0) {
5421 decorators |= ACCESS_READ | ACCESS_WRITE;
5422 }
5423 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5424 return bs->resolve(this, decorators, obj);
5425 }
5426
5427 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5428 Register thread_tmp, DecoratorSet decorators) {
5429 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
5430 }
5431
5432 // Doesn't do verfication, generates fixed size code
5433 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5434 Register thread_tmp, DecoratorSet decorators) {
5435 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
5436 }
5437
5438 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
5439 Register tmp2, DecoratorSet decorators) {
5440 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5441 }
5442
5443 // Used for storing NULLs.
5444 void MacroAssembler::store_heap_oop_null(Address dst) {
5445 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
5446 }
5447
5448 #ifdef _LP64
5449 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5450 if (UseCompressedClassPointers) {
5451 // Store to klass gap in destination
5452 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5453 }
5454 }
5455
5456 #ifdef ASSERT
5457 void MacroAssembler::verify_heapbase(const char* msg) {
5458 assert (UseCompressedOops, "should be compressed");
5459 assert (Universe::heap() != NULL, "java heap should be initialized");
5460 if (CheckCompressedOops) {
5461 Label ok;
5462 push(rscratch1); // cmpptr trashes rscratch1
5463 cmpptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
5464 jcc(Assembler::equal, ok);
5465 STOP(msg);
5466 bind(ok);
5467 pop(rscratch1);
5468 }
5469 }
5470 #endif
5471
5472 // Algorithm must match oop.inline.hpp encode_heap_oop.
5473 void MacroAssembler::encode_heap_oop(Register r) {
5474 #ifdef ASSERT
5475 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5476 #endif
5477 verify_oop(r, "broken oop in encode_heap_oop");
5478 if (CompressedOops::base() == NULL) {
5479 if (CompressedOops::shift() != 0) {
5480 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5481 shrq(r, LogMinObjAlignmentInBytes);
5482 }
5483 return;
5484 }
5485 testq(r, r);
5486 cmovq(Assembler::equal, r, r12_heapbase);
5487 subq(r, r12_heapbase);
5488 shrq(r, LogMinObjAlignmentInBytes);
5489 }
5490
5491 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5492 #ifdef ASSERT
5493 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5494 if (CheckCompressedOops) {
5495 Label ok;
5496 testq(r, r);
5497 jcc(Assembler::notEqual, ok);
5498 STOP("null oop passed to encode_heap_oop_not_null");
5499 bind(ok);
5500 }
5501 #endif
5502 verify_oop(r, "broken oop in encode_heap_oop_not_null");
5503 if (CompressedOops::base() != NULL) {
5504 subq(r, r12_heapbase);
5505 }
5506 if (CompressedOops::shift() != 0) {
5507 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5508 shrq(r, LogMinObjAlignmentInBytes);
5509 }
5510 }
5511
5512 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5513 #ifdef ASSERT
5514 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5515 if (CheckCompressedOops) {
5516 Label ok;
5517 testq(src, src);
5518 jcc(Assembler::notEqual, ok);
5519 STOP("null oop passed to encode_heap_oop_not_null2");
5520 bind(ok);
5521 }
5522 #endif
5523 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5524 if (dst != src) {
5525 movq(dst, src);
5526 }
5527 if (CompressedOops::base() != NULL) {
5528 subq(dst, r12_heapbase);
5529 }
5530 if (CompressedOops::shift() != 0) {
5531 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5532 shrq(dst, LogMinObjAlignmentInBytes);
5533 }
5534 }
5535
5536 void MacroAssembler::decode_heap_oop(Register r) {
5537 #ifdef ASSERT
5538 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5539 #endif
5540 if (CompressedOops::base() == NULL) {
5541 if (CompressedOops::shift() != 0) {
5542 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5543 shlq(r, LogMinObjAlignmentInBytes);
5544 }
5545 } else {
5546 Label done;
5547 shlq(r, LogMinObjAlignmentInBytes);
5548 jccb(Assembler::equal, done);
5549 addq(r, r12_heapbase);
5550 bind(done);
5551 }
5552 verify_oop(r, "broken oop in decode_heap_oop");
5553 }
5554
5555 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5556 // Note: it will change flags
5557 assert (UseCompressedOops, "should only be used for compressed headers");
5558 assert (Universe::heap() != NULL, "java heap should be initialized");
5559 // Cannot assert, unverified entry point counts instructions (see .ad file)
5560 // vtableStubs also counts instructions in pd_code_size_limit.
5561 // Also do not verify_oop as this is called by verify_oop.
5562 if (CompressedOops::shift() != 0) {
5563 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5564 shlq(r, LogMinObjAlignmentInBytes);
5565 if (CompressedOops::base() != NULL) {
5566 addq(r, r12_heapbase);
5567 }
5568 } else {
5569 assert (CompressedOops::base() == NULL, "sanity");
5570 }
5571 }
5572
5573 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5574 // Note: it will change flags
5575 assert (UseCompressedOops, "should only be used for compressed headers");
5576 assert (Universe::heap() != NULL, "java heap should be initialized");
5577 // Cannot assert, unverified entry point counts instructions (see .ad file)
5578 // vtableStubs also counts instructions in pd_code_size_limit.
5579 // Also do not verify_oop as this is called by verify_oop.
5580 if (CompressedOops::shift() != 0) {
5581 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5582 if (LogMinObjAlignmentInBytes == Address::times_8) {
5583 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5584 } else {
5585 if (dst != src) {
5586 movq(dst, src);
5587 }
5588 shlq(dst, LogMinObjAlignmentInBytes);
5589 if (CompressedOops::base() != NULL) {
5590 addq(dst, r12_heapbase);
5591 }
5592 }
5593 } else {
5594 assert (CompressedOops::base() == NULL, "sanity");
5595 if (dst != src) {
5596 movq(dst, src);
5597 }
5598 }
5599 }
5600
5601 void MacroAssembler::encode_klass_not_null(Register r) {
5602 if (CompressedKlassPointers::base() != NULL) {
5603 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5604 assert(r != r12_heapbase, "Encoding a klass in r12");
5605 mov64(r12_heapbase, (int64_t)CompressedKlassPointers::base());
5606 subq(r, r12_heapbase);
5607 }
5608 if (CompressedKlassPointers::shift() != 0) {
5609 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5610 shrq(r, LogKlassAlignmentInBytes);
5611 }
5612 if (CompressedKlassPointers::base() != NULL) {
5613 reinit_heapbase();
5614 }
5615 }
5616
5617 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5618 if (dst == src) {
5619 encode_klass_not_null(src);
5620 } else {
5621 if (CompressedKlassPointers::base() != NULL) {
5622 mov64(dst, (int64_t)CompressedKlassPointers::base());
5623 negq(dst);
5624 addq(dst, src);
5625 } else {
5626 movptr(dst, src);
5627 }
5628 if (CompressedKlassPointers::shift() != 0) {
5629 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5630 shrq(dst, LogKlassAlignmentInBytes);
5631 }
5632 }
5633 }
5634
5635 // Function instr_size_for_decode_klass_not_null() counts the instructions
5636 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5637 // when (Universe::heap() != NULL). Hence, if the instructions they
5638 // generate change, then this method needs to be updated.
5639 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5640 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5641 if (CompressedKlassPointers::base() != NULL) {
5642 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
5643 return (CompressedKlassPointers::shift() == 0 ? 20 : 24);
5644 } else {
5645 // longest load decode klass function, mov64, leaq
5646 return 16;
5647 }
5648 }
5649
5650 // !!! If the instructions that get generated here change then function
5651 // instr_size_for_decode_klass_not_null() needs to get updated.
5652 void MacroAssembler::decode_klass_not_null(Register r) {
5653 // Note: it will change flags
5654 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5655 assert(r != r12_heapbase, "Decoding a klass in r12");
5656 // Cannot assert, unverified entry point counts instructions (see .ad file)
5657 // vtableStubs also counts instructions in pd_code_size_limit.
5658 // Also do not verify_oop as this is called by verify_oop.
5659 if (CompressedKlassPointers::shift() != 0) {
5660 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5661 shlq(r, LogKlassAlignmentInBytes);
5662 }
5663 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5664 if (CompressedKlassPointers::base() != NULL) {
5665 mov64(r12_heapbase, (int64_t)CompressedKlassPointers::base());
5666 addq(r, r12_heapbase);
5667 reinit_heapbase();
5668 }
5669 }
5670
5671 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5672 // Note: it will change flags
5673 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5674 if (dst == src) {
5675 decode_klass_not_null(dst);
5676 } else {
5677 // Cannot assert, unverified entry point counts instructions (see .ad file)
5678 // vtableStubs also counts instructions in pd_code_size_limit.
5679 // Also do not verify_oop as this is called by verify_oop.
5680 mov64(dst, (int64_t)CompressedKlassPointers::base());
5681 if (CompressedKlassPointers::shift() != 0) {
5682 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5683 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
5684 leaq(dst, Address(dst, src, Address::times_8, 0));
5685 } else {
5686 addq(dst, src);
5687 }
5688 }
5689 }
5690
5691 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5692 assert (UseCompressedOops, "should only be used for compressed headers");
5693 assert (Universe::heap() != NULL, "java heap should be initialized");
5694 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5695 int oop_index = oop_recorder()->find_index(obj);
5696 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5697 mov_narrow_oop(dst, oop_index, rspec);
5698 }
5699
5700 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5701 assert (UseCompressedOops, "should only be used for compressed headers");
5702 assert (Universe::heap() != NULL, "java heap should be initialized");
5703 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5704 int oop_index = oop_recorder()->find_index(obj);
5705 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5706 mov_narrow_oop(dst, oop_index, rspec);
5707 }
5708
5709 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5710 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5711 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5712 int klass_index = oop_recorder()->find_index(k);
5713 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5714 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5715 }
5716
5717 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5718 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5719 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5720 int klass_index = oop_recorder()->find_index(k);
5721 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5722 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5723 }
5724
5725 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5726 assert (UseCompressedOops, "should only be used for compressed headers");
5727 assert (Universe::heap() != NULL, "java heap should be initialized");
5728 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5729 int oop_index = oop_recorder()->find_index(obj);
5730 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5731 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5732 }
5733
5734 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5735 assert (UseCompressedOops, "should only be used for compressed headers");
5736 assert (Universe::heap() != NULL, "java heap should be initialized");
5737 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5738 int oop_index = oop_recorder()->find_index(obj);
5739 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5740 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5741 }
5742
5743 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5744 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5745 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5746 int klass_index = oop_recorder()->find_index(k);
5747 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5748 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5749 }
5750
5751 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5752 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5753 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5754 int klass_index = oop_recorder()->find_index(k);
5755 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5756 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5757 }
5758
5759 void MacroAssembler::reinit_heapbase() {
5760 if (UseCompressedOops || UseCompressedClassPointers) {
5761 if (Universe::heap() != NULL) {
5762 if (CompressedOops::base() == NULL) {
5763 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5764 } else {
5765 mov64(r12_heapbase, (int64_t)CompressedOops::ptrs_base());
5766 }
5767 } else {
5768 movptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
5769 }
5770 }
5771 }
5772
5773 #endif // _LP64
5774
5775 // C2 compiled method's prolog code.
5776 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub) {
5777
5778 // WARNING: Initial instruction MUST be 5 bytes or longer so that
5779 // NativeJump::patch_verified_entry will be able to patch out the entry
5780 // code safely. The push to verify stack depth is ok at 5 bytes,
5781 // the frame allocation can be either 3 or 6 bytes. So if we don't do
5782 // stack bang then we must use the 6 byte frame allocation even if
5783 // we have no frame. :-(
5784 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
5785
5786 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5787 // Remove word for return addr
5788 framesize -= wordSize;
5789 stack_bang_size -= wordSize;
5790
5791 // Calls to C2R adapters often do not accept exceptional returns.
5792 // We require that their callers must bang for them. But be careful, because
5793 // some VM calls (such as call site linkage) can use several kilobytes of
5794 // stack. But the stack safety zone should account for that.
5795 // See bugs 4446381, 4468289, 4497237.
5796 if (stack_bang_size > 0) {
5797 generate_stack_overflow_check(stack_bang_size);
5798
5799 // We always push rbp, so that on return to interpreter rbp, will be
5800 // restored correctly and we can correct the stack.
5801 push(rbp);
5802 // Save caller's stack pointer into RBP if the frame pointer is preserved.
5803 if (PreserveFramePointer) {
5804 mov(rbp, rsp);
5805 }
5806 // Remove word for ebp
5807 framesize -= wordSize;
5808
5809 // Create frame
5810 if (framesize) {
5811 subptr(rsp, framesize);
5812 }
5813 } else {
5814 // Create frame (force generation of a 4 byte immediate value)
5815 subptr_imm32(rsp, framesize);
5816
5817 // Save RBP register now.
5818 framesize -= wordSize;
5819 movptr(Address(rsp, framesize), rbp);
5820 // Save caller's stack pointer into RBP if the frame pointer is preserved.
5821 if (PreserveFramePointer) {
5822 movptr(rbp, rsp);
5823 if (framesize > 0) {
5824 addptr(rbp, framesize);
5825 }
5826 }
5827 }
5828
5829 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
5830 framesize -= wordSize;
5831 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
5832 }
5833
5834 #ifndef _LP64
5835 // If method sets FPU control word do it now
5836 if (fp_mode_24b) {
5837 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
5838 }
5839 if (UseSSE >= 2 && VerifyFPU) {
5840 verify_FPU(0, "FPU stack must be clean on entry");
5841 }
5842 #endif
5843
5844 #ifdef ASSERT
5845 if (VerifyStackAtCalls) {
5846 Label L;
5847 push(rax);
5848 mov(rax, rsp);
5849 andptr(rax, StackAlignmentInBytes-1);
5850 cmpptr(rax, StackAlignmentInBytes-wordSize);
5851 pop(rax);
5852 jcc(Assembler::equal, L);
5853 STOP("Stack is not properly aligned!");
5854 bind(L);
5855 }
5856 #endif
5857
5858 if (!is_stub) {
5859 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5860 bs->nmethod_entry_barrier(this);
5861 }
5862 }
5863
5864 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
5865 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp) {
5866 // cnt - number of qwords (8-byte words).
5867 // base - start address, qword aligned.
5868 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5869 if (UseAVX >= 2) {
5870 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5871 } else {
5872 pxor(xtmp, xtmp);
5873 }
5874 jmp(L_zero_64_bytes);
5875
5876 BIND(L_loop);
5877 if (UseAVX >= 2) {
5878 vmovdqu(Address(base, 0), xtmp);
5879 vmovdqu(Address(base, 32), xtmp);
5880 } else {
5881 movdqu(Address(base, 0), xtmp);
5882 movdqu(Address(base, 16), xtmp);
5883 movdqu(Address(base, 32), xtmp);
5884 movdqu(Address(base, 48), xtmp);
5885 }
5886 addptr(base, 64);
5887
5888 BIND(L_zero_64_bytes);
5889 subptr(cnt, 8);
5890 jccb(Assembler::greaterEqual, L_loop);
5891 addptr(cnt, 4);
5892 jccb(Assembler::less, L_tail);
5893 // Copy trailing 32 bytes
5894 if (UseAVX >= 2) {
5895 vmovdqu(Address(base, 0), xtmp);
5896 } else {
5897 movdqu(Address(base, 0), xtmp);
5898 movdqu(Address(base, 16), xtmp);
5899 }
5900 addptr(base, 32);
5901 subptr(cnt, 4);
5902
5903 BIND(L_tail);
5904 addptr(cnt, 4);
5905 jccb(Assembler::lessEqual, L_end);
5906 decrement(cnt);
5907
5908 BIND(L_sloop);
5909 movq(Address(base, 0), xtmp);
5910 addptr(base, 8);
5911 decrement(cnt);
5912 jccb(Assembler::greaterEqual, L_sloop);
5913 BIND(L_end);
5914 }
5915
5916 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp, bool is_large) {
5917 // cnt - number of qwords (8-byte words).
5918 // base - start address, qword aligned.
5919 // is_large - if optimizers know cnt is larger than InitArrayShortSize
5920 assert(base==rdi, "base register must be edi for rep stos");
5921 assert(tmp==rax, "tmp register must be eax for rep stos");
5922 assert(cnt==rcx, "cnt register must be ecx for rep stos");
5923 assert(InitArrayShortSize % BytesPerLong == 0,
5924 "InitArrayShortSize should be the multiple of BytesPerLong");
5925
5926 Label DONE;
5927
5928 if (!is_large || !UseXMMForObjInit) {
5929 xorptr(tmp, tmp);
5930 }
5931
5932 if (!is_large) {
5933 Label LOOP, LONG;
5934 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
5935 jccb(Assembler::greater, LONG);
5936
5937 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5938
5939 decrement(cnt);
5940 jccb(Assembler::negative, DONE); // Zero length
5941
5942 // Use individual pointer-sized stores for small counts:
5943 BIND(LOOP);
5944 movptr(Address(base, cnt, Address::times_ptr), tmp);
5945 decrement(cnt);
5946 jccb(Assembler::greaterEqual, LOOP);
5947 jmpb(DONE);
5948
5949 BIND(LONG);
5950 }
5951
5952 // Use longer rep-prefixed ops for non-small counts:
5953 if (UseFastStosb) {
5954 shlptr(cnt, 3); // convert to number of bytes
5955 rep_stosb();
5956 } else if (UseXMMForObjInit) {
5957 movptr(tmp, base);
5958 xmm_clear_mem(tmp, cnt, xtmp);
5959 } else {
5960 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5961 rep_stos();
5962 }
5963
5964 BIND(DONE);
5965 }
5966
5967 #ifdef COMPILER2
5968
5969 // IndexOf for constant substrings with size >= 8 chars
5970 // which don't need to be loaded through stack.
5971 void MacroAssembler::string_indexofC8(Register str1, Register str2,
5972 Register cnt1, Register cnt2,
5973 int int_cnt2, Register result,
5974 XMMRegister vec, Register tmp,
5975 int ae) {
5976 ShortBranchVerifier sbv(this);
5977 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
5978 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
5979
5980 // This method uses the pcmpestri instruction with bound registers
5981 // inputs:
5982 // xmm - substring
5983 // rax - substring length (elements count)
5984 // mem - scanned string
5985 // rdx - string length (elements count)
5986 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
5987 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
5988 // outputs:
5989 // rcx - matched index in string
5990 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
5991 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
5992 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
5993 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
5994 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
5995
5996 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
5997 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
5998 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
5999
6000 // Note, inline_string_indexOf() generates checks:
6001 // if (substr.count > string.count) return -1;
6002 // if (substr.count == 0) return 0;
6003 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
6004
6005 // Load substring.
6006 if (ae == StrIntrinsicNode::UL) {
6007 pmovzxbw(vec, Address(str2, 0));
6008 } else {
6009 movdqu(vec, Address(str2, 0));
6010 }
6011 movl(cnt2, int_cnt2);
6012 movptr(result, str1); // string addr
6013
6014 if (int_cnt2 > stride) {
6015 jmpb(SCAN_TO_SUBSTR);
6016
6017 // Reload substr for rescan, this code
6018 // is executed only for large substrings (> 8 chars)
6019 bind(RELOAD_SUBSTR);
6020 if (ae == StrIntrinsicNode::UL) {
6021 pmovzxbw(vec, Address(str2, 0));
6022 } else {
6023 movdqu(vec, Address(str2, 0));
6024 }
6025 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
6026
6027 bind(RELOAD_STR);
6028 // We came here after the beginning of the substring was
6029 // matched but the rest of it was not so we need to search
6030 // again. Start from the next element after the previous match.
6031
6032 // cnt2 is number of substring reminding elements and
6033 // cnt1 is number of string reminding elements when cmp failed.
6034 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
6035 subl(cnt1, cnt2);
6036 addl(cnt1, int_cnt2);
6037 movl(cnt2, int_cnt2); // Now restore cnt2
6038
6039 decrementl(cnt1); // Shift to next element
6040 cmpl(cnt1, cnt2);
6041 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6042
6043 addptr(result, (1<<scale1));
6044
6045 } // (int_cnt2 > 8)
6046
6047 // Scan string for start of substr in 16-byte vectors
6048 bind(SCAN_TO_SUBSTR);
6049 pcmpestri(vec, Address(result, 0), mode);
6050 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6051 subl(cnt1, stride);
6052 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6053 cmpl(cnt1, cnt2);
6054 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6055 addptr(result, 16);
6056 jmpb(SCAN_TO_SUBSTR);
6057
6058 // Found a potential substr
6059 bind(FOUND_CANDIDATE);
6060 // Matched whole vector if first element matched (tmp(rcx) == 0).
6061 if (int_cnt2 == stride) {
6062 jccb(Assembler::overflow, RET_FOUND); // OF == 1
6063 } else { // int_cnt2 > 8
6064 jccb(Assembler::overflow, FOUND_SUBSTR);
6065 }
6066 // After pcmpestri tmp(rcx) contains matched element index
6067 // Compute start addr of substr
6068 lea(result, Address(result, tmp, scale1));
6069
6070 // Make sure string is still long enough
6071 subl(cnt1, tmp);
6072 cmpl(cnt1, cnt2);
6073 if (int_cnt2 == stride) {
6074 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6075 } else { // int_cnt2 > 8
6076 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
6077 }
6078 // Left less then substring.
6079
6080 bind(RET_NOT_FOUND);
6081 movl(result, -1);
6082 jmp(EXIT);
6083
6084 if (int_cnt2 > stride) {
6085 // This code is optimized for the case when whole substring
6086 // is matched if its head is matched.
6087 bind(MATCH_SUBSTR_HEAD);
6088 pcmpestri(vec, Address(result, 0), mode);
6089 // Reload only string if does not match
6090 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
6091
6092 Label CONT_SCAN_SUBSTR;
6093 // Compare the rest of substring (> 8 chars).
6094 bind(FOUND_SUBSTR);
6095 // First 8 chars are already matched.
6096 negptr(cnt2);
6097 addptr(cnt2, stride);
6098
6099 bind(SCAN_SUBSTR);
6100 subl(cnt1, stride);
6101 cmpl(cnt2, -stride); // Do not read beyond substring
6102 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
6103 // Back-up strings to avoid reading beyond substring:
6104 // cnt1 = cnt1 - cnt2 + 8
6105 addl(cnt1, cnt2); // cnt2 is negative
6106 addl(cnt1, stride);
6107 movl(cnt2, stride); negptr(cnt2);
6108 bind(CONT_SCAN_SUBSTR);
6109 if (int_cnt2 < (int)G) {
6110 int tail_off1 = int_cnt2<<scale1;
6111 int tail_off2 = int_cnt2<<scale2;
6112 if (ae == StrIntrinsicNode::UL) {
6113 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
6114 } else {
6115 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
6116 }
6117 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
6118 } else {
6119 // calculate index in register to avoid integer overflow (int_cnt2*2)
6120 movl(tmp, int_cnt2);
6121 addptr(tmp, cnt2);
6122 if (ae == StrIntrinsicNode::UL) {
6123 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
6124 } else {
6125 movdqu(vec, Address(str2, tmp, scale2, 0));
6126 }
6127 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
6128 }
6129 // Need to reload strings pointers if not matched whole vector
6130 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6131 addptr(cnt2, stride);
6132 jcc(Assembler::negative, SCAN_SUBSTR);
6133 // Fall through if found full substring
6134
6135 } // (int_cnt2 > 8)
6136
6137 bind(RET_FOUND);
6138 // Found result if we matched full small substring.
6139 // Compute substr offset
6140 subptr(result, str1);
6141 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6142 shrl(result, 1); // index
6143 }
6144 bind(EXIT);
6145
6146 } // string_indexofC8
6147
6148 // Small strings are loaded through stack if they cross page boundary.
6149 void MacroAssembler::string_indexof(Register str1, Register str2,
6150 Register cnt1, Register cnt2,
6151 int int_cnt2, Register result,
6152 XMMRegister vec, Register tmp,
6153 int ae) {
6154 ShortBranchVerifier sbv(this);
6155 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6156 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
6157
6158 //
6159 // int_cnt2 is length of small (< 8 chars) constant substring
6160 // or (-1) for non constant substring in which case its length
6161 // is in cnt2 register.
6162 //
6163 // Note, inline_string_indexOf() generates checks:
6164 // if (substr.count > string.count) return -1;
6165 // if (substr.count == 0) return 0;
6166 //
6167 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
6168 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
6169 // This method uses the pcmpestri instruction with bound registers
6170 // inputs:
6171 // xmm - substring
6172 // rax - substring length (elements count)
6173 // mem - scanned string
6174 // rdx - string length (elements count)
6175 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6176 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
6177 // outputs:
6178 // rcx - matched index in string
6179 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6180 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
6181 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
6182 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
6183
6184 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6185 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6186 FOUND_CANDIDATE;
6187
6188 { //========================================================
6189 // We don't know where these strings are located
6190 // and we can't read beyond them. Load them through stack.
6191 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6192
6193 movptr(tmp, rsp); // save old SP
6194
6195 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6196 if (int_cnt2 == (1>>scale2)) { // One byte
6197 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
6198 load_unsigned_byte(result, Address(str2, 0));
6199 movdl(vec, result); // move 32 bits
6200 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
6201 // Not enough header space in 32-bit VM: 12+3 = 15.
6202 movl(result, Address(str2, -1));
6203 shrl(result, 8);
6204 movdl(vec, result); // move 32 bits
6205 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
6206 load_unsigned_short(result, Address(str2, 0));
6207 movdl(vec, result); // move 32 bits
6208 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
6209 movdl(vec, Address(str2, 0)); // move 32 bits
6210 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
6211 movq(vec, Address(str2, 0)); // move 64 bits
6212 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
6213 // Array header size is 12 bytes in 32-bit VM
6214 // + 6 bytes for 3 chars == 18 bytes,
6215 // enough space to load vec and shift.
6216 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6217 if (ae == StrIntrinsicNode::UL) {
6218 int tail_off = int_cnt2-8;
6219 pmovzxbw(vec, Address(str2, tail_off));
6220 psrldq(vec, -2*tail_off);
6221 }
6222 else {
6223 int tail_off = int_cnt2*(1<<scale2);
6224 movdqu(vec, Address(str2, tail_off-16));
6225 psrldq(vec, 16-tail_off);
6226 }
6227 }
6228 } else { // not constant substring
6229 cmpl(cnt2, stride);
6230 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6231
6232 // We can read beyond string if srt+16 does not cross page boundary
6233 // since heaps are aligned and mapped by pages.
6234 assert(os::vm_page_size() < (int)G, "default page should be small");
6235 movl(result, str2); // We need only low 32 bits
6236 andl(result, (os::vm_page_size()-1));
6237 cmpl(result, (os::vm_page_size()-16));
6238 jccb(Assembler::belowEqual, CHECK_STR);
6239
6240 // Move small strings to stack to allow load 16 bytes into vec.
6241 subptr(rsp, 16);
6242 int stk_offset = wordSize-(1<<scale2);
6243 push(cnt2);
6244
6245 bind(COPY_SUBSTR);
6246 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
6247 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
6248 movb(Address(rsp, cnt2, scale2, stk_offset), result);
6249 } else if (ae == StrIntrinsicNode::UU) {
6250 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
6251 movw(Address(rsp, cnt2, scale2, stk_offset), result);
6252 }
6253 decrement(cnt2);
6254 jccb(Assembler::notZero, COPY_SUBSTR);
6255
6256 pop(cnt2);
6257 movptr(str2, rsp); // New substring address
6258 } // non constant
6259
6260 bind(CHECK_STR);
6261 cmpl(cnt1, stride);
6262 jccb(Assembler::aboveEqual, BIG_STRINGS);
6263
6264 // Check cross page boundary.
6265 movl(result, str1); // We need only low 32 bits
6266 andl(result, (os::vm_page_size()-1));
6267 cmpl(result, (os::vm_page_size()-16));
6268 jccb(Assembler::belowEqual, BIG_STRINGS);
6269
6270 subptr(rsp, 16);
6271 int stk_offset = -(1<<scale1);
6272 if (int_cnt2 < 0) { // not constant
6273 push(cnt2);
6274 stk_offset += wordSize;
6275 }
6276 movl(cnt2, cnt1);
6277
6278 bind(COPY_STR);
6279 if (ae == StrIntrinsicNode::LL) {
6280 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
6281 movb(Address(rsp, cnt2, scale1, stk_offset), result);
6282 } else {
6283 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
6284 movw(Address(rsp, cnt2, scale1, stk_offset), result);
6285 }
6286 decrement(cnt2);
6287 jccb(Assembler::notZero, COPY_STR);
6288
6289 if (int_cnt2 < 0) { // not constant
6290 pop(cnt2);
6291 }
6292 movptr(str1, rsp); // New string address
6293
6294 bind(BIG_STRINGS);
6295 // Load substring.
6296 if (int_cnt2 < 0) { // -1
6297 if (ae == StrIntrinsicNode::UL) {
6298 pmovzxbw(vec, Address(str2, 0));
6299 } else {
6300 movdqu(vec, Address(str2, 0));
6301 }
6302 push(cnt2); // substr count
6303 push(str2); // substr addr
6304 push(str1); // string addr
6305 } else {
6306 // Small (< 8 chars) constant substrings are loaded already.
6307 movl(cnt2, int_cnt2);
6308 }
6309 push(tmp); // original SP
6310
6311 } // Finished loading
6312
6313 //========================================================
6314 // Start search
6315 //
6316
6317 movptr(result, str1); // string addr
6318
6319 if (int_cnt2 < 0) { // Only for non constant substring
6320 jmpb(SCAN_TO_SUBSTR);
6321
6322 // SP saved at sp+0
6323 // String saved at sp+1*wordSize
6324 // Substr saved at sp+2*wordSize
6325 // Substr count saved at sp+3*wordSize
6326
6327 // Reload substr for rescan, this code
6328 // is executed only for large substrings (> 8 chars)
6329 bind(RELOAD_SUBSTR);
6330 movptr(str2, Address(rsp, 2*wordSize));
6331 movl(cnt2, Address(rsp, 3*wordSize));
6332 if (ae == StrIntrinsicNode::UL) {
6333 pmovzxbw(vec, Address(str2, 0));
6334 } else {
6335 movdqu(vec, Address(str2, 0));
6336 }
6337 // We came here after the beginning of the substring was
6338 // matched but the rest of it was not so we need to search
6339 // again. Start from the next element after the previous match.
6340 subptr(str1, result); // Restore counter
6341 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6342 shrl(str1, 1);
6343 }
6344 addl(cnt1, str1);
6345 decrementl(cnt1); // Shift to next element
6346 cmpl(cnt1, cnt2);
6347 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6348
6349 addptr(result, (1<<scale1));
6350 } // non constant
6351
6352 // Scan string for start of substr in 16-byte vectors
6353 bind(SCAN_TO_SUBSTR);
6354 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6355 pcmpestri(vec, Address(result, 0), mode);
6356 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6357 subl(cnt1, stride);
6358 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6359 cmpl(cnt1, cnt2);
6360 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6361 addptr(result, 16);
6362
6363 bind(ADJUST_STR);
6364 cmpl(cnt1, stride); // Do not read beyond string
6365 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6366 // Back-up string to avoid reading beyond string.
6367 lea(result, Address(result, cnt1, scale1, -16));
6368 movl(cnt1, stride);
6369 jmpb(SCAN_TO_SUBSTR);
6370
6371 // Found a potential substr
6372 bind(FOUND_CANDIDATE);
6373 // After pcmpestri tmp(rcx) contains matched element index
6374
6375 // Make sure string is still long enough
6376 subl(cnt1, tmp);
6377 cmpl(cnt1, cnt2);
6378 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6379 // Left less then substring.
6380
6381 bind(RET_NOT_FOUND);
6382 movl(result, -1);
6383 jmp(CLEANUP);
6384
6385 bind(FOUND_SUBSTR);
6386 // Compute start addr of substr
6387 lea(result, Address(result, tmp, scale1));
6388 if (int_cnt2 > 0) { // Constant substring
6389 // Repeat search for small substring (< 8 chars)
6390 // from new point without reloading substring.
6391 // Have to check that we don't read beyond string.
6392 cmpl(tmp, stride-int_cnt2);
6393 jccb(Assembler::greater, ADJUST_STR);
6394 // Fall through if matched whole substring.
6395 } else { // non constant
6396 assert(int_cnt2 == -1, "should be != 0");
6397
6398 addl(tmp, cnt2);
6399 // Found result if we matched whole substring.
6400 cmpl(tmp, stride);
6401 jcc(Assembler::lessEqual, RET_FOUND);
6402
6403 // Repeat search for small substring (<= 8 chars)
6404 // from new point 'str1' without reloading substring.
6405 cmpl(cnt2, stride);
6406 // Have to check that we don't read beyond string.
6407 jccb(Assembler::lessEqual, ADJUST_STR);
6408
6409 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6410 // Compare the rest of substring (> 8 chars).
6411 movptr(str1, result);
6412
6413 cmpl(tmp, cnt2);
6414 // First 8 chars are already matched.
6415 jccb(Assembler::equal, CHECK_NEXT);
6416
6417 bind(SCAN_SUBSTR);
6418 pcmpestri(vec, Address(str1, 0), mode);
6419 // Need to reload strings pointers if not matched whole vector
6420 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6421
6422 bind(CHECK_NEXT);
6423 subl(cnt2, stride);
6424 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6425 addptr(str1, 16);
6426 if (ae == StrIntrinsicNode::UL) {
6427 addptr(str2, 8);
6428 } else {
6429 addptr(str2, 16);
6430 }
6431 subl(cnt1, stride);
6432 cmpl(cnt2, stride); // Do not read beyond substring
6433 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6434 // Back-up strings to avoid reading beyond substring.
6435
6436 if (ae == StrIntrinsicNode::UL) {
6437 lea(str2, Address(str2, cnt2, scale2, -8));
6438 lea(str1, Address(str1, cnt2, scale1, -16));
6439 } else {
6440 lea(str2, Address(str2, cnt2, scale2, -16));
6441 lea(str1, Address(str1, cnt2, scale1, -16));
6442 }
6443 subl(cnt1, cnt2);
6444 movl(cnt2, stride);
6445 addl(cnt1, stride);
6446 bind(CONT_SCAN_SUBSTR);
6447 if (ae == StrIntrinsicNode::UL) {
6448 pmovzxbw(vec, Address(str2, 0));
6449 } else {
6450 movdqu(vec, Address(str2, 0));
6451 }
6452 jmp(SCAN_SUBSTR);
6453
6454 bind(RET_FOUND_LONG);
6455 movptr(str1, Address(rsp, wordSize));
6456 } // non constant
6457
6458 bind(RET_FOUND);
6459 // Compute substr offset
6460 subptr(result, str1);
6461 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6462 shrl(result, 1); // index
6463 }
6464 bind(CLEANUP);
6465 pop(rsp); // restore SP
6466
6467 } // string_indexof
6468
6469 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
6470 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
6471 ShortBranchVerifier sbv(this);
6472 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6473
6474 int stride = 8;
6475
6476 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
6477 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
6478 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
6479 FOUND_SEQ_CHAR, DONE_LABEL;
6480
6481 movptr(result, str1);
6482 if (UseAVX >= 2) {
6483 cmpl(cnt1, stride);
6484 jcc(Assembler::less, SCAN_TO_CHAR);
6485 cmpl(cnt1, 2*stride);
6486 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
6487 movdl(vec1, ch);
6488 vpbroadcastw(vec1, vec1, Assembler::AVX_256bit);
6489 vpxor(vec2, vec2);
6490 movl(tmp, cnt1);
6491 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
6492 andl(cnt1,0x0000000F); //tail count (in chars)
6493
6494 bind(SCAN_TO_16_CHAR_LOOP);
6495 vmovdqu(vec3, Address(result, 0));
6496 vpcmpeqw(vec3, vec3, vec1, 1);
6497 vptest(vec2, vec3);
6498 jcc(Assembler::carryClear, FOUND_CHAR);
6499 addptr(result, 32);
6500 subl(tmp, 2*stride);
6501 jcc(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
6502 jmp(SCAN_TO_8_CHAR);
6503 bind(SCAN_TO_8_CHAR_INIT);
6504 movdl(vec1, ch);
6505 pshuflw(vec1, vec1, 0x00);
6506 pshufd(vec1, vec1, 0);
6507 pxor(vec2, vec2);
6508 }
6509 bind(SCAN_TO_8_CHAR);
6510 cmpl(cnt1, stride);
6511 jcc(Assembler::less, SCAN_TO_CHAR);
6512 if (UseAVX < 2) {
6513 movdl(vec1, ch);
6514 pshuflw(vec1, vec1, 0x00);
6515 pshufd(vec1, vec1, 0);
6516 pxor(vec2, vec2);
6517 }
6518 movl(tmp, cnt1);
6519 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
6520 andl(cnt1,0x00000007); //tail count (in chars)
6521
6522 bind(SCAN_TO_8_CHAR_LOOP);
6523 movdqu(vec3, Address(result, 0));
6524 pcmpeqw(vec3, vec1);
6525 ptest(vec2, vec3);
6526 jcc(Assembler::carryClear, FOUND_CHAR);
6527 addptr(result, 16);
6528 subl(tmp, stride);
6529 jcc(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
6530 bind(SCAN_TO_CHAR);
6531 testl(cnt1, cnt1);
6532 jcc(Assembler::zero, RET_NOT_FOUND);
6533 bind(SCAN_TO_CHAR_LOOP);
6534 load_unsigned_short(tmp, Address(result, 0));
6535 cmpl(ch, tmp);
6536 jccb(Assembler::equal, FOUND_SEQ_CHAR);
6537 addptr(result, 2);
6538 subl(cnt1, 1);
6539 jccb(Assembler::zero, RET_NOT_FOUND);
6540 jmp(SCAN_TO_CHAR_LOOP);
6541
6542 bind(RET_NOT_FOUND);
6543 movl(result, -1);
6544 jmpb(DONE_LABEL);
6545
6546 bind(FOUND_CHAR);
6547 if (UseAVX >= 2) {
6548 vpmovmskb(tmp, vec3);
6549 } else {
6550 pmovmskb(tmp, vec3);
6551 }
6552 bsfl(ch, tmp);
6553 addl(result, ch);
6554
6555 bind(FOUND_SEQ_CHAR);
6556 subptr(result, str1);
6557 shrl(result, 1);
6558
6559 bind(DONE_LABEL);
6560 } // string_indexof_char
6561
6562 // helper function for string_compare
6563 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
6564 Address::ScaleFactor scale, Address::ScaleFactor scale1,
6565 Address::ScaleFactor scale2, Register index, int ae) {
6566 if (ae == StrIntrinsicNode::LL) {
6567 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
6568 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
6569 } else if (ae == StrIntrinsicNode::UU) {
6570 load_unsigned_short(elem1, Address(str1, index, scale, 0));
6571 load_unsigned_short(elem2, Address(str2, index, scale, 0));
6572 } else {
6573 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
6574 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
6575 }
6576 }
6577
6578 // Compare strings, used for char[] and byte[].
6579 void MacroAssembler::string_compare(Register str1, Register str2,
6580 Register cnt1, Register cnt2, Register result,
6581 XMMRegister vec1, int ae) {
6582 ShortBranchVerifier sbv(this);
6583 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6584 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
6585 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
6586 int stride2x2 = 0x40;
6587 Address::ScaleFactor scale = Address::no_scale;
6588 Address::ScaleFactor scale1 = Address::no_scale;
6589 Address::ScaleFactor scale2 = Address::no_scale;
6590
6591 if (ae != StrIntrinsicNode::LL) {
6592 stride2x2 = 0x20;
6593 }
6594
6595 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
6596 shrl(cnt2, 1);
6597 }
6598 // Compute the minimum of the string lengths and the
6599 // difference of the string lengths (stack).
6600 // Do the conditional move stuff
6601 movl(result, cnt1);
6602 subl(cnt1, cnt2);
6603 push(cnt1);
6604 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
6605
6606 // Is the minimum length zero?
6607 testl(cnt2, cnt2);
6608 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6609 if (ae == StrIntrinsicNode::LL) {
6610 // Load first bytes
6611 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
6612 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
6613 } else if (ae == StrIntrinsicNode::UU) {
6614 // Load first characters
6615 load_unsigned_short(result, Address(str1, 0));
6616 load_unsigned_short(cnt1, Address(str2, 0));
6617 } else {
6618 load_unsigned_byte(result, Address(str1, 0));
6619 load_unsigned_short(cnt1, Address(str2, 0));
6620 }
6621 subl(result, cnt1);
6622 jcc(Assembler::notZero, POP_LABEL);
6623
6624 if (ae == StrIntrinsicNode::UU) {
6625 // Divide length by 2 to get number of chars
6626 shrl(cnt2, 1);
6627 }
6628 cmpl(cnt2, 1);
6629 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6630
6631 // Check if the strings start at the same location and setup scale and stride
6632 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6633 cmpptr(str1, str2);
6634 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6635 if (ae == StrIntrinsicNode::LL) {
6636 scale = Address::times_1;
6637 stride = 16;
6638 } else {
6639 scale = Address::times_2;
6640 stride = 8;
6641 }
6642 } else {
6643 scale1 = Address::times_1;
6644 scale2 = Address::times_2;
6645 // scale not used
6646 stride = 8;
6647 }
6648
6649 if (UseAVX >= 2 && UseSSE42Intrinsics) {
6650 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6651 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6652 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
6653 Label COMPARE_TAIL_LONG;
6654 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
6655
6656 int pcmpmask = 0x19;
6657 if (ae == StrIntrinsicNode::LL) {
6658 pcmpmask &= ~0x01;
6659 }
6660
6661 // Setup to compare 16-chars (32-bytes) vectors,
6662 // start from first character again because it has aligned address.
6663 if (ae == StrIntrinsicNode::LL) {
6664 stride2 = 32;
6665 } else {
6666 stride2 = 16;
6667 }
6668 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6669 adr_stride = stride << scale;
6670 } else {
6671 adr_stride1 = 8; //stride << scale1;
6672 adr_stride2 = 16; //stride << scale2;
6673 }
6674
6675 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6676 // rax and rdx are used by pcmpestri as elements counters
6677 movl(result, cnt2);
6678 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
6679 jcc(Assembler::zero, COMPARE_TAIL_LONG);
6680
6681 // fast path : compare first 2 8-char vectors.
6682 bind(COMPARE_16_CHARS);
6683 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6684 movdqu(vec1, Address(str1, 0));
6685 } else {
6686 pmovzxbw(vec1, Address(str1, 0));
6687 }
6688 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6689 jccb(Assembler::below, COMPARE_INDEX_CHAR);
6690
6691 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6692 movdqu(vec1, Address(str1, adr_stride));
6693 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6694 } else {
6695 pmovzxbw(vec1, Address(str1, adr_stride1));
6696 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
6697 }
6698 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6699 addl(cnt1, stride);
6700
6701 // Compare the characters at index in cnt1
6702 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
6703 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
6704 subl(result, cnt2);
6705 jmp(POP_LABEL);
6706
6707 // Setup the registers to start vector comparison loop
6708 bind(COMPARE_WIDE_VECTORS);
6709 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6710 lea(str1, Address(str1, result, scale));
6711 lea(str2, Address(str2, result, scale));
6712 } else {
6713 lea(str1, Address(str1, result, scale1));
6714 lea(str2, Address(str2, result, scale2));
6715 }
6716 subl(result, stride2);
6717 subl(cnt2, stride2);
6718 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
6719 negptr(result);
6720
6721 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6722 bind(COMPARE_WIDE_VECTORS_LOOP);
6723
6724 #ifdef _LP64
6725 if ((AVX3Threshold == 0) && VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
6726 cmpl(cnt2, stride2x2);
6727 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
6728 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
6729 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
6730
6731 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
6732 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6733 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
6734 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
6735 } else {
6736 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
6737 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
6738 }
6739 kortestql(k7, k7);
6740 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
6741 addptr(result, stride2x2); // update since we already compared at this addr
6742 subl(cnt2, stride2x2); // and sub the size too
6743 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
6744
6745 vpxor(vec1, vec1);
6746 jmpb(COMPARE_WIDE_TAIL);
6747 }//if (VM_Version::supports_avx512vlbw())
6748 #endif // _LP64
6749
6750
6751 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6752 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6753 vmovdqu(vec1, Address(str1, result, scale));
6754 vpxor(vec1, Address(str2, result, scale));
6755 } else {
6756 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
6757 vpxor(vec1, Address(str2, result, scale2));
6758 }
6759 vptest(vec1, vec1);
6760 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
6761 addptr(result, stride2);
6762 subl(cnt2, stride2);
6763 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6764 // clean upper bits of YMM registers
6765 vpxor(vec1, vec1);
6766
6767 // compare wide vectors tail
6768 bind(COMPARE_WIDE_TAIL);
6769 testptr(result, result);
6770 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6771
6772 movl(result, stride2);
6773 movl(cnt2, result);
6774 negptr(result);
6775 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6776
6777 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6778 bind(VECTOR_NOT_EQUAL);
6779 // clean upper bits of YMM registers
6780 vpxor(vec1, vec1);
6781 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6782 lea(str1, Address(str1, result, scale));
6783 lea(str2, Address(str2, result, scale));
6784 } else {
6785 lea(str1, Address(str1, result, scale1));
6786 lea(str2, Address(str2, result, scale2));
6787 }
6788 jmp(COMPARE_16_CHARS);
6789
6790 // Compare tail chars, length between 1 to 15 chars
6791 bind(COMPARE_TAIL_LONG);
6792 movl(cnt2, result);
6793 cmpl(cnt2, stride);
6794 jcc(Assembler::less, COMPARE_SMALL_STR);
6795
6796 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6797 movdqu(vec1, Address(str1, 0));
6798 } else {
6799 pmovzxbw(vec1, Address(str1, 0));
6800 }
6801 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6802 jcc(Assembler::below, COMPARE_INDEX_CHAR);
6803 subptr(cnt2, stride);
6804 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6805 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6806 lea(str1, Address(str1, result, scale));
6807 lea(str2, Address(str2, result, scale));
6808 } else {
6809 lea(str1, Address(str1, result, scale1));
6810 lea(str2, Address(str2, result, scale2));
6811 }
6812 negptr(cnt2);
6813 jmpb(WHILE_HEAD_LABEL);
6814
6815 bind(COMPARE_SMALL_STR);
6816 } else if (UseSSE42Intrinsics) {
6817 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6818 int pcmpmask = 0x19;
6819 // Setup to compare 8-char (16-byte) vectors,
6820 // start from first character again because it has aligned address.
6821 movl(result, cnt2);
6822 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
6823 if (ae == StrIntrinsicNode::LL) {
6824 pcmpmask &= ~0x01;
6825 }
6826 jcc(Assembler::zero, COMPARE_TAIL);
6827 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6828 lea(str1, Address(str1, result, scale));
6829 lea(str2, Address(str2, result, scale));
6830 } else {
6831 lea(str1, Address(str1, result, scale1));
6832 lea(str2, Address(str2, result, scale2));
6833 }
6834 negptr(result);
6835
6836 // pcmpestri
6837 // inputs:
6838 // vec1- substring
6839 // rax - negative string length (elements count)
6840 // mem - scanned string
6841 // rdx - string length (elements count)
6842 // pcmpmask - cmp mode: 11000 (string compare with negated result)
6843 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
6844 // outputs:
6845 // rcx - first mismatched element index
6846 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6847
6848 bind(COMPARE_WIDE_VECTORS);
6849 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6850 movdqu(vec1, Address(str1, result, scale));
6851 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6852 } else {
6853 pmovzxbw(vec1, Address(str1, result, scale1));
6854 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
6855 }
6856 // After pcmpestri cnt1(rcx) contains mismatched element index
6857
6858 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
6859 addptr(result, stride);
6860 subptr(cnt2, stride);
6861 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6862
6863 // compare wide vectors tail
6864 testptr(result, result);
6865 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6866
6867 movl(cnt2, stride);
6868 movl(result, stride);
6869 negptr(result);
6870 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6871 movdqu(vec1, Address(str1, result, scale));
6872 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6873 } else {
6874 pmovzxbw(vec1, Address(str1, result, scale1));
6875 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
6876 }
6877 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6878
6879 // Mismatched characters in the vectors
6880 bind(VECTOR_NOT_EQUAL);
6881 addptr(cnt1, result);
6882 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
6883 subl(result, cnt2);
6884 jmpb(POP_LABEL);
6885
6886 bind(COMPARE_TAIL); // limit is zero
6887 movl(cnt2, result);
6888 // Fallthru to tail compare
6889 }
6890 // Shift str2 and str1 to the end of the arrays, negate min
6891 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6892 lea(str1, Address(str1, cnt2, scale));
6893 lea(str2, Address(str2, cnt2, scale));
6894 } else {
6895 lea(str1, Address(str1, cnt2, scale1));
6896 lea(str2, Address(str2, cnt2, scale2));
6897 }
6898 decrementl(cnt2); // first character was compared already
6899 negptr(cnt2);
6900
6901 // Compare the rest of the elements
6902 bind(WHILE_HEAD_LABEL);
6903 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
6904 subl(result, cnt1);
6905 jccb(Assembler::notZero, POP_LABEL);
6906 increment(cnt2);
6907 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6908
6909 // Strings are equal up to min length. Return the length difference.
6910 bind(LENGTH_DIFF_LABEL);
6911 pop(result);
6912 if (ae == StrIntrinsicNode::UU) {
6913 // Divide diff by 2 to get number of chars
6914 sarl(result, 1);
6915 }
6916 jmpb(DONE_LABEL);
6917
6918 #ifdef _LP64
6919 if (VM_Version::supports_avx512vlbw()) {
6920
6921 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
6922
6923 kmovql(cnt1, k7);
6924 notq(cnt1);
6925 bsfq(cnt2, cnt1);
6926 if (ae != StrIntrinsicNode::LL) {
6927 // Divide diff by 2 to get number of chars
6928 sarl(cnt2, 1);
6929 }
6930 addq(result, cnt2);
6931 if (ae == StrIntrinsicNode::LL) {
6932 load_unsigned_byte(cnt1, Address(str2, result));
6933 load_unsigned_byte(result, Address(str1, result));
6934 } else if (ae == StrIntrinsicNode::UU) {
6935 load_unsigned_short(cnt1, Address(str2, result, scale));
6936 load_unsigned_short(result, Address(str1, result, scale));
6937 } else {
6938 load_unsigned_short(cnt1, Address(str2, result, scale2));
6939 load_unsigned_byte(result, Address(str1, result, scale1));
6940 }
6941 subl(result, cnt1);
6942 jmpb(POP_LABEL);
6943 }//if (VM_Version::supports_avx512vlbw())
6944 #endif // _LP64
6945
6946 // Discard the stored length difference
6947 bind(POP_LABEL);
6948 pop(cnt1);
6949
6950 // That's it
6951 bind(DONE_LABEL);
6952 if(ae == StrIntrinsicNode::UL) {
6953 negl(result);
6954 }
6955
6956 }
6957
6958 // Search for Non-ASCII character (Negative byte value) in a byte array,
6959 // return true if it has any and false otherwise.
6960 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
6961 // @HotSpotIntrinsicCandidate
6962 // private static boolean hasNegatives(byte[] ba, int off, int len) {
6963 // for (int i = off; i < off + len; i++) {
6964 // if (ba[i] < 0) {
6965 // return true;
6966 // }
6967 // }
6968 // return false;
6969 // }
6970 void MacroAssembler::has_negatives(Register ary1, Register len,
6971 Register result, Register tmp1,
6972 XMMRegister vec1, XMMRegister vec2) {
6973 // rsi: byte array
6974 // rcx: len
6975 // rax: result
6976 ShortBranchVerifier sbv(this);
6977 assert_different_registers(ary1, len, result, tmp1);
6978 assert_different_registers(vec1, vec2);
6979 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
6980
6981 // len == 0
6982 testl(len, len);
6983 jcc(Assembler::zero, FALSE_LABEL);
6984
6985 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
6986 VM_Version::supports_avx512vlbw() &&
6987 VM_Version::supports_bmi2()) {
6988
6989 Label test_64_loop, test_tail;
6990 Register tmp3_aliased = len;
6991
6992 movl(tmp1, len);
6993 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
6994
6995 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
6996 andl(len, ~(64 - 1)); // vector count (in chars)
6997 jccb(Assembler::zero, test_tail);
6998
6999 lea(ary1, Address(ary1, len, Address::times_1));
7000 negptr(len);
7001
7002 bind(test_64_loop);
7003 // Check whether our 64 elements of size byte contain negatives
7004 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
7005 kortestql(k2, k2);
7006 jcc(Assembler::notZero, TRUE_LABEL);
7007
7008 addptr(len, 64);
7009 jccb(Assembler::notZero, test_64_loop);
7010
7011
7012 bind(test_tail);
7013 // bail out when there is nothing to be done
7014 testl(tmp1, -1);
7015 jcc(Assembler::zero, FALSE_LABEL);
7016
7017 // ~(~0 << len) applied up to two times (for 32-bit scenario)
7018 #ifdef _LP64
7019 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
7020 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
7021 notq(tmp3_aliased);
7022 kmovql(k3, tmp3_aliased);
7023 #else
7024 Label k_init;
7025 jmp(k_init);
7026
7027 // We could not read 64-bits from a general purpose register thus we move
7028 // data required to compose 64 1's to the instruction stream
7029 // We emit 64 byte wide series of elements from 0..63 which later on would
7030 // be used as a compare targets with tail count contained in tmp1 register.
7031 // Result would be a k register having tmp1 consecutive number or 1
7032 // counting from least significant bit.
7033 address tmp = pc();
7034 emit_int64(0x0706050403020100);
7035 emit_int64(0x0F0E0D0C0B0A0908);
7036 emit_int64(0x1716151413121110);
7037 emit_int64(0x1F1E1D1C1B1A1918);
7038 emit_int64(0x2726252423222120);
7039 emit_int64(0x2F2E2D2C2B2A2928);
7040 emit_int64(0x3736353433323130);
7041 emit_int64(0x3F3E3D3C3B3A3938);
7042
7043 bind(k_init);
7044 lea(len, InternalAddress(tmp));
7045 // create mask to test for negative byte inside a vector
7046 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
7047 evpcmpgtb(k3, vec1, Address(len, 0), Assembler::AVX_512bit);
7048
7049 #endif
7050 evpcmpgtb(k2, k3, vec2, Address(ary1, 0), Assembler::AVX_512bit);
7051 ktestq(k2, k3);
7052 jcc(Assembler::notZero, TRUE_LABEL);
7053
7054 jmp(FALSE_LABEL);
7055 } else {
7056 movl(result, len); // copy
7057
7058 if (UseAVX >= 2 && UseSSE >= 2) {
7059 // With AVX2, use 32-byte vector compare
7060 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7061
7062 // Compare 32-byte vectors
7063 andl(result, 0x0000001f); // tail count (in bytes)
7064 andl(len, 0xffffffe0); // vector count (in bytes)
7065 jccb(Assembler::zero, COMPARE_TAIL);
7066
7067 lea(ary1, Address(ary1, len, Address::times_1));
7068 negptr(len);
7069
7070 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
7071 movdl(vec2, tmp1);
7072 vpbroadcastd(vec2, vec2, Assembler::AVX_256bit);
7073
7074 bind(COMPARE_WIDE_VECTORS);
7075 vmovdqu(vec1, Address(ary1, len, Address::times_1));
7076 vptest(vec1, vec2);
7077 jccb(Assembler::notZero, TRUE_LABEL);
7078 addptr(len, 32);
7079 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7080
7081 testl(result, result);
7082 jccb(Assembler::zero, FALSE_LABEL);
7083
7084 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
7085 vptest(vec1, vec2);
7086 jccb(Assembler::notZero, TRUE_LABEL);
7087 jmpb(FALSE_LABEL);
7088
7089 bind(COMPARE_TAIL); // len is zero
7090 movl(len, result);
7091 // Fallthru to tail compare
7092 } else if (UseSSE42Intrinsics) {
7093 // With SSE4.2, use double quad vector compare
7094 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7095
7096 // Compare 16-byte vectors
7097 andl(result, 0x0000000f); // tail count (in bytes)
7098 andl(len, 0xfffffff0); // vector count (in bytes)
7099 jcc(Assembler::zero, COMPARE_TAIL);
7100
7101 lea(ary1, Address(ary1, len, Address::times_1));
7102 negptr(len);
7103
7104 movl(tmp1, 0x80808080);
7105 movdl(vec2, tmp1);
7106 pshufd(vec2, vec2, 0);
7107
7108 bind(COMPARE_WIDE_VECTORS);
7109 movdqu(vec1, Address(ary1, len, Address::times_1));
7110 ptest(vec1, vec2);
7111 jcc(Assembler::notZero, TRUE_LABEL);
7112 addptr(len, 16);
7113 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7114
7115 testl(result, result);
7116 jcc(Assembler::zero, FALSE_LABEL);
7117
7118 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7119 ptest(vec1, vec2);
7120 jccb(Assembler::notZero, TRUE_LABEL);
7121 jmpb(FALSE_LABEL);
7122
7123 bind(COMPARE_TAIL); // len is zero
7124 movl(len, result);
7125 // Fallthru to tail compare
7126 }
7127 }
7128 // Compare 4-byte vectors
7129 andl(len, 0xfffffffc); // vector count (in bytes)
7130 jccb(Assembler::zero, COMPARE_CHAR);
7131
7132 lea(ary1, Address(ary1, len, Address::times_1));
7133 negptr(len);
7134
7135 bind(COMPARE_VECTORS);
7136 movl(tmp1, Address(ary1, len, Address::times_1));
7137 andl(tmp1, 0x80808080);
7138 jccb(Assembler::notZero, TRUE_LABEL);
7139 addptr(len, 4);
7140 jcc(Assembler::notZero, COMPARE_VECTORS);
7141
7142 // Compare trailing char (final 2 bytes), if any
7143 bind(COMPARE_CHAR);
7144 testl(result, 0x2); // tail char
7145 jccb(Assembler::zero, COMPARE_BYTE);
7146 load_unsigned_short(tmp1, Address(ary1, 0));
7147 andl(tmp1, 0x00008080);
7148 jccb(Assembler::notZero, TRUE_LABEL);
7149 subptr(result, 2);
7150 lea(ary1, Address(ary1, 2));
7151
7152 bind(COMPARE_BYTE);
7153 testl(result, 0x1); // tail byte
7154 jccb(Assembler::zero, FALSE_LABEL);
7155 load_unsigned_byte(tmp1, Address(ary1, 0));
7156 andl(tmp1, 0x00000080);
7157 jccb(Assembler::notEqual, TRUE_LABEL);
7158 jmpb(FALSE_LABEL);
7159
7160 bind(TRUE_LABEL);
7161 movl(result, 1); // return true
7162 jmpb(DONE);
7163
7164 bind(FALSE_LABEL);
7165 xorl(result, result); // return false
7166
7167 // That's it
7168 bind(DONE);
7169 if (UseAVX >= 2 && UseSSE >= 2) {
7170 // clean upper bits of YMM registers
7171 vpxor(vec1, vec1);
7172 vpxor(vec2, vec2);
7173 }
7174 }
7175 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
7176 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
7177 Register limit, Register result, Register chr,
7178 XMMRegister vec1, XMMRegister vec2, bool is_char) {
7179 ShortBranchVerifier sbv(this);
7180 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
7181
7182 int length_offset = arrayOopDesc::length_offset_in_bytes();
7183 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
7184
7185 if (is_array_equ) {
7186 // Check the input args
7187 cmpoop(ary1, ary2);
7188 jcc(Assembler::equal, TRUE_LABEL);
7189
7190 // Need additional checks for arrays_equals.
7191 testptr(ary1, ary1);
7192 jcc(Assembler::zero, FALSE_LABEL);
7193 testptr(ary2, ary2);
7194 jcc(Assembler::zero, FALSE_LABEL);
7195
7196 // Check the lengths
7197 movl(limit, Address(ary1, length_offset));
7198 cmpl(limit, Address(ary2, length_offset));
7199 jcc(Assembler::notEqual, FALSE_LABEL);
7200 }
7201
7202 // count == 0
7203 testl(limit, limit);
7204 jcc(Assembler::zero, TRUE_LABEL);
7205
7206 if (is_array_equ) {
7207 // Load array address
7208 lea(ary1, Address(ary1, base_offset));
7209 lea(ary2, Address(ary2, base_offset));
7210 }
7211
7212 if (is_array_equ && is_char) {
7213 // arrays_equals when used for char[].
7214 shll(limit, 1); // byte count != 0
7215 }
7216 movl(result, limit); // copy
7217
7218 if (UseAVX >= 2) {
7219 // With AVX2, use 32-byte vector compare
7220 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7221
7222 // Compare 32-byte vectors
7223 andl(result, 0x0000001f); // tail count (in bytes)
7224 andl(limit, 0xffffffe0); // vector count (in bytes)
7225 jcc(Assembler::zero, COMPARE_TAIL);
7226
7227 lea(ary1, Address(ary1, limit, Address::times_1));
7228 lea(ary2, Address(ary2, limit, Address::times_1));
7229 negptr(limit);
7230
7231 #ifdef _LP64
7232 if ((AVX3Threshold == 0) && VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7233 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
7234
7235 cmpl(limit, -64);
7236 jcc(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7237
7238 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7239
7240 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
7241 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
7242 kortestql(k7, k7);
7243 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
7244 addptr(limit, 64); // update since we already compared at this addr
7245 cmpl(limit, -64);
7246 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7247
7248 // At this point we may still need to compare -limit+result bytes.
7249 // We could execute the next two instruction and just continue via non-wide path:
7250 // cmpl(limit, 0);
7251 // jcc(Assembler::equal, COMPARE_TAIL); // true
7252 // But since we stopped at the points ary{1,2}+limit which are
7253 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
7254 // (|limit| <= 32 and result < 32),
7255 // we may just compare the last 64 bytes.
7256 //
7257 addptr(result, -64); // it is safe, bc we just came from this area
7258 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
7259 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
7260 kortestql(k7, k7);
7261 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
7262
7263 jmp(TRUE_LABEL);
7264
7265 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7266
7267 }//if (VM_Version::supports_avx512vlbw())
7268 #endif //_LP64
7269 bind(COMPARE_WIDE_VECTORS);
7270 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
7271 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
7272 vpxor(vec1, vec2);
7273
7274 vptest(vec1, vec1);
7275 jcc(Assembler::notZero, FALSE_LABEL);
7276 addptr(limit, 32);
7277 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7278
7279 testl(result, result);
7280 jcc(Assembler::zero, TRUE_LABEL);
7281
7282 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
7283 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
7284 vpxor(vec1, vec2);
7285
7286 vptest(vec1, vec1);
7287 jccb(Assembler::notZero, FALSE_LABEL);
7288 jmpb(TRUE_LABEL);
7289
7290 bind(COMPARE_TAIL); // limit is zero
7291 movl(limit, result);
7292 // Fallthru to tail compare
7293 } else if (UseSSE42Intrinsics) {
7294 // With SSE4.2, use double quad vector compare
7295 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7296
7297 // Compare 16-byte vectors
7298 andl(result, 0x0000000f); // tail count (in bytes)
7299 andl(limit, 0xfffffff0); // vector count (in bytes)
7300 jcc(Assembler::zero, COMPARE_TAIL);
7301
7302 lea(ary1, Address(ary1, limit, Address::times_1));
7303 lea(ary2, Address(ary2, limit, Address::times_1));
7304 negptr(limit);
7305
7306 bind(COMPARE_WIDE_VECTORS);
7307 movdqu(vec1, Address(ary1, limit, Address::times_1));
7308 movdqu(vec2, Address(ary2, limit, Address::times_1));
7309 pxor(vec1, vec2);
7310
7311 ptest(vec1, vec1);
7312 jcc(Assembler::notZero, FALSE_LABEL);
7313 addptr(limit, 16);
7314 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7315
7316 testl(result, result);
7317 jcc(Assembler::zero, TRUE_LABEL);
7318
7319 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7320 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
7321 pxor(vec1, vec2);
7322
7323 ptest(vec1, vec1);
7324 jccb(Assembler::notZero, FALSE_LABEL);
7325 jmpb(TRUE_LABEL);
7326
7327 bind(COMPARE_TAIL); // limit is zero
7328 movl(limit, result);
7329 // Fallthru to tail compare
7330 }
7331
7332 // Compare 4-byte vectors
7333 andl(limit, 0xfffffffc); // vector count (in bytes)
7334 jccb(Assembler::zero, COMPARE_CHAR);
7335
7336 lea(ary1, Address(ary1, limit, Address::times_1));
7337 lea(ary2, Address(ary2, limit, Address::times_1));
7338 negptr(limit);
7339
7340 bind(COMPARE_VECTORS);
7341 movl(chr, Address(ary1, limit, Address::times_1));
7342 cmpl(chr, Address(ary2, limit, Address::times_1));
7343 jccb(Assembler::notEqual, FALSE_LABEL);
7344 addptr(limit, 4);
7345 jcc(Assembler::notZero, COMPARE_VECTORS);
7346
7347 // Compare trailing char (final 2 bytes), if any
7348 bind(COMPARE_CHAR);
7349 testl(result, 0x2); // tail char
7350 jccb(Assembler::zero, COMPARE_BYTE);
7351 load_unsigned_short(chr, Address(ary1, 0));
7352 load_unsigned_short(limit, Address(ary2, 0));
7353 cmpl(chr, limit);
7354 jccb(Assembler::notEqual, FALSE_LABEL);
7355
7356 if (is_array_equ && is_char) {
7357 bind(COMPARE_BYTE);
7358 } else {
7359 lea(ary1, Address(ary1, 2));
7360 lea(ary2, Address(ary2, 2));
7361
7362 bind(COMPARE_BYTE);
7363 testl(result, 0x1); // tail byte
7364 jccb(Assembler::zero, TRUE_LABEL);
7365 load_unsigned_byte(chr, Address(ary1, 0));
7366 load_unsigned_byte(limit, Address(ary2, 0));
7367 cmpl(chr, limit);
7368 jccb(Assembler::notEqual, FALSE_LABEL);
7369 }
7370 bind(TRUE_LABEL);
7371 movl(result, 1); // return true
7372 jmpb(DONE);
7373
7374 bind(FALSE_LABEL);
7375 xorl(result, result); // return false
7376
7377 // That's it
7378 bind(DONE);
7379 if (UseAVX >= 2) {
7380 // clean upper bits of YMM registers
7381 vpxor(vec1, vec1);
7382 vpxor(vec2, vec2);
7383 }
7384 }
7385
7386 #endif
7387
7388 void MacroAssembler::generate_fill(BasicType t, bool aligned,
7389 Register to, Register value, Register count,
7390 Register rtmp, XMMRegister xtmp) {
7391 ShortBranchVerifier sbv(this);
7392 assert_different_registers(to, value, count, rtmp);
7393 Label L_exit;
7394 Label L_fill_2_bytes, L_fill_4_bytes;
7395
7396 int shift = -1;
7397 switch (t) {
7398 case T_BYTE:
7399 shift = 2;
7400 break;
7401 case T_SHORT:
7402 shift = 1;
7403 break;
7404 case T_INT:
7405 shift = 0;
7406 break;
7407 default: ShouldNotReachHere();
7408 }
7409
7410 if (t == T_BYTE) {
7411 andl(value, 0xff);
7412 movl(rtmp, value);
7413 shll(rtmp, 8);
7414 orl(value, rtmp);
7415 }
7416 if (t == T_SHORT) {
7417 andl(value, 0xffff);
7418 }
7419 if (t == T_BYTE || t == T_SHORT) {
7420 movl(rtmp, value);
7421 shll(rtmp, 16);
7422 orl(value, rtmp);
7423 }
7424
7425 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7426 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7427 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7428 Label L_skip_align2;
7429 // align source address at 4 bytes address boundary
7430 if (t == T_BYTE) {
7431 Label L_skip_align1;
7432 // One byte misalignment happens only for byte arrays
7433 testptr(to, 1);
7434 jccb(Assembler::zero, L_skip_align1);
7435 movb(Address(to, 0), value);
7436 increment(to);
7437 decrement(count);
7438 BIND(L_skip_align1);
7439 }
7440 // Two bytes misalignment happens only for byte and short (char) arrays
7441 testptr(to, 2);
7442 jccb(Assembler::zero, L_skip_align2);
7443 movw(Address(to, 0), value);
7444 addptr(to, 2);
7445 subl(count, 1<<(shift-1));
7446 BIND(L_skip_align2);
7447 }
7448 if (UseSSE < 2) {
7449 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7450 // Fill 32-byte chunks
7451 subl(count, 8 << shift);
7452 jcc(Assembler::less, L_check_fill_8_bytes);
7453 align(16);
7454
7455 BIND(L_fill_32_bytes_loop);
7456
7457 for (int i = 0; i < 32; i += 4) {
7458 movl(Address(to, i), value);
7459 }
7460
7461 addptr(to, 32);
7462 subl(count, 8 << shift);
7463 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7464 BIND(L_check_fill_8_bytes);
7465 addl(count, 8 << shift);
7466 jccb(Assembler::zero, L_exit);
7467 jmpb(L_fill_8_bytes);
7468
7469 //
7470 // length is too short, just fill qwords
7471 //
7472 BIND(L_fill_8_bytes_loop);
7473 movl(Address(to, 0), value);
7474 movl(Address(to, 4), value);
7475 addptr(to, 8);
7476 BIND(L_fill_8_bytes);
7477 subl(count, 1 << (shift + 1));
7478 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7479 // fall through to fill 4 bytes
7480 } else {
7481 Label L_fill_32_bytes;
7482 if (!UseUnalignedLoadStores) {
7483 // align to 8 bytes, we know we are 4 byte aligned to start
7484 testptr(to, 4);
7485 jccb(Assembler::zero, L_fill_32_bytes);
7486 movl(Address(to, 0), value);
7487 addptr(to, 4);
7488 subl(count, 1<<shift);
7489 }
7490 BIND(L_fill_32_bytes);
7491 {
7492 assert( UseSSE >= 2, "supported cpu only" );
7493 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7494 movdl(xtmp, value);
7495 if (UseAVX >= 2 && UseUnalignedLoadStores) {
7496 Label L_check_fill_32_bytes;
7497 if (UseAVX > 2) {
7498 // Fill 64-byte chunks
7499 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
7500
7501 // If number of bytes to fill < AVX3Threshold, perform fill using AVX2
7502 cmpl(count, AVX3Threshold);
7503 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
7504
7505 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
7506
7507 subl(count, 16 << shift);
7508 jccb(Assembler::less, L_check_fill_32_bytes);
7509 align(16);
7510
7511 BIND(L_fill_64_bytes_loop_avx3);
7512 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
7513 addptr(to, 64);
7514 subl(count, 16 << shift);
7515 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
7516 jmpb(L_check_fill_32_bytes);
7517
7518 BIND(L_check_fill_64_bytes_avx2);
7519 }
7520 // Fill 64-byte chunks
7521 Label L_fill_64_bytes_loop;
7522 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
7523
7524 subl(count, 16 << shift);
7525 jcc(Assembler::less, L_check_fill_32_bytes);
7526 align(16);
7527
7528 BIND(L_fill_64_bytes_loop);
7529 vmovdqu(Address(to, 0), xtmp);
7530 vmovdqu(Address(to, 32), xtmp);
7531 addptr(to, 64);
7532 subl(count, 16 << shift);
7533 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7534
7535 BIND(L_check_fill_32_bytes);
7536 addl(count, 8 << shift);
7537 jccb(Assembler::less, L_check_fill_8_bytes);
7538 vmovdqu(Address(to, 0), xtmp);
7539 addptr(to, 32);
7540 subl(count, 8 << shift);
7541
7542 BIND(L_check_fill_8_bytes);
7543 // clean upper bits of YMM registers
7544 movdl(xtmp, value);
7545 pshufd(xtmp, xtmp, 0);
7546 } else {
7547 // Fill 32-byte chunks
7548 pshufd(xtmp, xtmp, 0);
7549
7550 subl(count, 8 << shift);
7551 jcc(Assembler::less, L_check_fill_8_bytes);
7552 align(16);
7553
7554 BIND(L_fill_32_bytes_loop);
7555
7556 if (UseUnalignedLoadStores) {
7557 movdqu(Address(to, 0), xtmp);
7558 movdqu(Address(to, 16), xtmp);
7559 } else {
7560 movq(Address(to, 0), xtmp);
7561 movq(Address(to, 8), xtmp);
7562 movq(Address(to, 16), xtmp);
7563 movq(Address(to, 24), xtmp);
7564 }
7565
7566 addptr(to, 32);
7567 subl(count, 8 << shift);
7568 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7569
7570 BIND(L_check_fill_8_bytes);
7571 }
7572 addl(count, 8 << shift);
7573 jccb(Assembler::zero, L_exit);
7574 jmpb(L_fill_8_bytes);
7575
7576 //
7577 // length is too short, just fill qwords
7578 //
7579 BIND(L_fill_8_bytes_loop);
7580 movq(Address(to, 0), xtmp);
7581 addptr(to, 8);
7582 BIND(L_fill_8_bytes);
7583 subl(count, 1 << (shift + 1));
7584 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7585 }
7586 }
7587 // fill trailing 4 bytes
7588 BIND(L_fill_4_bytes);
7589 testl(count, 1<<shift);
7590 jccb(Assembler::zero, L_fill_2_bytes);
7591 movl(Address(to, 0), value);
7592 if (t == T_BYTE || t == T_SHORT) {
7593 Label L_fill_byte;
7594 addptr(to, 4);
7595 BIND(L_fill_2_bytes);
7596 // fill trailing 2 bytes
7597 testl(count, 1<<(shift-1));
7598 jccb(Assembler::zero, L_fill_byte);
7599 movw(Address(to, 0), value);
7600 if (t == T_BYTE) {
7601 addptr(to, 2);
7602 BIND(L_fill_byte);
7603 // fill trailing byte
7604 testl(count, 1);
7605 jccb(Assembler::zero, L_exit);
7606 movb(Address(to, 0), value);
7607 } else {
7608 BIND(L_fill_byte);
7609 }
7610 } else {
7611 BIND(L_fill_2_bytes);
7612 }
7613 BIND(L_exit);
7614 }
7615
7616 // encode char[] to byte[] in ISO_8859_1
7617 //@HotSpotIntrinsicCandidate
7618 //private static int implEncodeISOArray(byte[] sa, int sp,
7619 //byte[] da, int dp, int len) {
7620 // int i = 0;
7621 // for (; i < len; i++) {
7622 // char c = StringUTF16.getChar(sa, sp++);
7623 // if (c > '\u00FF')
7624 // break;
7625 // da[dp++] = (byte)c;
7626 // }
7627 // return i;
7628 //}
7629 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7630 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7631 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7632 Register tmp5, Register result) {
7633
7634 // rsi: src
7635 // rdi: dst
7636 // rdx: len
7637 // rcx: tmp5
7638 // rax: result
7639 ShortBranchVerifier sbv(this);
7640 assert_different_registers(src, dst, len, tmp5, result);
7641 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7642
7643 // set result
7644 xorl(result, result);
7645 // check for zero length
7646 testl(len, len);
7647 jcc(Assembler::zero, L_done);
7648
7649 movl(result, len);
7650
7651 // Setup pointers
7652 lea(src, Address(src, len, Address::times_2)); // char[]
7653 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7654 negptr(len);
7655
7656 if (UseSSE42Intrinsics || UseAVX >= 2) {
7657 Label L_copy_8_chars, L_copy_8_chars_exit;
7658 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7659
7660 if (UseAVX >= 2) {
7661 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7662 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7663 movdl(tmp1Reg, tmp5);
7664 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7665 jmp(L_chars_32_check);
7666
7667 bind(L_copy_32_chars);
7668 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7669 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7670 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7671 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7672 jccb(Assembler::notZero, L_copy_32_chars_exit);
7673 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7674 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7675 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7676
7677 bind(L_chars_32_check);
7678 addptr(len, 32);
7679 jcc(Assembler::lessEqual, L_copy_32_chars);
7680
7681 bind(L_copy_32_chars_exit);
7682 subptr(len, 16);
7683 jccb(Assembler::greater, L_copy_16_chars_exit);
7684
7685 } else if (UseSSE42Intrinsics) {
7686 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7687 movdl(tmp1Reg, tmp5);
7688 pshufd(tmp1Reg, tmp1Reg, 0);
7689 jmpb(L_chars_16_check);
7690 }
7691
7692 bind(L_copy_16_chars);
7693 if (UseAVX >= 2) {
7694 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7695 vptest(tmp2Reg, tmp1Reg);
7696 jcc(Assembler::notZero, L_copy_16_chars_exit);
7697 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7698 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7699 } else {
7700 if (UseAVX > 0) {
7701 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7702 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7703 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7704 } else {
7705 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7706 por(tmp2Reg, tmp3Reg);
7707 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7708 por(tmp2Reg, tmp4Reg);
7709 }
7710 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7711 jccb(Assembler::notZero, L_copy_16_chars_exit);
7712 packuswb(tmp3Reg, tmp4Reg);
7713 }
7714 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7715
7716 bind(L_chars_16_check);
7717 addptr(len, 16);
7718 jcc(Assembler::lessEqual, L_copy_16_chars);
7719
7720 bind(L_copy_16_chars_exit);
7721 if (UseAVX >= 2) {
7722 // clean upper bits of YMM registers
7723 vpxor(tmp2Reg, tmp2Reg);
7724 vpxor(tmp3Reg, tmp3Reg);
7725 vpxor(tmp4Reg, tmp4Reg);
7726 movdl(tmp1Reg, tmp5);
7727 pshufd(tmp1Reg, tmp1Reg, 0);
7728 }
7729 subptr(len, 8);
7730 jccb(Assembler::greater, L_copy_8_chars_exit);
7731
7732 bind(L_copy_8_chars);
7733 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7734 ptest(tmp3Reg, tmp1Reg);
7735 jccb(Assembler::notZero, L_copy_8_chars_exit);
7736 packuswb(tmp3Reg, tmp1Reg);
7737 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7738 addptr(len, 8);
7739 jccb(Assembler::lessEqual, L_copy_8_chars);
7740
7741 bind(L_copy_8_chars_exit);
7742 subptr(len, 8);
7743 jccb(Assembler::zero, L_done);
7744 }
7745
7746 bind(L_copy_1_char);
7747 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7748 testl(tmp5, 0xff00); // check if Unicode char
7749 jccb(Assembler::notZero, L_copy_1_char_exit);
7750 movb(Address(dst, len, Address::times_1, 0), tmp5);
7751 addptr(len, 1);
7752 jccb(Assembler::less, L_copy_1_char);
7753
7754 bind(L_copy_1_char_exit);
7755 addptr(result, len); // len is negative count of not processed elements
7756
7757 bind(L_done);
7758 }
7759
7760 #ifdef _LP64
7761 /**
7762 * Helper for multiply_to_len().
7763 */
7764 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7765 addq(dest_lo, src1);
7766 adcq(dest_hi, 0);
7767 addq(dest_lo, src2);
7768 adcq(dest_hi, 0);
7769 }
7770
7771 /**
7772 * Multiply 64 bit by 64 bit first loop.
7773 */
7774 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7775 Register y, Register y_idx, Register z,
7776 Register carry, Register product,
7777 Register idx, Register kdx) {
7778 //
7779 // jlong carry, x[], y[], z[];
7780 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7781 // huge_128 product = y[idx] * x[xstart] + carry;
7782 // z[kdx] = (jlong)product;
7783 // carry = (jlong)(product >>> 64);
7784 // }
7785 // z[xstart] = carry;
7786 //
7787
7788 Label L_first_loop, L_first_loop_exit;
7789 Label L_one_x, L_one_y, L_multiply;
7790
7791 decrementl(xstart);
7792 jcc(Assembler::negative, L_one_x);
7793
7794 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7795 rorq(x_xstart, 32); // convert big-endian to little-endian
7796
7797 bind(L_first_loop);
7798 decrementl(idx);
7799 jcc(Assembler::negative, L_first_loop_exit);
7800 decrementl(idx);
7801 jcc(Assembler::negative, L_one_y);
7802 movq(y_idx, Address(y, idx, Address::times_4, 0));
7803 rorq(y_idx, 32); // convert big-endian to little-endian
7804 bind(L_multiply);
7805 movq(product, x_xstart);
7806 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7807 addq(product, carry);
7808 adcq(rdx, 0);
7809 subl(kdx, 2);
7810 movl(Address(z, kdx, Address::times_4, 4), product);
7811 shrq(product, 32);
7812 movl(Address(z, kdx, Address::times_4, 0), product);
7813 movq(carry, rdx);
7814 jmp(L_first_loop);
7815
7816 bind(L_one_y);
7817 movl(y_idx, Address(y, 0));
7818 jmp(L_multiply);
7819
7820 bind(L_one_x);
7821 movl(x_xstart, Address(x, 0));
7822 jmp(L_first_loop);
7823
7824 bind(L_first_loop_exit);
7825 }
7826
7827 /**
7828 * Multiply 64 bit by 64 bit and add 128 bit.
7829 */
7830 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7831 Register yz_idx, Register idx,
7832 Register carry, Register product, int offset) {
7833 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7834 // z[kdx] = (jlong)product;
7835
7836 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7837 rorq(yz_idx, 32); // convert big-endian to little-endian
7838 movq(product, x_xstart);
7839 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7840 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7841 rorq(yz_idx, 32); // convert big-endian to little-endian
7842
7843 add2_with_carry(rdx, product, carry, yz_idx);
7844
7845 movl(Address(z, idx, Address::times_4, offset+4), product);
7846 shrq(product, 32);
7847 movl(Address(z, idx, Address::times_4, offset), product);
7848
7849 }
7850
7851 /**
7852 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7853 */
7854 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7855 Register yz_idx, Register idx, Register jdx,
7856 Register carry, Register product,
7857 Register carry2) {
7858 // jlong carry, x[], y[], z[];
7859 // int kdx = ystart+1;
7860 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7861 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7862 // z[kdx+idx+1] = (jlong)product;
7863 // jlong carry2 = (jlong)(product >>> 64);
7864 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7865 // z[kdx+idx] = (jlong)product;
7866 // carry = (jlong)(product >>> 64);
7867 // }
7868 // idx += 2;
7869 // if (idx > 0) {
7870 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7871 // z[kdx+idx] = (jlong)product;
7872 // carry = (jlong)(product >>> 64);
7873 // }
7874 //
7875
7876 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7877
7878 movl(jdx, idx);
7879 andl(jdx, 0xFFFFFFFC);
7880 shrl(jdx, 2);
7881
7882 bind(L_third_loop);
7883 subl(jdx, 1);
7884 jcc(Assembler::negative, L_third_loop_exit);
7885 subl(idx, 4);
7886
7887 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7888 movq(carry2, rdx);
7889
7890 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7891 movq(carry, rdx);
7892 jmp(L_third_loop);
7893
7894 bind (L_third_loop_exit);
7895
7896 andl (idx, 0x3);
7897 jcc(Assembler::zero, L_post_third_loop_done);
7898
7899 Label L_check_1;
7900 subl(idx, 2);
7901 jcc(Assembler::negative, L_check_1);
7902
7903 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7904 movq(carry, rdx);
7905
7906 bind (L_check_1);
7907 addl (idx, 0x2);
7908 andl (idx, 0x1);
7909 subl(idx, 1);
7910 jcc(Assembler::negative, L_post_third_loop_done);
7911
7912 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7913 movq(product, x_xstart);
7914 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7915 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7916
7917 add2_with_carry(rdx, product, yz_idx, carry);
7918
7919 movl(Address(z, idx, Address::times_4, 0), product);
7920 shrq(product, 32);
7921
7922 shlq(rdx, 32);
7923 orq(product, rdx);
7924 movq(carry, product);
7925
7926 bind(L_post_third_loop_done);
7927 }
7928
7929 /**
7930 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7931 *
7932 */
7933 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7934 Register carry, Register carry2,
7935 Register idx, Register jdx,
7936 Register yz_idx1, Register yz_idx2,
7937 Register tmp, Register tmp3, Register tmp4) {
7938 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7939
7940 // jlong carry, x[], y[], z[];
7941 // int kdx = ystart+1;
7942 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7943 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7944 // jlong carry2 = (jlong)(tmp3 >>> 64);
7945 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7946 // carry = (jlong)(tmp4 >>> 64);
7947 // z[kdx+idx+1] = (jlong)tmp3;
7948 // z[kdx+idx] = (jlong)tmp4;
7949 // }
7950 // idx += 2;
7951 // if (idx > 0) {
7952 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7953 // z[kdx+idx] = (jlong)yz_idx1;
7954 // carry = (jlong)(yz_idx1 >>> 64);
7955 // }
7956 //
7957
7958 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7959
7960 movl(jdx, idx);
7961 andl(jdx, 0xFFFFFFFC);
7962 shrl(jdx, 2);
7963
7964 bind(L_third_loop);
7965 subl(jdx, 1);
7966 jcc(Assembler::negative, L_third_loop_exit);
7967 subl(idx, 4);
7968
7969 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7970 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7971 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7972 rorxq(yz_idx2, yz_idx2, 32);
7973
7974 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7975 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7976
7977 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7978 rorxq(yz_idx1, yz_idx1, 32);
7979 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7980 rorxq(yz_idx2, yz_idx2, 32);
7981
7982 if (VM_Version::supports_adx()) {
7983 adcxq(tmp3, carry);
7984 adoxq(tmp3, yz_idx1);
7985
7986 adcxq(tmp4, tmp);
7987 adoxq(tmp4, yz_idx2);
7988
7989 movl(carry, 0); // does not affect flags
7990 adcxq(carry2, carry);
7991 adoxq(carry2, carry);
7992 } else {
7993 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7994 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7995 }
7996 movq(carry, carry2);
7997
7998 movl(Address(z, idx, Address::times_4, 12), tmp3);
7999 shrq(tmp3, 32);
8000 movl(Address(z, idx, Address::times_4, 8), tmp3);
8001
8002 movl(Address(z, idx, Address::times_4, 4), tmp4);
8003 shrq(tmp4, 32);
8004 movl(Address(z, idx, Address::times_4, 0), tmp4);
8005
8006 jmp(L_third_loop);
8007
8008 bind (L_third_loop_exit);
8009
8010 andl (idx, 0x3);
8011 jcc(Assembler::zero, L_post_third_loop_done);
8012
8013 Label L_check_1;
8014 subl(idx, 2);
8015 jcc(Assembler::negative, L_check_1);
8016
8017 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
8018 rorxq(yz_idx1, yz_idx1, 32);
8019 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
8020 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
8021 rorxq(yz_idx2, yz_idx2, 32);
8022
8023 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
8024
8025 movl(Address(z, idx, Address::times_4, 4), tmp3);
8026 shrq(tmp3, 32);
8027 movl(Address(z, idx, Address::times_4, 0), tmp3);
8028 movq(carry, tmp4);
8029
8030 bind (L_check_1);
8031 addl (idx, 0x2);
8032 andl (idx, 0x1);
8033 subl(idx, 1);
8034 jcc(Assembler::negative, L_post_third_loop_done);
8035 movl(tmp4, Address(y, idx, Address::times_4, 0));
8036 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
8037 movl(tmp4, Address(z, idx, Address::times_4, 0));
8038
8039 add2_with_carry(carry2, tmp3, tmp4, carry);
8040
8041 movl(Address(z, idx, Address::times_4, 0), tmp3);
8042 shrq(tmp3, 32);
8043
8044 shlq(carry2, 32);
8045 orq(tmp3, carry2);
8046 movq(carry, tmp3);
8047
8048 bind(L_post_third_loop_done);
8049 }
8050
8051 /**
8052 * Code for BigInteger::multiplyToLen() instrinsic.
8053 *
8054 * rdi: x
8055 * rax: xlen
8056 * rsi: y
8057 * rcx: ylen
8058 * r8: z
8059 * r11: zlen
8060 * r12: tmp1
8061 * r13: tmp2
8062 * r14: tmp3
8063 * r15: tmp4
8064 * rbx: tmp5
8065 *
8066 */
8067 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
8068 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
8069 ShortBranchVerifier sbv(this);
8070 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
8071
8072 push(tmp1);
8073 push(tmp2);
8074 push(tmp3);
8075 push(tmp4);
8076 push(tmp5);
8077
8078 push(xlen);
8079 push(zlen);
8080
8081 const Register idx = tmp1;
8082 const Register kdx = tmp2;
8083 const Register xstart = tmp3;
8084
8085 const Register y_idx = tmp4;
8086 const Register carry = tmp5;
8087 const Register product = xlen;
8088 const Register x_xstart = zlen; // reuse register
8089
8090 // First Loop.
8091 //
8092 // final static long LONG_MASK = 0xffffffffL;
8093 // int xstart = xlen - 1;
8094 // int ystart = ylen - 1;
8095 // long carry = 0;
8096 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8097 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
8098 // z[kdx] = (int)product;
8099 // carry = product >>> 32;
8100 // }
8101 // z[xstart] = (int)carry;
8102 //
8103
8104 movl(idx, ylen); // idx = ylen;
8105 movl(kdx, zlen); // kdx = xlen+ylen;
8106 xorq(carry, carry); // carry = 0;
8107
8108 Label L_done;
8109
8110 movl(xstart, xlen);
8111 decrementl(xstart);
8112 jcc(Assembler::negative, L_done);
8113
8114 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
8115
8116 Label L_second_loop;
8117 testl(kdx, kdx);
8118 jcc(Assembler::zero, L_second_loop);
8119
8120 Label L_carry;
8121 subl(kdx, 1);
8122 jcc(Assembler::zero, L_carry);
8123
8124 movl(Address(z, kdx, Address::times_4, 0), carry);
8125 shrq(carry, 32);
8126 subl(kdx, 1);
8127
8128 bind(L_carry);
8129 movl(Address(z, kdx, Address::times_4, 0), carry);
8130
8131 // Second and third (nested) loops.
8132 //
8133 // for (int i = xstart-1; i >= 0; i--) { // Second loop
8134 // carry = 0;
8135 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
8136 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
8137 // (z[k] & LONG_MASK) + carry;
8138 // z[k] = (int)product;
8139 // carry = product >>> 32;
8140 // }
8141 // z[i] = (int)carry;
8142 // }
8143 //
8144 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
8145
8146 const Register jdx = tmp1;
8147
8148 bind(L_second_loop);
8149 xorl(carry, carry); // carry = 0;
8150 movl(jdx, ylen); // j = ystart+1
8151
8152 subl(xstart, 1); // i = xstart-1;
8153 jcc(Assembler::negative, L_done);
8154
8155 push (z);
8156
8157 Label L_last_x;
8158 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
8159 subl(xstart, 1); // i = xstart-1;
8160 jcc(Assembler::negative, L_last_x);
8161
8162 if (UseBMI2Instructions) {
8163 movq(rdx, Address(x, xstart, Address::times_4, 0));
8164 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
8165 } else {
8166 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8167 rorq(x_xstart, 32); // convert big-endian to little-endian
8168 }
8169
8170 Label L_third_loop_prologue;
8171 bind(L_third_loop_prologue);
8172
8173 push (x);
8174 push (xstart);
8175 push (ylen);
8176
8177
8178 if (UseBMI2Instructions) {
8179 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
8180 } else { // !UseBMI2Instructions
8181 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
8182 }
8183
8184 pop(ylen);
8185 pop(xlen);
8186 pop(x);
8187 pop(z);
8188
8189 movl(tmp3, xlen);
8190 addl(tmp3, 1);
8191 movl(Address(z, tmp3, Address::times_4, 0), carry);
8192 subl(tmp3, 1);
8193 jccb(Assembler::negative, L_done);
8194
8195 shrq(carry, 32);
8196 movl(Address(z, tmp3, Address::times_4, 0), carry);
8197 jmp(L_second_loop);
8198
8199 // Next infrequent code is moved outside loops.
8200 bind(L_last_x);
8201 if (UseBMI2Instructions) {
8202 movl(rdx, Address(x, 0));
8203 } else {
8204 movl(x_xstart, Address(x, 0));
8205 }
8206 jmp(L_third_loop_prologue);
8207
8208 bind(L_done);
8209
8210 pop(zlen);
8211 pop(xlen);
8212
8213 pop(tmp5);
8214 pop(tmp4);
8215 pop(tmp3);
8216 pop(tmp2);
8217 pop(tmp1);
8218 }
8219
8220 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
8221 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
8222 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
8223 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
8224 Label VECTOR8_TAIL, VECTOR4_TAIL;
8225 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
8226 Label SAME_TILL_END, DONE;
8227 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
8228
8229 //scale is in rcx in both Win64 and Unix
8230 ShortBranchVerifier sbv(this);
8231
8232 shlq(length);
8233 xorq(result, result);
8234
8235 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
8236 VM_Version::supports_avx512vlbw()) {
8237 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
8238
8239 cmpq(length, 64);
8240 jcc(Assembler::less, VECTOR32_TAIL);
8241
8242 movq(tmp1, length);
8243 andq(tmp1, 0x3F); // tail count
8244 andq(length, ~(0x3F)); //vector count
8245
8246 bind(VECTOR64_LOOP);
8247 // AVX512 code to compare 64 byte vectors.
8248 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
8249 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
8250 kortestql(k7, k7);
8251 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
8252 addq(result, 64);
8253 subq(length, 64);
8254 jccb(Assembler::notZero, VECTOR64_LOOP);
8255
8256 //bind(VECTOR64_TAIL);
8257 testq(tmp1, tmp1);
8258 jcc(Assembler::zero, SAME_TILL_END);
8259
8260 //bind(VECTOR64_TAIL);
8261 // AVX512 code to compare upto 63 byte vectors.
8262 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
8263 shlxq(tmp2, tmp2, tmp1);
8264 notq(tmp2);
8265 kmovql(k3, tmp2);
8266
8267 evmovdqub(rymm0, k3, Address(obja, result), Assembler::AVX_512bit);
8268 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
8269
8270 ktestql(k7, k3);
8271 jcc(Assembler::below, SAME_TILL_END); // not mismatch
8272
8273 bind(VECTOR64_NOT_EQUAL);
8274 kmovql(tmp1, k7);
8275 notq(tmp1);
8276 tzcntq(tmp1, tmp1);
8277 addq(result, tmp1);
8278 shrq(result);
8279 jmp(DONE);
8280 bind(VECTOR32_TAIL);
8281 }
8282
8283 cmpq(length, 8);
8284 jcc(Assembler::equal, VECTOR8_LOOP);
8285 jcc(Assembler::less, VECTOR4_TAIL);
8286
8287 if (UseAVX >= 2) {
8288 Label VECTOR16_TAIL, VECTOR32_LOOP;
8289
8290 cmpq(length, 16);
8291 jcc(Assembler::equal, VECTOR16_LOOP);
8292 jcc(Assembler::less, VECTOR8_LOOP);
8293
8294 cmpq(length, 32);
8295 jccb(Assembler::less, VECTOR16_TAIL);
8296
8297 subq(length, 32);
8298 bind(VECTOR32_LOOP);
8299 vmovdqu(rymm0, Address(obja, result));
8300 vmovdqu(rymm1, Address(objb, result));
8301 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
8302 vptest(rymm2, rymm2);
8303 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
8304 addq(result, 32);
8305 subq(length, 32);
8306 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
8307 addq(length, 32);
8308 jcc(Assembler::equal, SAME_TILL_END);
8309 //falling through if less than 32 bytes left //close the branch here.
8310
8311 bind(VECTOR16_TAIL);
8312 cmpq(length, 16);
8313 jccb(Assembler::less, VECTOR8_TAIL);
8314 bind(VECTOR16_LOOP);
8315 movdqu(rymm0, Address(obja, result));
8316 movdqu(rymm1, Address(objb, result));
8317 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
8318 ptest(rymm2, rymm2);
8319 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8320 addq(result, 16);
8321 subq(length, 16);
8322 jcc(Assembler::equal, SAME_TILL_END);
8323 //falling through if less than 16 bytes left
8324 } else {//regular intrinsics
8325
8326 cmpq(length, 16);
8327 jccb(Assembler::less, VECTOR8_TAIL);
8328
8329 subq(length, 16);
8330 bind(VECTOR16_LOOP);
8331 movdqu(rymm0, Address(obja, result));
8332 movdqu(rymm1, Address(objb, result));
8333 pxor(rymm0, rymm1);
8334 ptest(rymm0, rymm0);
8335 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8336 addq(result, 16);
8337 subq(length, 16);
8338 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
8339 addq(length, 16);
8340 jcc(Assembler::equal, SAME_TILL_END);
8341 //falling through if less than 16 bytes left
8342 }
8343
8344 bind(VECTOR8_TAIL);
8345 cmpq(length, 8);
8346 jccb(Assembler::less, VECTOR4_TAIL);
8347 bind(VECTOR8_LOOP);
8348 movq(tmp1, Address(obja, result));
8349 movq(tmp2, Address(objb, result));
8350 xorq(tmp1, tmp2);
8351 testq(tmp1, tmp1);
8352 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
8353 addq(result, 8);
8354 subq(length, 8);
8355 jcc(Assembler::equal, SAME_TILL_END);
8356 //falling through if less than 8 bytes left
8357
8358 bind(VECTOR4_TAIL);
8359 cmpq(length, 4);
8360 jccb(Assembler::less, BYTES_TAIL);
8361 bind(VECTOR4_LOOP);
8362 movl(tmp1, Address(obja, result));
8363 xorl(tmp1, Address(objb, result));
8364 testl(tmp1, tmp1);
8365 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
8366 addq(result, 4);
8367 subq(length, 4);
8368 jcc(Assembler::equal, SAME_TILL_END);
8369 //falling through if less than 4 bytes left
8370
8371 bind(BYTES_TAIL);
8372 bind(BYTES_LOOP);
8373 load_unsigned_byte(tmp1, Address(obja, result));
8374 load_unsigned_byte(tmp2, Address(objb, result));
8375 xorl(tmp1, tmp2);
8376 testl(tmp1, tmp1);
8377 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8378 decq(length);
8379 jcc(Assembler::zero, SAME_TILL_END);
8380 incq(result);
8381 load_unsigned_byte(tmp1, Address(obja, result));
8382 load_unsigned_byte(tmp2, Address(objb, result));
8383 xorl(tmp1, tmp2);
8384 testl(tmp1, tmp1);
8385 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8386 decq(length);
8387 jcc(Assembler::zero, SAME_TILL_END);
8388 incq(result);
8389 load_unsigned_byte(tmp1, Address(obja, result));
8390 load_unsigned_byte(tmp2, Address(objb, result));
8391 xorl(tmp1, tmp2);
8392 testl(tmp1, tmp1);
8393 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8394 jmp(SAME_TILL_END);
8395
8396 if (UseAVX >= 2) {
8397 bind(VECTOR32_NOT_EQUAL);
8398 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
8399 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
8400 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
8401 vpmovmskb(tmp1, rymm0);
8402 bsfq(tmp1, tmp1);
8403 addq(result, tmp1);
8404 shrq(result);
8405 jmp(DONE);
8406 }
8407
8408 bind(VECTOR16_NOT_EQUAL);
8409 if (UseAVX >= 2) {
8410 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
8411 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
8412 pxor(rymm0, rymm2);
8413 } else {
8414 pcmpeqb(rymm2, rymm2);
8415 pxor(rymm0, rymm1);
8416 pcmpeqb(rymm0, rymm1);
8417 pxor(rymm0, rymm2);
8418 }
8419 pmovmskb(tmp1, rymm0);
8420 bsfq(tmp1, tmp1);
8421 addq(result, tmp1);
8422 shrq(result);
8423 jmpb(DONE);
8424
8425 bind(VECTOR8_NOT_EQUAL);
8426 bind(VECTOR4_NOT_EQUAL);
8427 bsfq(tmp1, tmp1);
8428 shrq(tmp1, 3);
8429 addq(result, tmp1);
8430 bind(BYTES_NOT_EQUAL);
8431 shrq(result);
8432 jmpb(DONE);
8433
8434 bind(SAME_TILL_END);
8435 mov64(result, -1);
8436
8437 bind(DONE);
8438 }
8439
8440 //Helper functions for square_to_len()
8441
8442 /**
8443 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
8444 * Preserves x and z and modifies rest of the registers.
8445 */
8446 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8447 // Perform square and right shift by 1
8448 // Handle odd xlen case first, then for even xlen do the following
8449 // jlong carry = 0;
8450 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
8451 // huge_128 product = x[j:j+1] * x[j:j+1];
8452 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
8453 // z[i+2:i+3] = (jlong)(product >>> 1);
8454 // carry = (jlong)product;
8455 // }
8456
8457 xorq(tmp5, tmp5); // carry
8458 xorq(rdxReg, rdxReg);
8459 xorl(tmp1, tmp1); // index for x
8460 xorl(tmp4, tmp4); // index for z
8461
8462 Label L_first_loop, L_first_loop_exit;
8463
8464 testl(xlen, 1);
8465 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
8466
8467 // Square and right shift by 1 the odd element using 32 bit multiply
8468 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
8469 imulq(raxReg, raxReg);
8470 shrq(raxReg, 1);
8471 adcq(tmp5, 0);
8472 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
8473 incrementl(tmp1);
8474 addl(tmp4, 2);
8475
8476 // Square and right shift by 1 the rest using 64 bit multiply
8477 bind(L_first_loop);
8478 cmpptr(tmp1, xlen);
8479 jccb(Assembler::equal, L_first_loop_exit);
8480
8481 // Square
8482 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
8483 rorq(raxReg, 32); // convert big-endian to little-endian
8484 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
8485
8486 // Right shift by 1 and save carry
8487 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
8488 rcrq(rdxReg, 1);
8489 rcrq(raxReg, 1);
8490 adcq(tmp5, 0);
8491
8492 // Store result in z
8493 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
8494 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
8495
8496 // Update indices for x and z
8497 addl(tmp1, 2);
8498 addl(tmp4, 4);
8499 jmp(L_first_loop);
8500
8501 bind(L_first_loop_exit);
8502 }
8503
8504
8505 /**
8506 * Perform the following multiply add operation using BMI2 instructions
8507 * carry:sum = sum + op1*op2 + carry
8508 * op2 should be in rdx
8509 * op2 is preserved, all other registers are modified
8510 */
8511 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
8512 // assert op2 is rdx
8513 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
8514 addq(sum, carry);
8515 adcq(tmp2, 0);
8516 addq(sum, op1);
8517 adcq(tmp2, 0);
8518 movq(carry, tmp2);
8519 }
8520
8521 /**
8522 * Perform the following multiply add operation:
8523 * carry:sum = sum + op1*op2 + carry
8524 * Preserves op1, op2 and modifies rest of registers
8525 */
8526 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
8527 // rdx:rax = op1 * op2
8528 movq(raxReg, op2);
8529 mulq(op1);
8530
8531 // rdx:rax = sum + carry + rdx:rax
8532 addq(sum, carry);
8533 adcq(rdxReg, 0);
8534 addq(sum, raxReg);
8535 adcq(rdxReg, 0);
8536
8537 // carry:sum = rdx:sum
8538 movq(carry, rdxReg);
8539 }
8540
8541 /**
8542 * Add 64 bit long carry into z[] with carry propogation.
8543 * Preserves z and carry register values and modifies rest of registers.
8544 *
8545 */
8546 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
8547 Label L_fourth_loop, L_fourth_loop_exit;
8548
8549 movl(tmp1, 1);
8550 subl(zlen, 2);
8551 addq(Address(z, zlen, Address::times_4, 0), carry);
8552
8553 bind(L_fourth_loop);
8554 jccb(Assembler::carryClear, L_fourth_loop_exit);
8555 subl(zlen, 2);
8556 jccb(Assembler::negative, L_fourth_loop_exit);
8557 addq(Address(z, zlen, Address::times_4, 0), tmp1);
8558 jmp(L_fourth_loop);
8559 bind(L_fourth_loop_exit);
8560 }
8561
8562 /**
8563 * Shift z[] left by 1 bit.
8564 * Preserves x, len, z and zlen registers and modifies rest of the registers.
8565 *
8566 */
8567 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
8568
8569 Label L_fifth_loop, L_fifth_loop_exit;
8570
8571 // Fifth loop
8572 // Perform primitiveLeftShift(z, zlen, 1)
8573
8574 const Register prev_carry = tmp1;
8575 const Register new_carry = tmp4;
8576 const Register value = tmp2;
8577 const Register zidx = tmp3;
8578
8579 // int zidx, carry;
8580 // long value;
8581 // carry = 0;
8582 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
8583 // (carry:value) = (z[i] << 1) | carry ;
8584 // z[i] = value;
8585 // }
8586
8587 movl(zidx, zlen);
8588 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
8589
8590 bind(L_fifth_loop);
8591 decl(zidx); // Use decl to preserve carry flag
8592 decl(zidx);
8593 jccb(Assembler::negative, L_fifth_loop_exit);
8594
8595 if (UseBMI2Instructions) {
8596 movq(value, Address(z, zidx, Address::times_4, 0));
8597 rclq(value, 1);
8598 rorxq(value, value, 32);
8599 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8600 }
8601 else {
8602 // clear new_carry
8603 xorl(new_carry, new_carry);
8604
8605 // Shift z[i] by 1, or in previous carry and save new carry
8606 movq(value, Address(z, zidx, Address::times_4, 0));
8607 shlq(value, 1);
8608 adcl(new_carry, 0);
8609
8610 orq(value, prev_carry);
8611 rorq(value, 0x20);
8612 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8613
8614 // Set previous carry = new carry
8615 movl(prev_carry, new_carry);
8616 }
8617 jmp(L_fifth_loop);
8618
8619 bind(L_fifth_loop_exit);
8620 }
8621
8622
8623 /**
8624 * Code for BigInteger::squareToLen() intrinsic
8625 *
8626 * rdi: x
8627 * rsi: len
8628 * r8: z
8629 * rcx: zlen
8630 * r12: tmp1
8631 * r13: tmp2
8632 * r14: tmp3
8633 * r15: tmp4
8634 * rbx: tmp5
8635 *
8636 */
8637 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8638
8639 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
8640 push(tmp1);
8641 push(tmp2);
8642 push(tmp3);
8643 push(tmp4);
8644 push(tmp5);
8645
8646 // First loop
8647 // Store the squares, right shifted one bit (i.e., divided by 2).
8648 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8649
8650 // Add in off-diagonal sums.
8651 //
8652 // Second, third (nested) and fourth loops.
8653 // zlen +=2;
8654 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8655 // carry = 0;
8656 // long op2 = x[xidx:xidx+1];
8657 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8658 // k -= 2;
8659 // long op1 = x[j:j+1];
8660 // long sum = z[k:k+1];
8661 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8662 // z[k:k+1] = sum;
8663 // }
8664 // add_one_64(z, k, carry, tmp_regs);
8665 // }
8666
8667 const Register carry = tmp5;
8668 const Register sum = tmp3;
8669 const Register op1 = tmp4;
8670 Register op2 = tmp2;
8671
8672 push(zlen);
8673 push(len);
8674 addl(zlen,2);
8675 bind(L_second_loop);
8676 xorq(carry, carry);
8677 subl(zlen, 4);
8678 subl(len, 2);
8679 push(zlen);
8680 push(len);
8681 cmpl(len, 0);
8682 jccb(Assembler::lessEqual, L_second_loop_exit);
8683
8684 // Multiply an array by one 64 bit long.
8685 if (UseBMI2Instructions) {
8686 op2 = rdxReg;
8687 movq(op2, Address(x, len, Address::times_4, 0));
8688 rorxq(op2, op2, 32);
8689 }
8690 else {
8691 movq(op2, Address(x, len, Address::times_4, 0));
8692 rorq(op2, 32);
8693 }
8694
8695 bind(L_third_loop);
8696 decrementl(len);
8697 jccb(Assembler::negative, L_third_loop_exit);
8698 decrementl(len);
8699 jccb(Assembler::negative, L_last_x);
8700
8701 movq(op1, Address(x, len, Address::times_4, 0));
8702 rorq(op1, 32);
8703
8704 bind(L_multiply);
8705 subl(zlen, 2);
8706 movq(sum, Address(z, zlen, Address::times_4, 0));
8707
8708 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8709 if (UseBMI2Instructions) {
8710 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8711 }
8712 else {
8713 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8714 }
8715
8716 movq(Address(z, zlen, Address::times_4, 0), sum);
8717
8718 jmp(L_third_loop);
8719 bind(L_third_loop_exit);
8720
8721 // Fourth loop
8722 // Add 64 bit long carry into z with carry propogation.
8723 // Uses offsetted zlen.
8724 add_one_64(z, zlen, carry, tmp1);
8725
8726 pop(len);
8727 pop(zlen);
8728 jmp(L_second_loop);
8729
8730 // Next infrequent code is moved outside loops.
8731 bind(L_last_x);
8732 movl(op1, Address(x, 0));
8733 jmp(L_multiply);
8734
8735 bind(L_second_loop_exit);
8736 pop(len);
8737 pop(zlen);
8738 pop(len);
8739 pop(zlen);
8740
8741 // Fifth loop
8742 // Shift z left 1 bit.
8743 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8744
8745 // z[zlen-1] |= x[len-1] & 1;
8746 movl(tmp3, Address(x, len, Address::times_4, -4));
8747 andl(tmp3, 1);
8748 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8749
8750 pop(tmp5);
8751 pop(tmp4);
8752 pop(tmp3);
8753 pop(tmp2);
8754 pop(tmp1);
8755 }
8756
8757 /**
8758 * Helper function for mul_add()
8759 * Multiply the in[] by int k and add to out[] starting at offset offs using
8760 * 128 bit by 32 bit multiply and return the carry in tmp5.
8761 * Only quad int aligned length of in[] is operated on in this function.
8762 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8763 * This function preserves out, in and k registers.
8764 * len and offset point to the appropriate index in "in" & "out" correspondingly
8765 * tmp5 has the carry.
8766 * other registers are temporary and are modified.
8767 *
8768 */
8769 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8770 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8771 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8772
8773 Label L_first_loop, L_first_loop_exit;
8774
8775 movl(tmp1, len);
8776 shrl(tmp1, 2);
8777
8778 bind(L_first_loop);
8779 subl(tmp1, 1);
8780 jccb(Assembler::negative, L_first_loop_exit);
8781
8782 subl(len, 4);
8783 subl(offset, 4);
8784
8785 Register op2 = tmp2;
8786 const Register sum = tmp3;
8787 const Register op1 = tmp4;
8788 const Register carry = tmp5;
8789
8790 if (UseBMI2Instructions) {
8791 op2 = rdxReg;
8792 }
8793
8794 movq(op1, Address(in, len, Address::times_4, 8));
8795 rorq(op1, 32);
8796 movq(sum, Address(out, offset, Address::times_4, 8));
8797 rorq(sum, 32);
8798 if (UseBMI2Instructions) {
8799 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8800 }
8801 else {
8802 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8803 }
8804 // Store back in big endian from little endian
8805 rorq(sum, 0x20);
8806 movq(Address(out, offset, Address::times_4, 8), sum);
8807
8808 movq(op1, Address(in, len, Address::times_4, 0));
8809 rorq(op1, 32);
8810 movq(sum, Address(out, offset, Address::times_4, 0));
8811 rorq(sum, 32);
8812 if (UseBMI2Instructions) {
8813 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8814 }
8815 else {
8816 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8817 }
8818 // Store back in big endian from little endian
8819 rorq(sum, 0x20);
8820 movq(Address(out, offset, Address::times_4, 0), sum);
8821
8822 jmp(L_first_loop);
8823 bind(L_first_loop_exit);
8824 }
8825
8826 /**
8827 * Code for BigInteger::mulAdd() intrinsic
8828 *
8829 * rdi: out
8830 * rsi: in
8831 * r11: offs (out.length - offset)
8832 * rcx: len
8833 * r8: k
8834 * r12: tmp1
8835 * r13: tmp2
8836 * r14: tmp3
8837 * r15: tmp4
8838 * rbx: tmp5
8839 * Multiply the in[] by word k and add to out[], return the carry in rax
8840 */
8841 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8842 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8843 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8844
8845 Label L_carry, L_last_in, L_done;
8846
8847 // carry = 0;
8848 // for (int j=len-1; j >= 0; j--) {
8849 // long product = (in[j] & LONG_MASK) * kLong +
8850 // (out[offs] & LONG_MASK) + carry;
8851 // out[offs--] = (int)product;
8852 // carry = product >>> 32;
8853 // }
8854 //
8855 push(tmp1);
8856 push(tmp2);
8857 push(tmp3);
8858 push(tmp4);
8859 push(tmp5);
8860
8861 Register op2 = tmp2;
8862 const Register sum = tmp3;
8863 const Register op1 = tmp4;
8864 const Register carry = tmp5;
8865
8866 if (UseBMI2Instructions) {
8867 op2 = rdxReg;
8868 movl(op2, k);
8869 }
8870 else {
8871 movl(op2, k);
8872 }
8873
8874 xorq(carry, carry);
8875
8876 //First loop
8877
8878 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8879 //The carry is in tmp5
8880 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8881
8882 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8883 decrementl(len);
8884 jccb(Assembler::negative, L_carry);
8885 decrementl(len);
8886 jccb(Assembler::negative, L_last_in);
8887
8888 movq(op1, Address(in, len, Address::times_4, 0));
8889 rorq(op1, 32);
8890
8891 subl(offs, 2);
8892 movq(sum, Address(out, offs, Address::times_4, 0));
8893 rorq(sum, 32);
8894
8895 if (UseBMI2Instructions) {
8896 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8897 }
8898 else {
8899 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8900 }
8901
8902 // Store back in big endian from little endian
8903 rorq(sum, 0x20);
8904 movq(Address(out, offs, Address::times_4, 0), sum);
8905
8906 testl(len, len);
8907 jccb(Assembler::zero, L_carry);
8908
8909 //Multiply the last in[] entry, if any
8910 bind(L_last_in);
8911 movl(op1, Address(in, 0));
8912 movl(sum, Address(out, offs, Address::times_4, -4));
8913
8914 movl(raxReg, k);
8915 mull(op1); //tmp4 * eax -> edx:eax
8916 addl(sum, carry);
8917 adcl(rdxReg, 0);
8918 addl(sum, raxReg);
8919 adcl(rdxReg, 0);
8920 movl(carry, rdxReg);
8921
8922 movl(Address(out, offs, Address::times_4, -4), sum);
8923
8924 bind(L_carry);
8925 //return tmp5/carry as carry in rax
8926 movl(rax, carry);
8927
8928 bind(L_done);
8929 pop(tmp5);
8930 pop(tmp4);
8931 pop(tmp3);
8932 pop(tmp2);
8933 pop(tmp1);
8934 }
8935 #endif
8936
8937 /**
8938 * Emits code to update CRC-32 with a byte value according to constants in table
8939 *
8940 * @param [in,out]crc Register containing the crc.
8941 * @param [in]val Register containing the byte to fold into the CRC.
8942 * @param [in]table Register containing the table of crc constants.
8943 *
8944 * uint32_t crc;
8945 * val = crc_table[(val ^ crc) & 0xFF];
8946 * crc = val ^ (crc >> 8);
8947 *
8948 */
8949 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8950 xorl(val, crc);
8951 andl(val, 0xFF);
8952 shrl(crc, 8); // unsigned shift
8953 xorl(crc, Address(table, val, Address::times_4, 0));
8954 }
8955
8956 /**
8957 * Fold four 128-bit data chunks
8958 */
8959 void MacroAssembler::fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8960 evpclmulhdq(xtmp, xK, xcrc, Assembler::AVX_512bit); // [123:64]
8961 evpclmulldq(xcrc, xK, xcrc, Assembler::AVX_512bit); // [63:0]
8962 evpxorq(xcrc, xcrc, Address(buf, offset), Assembler::AVX_512bit /* vector_len */);
8963 evpxorq(xcrc, xcrc, xtmp, Assembler::AVX_512bit /* vector_len */);
8964 }
8965
8966 /**
8967 * Fold 128-bit data chunk
8968 */
8969 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8970 if (UseAVX > 0) {
8971 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8972 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8973 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8974 pxor(xcrc, xtmp);
8975 } else {
8976 movdqa(xtmp, xcrc);
8977 pclmulhdq(xtmp, xK); // [123:64]
8978 pclmulldq(xcrc, xK); // [63:0]
8979 pxor(xcrc, xtmp);
8980 movdqu(xtmp, Address(buf, offset));
8981 pxor(xcrc, xtmp);
8982 }
8983 }
8984
8985 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8986 if (UseAVX > 0) {
8987 vpclmulhdq(xtmp, xK, xcrc);
8988 vpclmulldq(xcrc, xK, xcrc);
8989 pxor(xcrc, xbuf);
8990 pxor(xcrc, xtmp);
8991 } else {
8992 movdqa(xtmp, xcrc);
8993 pclmulhdq(xtmp, xK);
8994 pclmulldq(xcrc, xK);
8995 pxor(xcrc, xbuf);
8996 pxor(xcrc, xtmp);
8997 }
8998 }
8999
9000 /**
9001 * 8-bit folds to compute 32-bit CRC
9002 *
9003 * uint64_t xcrc;
9004 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
9005 */
9006 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
9007 movdl(tmp, xcrc);
9008 andl(tmp, 0xFF);
9009 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
9010 psrldq(xcrc, 1); // unsigned shift one byte
9011 pxor(xcrc, xtmp);
9012 }
9013
9014 /**
9015 * uint32_t crc;
9016 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
9017 */
9018 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
9019 movl(tmp, crc);
9020 andl(tmp, 0xFF);
9021 shrl(crc, 8);
9022 xorl(crc, Address(table, tmp, Address::times_4, 0));
9023 }
9024
9025 /**
9026 * @param crc register containing existing CRC (32-bit)
9027 * @param buf register pointing to input byte buffer (byte*)
9028 * @param len register containing number of bytes
9029 * @param table register that will contain address of CRC table
9030 * @param tmp scratch register
9031 */
9032 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
9033 assert_different_registers(crc, buf, len, table, tmp, rax);
9034
9035 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
9036 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
9037
9038 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
9039 // context for the registers used, where all instructions below are using 128-bit mode
9040 // On EVEX without VL and BW, these instructions will all be AVX.
9041 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
9042 notl(crc); // ~crc
9043 cmpl(len, 16);
9044 jcc(Assembler::less, L_tail);
9045
9046 // Align buffer to 16 bytes
9047 movl(tmp, buf);
9048 andl(tmp, 0xF);
9049 jccb(Assembler::zero, L_aligned);
9050 subl(tmp, 16);
9051 addl(len, tmp);
9052
9053 align(4);
9054 BIND(L_align_loop);
9055 movsbl(rax, Address(buf, 0)); // load byte with sign extension
9056 update_byte_crc32(crc, rax, table);
9057 increment(buf);
9058 incrementl(tmp);
9059 jccb(Assembler::less, L_align_loop);
9060
9061 BIND(L_aligned);
9062 movl(tmp, len); // save
9063 shrl(len, 4);
9064 jcc(Assembler::zero, L_tail_restore);
9065
9066 // Fold crc into first bytes of vector
9067 movdqa(xmm1, Address(buf, 0));
9068 movdl(rax, xmm1);
9069 xorl(crc, rax);
9070 if (VM_Version::supports_sse4_1()) {
9071 pinsrd(xmm1, crc, 0);
9072 } else {
9073 pinsrw(xmm1, crc, 0);
9074 shrl(crc, 16);
9075 pinsrw(xmm1, crc, 1);
9076 }
9077 addptr(buf, 16);
9078 subl(len, 4); // len > 0
9079 jcc(Assembler::less, L_fold_tail);
9080
9081 movdqa(xmm2, Address(buf, 0));
9082 movdqa(xmm3, Address(buf, 16));
9083 movdqa(xmm4, Address(buf, 32));
9084 addptr(buf, 48);
9085 subl(len, 3);
9086 jcc(Assembler::lessEqual, L_fold_512b);
9087
9088 // Fold total 512 bits of polynomial on each iteration,
9089 // 128 bits per each of 4 parallel streams.
9090 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
9091
9092 align(32);
9093 BIND(L_fold_512b_loop);
9094 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
9095 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
9096 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
9097 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
9098 addptr(buf, 64);
9099 subl(len, 4);
9100 jcc(Assembler::greater, L_fold_512b_loop);
9101
9102 // Fold 512 bits to 128 bits.
9103 BIND(L_fold_512b);
9104 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
9105 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
9106 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
9107 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
9108
9109 // Fold the rest of 128 bits data chunks
9110 BIND(L_fold_tail);
9111 addl(len, 3);
9112 jccb(Assembler::lessEqual, L_fold_128b);
9113 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
9114
9115 BIND(L_fold_tail_loop);
9116 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
9117 addptr(buf, 16);
9118 decrementl(len);
9119 jccb(Assembler::greater, L_fold_tail_loop);
9120
9121 // Fold 128 bits in xmm1 down into 32 bits in crc register.
9122 BIND(L_fold_128b);
9123 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
9124 if (UseAVX > 0) {
9125 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
9126 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
9127 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
9128 } else {
9129 movdqa(xmm2, xmm0);
9130 pclmulqdq(xmm2, xmm1, 0x1);
9131 movdqa(xmm3, xmm0);
9132 pand(xmm3, xmm2);
9133 pclmulqdq(xmm0, xmm3, 0x1);
9134 }
9135 psrldq(xmm1, 8);
9136 psrldq(xmm2, 4);
9137 pxor(xmm0, xmm1);
9138 pxor(xmm0, xmm2);
9139
9140 // 8 8-bit folds to compute 32-bit CRC.
9141 for (int j = 0; j < 4; j++) {
9142 fold_8bit_crc32(xmm0, table, xmm1, rax);
9143 }
9144 movdl(crc, xmm0); // mov 32 bits to general register
9145 for (int j = 0; j < 4; j++) {
9146 fold_8bit_crc32(crc, table, rax);
9147 }
9148
9149 BIND(L_tail_restore);
9150 movl(len, tmp); // restore
9151 BIND(L_tail);
9152 andl(len, 0xf);
9153 jccb(Assembler::zero, L_exit);
9154
9155 // Fold the rest of bytes
9156 align(4);
9157 BIND(L_tail_loop);
9158 movsbl(rax, Address(buf, 0)); // load byte with sign extension
9159 update_byte_crc32(crc, rax, table);
9160 increment(buf);
9161 decrementl(len);
9162 jccb(Assembler::greater, L_tail_loop);
9163
9164 BIND(L_exit);
9165 notl(crc); // ~c
9166 }
9167
9168 #ifdef _LP64
9169 // S. Gueron / Information Processing Letters 112 (2012) 184
9170 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
9171 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
9172 // Output: the 64-bit carry-less product of B * CONST
9173 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
9174 Register tmp1, Register tmp2, Register tmp3) {
9175 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9176 if (n > 0) {
9177 addq(tmp3, n * 256 * 8);
9178 }
9179 // Q1 = TABLEExt[n][B & 0xFF];
9180 movl(tmp1, in);
9181 andl(tmp1, 0x000000FF);
9182 shll(tmp1, 3);
9183 addq(tmp1, tmp3);
9184 movq(tmp1, Address(tmp1, 0));
9185
9186 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9187 movl(tmp2, in);
9188 shrl(tmp2, 8);
9189 andl(tmp2, 0x000000FF);
9190 shll(tmp2, 3);
9191 addq(tmp2, tmp3);
9192 movq(tmp2, Address(tmp2, 0));
9193
9194 shlq(tmp2, 8);
9195 xorq(tmp1, tmp2);
9196
9197 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9198 movl(tmp2, in);
9199 shrl(tmp2, 16);
9200 andl(tmp2, 0x000000FF);
9201 shll(tmp2, 3);
9202 addq(tmp2, tmp3);
9203 movq(tmp2, Address(tmp2, 0));
9204
9205 shlq(tmp2, 16);
9206 xorq(tmp1, tmp2);
9207
9208 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9209 shrl(in, 24);
9210 andl(in, 0x000000FF);
9211 shll(in, 3);
9212 addq(in, tmp3);
9213 movq(in, Address(in, 0));
9214
9215 shlq(in, 24);
9216 xorq(in, tmp1);
9217 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9218 }
9219
9220 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9221 Register in_out,
9222 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9223 XMMRegister w_xtmp2,
9224 Register tmp1,
9225 Register n_tmp2, Register n_tmp3) {
9226 if (is_pclmulqdq_supported) {
9227 movdl(w_xtmp1, in_out); // modified blindly
9228
9229 movl(tmp1, const_or_pre_comp_const_index);
9230 movdl(w_xtmp2, tmp1);
9231 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9232
9233 movdq(in_out, w_xtmp1);
9234 } else {
9235 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
9236 }
9237 }
9238
9239 // Recombination Alternative 2: No bit-reflections
9240 // T1 = (CRC_A * U1) << 1
9241 // T2 = (CRC_B * U2) << 1
9242 // C1 = T1 >> 32
9243 // C2 = T2 >> 32
9244 // T1 = T1 & 0xFFFFFFFF
9245 // T2 = T2 & 0xFFFFFFFF
9246 // T1 = CRC32(0, T1)
9247 // T2 = CRC32(0, T2)
9248 // C1 = C1 ^ T1
9249 // C2 = C2 ^ T2
9250 // CRC = C1 ^ C2 ^ CRC_C
9251 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9252 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9253 Register tmp1, Register tmp2,
9254 Register n_tmp3) {
9255 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9256 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9257 shlq(in_out, 1);
9258 movl(tmp1, in_out);
9259 shrq(in_out, 32);
9260 xorl(tmp2, tmp2);
9261 crc32(tmp2, tmp1, 4);
9262 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
9263 shlq(in1, 1);
9264 movl(tmp1, in1);
9265 shrq(in1, 32);
9266 xorl(tmp2, tmp2);
9267 crc32(tmp2, tmp1, 4);
9268 xorl(in1, tmp2);
9269 xorl(in_out, in1);
9270 xorl(in_out, in2);
9271 }
9272
9273 // Set N to predefined value
9274 // Subtract from a lenght of a buffer
9275 // execute in a loop:
9276 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
9277 // for i = 1 to N do
9278 // CRC_A = CRC32(CRC_A, A[i])
9279 // CRC_B = CRC32(CRC_B, B[i])
9280 // CRC_C = CRC32(CRC_C, C[i])
9281 // end for
9282 // Recombine
9283 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9284 Register in_out1, Register in_out2, Register in_out3,
9285 Register tmp1, Register tmp2, Register tmp3,
9286 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9287 Register tmp4, Register tmp5,
9288 Register n_tmp6) {
9289 Label L_processPartitions;
9290 Label L_processPartition;
9291 Label L_exit;
9292
9293 bind(L_processPartitions);
9294 cmpl(in_out1, 3 * size);
9295 jcc(Assembler::less, L_exit);
9296 xorl(tmp1, tmp1);
9297 xorl(tmp2, tmp2);
9298 movq(tmp3, in_out2);
9299 addq(tmp3, size);
9300
9301 bind(L_processPartition);
9302 crc32(in_out3, Address(in_out2, 0), 8);
9303 crc32(tmp1, Address(in_out2, size), 8);
9304 crc32(tmp2, Address(in_out2, size * 2), 8);
9305 addq(in_out2, 8);
9306 cmpq(in_out2, tmp3);
9307 jcc(Assembler::less, L_processPartition);
9308 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9309 w_xtmp1, w_xtmp2, w_xtmp3,
9310 tmp4, tmp5,
9311 n_tmp6);
9312 addq(in_out2, 2 * size);
9313 subl(in_out1, 3 * size);
9314 jmp(L_processPartitions);
9315
9316 bind(L_exit);
9317 }
9318 #else
9319 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
9320 Register tmp1, Register tmp2, Register tmp3,
9321 XMMRegister xtmp1, XMMRegister xtmp2) {
9322 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9323 if (n > 0) {
9324 addl(tmp3, n * 256 * 8);
9325 }
9326 // Q1 = TABLEExt[n][B & 0xFF];
9327 movl(tmp1, in_out);
9328 andl(tmp1, 0x000000FF);
9329 shll(tmp1, 3);
9330 addl(tmp1, tmp3);
9331 movq(xtmp1, Address(tmp1, 0));
9332
9333 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9334 movl(tmp2, in_out);
9335 shrl(tmp2, 8);
9336 andl(tmp2, 0x000000FF);
9337 shll(tmp2, 3);
9338 addl(tmp2, tmp3);
9339 movq(xtmp2, Address(tmp2, 0));
9340
9341 psllq(xtmp2, 8);
9342 pxor(xtmp1, xtmp2);
9343
9344 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9345 movl(tmp2, in_out);
9346 shrl(tmp2, 16);
9347 andl(tmp2, 0x000000FF);
9348 shll(tmp2, 3);
9349 addl(tmp2, tmp3);
9350 movq(xtmp2, Address(tmp2, 0));
9351
9352 psllq(xtmp2, 16);
9353 pxor(xtmp1, xtmp2);
9354
9355 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9356 shrl(in_out, 24);
9357 andl(in_out, 0x000000FF);
9358 shll(in_out, 3);
9359 addl(in_out, tmp3);
9360 movq(xtmp2, Address(in_out, 0));
9361
9362 psllq(xtmp2, 24);
9363 pxor(xtmp1, xtmp2); // Result in CXMM
9364 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9365 }
9366
9367 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9368 Register in_out,
9369 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9370 XMMRegister w_xtmp2,
9371 Register tmp1,
9372 Register n_tmp2, Register n_tmp3) {
9373 if (is_pclmulqdq_supported) {
9374 movdl(w_xtmp1, in_out);
9375
9376 movl(tmp1, const_or_pre_comp_const_index);
9377 movdl(w_xtmp2, tmp1);
9378 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9379 // Keep result in XMM since GPR is 32 bit in length
9380 } else {
9381 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
9382 }
9383 }
9384
9385 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9386 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9387 Register tmp1, Register tmp2,
9388 Register n_tmp3) {
9389 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9390 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9391
9392 psllq(w_xtmp1, 1);
9393 movdl(tmp1, w_xtmp1);
9394 psrlq(w_xtmp1, 32);
9395 movdl(in_out, w_xtmp1);
9396
9397 xorl(tmp2, tmp2);
9398 crc32(tmp2, tmp1, 4);
9399 xorl(in_out, tmp2);
9400
9401 psllq(w_xtmp2, 1);
9402 movdl(tmp1, w_xtmp2);
9403 psrlq(w_xtmp2, 32);
9404 movdl(in1, w_xtmp2);
9405
9406 xorl(tmp2, tmp2);
9407 crc32(tmp2, tmp1, 4);
9408 xorl(in1, tmp2);
9409 xorl(in_out, in1);
9410 xorl(in_out, in2);
9411 }
9412
9413 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9414 Register in_out1, Register in_out2, Register in_out3,
9415 Register tmp1, Register tmp2, Register tmp3,
9416 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9417 Register tmp4, Register tmp5,
9418 Register n_tmp6) {
9419 Label L_processPartitions;
9420 Label L_processPartition;
9421 Label L_exit;
9422
9423 bind(L_processPartitions);
9424 cmpl(in_out1, 3 * size);
9425 jcc(Assembler::less, L_exit);
9426 xorl(tmp1, tmp1);
9427 xorl(tmp2, tmp2);
9428 movl(tmp3, in_out2);
9429 addl(tmp3, size);
9430
9431 bind(L_processPartition);
9432 crc32(in_out3, Address(in_out2, 0), 4);
9433 crc32(tmp1, Address(in_out2, size), 4);
9434 crc32(tmp2, Address(in_out2, size*2), 4);
9435 crc32(in_out3, Address(in_out2, 0+4), 4);
9436 crc32(tmp1, Address(in_out2, size+4), 4);
9437 crc32(tmp2, Address(in_out2, size*2+4), 4);
9438 addl(in_out2, 8);
9439 cmpl(in_out2, tmp3);
9440 jcc(Assembler::less, L_processPartition);
9441
9442 push(tmp3);
9443 push(in_out1);
9444 push(in_out2);
9445 tmp4 = tmp3;
9446 tmp5 = in_out1;
9447 n_tmp6 = in_out2;
9448
9449 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9450 w_xtmp1, w_xtmp2, w_xtmp3,
9451 tmp4, tmp5,
9452 n_tmp6);
9453
9454 pop(in_out2);
9455 pop(in_out1);
9456 pop(tmp3);
9457
9458 addl(in_out2, 2 * size);
9459 subl(in_out1, 3 * size);
9460 jmp(L_processPartitions);
9461
9462 bind(L_exit);
9463 }
9464 #endif //LP64
9465
9466 #ifdef _LP64
9467 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9468 // Input: A buffer I of L bytes.
9469 // Output: the CRC32C value of the buffer.
9470 // Notations:
9471 // Write L = 24N + r, with N = floor (L/24).
9472 // r = L mod 24 (0 <= r < 24).
9473 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9474 // N quadwords, and R consists of r bytes.
9475 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9476 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9477 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9478 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9479 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9480 Register tmp1, Register tmp2, Register tmp3,
9481 Register tmp4, Register tmp5, Register tmp6,
9482 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9483 bool is_pclmulqdq_supported) {
9484 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9485 Label L_wordByWord;
9486 Label L_byteByByteProlog;
9487 Label L_byteByByte;
9488 Label L_exit;
9489
9490 if (is_pclmulqdq_supported ) {
9491 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9492 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
9493
9494 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9495 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9496
9497 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9498 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9499 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9500 } else {
9501 const_or_pre_comp_const_index[0] = 1;
9502 const_or_pre_comp_const_index[1] = 0;
9503
9504 const_or_pre_comp_const_index[2] = 3;
9505 const_or_pre_comp_const_index[3] = 2;
9506
9507 const_or_pre_comp_const_index[4] = 5;
9508 const_or_pre_comp_const_index[5] = 4;
9509 }
9510 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9511 in2, in1, in_out,
9512 tmp1, tmp2, tmp3,
9513 w_xtmp1, w_xtmp2, w_xtmp3,
9514 tmp4, tmp5,
9515 tmp6);
9516 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9517 in2, in1, in_out,
9518 tmp1, tmp2, tmp3,
9519 w_xtmp1, w_xtmp2, w_xtmp3,
9520 tmp4, tmp5,
9521 tmp6);
9522 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9523 in2, in1, in_out,
9524 tmp1, tmp2, tmp3,
9525 w_xtmp1, w_xtmp2, w_xtmp3,
9526 tmp4, tmp5,
9527 tmp6);
9528 movl(tmp1, in2);
9529 andl(tmp1, 0x00000007);
9530 negl(tmp1);
9531 addl(tmp1, in2);
9532 addq(tmp1, in1);
9533
9534 BIND(L_wordByWord);
9535 cmpq(in1, tmp1);
9536 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9537 crc32(in_out, Address(in1, 0), 4);
9538 addq(in1, 4);
9539 jmp(L_wordByWord);
9540
9541 BIND(L_byteByByteProlog);
9542 andl(in2, 0x00000007);
9543 movl(tmp2, 1);
9544
9545 BIND(L_byteByByte);
9546 cmpl(tmp2, in2);
9547 jccb(Assembler::greater, L_exit);
9548 crc32(in_out, Address(in1, 0), 1);
9549 incq(in1);
9550 incl(tmp2);
9551 jmp(L_byteByByte);
9552
9553 BIND(L_exit);
9554 }
9555 #else
9556 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9557 Register tmp1, Register tmp2, Register tmp3,
9558 Register tmp4, Register tmp5, Register tmp6,
9559 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9560 bool is_pclmulqdq_supported) {
9561 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9562 Label L_wordByWord;
9563 Label L_byteByByteProlog;
9564 Label L_byteByByte;
9565 Label L_exit;
9566
9567 if (is_pclmulqdq_supported) {
9568 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9569 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
9570
9571 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9572 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9573
9574 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9575 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9576 } else {
9577 const_or_pre_comp_const_index[0] = 1;
9578 const_or_pre_comp_const_index[1] = 0;
9579
9580 const_or_pre_comp_const_index[2] = 3;
9581 const_or_pre_comp_const_index[3] = 2;
9582
9583 const_or_pre_comp_const_index[4] = 5;
9584 const_or_pre_comp_const_index[5] = 4;
9585 }
9586 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9587 in2, in1, in_out,
9588 tmp1, tmp2, tmp3,
9589 w_xtmp1, w_xtmp2, w_xtmp3,
9590 tmp4, tmp5,
9591 tmp6);
9592 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9593 in2, in1, in_out,
9594 tmp1, tmp2, tmp3,
9595 w_xtmp1, w_xtmp2, w_xtmp3,
9596 tmp4, tmp5,
9597 tmp6);
9598 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9599 in2, in1, in_out,
9600 tmp1, tmp2, tmp3,
9601 w_xtmp1, w_xtmp2, w_xtmp3,
9602 tmp4, tmp5,
9603 tmp6);
9604 movl(tmp1, in2);
9605 andl(tmp1, 0x00000007);
9606 negl(tmp1);
9607 addl(tmp1, in2);
9608 addl(tmp1, in1);
9609
9610 BIND(L_wordByWord);
9611 cmpl(in1, tmp1);
9612 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9613 crc32(in_out, Address(in1,0), 4);
9614 addl(in1, 4);
9615 jmp(L_wordByWord);
9616
9617 BIND(L_byteByByteProlog);
9618 andl(in2, 0x00000007);
9619 movl(tmp2, 1);
9620
9621 BIND(L_byteByByte);
9622 cmpl(tmp2, in2);
9623 jccb(Assembler::greater, L_exit);
9624 movb(tmp1, Address(in1, 0));
9625 crc32(in_out, tmp1, 1);
9626 incl(in1);
9627 incl(tmp2);
9628 jmp(L_byteByByte);
9629
9630 BIND(L_exit);
9631 }
9632 #endif // LP64
9633 #undef BIND
9634 #undef BLOCK_COMMENT
9635
9636 // Compress char[] array to byte[].
9637 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
9638 // @HotSpotIntrinsicCandidate
9639 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9640 // for (int i = 0; i < len; i++) {
9641 // int c = src[srcOff++];
9642 // if (c >>> 8 != 0) {
9643 // return 0;
9644 // }
9645 // dst[dstOff++] = (byte)c;
9646 // }
9647 // return len;
9648 // }
9649 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9650 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9651 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9652 Register tmp5, Register result) {
9653 Label copy_chars_loop, return_length, return_zero, done;
9654
9655 // rsi: src
9656 // rdi: dst
9657 // rdx: len
9658 // rcx: tmp5
9659 // rax: result
9660
9661 // rsi holds start addr of source char[] to be compressed
9662 // rdi holds start addr of destination byte[]
9663 // rdx holds length
9664
9665 assert(len != result, "");
9666
9667 // save length for return
9668 push(len);
9669
9670 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9671 VM_Version::supports_avx512vlbw() &&
9672 VM_Version::supports_bmi2()) {
9673
9674 Label copy_32_loop, copy_loop_tail, below_threshold;
9675
9676 // alignment
9677 Label post_alignment;
9678
9679 // if length of the string is less than 16, handle it in an old fashioned way
9680 testl(len, -32);
9681 jcc(Assembler::zero, below_threshold);
9682
9683 // First check whether a character is compressable ( <= 0xFF).
9684 // Create mask to test for Unicode chars inside zmm vector
9685 movl(result, 0x00FF);
9686 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
9687
9688 testl(len, -64);
9689 jcc(Assembler::zero, post_alignment);
9690
9691 movl(tmp5, dst);
9692 andl(tmp5, (32 - 1));
9693 negl(tmp5);
9694 andl(tmp5, (32 - 1));
9695
9696 // bail out when there is nothing to be done
9697 testl(tmp5, 0xFFFFFFFF);
9698 jcc(Assembler::zero, post_alignment);
9699
9700 // ~(~0 << len), where len is the # of remaining elements to process
9701 movl(result, 0xFFFFFFFF);
9702 shlxl(result, result, tmp5);
9703 notl(result);
9704 kmovdl(k3, result);
9705
9706 evmovdquw(tmp1Reg, k3, Address(src, 0), Assembler::AVX_512bit);
9707 evpcmpuw(k2, k3, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9708 ktestd(k2, k3);
9709 jcc(Assembler::carryClear, return_zero);
9710
9711 evpmovwb(Address(dst, 0), k3, tmp1Reg, Assembler::AVX_512bit);
9712
9713 addptr(src, tmp5);
9714 addptr(src, tmp5);
9715 addptr(dst, tmp5);
9716 subl(len, tmp5);
9717
9718 bind(post_alignment);
9719 // end of alignment
9720
9721 movl(tmp5, len);
9722 andl(tmp5, (32 - 1)); // tail count (in chars)
9723 andl(len, ~(32 - 1)); // vector count (in chars)
9724 jcc(Assembler::zero, copy_loop_tail);
9725
9726 lea(src, Address(src, len, Address::times_2));
9727 lea(dst, Address(dst, len, Address::times_1));
9728 negptr(len);
9729
9730 bind(copy_32_loop);
9731 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9732 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9733 kortestdl(k2, k2);
9734 jcc(Assembler::carryClear, return_zero);
9735
9736 // All elements in current processed chunk are valid candidates for
9737 // compression. Write a truncated byte elements to the memory.
9738 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9739 addptr(len, 32);
9740 jcc(Assembler::notZero, copy_32_loop);
9741
9742 bind(copy_loop_tail);
9743 // bail out when there is nothing to be done
9744 testl(tmp5, 0xFFFFFFFF);
9745 jcc(Assembler::zero, return_length);
9746
9747 movl(len, tmp5);
9748
9749 // ~(~0 << len), where len is the # of remaining elements to process
9750 movl(result, 0xFFFFFFFF);
9751 shlxl(result, result, len);
9752 notl(result);
9753
9754 kmovdl(k3, result);
9755
9756 evmovdquw(tmp1Reg, k3, Address(src, 0), Assembler::AVX_512bit);
9757 evpcmpuw(k2, k3, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9758 ktestd(k2, k3);
9759 jcc(Assembler::carryClear, return_zero);
9760
9761 evpmovwb(Address(dst, 0), k3, tmp1Reg, Assembler::AVX_512bit);
9762 jmp(return_length);
9763
9764 bind(below_threshold);
9765 }
9766
9767 if (UseSSE42Intrinsics) {
9768 Label copy_32_loop, copy_16, copy_tail;
9769
9770 movl(result, len);
9771
9772 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9773
9774 // vectored compression
9775 andl(len, 0xfffffff0); // vector count (in chars)
9776 andl(result, 0x0000000f); // tail count (in chars)
9777 testl(len, len);
9778 jcc(Assembler::zero, copy_16);
9779
9780 // compress 16 chars per iter
9781 movdl(tmp1Reg, tmp5);
9782 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9783 pxor(tmp4Reg, tmp4Reg);
9784
9785 lea(src, Address(src, len, Address::times_2));
9786 lea(dst, Address(dst, len, Address::times_1));
9787 negptr(len);
9788
9789 bind(copy_32_loop);
9790 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9791 por(tmp4Reg, tmp2Reg);
9792 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9793 por(tmp4Reg, tmp3Reg);
9794 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9795 jcc(Assembler::notZero, return_zero);
9796 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9797 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9798 addptr(len, 16);
9799 jcc(Assembler::notZero, copy_32_loop);
9800
9801 // compress next vector of 8 chars (if any)
9802 bind(copy_16);
9803 movl(len, result);
9804 andl(len, 0xfffffff8); // vector count (in chars)
9805 andl(result, 0x00000007); // tail count (in chars)
9806 testl(len, len);
9807 jccb(Assembler::zero, copy_tail);
9808
9809 movdl(tmp1Reg, tmp5);
9810 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9811 pxor(tmp3Reg, tmp3Reg);
9812
9813 movdqu(tmp2Reg, Address(src, 0));
9814 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9815 jccb(Assembler::notZero, return_zero);
9816 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9817 movq(Address(dst, 0), tmp2Reg);
9818 addptr(src, 16);
9819 addptr(dst, 8);
9820
9821 bind(copy_tail);
9822 movl(len, result);
9823 }
9824 // compress 1 char per iter
9825 testl(len, len);
9826 jccb(Assembler::zero, return_length);
9827 lea(src, Address(src, len, Address::times_2));
9828 lea(dst, Address(dst, len, Address::times_1));
9829 negptr(len);
9830
9831 bind(copy_chars_loop);
9832 load_unsigned_short(result, Address(src, len, Address::times_2));
9833 testl(result, 0xff00); // check if Unicode char
9834 jccb(Assembler::notZero, return_zero);
9835 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
9836 increment(len);
9837 jcc(Assembler::notZero, copy_chars_loop);
9838
9839 // if compression succeeded, return length
9840 bind(return_length);
9841 pop(result);
9842 jmpb(done);
9843
9844 // if compression failed, return 0
9845 bind(return_zero);
9846 xorl(result, result);
9847 addptr(rsp, wordSize);
9848
9849 bind(done);
9850 }
9851
9852 // Inflate byte[] array to char[].
9853 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9854 // @HotSpotIntrinsicCandidate
9855 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9856 // for (int i = 0; i < len; i++) {
9857 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9858 // }
9859 // }
9860 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9861 XMMRegister tmp1, Register tmp2) {
9862 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9863 // rsi: src
9864 // rdi: dst
9865 // rdx: len
9866 // rcx: tmp2
9867
9868 // rsi holds start addr of source byte[] to be inflated
9869 // rdi holds start addr of destination char[]
9870 // rdx holds length
9871 assert_different_registers(src, dst, len, tmp2);
9872 movl(tmp2, len);
9873 if ((UseAVX > 2) && // AVX512
9874 VM_Version::supports_avx512vlbw() &&
9875 VM_Version::supports_bmi2()) {
9876
9877 Label copy_32_loop, copy_tail;
9878 Register tmp3_aliased = len;
9879
9880 // if length of the string is less than 16, handle it in an old fashioned way
9881 testl(len, -16);
9882 jcc(Assembler::zero, below_threshold);
9883
9884 testl(len, -1 * AVX3Threshold);
9885 jcc(Assembler::zero, avx3_threshold);
9886
9887 // In order to use only one arithmetic operation for the main loop we use
9888 // this pre-calculation
9889 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9890 andl(len, -32); // vector count
9891 jccb(Assembler::zero, copy_tail);
9892
9893 lea(src, Address(src, len, Address::times_1));
9894 lea(dst, Address(dst, len, Address::times_2));
9895 negptr(len);
9896
9897
9898 // inflate 32 chars per iter
9899 bind(copy_32_loop);
9900 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9901 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9902 addptr(len, 32);
9903 jcc(Assembler::notZero, copy_32_loop);
9904
9905 bind(copy_tail);
9906 // bail out when there is nothing to be done
9907 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9908 jcc(Assembler::zero, done);
9909
9910 // ~(~0 << length), where length is the # of remaining elements to process
9911 movl(tmp3_aliased, -1);
9912 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9913 notl(tmp3_aliased);
9914 kmovdl(k2, tmp3_aliased);
9915 evpmovzxbw(tmp1, k2, Address(src, 0), Assembler::AVX_512bit);
9916 evmovdquw(Address(dst, 0), k2, tmp1, Assembler::AVX_512bit);
9917
9918 jmp(done);
9919 bind(avx3_threshold);
9920 }
9921 if (UseSSE42Intrinsics) {
9922 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9923
9924 if (UseAVX > 1) {
9925 andl(tmp2, (16 - 1));
9926 andl(len, -16);
9927 jccb(Assembler::zero, copy_new_tail);
9928 } else {
9929 andl(tmp2, 0x00000007); // tail count (in chars)
9930 andl(len, 0xfffffff8); // vector count (in chars)
9931 jccb(Assembler::zero, copy_tail);
9932 }
9933
9934 // vectored inflation
9935 lea(src, Address(src, len, Address::times_1));
9936 lea(dst, Address(dst, len, Address::times_2));
9937 negptr(len);
9938
9939 if (UseAVX > 1) {
9940 bind(copy_16_loop);
9941 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9942 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9943 addptr(len, 16);
9944 jcc(Assembler::notZero, copy_16_loop);
9945
9946 bind(below_threshold);
9947 bind(copy_new_tail);
9948 movl(len, tmp2);
9949 andl(tmp2, 0x00000007);
9950 andl(len, 0xFFFFFFF8);
9951 jccb(Assembler::zero, copy_tail);
9952
9953 pmovzxbw(tmp1, Address(src, 0));
9954 movdqu(Address(dst, 0), tmp1);
9955 addptr(src, 8);
9956 addptr(dst, 2 * 8);
9957
9958 jmp(copy_tail, true);
9959 }
9960
9961 // inflate 8 chars per iter
9962 bind(copy_8_loop);
9963 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9964 movdqu(Address(dst, len, Address::times_2), tmp1);
9965 addptr(len, 8);
9966 jcc(Assembler::notZero, copy_8_loop);
9967
9968 bind(copy_tail);
9969 movl(len, tmp2);
9970
9971 cmpl(len, 4);
9972 jccb(Assembler::less, copy_bytes);
9973
9974 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9975 pmovzxbw(tmp1, tmp1);
9976 movq(Address(dst, 0), tmp1);
9977 subptr(len, 4);
9978 addptr(src, 4);
9979 addptr(dst, 8);
9980
9981 bind(copy_bytes);
9982 } else {
9983 bind(below_threshold);
9984 }
9985
9986 testl(len, len);
9987 jccb(Assembler::zero, done);
9988 lea(src, Address(src, len, Address::times_1));
9989 lea(dst, Address(dst, len, Address::times_2));
9990 negptr(len);
9991
9992 // inflate 1 char per iter
9993 bind(copy_chars_loop);
9994 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9995 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9996 increment(len);
9997 jcc(Assembler::notZero, copy_chars_loop);
9998
9999 bind(done);
10000 }
10001
10002 #ifdef _LP64
10003 void MacroAssembler::cache_wb(Address line)
10004 {
10005 // 64 bit cpus always support clflush
10006 assert(VM_Version::supports_clflush(), "clflush should be available");
10007 bool optimized = VM_Version::supports_clflushopt();
10008 bool no_evict = VM_Version::supports_clwb();
10009
10010 // prefer clwb (writeback without evict) otherwise
10011 // prefer clflushopt (potentially parallel writeback with evict)
10012 // otherwise fallback on clflush (serial writeback with evict)
10013
10014 if (optimized) {
10015 if (no_evict) {
10016 clwb(line);
10017 } else {
10018 clflushopt(line);
10019 }
10020 } else {
10021 // no need for fence when using CLFLUSH
10022 clflush(line);
10023 }
10024 }
10025
10026 void MacroAssembler::cache_wbsync(bool is_pre)
10027 {
10028 assert(VM_Version::supports_clflush(), "clflush should be available");
10029 bool optimized = VM_Version::supports_clflushopt();
10030 bool no_evict = VM_Version::supports_clwb();
10031
10032 // pick the correct implementation
10033
10034 if (!is_pre && (optimized || no_evict)) {
10035 // need an sfence for post flush when using clflushopt or clwb
10036 // otherwise no no need for any synchroniaztion
10037
10038 sfence();
10039 }
10040 }
10041 #endif // _LP64
10042
10043 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10044 switch (cond) {
10045 // Note some conditions are synonyms for others
10046 case Assembler::zero: return Assembler::notZero;
10047 case Assembler::notZero: return Assembler::zero;
10048 case Assembler::less: return Assembler::greaterEqual;
10049 case Assembler::lessEqual: return Assembler::greater;
10050 case Assembler::greater: return Assembler::lessEqual;
10051 case Assembler::greaterEqual: return Assembler::less;
10052 case Assembler::below: return Assembler::aboveEqual;
10053 case Assembler::belowEqual: return Assembler::above;
10054 case Assembler::above: return Assembler::belowEqual;
10055 case Assembler::aboveEqual: return Assembler::below;
10056 case Assembler::overflow: return Assembler::noOverflow;
10057 case Assembler::noOverflow: return Assembler::overflow;
10058 case Assembler::negative: return Assembler::positive;
10059 case Assembler::positive: return Assembler::negative;
10060 case Assembler::parity: return Assembler::noParity;
10061 case Assembler::noParity: return Assembler::parity;
10062 }
10063 ShouldNotReachHere(); return Assembler::overflow;
10064 }
10065
10066 SkipIfEqual::SkipIfEqual(
10067 MacroAssembler* masm, const bool* flag_addr, bool value) {
10068 _masm = masm;
10069 _masm->cmp8(ExternalAddress((address)flag_addr), value);
10070 _masm->jcc(Assembler::equal, _label);
10071 }
10072
10073 SkipIfEqual::~SkipIfEqual() {
10074 _masm->bind(_label);
10075 }
10076
10077 // 32-bit Windows has its own fast-path implementation
10078 // of get_thread
10079 #if !defined(WIN32) || defined(_LP64)
10080
10081 // This is simply a call to Thread::current()
10082 void MacroAssembler::get_thread(Register thread) {
10083 if (thread != rax) {
10084 push(rax);
10085 }
10086 LP64_ONLY(push(rdi);)
10087 LP64_ONLY(push(rsi);)
10088 push(rdx);
10089 push(rcx);
10090 #ifdef _LP64
10091 push(r8);
10092 push(r9);
10093 push(r10);
10094 push(r11);
10095 #endif
10096
10097 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10098
10099 #ifdef _LP64
10100 pop(r11);
10101 pop(r10);
10102 pop(r9);
10103 pop(r8);
10104 #endif
10105 pop(rcx);
10106 pop(rdx);
10107 LP64_ONLY(pop(rsi);)
10108 LP64_ONLY(pop(rdi);)
10109 if (thread != rax) {
10110 mov(thread, rax);
10111 pop(rax);
10112 }
10113 }
10114
10115 #endif