21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_GLOBALDEFINITIONS_X86_HPP
26 #define CPU_X86_GLOBALDEFINITIONS_X86_HPP
27
28 const int StackAlignmentInBytes = 16;
29
30 // Indicates whether the C calling conventions require that
31 // 32-bit integer argument values are extended to 64 bits.
32 const bool CCallingConventionRequiresIntsAsLongs = false;
33
34 #define SUPPORTS_NATIVE_CX8
35
36 // The expected size in bytes of a cache line, used to pad data structures.
37 #if defined(TIERED)
38 #ifdef _LP64
39 // tiered, 64-bit, large machine
40 #define DEFAULT_CACHE_LINE_SIZE 128
41 #else
42 // tiered, 32-bit, medium machine
43 #define DEFAULT_CACHE_LINE_SIZE 64
44 #endif
45 #elif defined(COMPILER1)
46 // pure C1, 32-bit, small machine
47 // i486 was the last Intel chip with 16-byte cache line size
48 #define DEFAULT_CACHE_LINE_SIZE 32
49 #elif defined(COMPILER2)
50 #ifdef _LP64
51 // pure C2, 64-bit, large machine
52 #define DEFAULT_CACHE_LINE_SIZE 128
53 #else
54 // pure C2, 32-bit, medium machine
55 #define DEFAULT_CACHE_LINE_SIZE 64
56 #endif
57 #endif
58
59 #if defined(COMPILER2)
60 // Include Restricted Transactional Memory lock eliding optimization
61 #define INCLUDE_RTM_OPT 1
62 #endif
63
64 #if defined(LINUX) || defined(SOLARIS) || defined(__APPLE__)
65 #define SUPPORT_RESERVED_STACK_AREA
66 #endif
67
68 #define THREAD_LOCAL_POLL
69
70 #endif // CPU_X86_GLOBALDEFINITIONS_X86_HPP
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21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_GLOBALDEFINITIONS_X86_HPP
26 #define CPU_X86_GLOBALDEFINITIONS_X86_HPP
27
28 const int StackAlignmentInBytes = 16;
29
30 // Indicates whether the C calling conventions require that
31 // 32-bit integer argument values are extended to 64 bits.
32 const bool CCallingConventionRequiresIntsAsLongs = false;
33
34 #define SUPPORTS_NATIVE_CX8
35
36 // The expected size in bytes of a cache line, used to pad data structures.
37 #if defined(TIERED)
38 #ifdef _LP64
39 // tiered, 64-bit, large machine
40 #define DEFAULT_CACHE_LINE_SIZE 128
41 #define OM_CACHE_LINE_SIZE 64
42 #else
43 // tiered, 32-bit, medium machine
44 #define DEFAULT_CACHE_LINE_SIZE 64
45 #endif
46 #elif defined(COMPILER1)
47 // pure C1, 32-bit, small machine
48 // i486 was the last Intel chip with 16-byte cache line size
49 #define DEFAULT_CACHE_LINE_SIZE 32
50 #elif defined(COMPILER2)
51 #ifdef _LP64
52 // pure C2, 64-bit, large machine
53 #define DEFAULT_CACHE_LINE_SIZE 128
54 #define OM_CACHE_LINE_SIZE 64
55 #else
56 // pure C2, 32-bit, medium machine
57 #define DEFAULT_CACHE_LINE_SIZE 64
58 #endif
59 #endif
60
61 #if defined(COMPILER2)
62 // Include Restricted Transactional Memory lock eliding optimization
63 #define INCLUDE_RTM_OPT 1
64 #endif
65
66 #if defined(LINUX) || defined(SOLARIS) || defined(__APPLE__)
67 #define SUPPORT_RESERVED_STACK_AREA
68 #endif
69
70 #define THREAD_LOCAL_POLL
71
72 #endif // CPU_X86_GLOBALDEFINITIONS_X86_HPP
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