23  */
  24 
  25 #ifndef CPU_X86_GLOBALDEFINITIONS_X86_HPP
  26 #define CPU_X86_GLOBALDEFINITIONS_X86_HPP
  27 
  28 const int StackAlignmentInBytes  = 16;
  29 
  30 // Indicates whether the C calling conventions require that
  31 // 32-bit integer argument values are extended to 64 bits.
  32 const bool CCallingConventionRequiresIntsAsLongs = false;
  33 
  34 #define SUPPORTS_NATIVE_CX8
  35 
  36 #define CPU_MULTI_COPY_ATOMIC
  37 
  38 // The expected size in bytes of a cache line, used to pad data structures.
  39 #if defined(TIERED)
  40   #ifdef _LP64
  41     // tiered, 64-bit, large machine
  42     #define DEFAULT_CACHE_LINE_SIZE 128

  43   #else
  44     // tiered, 32-bit, medium machine
  45     #define DEFAULT_CACHE_LINE_SIZE 64
  46   #endif
  47 #elif defined(COMPILER1)
  48   // pure C1, 32-bit, small machine
  49   // i486 was the last Intel chip with 16-byte cache line size
  50   #define DEFAULT_CACHE_LINE_SIZE 32
  51 #elif defined(COMPILER2)
  52   #ifdef _LP64
  53     // pure C2, 64-bit, large machine
  54     #define DEFAULT_CACHE_LINE_SIZE 128

  55   #else
  56     // pure C2, 32-bit, medium machine
  57     #define DEFAULT_CACHE_LINE_SIZE 64
  58   #endif
  59 #endif
  60 
  61 #if defined(COMPILER2)
  62 // Include Restricted Transactional Memory lock eliding optimization
  63 #define INCLUDE_RTM_OPT 1
  64 #endif
  65 
  66 #if defined(LINUX) || defined(SOLARIS) || defined(__APPLE__)
  67 #define SUPPORT_RESERVED_STACK_AREA
  68 #endif
  69 
  70 #define THREAD_LOCAL_POLL
  71 
  72 #endif // CPU_X86_GLOBALDEFINITIONS_X86_HPP

  23  */
  24 
  25 #ifndef CPU_X86_GLOBALDEFINITIONS_X86_HPP
  26 #define CPU_X86_GLOBALDEFINITIONS_X86_HPP
  27 
  28 const int StackAlignmentInBytes  = 16;
  29 
  30 // Indicates whether the C calling conventions require that
  31 // 32-bit integer argument values are extended to 64 bits.
  32 const bool CCallingConventionRequiresIntsAsLongs = false;
  33 
  34 #define SUPPORTS_NATIVE_CX8
  35 
  36 #define CPU_MULTI_COPY_ATOMIC
  37 
  38 // The expected size in bytes of a cache line, used to pad data structures.
  39 #if defined(TIERED)
  40   #ifdef _LP64
  41     // tiered, 64-bit, large machine
  42     #define DEFAULT_CACHE_LINE_SIZE 128
  43     #define OM_CACHE_LINE_SIZE 64
  44   #else
  45     // tiered, 32-bit, medium machine
  46     #define DEFAULT_CACHE_LINE_SIZE 64
  47   #endif
  48 #elif defined(COMPILER1)
  49   // pure C1, 32-bit, small machine
  50   // i486 was the last Intel chip with 16-byte cache line size
  51   #define DEFAULT_CACHE_LINE_SIZE 32
  52 #elif defined(COMPILER2)
  53   #ifdef _LP64
  54     // pure C2, 64-bit, large machine
  55     #define DEFAULT_CACHE_LINE_SIZE 128
  56     #define OM_CACHE_LINE_SIZE 64
  57   #else
  58     // pure C2, 32-bit, medium machine
  59     #define DEFAULT_CACHE_LINE_SIZE 64
  60   #endif
  61 #endif
  62 
  63 #if defined(COMPILER2)
  64 // Include Restricted Transactional Memory lock eliding optimization
  65 #define INCLUDE_RTM_OPT 1
  66 #endif
  67 
  68 #if defined(LINUX) || defined(SOLARIS) || defined(__APPLE__)
  69 #define SUPPORT_RESERVED_STACK_AREA
  70 #endif
  71 
  72 #define THREAD_LOCAL_POLL
  73 
  74 #endif // CPU_X86_GLOBALDEFINITIONS_X86_HPP