1 /*
2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef SHARE_VM_C1_C1_LIR_HPP
26 #define SHARE_VM_C1_C1_LIR_HPP
27
28 #include "c1/c1_ValueType.hpp"
29 #include "oops/method.hpp"
30
31 class BlockBegin;
32 class BlockList;
33 class LIR_Assembler;
34 class CodeEmitInfo;
35 class CodeStub;
36 class CodeStubList;
37 class ArrayCopyStub;
38 class LIR_Op;
39 class ciType;
40 class ValueType;
41 class LIR_OpVisitState;
42 class FpuStackSim;
43
44 //---------------------------------------------------------------------
45 // LIR Operands
46 // LIR_OprDesc
47 // LIR_OprPtr
544 #if defined(X86) || defined(ARM)
545 LIR_Address(LIR_Opr base, LIR_Opr index, Scale scale, intx disp, BasicType type):
546 _base(base)
547 , _index(index)
548 , _scale(scale)
549 , _type(type)
550 , _disp(disp) { verify(); }
551 #endif // X86 || ARM
552
553 LIR_Opr base() const { return _base; }
554 LIR_Opr index() const { return _index; }
555 Scale scale() const { return _scale; }
556 intx disp() const { return _disp; }
557
558 bool equals(LIR_Address* other) const { return base() == other->base() && index() == other->index() && disp() == other->disp() && scale() == other->scale(); }
559
560 virtual LIR_Address* as_address() { return this; }
561 virtual BasicType type() const { return _type; }
562 virtual void print_value_on(outputStream* out) const PRODUCT_RETURN;
563
564 void verify() const PRODUCT_RETURN;
565
566 static Scale scale(BasicType type);
567 };
568
569
570 // operand factory
571 class LIR_OprFact: public AllStatic {
572 public:
573
574 static LIR_Opr illegalOpr;
575
576 static LIR_Opr single_cpu(int reg) {
577 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
578 LIR_OprDesc::int_type |
579 LIR_OprDesc::cpu_register |
580 LIR_OprDesc::single_size);
581 }
582 static LIR_Opr single_cpu_oop(int reg) {
583 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
584 LIR_OprDesc::object_type |
593 }
594 static LIR_Opr single_cpu_metadata(int reg) {
595 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
596 LIR_OprDesc::metadata_type |
597 LIR_OprDesc::cpu_register |
598 LIR_OprDesc::single_size);
599 }
600 static LIR_Opr double_cpu(int reg1, int reg2) {
601 LP64_ONLY(assert(reg1 == reg2, "must be identical"));
602 return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
603 (reg2 << LIR_OprDesc::reg2_shift) |
604 LIR_OprDesc::long_type |
605 LIR_OprDesc::cpu_register |
606 LIR_OprDesc::double_size);
607 }
608
609 static LIR_Opr single_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
610 LIR_OprDesc::float_type |
611 LIR_OprDesc::fpu_register |
612 LIR_OprDesc::single_size); }
613 #if defined(ARM)
614 static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); }
615 static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) | LIR_OprDesc::float_type | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size); }
616 static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::cpu_register | LIR_OprDesc::double_size); }
617 #endif
618 #ifdef SPARC
619 static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
620 (reg2 << LIR_OprDesc::reg2_shift) |
621 LIR_OprDesc::double_type |
622 LIR_OprDesc::fpu_register |
623 LIR_OprDesc::double_size); }
624 #endif
625 #ifdef X86
626 static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
627 (reg << LIR_OprDesc::reg2_shift) |
628 LIR_OprDesc::double_type |
629 LIR_OprDesc::fpu_register |
630 LIR_OprDesc::double_size); }
631
632 static LIR_Opr single_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
633 LIR_OprDesc::float_type |
634 LIR_OprDesc::fpu_register |
635 LIR_OprDesc::single_size |
636 LIR_OprDesc::is_xmm_mask); }
637 static LIR_Opr double_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
638 (reg << LIR_OprDesc::reg2_shift) |
639 LIR_OprDesc::double_type |
640 LIR_OprDesc::fpu_register |
641 LIR_OprDesc::double_size |
642 LIR_OprDesc::is_xmm_mask); }
643 #endif // X86
644 #ifdef PPC
645 static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
646 (reg << LIR_OprDesc::reg2_shift) |
647 LIR_OprDesc::double_type |
648 LIR_OprDesc::fpu_register |
649 LIR_OprDesc::double_size); }
650 static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) |
651 LIR_OprDesc::float_type |
652 LIR_OprDesc::cpu_register |
653 LIR_OprDesc::single_size); }
654 static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg2 << LIR_OprDesc::reg1_shift) |
655 (reg1 << LIR_OprDesc::reg2_shift) |
656 LIR_OprDesc::double_type |
657 LIR_OprDesc::cpu_register |
658 LIR_OprDesc::double_size); }
659 #endif // PPC
660
661 static LIR_Opr virtual_register(int index, BasicType type) {
662 LIR_Opr res;
663 switch (type) {
664 case T_OBJECT: // fall through
|
1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef SHARE_VM_C1_C1_LIR_HPP
26 #define SHARE_VM_C1_C1_LIR_HPP
27
28 #include "c1/c1_Defs.hpp"
29 #include "c1/c1_ValueType.hpp"
30 #include "oops/method.hpp"
31
32 class BlockBegin;
33 class BlockList;
34 class LIR_Assembler;
35 class CodeEmitInfo;
36 class CodeStub;
37 class CodeStubList;
38 class ArrayCopyStub;
39 class LIR_Op;
40 class ciType;
41 class ValueType;
42 class LIR_OpVisitState;
43 class FpuStackSim;
44
45 //---------------------------------------------------------------------
46 // LIR Operands
47 // LIR_OprDesc
48 // LIR_OprPtr
545 #if defined(X86) || defined(ARM)
546 LIR_Address(LIR_Opr base, LIR_Opr index, Scale scale, intx disp, BasicType type):
547 _base(base)
548 , _index(index)
549 , _scale(scale)
550 , _type(type)
551 , _disp(disp) { verify(); }
552 #endif // X86 || ARM
553
554 LIR_Opr base() const { return _base; }
555 LIR_Opr index() const { return _index; }
556 Scale scale() const { return _scale; }
557 intx disp() const { return _disp; }
558
559 bool equals(LIR_Address* other) const { return base() == other->base() && index() == other->index() && disp() == other->disp() && scale() == other->scale(); }
560
561 virtual LIR_Address* as_address() { return this; }
562 virtual BasicType type() const { return _type; }
563 virtual void print_value_on(outputStream* out) const PRODUCT_RETURN;
564
565 void verify0() const PRODUCT_RETURN;
566 #if defined(LIR_ADDRESS_PD_VERIFY) && !defined(PRODUCT)
567 void pd_verify() const;
568 void verify() const { pd_verify(); }
569 #else
570 void verify() const { verify0(); }
571 #endif
572
573 static Scale scale(BasicType type);
574 };
575
576
577 // operand factory
578 class LIR_OprFact: public AllStatic {
579 public:
580
581 static LIR_Opr illegalOpr;
582
583 static LIR_Opr single_cpu(int reg) {
584 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
585 LIR_OprDesc::int_type |
586 LIR_OprDesc::cpu_register |
587 LIR_OprDesc::single_size);
588 }
589 static LIR_Opr single_cpu_oop(int reg) {
590 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
591 LIR_OprDesc::object_type |
600 }
601 static LIR_Opr single_cpu_metadata(int reg) {
602 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
603 LIR_OprDesc::metadata_type |
604 LIR_OprDesc::cpu_register |
605 LIR_OprDesc::single_size);
606 }
607 static LIR_Opr double_cpu(int reg1, int reg2) {
608 LP64_ONLY(assert(reg1 == reg2, "must be identical"));
609 return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
610 (reg2 << LIR_OprDesc::reg2_shift) |
611 LIR_OprDesc::long_type |
612 LIR_OprDesc::cpu_register |
613 LIR_OprDesc::double_size);
614 }
615
616 static LIR_Opr single_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
617 LIR_OprDesc::float_type |
618 LIR_OprDesc::fpu_register |
619 LIR_OprDesc::single_size); }
620 #if defined(C1_LIR_MD_HPP)
621 # include C1_LIR_MD_HPP
622 #elif defined(SPARC)
623 static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
624 (reg2 << LIR_OprDesc::reg2_shift) |
625 LIR_OprDesc::double_type |
626 LIR_OprDesc::fpu_register |
627 LIR_OprDesc::double_size); }
628 #elif defined(X86)
629 static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
630 (reg << LIR_OprDesc::reg2_shift) |
631 LIR_OprDesc::double_type |
632 LIR_OprDesc::fpu_register |
633 LIR_OprDesc::double_size); }
634
635 static LIR_Opr single_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
636 LIR_OprDesc::float_type |
637 LIR_OprDesc::fpu_register |
638 LIR_OprDesc::single_size |
639 LIR_OprDesc::is_xmm_mask); }
640 static LIR_Opr double_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
641 (reg << LIR_OprDesc::reg2_shift) |
642 LIR_OprDesc::double_type |
643 LIR_OprDesc::fpu_register |
644 LIR_OprDesc::double_size |
645 LIR_OprDesc::is_xmm_mask); }
646 #elif defined(PPC)
647 static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
648 (reg << LIR_OprDesc::reg2_shift) |
649 LIR_OprDesc::double_type |
650 LIR_OprDesc::fpu_register |
651 LIR_OprDesc::double_size); }
652 static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) |
653 LIR_OprDesc::float_type |
654 LIR_OprDesc::cpu_register |
655 LIR_OprDesc::single_size); }
656 static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg2 << LIR_OprDesc::reg1_shift) |
657 (reg1 << LIR_OprDesc::reg2_shift) |
658 LIR_OprDesc::double_type |
659 LIR_OprDesc::cpu_register |
660 LIR_OprDesc::double_size); }
661 #endif // PPC
662
663 static LIR_Opr virtual_register(int index, BasicType type) {
664 LIR_Opr res;
665 switch (type) {
666 case T_OBJECT: // fall through
|