1 /*
2 * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_InstructionPrinter.hpp"
27 #include "c1/c1_LIR.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_ValueStack.hpp"
30 #include "ci/ciInstance.hpp"
31 #include "runtime/sharedRuntime.hpp"
32
33 Register LIR_OprDesc::as_register() const {
34 return FrameMap::cpu_rnr2reg(cpu_regnr());
35 }
36
37 Register LIR_OprDesc::as_register_lo() const {
38 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
39 }
40
41 Register LIR_OprDesc::as_register_hi() const {
42 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
43 }
44
45 #if defined(X86)
46
47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
48 return FrameMap::nr2xmmreg(xmm_regnr());
49 }
50
51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
53 return FrameMap::nr2xmmreg(xmm_regnrLo());
54 }
55
56 #endif // X86
57
58 #if defined(SPARC) || defined(PPC)
59
60 FloatRegister LIR_OprDesc::as_float_reg() const {
61 return FrameMap::nr2floatreg(fpu_regnr());
62 }
63
64 FloatRegister LIR_OprDesc::as_double_reg() const {
65 return FrameMap::nr2floatreg(fpu_regnrHi());
66 }
67
68 #endif
69
70 #if defined(ARM) || defined (AARCH64)
71
72 FloatRegister LIR_OprDesc::as_float_reg() const {
73 return as_FloatRegister(fpu_regnr());
74 }
75
76 FloatRegister LIR_OprDesc::as_double_reg() const {
77 return as_FloatRegister(fpu_regnrLo());
78 }
79
80 #endif
81
82
83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
84
85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
86 ValueTag tag = type->tag();
87 switch (tag) {
88 case metaDataTag : {
89 ClassConstant* c = type->as_ClassConstant();
90 if (c != NULL && !c->value()->is_loaded()) {
91 return LIR_OprFact::metadataConst(NULL);
92 } else if (c != NULL) {
93 return LIR_OprFact::metadataConst(c->value()->constant_encoding());
94 } else {
95 MethodConstant* m = type->as_MethodConstant();
96 assert (m != NULL, "not a class or a method?");
97 return LIR_OprFact::metadataConst(m->value()->constant_encoding());
98 }
99 }
100 case objectTag : {
101 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
102 }
103 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
104 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
105 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
106 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
107 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
108 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
109 }
110 }
111
112
113 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
114 switch (type->tag()) {
115 case objectTag: return LIR_OprFact::oopConst(NULL);
116 case addressTag:return LIR_OprFact::addressConst(0);
117 case intTag: return LIR_OprFact::intConst(0);
118 case floatTag: return LIR_OprFact::floatConst(0.0);
119 case longTag: return LIR_OprFact::longConst(0);
120 case doubleTag: return LIR_OprFact::doubleConst(0.0);
121 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
122 }
123 return illegalOpr;
124 }
125
126
127
128 //---------------------------------------------------
129
130
131 LIR_Address::Scale LIR_Address::scale(BasicType type) {
132 int elem_size = type2aelembytes(type);
133 switch (elem_size) {
134 case 1: return LIR_Address::times_1;
135 case 2: return LIR_Address::times_2;
136 case 4: return LIR_Address::times_4;
137 case 8: return LIR_Address::times_8;
138 }
139 ShouldNotReachHere();
140 return LIR_Address::times_1;
141 }
142
143
144 #ifndef PRODUCT
145 void LIR_Address::verify() const {
146 #if defined(SPARC) || defined(PPC)
147 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
148 assert(disp() == 0 || index()->is_illegal(), "can't have both");
149 #endif
150 #ifdef ARM
151 assert(disp() == 0 || index()->is_illegal(), "can't have both");
152 // Note: offsets higher than 4096 must not be rejected here. They can
153 // be handled by the back-end or will be rejected if not.
154 #endif
155 #ifdef _LP64
156 assert(base()->is_cpu_register(), "wrong base operand");
157 #ifndef AARCH64
158 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
159 #else
160 assert(index()->is_illegal() || index()->is_double_cpu() || index()->is_single_cpu(), "wrong index operand");
161 #endif
162 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
163 "wrong type for addresses");
164 #else
165 assert(base()->is_single_cpu(), "wrong base operand");
166 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
167 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
168 "wrong type for addresses");
169 #endif
170 }
171 #endif
172
173
174 //---------------------------------------------------
175
176 char LIR_OprDesc::type_char(BasicType t) {
177 switch (t) {
178 case T_ARRAY:
179 t = T_OBJECT;
180 case T_BOOLEAN:
181 case T_CHAR:
182 case T_FLOAT:
183 case T_DOUBLE:
184 case T_BYTE:
185 case T_SHORT:
186 case T_INT:
187 case T_LONG:
188 case T_OBJECT:
189 case T_ADDRESS:
190 case T_VOID:
191 return ::type2char(t);
192 case T_METADATA:
193 return 'M';
194 case T_ILLEGAL:
195 return '?';
196
197 default:
198 ShouldNotReachHere();
199 return '?';
200 }
201 }
202
203 #ifndef PRODUCT
204 void LIR_OprDesc::validate_type() const {
205
206 #ifdef ASSERT
207 if (!is_pointer() && !is_illegal()) {
208 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
209 switch (as_BasicType(type_field())) {
210 case T_LONG:
211 assert((kindfield == cpu_register || kindfield == stack_value) &&
212 size_field() == double_size, "must match");
213 break;
214 case T_FLOAT:
215 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
216 assert((kindfield == fpu_register || kindfield == stack_value
217 ARM_ONLY(|| kindfield == cpu_register)
218 PPC_ONLY(|| kindfield == cpu_register) ) &&
219 size_field() == single_size, "must match");
220 break;
221 case T_DOUBLE:
222 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
223 assert((kindfield == fpu_register || kindfield == stack_value
224 ARM_ONLY(|| kindfield == cpu_register)
225 PPC_ONLY(|| kindfield == cpu_register) ) &&
226 size_field() == double_size, "must match");
227 break;
228 case T_BOOLEAN:
229 case T_CHAR:
230 case T_BYTE:
231 case T_SHORT:
232 case T_INT:
233 case T_ADDRESS:
234 case T_OBJECT:
235 case T_METADATA:
236 case T_ARRAY:
237 assert((kindfield == cpu_register || kindfield == stack_value) &&
238 size_field() == single_size, "must match");
239 break;
240
241 case T_ILLEGAL:
242 // XXX TKR also means unknown right now
243 // assert(is_illegal(), "must match");
244 break;
245
246 default:
247 ShouldNotReachHere();
248 }
249 }
250 #endif
251
252 }
253 #endif // PRODUCT
254
255
256 bool LIR_OprDesc::is_oop() const {
257 if (is_pointer()) {
258 return pointer()->is_oop_pointer();
259 } else {
260 OprType t= type_field();
261 assert(t != unknown_type, "not set");
262 return t == object_type;
263 }
264 }
265
266
267
268 void LIR_Op2::verify() const {
269 #ifdef ASSERT
270 switch (code()) {
271 case lir_cmove:
272 case lir_xchg:
273 break;
274
275 default:
276 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
277 "can't produce oops from arith");
278 }
279
280 if (TwoOperandLIRForm) {
281 switch (code()) {
282 case lir_add:
283 case lir_sub:
284 case lir_mul:
285 case lir_mul_strictfp:
286 case lir_div:
287 case lir_div_strictfp:
288 case lir_rem:
289 case lir_logic_and:
290 case lir_logic_or:
291 case lir_logic_xor:
292 case lir_shl:
293 case lir_shr:
294 assert(in_opr1() == result_opr(), "opr1 and result must match");
295 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
296 break;
297
298 // special handling for lir_ushr because of write barriers
299 case lir_ushr:
300 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
301 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
302 break;
303
304 }
305 }
306 #endif
307 }
308
309
310 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
311 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
312 , _cond(cond)
313 , _type(type)
314 , _label(block->label())
315 , _block(block)
316 , _ublock(NULL)
317 , _stub(NULL) {
318 }
319
320 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
321 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
322 , _cond(cond)
323 , _type(type)
324 , _label(stub->entry())
325 , _block(NULL)
326 , _ublock(NULL)
327 , _stub(stub) {
328 }
329
330 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
331 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
332 , _cond(cond)
333 , _type(type)
334 , _label(block->label())
335 , _block(block)
336 , _ublock(ublock)
337 , _stub(NULL)
338 {
339 }
340
341 void LIR_OpBranch::change_block(BlockBegin* b) {
342 assert(_block != NULL, "must have old block");
343 assert(_block->label() == label(), "must be equal");
344
345 _block = b;
346 _label = b->label();
347 }
348
349 void LIR_OpBranch::change_ublock(BlockBegin* b) {
350 assert(_ublock != NULL, "must have old block");
351 _ublock = b;
352 }
353
354 void LIR_OpBranch::negate_cond() {
355 switch (_cond) {
356 case lir_cond_equal: _cond = lir_cond_notEqual; break;
357 case lir_cond_notEqual: _cond = lir_cond_equal; break;
358 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
359 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
360 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
361 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
362 default: ShouldNotReachHere();
363 }
364 }
365
366
367 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
368 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
369 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
370 CodeStub* stub)
371
372 : LIR_Op(code, result, NULL)
373 , _object(object)
374 , _array(LIR_OprFact::illegalOpr)
375 , _klass(klass)
376 , _tmp1(tmp1)
377 , _tmp2(tmp2)
378 , _tmp3(tmp3)
379 , _fast_check(fast_check)
380 , _stub(stub)
381 , _info_for_patch(info_for_patch)
382 , _info_for_exception(info_for_exception)
383 , _profiled_method(NULL)
384 , _profiled_bci(-1)
385 , _should_profile(false)
386 {
387 if (code == lir_checkcast) {
388 assert(info_for_exception != NULL, "checkcast throws exceptions");
389 } else if (code == lir_instanceof) {
390 assert(info_for_exception == NULL, "instanceof throws no exceptions");
391 } else {
392 ShouldNotReachHere();
393 }
394 }
395
396
397
398 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
399 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
400 , _object(object)
401 , _array(array)
402 , _klass(NULL)
403 , _tmp1(tmp1)
404 , _tmp2(tmp2)
405 , _tmp3(tmp3)
406 , _fast_check(false)
407 , _stub(NULL)
408 , _info_for_patch(NULL)
409 , _info_for_exception(info_for_exception)
410 , _profiled_method(NULL)
411 , _profiled_bci(-1)
412 , _should_profile(false)
413 {
414 if (code == lir_store_check) {
415 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
416 assert(info_for_exception != NULL, "store_check throws exceptions");
417 } else {
418 ShouldNotReachHere();
419 }
420 }
421
422
423 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
424 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
425 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
426 , _tmp(tmp)
427 , _src(src)
428 , _src_pos(src_pos)
429 , _dst(dst)
430 , _dst_pos(dst_pos)
431 , _flags(flags)
432 , _expected_type(expected_type)
433 , _length(length) {
434 _stub = new ArrayCopyStub(this);
435 }
436
437 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
438 : LIR_Op(lir_updatecrc32, res, NULL)
439 , _crc(crc)
440 , _val(val) {
441 }
442
443 //-------------------verify--------------------------
444
445 void LIR_Op1::verify() const {
446 switch(code()) {
447 case lir_move:
448 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
449 break;
450 case lir_null_check:
451 assert(in_opr()->is_register(), "must be");
452 break;
453 case lir_return:
454 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
455 break;
456 }
457 }
458
459 void LIR_OpRTCall::verify() const {
460 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
461 }
462
463 //-------------------visits--------------------------
464
465 // complete rework of LIR instruction visitor.
466 // The virtual calls for each instruction type is replaced by a big
467 // switch that adds the operands for each instruction
468
469 void LIR_OpVisitState::visit(LIR_Op* op) {
470 // copy information from the LIR_Op
471 reset();
472 set_op(op);
473
474 switch (op->code()) {
475
476 // LIR_Op0
477 case lir_word_align: // result and info always invalid
478 case lir_backwardbranch_target: // result and info always invalid
479 case lir_build_frame: // result and info always invalid
480 case lir_fpop_raw: // result and info always invalid
481 case lir_24bit_FPU: // result and info always invalid
482 case lir_reset_FPU: // result and info always invalid
483 case lir_breakpoint: // result and info always invalid
484 case lir_membar: // result and info always invalid
485 case lir_membar_acquire: // result and info always invalid
486 case lir_membar_release: // result and info always invalid
487 case lir_membar_loadload: // result and info always invalid
488 case lir_membar_storestore: // result and info always invalid
489 case lir_membar_loadstore: // result and info always invalid
490 case lir_membar_storeload: // result and info always invalid
491 {
492 assert(op->as_Op0() != NULL, "must be");
493 assert(op->_info == NULL, "info not used by this instruction");
494 assert(op->_result->is_illegal(), "not used");
495 break;
496 }
497
498 case lir_nop: // may have info, result always invalid
499 case lir_std_entry: // may have result, info always invalid
500 case lir_osr_entry: // may have result, info always invalid
501 case lir_get_thread: // may have result, info always invalid
502 {
503 assert(op->as_Op0() != NULL, "must be");
504 if (op->_info != NULL) do_info(op->_info);
505 if (op->_result->is_valid()) do_output(op->_result);
506 break;
507 }
508
509
510 // LIR_OpLabel
511 case lir_label: // result and info always invalid
512 {
513 assert(op->as_OpLabel() != NULL, "must be");
514 assert(op->_info == NULL, "info not used by this instruction");
515 assert(op->_result->is_illegal(), "not used");
516 break;
517 }
518
519
520 // LIR_Op1
521 case lir_fxch: // input always valid, result and info always invalid
522 case lir_fld: // input always valid, result and info always invalid
523 case lir_ffree: // input always valid, result and info always invalid
524 case lir_push: // input always valid, result and info always invalid
525 case lir_pop: // input always valid, result and info always invalid
526 case lir_return: // input always valid, result and info always invalid
527 case lir_leal: // input and result always valid, info always invalid
528 case lir_neg: // input and result always valid, info always invalid
529 case lir_monaddr: // input and result always valid, info always invalid
530 case lir_null_check: // input and info always valid, result always invalid
531 case lir_move: // input and result always valid, may have info
532 case lir_pack64: // input and result always valid
533 case lir_unpack64: // input and result always valid
534 {
535 assert(op->as_Op1() != NULL, "must be");
536 LIR_Op1* op1 = (LIR_Op1*)op;
537
538 if (op1->_info) do_info(op1->_info);
539 if (op1->_opr->is_valid()) do_input(op1->_opr);
540 if (op1->_result->is_valid()) do_output(op1->_result);
541
542 break;
543 }
544
545 case lir_safepoint:
546 {
547 assert(op->as_Op1() != NULL, "must be");
548 LIR_Op1* op1 = (LIR_Op1*)op;
549
550 assert(op1->_info != NULL, ""); do_info(op1->_info);
551 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
552 assert(op1->_result->is_illegal(), "safepoint does not produce value");
553
554 break;
555 }
556
557 // LIR_OpConvert;
558 case lir_convert: // input and result always valid, info always invalid
559 {
560 assert(op->as_OpConvert() != NULL, "must be");
561 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
562
563 assert(opConvert->_info == NULL, "must be");
564 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
565 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
566 #ifdef PPC
567 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
568 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
569 #endif
570 do_stub(opConvert->_stub);
571
572 break;
573 }
574
575 // LIR_OpBranch;
576 case lir_branch: // may have info, input and result register always invalid
577 case lir_cond_float_branch: // may have info, input and result register always invalid
578 {
579 assert(op->as_OpBranch() != NULL, "must be");
580 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
581
582 if (opBranch->_info != NULL) do_info(opBranch->_info);
583 assert(opBranch->_result->is_illegal(), "not used");
584 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
585
586 break;
587 }
588
589
590 // LIR_OpAllocObj
591 case lir_alloc_object:
592 {
593 assert(op->as_OpAllocObj() != NULL, "must be");
594 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
595
596 if (opAllocObj->_info) do_info(opAllocObj->_info);
597 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
598 do_temp(opAllocObj->_opr);
599 }
600 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
601 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
602 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
603 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
604 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
605 do_stub(opAllocObj->_stub);
606 break;
607 }
608
609
610 // LIR_OpRoundFP;
611 case lir_roundfp: {
612 assert(op->as_OpRoundFP() != NULL, "must be");
613 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
614
615 assert(op->_info == NULL, "info not used by this instruction");
616 assert(opRoundFP->_tmp->is_illegal(), "not used");
617 do_input(opRoundFP->_opr);
618 do_output(opRoundFP->_result);
619
620 break;
621 }
622
623
624 // LIR_Op2
625 case lir_cmp:
626 case lir_cmp_l2i:
627 case lir_ucmp_fd2i:
628 case lir_cmp_fd2i:
629 case lir_add:
630 case lir_sub:
631 case lir_mul:
632 case lir_div:
633 case lir_rem:
634 case lir_sqrt:
635 case lir_abs:
636 case lir_logic_and:
637 case lir_logic_or:
638 case lir_logic_xor:
639 case lir_shl:
640 case lir_shr:
641 case lir_ushr:
642 case lir_xadd:
643 case lir_xchg:
644 case lir_assert:
645 {
646 assert(op->as_Op2() != NULL, "must be");
647 LIR_Op2* op2 = (LIR_Op2*)op;
648 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
649 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
650
651 if (op2->_info) do_info(op2->_info);
652 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
653 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
654 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
655 if (op2->_result->is_valid()) do_output(op2->_result);
656 if (op->code() == lir_xchg || op->code() == lir_xadd) {
657 // on ARM and PPC, return value is loaded first so could
658 // destroy inputs. On other platforms that implement those
659 // (x86, sparc), the extra constrainsts are harmless.
660 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
661 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
662 }
663
664 break;
665 }
666
667 // special handling for cmove: right input operand must not be equal
668 // to the result operand, otherwise the backend fails
669 case lir_cmove:
670 {
671 assert(op->as_Op2() != NULL, "must be");
672 LIR_Op2* op2 = (LIR_Op2*)op;
673
674 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
675 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
676 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
677
678 do_input(op2->_opr1);
679 do_input(op2->_opr2);
680 do_temp(op2->_opr2);
681 do_output(op2->_result);
682
683 break;
684 }
685
686 // vspecial handling for strict operations: register input operands
687 // as temp to guarantee that they do not overlap with other
688 // registers
689 case lir_mul_strictfp:
690 case lir_div_strictfp:
691 {
692 assert(op->as_Op2() != NULL, "must be");
693 LIR_Op2* op2 = (LIR_Op2*)op;
694
695 assert(op2->_info == NULL, "not used");
696 assert(op2->_opr1->is_valid(), "used");
697 assert(op2->_opr2->is_valid(), "used");
698 assert(op2->_result->is_valid(), "used");
699 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
700 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
701
702 do_input(op2->_opr1); do_temp(op2->_opr1);
703 do_input(op2->_opr2); do_temp(op2->_opr2);
704 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
705 do_output(op2->_result);
706
707 break;
708 }
709
710 case lir_throw: {
711 assert(op->as_Op2() != NULL, "must be");
712 LIR_Op2* op2 = (LIR_Op2*)op;
713
714 if (op2->_info) do_info(op2->_info);
715 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
716 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
717 assert(op2->_result->is_illegal(), "no result");
718 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
719 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
720
721 break;
722 }
723
724 case lir_unwind: {
725 assert(op->as_Op1() != NULL, "must be");
726 LIR_Op1* op1 = (LIR_Op1*)op;
727
728 assert(op1->_info == NULL, "no info");
729 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
730 assert(op1->_result->is_illegal(), "no result");
731
732 break;
733 }
734
735
736 case lir_tan:
737 case lir_sin:
738 case lir_cos:
739 case lir_log:
740 case lir_log10:
741 case lir_exp: {
742 assert(op->as_Op2() != NULL, "must be");
743 LIR_Op2* op2 = (LIR_Op2*)op;
744
745 // On x86 tan/sin/cos need two temporary fpu stack slots and
746 // log/log10 need one so handle opr2 and tmp as temp inputs.
747 // Register input operand as temp to guarantee that it doesn't
748 // overlap with the input.
749 assert(op2->_info == NULL, "not used");
750 assert(op2->_tmp5->is_illegal(), "not used");
751 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used");
752 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used");
753 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used");
754 assert(op2->_opr1->is_valid(), "used");
755 do_input(op2->_opr1); do_temp(op2->_opr1);
756
757 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
758 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
759 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2);
760 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3);
761 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4);
762 if (op2->_result->is_valid()) do_output(op2->_result);
763
764 break;
765 }
766
767 case lir_pow: {
768 assert(op->as_Op2() != NULL, "must be");
769 LIR_Op2* op2 = (LIR_Op2*)op;
770
771 // On x86 pow needs two temporary fpu stack slots: tmp1 and
772 // tmp2. Register input operands as temps to guarantee that it
773 // doesn't overlap with the temporary slots.
774 assert(op2->_info == NULL, "not used");
775 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used");
776 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid()
777 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used");
778 assert(op2->_result->is_valid(), "used");
779
780 do_input(op2->_opr1); do_temp(op2->_opr1);
781 do_input(op2->_opr2); do_temp(op2->_opr2);
782 do_temp(op2->_tmp1);
783 do_temp(op2->_tmp2);
784 do_temp(op2->_tmp3);
785 do_temp(op2->_tmp4);
786 do_temp(op2->_tmp5);
787 do_output(op2->_result);
788
789 break;
790 }
791
792 // LIR_Op3
793 case lir_idiv:
794 case lir_irem: {
795 assert(op->as_Op3() != NULL, "must be");
796 LIR_Op3* op3= (LIR_Op3*)op;
797
798 if (op3->_info) do_info(op3->_info);
799 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
800
801 // second operand is input and temp, so ensure that second operand
802 // and third operand get not the same register
803 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
804 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
805 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
806
807 if (op3->_result->is_valid()) do_output(op3->_result);
808
809 break;
810 }
811
812
813 // LIR_OpJavaCall
814 case lir_static_call:
815 case lir_optvirtual_call:
816 case lir_icvirtual_call:
817 case lir_virtual_call:
818 case lir_dynamic_call: {
819 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
820 assert(opJavaCall != NULL, "must be");
821
822 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
823
824 // only visit register parameters
825 int n = opJavaCall->_arguments->length();
826 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
827 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
828 do_input(*opJavaCall->_arguments->adr_at(i));
829 }
830 }
831
832 if (opJavaCall->_info) do_info(opJavaCall->_info);
833 if (opJavaCall->is_method_handle_invoke()) {
834 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
835 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
836 }
837 do_call();
838 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
839
840 break;
841 }
842
843
844 // LIR_OpRTCall
845 case lir_rtcall: {
846 assert(op->as_OpRTCall() != NULL, "must be");
847 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
848
849 // only visit register parameters
850 int n = opRTCall->_arguments->length();
851 for (int i = 0; i < n; i++) {
852 if (!opRTCall->_arguments->at(i)->is_pointer()) {
853 do_input(*opRTCall->_arguments->adr_at(i));
854 }
855 }
856 if (opRTCall->_info) do_info(opRTCall->_info);
857 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
858 do_call();
859 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
860
861 break;
862 }
863
864
865 // LIR_OpArrayCopy
866 case lir_arraycopy: {
867 assert(op->as_OpArrayCopy() != NULL, "must be");
868 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
869
870 assert(opArrayCopy->_result->is_illegal(), "unused");
871 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
872 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
873 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
874 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
875 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
876 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
877 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
878
879 // the implementation of arraycopy always has a call into the runtime
880 do_call();
881
882 break;
883 }
884
885
886 // LIR_OpUpdateCRC32
887 case lir_updatecrc32: {
888 assert(op->as_OpUpdateCRC32() != NULL, "must be");
889 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
890
891 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc);
892 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val);
893 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result);
894 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
895
896 break;
897 }
898
899
900 // LIR_OpLock
901 case lir_lock:
902 case lir_unlock: {
903 assert(op->as_OpLock() != NULL, "must be");
904 LIR_OpLock* opLock = (LIR_OpLock*)op;
905
906 if (opLock->_info) do_info(opLock->_info);
907
908 // TODO: check if these operands really have to be temp
909 // (or if input is sufficient). This may have influence on the oop map!
910 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
911 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
912 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
913
914 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
915 assert(opLock->_result->is_illegal(), "unused");
916
917 do_stub(opLock->_stub);
918
919 break;
920 }
921
922
923 // LIR_OpDelay
924 case lir_delay_slot: {
925 assert(op->as_OpDelay() != NULL, "must be");
926 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
927
928 visit(opDelay->delay_op());
929 break;
930 }
931
932 // LIR_OpTypeCheck
933 case lir_instanceof:
934 case lir_checkcast:
935 case lir_store_check: {
936 assert(op->as_OpTypeCheck() != NULL, "must be");
937 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
938
939 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
940 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
941 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
942 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
943 do_temp(opTypeCheck->_object);
944 }
945 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
946 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
947 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
948 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
949 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
950 do_stub(opTypeCheck->_stub);
951 break;
952 }
953
954 // LIR_OpCompareAndSwap
955 case lir_cas_long:
956 case lir_cas_obj:
957 case lir_cas_int: {
958 assert(op->as_OpCompareAndSwap() != NULL, "must be");
959 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
960
961 assert(opCompareAndSwap->_addr->is_valid(), "used");
962 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
963 assert(opCompareAndSwap->_new_value->is_valid(), "used");
964 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
965 do_input(opCompareAndSwap->_addr);
966 do_temp(opCompareAndSwap->_addr);
967 do_input(opCompareAndSwap->_cmp_value);
968 do_temp(opCompareAndSwap->_cmp_value);
969 do_input(opCompareAndSwap->_new_value);
970 do_temp(opCompareAndSwap->_new_value);
971 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
972 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
973 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
974
975 break;
976 }
977
978
979 // LIR_OpAllocArray;
980 case lir_alloc_array: {
981 assert(op->as_OpAllocArray() != NULL, "must be");
982 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
983
984 if (opAllocArray->_info) do_info(opAllocArray->_info);
985 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
986 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
987 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
988 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
989 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
990 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
991 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
992 do_stub(opAllocArray->_stub);
993 break;
994 }
995
996 // LIR_OpProfileCall:
997 case lir_profile_call: {
998 assert(op->as_OpProfileCall() != NULL, "must be");
999 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
1000
1001 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
1002 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
1003 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
1004 break;
1005 }
1006
1007 // LIR_OpProfileType:
1008 case lir_profile_type: {
1009 assert(op->as_OpProfileType() != NULL, "must be");
1010 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
1011
1012 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
1013 do_input(opProfileType->_obj);
1014 do_temp(opProfileType->_tmp);
1015 break;
1016 }
1017 default:
1018 ShouldNotReachHere();
1019 }
1020 }
1021
1022
1023 void LIR_OpVisitState::do_stub(CodeStub* stub) {
1024 if (stub != NULL) {
1025 stub->visit(this);
1026 }
1027 }
1028
1029 XHandlers* LIR_OpVisitState::all_xhandler() {
1030 XHandlers* result = NULL;
1031
1032 int i;
1033 for (i = 0; i < info_count(); i++) {
1034 if (info_at(i)->exception_handlers() != NULL) {
1035 result = info_at(i)->exception_handlers();
1036 break;
1037 }
1038 }
1039
1040 #ifdef ASSERT
1041 for (i = 0; i < info_count(); i++) {
1042 assert(info_at(i)->exception_handlers() == NULL ||
1043 info_at(i)->exception_handlers() == result,
1044 "only one xhandler list allowed per LIR-operation");
1045 }
1046 #endif
1047
1048 if (result != NULL) {
1049 return result;
1050 } else {
1051 return new XHandlers();
1052 }
1053
1054 return result;
1055 }
1056
1057
1058 #ifdef ASSERT
1059 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1060 visit(op);
1061
1062 return opr_count(inputMode) == 0 &&
1063 opr_count(outputMode) == 0 &&
1064 opr_count(tempMode) == 0 &&
1065 info_count() == 0 &&
1066 !has_call() &&
1067 !has_slow_case();
1068 }
1069 #endif
1070
1071 //---------------------------------------------------
1072
1073
1074 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1075 masm->emit_call(this);
1076 }
1077
1078 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1079 masm->emit_rtcall(this);
1080 }
1081
1082 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1083 masm->emit_opLabel(this);
1084 }
1085
1086 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1087 masm->emit_arraycopy(this);
1088 masm->append_code_stub(stub());
1089 }
1090
1091 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1092 masm->emit_updatecrc32(this);
1093 }
1094
1095 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1096 masm->emit_op0(this);
1097 }
1098
1099 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1100 masm->emit_op1(this);
1101 }
1102
1103 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1104 masm->emit_alloc_obj(this);
1105 masm->append_code_stub(stub());
1106 }
1107
1108 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1109 masm->emit_opBranch(this);
1110 if (stub()) {
1111 masm->append_code_stub(stub());
1112 }
1113 }
1114
1115 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1116 masm->emit_opConvert(this);
1117 if (stub() != NULL) {
1118 masm->append_code_stub(stub());
1119 }
1120 }
1121
1122 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1123 masm->emit_op2(this);
1124 }
1125
1126 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1127 masm->emit_alloc_array(this);
1128 masm->append_code_stub(stub());
1129 }
1130
1131 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1132 masm->emit_opTypeCheck(this);
1133 if (stub()) {
1134 masm->append_code_stub(stub());
1135 }
1136 }
1137
1138 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1139 masm->emit_compare_and_swap(this);
1140 }
1141
1142 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1143 masm->emit_op3(this);
1144 }
1145
1146 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1147 masm->emit_lock(this);
1148 if (stub()) {
1149 masm->append_code_stub(stub());
1150 }
1151 }
1152
1153 #ifdef ASSERT
1154 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1155 masm->emit_assert(this);
1156 }
1157 #endif
1158
1159 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1160 masm->emit_delay(this);
1161 }
1162
1163 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1164 masm->emit_profile_call(this);
1165 }
1166
1167 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1168 masm->emit_profile_type(this);
1169 }
1170
1171 // LIR_List
1172 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1173 : _operations(8)
1174 , _compilation(compilation)
1175 #ifndef PRODUCT
1176 , _block(block)
1177 #endif
1178 #ifdef ASSERT
1179 , _file(NULL)
1180 , _line(0)
1181 #endif
1182 { }
1183
1184
1185 #ifdef ASSERT
1186 void LIR_List::set_file_and_line(const char * file, int line) {
1187 const char * f = strrchr(file, '/');
1188 if (f == NULL) f = strrchr(file, '\\');
1189 if (f == NULL) {
1190 f = file;
1191 } else {
1192 f++;
1193 }
1194 _file = f;
1195 _line = line;
1196 }
1197 #endif
1198
1199
1200 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1201 assert(this == buffer->lir_list(), "wrong lir list");
1202 const int n = _operations.length();
1203
1204 if (buffer->number_of_ops() > 0) {
1205 // increase size of instructions list
1206 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1207 // insert ops from buffer into instructions list
1208 int op_index = buffer->number_of_ops() - 1;
1209 int ip_index = buffer->number_of_insertion_points() - 1;
1210 int from_index = n - 1;
1211 int to_index = _operations.length() - 1;
1212 for (; ip_index >= 0; ip_index --) {
1213 int index = buffer->index_at(ip_index);
1214 // make room after insertion point
1215 while (index < from_index) {
1216 _operations.at_put(to_index --, _operations.at(from_index --));
1217 }
1218 // insert ops from buffer
1219 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1220 _operations.at_put(to_index --, buffer->op_at(op_index --));
1221 }
1222 }
1223 }
1224
1225 buffer->finish();
1226 }
1227
1228
1229 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1230 assert(reg->type() == T_OBJECT, "bad reg");
1231 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1232 }
1233
1234 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1235 assert(reg->type() == T_METADATA, "bad reg");
1236 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1237 }
1238
1239 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1240 append(new LIR_Op1(
1241 lir_move,
1242 LIR_OprFact::address(addr),
1243 src,
1244 addr->type(),
1245 patch_code,
1246 info));
1247 }
1248
1249
1250 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1251 append(new LIR_Op1(
1252 lir_move,
1253 LIR_OprFact::address(address),
1254 dst,
1255 address->type(),
1256 patch_code,
1257 info, lir_move_volatile));
1258 }
1259
1260 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1261 append(new LIR_Op1(
1262 lir_move,
1263 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1264 dst,
1265 type,
1266 patch_code,
1267 info, lir_move_volatile));
1268 }
1269
1270
1271 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1272 append(new LIR_Op1(
1273 lir_move,
1274 LIR_OprFact::intConst(v),
1275 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1276 type,
1277 patch_code,
1278 info));
1279 }
1280
1281
1282 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1283 append(new LIR_Op1(
1284 lir_move,
1285 LIR_OprFact::oopConst(o),
1286 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1287 type,
1288 patch_code,
1289 info));
1290 }
1291
1292
1293 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1294 append(new LIR_Op1(
1295 lir_move,
1296 src,
1297 LIR_OprFact::address(addr),
1298 addr->type(),
1299 patch_code,
1300 info));
1301 }
1302
1303
1304 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1305 append(new LIR_Op1(
1306 lir_move,
1307 src,
1308 LIR_OprFact::address(addr),
1309 addr->type(),
1310 patch_code,
1311 info,
1312 lir_move_volatile));
1313 }
1314
1315 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1316 append(new LIR_Op1(
1317 lir_move,
1318 src,
1319 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1320 type,
1321 patch_code,
1322 info, lir_move_volatile));
1323 }
1324
1325
1326 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1327 append(new LIR_Op3(
1328 lir_idiv,
1329 left,
1330 right,
1331 tmp,
1332 res,
1333 info));
1334 }
1335
1336
1337 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1338 append(new LIR_Op3(
1339 lir_idiv,
1340 left,
1341 LIR_OprFact::intConst(right),
1342 tmp,
1343 res,
1344 info));
1345 }
1346
1347
1348 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1349 append(new LIR_Op3(
1350 lir_irem,
1351 left,
1352 right,
1353 tmp,
1354 res,
1355 info));
1356 }
1357
1358
1359 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1360 append(new LIR_Op3(
1361 lir_irem,
1362 left,
1363 LIR_OprFact::intConst(right),
1364 tmp,
1365 res,
1366 info));
1367 }
1368
1369
1370 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1371 append(new LIR_Op2(
1372 lir_cmp,
1373 condition,
1374 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1375 LIR_OprFact::intConst(c),
1376 info));
1377 }
1378
1379
1380 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1381 append(new LIR_Op2(
1382 lir_cmp,
1383 condition,
1384 reg,
1385 LIR_OprFact::address(addr),
1386 info));
1387 }
1388
1389 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1390 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1391 append(new LIR_OpAllocObj(
1392 klass,
1393 dst,
1394 t1,
1395 t2,
1396 t3,
1397 t4,
1398 header_size,
1399 object_size,
1400 init_check,
1401 stub));
1402 }
1403
1404 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1405 append(new LIR_OpAllocArray(
1406 klass,
1407 len,
1408 dst,
1409 t1,
1410 t2,
1411 t3,
1412 t4,
1413 type,
1414 stub));
1415 }
1416
1417 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1418 append(new LIR_Op2(
1419 lir_shl,
1420 value,
1421 count,
1422 dst,
1423 tmp));
1424 }
1425
1426 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1427 append(new LIR_Op2(
1428 lir_shr,
1429 value,
1430 count,
1431 dst,
1432 tmp));
1433 }
1434
1435
1436 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1437 append(new LIR_Op2(
1438 lir_ushr,
1439 value,
1440 count,
1441 dst,
1442 tmp));
1443 }
1444
1445 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1446 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1447 left,
1448 right,
1449 dst));
1450 }
1451
1452 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1453 append(new LIR_OpLock(
1454 lir_lock,
1455 hdr,
1456 obj,
1457 lock,
1458 scratch,
1459 stub,
1460 info));
1461 }
1462
1463 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1464 append(new LIR_OpLock(
1465 lir_unlock,
1466 hdr,
1467 obj,
1468 lock,
1469 scratch,
1470 stub,
1471 NULL));
1472 }
1473
1474
1475 void check_LIR() {
1476 // cannot do the proper checking as PRODUCT and other modes return different results
1477 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1478 }
1479
1480
1481
1482 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1483 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1484 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1485 ciMethod* profiled_method, int profiled_bci) {
1486 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1487 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1488 if (profiled_method != NULL) {
1489 c->set_profiled_method(profiled_method);
1490 c->set_profiled_bci(profiled_bci);
1491 c->set_should_profile(true);
1492 }
1493 append(c);
1494 }
1495
1496 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1497 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1498 if (profiled_method != NULL) {
1499 c->set_profiled_method(profiled_method);
1500 c->set_profiled_bci(profiled_bci);
1501 c->set_should_profile(true);
1502 }
1503 append(c);
1504 }
1505
1506
1507 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1508 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1509 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1510 if (profiled_method != NULL) {
1511 c->set_profiled_method(profiled_method);
1512 c->set_profiled_bci(profiled_bci);
1513 c->set_should_profile(true);
1514 }
1515 append(c);
1516 }
1517
1518
1519 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1520 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1521 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1522 }
1523
1524 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1525 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1526 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1527 }
1528
1529 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1530 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1531 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1532 }
1533
1534
1535 #ifdef PRODUCT
1536
1537 void print_LIR(BlockList* blocks) {
1538 }
1539
1540 #else
1541 // LIR_OprDesc
1542 void LIR_OprDesc::print() const {
1543 print(tty);
1544 }
1545
1546 void LIR_OprDesc::print(outputStream* out) const {
1547 if (is_illegal()) {
1548 return;
1549 }
1550
1551 out->print("[");
1552 if (is_pointer()) {
1553 pointer()->print_value_on(out);
1554 } else if (is_single_stack()) {
1555 out->print("stack:%d", single_stack_ix());
1556 } else if (is_double_stack()) {
1557 out->print("dbl_stack:%d",double_stack_ix());
1558 } else if (is_virtual()) {
1559 out->print("R%d", vreg_number());
1560 } else if (is_single_cpu()) {
1561 out->print("%s", as_register()->name());
1562 } else if (is_double_cpu()) {
1563 out->print("%s", as_register_hi()->name());
1564 out->print("%s", as_register_lo()->name());
1565 #if defined(X86)
1566 } else if (is_single_xmm()) {
1567 out->print("%s", as_xmm_float_reg()->name());
1568 } else if (is_double_xmm()) {
1569 out->print("%s", as_xmm_double_reg()->name());
1570 } else if (is_single_fpu()) {
1571 out->print("fpu%d", fpu_regnr());
1572 } else if (is_double_fpu()) {
1573 out->print("fpu%d", fpu_regnrLo());
1574 #elif defined(AARCH64)
1575 } else if (is_single_fpu()) {
1576 out->print("fpu%d", fpu_regnr());
1577 } else if (is_double_fpu()) {
1578 out->print("fpu%d", fpu_regnrLo());
1579 #elif defined(ARM)
1580 } else if (is_single_fpu()) {
1581 out->print("s%d", fpu_regnr());
1582 } else if (is_double_fpu()) {
1583 out->print("d%d", fpu_regnrLo() >> 1);
1584 #else
1585 } else if (is_single_fpu()) {
1586 out->print("%s", as_float_reg()->name());
1587 } else if (is_double_fpu()) {
1588 out->print("%s", as_double_reg()->name());
1589 #endif
1590
1591 } else if (is_illegal()) {
1592 out->print("-");
1593 } else {
1594 out->print("Unknown Operand");
1595 }
1596 if (!is_illegal()) {
1597 out->print("|%c", type_char());
1598 }
1599 if (is_register() && is_last_use()) {
1600 out->print("(last_use)");
1601 }
1602 out->print("]");
1603 }
1604
1605
1606 // LIR_Address
1607 void LIR_Const::print_value_on(outputStream* out) const {
1608 switch (type()) {
1609 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1610 case T_INT: out->print("int:%d", as_jint()); break;
1611 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1612 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1613 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1614 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break;
1615 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break;
1616 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
1617 }
1618 }
1619
1620 // LIR_Address
1621 void LIR_Address::print_value_on(outputStream* out) const {
1622 out->print("Base:"); _base->print(out);
1623 if (!_index->is_illegal()) {
1624 out->print(" Index:"); _index->print(out);
1625 switch (scale()) {
1626 case times_1: break;
1627 case times_2: out->print(" * 2"); break;
1628 case times_4: out->print(" * 4"); break;
1629 case times_8: out->print(" * 8"); break;
1630 }
1631 }
1632 out->print(" Disp: " INTX_FORMAT, _disp);
1633 }
1634
1635 // debug output of block header without InstructionPrinter
1636 // (because phi functions are not necessary for LIR)
1637 static void print_block(BlockBegin* x) {
1638 // print block id
1639 BlockEnd* end = x->end();
1640 tty->print("B%d ", x->block_id());
1641
1642 // print flags
1643 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1644 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1645 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1646 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1647 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1648 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1649 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1650
1651 // print block bci range
1652 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1653
1654 // print predecessors and successors
1655 if (x->number_of_preds() > 0) {
1656 tty->print("preds: ");
1657 for (int i = 0; i < x->number_of_preds(); i ++) {
1658 tty->print("B%d ", x->pred_at(i)->block_id());
1659 }
1660 }
1661
1662 if (x->number_of_sux() > 0) {
1663 tty->print("sux: ");
1664 for (int i = 0; i < x->number_of_sux(); i ++) {
1665 tty->print("B%d ", x->sux_at(i)->block_id());
1666 }
1667 }
1668
1669 // print exception handlers
1670 if (x->number_of_exception_handlers() > 0) {
1671 tty->print("xhandler: ");
1672 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1673 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1674 }
1675 }
1676
1677 tty->cr();
1678 }
1679
1680 void print_LIR(BlockList* blocks) {
1681 tty->print_cr("LIR:");
1682 int i;
1683 for (i = 0; i < blocks->length(); i++) {
1684 BlockBegin* bb = blocks->at(i);
1685 print_block(bb);
1686 tty->print("__id_Instruction___________________________________________"); tty->cr();
1687 bb->lir()->print_instructions();
1688 }
1689 }
1690
1691 void LIR_List::print_instructions() {
1692 for (int i = 0; i < _operations.length(); i++) {
1693 _operations.at(i)->print(); tty->cr();
1694 }
1695 tty->cr();
1696 }
1697
1698 // LIR_Ops printing routines
1699 // LIR_Op
1700 void LIR_Op::print_on(outputStream* out) const {
1701 if (id() != -1 || PrintCFGToFile) {
1702 out->print("%4d ", id());
1703 } else {
1704 out->print(" ");
1705 }
1706 out->print("%s ", name());
1707 print_instr(out);
1708 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1709 #ifdef ASSERT
1710 if (Verbose && _file != NULL) {
1711 out->print(" (%s:%d)", _file, _line);
1712 }
1713 #endif
1714 }
1715
1716 const char * LIR_Op::name() const {
1717 const char* s = NULL;
1718 switch(code()) {
1719 // LIR_Op0
1720 case lir_membar: s = "membar"; break;
1721 case lir_membar_acquire: s = "membar_acquire"; break;
1722 case lir_membar_release: s = "membar_release"; break;
1723 case lir_membar_loadload: s = "membar_loadload"; break;
1724 case lir_membar_storestore: s = "membar_storestore"; break;
1725 case lir_membar_loadstore: s = "membar_loadstore"; break;
1726 case lir_membar_storeload: s = "membar_storeload"; break;
1727 case lir_word_align: s = "word_align"; break;
1728 case lir_label: s = "label"; break;
1729 case lir_nop: s = "nop"; break;
1730 case lir_backwardbranch_target: s = "backbranch"; break;
1731 case lir_std_entry: s = "std_entry"; break;
1732 case lir_osr_entry: s = "osr_entry"; break;
1733 case lir_build_frame: s = "build_frm"; break;
1734 case lir_fpop_raw: s = "fpop_raw"; break;
1735 case lir_24bit_FPU: s = "24bit_FPU"; break;
1736 case lir_reset_FPU: s = "reset_FPU"; break;
1737 case lir_breakpoint: s = "breakpoint"; break;
1738 case lir_get_thread: s = "get_thread"; break;
1739 // LIR_Op1
1740 case lir_fxch: s = "fxch"; break;
1741 case lir_fld: s = "fld"; break;
1742 case lir_ffree: s = "ffree"; break;
1743 case lir_push: s = "push"; break;
1744 case lir_pop: s = "pop"; break;
1745 case lir_null_check: s = "null_check"; break;
1746 case lir_return: s = "return"; break;
1747 case lir_safepoint: s = "safepoint"; break;
1748 case lir_neg: s = "neg"; break;
1749 case lir_leal: s = "leal"; break;
1750 case lir_branch: s = "branch"; break;
1751 case lir_cond_float_branch: s = "flt_cond_br"; break;
1752 case lir_move: s = "move"; break;
1753 case lir_roundfp: s = "roundfp"; break;
1754 case lir_rtcall: s = "rtcall"; break;
1755 case lir_throw: s = "throw"; break;
1756 case lir_unwind: s = "unwind"; break;
1757 case lir_convert: s = "convert"; break;
1758 case lir_alloc_object: s = "alloc_obj"; break;
1759 case lir_monaddr: s = "mon_addr"; break;
1760 case lir_pack64: s = "pack64"; break;
1761 case lir_unpack64: s = "unpack64"; break;
1762 // LIR_Op2
1763 case lir_cmp: s = "cmp"; break;
1764 case lir_cmp_l2i: s = "cmp_l2i"; break;
1765 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1766 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1767 case lir_cmove: s = "cmove"; break;
1768 case lir_add: s = "add"; break;
1769 case lir_sub: s = "sub"; break;
1770 case lir_mul: s = "mul"; break;
1771 case lir_mul_strictfp: s = "mul_strictfp"; break;
1772 case lir_div: s = "div"; break;
1773 case lir_div_strictfp: s = "div_strictfp"; break;
1774 case lir_rem: s = "rem"; break;
1775 case lir_abs: s = "abs"; break;
1776 case lir_sqrt: s = "sqrt"; break;
1777 case lir_sin: s = "sin"; break;
1778 case lir_cos: s = "cos"; break;
1779 case lir_tan: s = "tan"; break;
1780 case lir_log: s = "log"; break;
1781 case lir_log10: s = "log10"; break;
1782 case lir_exp: s = "exp"; break;
1783 case lir_pow: s = "pow"; break;
1784 case lir_logic_and: s = "logic_and"; break;
1785 case lir_logic_or: s = "logic_or"; break;
1786 case lir_logic_xor: s = "logic_xor"; break;
1787 case lir_shl: s = "shift_left"; break;
1788 case lir_shr: s = "shift_right"; break;
1789 case lir_ushr: s = "ushift_right"; break;
1790 case lir_alloc_array: s = "alloc_array"; break;
1791 case lir_xadd: s = "xadd"; break;
1792 case lir_xchg: s = "xchg"; break;
1793 // LIR_Op3
1794 case lir_idiv: s = "idiv"; break;
1795 case lir_irem: s = "irem"; break;
1796 // LIR_OpJavaCall
1797 case lir_static_call: s = "static"; break;
1798 case lir_optvirtual_call: s = "optvirtual"; break;
1799 case lir_icvirtual_call: s = "icvirtual"; break;
1800 case lir_virtual_call: s = "virtual"; break;
1801 case lir_dynamic_call: s = "dynamic"; break;
1802 // LIR_OpArrayCopy
1803 case lir_arraycopy: s = "arraycopy"; break;
1804 // LIR_OpUpdateCRC32
1805 case lir_updatecrc32: s = "updatecrc32"; break;
1806 // LIR_OpLock
1807 case lir_lock: s = "lock"; break;
1808 case lir_unlock: s = "unlock"; break;
1809 // LIR_OpDelay
1810 case lir_delay_slot: s = "delay"; break;
1811 // LIR_OpTypeCheck
1812 case lir_instanceof: s = "instanceof"; break;
1813 case lir_checkcast: s = "checkcast"; break;
1814 case lir_store_check: s = "store_check"; break;
1815 // LIR_OpCompareAndSwap
1816 case lir_cas_long: s = "cas_long"; break;
1817 case lir_cas_obj: s = "cas_obj"; break;
1818 case lir_cas_int: s = "cas_int"; break;
1819 // LIR_OpProfileCall
1820 case lir_profile_call: s = "profile_call"; break;
1821 // LIR_OpProfileType
1822 case lir_profile_type: s = "profile_type"; break;
1823 // LIR_OpAssert
1824 #ifdef ASSERT
1825 case lir_assert: s = "assert"; break;
1826 #endif
1827 case lir_none: ShouldNotReachHere();break;
1828 default: s = "illegal_op"; break;
1829 }
1830 return s;
1831 }
1832
1833 // LIR_OpJavaCall
1834 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1835 out->print("call: ");
1836 out->print("[addr: " INTPTR_FORMAT "]", p2i(address()));
1837 if (receiver()->is_valid()) {
1838 out->print(" [recv: "); receiver()->print(out); out->print("]");
1839 }
1840 if (result_opr()->is_valid()) {
1841 out->print(" [result: "); result_opr()->print(out); out->print("]");
1842 }
1843 }
1844
1845 // LIR_OpLabel
1846 void LIR_OpLabel::print_instr(outputStream* out) const {
1847 out->print("[label:" INTPTR_FORMAT "]", p2i(_label));
1848 }
1849
1850 // LIR_OpArrayCopy
1851 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1852 src()->print(out); out->print(" ");
1853 src_pos()->print(out); out->print(" ");
1854 dst()->print(out); out->print(" ");
1855 dst_pos()->print(out); out->print(" ");
1856 length()->print(out); out->print(" ");
1857 tmp()->print(out); out->print(" ");
1858 }
1859
1860 // LIR_OpUpdateCRC32
1861 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
1862 crc()->print(out); out->print(" ");
1863 val()->print(out); out->print(" ");
1864 result_opr()->print(out); out->print(" ");
1865 }
1866
1867 // LIR_OpCompareAndSwap
1868 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1869 addr()->print(out); out->print(" ");
1870 cmp_value()->print(out); out->print(" ");
1871 new_value()->print(out); out->print(" ");
1872 tmp1()->print(out); out->print(" ");
1873 tmp2()->print(out); out->print(" ");
1874
1875 }
1876
1877 // LIR_Op0
1878 void LIR_Op0::print_instr(outputStream* out) const {
1879 result_opr()->print(out);
1880 }
1881
1882 // LIR_Op1
1883 const char * LIR_Op1::name() const {
1884 if (code() == lir_move) {
1885 switch (move_kind()) {
1886 case lir_move_normal:
1887 return "move";
1888 case lir_move_unaligned:
1889 return "unaligned move";
1890 case lir_move_volatile:
1891 return "volatile_move";
1892 case lir_move_wide:
1893 return "wide_move";
1894 default:
1895 ShouldNotReachHere();
1896 return "illegal_op";
1897 }
1898 } else {
1899 return LIR_Op::name();
1900 }
1901 }
1902
1903
1904 void LIR_Op1::print_instr(outputStream* out) const {
1905 _opr->print(out); out->print(" ");
1906 result_opr()->print(out); out->print(" ");
1907 print_patch_code(out, patch_code());
1908 }
1909
1910
1911 // LIR_Op1
1912 void LIR_OpRTCall::print_instr(outputStream* out) const {
1913 intx a = (intx)addr();
1914 out->print("%s", Runtime1::name_for_address(addr()));
1915 out->print(" ");
1916 tmp()->print(out);
1917 }
1918
1919 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1920 switch(code) {
1921 case lir_patch_none: break;
1922 case lir_patch_low: out->print("[patch_low]"); break;
1923 case lir_patch_high: out->print("[patch_high]"); break;
1924 case lir_patch_normal: out->print("[patch_normal]"); break;
1925 default: ShouldNotReachHere();
1926 }
1927 }
1928
1929 // LIR_OpBranch
1930 void LIR_OpBranch::print_instr(outputStream* out) const {
1931 print_condition(out, cond()); out->print(" ");
1932 if (block() != NULL) {
1933 out->print("[B%d] ", block()->block_id());
1934 } else if (stub() != NULL) {
1935 out->print("[");
1936 stub()->print_name(out);
1937 out->print(": " INTPTR_FORMAT "]", p2i(stub()));
1938 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1939 } else {
1940 out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
1941 }
1942 if (ublock() != NULL) {
1943 out->print("unordered: [B%d] ", ublock()->block_id());
1944 }
1945 }
1946
1947 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1948 switch(cond) {
1949 case lir_cond_equal: out->print("[EQ]"); break;
1950 case lir_cond_notEqual: out->print("[NE]"); break;
1951 case lir_cond_less: out->print("[LT]"); break;
1952 case lir_cond_lessEqual: out->print("[LE]"); break;
1953 case lir_cond_greaterEqual: out->print("[GE]"); break;
1954 case lir_cond_greater: out->print("[GT]"); break;
1955 case lir_cond_belowEqual: out->print("[BE]"); break;
1956 case lir_cond_aboveEqual: out->print("[AE]"); break;
1957 case lir_cond_always: out->print("[AL]"); break;
1958 default: out->print("[%d]",cond); break;
1959 }
1960 }
1961
1962 // LIR_OpConvert
1963 void LIR_OpConvert::print_instr(outputStream* out) const {
1964 print_bytecode(out, bytecode());
1965 in_opr()->print(out); out->print(" ");
1966 result_opr()->print(out); out->print(" ");
1967 #ifdef PPC
1968 if(tmp1()->is_valid()) {
1969 tmp1()->print(out); out->print(" ");
1970 tmp2()->print(out); out->print(" ");
1971 }
1972 #endif
1973 }
1974
1975 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1976 switch(code) {
1977 case Bytecodes::_d2f: out->print("[d2f] "); break;
1978 case Bytecodes::_d2i: out->print("[d2i] "); break;
1979 case Bytecodes::_d2l: out->print("[d2l] "); break;
1980 case Bytecodes::_f2d: out->print("[f2d] "); break;
1981 case Bytecodes::_f2i: out->print("[f2i] "); break;
1982 case Bytecodes::_f2l: out->print("[f2l] "); break;
1983 case Bytecodes::_i2b: out->print("[i2b] "); break;
1984 case Bytecodes::_i2c: out->print("[i2c] "); break;
1985 case Bytecodes::_i2d: out->print("[i2d] "); break;
1986 case Bytecodes::_i2f: out->print("[i2f] "); break;
1987 case Bytecodes::_i2l: out->print("[i2l] "); break;
1988 case Bytecodes::_i2s: out->print("[i2s] "); break;
1989 case Bytecodes::_l2i: out->print("[l2i] "); break;
1990 case Bytecodes::_l2f: out->print("[l2f] "); break;
1991 case Bytecodes::_l2d: out->print("[l2d] "); break;
1992 default:
1993 out->print("[?%d]",code);
1994 break;
1995 }
1996 }
1997
1998 void LIR_OpAllocObj::print_instr(outputStream* out) const {
1999 klass()->print(out); out->print(" ");
2000 obj()->print(out); out->print(" ");
2001 tmp1()->print(out); out->print(" ");
2002 tmp2()->print(out); out->print(" ");
2003 tmp3()->print(out); out->print(" ");
2004 tmp4()->print(out); out->print(" ");
2005 out->print("[hdr:%d]", header_size()); out->print(" ");
2006 out->print("[obj:%d]", object_size()); out->print(" ");
2007 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2008 }
2009
2010 void LIR_OpRoundFP::print_instr(outputStream* out) const {
2011 _opr->print(out); out->print(" ");
2012 tmp()->print(out); out->print(" ");
2013 result_opr()->print(out); out->print(" ");
2014 }
2015
2016 // LIR_Op2
2017 void LIR_Op2::print_instr(outputStream* out) const {
2018 if (code() == lir_cmove) {
2019 print_condition(out, condition()); out->print(" ");
2020 }
2021 in_opr1()->print(out); out->print(" ");
2022 in_opr2()->print(out); out->print(" ");
2023 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2024 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2025 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2026 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
2027 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
2028 result_opr()->print(out);
2029 }
2030
2031 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2032 klass()->print(out); out->print(" ");
2033 len()->print(out); out->print(" ");
2034 obj()->print(out); out->print(" ");
2035 tmp1()->print(out); out->print(" ");
2036 tmp2()->print(out); out->print(" ");
2037 tmp3()->print(out); out->print(" ");
2038 tmp4()->print(out); out->print(" ");
2039 out->print("[type:0x%x]", type()); out->print(" ");
2040 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2041 }
2042
2043
2044 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
2045 object()->print(out); out->print(" ");
2046 if (code() == lir_store_check) {
2047 array()->print(out); out->print(" ");
2048 }
2049 if (code() != lir_store_check) {
2050 klass()->print_name_on(out); out->print(" ");
2051 if (fast_check()) out->print("fast_check ");
2052 }
2053 tmp1()->print(out); out->print(" ");
2054 tmp2()->print(out); out->print(" ");
2055 tmp3()->print(out); out->print(" ");
2056 result_opr()->print(out); out->print(" ");
2057 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2058 }
2059
2060
2061 // LIR_Op3
2062 void LIR_Op3::print_instr(outputStream* out) const {
2063 in_opr1()->print(out); out->print(" ");
2064 in_opr2()->print(out); out->print(" ");
2065 in_opr3()->print(out); out->print(" ");
2066 result_opr()->print(out);
2067 }
2068
2069
2070 void LIR_OpLock::print_instr(outputStream* out) const {
2071 hdr_opr()->print(out); out->print(" ");
2072 obj_opr()->print(out); out->print(" ");
2073 lock_opr()->print(out); out->print(" ");
2074 if (_scratch->is_valid()) {
2075 _scratch->print(out); out->print(" ");
2076 }
2077 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2078 }
2079
2080 #ifdef ASSERT
2081 void LIR_OpAssert::print_instr(outputStream* out) const {
2082 print_condition(out, condition()); out->print(" ");
2083 in_opr1()->print(out); out->print(" ");
2084 in_opr2()->print(out); out->print(", \"");
2085 out->print("%s", msg()); out->print("\"");
2086 }
2087 #endif
2088
2089
2090 void LIR_OpDelay::print_instr(outputStream* out) const {
2091 _op->print_on(out);
2092 }
2093
2094
2095 // LIR_OpProfileCall
2096 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2097 profiled_method()->name()->print_symbol_on(out);
2098 out->print(".");
2099 profiled_method()->holder()->name()->print_symbol_on(out);
2100 out->print(" @ %d ", profiled_bci());
2101 mdo()->print(out); out->print(" ");
2102 recv()->print(out); out->print(" ");
2103 tmp1()->print(out); out->print(" ");
2104 }
2105
2106 // LIR_OpProfileType
2107 void LIR_OpProfileType::print_instr(outputStream* out) const {
2108 out->print("exact = "); exact_klass()->print_name_on(out);
2109 out->print("current = "); ciTypeEntries::print_ciklass(out, current_klass());
2110 mdp()->print(out); out->print(" ");
2111 obj()->print(out); out->print(" ");
2112 tmp()->print(out); out->print(" ");
2113 }
2114
2115 #endif // PRODUCT
2116
2117 // Implementation of LIR_InsertionBuffer
2118
2119 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2120 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2121
2122 int i = number_of_insertion_points() - 1;
2123 if (i < 0 || index_at(i) < index) {
2124 append_new(index, 1);
2125 } else {
2126 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2127 assert(count_at(i) > 0, "check");
2128 set_count_at(i, count_at(i) + 1);
2129 }
2130 _ops.push(op);
2131
2132 DEBUG_ONLY(verify());
2133 }
2134
2135 #ifdef ASSERT
2136 void LIR_InsertionBuffer::verify() {
2137 int sum = 0;
2138 int prev_idx = -1;
2139
2140 for (int i = 0; i < number_of_insertion_points(); i++) {
2141 assert(prev_idx < index_at(i), "index must be ordered ascending");
2142 sum += count_at(i);
2143 }
2144 assert(sum == number_of_ops(), "wrong total sum");
2145 }
2146 #endif