1 /* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "asm/macroAssembler.hpp" 28 #include "asm/macroAssembler.inline.hpp" 29 #include "memory/resourceArea.hpp" 30 #include "runtime/java.hpp" 31 #include "runtime/stubCodeGenerator.hpp" 32 #include "utilities/macros.hpp" 33 #include "vm_version_aarch64.hpp" 34 35 #include OS_HEADER_INLINE(os) 36 37 #ifndef BUILTIN_SIM 38 #include <sys/auxv.h> 39 #include <asm/hwcap.h> 40 #else 41 #define getauxval(hwcap) 0 42 #endif 43 44 #ifndef HWCAP_AES 45 #define HWCAP_AES (1<<3) 46 #endif 47 48 #ifndef HWCAP_PMULL 49 #define HWCAP_PMULL (1<<4) 50 #endif 51 52 #ifndef HWCAP_SHA1 53 #define HWCAP_SHA1 (1<<5) 54 #endif 55 56 #ifndef HWCAP_SHA2 57 #define HWCAP_SHA2 (1<<6) 58 #endif 59 60 #ifndef HWCAP_CRC32 61 #define HWCAP_CRC32 (1<<7) 62 #endif 63 64 #ifndef HWCAP_ATOMICS 65 #define HWCAP_ATOMICS (1<<8) 66 #endif 67 68 int VM_Version::_cpu; 69 int VM_Version::_model; 70 int VM_Version::_model2; 71 int VM_Version::_variant; 72 int VM_Version::_revision; 73 int VM_Version::_stepping; 74 VM_Version::PsrInfo VM_Version::_psr_info = { 0, }; 75 76 static BufferBlob* stub_blob; 77 static const int stub_size = 550; 78 79 extern "C" { 80 typedef void (*getPsrInfo_stub_t)(void*); 81 } 82 static getPsrInfo_stub_t getPsrInfo_stub = NULL; 83 84 85 class VM_Version_StubGenerator: public StubCodeGenerator { 86 public: 87 88 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} 89 90 address generate_getPsrInfo() { 91 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub"); 92 # define __ _masm-> 93 address start = __ pc(); 94 95 #ifdef BUILTIN_SIM 96 __ c_stub_prolog(1, 0, MacroAssembler::ret_type_void); 97 #endif 98 99 // void getPsrInfo(VM_Version::PsrInfo* psr_info); 100 101 address entry = __ pc(); 102 103 __ enter(); 104 105 __ get_dczid_el0(rscratch1); 106 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset()))); 107 108 __ get_ctr_el0(rscratch1); 109 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset()))); 110 111 __ leave(); 112 __ ret(lr); 113 114 # undef __ 115 116 return start; 117 } 118 }; 119 120 121 void VM_Version::get_processor_features() { 122 _supports_cx8 = true; 123 _supports_atomic_getset4 = true; 124 _supports_atomic_getadd4 = true; 125 _supports_atomic_getset8 = true; 126 _supports_atomic_getadd8 = true; 127 128 getPsrInfo_stub(&_psr_info); 129 130 int dcache_line = VM_Version::dcache_line_size(); 131 132 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) 133 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 3*dcache_line); 134 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize)) 135 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line); 136 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) 137 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line); 138 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) 139 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line); 140 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) 141 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line); 142 143 if (PrefetchCopyIntervalInBytes != -1 && 144 ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) { 145 warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768"); 146 PrefetchCopyIntervalInBytes &= ~7; 147 if (PrefetchCopyIntervalInBytes >= 32768) 148 PrefetchCopyIntervalInBytes = 32760; 149 } 150 151 if (SoftwarePrefetchHintDistance != -1 && 152 (SoftwarePrefetchHintDistance & 7)) { 153 warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8"); 154 SoftwarePrefetchHintDistance &= ~7; 155 } 156 157 unsigned long auxv = getauxval(AT_HWCAP); 158 159 char buf[512]; 160 161 _features = auxv; 162 163 int cpu_lines = 0; 164 if (FILE *f = fopen("/proc/cpuinfo", "r")) { 165 char buf[128], *p; 166 while (fgets(buf, sizeof (buf), f) != NULL) { 167 if (p = strchr(buf, ':')) { 168 long v = strtol(p+1, NULL, 0); 169 if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) { 170 _cpu = v; 171 cpu_lines++; 172 } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) { 173 _variant = v; 174 } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) { 175 if (_model != v) _model2 = _model; 176 _model = v; 177 } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) { 178 _revision = v; 179 } 180 } 181 } 182 fclose(f); 183 } 184 185 // Enable vendor specific features 186 if (_cpu == CPU_CAVIUM) { 187 if (_variant == 0) _features |= CPU_DMB_ATOMICS; 188 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) { 189 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true); 190 } 191 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) { 192 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0)); 193 } 194 } 195 if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) _features |= CPU_A53MAC; 196 if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH; 197 // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07) 198 // we assume the worst and assume we could be on a big little system and have 199 // undisclosed A53 cores which we could be swapped to at any stage 200 if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC; 201 202 sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision); 203 if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2); 204 if (auxv & HWCAP_ASIMD) strcat(buf, ", simd"); 205 if (auxv & HWCAP_CRC32) strcat(buf, ", crc"); 206 if (auxv & HWCAP_AES) strcat(buf, ", aes"); 207 if (auxv & HWCAP_SHA1) strcat(buf, ", sha1"); 208 if (auxv & HWCAP_SHA2) strcat(buf, ", sha256"); 209 if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse"); 210 211 _features_string = os::strdup(buf); 212 213 if (FLAG_IS_DEFAULT(UseCRC32)) { 214 UseCRC32 = (auxv & HWCAP_CRC32) != 0; 215 } 216 if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) { 217 warning("UseCRC32 specified, but not supported on this CPU"); 218 } 219 220 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) { 221 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true); 222 } 223 224 if (UseVectorizedMismatchIntrinsic) { 225 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU."); 226 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); 227 } 228 229 if (auxv & HWCAP_ATOMICS) { 230 if (FLAG_IS_DEFAULT(UseLSE)) 231 FLAG_SET_DEFAULT(UseLSE, true); 232 } else { 233 if (UseLSE) { 234 warning("UseLSE specified, but not supported on this CPU"); 235 } 236 } 237 238 if (auxv & HWCAP_AES) { 239 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES); 240 UseAESIntrinsics = 241 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics)); 242 if (UseAESIntrinsics && !UseAES) { 243 warning("UseAESIntrinsics enabled, but UseAES not, enabling"); 244 UseAES = true; 245 } 246 } else { 247 if (UseAES) { 248 warning("UseAES specified, but not supported on this CPU"); 249 } 250 if (UseAESIntrinsics) { 251 warning("UseAESIntrinsics specified, but not supported on this CPU"); 252 } 253 } 254 255 if (UseAESCTRIntrinsics) { 256 warning("AES/CTR intrinsics are not available on this CPU"); 257 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 258 } 259 260 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 261 UseCRC32Intrinsics = true; 262 } 263 264 if (auxv & HWCAP_CRC32) { 265 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { 266 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true); 267 } 268 } else if (UseCRC32CIntrinsics) { 269 warning("CRC32C is not available on the CPU"); 270 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 271 } 272 273 if (FLAG_IS_DEFAULT(UseFMA)) { 274 FLAG_SET_DEFAULT(UseFMA, true); 275 } 276 277 if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) { 278 if (FLAG_IS_DEFAULT(UseSHA)) { 279 FLAG_SET_DEFAULT(UseSHA, true); 280 } 281 } else if (UseSHA) { 282 warning("SHA instructions are not available on this CPU"); 283 FLAG_SET_DEFAULT(UseSHA, false); 284 } 285 286 if (UseSHA && (auxv & HWCAP_SHA1)) { 287 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { 288 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); 289 } 290 } else if (UseSHA1Intrinsics) { 291 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU."); 292 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 293 } 294 295 if (UseSHA && (auxv & HWCAP_SHA2)) { 296 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { 297 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); 298 } 299 } else if (UseSHA256Intrinsics) { 300 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU."); 301 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 302 } 303 304 if (UseSHA512Intrinsics) { 305 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU."); 306 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 307 } 308 309 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { 310 FLAG_SET_DEFAULT(UseSHA, false); 311 } 312 313 if (auxv & HWCAP_PMULL) { 314 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { 315 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true); 316 } 317 } else if (UseGHASHIntrinsics) { 318 warning("GHASH intrinsics are not available on this CPU"); 319 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); 320 } 321 322 if (is_zva_enabled()) { 323 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { 324 FLAG_SET_DEFAULT(UseBlockZeroing, true); 325 } 326 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) { 327 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length()); 328 } 329 } else if (UseBlockZeroing) { 330 warning("DC ZVA is not available on this CPU"); 331 FLAG_SET_DEFAULT(UseBlockZeroing, false); 332 } 333 334 // This machine allows unaligned memory accesses 335 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { 336 FLAG_SET_DEFAULT(UseUnalignedAccesses, true); 337 } 338 339 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { 340 UseMultiplyToLenIntrinsic = true; 341 } 342 343 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) { 344 UseSquareToLenIntrinsic = true; 345 } 346 347 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) { 348 UseMulAddIntrinsic = true; 349 } 350 351 if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) { 352 UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0; 353 } 354 355 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { 356 UsePopCountInstruction = true; 357 } 358 359 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { 360 UseMontgomeryMultiplyIntrinsic = true; 361 } 362 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { 363 UseMontgomerySquareIntrinsic = true; 364 } 365 366 #ifdef COMPILER2 367 if (FLAG_IS_DEFAULT(OptoScheduling)) { 368 OptoScheduling = true; 369 } 370 #endif 371 } 372 373 void VM_Version::initialize() { 374 ResourceMark rm; 375 376 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size); 377 if (stub_blob == NULL) { 378 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub"); 379 } 380 381 CodeBuffer c(stub_blob); 382 VM_Version_StubGenerator g(&c); 383 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t, 384 g.generate_getPsrInfo()); 385 386 get_processor_features(); 387 }