1 /*
   2  * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2015, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.hpp"
  28 #include "asm/macroAssembler.inline.hpp"
  29 #include "memory/resourceArea.hpp"
  30 #include "runtime/java.hpp"
  31 #include "runtime/stubCodeGenerator.hpp"
  32 #include "utilities/macros.hpp"
  33 #include "vm_version_aarch64.hpp"
  34 
  35 #include OS_HEADER_INLINE(os)
  36 
  37 #ifndef BUILTIN_SIM
  38 #include <sys/auxv.h>
  39 #include <asm/hwcap.h>
  40 #else
  41 #define getauxval(hwcap) 0
  42 #endif
  43 
  44 #ifndef HWCAP_AES
  45 #define HWCAP_AES   (1<<3)
  46 #endif
  47 
  48 #ifndef HWCAP_PMULL
  49 #define HWCAP_PMULL (1<<4)
  50 #endif
  51 
  52 #ifndef HWCAP_SHA1
  53 #define HWCAP_SHA1  (1<<5)
  54 #endif
  55 
  56 #ifndef HWCAP_SHA2
  57 #define HWCAP_SHA2  (1<<6)
  58 #endif
  59 
  60 #ifndef HWCAP_CRC32
  61 #define HWCAP_CRC32 (1<<7)
  62 #endif
  63 
  64 #ifndef HWCAP_ATOMICS
  65 #define HWCAP_ATOMICS (1<<8)
  66 #endif
  67 
  68 int VM_Version::_cpu;
  69 int VM_Version::_model;
  70 int VM_Version::_model2;
  71 int VM_Version::_variant;
  72 int VM_Version::_revision;
  73 int VM_Version::_stepping;
  74 VM_Version::PsrInfo VM_Version::_psr_info   = { 0, };
  75 
  76 static BufferBlob* stub_blob;
  77 static const int stub_size = 550;
  78 
  79 extern "C" {
  80   typedef void (*getPsrInfo_stub_t)(void*);
  81 }
  82 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
  83 
  84 
  85 class VM_Version_StubGenerator: public StubCodeGenerator {
  86  public:
  87 
  88   VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
  89 
  90   address generate_getPsrInfo() {
  91     StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
  92 #   define __ _masm->
  93     address start = __ pc();
  94 
  95 #ifdef BUILTIN_SIM
  96     __ c_stub_prolog(1, 0, MacroAssembler::ret_type_void);
  97 #endif
  98 
  99     // void getPsrInfo(VM_Version::PsrInfo* psr_info);
 100 
 101     address entry = __ pc();
 102 
 103     __ enter();
 104 
 105     __ get_dczid_el0(rscratch1);
 106     __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset())));
 107 
 108     __ get_ctr_el0(rscratch1);
 109     __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset())));
 110 
 111     __ leave();
 112     __ ret(lr);
 113 
 114 #   undef __
 115 
 116     return start;
 117   }
 118 };
 119 
 120 
 121 void VM_Version::get_processor_features() {
 122   _supports_cx8 = true;
 123   _supports_atomic_getset4 = true;
 124   _supports_atomic_getadd4 = true;
 125   _supports_atomic_getset8 = true;
 126   _supports_atomic_getadd8 = true;
 127 
 128   getPsrInfo_stub(&_psr_info);
 129 
 130   int dcache_line = VM_Version::dcache_line_size();
 131 
 132   if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
 133     FLAG_SET_DEFAULT(AllocatePrefetchDistance, 3*dcache_line);
 134   if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
 135     FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
 136   if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
 137     FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
 138   if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
 139     FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
 140   if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
 141     FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
 142 
 143   if (PrefetchCopyIntervalInBytes != -1 &&
 144        ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
 145     warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
 146     PrefetchCopyIntervalInBytes &= ~7;
 147     if (PrefetchCopyIntervalInBytes >= 32768)
 148       PrefetchCopyIntervalInBytes = 32760;
 149   }
 150 
 151   if (SoftwarePrefetchHintDistance != -1 &&
 152        (SoftwarePrefetchHintDistance & 7)) {
 153     warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
 154     SoftwarePrefetchHintDistance &= ~7;
 155   }
 156 
 157   unsigned long auxv = getauxval(AT_HWCAP);
 158 
 159   char buf[512];
 160 
 161   _features = auxv;
 162 
 163   int cpu_lines = 0;
 164   if (FILE *f = fopen("/proc/cpuinfo", "r")) {
 165     char buf[128], *p;
 166     while (fgets(buf, sizeof (buf), f) != NULL) {
 167       if (p = strchr(buf, ':')) {
 168         long v = strtol(p+1, NULL, 0);
 169         if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
 170           _cpu = v;
 171           cpu_lines++;
 172         } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
 173           _variant = v;
 174         } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
 175           if (_model != v)  _model2 = _model;
 176           _model = v;
 177         } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
 178           _revision = v;
 179         }
 180       }
 181     }
 182     fclose(f);
 183   }
 184 
 185   // Enable vendor specific features
 186   if (_cpu == CPU_CAVIUM) {
 187     if (_variant == 0) _features |= CPU_DMB_ATOMICS;
 188     if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
 189       FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
 190     }
 191     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
 192       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
 193     }
 194     if ((_model == 0x0a1 || _model2 == 0x0a1) && FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
 195         UseSIMDForArrayEquals = false; // ThunderX T88 is slow with SIMD
 196     }
 197   }
 198   if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) _features |= CPU_A53MAC;
 199   if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH;
 200   // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
 201   // we assume the worst and assume we could be on a big little system and have
 202   // undisclosed A53 cores which we could be swapped to at any stage
 203   if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
 204 
 205   sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
 206   if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
 207   if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
 208   if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
 209   if (auxv & HWCAP_AES)   strcat(buf, ", aes");
 210   if (auxv & HWCAP_SHA1)  strcat(buf, ", sha1");
 211   if (auxv & HWCAP_SHA2)  strcat(buf, ", sha256");
 212   if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse");
 213 
 214   _features_string = os::strdup(buf);
 215 
 216   if (FLAG_IS_DEFAULT(UseCRC32)) {
 217     UseCRC32 = (auxv & HWCAP_CRC32) != 0;
 218   }
 219   if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
 220     warning("UseCRC32 specified, but not supported on this CPU");
 221   }
 222 
 223   if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
 224     FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
 225   }
 226 
 227   if (UseVectorizedMismatchIntrinsic) {
 228     warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
 229     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
 230   }
 231 
 232   if (auxv & HWCAP_ATOMICS) {
 233     if (FLAG_IS_DEFAULT(UseLSE))
 234       FLAG_SET_DEFAULT(UseLSE, true);
 235   } else {
 236     if (UseLSE) {
 237       warning("UseLSE specified, but not supported on this CPU");
 238     }
 239   }
 240 
 241   if (auxv & HWCAP_AES) {
 242     UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
 243     UseAESIntrinsics =
 244         UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
 245     if (UseAESIntrinsics && !UseAES) {
 246       warning("UseAESIntrinsics enabled, but UseAES not, enabling");
 247       UseAES = true;
 248     }
 249   } else {
 250     if (UseAES) {
 251       warning("UseAES specified, but not supported on this CPU");
 252     }
 253     if (UseAESIntrinsics) {
 254       warning("UseAESIntrinsics specified, but not supported on this CPU");
 255     }
 256   }
 257 
 258   if (UseAESCTRIntrinsics) {
 259     warning("AES/CTR intrinsics are not available on this CPU");
 260     FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 261   }
 262 
 263   if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 264     UseCRC32Intrinsics = true;
 265   }
 266 
 267   if (auxv & HWCAP_CRC32) {
 268     if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 269       FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
 270     }
 271   } else if (UseCRC32CIntrinsics) {
 272     warning("CRC32C is not available on the CPU");
 273     FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
 274   }
 275 
 276   if (FLAG_IS_DEFAULT(UseFMA)) {
 277     FLAG_SET_DEFAULT(UseFMA, true);
 278   }
 279 
 280   if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
 281     if (FLAG_IS_DEFAULT(UseSHA)) {
 282       FLAG_SET_DEFAULT(UseSHA, true);
 283     }
 284   } else if (UseSHA) {
 285     warning("SHA instructions are not available on this CPU");
 286     FLAG_SET_DEFAULT(UseSHA, false);
 287   }
 288 
 289   if (UseSHA && (auxv & HWCAP_SHA1)) {
 290     if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
 291       FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
 292     }
 293   } else if (UseSHA1Intrinsics) {
 294     warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
 295     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 296   }
 297 
 298   if (UseSHA && (auxv & HWCAP_SHA2)) {
 299     if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
 300       FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
 301     }
 302   } else if (UseSHA256Intrinsics) {
 303     warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
 304     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 305   }
 306 
 307   if (UseSHA512Intrinsics) {
 308     warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
 309     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 310   }
 311 
 312   if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
 313     FLAG_SET_DEFAULT(UseSHA, false);
 314   }
 315 
 316   if (auxv & HWCAP_PMULL) {
 317     if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
 318       FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
 319     }
 320   } else if (UseGHASHIntrinsics) {
 321     warning("GHASH intrinsics are not available on this CPU");
 322     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
 323   }
 324 
 325   if (is_zva_enabled()) {
 326     if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
 327       FLAG_SET_DEFAULT(UseBlockZeroing, true);
 328     }
 329     if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
 330       FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
 331     }
 332   } else if (UseBlockZeroing) {
 333     warning("DC ZVA is not available on this CPU");
 334     FLAG_SET_DEFAULT(UseBlockZeroing, false);
 335   }
 336 
 337   // This machine allows unaligned memory accesses
 338   if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
 339     FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
 340   }
 341 
 342   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
 343     UseMultiplyToLenIntrinsic = true;
 344   }
 345 
 346   if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
 347     UseSquareToLenIntrinsic = true;
 348   }
 349 
 350   if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
 351     UseMulAddIntrinsic = true;
 352   }
 353 
 354   if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) {
 355     UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0;
 356   }
 357 
 358   if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
 359     UsePopCountInstruction = true;
 360   }
 361 
 362   if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
 363     UseMontgomeryMultiplyIntrinsic = true;
 364   }
 365   if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
 366     UseMontgomerySquareIntrinsic = true;
 367   }
 368 
 369 #ifdef COMPILER2
 370   if (FLAG_IS_DEFAULT(OptoScheduling)) {
 371     OptoScheduling = true;
 372   }
 373 #endif
 374 }
 375 
 376 void VM_Version::initialize() {
 377   ResourceMark rm;
 378 
 379   stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
 380   if (stub_blob == NULL) {
 381     vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
 382   }
 383 
 384   CodeBuffer c(stub_blob);
 385   VM_Version_StubGenerator g(&c);
 386   getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
 387                                    g.generate_getPsrInfo());
 388 
 389   get_processor_features();
 390 }