1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30 #include "oops/compressedOops.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39
40 public:
41 using Assembler::mov;
42 using Assembler::movi;
43
44 protected:
45
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51 virtual void call_VM_leaf_base(
52 address entry_point, // the entry point
53 int number_of_arguments, // the number of arguments to pop after the call
54 Label *retaddr = NULL
55 );
56
57 virtual void call_VM_leaf_base(
58 address entry_point, // the entry point
59 int number_of_arguments, // the number of arguments to pop after the call
60 Label &retaddr) {
61 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
62 }
63
64 // This is the base routine called by the different versions of call_VM. The interpreter
65 // may customize this version by overriding it for its purposes (e.g., to save/restore
66 // additional registers when doing a VM call).
67 //
68 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
69 // returns the register which contains the thread upon return. If a thread register has been
70 // specified, the return value will correspond to that register. If no last_java_sp is specified
71 // (noreg) than rsp will be used instead.
72 virtual void call_VM_base( // returns the register containing the thread upon return
73 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
74 Register java_thread, // the thread if computed before ; use noreg otherwise
75 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
76 address entry_point, // the entry point
77 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
78 bool check_exceptions // whether to check for pending exceptions after return
79 );
80
81 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
82
83 // True if an XOR can be used to expand narrow klass references.
84 bool use_XOR_for_compressed_class_base;
85
86 public:
87 MacroAssembler(CodeBuffer* code) : Assembler(code) {
88 use_XOR_for_compressed_class_base
89 = operand_valid_for_logical_immediate
90 (/*is32*/false, (uint64_t)CompressedKlassPointers::base())
91 && ((uint64_t)CompressedKlassPointers::base()
92 > (1UL << log2_intptr(CompressedKlassPointers::range())));
93 }
94
95 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
96 // The implementation is only non-empty for the InterpreterMacroAssembler,
97 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
98 virtual void check_and_handle_popframe(Register java_thread);
99 virtual void check_and_handle_earlyret(Register java_thread);
100
101 void safepoint_poll(Label& slow_path);
102 void safepoint_poll_acquire(Label& slow_path);
103
104 // Biased locking support
105 // lock_reg and obj_reg must be loaded up with the appropriate values.
106 // swap_reg is killed.
107 // tmp_reg must be supplied and must not be rscratch1 or rscratch2
108 // Optional slow case is for implementations (interpreter and C1) which branch to
109 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
110 // Returns offset of first potentially-faulting instruction for null
111 // check info (currently consumed only by C1). If
112 // swap_reg_contains_mark is true then returns -1 as it is assumed
113 // the calling code has already passed any potential faults.
114 int biased_locking_enter(Register lock_reg, Register obj_reg,
115 Register swap_reg, Register tmp_reg,
116 bool swap_reg_contains_mark,
117 Label& done, Label* slow_case = NULL,
118 BiasedLockingCounters* counters = NULL);
119 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
120
121
122 // Helper functions for statistics gathering.
123 // Unconditional atomic increment.
124 void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
125 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
126 lea(tmp1, counter_addr);
127 atomic_incw(tmp1, tmp2, tmp3);
128 }
129 // Load Effective Address
130 void lea(Register r, const Address &a) {
131 InstructionMark im(this);
132 code_section()->relocate(inst_mark(), a.rspec());
133 a.lea(this, r);
134 }
135
136 void addmw(Address a, Register incr, Register scratch) {
137 ldrw(scratch, a);
138 addw(scratch, scratch, incr);
139 strw(scratch, a);
140 }
141
142 // Add constant to memory word
143 void addmw(Address a, int imm, Register scratch) {
144 ldrw(scratch, a);
145 if (imm > 0)
146 addw(scratch, scratch, (unsigned)imm);
147 else
148 subw(scratch, scratch, (unsigned)-imm);
149 strw(scratch, a);
150 }
151
152 void bind(Label& L) {
153 Assembler::bind(L);
154 code()->clear_last_insn();
155 }
156
157 void membar(Membar_mask_bits order_constraint);
158
159 using Assembler::ldr;
160 using Assembler::str;
161
162 void ldr(Register Rx, const Address &adr);
163 void ldrw(Register Rw, const Address &adr);
164 void str(Register Rx, const Address &adr);
165 void strw(Register Rx, const Address &adr);
166
167 // Frame creation and destruction shared between JITs.
168 void build_frame(int framesize);
169 void remove_frame(int framesize);
170
171 virtual void _call_Unimplemented(address call_site) {
172 mov(rscratch2, call_site);
173 haltsim();
174 }
175
176 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
177
178 virtual void notify(int type);
179
180 // aliases defined in AARCH64 spec
181
182 template<class T>
183 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
184
185 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
186 inline void cmp(Register Rd, unsigned imm) __attribute__ ((deprecated));
187
188 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
189 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
190
191 void cset(Register Rd, Assembler::Condition cond) {
192 csinc(Rd, zr, zr, ~cond);
193 }
194 void csetw(Register Rd, Assembler::Condition cond) {
195 csincw(Rd, zr, zr, ~cond);
196 }
197
198 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
199 csneg(Rd, Rn, Rn, ~cond);
200 }
201 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
202 csnegw(Rd, Rn, Rn, ~cond);
203 }
204
205 inline void movw(Register Rd, Register Rn) {
206 if (Rd == sp || Rn == sp) {
207 addw(Rd, Rn, 0U);
208 } else {
209 orrw(Rd, zr, Rn);
210 }
211 }
212 inline void mov(Register Rd, Register Rn) {
213 assert(Rd != r31_sp && Rn != r31_sp, "should be");
214 if (Rd == Rn) {
215 } else if (Rd == sp || Rn == sp) {
216 add(Rd, Rn, 0U);
217 } else {
218 orr(Rd, zr, Rn);
219 }
220 }
221
222 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
223 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
224
225 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
226 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
227
228 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
229 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
230
231 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
232 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
233 }
234 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
235 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
236 }
237
238 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
239 bfmw(Rd, Rn, lsb, (lsb + width - 1));
240 }
241 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
242 bfm(Rd, Rn, lsb , (lsb + width - 1));
243 }
244
245 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
246 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
247 }
248 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
249 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
250 }
251
252 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
253 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
254 }
255 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
256 sbfm(Rd, Rn, lsb , (lsb + width - 1));
257 }
258
259 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
260 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
261 }
262 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
263 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
264 }
265
266 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
267 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
268 }
269 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
270 ubfm(Rd, Rn, lsb , (lsb + width - 1));
271 }
272
273 inline void asrw(Register Rd, Register Rn, unsigned imm) {
274 sbfmw(Rd, Rn, imm, 31);
275 }
276
277 inline void asr(Register Rd, Register Rn, unsigned imm) {
278 sbfm(Rd, Rn, imm, 63);
279 }
280
281 inline void lslw(Register Rd, Register Rn, unsigned imm) {
282 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
283 }
284
285 inline void lsl(Register Rd, Register Rn, unsigned imm) {
286 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
287 }
288
289 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
290 ubfmw(Rd, Rn, imm, 31);
291 }
292
293 inline void lsr(Register Rd, Register Rn, unsigned imm) {
294 ubfm(Rd, Rn, imm, 63);
295 }
296
297 inline void rorw(Register Rd, Register Rn, unsigned imm) {
298 extrw(Rd, Rn, Rn, imm);
299 }
300
301 inline void ror(Register Rd, Register Rn, unsigned imm) {
302 extr(Rd, Rn, Rn, imm);
303 }
304
305 inline void sxtbw(Register Rd, Register Rn) {
306 sbfmw(Rd, Rn, 0, 7);
307 }
308 inline void sxthw(Register Rd, Register Rn) {
309 sbfmw(Rd, Rn, 0, 15);
310 }
311 inline void sxtb(Register Rd, Register Rn) {
312 sbfm(Rd, Rn, 0, 7);
313 }
314 inline void sxth(Register Rd, Register Rn) {
315 sbfm(Rd, Rn, 0, 15);
316 }
317 inline void sxtw(Register Rd, Register Rn) {
318 sbfm(Rd, Rn, 0, 31);
319 }
320
321 inline void uxtbw(Register Rd, Register Rn) {
322 ubfmw(Rd, Rn, 0, 7);
323 }
324 inline void uxthw(Register Rd, Register Rn) {
325 ubfmw(Rd, Rn, 0, 15);
326 }
327 inline void uxtb(Register Rd, Register Rn) {
328 ubfm(Rd, Rn, 0, 7);
329 }
330 inline void uxth(Register Rd, Register Rn) {
331 ubfm(Rd, Rn, 0, 15);
332 }
333 inline void uxtw(Register Rd, Register Rn) {
334 ubfm(Rd, Rn, 0, 31);
335 }
336
337 inline void cmnw(Register Rn, Register Rm) {
338 addsw(zr, Rn, Rm);
339 }
340 inline void cmn(Register Rn, Register Rm) {
341 adds(zr, Rn, Rm);
342 }
343
344 inline void cmpw(Register Rn, Register Rm) {
345 subsw(zr, Rn, Rm);
346 }
347 inline void cmp(Register Rn, Register Rm) {
348 subs(zr, Rn, Rm);
349 }
350
351 inline void negw(Register Rd, Register Rn) {
352 subw(Rd, zr, Rn);
353 }
354
355 inline void neg(Register Rd, Register Rn) {
356 sub(Rd, zr, Rn);
357 }
358
359 inline void negsw(Register Rd, Register Rn) {
360 subsw(Rd, zr, Rn);
361 }
362
363 inline void negs(Register Rd, Register Rn) {
364 subs(Rd, zr, Rn);
365 }
366
367 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
368 addsw(zr, Rn, Rm, kind, shift);
369 }
370 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
371 adds(zr, Rn, Rm, kind, shift);
372 }
373
374 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
375 subsw(zr, Rn, Rm, kind, shift);
376 }
377 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
378 subs(zr, Rn, Rm, kind, shift);
379 }
380
381 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
382 subw(Rd, zr, Rn, kind, shift);
383 }
384
385 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
386 sub(Rd, zr, Rn, kind, shift);
387 }
388
389 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
390 subsw(Rd, zr, Rn, kind, shift);
391 }
392
393 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
394 subs(Rd, zr, Rn, kind, shift);
395 }
396
397 inline void mnegw(Register Rd, Register Rn, Register Rm) {
398 msubw(Rd, Rn, Rm, zr);
399 }
400 inline void mneg(Register Rd, Register Rn, Register Rm) {
401 msub(Rd, Rn, Rm, zr);
402 }
403
404 inline void mulw(Register Rd, Register Rn, Register Rm) {
405 maddw(Rd, Rn, Rm, zr);
406 }
407 inline void mul(Register Rd, Register Rn, Register Rm) {
408 madd(Rd, Rn, Rm, zr);
409 }
410
411 inline void smnegl(Register Rd, Register Rn, Register Rm) {
412 smsubl(Rd, Rn, Rm, zr);
413 }
414 inline void smull(Register Rd, Register Rn, Register Rm) {
415 smaddl(Rd, Rn, Rm, zr);
416 }
417
418 inline void umnegl(Register Rd, Register Rn, Register Rm) {
419 umsubl(Rd, Rn, Rm, zr);
420 }
421 inline void umull(Register Rd, Register Rn, Register Rm) {
422 umaddl(Rd, Rn, Rm, zr);
423 }
424
425 #define WRAP(INSN) \
426 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
427 if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr) \
428 nop(); \
429 Assembler::INSN(Rd, Rn, Rm, Ra); \
430 }
431
432 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
433 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
434 #undef WRAP
435
436
437 // macro assembly operations needed for aarch64
438
439 // first two private routines for loading 32 bit or 64 bit constants
440 private:
441
442 void mov_immediate64(Register dst, u_int64_t imm64);
443 void mov_immediate32(Register dst, u_int32_t imm32);
444
445 int push(unsigned int bitset, Register stack);
446 int pop(unsigned int bitset, Register stack);
447
448 void mov(Register dst, Address a);
449
450 public:
451 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
452 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
453
454 // Push and pop everything that might be clobbered by a native
455 // runtime call except rscratch1 and rscratch2. (They are always
456 // scratch, so we don't have to protect them.) Only save the lower
457 // 64 bits of each vector register.
458 void push_call_clobbered_registers();
459 void pop_call_clobbered_registers();
460
461 // now mov instructions for loading absolute addresses and 32 or
462 // 64 bit integers
463
464 inline void mov(Register dst, address addr)
465 {
466 mov_immediate64(dst, (u_int64_t)addr);
467 }
468
469 inline void mov(Register dst, u_int64_t imm64)
470 {
471 mov_immediate64(dst, imm64);
472 }
473
474 inline void movw(Register dst, u_int32_t imm32)
475 {
476 mov_immediate32(dst, imm32);
477 }
478
479 inline void mov(Register dst, long l)
480 {
481 mov(dst, (u_int64_t)l);
482 }
483
484 inline void mov(Register dst, int i)
485 {
486 mov(dst, (long)i);
487 }
488
489 void mov(Register dst, RegisterOrConstant src) {
490 if (src.is_register())
491 mov(dst, src.as_register());
492 else
493 mov(dst, src.as_constant());
494 }
495
496 void movptr(Register r, uintptr_t imm64);
497
498 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
499
500 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
501 orr(Vd, T, Vn, Vn);
502 }
503
504 public:
505
506 // Generalized Test Bit And Branch, including a "far" variety which
507 // spans more than 32KiB.
508 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
509 assert(cond == EQ || cond == NE, "must be");
510
511 if (far)
512 cond = ~cond;
513
514 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
515 if (cond == Assembler::EQ)
516 branch = &Assembler::tbz;
517 else
518 branch = &Assembler::tbnz;
519
520 if (far) {
521 Label L;
522 (this->*branch)(Rt, bitpos, L);
523 b(dest);
524 bind(L);
525 } else {
526 (this->*branch)(Rt, bitpos, dest);
527 }
528 }
529
530 // macro instructions for accessing and updating floating point
531 // status register
532 //
533 // FPSR : op1 == 011
534 // CRn == 0100
535 // CRm == 0100
536 // op2 == 001
537
538 inline void get_fpsr(Register reg)
539 {
540 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
541 }
542
543 inline void set_fpsr(Register reg)
544 {
545 msr(0b011, 0b0100, 0b0100, 0b001, reg);
546 }
547
548 inline void clear_fpsr()
549 {
550 msr(0b011, 0b0100, 0b0100, 0b001, zr);
551 }
552
553 // DCZID_EL0: op1 == 011
554 // CRn == 0000
555 // CRm == 0000
556 // op2 == 111
557 inline void get_dczid_el0(Register reg)
558 {
559 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
560 }
561
562 // CTR_EL0: op1 == 011
563 // CRn == 0000
564 // CRm == 0000
565 // op2 == 001
566 inline void get_ctr_el0(Register reg)
567 {
568 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
569 }
570
571 // idiv variant which deals with MINLONG as dividend and -1 as divisor
572 int corrected_idivl(Register result, Register ra, Register rb,
573 bool want_remainder, Register tmp = rscratch1);
574 int corrected_idivq(Register result, Register ra, Register rb,
575 bool want_remainder, Register tmp = rscratch1);
576
577 // Support for NULL-checks
578 //
579 // Generates code that causes a NULL OS exception if the content of reg is NULL.
580 // If the accessed location is M[reg + offset] and the offset is known, provide the
581 // offset. No explicit code generation is needed if the offset is within a certain
582 // range (0 <= offset <= page_size).
583
584 virtual void null_check(Register reg, int offset = -1);
585 static bool needs_explicit_null_check(intptr_t offset);
586 static bool uses_implicit_null_check(void* address);
587
588 static address target_addr_for_insn(address insn_addr, unsigned insn);
589 static address target_addr_for_insn(address insn_addr) {
590 unsigned insn = *(unsigned*)insn_addr;
591 return target_addr_for_insn(insn_addr, insn);
592 }
593
594 // Required platform-specific helpers for Label::patch_instructions.
595 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
596 static int pd_patch_instruction_size(address branch, address target);
597 static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
598 pd_patch_instruction_size(branch, target);
599 }
600 static address pd_call_destination(address branch) {
601 return target_addr_for_insn(branch);
602 }
603 #ifndef PRODUCT
604 static void pd_print_patched_instruction(address branch);
605 #endif
606
607 static int patch_oop(address insn_addr, address o);
608 static int patch_narrow_klass(address insn_addr, narrowKlass n);
609
610 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
611 void emit_static_call_stub();
612
613 // The following 4 methods return the offset of the appropriate move instruction
614
615 // Support for fast byte/short loading with zero extension (depending on particular CPU)
616 int load_unsigned_byte(Register dst, Address src);
617 int load_unsigned_short(Register dst, Address src);
618
619 // Support for fast byte/short loading with sign extension (depending on particular CPU)
620 int load_signed_byte(Register dst, Address src);
621 int load_signed_short(Register dst, Address src);
622
623 int load_signed_byte32(Register dst, Address src);
624 int load_signed_short32(Register dst, Address src);
625
626 // Support for sign-extension (hi:lo = extend_sign(lo))
627 void extend_sign(Register hi, Register lo);
628
629 // Load and store values by size and signed-ness
630 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
631 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
632
633 // Support for inc/dec with optimal instruction selection depending on value
634
635 // x86_64 aliases an unqualified register/address increment and
636 // decrement to call incrementq and decrementq but also supports
637 // explicitly sized calls to incrementq/decrementq or
638 // incrementl/decrementl
639
640 // for aarch64 the proper convention would be to use
641 // increment/decrement for 64 bit operatons and
642 // incrementw/decrementw for 32 bit operations. so when porting
643 // x86_64 code we can leave calls to increment/decrement as is,
644 // replace incrementq/decrementq with increment/decrement and
645 // replace incrementl/decrementl with incrementw/decrementw.
646
647 // n.b. increment/decrement calls with an Address destination will
648 // need to use a scratch register to load the value to be
649 // incremented. increment/decrement calls which add or subtract a
650 // constant value greater than 2^12 will need to use a 2nd scratch
651 // register to hold the constant. so, a register increment/decrement
652 // may trash rscratch2 and an address increment/decrement trash
653 // rscratch and rscratch2
654
655 void decrementw(Address dst, int value = 1);
656 void decrementw(Register reg, int value = 1);
657
658 void decrement(Register reg, int value = 1);
659 void decrement(Address dst, int value = 1);
660
661 void incrementw(Address dst, int value = 1);
662 void incrementw(Register reg, int value = 1);
663
664 void increment(Register reg, int value = 1);
665 void increment(Address dst, int value = 1);
666
667
668 // Alignment
669 void align(int modulus);
670
671 // Stack frame creation/removal
672 void enter()
673 {
674 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
675 mov(rfp, sp);
676 }
677 void leave()
678 {
679 mov(sp, rfp);
680 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
681 }
682
683 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
684 // The pointer will be loaded into the thread register.
685 void get_thread(Register thread);
686
687
688 // Support for VM calls
689 //
690 // It is imperative that all calls into the VM are handled via the call_VM macros.
691 // They make sure that the stack linkage is setup correctly. call_VM's correspond
692 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
693
694
695 void call_VM(Register oop_result,
696 address entry_point,
697 bool check_exceptions = true);
698 void call_VM(Register oop_result,
699 address entry_point,
700 Register arg_1,
701 bool check_exceptions = true);
702 void call_VM(Register oop_result,
703 address entry_point,
704 Register arg_1, Register arg_2,
705 bool check_exceptions = true);
706 void call_VM(Register oop_result,
707 address entry_point,
708 Register arg_1, Register arg_2, Register arg_3,
709 bool check_exceptions = true);
710
711 // Overloadings with last_Java_sp
712 void call_VM(Register oop_result,
713 Register last_java_sp,
714 address entry_point,
715 int number_of_arguments = 0,
716 bool check_exceptions = true);
717 void call_VM(Register oop_result,
718 Register last_java_sp,
719 address entry_point,
720 Register arg_1, bool
721 check_exceptions = true);
722 void call_VM(Register oop_result,
723 Register last_java_sp,
724 address entry_point,
725 Register arg_1, Register arg_2,
726 bool check_exceptions = true);
727 void call_VM(Register oop_result,
728 Register last_java_sp,
729 address entry_point,
730 Register arg_1, Register arg_2, Register arg_3,
731 bool check_exceptions = true);
732
733 void get_vm_result (Register oop_result, Register thread);
734 void get_vm_result_2(Register metadata_result, Register thread);
735
736 // These always tightly bind to MacroAssembler::call_VM_base
737 // bypassing the virtual implementation
738 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
739 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
740 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
741 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
742 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
743
744 void call_VM_leaf(address entry_point,
745 int number_of_arguments = 0);
746 void call_VM_leaf(address entry_point,
747 Register arg_1);
748 void call_VM_leaf(address entry_point,
749 Register arg_1, Register arg_2);
750 void call_VM_leaf(address entry_point,
751 Register arg_1, Register arg_2, Register arg_3);
752
753 // These always tightly bind to MacroAssembler::call_VM_leaf_base
754 // bypassing the virtual implementation
755 void super_call_VM_leaf(address entry_point);
756 void super_call_VM_leaf(address entry_point, Register arg_1);
757 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
758 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
759 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
760
761 // last Java Frame (fills frame anchor)
762 void set_last_Java_frame(Register last_java_sp,
763 Register last_java_fp,
764 address last_java_pc,
765 Register scratch);
766
767 void set_last_Java_frame(Register last_java_sp,
768 Register last_java_fp,
769 Label &last_java_pc,
770 Register scratch);
771
772 void set_last_Java_frame(Register last_java_sp,
773 Register last_java_fp,
774 Register last_java_pc,
775 Register scratch);
776
777 void reset_last_Java_frame(Register thread);
778
779 // thread in the default location (rthread)
780 void reset_last_Java_frame(bool clear_fp);
781
782 // Stores
783 void store_check(Register obj); // store check for obj - register is destroyed afterwards
784 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
785
786 void resolve_jobject(Register value, Register thread, Register tmp);
787
788 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
789 void c2bool(Register x);
790
791 // oop manipulations
792 void load_klass(Register dst, Register src);
793 void store_klass(Register dst, Register src);
794 void cmp_klass(Register oop, Register trial_klass, Register tmp);
795
796 void resolve_oop_handle(Register result, Register tmp = r5);
797 void load_mirror(Register dst, Register method, Register tmp = r5);
798
799 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
800 Register tmp1, Register tmp_thread);
801
802 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
803 Register tmp1, Register tmp_thread);
804
805 // Resolves obj for access. Result is placed in the same register.
806 // All other registers are preserved.
807 void resolve(DecoratorSet decorators, Register obj);
808
809 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
810 Register thread_tmp = noreg, DecoratorSet decorators = 0);
811
812 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
813 Register thread_tmp = noreg, DecoratorSet decorators = 0);
814 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
815 Register tmp_thread = noreg, DecoratorSet decorators = 0);
816
817 // currently unimplemented
818 // Used for storing NULL. All other oop constants should be
819 // stored using routines that take a jobject.
820 void store_heap_oop_null(Address dst);
821
822 void load_prototype_header(Register dst, Register src);
823
824 void store_klass_gap(Register dst, Register src);
825
826 // This dummy is to prevent a call to store_heap_oop from
827 // converting a zero (like NULL) into a Register by giving
828 // the compiler two choices it can't resolve
829
830 void store_heap_oop(Address dst, void* dummy);
831
832 void encode_heap_oop(Register d, Register s);
833 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
834 void decode_heap_oop(Register d, Register s);
835 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
836 void encode_heap_oop_not_null(Register r);
837 void decode_heap_oop_not_null(Register r);
838 void encode_heap_oop_not_null(Register dst, Register src);
839 void decode_heap_oop_not_null(Register dst, Register src);
840
841 void set_narrow_oop(Register dst, jobject obj);
842
843 void encode_klass_not_null(Register r);
844 void decode_klass_not_null(Register r);
845 void encode_klass_not_null(Register dst, Register src);
846 void decode_klass_not_null(Register dst, Register src);
847
848 void set_narrow_klass(Register dst, Klass* k);
849
850 // if heap base register is used - reinit it with the correct value
851 void reinit_heapbase();
852
853 DEBUG_ONLY(void verify_heapbase(const char* msg);)
854
855 void push_CPU_state(bool save_vectors = false);
856 void pop_CPU_state(bool restore_vectors = false) ;
857
858 // Round up to a power of two
859 void round_to(Register reg, int modulus);
860
861 // allocation
862 void eden_allocate(
863 Register obj, // result: pointer to object after successful allocation
864 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
865 int con_size_in_bytes, // object size in bytes if known at compile time
866 Register t1, // temp register
867 Label& slow_case // continuation point if fast allocation fails
868 );
869 void tlab_allocate(
870 Register obj, // result: pointer to object after successful allocation
871 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
872 int con_size_in_bytes, // object size in bytes if known at compile time
873 Register t1, // temp register
874 Register t2, // temp register
875 Label& slow_case // continuation point if fast allocation fails
876 );
877 void zero_memory(Register addr, Register len, Register t1);
878 void verify_tlab();
879
880 // interface method calling
881 void lookup_interface_method(Register recv_klass,
882 Register intf_klass,
883 RegisterOrConstant itable_index,
884 Register method_result,
885 Register scan_temp,
886 Label& no_such_interface,
887 bool return_method = true);
888
889 // virtual method calling
890 // n.b. x86 allows RegisterOrConstant for vtable_index
891 void lookup_virtual_method(Register recv_klass,
892 RegisterOrConstant vtable_index,
893 Register method_result);
894
895 // Test sub_klass against super_klass, with fast and slow paths.
896
897 // The fast path produces a tri-state answer: yes / no / maybe-slow.
898 // One of the three labels can be NULL, meaning take the fall-through.
899 // If super_check_offset is -1, the value is loaded up from super_klass.
900 // No registers are killed, except temp_reg.
901 void check_klass_subtype_fast_path(Register sub_klass,
902 Register super_klass,
903 Register temp_reg,
904 Label* L_success,
905 Label* L_failure,
906 Label* L_slow_path,
907 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
908
909 // The rest of the type check; must be wired to a corresponding fast path.
910 // It does not repeat the fast path logic, so don't use it standalone.
911 // The temp_reg and temp2_reg can be noreg, if no temps are available.
912 // Updates the sub's secondary super cache as necessary.
913 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
914 void check_klass_subtype_slow_path(Register sub_klass,
915 Register super_klass,
916 Register temp_reg,
917 Register temp2_reg,
918 Label* L_success,
919 Label* L_failure,
920 bool set_cond_codes = false);
921
922 // Simplified, combined version, good for typical uses.
923 // Falls through on failure.
924 void check_klass_subtype(Register sub_klass,
925 Register super_klass,
926 Register temp_reg,
927 Label& L_success);
928
929 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
930
931
932 // Debugging
933
934 // only if +VerifyOops
935 void verify_oop(Register reg, const char* s = "broken oop");
936 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
937
938 // TODO: verify method and klass metadata (compare against vptr?)
939 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
940 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
941
942 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
943 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
944
945 // only if +VerifyFPU
946 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
947
948 // prints msg, dumps registers and stops execution
949 void stop(const char* msg);
950
951 // prints msg and continues
952 void warn(const char* msg);
953
954 static void debug64(char* msg, int64_t pc, int64_t regs[]);
955
956 void untested() { stop("untested"); }
957
958 void unimplemented(const char* what = "");
959
960 void should_not_reach_here() { stop("should not reach here"); }
961
962 // Stack overflow checking
963 void bang_stack_with_offset(int offset) {
964 // stack grows down, caller passes positive offset
965 assert(offset > 0, "must bang with negative offset");
966 sub(rscratch2, sp, offset);
967 str(zr, Address(rscratch2));
968 }
969
970 // Writes to stack successive pages until offset reached to check for
971 // stack overflow + shadow pages. Also, clobbers tmp
972 void bang_stack_size(Register size, Register tmp);
973
974 // Check for reserved stack access in method being exited (for JIT)
975 void reserved_stack_check();
976
977 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
978 Register tmp,
979 int offset);
980
981 // Arithmetics
982
983 void addptr(const Address &dst, int32_t src);
984 void cmpptr(Register src1, Address src2);
985
986 void cmpoop(Register obj1, Register obj2);
987
988 // Various forms of CAS
989
990 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
991 Label &suceed, Label *fail);
992 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
993 Label &suceed, Label *fail);
994
995 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
996 Label &suceed, Label *fail);
997
998 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
999 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1000 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1001 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1002
1003 void atomic_xchg(Register prev, Register newv, Register addr);
1004 void atomic_xchgw(Register prev, Register newv, Register addr);
1005 void atomic_xchgal(Register prev, Register newv, Register addr);
1006 void atomic_xchgalw(Register prev, Register newv, Register addr);
1007
1008 void orptr(Address adr, RegisterOrConstant src) {
1009 ldr(rscratch1, adr);
1010 if (src.is_register())
1011 orr(rscratch1, rscratch1, src.as_register());
1012 else
1013 orr(rscratch1, rscratch1, src.as_constant());
1014 str(rscratch1, adr);
1015 }
1016
1017 // A generic CAS; success or failure is in the EQ flag.
1018 // Clobbers rscratch1
1019 void cmpxchg(Register addr, Register expected, Register new_val,
1020 enum operand_size size,
1021 bool acquire, bool release, bool weak,
1022 Register result);
1023 private:
1024 void compare_eq(Register rn, Register rm, enum operand_size size);
1025
1026 public:
1027 // Calls
1028
1029 address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1030
1031 static bool far_branches() {
1032 return ReservedCodeCacheSize > branch_range || UseAOT;
1033 }
1034
1035 // Jumps that can reach anywhere in the code cache.
1036 // Trashes tmp.
1037 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1038 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1039
1040 static int far_branch_size() {
1041 if (far_branches()) {
1042 return 3 * 4; // adrp, add, br
1043 } else {
1044 return 4;
1045 }
1046 }
1047
1048 // Emit the CompiledIC call idiom
1049 address ic_call(address entry, jint method_index = 0);
1050
1051 public:
1052
1053 // Data
1054
1055 void mov_metadata(Register dst, Metadata* obj);
1056 Address allocate_metadata_address(Metadata* obj);
1057 Address constant_oop_address(jobject obj);
1058
1059 void movoop(Register dst, jobject obj, bool immediate = false);
1060
1061 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1062 void kernel_crc32(Register crc, Register buf, Register len,
1063 Register table0, Register table1, Register table2, Register table3,
1064 Register tmp, Register tmp2, Register tmp3);
1065 // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1066 void kernel_crc32c(Register crc, Register buf, Register len,
1067 Register table0, Register table1, Register table2, Register table3,
1068 Register tmp, Register tmp2, Register tmp3);
1069
1070 // Stack push and pop individual 64 bit registers
1071 void push(Register src);
1072 void pop(Register dst);
1073
1074 // push all registers onto the stack
1075 void pusha();
1076 void popa();
1077
1078 void repne_scan(Register addr, Register value, Register count,
1079 Register scratch);
1080 void repne_scanw(Register addr, Register value, Register count,
1081 Register scratch);
1082
1083 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1084 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1085
1086 // If a constant does not fit in an immediate field, generate some
1087 // number of MOV instructions and then perform the operation
1088 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1089 add_sub_imm_insn insn1,
1090 add_sub_reg_insn insn2);
1091 // Seperate vsn which sets the flags
1092 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1093 add_sub_imm_insn insn1,
1094 add_sub_reg_insn insn2);
1095
1096 #define WRAP(INSN) \
1097 void INSN(Register Rd, Register Rn, unsigned imm) { \
1098 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1099 } \
1100 \
1101 void INSN(Register Rd, Register Rn, Register Rm, \
1102 enum shift_kind kind, unsigned shift = 0) { \
1103 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1104 } \
1105 \
1106 void INSN(Register Rd, Register Rn, Register Rm) { \
1107 Assembler::INSN(Rd, Rn, Rm); \
1108 } \
1109 \
1110 void INSN(Register Rd, Register Rn, Register Rm, \
1111 ext::operation option, int amount = 0) { \
1112 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1113 }
1114
1115 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1116
1117 #undef WRAP
1118 #define WRAP(INSN) \
1119 void INSN(Register Rd, Register Rn, unsigned imm) { \
1120 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1121 } \
1122 \
1123 void INSN(Register Rd, Register Rn, Register Rm, \
1124 enum shift_kind kind, unsigned shift = 0) { \
1125 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1126 } \
1127 \
1128 void INSN(Register Rd, Register Rn, Register Rm) { \
1129 Assembler::INSN(Rd, Rn, Rm); \
1130 } \
1131 \
1132 void INSN(Register Rd, Register Rn, Register Rm, \
1133 ext::operation option, int amount = 0) { \
1134 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1135 }
1136
1137 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1138
1139 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1140 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1141 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1142 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1143
1144 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1145
1146 void tableswitch(Register index, jint lowbound, jint highbound,
1147 Label &jumptable, Label &jumptable_end, int stride = 1) {
1148 adr(rscratch1, jumptable);
1149 subsw(rscratch2, index, lowbound);
1150 subsw(zr, rscratch2, highbound - lowbound);
1151 br(Assembler::HS, jumptable_end);
1152 add(rscratch1, rscratch1, rscratch2,
1153 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1154 br(rscratch1);
1155 }
1156
1157 // Form an address from base + offset in Rd. Rd may or may not
1158 // actually be used: you must use the Address that is returned. It
1159 // is up to you to ensure that the shift provided matches the size
1160 // of your data.
1161 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1162
1163 // Return true iff an address is within the 48-bit AArch64 address
1164 // space.
1165 bool is_valid_AArch64_address(address a) {
1166 return ((uint64_t)a >> 48) == 0;
1167 }
1168
1169 // Load the base of the cardtable byte map into reg.
1170 void load_byte_map_base(Register reg);
1171
1172 // Prolog generator routines to support switch between x86 code and
1173 // generated ARM code
1174
1175 // routine to generate an x86 prolog for a stub function which
1176 // bootstraps into the generated ARM code which directly follows the
1177 // stub
1178 //
1179
1180 public:
1181 // enum used for aarch64--x86 linkage to define return type of x86 function
1182 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1183
1184 #ifdef BUILTIN_SIM
1185 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1186 #else
1187 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1188 #endif
1189
1190 // special version of call_VM_leaf_base needed for aarch64 simulator
1191 // where we need to specify both the gp and fp arg counts and the
1192 // return type so that the linkage routine from aarch64 to x86 and
1193 // back knows which aarch64 registers to copy to x86 registers and
1194 // which x86 result register to copy back to an aarch64 register
1195
1196 void call_VM_leaf_base1(
1197 address entry_point, // the entry point
1198 int number_of_gp_arguments, // the number of gp reg arguments to pass
1199 int number_of_fp_arguments, // the number of fp reg arguments to pass
1200 ret_type type, // the return type for the call
1201 Label* retaddr = NULL
1202 );
1203
1204 void ldr_constant(Register dest, const Address &const_addr) {
1205 if (NearCpool) {
1206 ldr(dest, const_addr);
1207 } else {
1208 unsigned long offset;
1209 adrp(dest, InternalAddress(const_addr.target()), offset);
1210 ldr(dest, Address(dest, offset));
1211 }
1212 }
1213
1214 address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1215 address read_polling_page(Register r, relocInfo::relocType rtype);
1216 void get_polling_page(Register dest, address page, relocInfo::relocType rtype);
1217
1218 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1219 void update_byte_crc32(Register crc, Register val, Register table);
1220 void update_word_crc32(Register crc, Register v, Register tmp,
1221 Register table0, Register table1, Register table2, Register table3,
1222 bool upper = false);
1223
1224 void string_compare(Register str1, Register str2,
1225 Register cnt1, Register cnt2, Register result,
1226 Register tmp1, Register tmp2, FloatRegister vtmp1,
1227 FloatRegister vtmp2, FloatRegister vtmp3, int ae);
1228
1229 void has_negatives(Register ary1, Register len, Register result);
1230
1231 void arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1232 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1233
1234 void string_equals(Register a1, Register a2, Register result, Register cnt1,
1235 int elem_size);
1236
1237 void fill_words(Register base, Register cnt, Register value);
1238 void zero_words(Register base, u_int64_t cnt);
1239 void zero_words(Register ptr, Register cnt);
1240 void zero_dcache_blocks(Register base, Register cnt);
1241
1242 static const int zero_words_block_size;
1243
1244 void byte_array_inflate(Register src, Register dst, Register len,
1245 FloatRegister vtmp1, FloatRegister vtmp2,
1246 FloatRegister vtmp3, Register tmp4);
1247
1248 void char_array_compress(Register src, Register dst, Register len,
1249 FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1250 FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1251 Register result);
1252
1253 void encode_iso_array(Register src, Register dst,
1254 Register len, Register result,
1255 FloatRegister Vtmp1, FloatRegister Vtmp2,
1256 FloatRegister Vtmp3, FloatRegister Vtmp4);
1257 void string_indexof(Register str1, Register str2,
1258 Register cnt1, Register cnt2,
1259 Register tmp1, Register tmp2,
1260 Register tmp3, Register tmp4,
1261 Register tmp5, Register tmp6,
1262 int int_cnt1, Register result, int ae);
1263 void string_indexof_char(Register str1, Register cnt1,
1264 Register ch, Register result,
1265 Register tmp1, Register tmp2, Register tmp3);
1266 void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1267 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1268 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1269 FloatRegister tmpC4, Register tmp1, Register tmp2,
1270 Register tmp3, Register tmp4, Register tmp5);
1271 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1272 address pio2, address dsin_coef, address dcos_coef);
1273 private:
1274 // begin trigonometric functions support block
1275 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1276 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1277 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1278 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1279 // end trigonometric functions support block
1280 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1281 Register src1, Register src2);
1282 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1283 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1284 }
1285 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1286 Register y, Register y_idx, Register z,
1287 Register carry, Register product,
1288 Register idx, Register kdx);
1289 void multiply_128_x_128_loop(Register y, Register z,
1290 Register carry, Register carry2,
1291 Register idx, Register jdx,
1292 Register yz_idx1, Register yz_idx2,
1293 Register tmp, Register tmp3, Register tmp4,
1294 Register tmp7, Register product_hi);
1295 void kernel_crc32_using_crc32(Register crc, Register buf,
1296 Register len, Register tmp0, Register tmp1, Register tmp2,
1297 Register tmp3);
1298 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1299 Register len, Register tmp0, Register tmp1, Register tmp2,
1300 Register tmp3);
1301 public:
1302 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1303 Register zlen, Register tmp1, Register tmp2, Register tmp3,
1304 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1305 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1306 // ISB may be needed because of a safepoint
1307 void maybe_isb() { isb(); }
1308
1309 private:
1310 // Return the effective address r + (r1 << ext) + offset.
1311 // Uses rscratch2.
1312 Address offsetted_address(Register r, Register r1, Address::extend ext,
1313 int offset, int size);
1314
1315 private:
1316 // Returns an address on the stack which is reachable with a ldr/str of size
1317 // Uses rscratch2 if the address is not directly reachable
1318 Address spill_address(int size, int offset, Register tmp=rscratch2);
1319
1320 bool merge_alignment_check(Register base, size_t size, long cur_offset, long prev_offset) const;
1321
1322 // Check whether two loads/stores can be merged into ldp/stp.
1323 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1324
1325 // Merge current load/store with previous load/store into ldp/stp.
1326 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1327
1328 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1329 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1330
1331 public:
1332 void spill(Register Rx, bool is64, int offset) {
1333 if (is64) {
1334 str(Rx, spill_address(8, offset));
1335 } else {
1336 strw(Rx, spill_address(4, offset));
1337 }
1338 }
1339 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1340 str(Vx, T, spill_address(1 << (int)T, offset));
1341 }
1342 void unspill(Register Rx, bool is64, int offset) {
1343 if (is64) {
1344 ldr(Rx, spill_address(8, offset));
1345 } else {
1346 ldrw(Rx, spill_address(4, offset));
1347 }
1348 }
1349 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1350 ldr(Vx, T, spill_address(1 << (int)T, offset));
1351 }
1352 void spill_copy128(int src_offset, int dst_offset,
1353 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1354 if (src_offset < 512 && (src_offset & 7) == 0 &&
1355 dst_offset < 512 && (dst_offset & 7) == 0) {
1356 ldp(tmp1, tmp2, Address(sp, src_offset));
1357 stp(tmp1, tmp2, Address(sp, dst_offset));
1358 } else {
1359 unspill(tmp1, true, src_offset);
1360 spill(tmp1, true, dst_offset);
1361 unspill(tmp1, true, src_offset+8);
1362 spill(tmp1, true, dst_offset+8);
1363 }
1364 }
1365 };
1366
1367 #ifdef ASSERT
1368 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1369 #endif
1370
1371 /**
1372 * class SkipIfEqual:
1373 *
1374 * Instantiating this class will result in assembly code being output that will
1375 * jump around any code emitted between the creation of the instance and it's
1376 * automatic destruction at the end of a scope block, depending on the value of
1377 * the flag passed to the constructor, which will be checked at run-time.
1378 */
1379 class SkipIfEqual {
1380 private:
1381 MacroAssembler* _masm;
1382 Label _label;
1383
1384 public:
1385 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1386 ~SkipIfEqual();
1387 };
1388
1389 struct tableswitch {
1390 Register _reg;
1391 int _insn_index; jint _first_key; jint _last_key;
1392 Label _after;
1393 Label _branches;
1394 };
1395
1396 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP