12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30 #include "oops/compressedOops.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39
40 public:
41 using Assembler::mov;
42 using Assembler::movi;
43
44 protected:
45
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51 virtual void call_VM_leaf_base(
568 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
569 }
570
571 // idiv variant which deals with MINLONG as dividend and -1 as divisor
572 int corrected_idivl(Register result, Register ra, Register rb,
573 bool want_remainder, Register tmp = rscratch1);
574 int corrected_idivq(Register result, Register ra, Register rb,
575 bool want_remainder, Register tmp = rscratch1);
576
577 // Support for NULL-checks
578 //
579 // Generates code that causes a NULL OS exception if the content of reg is NULL.
580 // If the accessed location is M[reg + offset] and the offset is known, provide the
581 // offset. No explicit code generation is needed if the offset is within a certain
582 // range (0 <= offset <= page_size).
583
584 virtual void null_check(Register reg, int offset = -1);
585 static bool needs_explicit_null_check(intptr_t offset);
586 static bool uses_implicit_null_check(void* address);
587
588 static address target_addr_for_insn(address insn_addr, unsigned insn);
589 static address target_addr_for_insn(address insn_addr) {
590 unsigned insn = *(unsigned*)insn_addr;
591 return target_addr_for_insn(insn_addr, insn);
592 }
593
594 // Required platform-specific helpers for Label::patch_instructions.
595 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
596 static int pd_patch_instruction_size(address branch, address target);
597 static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
598 pd_patch_instruction_size(branch, target);
599 }
600 static address pd_call_destination(address branch) {
601 return target_addr_for_insn(branch);
602 }
603 #ifndef PRODUCT
604 static void pd_print_patched_instruction(address branch);
605 #endif
606
607 static int patch_oop(address insn_addr, address o);
772 void set_last_Java_frame(Register last_java_sp,
773 Register last_java_fp,
774 Register last_java_pc,
775 Register scratch);
776
777 void reset_last_Java_frame(Register thread);
778
779 // thread in the default location (rthread)
780 void reset_last_Java_frame(bool clear_fp);
781
782 // Stores
783 void store_check(Register obj); // store check for obj - register is destroyed afterwards
784 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
785
786 void resolve_jobject(Register value, Register thread, Register tmp);
787
788 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
789 void c2bool(Register x);
790
791 // oop manipulations
792 void load_klass(Register dst, Register src);
793 void store_klass(Register dst, Register src);
794 void cmp_klass(Register oop, Register trial_klass, Register tmp);
795
796 void resolve_oop_handle(Register result, Register tmp = r5);
797 void load_mirror(Register dst, Register method, Register tmp = r5);
798
799 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
800 Register tmp1, Register tmp_thread);
801
802 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
803 Register tmp1, Register tmp_thread);
804
805 // Resolves obj for access. Result is placed in the same register.
806 // All other registers are preserved.
807 void resolve(DecoratorSet decorators, Register obj);
808
809 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
810 Register thread_tmp = noreg, DecoratorSet decorators = 0);
811
812 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
813 Register thread_tmp = noreg, DecoratorSet decorators = 0);
814 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
815 Register tmp_thread = noreg, DecoratorSet decorators = 0);
816
817 // currently unimplemented
818 // Used for storing NULL. All other oop constants should be
819 // stored using routines that take a jobject.
820 void store_heap_oop_null(Address dst);
821
822 void load_prototype_header(Register dst, Register src);
823
824 void store_klass_gap(Register dst, Register src);
825
826 // This dummy is to prevent a call to store_heap_oop from
827 // converting a zero (like NULL) into a Register by giving
828 // the compiler two choices it can't resolve
829
830 void store_heap_oop(Address dst, void* dummy);
831
832 void encode_heap_oop(Register d, Register s);
833 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
834 void decode_heap_oop(Register d, Register s);
835 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
1126 } \
1127 \
1128 void INSN(Register Rd, Register Rn, Register Rm) { \
1129 Assembler::INSN(Rd, Rn, Rm); \
1130 } \
1131 \
1132 void INSN(Register Rd, Register Rn, Register Rm, \
1133 ext::operation option, int amount = 0) { \
1134 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1135 }
1136
1137 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1138
1139 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1140 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1141 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1142 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1143
1144 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1145
1146 void tableswitch(Register index, jint lowbound, jint highbound,
1147 Label &jumptable, Label &jumptable_end, int stride = 1) {
1148 adr(rscratch1, jumptable);
1149 subsw(rscratch2, index, lowbound);
1150 subsw(zr, rscratch2, highbound - lowbound);
1151 br(Assembler::HS, jumptable_end);
1152 add(rscratch1, rscratch1, rscratch2,
1153 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1154 br(rscratch1);
1155 }
1156
1157 // Form an address from base + offset in Rd. Rd may or may not
1158 // actually be used: you must use the Address that is returned. It
1159 // is up to you to ensure that the shift provided matches the size
1160 // of your data.
1161 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1162
1163 // Return true iff an address is within the 48-bit AArch64 address
1164 // space.
1165 bool is_valid_AArch64_address(address a) {
1218 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1219 void update_byte_crc32(Register crc, Register val, Register table);
1220 void update_word_crc32(Register crc, Register v, Register tmp,
1221 Register table0, Register table1, Register table2, Register table3,
1222 bool upper = false);
1223
1224 void string_compare(Register str1, Register str2,
1225 Register cnt1, Register cnt2, Register result,
1226 Register tmp1, Register tmp2, FloatRegister vtmp1,
1227 FloatRegister vtmp2, FloatRegister vtmp3, int ae);
1228
1229 void has_negatives(Register ary1, Register len, Register result);
1230
1231 void arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1232 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1233
1234 void string_equals(Register a1, Register a2, Register result, Register cnt1,
1235 int elem_size);
1236
1237 void fill_words(Register base, Register cnt, Register value);
1238 void zero_words(Register base, u_int64_t cnt);
1239 void zero_words(Register ptr, Register cnt);
1240 void zero_dcache_blocks(Register base, Register cnt);
1241
1242 static const int zero_words_block_size;
1243
1244 void byte_array_inflate(Register src, Register dst, Register len,
1245 FloatRegister vtmp1, FloatRegister vtmp2,
1246 FloatRegister vtmp3, Register tmp4);
1247
1248 void char_array_compress(Register src, Register dst, Register len,
1249 FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1250 FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1251 Register result);
1252
1253 void encode_iso_array(Register src, Register dst,
1254 Register len, Register result,
1255 FloatRegister Vtmp1, FloatRegister Vtmp2,
1256 FloatRegister Vtmp3, FloatRegister Vtmp4);
1257 void string_indexof(Register str1, Register str2,
|
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30 #include "oops/compressedOops.hpp"
31
32 class ciValueKlass;
33
34 // MacroAssembler extends Assembler by frequently used macros.
35 //
36 // Instructions for which a 'better' code sequence exists depending
37 // on arguments should also go in here.
38
39 class MacroAssembler: public Assembler {
40 friend class LIR_Assembler;
41
42 public:
43 using Assembler::mov;
44 using Assembler::movi;
45
46 protected:
47
48 // Support for VM calls
49 //
50 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
51 // may customize this version by overriding it for its purposes (e.g., to save/restore
52 // additional registers when doing a VM call).
53 virtual void call_VM_leaf_base(
570 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
571 }
572
573 // idiv variant which deals with MINLONG as dividend and -1 as divisor
574 int corrected_idivl(Register result, Register ra, Register rb,
575 bool want_remainder, Register tmp = rscratch1);
576 int corrected_idivq(Register result, Register ra, Register rb,
577 bool want_remainder, Register tmp = rscratch1);
578
579 // Support for NULL-checks
580 //
581 // Generates code that causes a NULL OS exception if the content of reg is NULL.
582 // If the accessed location is M[reg + offset] and the offset is known, provide the
583 // offset. No explicit code generation is needed if the offset is within a certain
584 // range (0 <= offset <= page_size).
585
586 virtual void null_check(Register reg, int offset = -1);
587 static bool needs_explicit_null_check(intptr_t offset);
588 static bool uses_implicit_null_check(void* address);
589
590 void test_klass_is_value(Register klass, Register temp_reg, Label& is_value);
591
592 void test_field_is_flattenable(Register flags, Register temp_reg, Label& is_flattenable);
593 void test_field_is_not_flattenable(Register flags, Register temp_reg, Label& notFlattenable);
594 void test_field_is_flattened(Register flags, Register temp_reg, Label& is_flattened);
595
596 // Check klass/oops is flat value type array (oop->_klass->_layout_helper & vt_bit)
597 void test_flattened_array_oop(Register klass, Register temp_reg, Label& is_flattened_array);
598 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
599
600 static address target_addr_for_insn(address insn_addr, unsigned insn);
601 static address target_addr_for_insn(address insn_addr) {
602 unsigned insn = *(unsigned*)insn_addr;
603 return target_addr_for_insn(insn_addr, insn);
604 }
605
606 // Required platform-specific helpers for Label::patch_instructions.
607 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
608 static int pd_patch_instruction_size(address branch, address target);
609 static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
610 pd_patch_instruction_size(branch, target);
611 }
612 static address pd_call_destination(address branch) {
613 return target_addr_for_insn(branch);
614 }
615 #ifndef PRODUCT
616 static void pd_print_patched_instruction(address branch);
617 #endif
618
619 static int patch_oop(address insn_addr, address o);
784 void set_last_Java_frame(Register last_java_sp,
785 Register last_java_fp,
786 Register last_java_pc,
787 Register scratch);
788
789 void reset_last_Java_frame(Register thread);
790
791 // thread in the default location (rthread)
792 void reset_last_Java_frame(bool clear_fp);
793
794 // Stores
795 void store_check(Register obj); // store check for obj - register is destroyed afterwards
796 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
797
798 void resolve_jobject(Register value, Register thread, Register tmp);
799
800 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
801 void c2bool(Register x);
802
803 // oop manipulations
804 void load_metadata(Register dst, Register src);
805 void load_storage_props(Register dst, Register src);
806
807 void load_klass(Register dst, Register src);
808 void store_klass(Register dst, Register src);
809 void cmp_klass(Register oop, Register trial_klass, Register tmp);
810
811 void resolve_oop_handle(Register result, Register tmp = r5);
812 void load_mirror(Register dst, Register method, Register tmp = r5);
813
814 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
815 Register tmp1, Register tmp_thread);
816
817 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
818 Register tmp1, Register tmp_thread, Register tmp3 = noreg);
819
820 // Resolves obj for access. Result is placed in the same register.
821 // All other registers are preserved.
822 void resolve(DecoratorSet decorators, Register obj);
823
824 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
825 Register thread_tmp = noreg, DecoratorSet decorators = 0);
826
827 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
828 Register thread_tmp = noreg, DecoratorSet decorators = 0);
829 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
830 Register tmp_thread = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
831
832 // currently unimplemented
833 // Used for storing NULL. All other oop constants should be
834 // stored using routines that take a jobject.
835 void store_heap_oop_null(Address dst);
836
837 void load_prototype_header(Register dst, Register src);
838
839 void store_klass_gap(Register dst, Register src);
840
841 // This dummy is to prevent a call to store_heap_oop from
842 // converting a zero (like NULL) into a Register by giving
843 // the compiler two choices it can't resolve
844
845 void store_heap_oop(Address dst, void* dummy);
846
847 void encode_heap_oop(Register d, Register s);
848 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
849 void decode_heap_oop(Register d, Register s);
850 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
1141 } \
1142 \
1143 void INSN(Register Rd, Register Rn, Register Rm) { \
1144 Assembler::INSN(Rd, Rn, Rm); \
1145 } \
1146 \
1147 void INSN(Register Rd, Register Rn, Register Rm, \
1148 ext::operation option, int amount = 0) { \
1149 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1150 }
1151
1152 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1153
1154 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1155 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1156 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1157 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1158
1159 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1160
1161
1162 enum RegState {
1163 reg_readonly,
1164 reg_writable,
1165 reg_written
1166 };
1167
1168 void verified_entry(Compile* C, int sp_inc);
1169
1170 // Unpack all value type arguments passed as oops
1171 void unpack_value_args(Compile* C, bool receiver_only);
1172 void store_value_type_fields_to_buf(ciValueKlass* vk);
1173
1174 void tableswitch(Register index, jint lowbound, jint highbound,
1175 Label &jumptable, Label &jumptable_end, int stride = 1) {
1176 adr(rscratch1, jumptable);
1177 subsw(rscratch2, index, lowbound);
1178 subsw(zr, rscratch2, highbound - lowbound);
1179 br(Assembler::HS, jumptable_end);
1180 add(rscratch1, rscratch1, rscratch2,
1181 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1182 br(rscratch1);
1183 }
1184
1185 // Form an address from base + offset in Rd. Rd may or may not
1186 // actually be used: you must use the Address that is returned. It
1187 // is up to you to ensure that the shift provided matches the size
1188 // of your data.
1189 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1190
1191 // Return true iff an address is within the 48-bit AArch64 address
1192 // space.
1193 bool is_valid_AArch64_address(address a) {
1246 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1247 void update_byte_crc32(Register crc, Register val, Register table);
1248 void update_word_crc32(Register crc, Register v, Register tmp,
1249 Register table0, Register table1, Register table2, Register table3,
1250 bool upper = false);
1251
1252 void string_compare(Register str1, Register str2,
1253 Register cnt1, Register cnt2, Register result,
1254 Register tmp1, Register tmp2, FloatRegister vtmp1,
1255 FloatRegister vtmp2, FloatRegister vtmp3, int ae);
1256
1257 void has_negatives(Register ary1, Register len, Register result);
1258
1259 void arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1260 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1261
1262 void string_equals(Register a1, Register a2, Register result, Register cnt1,
1263 int elem_size);
1264
1265 void fill_words(Register base, Register cnt, Register value);
1266 void fill_words(Register base, u_int64_t cnt, Register value);
1267
1268 void zero_words(Register base, u_int64_t cnt);
1269 void zero_words(Register ptr, Register cnt);
1270 void zero_dcache_blocks(Register base, Register cnt);
1271
1272 static const int zero_words_block_size;
1273
1274 void byte_array_inflate(Register src, Register dst, Register len,
1275 FloatRegister vtmp1, FloatRegister vtmp2,
1276 FloatRegister vtmp3, Register tmp4);
1277
1278 void char_array_compress(Register src, Register dst, Register len,
1279 FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1280 FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1281 Register result);
1282
1283 void encode_iso_array(Register src, Register dst,
1284 Register len, Register result,
1285 FloatRegister Vtmp1, FloatRegister Vtmp2,
1286 FloatRegister Vtmp3, FloatRegister Vtmp4);
1287 void string_indexof(Register str1, Register str2,
|