1 /* 2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "c1/c1_Compilation.hpp" 29 #include "c1/c1_LIRAssembler.hpp" 30 #include "c1/c1_MacroAssembler.hpp" 31 #include "c1/c1_Runtime1.hpp" 32 #include "c1/c1_ValueStack.hpp" 33 #include "ci/ciArrayKlass.hpp" 34 #include "ci/ciInstance.hpp" 35 #include "gc/shared/barrierSet.hpp" 36 #include "gc/shared/cardTableModRefBS.hpp" 37 #include "gc/shared/collectedHeap.hpp" 38 #include "nativeInst_x86.hpp" 39 #include "oops/objArrayKlass.hpp" 40 #include "runtime/sharedRuntime.hpp" 41 #include "vmreg_x86.inline.hpp" 42 43 44 // These masks are used to provide 128-bit aligned bitmasks to the XMM 45 // instructions, to allow sign-masking or sign-bit flipping. They allow 46 // fast versions of NegF/NegD and AbsF/AbsD. 47 48 // Note: 'double' and 'long long' have 32-bits alignment on x86. 49 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 50 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 51 // of 128-bits operands for SSE instructions. 52 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); 53 // Store the value to a 128-bits operand. 54 operand[0] = lo; 55 operand[1] = hi; 56 return operand; 57 } 58 59 // Buffer for 128-bits masks used by SSE instructions. 60 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 61 62 // Static initialization during VM startup. 63 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 64 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 65 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000)); 66 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000)); 67 68 69 70 NEEDS_CLEANUP // remove this definitions ? 71 const Register IC_Klass = rax; // where the IC klass is cached 72 const Register SYNC_header = rax; // synchronization header 73 const Register SHIFT_count = rcx; // where count for shift operations must be 74 75 #define __ _masm-> 76 77 78 static void select_different_registers(Register preserve, 79 Register extra, 80 Register &tmp1, 81 Register &tmp2) { 82 if (tmp1 == preserve) { 83 assert_different_registers(tmp1, tmp2, extra); 84 tmp1 = extra; 85 } else if (tmp2 == preserve) { 86 assert_different_registers(tmp1, tmp2, extra); 87 tmp2 = extra; 88 } 89 assert_different_registers(preserve, tmp1, tmp2); 90 } 91 92 93 94 static void select_different_registers(Register preserve, 95 Register extra, 96 Register &tmp1, 97 Register &tmp2, 98 Register &tmp3) { 99 if (tmp1 == preserve) { 100 assert_different_registers(tmp1, tmp2, tmp3, extra); 101 tmp1 = extra; 102 } else if (tmp2 == preserve) { 103 assert_different_registers(tmp1, tmp2, tmp3, extra); 104 tmp2 = extra; 105 } else if (tmp3 == preserve) { 106 assert_different_registers(tmp1, tmp2, tmp3, extra); 107 tmp3 = extra; 108 } 109 assert_different_registers(preserve, tmp1, tmp2, tmp3); 110 } 111 112 113 114 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 115 if (opr->is_constant()) { 116 LIR_Const* constant = opr->as_constant_ptr(); 117 switch (constant->type()) { 118 case T_INT: { 119 return true; 120 } 121 122 default: 123 return false; 124 } 125 } 126 return false; 127 } 128 129 130 LIR_Opr LIR_Assembler::receiverOpr() { 131 return FrameMap::receiver_opr; 132 } 133 134 LIR_Opr LIR_Assembler::osrBufferPointer() { 135 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 136 } 137 138 //--------------fpu register translations----------------------- 139 140 141 address LIR_Assembler::float_constant(float f) { 142 address const_addr = __ float_constant(f); 143 if (const_addr == NULL) { 144 bailout("const section overflow"); 145 return __ code()->consts()->start(); 146 } else { 147 return const_addr; 148 } 149 } 150 151 152 address LIR_Assembler::double_constant(double d) { 153 address const_addr = __ double_constant(d); 154 if (const_addr == NULL) { 155 bailout("const section overflow"); 156 return __ code()->consts()->start(); 157 } else { 158 return const_addr; 159 } 160 } 161 162 163 void LIR_Assembler::set_24bit_FPU() { 164 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 165 } 166 167 void LIR_Assembler::reset_FPU() { 168 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 169 } 170 171 void LIR_Assembler::fpop() { 172 __ fpop(); 173 } 174 175 void LIR_Assembler::fxch(int i) { 176 __ fxch(i); 177 } 178 179 void LIR_Assembler::fld(int i) { 180 __ fld_s(i); 181 } 182 183 void LIR_Assembler::ffree(int i) { 184 __ ffree(i); 185 } 186 187 void LIR_Assembler::breakpoint() { 188 __ int3(); 189 } 190 191 void LIR_Assembler::push(LIR_Opr opr) { 192 if (opr->is_single_cpu()) { 193 __ push_reg(opr->as_register()); 194 } else if (opr->is_double_cpu()) { 195 NOT_LP64(__ push_reg(opr->as_register_hi())); 196 __ push_reg(opr->as_register_lo()); 197 } else if (opr->is_stack()) { 198 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 199 } else if (opr->is_constant()) { 200 LIR_Const* const_opr = opr->as_constant_ptr(); 201 if (const_opr->type() == T_OBJECT) { 202 __ push_oop(const_opr->as_jobject()); 203 } else if (const_opr->type() == T_INT) { 204 __ push_jint(const_opr->as_jint()); 205 } else { 206 ShouldNotReachHere(); 207 } 208 209 } else { 210 ShouldNotReachHere(); 211 } 212 } 213 214 void LIR_Assembler::pop(LIR_Opr opr) { 215 if (opr->is_single_cpu()) { 216 __ pop_reg(opr->as_register()); 217 } else { 218 ShouldNotReachHere(); 219 } 220 } 221 222 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 223 return addr->base()->is_illegal() && addr->index()->is_illegal(); 224 } 225 226 //------------------------------------------- 227 228 Address LIR_Assembler::as_Address(LIR_Address* addr) { 229 return as_Address(addr, rscratch1); 230 } 231 232 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 233 if (addr->base()->is_illegal()) { 234 assert(addr->index()->is_illegal(), "must be illegal too"); 235 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 236 if (! __ reachable(laddr)) { 237 __ movptr(tmp, laddr.addr()); 238 Address res(tmp, 0); 239 return res; 240 } else { 241 return __ as_Address(laddr); 242 } 243 } 244 245 Register base = addr->base()->as_pointer_register(); 246 247 if (addr->index()->is_illegal()) { 248 return Address( base, addr->disp()); 249 } else if (addr->index()->is_cpu_register()) { 250 Register index = addr->index()->as_pointer_register(); 251 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 252 } else if (addr->index()->is_constant()) { 253 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 254 assert(Assembler::is_simm32(addr_offset), "must be"); 255 256 return Address(base, addr_offset); 257 } else { 258 Unimplemented(); 259 return Address(); 260 } 261 } 262 263 264 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 265 Address base = as_Address(addr); 266 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 267 } 268 269 270 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 271 return as_Address(addr); 272 } 273 274 275 void LIR_Assembler::osr_entry() { 276 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 277 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 278 ValueStack* entry_state = osr_entry->state(); 279 int number_of_locks = entry_state->locks_size(); 280 281 // we jump here if osr happens with the interpreter 282 // state set up to continue at the beginning of the 283 // loop that triggered osr - in particular, we have 284 // the following registers setup: 285 // 286 // rcx: osr buffer 287 // 288 289 // build frame 290 ciMethod* m = compilation()->method(); 291 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 292 293 // OSR buffer is 294 // 295 // locals[nlocals-1..0] 296 // monitors[0..number_of_locks] 297 // 298 // locals is a direct copy of the interpreter frame so in the osr buffer 299 // so first slot in the local array is the last local from the interpreter 300 // and last slot is local[0] (receiver) from the interpreter 301 // 302 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 303 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 304 // in the interpreter frame (the method lock if a sync method) 305 306 // Initialize monitors in the compiled activation. 307 // rcx: pointer to osr buffer 308 // 309 // All other registers are dead at this point and the locals will be 310 // copied into place by code emitted in the IR. 311 312 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 313 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 314 int monitor_offset = BytesPerWord * method()->max_locals() + 315 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); 316 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 317 // the OSR buffer using 2 word entries: first the lock and then 318 // the oop. 319 for (int i = 0; i < number_of_locks; i++) { 320 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 321 #ifdef ASSERT 322 // verify the interpreter's monitor has a non-null object 323 { 324 Label L; 325 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); 326 __ jcc(Assembler::notZero, L); 327 __ stop("locked object is NULL"); 328 __ bind(L); 329 } 330 #endif 331 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 332 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 333 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 334 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 335 } 336 } 337 } 338 339 340 // inline cache check; done before the frame is built. 341 int LIR_Assembler::check_icache() { 342 Register receiver = FrameMap::receiver_opr->as_register(); 343 Register ic_klass = IC_Klass; 344 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 345 const bool do_post_padding = VerifyOops || UseCompressedClassPointers; 346 if (!do_post_padding) { 347 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 348 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size); 349 } 350 int offset = __ offset(); 351 __ inline_cache_check(receiver, IC_Klass); 352 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); 353 if (do_post_padding) { 354 // force alignment after the cache check. 355 // It's been verified to be aligned if !VerifyOops 356 __ align(CodeEntryAlignment); 357 } 358 return offset; 359 } 360 361 362 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 363 jobject o = NULL; 364 PatchingStub* patch = new PatchingStub(_masm, patching_id(info)); 365 __ movoop(reg, o); 366 patching_epilog(patch, lir_patch_normal, reg, info); 367 } 368 369 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { 370 Metadata* o = NULL; 371 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 372 __ mov_metadata(reg, o); 373 patching_epilog(patch, lir_patch_normal, reg, info); 374 } 375 376 // This specifies the rsp decrement needed to build the frame 377 int LIR_Assembler::initial_frame_size_in_bytes() const { 378 // if rounding, must let FrameMap know! 379 380 // The frame_map records size in slots (32bit word) 381 382 // subtract two words to account for return address and link 383 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 384 } 385 386 387 int LIR_Assembler::emit_exception_handler() { 388 // if the last instruction is a call (typically to do a throw which 389 // is coming at the end after block reordering) the return address 390 // must still point into the code area in order to avoid assertion 391 // failures when searching for the corresponding bci => add a nop 392 // (was bug 5/14/1999 - gri) 393 __ nop(); 394 395 // generate code for exception handler 396 address handler_base = __ start_a_stub(exception_handler_size()); 397 if (handler_base == NULL) { 398 // not enough space left for the handler 399 bailout("exception handler overflow"); 400 return -1; 401 } 402 403 int offset = code_offset(); 404 405 // the exception oop and pc are in rax, and rdx 406 // no other registers need to be preserved, so invalidate them 407 __ invalidate_registers(false, true, true, false, true, true); 408 409 // check that there is really an exception 410 __ verify_not_null_oop(rax); 411 412 // search an exception handler (rax: exception oop, rdx: throwing pc) 413 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 414 __ should_not_reach_here(); 415 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 416 __ end_a_stub(); 417 418 return offset; 419 } 420 421 422 // Emit the code to remove the frame from the stack in the exception 423 // unwind path. 424 int LIR_Assembler::emit_unwind_handler() { 425 #ifndef PRODUCT 426 if (CommentedAssembly) { 427 _masm->block_comment("Unwind handler"); 428 } 429 #endif 430 431 int offset = code_offset(); 432 433 // Fetch the exception from TLS and clear out exception related thread state 434 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 435 NOT_LP64(__ get_thread(rsi)); 436 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset())); 437 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD); 438 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD); 439 440 __ bind(_unwind_handler_entry); 441 __ verify_not_null_oop(rax); 442 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 443 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved) 444 } 445 446 // Preform needed unlocking 447 MonitorExitStub* stub = NULL; 448 if (method()->is_synchronized()) { 449 monitor_address(0, FrameMap::rax_opr); 450 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); 451 __ unlock_object(rdi, rsi, rax, *stub->entry()); 452 __ bind(*stub->continuation()); 453 } 454 455 if (compilation()->env()->dtrace_method_probes()) { 456 #ifdef _LP64 457 __ mov(rdi, r15_thread); 458 __ mov_metadata(rsi, method()->constant_encoding()); 459 #else 460 __ get_thread(rax); 461 __ movptr(Address(rsp, 0), rax); 462 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding()); 463 #endif 464 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 465 } 466 467 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 468 __ mov(rax, rbx); // Restore the exception 469 } 470 471 // remove the activation and dispatch to the unwind handler 472 __ remove_frame(initial_frame_size_in_bytes()); 473 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 474 475 // Emit the slow path assembly 476 if (stub != NULL) { 477 stub->emit_code(this); 478 } 479 480 return offset; 481 } 482 483 484 int LIR_Assembler::emit_deopt_handler() { 485 // if the last instruction is a call (typically to do a throw which 486 // is coming at the end after block reordering) the return address 487 // must still point into the code area in order to avoid assertion 488 // failures when searching for the corresponding bci => add a nop 489 // (was bug 5/14/1999 - gri) 490 __ nop(); 491 492 // generate code for exception handler 493 address handler_base = __ start_a_stub(deopt_handler_size()); 494 if (handler_base == NULL) { 495 // not enough space left for the handler 496 bailout("deopt handler overflow"); 497 return -1; 498 } 499 500 int offset = code_offset(); 501 InternalAddress here(__ pc()); 502 503 __ pushptr(here.addr()); 504 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 505 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 506 __ end_a_stub(); 507 508 return offset; 509 } 510 511 512 void LIR_Assembler::return_op(LIR_Opr result) { 513 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 514 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 515 assert(result->fpu() == 0, "result must already be on TOS"); 516 } 517 518 // Pop the stack before the safepoint code 519 __ remove_frame(initial_frame_size_in_bytes()); 520 521 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 522 __ reserved_stack_check(); 523 } 524 525 bool result_is_oop = result->is_valid() ? result->is_oop() : false; 526 527 // Note: we do not need to round double result; float result has the right precision 528 // the poll sets the condition code, but no data registers 529 530 if (SafepointMechanism::uses_thread_local_poll()) { 531 #ifdef _LP64 532 const Register poll_addr = rscratch1; 533 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset())); 534 #else 535 const Register poll_addr = rbx; 536 assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite"); 537 __ get_thread(poll_addr); 538 __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset())); 539 #endif 540 __ relocate(relocInfo::poll_return_type); 541 __ testl(rax, Address(poll_addr, 0)); 542 } else { 543 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); 544 545 if (Assembler::is_polling_page_far()) { 546 __ lea(rscratch1, polling_page); 547 __ relocate(relocInfo::poll_return_type); 548 __ testl(rax, Address(rscratch1, 0)); 549 } else { 550 __ testl(rax, polling_page); 551 } 552 } 553 __ ret(0); 554 } 555 556 557 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 558 guarantee(info != NULL, "Shouldn't be NULL"); 559 int offset = __ offset(); 560 if (SafepointMechanism::uses_thread_local_poll()) { 561 #ifdef _LP64 562 const Register poll_addr = rscratch1; 563 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset())); 564 #else 565 assert(tmp->is_cpu_register(), "needed"); 566 const Register poll_addr = tmp->as_register(); 567 __ get_thread(poll_addr); 568 __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset()))); 569 #endif 570 add_debug_info_for_branch(info); 571 __ relocate(relocInfo::poll_type); 572 address pre_pc = __ pc(); 573 __ testl(rax, Address(poll_addr, 0)); 574 address post_pc = __ pc(); 575 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length"); 576 } else { 577 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type); 578 if (Assembler::is_polling_page_far()) { 579 __ lea(rscratch1, polling_page); 580 offset = __ offset(); 581 add_debug_info_for_branch(info); 582 __ relocate(relocInfo::poll_type); 583 __ testl(rax, Address(rscratch1, 0)); 584 } else { 585 add_debug_info_for_branch(info); 586 __ testl(rax, polling_page); 587 } 588 } 589 return offset; 590 } 591 592 593 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 594 if (from_reg != to_reg) __ mov(to_reg, from_reg); 595 } 596 597 void LIR_Assembler::swap_reg(Register a, Register b) { 598 __ xchgptr(a, b); 599 } 600 601 602 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 603 assert(src->is_constant(), "should not call otherwise"); 604 assert(dest->is_register(), "should not call otherwise"); 605 LIR_Const* c = src->as_constant_ptr(); 606 607 switch (c->type()) { 608 case T_INT: { 609 assert(patch_code == lir_patch_none, "no patching handled here"); 610 __ movl(dest->as_register(), c->as_jint()); 611 break; 612 } 613 614 case T_ADDRESS: { 615 assert(patch_code == lir_patch_none, "no patching handled here"); 616 __ movptr(dest->as_register(), c->as_jint()); 617 break; 618 } 619 620 case T_LONG: { 621 assert(patch_code == lir_patch_none, "no patching handled here"); 622 #ifdef _LP64 623 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 624 #else 625 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 626 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 627 #endif // _LP64 628 break; 629 } 630 631 case T_OBJECT: { 632 if (patch_code != lir_patch_none) { 633 jobject2reg_with_patching(dest->as_register(), info); 634 } else { 635 __ movoop(dest->as_register(), c->as_jobject()); 636 } 637 break; 638 } 639 640 case T_METADATA: { 641 if (patch_code != lir_patch_none) { 642 klass2reg_with_patching(dest->as_register(), info); 643 } else { 644 __ mov_metadata(dest->as_register(), c->as_metadata()); 645 } 646 break; 647 } 648 649 case T_FLOAT: { 650 if (dest->is_single_xmm()) { 651 if (c->is_zero_float()) { 652 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 653 } else { 654 __ movflt(dest->as_xmm_float_reg(), 655 InternalAddress(float_constant(c->as_jfloat()))); 656 } 657 } else { 658 assert(dest->is_single_fpu(), "must be"); 659 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 660 if (c->is_zero_float()) { 661 __ fldz(); 662 } else if (c->is_one_float()) { 663 __ fld1(); 664 } else { 665 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 666 } 667 } 668 break; 669 } 670 671 case T_DOUBLE: { 672 if (dest->is_double_xmm()) { 673 if (c->is_zero_double()) { 674 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 675 } else { 676 __ movdbl(dest->as_xmm_double_reg(), 677 InternalAddress(double_constant(c->as_jdouble()))); 678 } 679 } else { 680 assert(dest->is_double_fpu(), "must be"); 681 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 682 if (c->is_zero_double()) { 683 __ fldz(); 684 } else if (c->is_one_double()) { 685 __ fld1(); 686 } else { 687 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 688 } 689 } 690 break; 691 } 692 693 default: 694 ShouldNotReachHere(); 695 } 696 } 697 698 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 699 assert(src->is_constant(), "should not call otherwise"); 700 assert(dest->is_stack(), "should not call otherwise"); 701 LIR_Const* c = src->as_constant_ptr(); 702 703 switch (c->type()) { 704 case T_INT: // fall through 705 case T_FLOAT: 706 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 707 break; 708 709 case T_ADDRESS: 710 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 711 break; 712 713 case T_OBJECT: 714 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); 715 break; 716 717 case T_LONG: // fall through 718 case T_DOUBLE: 719 #ifdef _LP64 720 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 721 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); 722 #else 723 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 724 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 725 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 726 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 727 #endif // _LP64 728 break; 729 730 default: 731 ShouldNotReachHere(); 732 } 733 } 734 735 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 736 assert(src->is_constant(), "should not call otherwise"); 737 assert(dest->is_address(), "should not call otherwise"); 738 LIR_Const* c = src->as_constant_ptr(); 739 LIR_Address* addr = dest->as_address_ptr(); 740 741 int null_check_here = code_offset(); 742 switch (type) { 743 case T_INT: // fall through 744 case T_FLOAT: 745 __ movl(as_Address(addr), c->as_jint_bits()); 746 break; 747 748 case T_ADDRESS: 749 __ movptr(as_Address(addr), c->as_jint_bits()); 750 break; 751 752 case T_OBJECT: // fall through 753 case T_ARRAY: 754 if (c->as_jobject() == NULL) { 755 if (UseCompressedOops && !wide) { 756 __ movl(as_Address(addr), (int32_t)NULL_WORD); 757 } else { 758 #ifdef _LP64 759 __ xorptr(rscratch1, rscratch1); 760 null_check_here = code_offset(); 761 __ movptr(as_Address(addr), rscratch1); 762 #else 763 __ movptr(as_Address(addr), NULL_WORD); 764 #endif 765 } 766 } else { 767 if (is_literal_address(addr)) { 768 ShouldNotReachHere(); 769 __ movoop(as_Address(addr, noreg), c->as_jobject()); 770 } else { 771 #ifdef _LP64 772 __ movoop(rscratch1, c->as_jobject()); 773 if (UseCompressedOops && !wide) { 774 __ encode_heap_oop(rscratch1); 775 null_check_here = code_offset(); 776 __ movl(as_Address_lo(addr), rscratch1); 777 } else { 778 null_check_here = code_offset(); 779 __ movptr(as_Address_lo(addr), rscratch1); 780 } 781 #else 782 __ movoop(as_Address(addr), c->as_jobject()); 783 #endif 784 } 785 } 786 break; 787 788 case T_LONG: // fall through 789 case T_DOUBLE: 790 #ifdef _LP64 791 if (is_literal_address(addr)) { 792 ShouldNotReachHere(); 793 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 794 } else { 795 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 796 null_check_here = code_offset(); 797 __ movptr(as_Address_lo(addr), r10); 798 } 799 #else 800 // Always reachable in 32bit so this doesn't produce useless move literal 801 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 802 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 803 #endif // _LP64 804 break; 805 806 case T_BOOLEAN: // fall through 807 case T_BYTE: 808 __ movb(as_Address(addr), c->as_jint() & 0xFF); 809 break; 810 811 case T_CHAR: // fall through 812 case T_SHORT: 813 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 814 break; 815 816 default: 817 ShouldNotReachHere(); 818 }; 819 820 if (info != NULL) { 821 add_debug_info_for_null_check(null_check_here, info); 822 } 823 } 824 825 826 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 827 assert(src->is_register(), "should not call otherwise"); 828 assert(dest->is_register(), "should not call otherwise"); 829 830 // move between cpu-registers 831 if (dest->is_single_cpu()) { 832 #ifdef _LP64 833 if (src->type() == T_LONG) { 834 // Can do LONG -> OBJECT 835 move_regs(src->as_register_lo(), dest->as_register()); 836 return; 837 } 838 #endif 839 assert(src->is_single_cpu(), "must match"); 840 if (src->type() == T_OBJECT) { 841 __ verify_oop(src->as_register()); 842 } 843 move_regs(src->as_register(), dest->as_register()); 844 845 } else if (dest->is_double_cpu()) { 846 #ifdef _LP64 847 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { 848 // Surprising to me but we can see move of a long to t_object 849 __ verify_oop(src->as_register()); 850 move_regs(src->as_register(), dest->as_register_lo()); 851 return; 852 } 853 #endif 854 assert(src->is_double_cpu(), "must match"); 855 Register f_lo = src->as_register_lo(); 856 Register f_hi = src->as_register_hi(); 857 Register t_lo = dest->as_register_lo(); 858 Register t_hi = dest->as_register_hi(); 859 #ifdef _LP64 860 assert(f_hi == f_lo, "must be same"); 861 assert(t_hi == t_lo, "must be same"); 862 move_regs(f_lo, t_lo); 863 #else 864 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 865 866 867 if (f_lo == t_hi && f_hi == t_lo) { 868 swap_reg(f_lo, f_hi); 869 } else if (f_hi == t_lo) { 870 assert(f_lo != t_hi, "overwriting register"); 871 move_regs(f_hi, t_hi); 872 move_regs(f_lo, t_lo); 873 } else { 874 assert(f_hi != t_lo, "overwriting register"); 875 move_regs(f_lo, t_lo); 876 move_regs(f_hi, t_hi); 877 } 878 #endif // LP64 879 880 // special moves from fpu-register to xmm-register 881 // necessary for method results 882 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 883 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 884 __ fld_s(Address(rsp, 0)); 885 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 886 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 887 __ fld_d(Address(rsp, 0)); 888 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 889 __ fstp_s(Address(rsp, 0)); 890 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 891 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 892 __ fstp_d(Address(rsp, 0)); 893 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 894 895 // move between xmm-registers 896 } else if (dest->is_single_xmm()) { 897 assert(src->is_single_xmm(), "must match"); 898 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 899 } else if (dest->is_double_xmm()) { 900 assert(src->is_double_xmm(), "must match"); 901 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 902 903 // move between fpu-registers (no instruction necessary because of fpu-stack) 904 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 905 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 906 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 907 } else { 908 ShouldNotReachHere(); 909 } 910 } 911 912 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 913 assert(src->is_register(), "should not call otherwise"); 914 assert(dest->is_stack(), "should not call otherwise"); 915 916 if (src->is_single_cpu()) { 917 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 918 if (type == T_OBJECT || type == T_ARRAY) { 919 __ verify_oop(src->as_register()); 920 __ movptr (dst, src->as_register()); 921 } else if (type == T_METADATA) { 922 __ movptr (dst, src->as_register()); 923 } else { 924 __ movl (dst, src->as_register()); 925 } 926 927 } else if (src->is_double_cpu()) { 928 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 929 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 930 __ movptr (dstLO, src->as_register_lo()); 931 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 932 933 } else if (src->is_single_xmm()) { 934 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 935 __ movflt(dst_addr, src->as_xmm_float_reg()); 936 937 } else if (src->is_double_xmm()) { 938 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 939 __ movdbl(dst_addr, src->as_xmm_double_reg()); 940 941 } else if (src->is_single_fpu()) { 942 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 943 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 944 if (pop_fpu_stack) __ fstp_s (dst_addr); 945 else __ fst_s (dst_addr); 946 947 } else if (src->is_double_fpu()) { 948 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 949 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 950 if (pop_fpu_stack) __ fstp_d (dst_addr); 951 else __ fst_d (dst_addr); 952 953 } else { 954 ShouldNotReachHere(); 955 } 956 } 957 958 959 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { 960 LIR_Address* to_addr = dest->as_address_ptr(); 961 PatchingStub* patch = NULL; 962 Register compressed_src = rscratch1; 963 964 if (type == T_ARRAY || type == T_OBJECT) { 965 __ verify_oop(src->as_register()); 966 #ifdef _LP64 967 if (UseCompressedOops && !wide) { 968 __ movptr(compressed_src, src->as_register()); 969 __ encode_heap_oop(compressed_src); 970 if (patch_code != lir_patch_none) { 971 info->oop_map()->set_narrowoop(compressed_src->as_VMReg()); 972 } 973 } 974 #endif 975 } 976 977 if (patch_code != lir_patch_none) { 978 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 979 Address toa = as_Address(to_addr); 980 assert(toa.disp() != 0, "must have"); 981 } 982 983 int null_check_here = code_offset(); 984 switch (type) { 985 case T_FLOAT: { 986 if (src->is_single_xmm()) { 987 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 988 } else { 989 assert(src->is_single_fpu(), "must be"); 990 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 991 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 992 else __ fst_s (as_Address(to_addr)); 993 } 994 break; 995 } 996 997 case T_DOUBLE: { 998 if (src->is_double_xmm()) { 999 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 1000 } else { 1001 assert(src->is_double_fpu(), "must be"); 1002 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 1003 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 1004 else __ fst_d (as_Address(to_addr)); 1005 } 1006 break; 1007 } 1008 1009 case T_ARRAY: // fall through 1010 case T_OBJECT: // fall through 1011 if (UseCompressedOops && !wide) { 1012 __ movl(as_Address(to_addr), compressed_src); 1013 } else { 1014 __ movptr(as_Address(to_addr), src->as_register()); 1015 } 1016 break; 1017 case T_METADATA: 1018 // We get here to store a method pointer to the stack to pass to 1019 // a dtrace runtime call. This can't work on 64 bit with 1020 // compressed klass ptrs: T_METADATA can be a compressed klass 1021 // ptr or a 64 bit method pointer. 1022 LP64_ONLY(ShouldNotReachHere()); 1023 __ movptr(as_Address(to_addr), src->as_register()); 1024 break; 1025 case T_ADDRESS: 1026 __ movptr(as_Address(to_addr), src->as_register()); 1027 break; 1028 case T_INT: 1029 __ movl(as_Address(to_addr), src->as_register()); 1030 break; 1031 1032 case T_LONG: { 1033 Register from_lo = src->as_register_lo(); 1034 Register from_hi = src->as_register_hi(); 1035 #ifdef _LP64 1036 __ movptr(as_Address_lo(to_addr), from_lo); 1037 #else 1038 Register base = to_addr->base()->as_register(); 1039 Register index = noreg; 1040 if (to_addr->index()->is_register()) { 1041 index = to_addr->index()->as_register(); 1042 } 1043 if (base == from_lo || index == from_lo) { 1044 assert(base != from_hi, "can't be"); 1045 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1046 __ movl(as_Address_hi(to_addr), from_hi); 1047 if (patch != NULL) { 1048 patching_epilog(patch, lir_patch_high, base, info); 1049 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1050 patch_code = lir_patch_low; 1051 } 1052 __ movl(as_Address_lo(to_addr), from_lo); 1053 } else { 1054 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1055 __ movl(as_Address_lo(to_addr), from_lo); 1056 if (patch != NULL) { 1057 patching_epilog(patch, lir_patch_low, base, info); 1058 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1059 patch_code = lir_patch_high; 1060 } 1061 __ movl(as_Address_hi(to_addr), from_hi); 1062 } 1063 #endif // _LP64 1064 break; 1065 } 1066 1067 case T_BYTE: // fall through 1068 case T_BOOLEAN: { 1069 Register src_reg = src->as_register(); 1070 Address dst_addr = as_Address(to_addr); 1071 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1072 __ movb(dst_addr, src_reg); 1073 break; 1074 } 1075 1076 case T_CHAR: // fall through 1077 case T_SHORT: 1078 __ movw(as_Address(to_addr), src->as_register()); 1079 break; 1080 1081 default: 1082 ShouldNotReachHere(); 1083 } 1084 if (info != NULL) { 1085 add_debug_info_for_null_check(null_check_here, info); 1086 } 1087 1088 if (patch_code != lir_patch_none) { 1089 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1090 } 1091 } 1092 1093 1094 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1095 assert(src->is_stack(), "should not call otherwise"); 1096 assert(dest->is_register(), "should not call otherwise"); 1097 1098 if (dest->is_single_cpu()) { 1099 if (type == T_ARRAY || type == T_OBJECT) { 1100 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1101 __ verify_oop(dest->as_register()); 1102 } else if (type == T_METADATA) { 1103 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1104 } else { 1105 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1106 } 1107 1108 } else if (dest->is_double_cpu()) { 1109 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1110 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1111 __ movptr(dest->as_register_lo(), src_addr_LO); 1112 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1113 1114 } else if (dest->is_single_xmm()) { 1115 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1116 __ movflt(dest->as_xmm_float_reg(), src_addr); 1117 1118 } else if (dest->is_double_xmm()) { 1119 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1120 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1121 1122 } else if (dest->is_single_fpu()) { 1123 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1124 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1125 __ fld_s(src_addr); 1126 1127 } else if (dest->is_double_fpu()) { 1128 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1129 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1130 __ fld_d(src_addr); 1131 1132 } else { 1133 ShouldNotReachHere(); 1134 } 1135 } 1136 1137 1138 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1139 if (src->is_single_stack()) { 1140 if (type == T_OBJECT || type == T_ARRAY) { 1141 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1142 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1143 } else { 1144 #ifndef _LP64 1145 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1146 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1147 #else 1148 //no pushl on 64bits 1149 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1150 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1151 #endif 1152 } 1153 1154 } else if (src->is_double_stack()) { 1155 #ifdef _LP64 1156 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1157 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1158 #else 1159 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1160 // push and pop the part at src + wordSize, adding wordSize for the previous push 1161 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1162 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1163 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1164 #endif // _LP64 1165 1166 } else { 1167 ShouldNotReachHere(); 1168 } 1169 } 1170 1171 1172 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { 1173 assert(src->is_address(), "should not call otherwise"); 1174 assert(dest->is_register(), "should not call otherwise"); 1175 1176 LIR_Address* addr = src->as_address_ptr(); 1177 Address from_addr = as_Address(addr); 1178 1179 if (addr->base()->type() == T_OBJECT) { 1180 __ verify_oop(addr->base()->as_pointer_register()); 1181 } 1182 1183 switch (type) { 1184 case T_BOOLEAN: // fall through 1185 case T_BYTE: // fall through 1186 case T_CHAR: // fall through 1187 case T_SHORT: 1188 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1189 // on pre P6 processors we may get partial register stalls 1190 // so blow away the value of to_rinfo before loading a 1191 // partial word into it. Do it here so that it precedes 1192 // the potential patch point below. 1193 __ xorptr(dest->as_register(), dest->as_register()); 1194 } 1195 break; 1196 default: 1197 break; 1198 } 1199 1200 PatchingStub* patch = NULL; 1201 if (patch_code != lir_patch_none) { 1202 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1203 assert(from_addr.disp() != 0, "must have"); 1204 } 1205 if (info != NULL) { 1206 add_debug_info_for_null_check_here(info); 1207 } 1208 1209 switch (type) { 1210 case T_FLOAT: { 1211 if (dest->is_single_xmm()) { 1212 __ movflt(dest->as_xmm_float_reg(), from_addr); 1213 } else { 1214 assert(dest->is_single_fpu(), "must be"); 1215 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1216 __ fld_s(from_addr); 1217 } 1218 break; 1219 } 1220 1221 case T_DOUBLE: { 1222 if (dest->is_double_xmm()) { 1223 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1224 } else { 1225 assert(dest->is_double_fpu(), "must be"); 1226 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1227 __ fld_d(from_addr); 1228 } 1229 break; 1230 } 1231 1232 case T_OBJECT: // fall through 1233 case T_ARRAY: // fall through 1234 if (UseCompressedOops && !wide) { 1235 __ movl(dest->as_register(), from_addr); 1236 } else { 1237 __ movptr(dest->as_register(), from_addr); 1238 } 1239 break; 1240 1241 case T_ADDRESS: 1242 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1243 __ movl(dest->as_register(), from_addr); 1244 } else { 1245 __ movptr(dest->as_register(), from_addr); 1246 } 1247 break; 1248 case T_INT: 1249 __ movl(dest->as_register(), from_addr); 1250 break; 1251 1252 case T_LONG: { 1253 Register to_lo = dest->as_register_lo(); 1254 Register to_hi = dest->as_register_hi(); 1255 #ifdef _LP64 1256 __ movptr(to_lo, as_Address_lo(addr)); 1257 #else 1258 Register base = addr->base()->as_register(); 1259 Register index = noreg; 1260 if (addr->index()->is_register()) { 1261 index = addr->index()->as_register(); 1262 } 1263 if ((base == to_lo && index == to_hi) || 1264 (base == to_hi && index == to_lo)) { 1265 // addresses with 2 registers are only formed as a result of 1266 // array access so this code will never have to deal with 1267 // patches or null checks. 1268 assert(info == NULL && patch == NULL, "must be"); 1269 __ lea(to_hi, as_Address(addr)); 1270 __ movl(to_lo, Address(to_hi, 0)); 1271 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1272 } else if (base == to_lo || index == to_lo) { 1273 assert(base != to_hi, "can't be"); 1274 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1275 __ movl(to_hi, as_Address_hi(addr)); 1276 if (patch != NULL) { 1277 patching_epilog(patch, lir_patch_high, base, info); 1278 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1279 patch_code = lir_patch_low; 1280 } 1281 __ movl(to_lo, as_Address_lo(addr)); 1282 } else { 1283 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1284 __ movl(to_lo, as_Address_lo(addr)); 1285 if (patch != NULL) { 1286 patching_epilog(patch, lir_patch_low, base, info); 1287 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1288 patch_code = lir_patch_high; 1289 } 1290 __ movl(to_hi, as_Address_hi(addr)); 1291 } 1292 #endif // _LP64 1293 break; 1294 } 1295 1296 case T_BOOLEAN: // fall through 1297 case T_BYTE: { 1298 Register dest_reg = dest->as_register(); 1299 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1300 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1301 __ movsbl(dest_reg, from_addr); 1302 } else { 1303 __ movb(dest_reg, from_addr); 1304 __ shll(dest_reg, 24); 1305 __ sarl(dest_reg, 24); 1306 } 1307 break; 1308 } 1309 1310 case T_CHAR: { 1311 Register dest_reg = dest->as_register(); 1312 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1313 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1314 __ movzwl(dest_reg, from_addr); 1315 } else { 1316 __ movw(dest_reg, from_addr); 1317 } 1318 break; 1319 } 1320 1321 case T_SHORT: { 1322 Register dest_reg = dest->as_register(); 1323 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1324 __ movswl(dest_reg, from_addr); 1325 } else { 1326 __ movw(dest_reg, from_addr); 1327 __ shll(dest_reg, 16); 1328 __ sarl(dest_reg, 16); 1329 } 1330 break; 1331 } 1332 1333 default: 1334 ShouldNotReachHere(); 1335 } 1336 1337 if (patch != NULL) { 1338 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1339 } 1340 1341 if (type == T_ARRAY || type == T_OBJECT) { 1342 #ifdef _LP64 1343 if (UseCompressedOops && !wide) { 1344 __ decode_heap_oop(dest->as_register()); 1345 } 1346 #endif 1347 __ verify_oop(dest->as_register()); 1348 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1349 #ifdef _LP64 1350 if (UseCompressedClassPointers) { 1351 __ decode_klass_not_null(dest->as_register()); 1352 } 1353 #endif 1354 } 1355 } 1356 1357 1358 NEEDS_CLEANUP; // This could be static? 1359 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1360 int elem_size = type2aelembytes(type); 1361 switch (elem_size) { 1362 case 1: return Address::times_1; 1363 case 2: return Address::times_2; 1364 case 4: return Address::times_4; 1365 case 8: return Address::times_8; 1366 } 1367 ShouldNotReachHere(); 1368 return Address::no_scale; 1369 } 1370 1371 1372 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1373 switch (op->code()) { 1374 case lir_idiv: 1375 case lir_irem: 1376 arithmetic_idiv(op->code(), 1377 op->in_opr1(), 1378 op->in_opr2(), 1379 op->in_opr3(), 1380 op->result_opr(), 1381 op->info()); 1382 break; 1383 case lir_fmad: 1384 __ fmad(op->result_opr()->as_xmm_double_reg(), 1385 op->in_opr1()->as_xmm_double_reg(), 1386 op->in_opr2()->as_xmm_double_reg(), 1387 op->in_opr3()->as_xmm_double_reg()); 1388 break; 1389 case lir_fmaf: 1390 __ fmaf(op->result_opr()->as_xmm_float_reg(), 1391 op->in_opr1()->as_xmm_float_reg(), 1392 op->in_opr2()->as_xmm_float_reg(), 1393 op->in_opr3()->as_xmm_float_reg()); 1394 break; 1395 default: ShouldNotReachHere(); break; 1396 } 1397 } 1398 1399 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1400 #ifdef ASSERT 1401 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1402 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1403 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1404 #endif 1405 1406 if (op->cond() == lir_cond_always) { 1407 if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1408 __ jmp (*(op->label())); 1409 } else { 1410 Assembler::Condition acond = Assembler::zero; 1411 if (op->code() == lir_cond_float_branch) { 1412 assert(op->ublock() != NULL, "must have unordered successor"); 1413 __ jcc(Assembler::parity, *(op->ublock()->label())); 1414 switch(op->cond()) { 1415 case lir_cond_equal: acond = Assembler::equal; break; 1416 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1417 case lir_cond_less: acond = Assembler::below; break; 1418 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1419 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1420 case lir_cond_greater: acond = Assembler::above; break; 1421 default: ShouldNotReachHere(); 1422 } 1423 } else { 1424 switch (op->cond()) { 1425 case lir_cond_equal: acond = Assembler::equal; break; 1426 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1427 case lir_cond_less: acond = Assembler::less; break; 1428 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1429 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1430 case lir_cond_greater: acond = Assembler::greater; break; 1431 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1432 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1433 default: ShouldNotReachHere(); 1434 } 1435 } 1436 __ jcc(acond,*(op->label())); 1437 } 1438 } 1439 1440 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1441 LIR_Opr src = op->in_opr(); 1442 LIR_Opr dest = op->result_opr(); 1443 1444 switch (op->bytecode()) { 1445 case Bytecodes::_i2l: 1446 #ifdef _LP64 1447 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1448 #else 1449 move_regs(src->as_register(), dest->as_register_lo()); 1450 move_regs(src->as_register(), dest->as_register_hi()); 1451 __ sarl(dest->as_register_hi(), 31); 1452 #endif // LP64 1453 break; 1454 1455 case Bytecodes::_l2i: 1456 #ifdef _LP64 1457 __ movl(dest->as_register(), src->as_register_lo()); 1458 #else 1459 move_regs(src->as_register_lo(), dest->as_register()); 1460 #endif 1461 break; 1462 1463 case Bytecodes::_i2b: 1464 move_regs(src->as_register(), dest->as_register()); 1465 __ sign_extend_byte(dest->as_register()); 1466 break; 1467 1468 case Bytecodes::_i2c: 1469 move_regs(src->as_register(), dest->as_register()); 1470 __ andl(dest->as_register(), 0xFFFF); 1471 break; 1472 1473 case Bytecodes::_i2s: 1474 move_regs(src->as_register(), dest->as_register()); 1475 __ sign_extend_short(dest->as_register()); 1476 break; 1477 1478 1479 case Bytecodes::_f2d: 1480 case Bytecodes::_d2f: 1481 if (dest->is_single_xmm()) { 1482 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1483 } else if (dest->is_double_xmm()) { 1484 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1485 } else { 1486 assert(src->fpu() == dest->fpu(), "register must be equal"); 1487 // do nothing (float result is rounded later through spilling) 1488 } 1489 break; 1490 1491 case Bytecodes::_i2f: 1492 case Bytecodes::_i2d: 1493 if (dest->is_single_xmm()) { 1494 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1495 } else if (dest->is_double_xmm()) { 1496 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1497 } else { 1498 assert(dest->fpu() == 0, "result must be on TOS"); 1499 __ movl(Address(rsp, 0), src->as_register()); 1500 __ fild_s(Address(rsp, 0)); 1501 } 1502 break; 1503 1504 case Bytecodes::_f2i: 1505 case Bytecodes::_d2i: 1506 if (src->is_single_xmm()) { 1507 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1508 } else if (src->is_double_xmm()) { 1509 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1510 } else { 1511 assert(src->fpu() == 0, "input must be on TOS"); 1512 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 1513 __ fist_s(Address(rsp, 0)); 1514 __ movl(dest->as_register(), Address(rsp, 0)); 1515 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1516 } 1517 1518 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1519 assert(op->stub() != NULL, "stub required"); 1520 __ cmpl(dest->as_register(), 0x80000000); 1521 __ jcc(Assembler::equal, *op->stub()->entry()); 1522 __ bind(*op->stub()->continuation()); 1523 break; 1524 1525 case Bytecodes::_l2f: 1526 case Bytecodes::_l2d: 1527 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1528 assert(dest->fpu() == 0, "result must be on TOS"); 1529 1530 __ movptr(Address(rsp, 0), src->as_register_lo()); 1531 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); 1532 __ fild_d(Address(rsp, 0)); 1533 // float result is rounded later through spilling 1534 break; 1535 1536 case Bytecodes::_f2l: 1537 case Bytecodes::_d2l: 1538 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1539 assert(src->fpu() == 0, "input must be on TOS"); 1540 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1541 1542 // instruction sequence too long to inline it here 1543 { 1544 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1545 } 1546 break; 1547 1548 default: ShouldNotReachHere(); 1549 } 1550 } 1551 1552 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1553 if (op->init_check()) { 1554 add_debug_info_for_null_check_here(op->stub()->info()); 1555 __ cmpb(Address(op->klass()->as_register(), 1556 InstanceKlass::init_state_offset()), 1557 InstanceKlass::fully_initialized); 1558 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1559 } 1560 __ allocate_object(op->obj()->as_register(), 1561 op->tmp1()->as_register(), 1562 op->tmp2()->as_register(), 1563 op->header_size(), 1564 op->object_size(), 1565 op->klass()->as_register(), 1566 *op->stub()->entry()); 1567 __ bind(*op->stub()->continuation()); 1568 } 1569 1570 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1571 Register len = op->len()->as_register(); 1572 LP64_ONLY( __ movslq(len, len); ) 1573 1574 if (UseSlowPath || 1575 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 1576 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 1577 __ jmp(*op->stub()->entry()); 1578 } else { 1579 Register tmp1 = op->tmp1()->as_register(); 1580 Register tmp2 = op->tmp2()->as_register(); 1581 Register tmp3 = op->tmp3()->as_register(); 1582 if (len == tmp1) { 1583 tmp1 = tmp3; 1584 } else if (len == tmp2) { 1585 tmp2 = tmp3; 1586 } else if (len == tmp3) { 1587 // everything is ok 1588 } else { 1589 __ mov(tmp3, len); 1590 } 1591 __ allocate_array(op->obj()->as_register(), 1592 len, 1593 tmp1, 1594 tmp2, 1595 arrayOopDesc::header_size(op->type()), 1596 array_element_size(op->type()), 1597 op->klass()->as_register(), 1598 *op->stub()->entry()); 1599 } 1600 __ bind(*op->stub()->continuation()); 1601 } 1602 1603 void LIR_Assembler::type_profile_helper(Register mdo, 1604 ciMethodData *md, ciProfileData *data, 1605 Register recv, Label* update_done) { 1606 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1607 Label next_test; 1608 // See if the receiver is receiver[n]. 1609 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1610 __ jccb(Assembler::notEqual, next_test); 1611 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1612 __ addptr(data_addr, DataLayout::counter_increment); 1613 __ jmp(*update_done); 1614 __ bind(next_test); 1615 } 1616 1617 // Didn't find receiver; find next empty slot and fill it in 1618 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1619 Label next_test; 1620 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 1621 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); 1622 __ jccb(Assembler::notEqual, next_test); 1623 __ movptr(recv_addr, recv); 1624 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); 1625 __ jmp(*update_done); 1626 __ bind(next_test); 1627 } 1628 } 1629 1630 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1631 // we always need a stub for the failure case. 1632 CodeStub* stub = op->stub(); 1633 Register obj = op->object()->as_register(); 1634 Register k_RInfo = op->tmp1()->as_register(); 1635 Register klass_RInfo = op->tmp2()->as_register(); 1636 Register dst = op->result_opr()->as_register(); 1637 ciKlass* k = op->klass(); 1638 Register Rtmp1 = noreg; 1639 1640 // check if it needs to be profiled 1641 ciMethodData* md = NULL; 1642 ciProfileData* data = NULL; 1643 1644 if (op->should_profile()) { 1645 ciMethod* method = op->profiled_method(); 1646 assert(method != NULL, "Should have method"); 1647 int bci = op->profiled_bci(); 1648 md = method->method_data_or_null(); 1649 assert(md != NULL, "Sanity"); 1650 data = md->bci_to_data(bci); 1651 assert(data != NULL, "need data for type check"); 1652 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1653 } 1654 Label profile_cast_success, profile_cast_failure; 1655 Label *success_target = op->should_profile() ? &profile_cast_success : success; 1656 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 1657 1658 if (obj == k_RInfo) { 1659 k_RInfo = dst; 1660 } else if (obj == klass_RInfo) { 1661 klass_RInfo = dst; 1662 } 1663 if (k->is_loaded() && !UseCompressedClassPointers) { 1664 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1665 } else { 1666 Rtmp1 = op->tmp3()->as_register(); 1667 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1668 } 1669 1670 assert_different_registers(obj, k_RInfo, klass_RInfo); 1671 1672 __ cmpptr(obj, (int32_t)NULL_WORD); 1673 if (op->should_profile()) { 1674 Label not_null; 1675 __ jccb(Assembler::notEqual, not_null); 1676 // Object is null; update MDO and exit 1677 Register mdo = klass_RInfo; 1678 __ mov_metadata(mdo, md->constant_encoding()); 1679 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1680 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1681 __ orl(data_addr, header_bits); 1682 __ jmp(*obj_is_null); 1683 __ bind(not_null); 1684 } else { 1685 __ jcc(Assembler::equal, *obj_is_null); 1686 } 1687 1688 if (!k->is_loaded()) { 1689 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 1690 } else { 1691 #ifdef _LP64 1692 __ mov_metadata(k_RInfo, k->constant_encoding()); 1693 #endif // _LP64 1694 } 1695 __ verify_oop(obj); 1696 1697 if (op->fast_check()) { 1698 // get object class 1699 // not a safepoint as obj null check happens earlier 1700 #ifdef _LP64 1701 if (UseCompressedClassPointers) { 1702 __ load_klass(Rtmp1, obj); 1703 __ cmpptr(k_RInfo, Rtmp1); 1704 } else { 1705 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1706 } 1707 #else 1708 if (k->is_loaded()) { 1709 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 1710 } else { 1711 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1712 } 1713 #endif 1714 __ jcc(Assembler::notEqual, *failure_target); 1715 // successful cast, fall through to profile or jump 1716 } else { 1717 // get object class 1718 // not a safepoint as obj null check happens earlier 1719 __ load_klass(klass_RInfo, obj); 1720 if (k->is_loaded()) { 1721 // See if we get an immediate positive hit 1722 #ifdef _LP64 1723 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1724 #else 1725 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1726 #endif // _LP64 1727 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1728 __ jcc(Assembler::notEqual, *failure_target); 1729 // successful cast, fall through to profile or jump 1730 } else { 1731 // See if we get an immediate positive hit 1732 __ jcc(Assembler::equal, *success_target); 1733 // check for self 1734 #ifdef _LP64 1735 __ cmpptr(klass_RInfo, k_RInfo); 1736 #else 1737 __ cmpklass(klass_RInfo, k->constant_encoding()); 1738 #endif // _LP64 1739 __ jcc(Assembler::equal, *success_target); 1740 1741 __ push(klass_RInfo); 1742 #ifdef _LP64 1743 __ push(k_RInfo); 1744 #else 1745 __ pushklass(k->constant_encoding()); 1746 #endif // _LP64 1747 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1748 __ pop(klass_RInfo); 1749 __ pop(klass_RInfo); 1750 // result is a boolean 1751 __ cmpl(klass_RInfo, 0); 1752 __ jcc(Assembler::equal, *failure_target); 1753 // successful cast, fall through to profile or jump 1754 } 1755 } else { 1756 // perform the fast part of the checking logic 1757 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1758 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1759 __ push(klass_RInfo); 1760 __ push(k_RInfo); 1761 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1762 __ pop(klass_RInfo); 1763 __ pop(k_RInfo); 1764 // result is a boolean 1765 __ cmpl(k_RInfo, 0); 1766 __ jcc(Assembler::equal, *failure_target); 1767 // successful cast, fall through to profile or jump 1768 } 1769 } 1770 if (op->should_profile()) { 1771 Register mdo = klass_RInfo, recv = k_RInfo; 1772 __ bind(profile_cast_success); 1773 __ mov_metadata(mdo, md->constant_encoding()); 1774 __ load_klass(recv, obj); 1775 Label update_done; 1776 type_profile_helper(mdo, md, data, recv, success); 1777 __ jmp(*success); 1778 1779 __ bind(profile_cast_failure); 1780 __ mov_metadata(mdo, md->constant_encoding()); 1781 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1782 __ subptr(counter_addr, DataLayout::counter_increment); 1783 __ jmp(*failure); 1784 } 1785 __ jmp(*success); 1786 } 1787 1788 1789 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1790 LIR_Code code = op->code(); 1791 if (code == lir_store_check) { 1792 Register value = op->object()->as_register(); 1793 Register array = op->array()->as_register(); 1794 Register k_RInfo = op->tmp1()->as_register(); 1795 Register klass_RInfo = op->tmp2()->as_register(); 1796 Register Rtmp1 = op->tmp3()->as_register(); 1797 1798 CodeStub* stub = op->stub(); 1799 1800 // check if it needs to be profiled 1801 ciMethodData* md = NULL; 1802 ciProfileData* data = NULL; 1803 1804 if (op->should_profile()) { 1805 ciMethod* method = op->profiled_method(); 1806 assert(method != NULL, "Should have method"); 1807 int bci = op->profiled_bci(); 1808 md = method->method_data_or_null(); 1809 assert(md != NULL, "Sanity"); 1810 data = md->bci_to_data(bci); 1811 assert(data != NULL, "need data for type check"); 1812 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1813 } 1814 Label profile_cast_success, profile_cast_failure, done; 1815 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 1816 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 1817 1818 __ cmpptr(value, (int32_t)NULL_WORD); 1819 if (op->should_profile()) { 1820 Label not_null; 1821 __ jccb(Assembler::notEqual, not_null); 1822 // Object is null; update MDO and exit 1823 Register mdo = klass_RInfo; 1824 __ mov_metadata(mdo, md->constant_encoding()); 1825 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1826 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1827 __ orl(data_addr, header_bits); 1828 __ jmp(done); 1829 __ bind(not_null); 1830 } else { 1831 __ jcc(Assembler::equal, done); 1832 } 1833 1834 add_debug_info_for_null_check_here(op->info_for_exception()); 1835 __ load_klass(k_RInfo, array); 1836 __ load_klass(klass_RInfo, value); 1837 1838 // get instance klass (it's already uncompressed) 1839 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 1840 // perform the fast part of the checking logic 1841 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1842 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1843 __ push(klass_RInfo); 1844 __ push(k_RInfo); 1845 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1846 __ pop(klass_RInfo); 1847 __ pop(k_RInfo); 1848 // result is a boolean 1849 __ cmpl(k_RInfo, 0); 1850 __ jcc(Assembler::equal, *failure_target); 1851 // fall through to the success case 1852 1853 if (op->should_profile()) { 1854 Register mdo = klass_RInfo, recv = k_RInfo; 1855 __ bind(profile_cast_success); 1856 __ mov_metadata(mdo, md->constant_encoding()); 1857 __ load_klass(recv, value); 1858 Label update_done; 1859 type_profile_helper(mdo, md, data, recv, &done); 1860 __ jmpb(done); 1861 1862 __ bind(profile_cast_failure); 1863 __ mov_metadata(mdo, md->constant_encoding()); 1864 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1865 __ subptr(counter_addr, DataLayout::counter_increment); 1866 __ jmp(*stub->entry()); 1867 } 1868 1869 __ bind(done); 1870 } else 1871 if (code == lir_checkcast) { 1872 Register obj = op->object()->as_register(); 1873 Register dst = op->result_opr()->as_register(); 1874 Label success; 1875 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1876 __ bind(success); 1877 if (dst != obj) { 1878 __ mov(dst, obj); 1879 } 1880 } else 1881 if (code == lir_instanceof) { 1882 Register obj = op->object()->as_register(); 1883 Register dst = op->result_opr()->as_register(); 1884 Label success, failure, done; 1885 emit_typecheck_helper(op, &success, &failure, &failure); 1886 __ bind(failure); 1887 __ xorptr(dst, dst); 1888 __ jmpb(done); 1889 __ bind(success); 1890 __ movptr(dst, 1); 1891 __ bind(done); 1892 } else { 1893 ShouldNotReachHere(); 1894 } 1895 1896 } 1897 1898 1899 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1900 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { 1901 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1902 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1903 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1904 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1905 Register addr = op->addr()->as_register(); 1906 if (os::is_MP()) { 1907 __ lock(); 1908 } 1909 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1910 1911 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1912 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1913 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1914 Register newval = op->new_value()->as_register(); 1915 Register cmpval = op->cmp_value()->as_register(); 1916 assert(cmpval == rax, "wrong register"); 1917 assert(newval != NULL, "new val must be register"); 1918 assert(cmpval != newval, "cmp and new values must be in different registers"); 1919 assert(cmpval != addr, "cmp and addr must be in different registers"); 1920 assert(newval != addr, "new value and addr must be in different registers"); 1921 1922 if ( op->code() == lir_cas_obj) { 1923 #ifdef _LP64 1924 if (UseCompressedOops) { 1925 __ encode_heap_oop(cmpval); 1926 __ mov(rscratch1, newval); 1927 __ encode_heap_oop(rscratch1); 1928 if (os::is_MP()) { 1929 __ lock(); 1930 } 1931 // cmpval (rax) is implicitly used by this instruction 1932 __ cmpxchgl(rscratch1, Address(addr, 0)); 1933 } else 1934 #endif 1935 { 1936 if (os::is_MP()) { 1937 __ lock(); 1938 } 1939 __ cmpxchgptr(newval, Address(addr, 0)); 1940 } 1941 } else { 1942 assert(op->code() == lir_cas_int, "lir_cas_int expected"); 1943 if (os::is_MP()) { 1944 __ lock(); 1945 } 1946 __ cmpxchgl(newval, Address(addr, 0)); 1947 } 1948 #ifdef _LP64 1949 } else if (op->code() == lir_cas_long) { 1950 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1951 Register newval = op->new_value()->as_register_lo(); 1952 Register cmpval = op->cmp_value()->as_register_lo(); 1953 assert(cmpval == rax, "wrong register"); 1954 assert(newval != NULL, "new val must be register"); 1955 assert(cmpval != newval, "cmp and new values must be in different registers"); 1956 assert(cmpval != addr, "cmp and addr must be in different registers"); 1957 assert(newval != addr, "new value and addr must be in different registers"); 1958 if (os::is_MP()) { 1959 __ lock(); 1960 } 1961 __ cmpxchgq(newval, Address(addr, 0)); 1962 #endif // _LP64 1963 } else { 1964 Unimplemented(); 1965 } 1966 } 1967 1968 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1969 Assembler::Condition acond, ncond; 1970 switch (condition) { 1971 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 1972 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 1973 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 1974 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 1975 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 1976 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 1977 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 1978 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 1979 default: acond = Assembler::equal; ncond = Assembler::notEqual; 1980 ShouldNotReachHere(); 1981 } 1982 1983 if (opr1->is_cpu_register()) { 1984 reg2reg(opr1, result); 1985 } else if (opr1->is_stack()) { 1986 stack2reg(opr1, result, result->type()); 1987 } else if (opr1->is_constant()) { 1988 const2reg(opr1, result, lir_patch_none, NULL); 1989 } else { 1990 ShouldNotReachHere(); 1991 } 1992 1993 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 1994 // optimized version that does not require a branch 1995 if (opr2->is_single_cpu()) { 1996 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 1997 __ cmov(ncond, result->as_register(), opr2->as_register()); 1998 } else if (opr2->is_double_cpu()) { 1999 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2000 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2001 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 2002 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 2003 } else if (opr2->is_single_stack()) { 2004 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 2005 } else if (opr2->is_double_stack()) { 2006 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 2007 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 2008 } else { 2009 ShouldNotReachHere(); 2010 } 2011 2012 } else { 2013 Label skip; 2014 __ jcc (acond, skip); 2015 if (opr2->is_cpu_register()) { 2016 reg2reg(opr2, result); 2017 } else if (opr2->is_stack()) { 2018 stack2reg(opr2, result, result->type()); 2019 } else if (opr2->is_constant()) { 2020 const2reg(opr2, result, lir_patch_none, NULL); 2021 } else { 2022 ShouldNotReachHere(); 2023 } 2024 __ bind(skip); 2025 } 2026 } 2027 2028 2029 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 2030 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 2031 2032 if (left->is_single_cpu()) { 2033 assert(left == dest, "left and dest must be equal"); 2034 Register lreg = left->as_register(); 2035 2036 if (right->is_single_cpu()) { 2037 // cpu register - cpu register 2038 Register rreg = right->as_register(); 2039 switch (code) { 2040 case lir_add: __ addl (lreg, rreg); break; 2041 case lir_sub: __ subl (lreg, rreg); break; 2042 case lir_mul: __ imull(lreg, rreg); break; 2043 default: ShouldNotReachHere(); 2044 } 2045 2046 } else if (right->is_stack()) { 2047 // cpu register - stack 2048 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2049 switch (code) { 2050 case lir_add: __ addl(lreg, raddr); break; 2051 case lir_sub: __ subl(lreg, raddr); break; 2052 default: ShouldNotReachHere(); 2053 } 2054 2055 } else if (right->is_constant()) { 2056 // cpu register - constant 2057 jint c = right->as_constant_ptr()->as_jint(); 2058 switch (code) { 2059 case lir_add: { 2060 __ incrementl(lreg, c); 2061 break; 2062 } 2063 case lir_sub: { 2064 __ decrementl(lreg, c); 2065 break; 2066 } 2067 default: ShouldNotReachHere(); 2068 } 2069 2070 } else { 2071 ShouldNotReachHere(); 2072 } 2073 2074 } else if (left->is_double_cpu()) { 2075 assert(left == dest, "left and dest must be equal"); 2076 Register lreg_lo = left->as_register_lo(); 2077 Register lreg_hi = left->as_register_hi(); 2078 2079 if (right->is_double_cpu()) { 2080 // cpu register - cpu register 2081 Register rreg_lo = right->as_register_lo(); 2082 Register rreg_hi = right->as_register_hi(); 2083 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2084 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2085 switch (code) { 2086 case lir_add: 2087 __ addptr(lreg_lo, rreg_lo); 2088 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2089 break; 2090 case lir_sub: 2091 __ subptr(lreg_lo, rreg_lo); 2092 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2093 break; 2094 case lir_mul: 2095 #ifdef _LP64 2096 __ imulq(lreg_lo, rreg_lo); 2097 #else 2098 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2099 __ imull(lreg_hi, rreg_lo); 2100 __ imull(rreg_hi, lreg_lo); 2101 __ addl (rreg_hi, lreg_hi); 2102 __ mull (rreg_lo); 2103 __ addl (lreg_hi, rreg_hi); 2104 #endif // _LP64 2105 break; 2106 default: 2107 ShouldNotReachHere(); 2108 } 2109 2110 } else if (right->is_constant()) { 2111 // cpu register - constant 2112 #ifdef _LP64 2113 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2114 __ movptr(r10, (intptr_t) c); 2115 switch (code) { 2116 case lir_add: 2117 __ addptr(lreg_lo, r10); 2118 break; 2119 case lir_sub: 2120 __ subptr(lreg_lo, r10); 2121 break; 2122 default: 2123 ShouldNotReachHere(); 2124 } 2125 #else 2126 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2127 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2128 switch (code) { 2129 case lir_add: 2130 __ addptr(lreg_lo, c_lo); 2131 __ adcl(lreg_hi, c_hi); 2132 break; 2133 case lir_sub: 2134 __ subptr(lreg_lo, c_lo); 2135 __ sbbl(lreg_hi, c_hi); 2136 break; 2137 default: 2138 ShouldNotReachHere(); 2139 } 2140 #endif // _LP64 2141 2142 } else { 2143 ShouldNotReachHere(); 2144 } 2145 2146 } else if (left->is_single_xmm()) { 2147 assert(left == dest, "left and dest must be equal"); 2148 XMMRegister lreg = left->as_xmm_float_reg(); 2149 2150 if (right->is_single_xmm()) { 2151 XMMRegister rreg = right->as_xmm_float_reg(); 2152 switch (code) { 2153 case lir_add: __ addss(lreg, rreg); break; 2154 case lir_sub: __ subss(lreg, rreg); break; 2155 case lir_mul_strictfp: // fall through 2156 case lir_mul: __ mulss(lreg, rreg); break; 2157 case lir_div_strictfp: // fall through 2158 case lir_div: __ divss(lreg, rreg); break; 2159 default: ShouldNotReachHere(); 2160 } 2161 } else { 2162 Address raddr; 2163 if (right->is_single_stack()) { 2164 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2165 } else if (right->is_constant()) { 2166 // hack for now 2167 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2168 } else { 2169 ShouldNotReachHere(); 2170 } 2171 switch (code) { 2172 case lir_add: __ addss(lreg, raddr); break; 2173 case lir_sub: __ subss(lreg, raddr); break; 2174 case lir_mul_strictfp: // fall through 2175 case lir_mul: __ mulss(lreg, raddr); break; 2176 case lir_div_strictfp: // fall through 2177 case lir_div: __ divss(lreg, raddr); break; 2178 default: ShouldNotReachHere(); 2179 } 2180 } 2181 2182 } else if (left->is_double_xmm()) { 2183 assert(left == dest, "left and dest must be equal"); 2184 2185 XMMRegister lreg = left->as_xmm_double_reg(); 2186 if (right->is_double_xmm()) { 2187 XMMRegister rreg = right->as_xmm_double_reg(); 2188 switch (code) { 2189 case lir_add: __ addsd(lreg, rreg); break; 2190 case lir_sub: __ subsd(lreg, rreg); break; 2191 case lir_mul_strictfp: // fall through 2192 case lir_mul: __ mulsd(lreg, rreg); break; 2193 case lir_div_strictfp: // fall through 2194 case lir_div: __ divsd(lreg, rreg); break; 2195 default: ShouldNotReachHere(); 2196 } 2197 } else { 2198 Address raddr; 2199 if (right->is_double_stack()) { 2200 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2201 } else if (right->is_constant()) { 2202 // hack for now 2203 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2204 } else { 2205 ShouldNotReachHere(); 2206 } 2207 switch (code) { 2208 case lir_add: __ addsd(lreg, raddr); break; 2209 case lir_sub: __ subsd(lreg, raddr); break; 2210 case lir_mul_strictfp: // fall through 2211 case lir_mul: __ mulsd(lreg, raddr); break; 2212 case lir_div_strictfp: // fall through 2213 case lir_div: __ divsd(lreg, raddr); break; 2214 default: ShouldNotReachHere(); 2215 } 2216 } 2217 2218 } else if (left->is_single_fpu()) { 2219 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2220 2221 if (right->is_single_fpu()) { 2222 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2223 2224 } else { 2225 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2226 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2227 2228 Address raddr; 2229 if (right->is_single_stack()) { 2230 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2231 } else if (right->is_constant()) { 2232 address const_addr = float_constant(right->as_jfloat()); 2233 assert(const_addr != NULL, "incorrect float/double constant maintainance"); 2234 // hack for now 2235 raddr = __ as_Address(InternalAddress(const_addr)); 2236 } else { 2237 ShouldNotReachHere(); 2238 } 2239 2240 switch (code) { 2241 case lir_add: __ fadd_s(raddr); break; 2242 case lir_sub: __ fsub_s(raddr); break; 2243 case lir_mul_strictfp: // fall through 2244 case lir_mul: __ fmul_s(raddr); break; 2245 case lir_div_strictfp: // fall through 2246 case lir_div: __ fdiv_s(raddr); break; 2247 default: ShouldNotReachHere(); 2248 } 2249 } 2250 2251 } else if (left->is_double_fpu()) { 2252 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2253 2254 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2255 // Double values require special handling for strictfp mul/div on x86 2256 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); 2257 __ fmulp(left->fpu_regnrLo() + 1); 2258 } 2259 2260 if (right->is_double_fpu()) { 2261 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2262 2263 } else { 2264 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2265 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2266 2267 Address raddr; 2268 if (right->is_double_stack()) { 2269 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2270 } else if (right->is_constant()) { 2271 // hack for now 2272 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2273 } else { 2274 ShouldNotReachHere(); 2275 } 2276 2277 switch (code) { 2278 case lir_add: __ fadd_d(raddr); break; 2279 case lir_sub: __ fsub_d(raddr); break; 2280 case lir_mul_strictfp: // fall through 2281 case lir_mul: __ fmul_d(raddr); break; 2282 case lir_div_strictfp: // fall through 2283 case lir_div: __ fdiv_d(raddr); break; 2284 default: ShouldNotReachHere(); 2285 } 2286 } 2287 2288 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2289 // Double values require special handling for strictfp mul/div on x86 2290 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); 2291 __ fmulp(dest->fpu_regnrLo() + 1); 2292 } 2293 2294 } else if (left->is_single_stack() || left->is_address()) { 2295 assert(left == dest, "left and dest must be equal"); 2296 2297 Address laddr; 2298 if (left->is_single_stack()) { 2299 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2300 } else if (left->is_address()) { 2301 laddr = as_Address(left->as_address_ptr()); 2302 } else { 2303 ShouldNotReachHere(); 2304 } 2305 2306 if (right->is_single_cpu()) { 2307 Register rreg = right->as_register(); 2308 switch (code) { 2309 case lir_add: __ addl(laddr, rreg); break; 2310 case lir_sub: __ subl(laddr, rreg); break; 2311 default: ShouldNotReachHere(); 2312 } 2313 } else if (right->is_constant()) { 2314 jint c = right->as_constant_ptr()->as_jint(); 2315 switch (code) { 2316 case lir_add: { 2317 __ incrementl(laddr, c); 2318 break; 2319 } 2320 case lir_sub: { 2321 __ decrementl(laddr, c); 2322 break; 2323 } 2324 default: ShouldNotReachHere(); 2325 } 2326 } else { 2327 ShouldNotReachHere(); 2328 } 2329 2330 } else { 2331 ShouldNotReachHere(); 2332 } 2333 } 2334 2335 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2336 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2337 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2338 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2339 2340 bool left_is_tos = (left_index == 0); 2341 bool dest_is_tos = (dest_index == 0); 2342 int non_tos_index = (left_is_tos ? right_index : left_index); 2343 2344 switch (code) { 2345 case lir_add: 2346 if (pop_fpu_stack) __ faddp(non_tos_index); 2347 else if (dest_is_tos) __ fadd (non_tos_index); 2348 else __ fadda(non_tos_index); 2349 break; 2350 2351 case lir_sub: 2352 if (left_is_tos) { 2353 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2354 else if (dest_is_tos) __ fsub (non_tos_index); 2355 else __ fsubra(non_tos_index); 2356 } else { 2357 if (pop_fpu_stack) __ fsubp (non_tos_index); 2358 else if (dest_is_tos) __ fsubr (non_tos_index); 2359 else __ fsuba (non_tos_index); 2360 } 2361 break; 2362 2363 case lir_mul_strictfp: // fall through 2364 case lir_mul: 2365 if (pop_fpu_stack) __ fmulp(non_tos_index); 2366 else if (dest_is_tos) __ fmul (non_tos_index); 2367 else __ fmula(non_tos_index); 2368 break; 2369 2370 case lir_div_strictfp: // fall through 2371 case lir_div: 2372 if (left_is_tos) { 2373 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2374 else if (dest_is_tos) __ fdiv (non_tos_index); 2375 else __ fdivra(non_tos_index); 2376 } else { 2377 if (pop_fpu_stack) __ fdivp (non_tos_index); 2378 else if (dest_is_tos) __ fdivr (non_tos_index); 2379 else __ fdiva (non_tos_index); 2380 } 2381 break; 2382 2383 case lir_rem: 2384 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2385 __ fremr(noreg); 2386 break; 2387 2388 default: 2389 ShouldNotReachHere(); 2390 } 2391 } 2392 2393 2394 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { 2395 if (value->is_double_xmm()) { 2396 switch(code) { 2397 case lir_abs : 2398 { 2399 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2400 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2401 } 2402 __ andpd(dest->as_xmm_double_reg(), 2403 ExternalAddress((address)double_signmask_pool)); 2404 } 2405 break; 2406 2407 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2408 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2409 default : ShouldNotReachHere(); 2410 } 2411 2412 } else if (value->is_double_fpu()) { 2413 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2414 switch(code) { 2415 case lir_abs : __ fabs() ; break; 2416 case lir_sqrt : __ fsqrt(); break; 2417 default : ShouldNotReachHere(); 2418 } 2419 } else { 2420 Unimplemented(); 2421 } 2422 } 2423 2424 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2425 // assert(left->destroys_register(), "check"); 2426 if (left->is_single_cpu()) { 2427 Register reg = left->as_register(); 2428 if (right->is_constant()) { 2429 int val = right->as_constant_ptr()->as_jint(); 2430 switch (code) { 2431 case lir_logic_and: __ andl (reg, val); break; 2432 case lir_logic_or: __ orl (reg, val); break; 2433 case lir_logic_xor: __ xorl (reg, val); break; 2434 default: ShouldNotReachHere(); 2435 } 2436 } else if (right->is_stack()) { 2437 // added support for stack operands 2438 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2439 switch (code) { 2440 case lir_logic_and: __ andl (reg, raddr); break; 2441 case lir_logic_or: __ orl (reg, raddr); break; 2442 case lir_logic_xor: __ xorl (reg, raddr); break; 2443 default: ShouldNotReachHere(); 2444 } 2445 } else { 2446 Register rright = right->as_register(); 2447 switch (code) { 2448 case lir_logic_and: __ andptr (reg, rright); break; 2449 case lir_logic_or : __ orptr (reg, rright); break; 2450 case lir_logic_xor: __ xorptr (reg, rright); break; 2451 default: ShouldNotReachHere(); 2452 } 2453 } 2454 move_regs(reg, dst->as_register()); 2455 } else { 2456 Register l_lo = left->as_register_lo(); 2457 Register l_hi = left->as_register_hi(); 2458 if (right->is_constant()) { 2459 #ifdef _LP64 2460 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2461 switch (code) { 2462 case lir_logic_and: 2463 __ andq(l_lo, rscratch1); 2464 break; 2465 case lir_logic_or: 2466 __ orq(l_lo, rscratch1); 2467 break; 2468 case lir_logic_xor: 2469 __ xorq(l_lo, rscratch1); 2470 break; 2471 default: ShouldNotReachHere(); 2472 } 2473 #else 2474 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2475 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2476 switch (code) { 2477 case lir_logic_and: 2478 __ andl(l_lo, r_lo); 2479 __ andl(l_hi, r_hi); 2480 break; 2481 case lir_logic_or: 2482 __ orl(l_lo, r_lo); 2483 __ orl(l_hi, r_hi); 2484 break; 2485 case lir_logic_xor: 2486 __ xorl(l_lo, r_lo); 2487 __ xorl(l_hi, r_hi); 2488 break; 2489 default: ShouldNotReachHere(); 2490 } 2491 #endif // _LP64 2492 } else { 2493 #ifdef _LP64 2494 Register r_lo; 2495 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { 2496 r_lo = right->as_register(); 2497 } else { 2498 r_lo = right->as_register_lo(); 2499 } 2500 #else 2501 Register r_lo = right->as_register_lo(); 2502 Register r_hi = right->as_register_hi(); 2503 assert(l_lo != r_hi, "overwriting registers"); 2504 #endif 2505 switch (code) { 2506 case lir_logic_and: 2507 __ andptr(l_lo, r_lo); 2508 NOT_LP64(__ andptr(l_hi, r_hi);) 2509 break; 2510 case lir_logic_or: 2511 __ orptr(l_lo, r_lo); 2512 NOT_LP64(__ orptr(l_hi, r_hi);) 2513 break; 2514 case lir_logic_xor: 2515 __ xorptr(l_lo, r_lo); 2516 NOT_LP64(__ xorptr(l_hi, r_hi);) 2517 break; 2518 default: ShouldNotReachHere(); 2519 } 2520 } 2521 2522 Register dst_lo = dst->as_register_lo(); 2523 Register dst_hi = dst->as_register_hi(); 2524 2525 #ifdef _LP64 2526 move_regs(l_lo, dst_lo); 2527 #else 2528 if (dst_lo == l_hi) { 2529 assert(dst_hi != l_lo, "overwriting registers"); 2530 move_regs(l_hi, dst_hi); 2531 move_regs(l_lo, dst_lo); 2532 } else { 2533 assert(dst_lo != l_hi, "overwriting registers"); 2534 move_regs(l_lo, dst_lo); 2535 move_regs(l_hi, dst_hi); 2536 } 2537 #endif // _LP64 2538 } 2539 } 2540 2541 2542 // we assume that rax, and rdx can be overwritten 2543 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2544 2545 assert(left->is_single_cpu(), "left must be register"); 2546 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2547 assert(result->is_single_cpu(), "result must be register"); 2548 2549 // assert(left->destroys_register(), "check"); 2550 // assert(right->destroys_register(), "check"); 2551 2552 Register lreg = left->as_register(); 2553 Register dreg = result->as_register(); 2554 2555 if (right->is_constant()) { 2556 int divisor = right->as_constant_ptr()->as_jint(); 2557 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2558 if (code == lir_idiv) { 2559 assert(lreg == rax, "must be rax,"); 2560 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2561 __ cdql(); // sign extend into rdx:rax 2562 if (divisor == 2) { 2563 __ subl(lreg, rdx); 2564 } else { 2565 __ andl(rdx, divisor - 1); 2566 __ addl(lreg, rdx); 2567 } 2568 __ sarl(lreg, log2_intptr(divisor)); 2569 move_regs(lreg, dreg); 2570 } else if (code == lir_irem) { 2571 Label done; 2572 __ mov(dreg, lreg); 2573 __ andl(dreg, 0x80000000 | (divisor - 1)); 2574 __ jcc(Assembler::positive, done); 2575 __ decrement(dreg); 2576 __ orl(dreg, ~(divisor - 1)); 2577 __ increment(dreg); 2578 __ bind(done); 2579 } else { 2580 ShouldNotReachHere(); 2581 } 2582 } else { 2583 Register rreg = right->as_register(); 2584 assert(lreg == rax, "left register must be rax,"); 2585 assert(rreg != rdx, "right register must not be rdx"); 2586 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2587 2588 move_regs(lreg, rax); 2589 2590 int idivl_offset = __ corrected_idivl(rreg); 2591 if (ImplicitDiv0Checks) { 2592 add_debug_info_for_div0(idivl_offset, info); 2593 } 2594 if (code == lir_irem) { 2595 move_regs(rdx, dreg); // result is in rdx 2596 } else { 2597 move_regs(rax, dreg); 2598 } 2599 } 2600 } 2601 2602 2603 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2604 if (opr1->is_single_cpu()) { 2605 Register reg1 = opr1->as_register(); 2606 if (opr2->is_single_cpu()) { 2607 // cpu register - cpu register 2608 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2609 __ cmpoop(reg1, opr2->as_register()); 2610 } else { 2611 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); 2612 __ cmpl(reg1, opr2->as_register()); 2613 } 2614 } else if (opr2->is_stack()) { 2615 // cpu register - stack 2616 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2617 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2618 } else { 2619 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2620 } 2621 } else if (opr2->is_constant()) { 2622 // cpu register - constant 2623 LIR_Const* c = opr2->as_constant_ptr(); 2624 if (c->type() == T_INT) { 2625 __ cmpl(reg1, c->as_jint()); 2626 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2627 // In 64bit oops are single register 2628 jobject o = c->as_jobject(); 2629 if (o == NULL) { 2630 __ cmpptr(reg1, (int32_t)NULL_WORD); 2631 } else { 2632 __ cmpoop(reg1, o); 2633 } 2634 } else { 2635 fatal("unexpected type: %s", basictype_to_str(c->type())); 2636 } 2637 // cpu register - address 2638 } else if (opr2->is_address()) { 2639 if (op->info() != NULL) { 2640 add_debug_info_for_null_check_here(op->info()); 2641 } 2642 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2643 } else { 2644 ShouldNotReachHere(); 2645 } 2646 2647 } else if(opr1->is_double_cpu()) { 2648 Register xlo = opr1->as_register_lo(); 2649 Register xhi = opr1->as_register_hi(); 2650 if (opr2->is_double_cpu()) { 2651 #ifdef _LP64 2652 __ cmpptr(xlo, opr2->as_register_lo()); 2653 #else 2654 // cpu register - cpu register 2655 Register ylo = opr2->as_register_lo(); 2656 Register yhi = opr2->as_register_hi(); 2657 __ subl(xlo, ylo); 2658 __ sbbl(xhi, yhi); 2659 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2660 __ orl(xhi, xlo); 2661 } 2662 #endif // _LP64 2663 } else if (opr2->is_constant()) { 2664 // cpu register - constant 0 2665 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2666 #ifdef _LP64 2667 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2668 #else 2669 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2670 __ orl(xhi, xlo); 2671 #endif // _LP64 2672 } else { 2673 ShouldNotReachHere(); 2674 } 2675 2676 } else if (opr1->is_single_xmm()) { 2677 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2678 if (opr2->is_single_xmm()) { 2679 // xmm register - xmm register 2680 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2681 } else if (opr2->is_stack()) { 2682 // xmm register - stack 2683 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2684 } else if (opr2->is_constant()) { 2685 // xmm register - constant 2686 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2687 } else if (opr2->is_address()) { 2688 // xmm register - address 2689 if (op->info() != NULL) { 2690 add_debug_info_for_null_check_here(op->info()); 2691 } 2692 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2693 } else { 2694 ShouldNotReachHere(); 2695 } 2696 2697 } else if (opr1->is_double_xmm()) { 2698 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2699 if (opr2->is_double_xmm()) { 2700 // xmm register - xmm register 2701 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2702 } else if (opr2->is_stack()) { 2703 // xmm register - stack 2704 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2705 } else if (opr2->is_constant()) { 2706 // xmm register - constant 2707 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2708 } else if (opr2->is_address()) { 2709 // xmm register - address 2710 if (op->info() != NULL) { 2711 add_debug_info_for_null_check_here(op->info()); 2712 } 2713 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2714 } else { 2715 ShouldNotReachHere(); 2716 } 2717 2718 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2719 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2720 assert(opr2->is_fpu_register(), "both must be registers"); 2721 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2722 2723 } else if (opr1->is_address() && opr2->is_constant()) { 2724 LIR_Const* c = opr2->as_constant_ptr(); 2725 #ifdef _LP64 2726 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2727 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2728 __ movoop(rscratch1, c->as_jobject()); 2729 } 2730 #endif // LP64 2731 if (op->info() != NULL) { 2732 add_debug_info_for_null_check_here(op->info()); 2733 } 2734 // special case: address - constant 2735 LIR_Address* addr = opr1->as_address_ptr(); 2736 if (c->type() == T_INT) { 2737 __ cmpl(as_Address(addr), c->as_jint()); 2738 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2739 #ifdef _LP64 2740 // %%% Make this explode if addr isn't reachable until we figure out a 2741 // better strategy by giving noreg as the temp for as_Address 2742 __ cmpoop(rscratch1, as_Address(addr, noreg)); 2743 #else 2744 __ cmpoop(as_Address(addr), c->as_jobject()); 2745 #endif // _LP64 2746 } else { 2747 ShouldNotReachHere(); 2748 } 2749 2750 } else { 2751 ShouldNotReachHere(); 2752 } 2753 } 2754 2755 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2756 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2757 if (left->is_single_xmm()) { 2758 assert(right->is_single_xmm(), "must match"); 2759 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2760 } else if (left->is_double_xmm()) { 2761 assert(right->is_double_xmm(), "must match"); 2762 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2763 2764 } else { 2765 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2766 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2767 2768 assert(left->fpu() == 0, "left must be on TOS"); 2769 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2770 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2771 } 2772 } else { 2773 assert(code == lir_cmp_l2i, "check"); 2774 #ifdef _LP64 2775 Label done; 2776 Register dest = dst->as_register(); 2777 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2778 __ movl(dest, -1); 2779 __ jccb(Assembler::less, done); 2780 __ set_byte_if_not_zero(dest); 2781 __ movzbl(dest, dest); 2782 __ bind(done); 2783 #else 2784 __ lcmp2int(left->as_register_hi(), 2785 left->as_register_lo(), 2786 right->as_register_hi(), 2787 right->as_register_lo()); 2788 move_regs(left->as_register_hi(), dst->as_register()); 2789 #endif // _LP64 2790 } 2791 } 2792 2793 2794 void LIR_Assembler::align_call(LIR_Code code) { 2795 if (os::is_MP()) { 2796 // make sure that the displacement word of the call ends up word aligned 2797 int offset = __ offset(); 2798 switch (code) { 2799 case lir_static_call: 2800 case lir_optvirtual_call: 2801 case lir_dynamic_call: 2802 offset += NativeCall::displacement_offset; 2803 break; 2804 case lir_icvirtual_call: 2805 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2806 break; 2807 case lir_virtual_call: // currently, sparc-specific for niagara 2808 default: ShouldNotReachHere(); 2809 } 2810 __ align(BytesPerWord, offset); 2811 } 2812 } 2813 2814 2815 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2816 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2817 "must be aligned"); 2818 __ call(AddressLiteral(op->addr(), rtype)); 2819 add_call_info(code_offset(), op->info()); 2820 } 2821 2822 2823 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2824 __ ic_call(op->addr()); 2825 add_call_info(code_offset(), op->info()); 2826 assert(!os::is_MP() || 2827 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0, 2828 "must be aligned"); 2829 } 2830 2831 2832 /* Currently, vtable-dispatch is only enabled for sparc platforms */ 2833 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 2834 ShouldNotReachHere(); 2835 } 2836 2837 2838 void LIR_Assembler::emit_static_call_stub() { 2839 address call_pc = __ pc(); 2840 address stub = __ start_a_stub(call_stub_size()); 2841 if (stub == NULL) { 2842 bailout("static call stub overflow"); 2843 return; 2844 } 2845 2846 int start = __ offset(); 2847 if (os::is_MP()) { 2848 // make sure that the displacement word of the call ends up word aligned 2849 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset); 2850 } 2851 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */)); 2852 __ mov_metadata(rbx, (Metadata*)NULL); 2853 // must be set to -1 at code generation time 2854 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); 2855 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2856 __ jump(RuntimeAddress(__ pc())); 2857 2858 if (UseAOT) { 2859 // Trampoline to aot code 2860 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */)); 2861 #ifdef _LP64 2862 __ mov64(rax, CONST64(0)); // address is zapped till fixup time. 2863 #else 2864 __ movl(rax, 0xdeadffff); // address is zapped till fixup time. 2865 #endif 2866 __ jmp(rax); 2867 } 2868 assert(__ offset() - start <= call_stub_size(), "stub too big"); 2869 __ end_a_stub(); 2870 } 2871 2872 2873 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2874 assert(exceptionOop->as_register() == rax, "must match"); 2875 assert(exceptionPC->as_register() == rdx, "must match"); 2876 2877 // exception object is not added to oop map by LinearScan 2878 // (LinearScan assumes that no oops are in fixed registers) 2879 info->add_register_oop(exceptionOop); 2880 Runtime1::StubID unwind_id; 2881 2882 // get current pc information 2883 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2884 int pc_for_athrow_offset = __ offset(); 2885 InternalAddress pc_for_athrow(__ pc()); 2886 __ lea(exceptionPC->as_register(), pc_for_athrow); 2887 add_call_info(pc_for_athrow_offset, info); // for exception handler 2888 2889 __ verify_not_null_oop(rax); 2890 // search an exception handler (rax: exception oop, rdx: throwing pc) 2891 if (compilation()->has_fpu_code()) { 2892 unwind_id = Runtime1::handle_exception_id; 2893 } else { 2894 unwind_id = Runtime1::handle_exception_nofpu_id; 2895 } 2896 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2897 2898 // enough room for two byte trap 2899 __ nop(); 2900 } 2901 2902 2903 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2904 assert(exceptionOop->as_register() == rax, "must match"); 2905 2906 __ jmp(_unwind_handler_entry); 2907 } 2908 2909 2910 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2911 2912 // optimized version for linear scan: 2913 // * count must be already in ECX (guaranteed by LinearScan) 2914 // * left and dest must be equal 2915 // * tmp must be unused 2916 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 2917 assert(left == dest, "left and dest must be equal"); 2918 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2919 2920 if (left->is_single_cpu()) { 2921 Register value = left->as_register(); 2922 assert(value != SHIFT_count, "left cannot be ECX"); 2923 2924 switch (code) { 2925 case lir_shl: __ shll(value); break; 2926 case lir_shr: __ sarl(value); break; 2927 case lir_ushr: __ shrl(value); break; 2928 default: ShouldNotReachHere(); 2929 } 2930 } else if (left->is_double_cpu()) { 2931 Register lo = left->as_register_lo(); 2932 Register hi = left->as_register_hi(); 2933 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 2934 #ifdef _LP64 2935 switch (code) { 2936 case lir_shl: __ shlptr(lo); break; 2937 case lir_shr: __ sarptr(lo); break; 2938 case lir_ushr: __ shrptr(lo); break; 2939 default: ShouldNotReachHere(); 2940 } 2941 #else 2942 2943 switch (code) { 2944 case lir_shl: __ lshl(hi, lo); break; 2945 case lir_shr: __ lshr(hi, lo, true); break; 2946 case lir_ushr: __ lshr(hi, lo, false); break; 2947 default: ShouldNotReachHere(); 2948 } 2949 #endif // LP64 2950 } else { 2951 ShouldNotReachHere(); 2952 } 2953 } 2954 2955 2956 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2957 if (dest->is_single_cpu()) { 2958 // first move left into dest so that left is not destroyed by the shift 2959 Register value = dest->as_register(); 2960 count = count & 0x1F; // Java spec 2961 2962 move_regs(left->as_register(), value); 2963 switch (code) { 2964 case lir_shl: __ shll(value, count); break; 2965 case lir_shr: __ sarl(value, count); break; 2966 case lir_ushr: __ shrl(value, count); break; 2967 default: ShouldNotReachHere(); 2968 } 2969 } else if (dest->is_double_cpu()) { 2970 #ifndef _LP64 2971 Unimplemented(); 2972 #else 2973 // first move left into dest so that left is not destroyed by the shift 2974 Register value = dest->as_register_lo(); 2975 count = count & 0x1F; // Java spec 2976 2977 move_regs(left->as_register_lo(), value); 2978 switch (code) { 2979 case lir_shl: __ shlptr(value, count); break; 2980 case lir_shr: __ sarptr(value, count); break; 2981 case lir_ushr: __ shrptr(value, count); break; 2982 default: ShouldNotReachHere(); 2983 } 2984 #endif // _LP64 2985 } else { 2986 ShouldNotReachHere(); 2987 } 2988 } 2989 2990 2991 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 2992 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2993 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2994 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2995 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 2996 } 2997 2998 2999 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 3000 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3001 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3002 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3003 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 3004 } 3005 3006 3007 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 3008 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3009 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3010 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3011 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); 3012 } 3013 3014 3015 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) { 3016 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3017 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3018 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3019 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m); 3020 } 3021 3022 3023 // This code replaces a call to arraycopy; no exception may 3024 // be thrown in this code, they must be thrown in the System.arraycopy 3025 // activation frame; we could save some checks if this would not be the case 3026 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 3027 ciArrayKlass* default_type = op->expected_type(); 3028 Register src = op->src()->as_register(); 3029 Register dst = op->dst()->as_register(); 3030 Register src_pos = op->src_pos()->as_register(); 3031 Register dst_pos = op->dst_pos()->as_register(); 3032 Register length = op->length()->as_register(); 3033 Register tmp = op->tmp()->as_register(); 3034 3035 CodeStub* stub = op->stub(); 3036 int flags = op->flags(); 3037 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 3038 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 3039 3040 // if we don't know anything, just go through the generic arraycopy 3041 if (default_type == NULL) { 3042 Label done; 3043 // save outgoing arguments on stack in case call to System.arraycopy is needed 3044 // HACK ALERT. This code used to push the parameters in a hardwired fashion 3045 // for interpreter calling conventions. Now we have to do it in new style conventions. 3046 // For the moment until C1 gets the new register allocator I just force all the 3047 // args to the right place (except the register args) and then on the back side 3048 // reload the register args properly if we go slow path. Yuck 3049 3050 // These are proper for the calling convention 3051 store_parameter(length, 2); 3052 store_parameter(dst_pos, 1); 3053 store_parameter(dst, 0); 3054 3055 // these are just temporary placements until we need to reload 3056 store_parameter(src_pos, 3); 3057 store_parameter(src, 4); 3058 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3059 3060 address copyfunc_addr = StubRoutines::generic_arraycopy(); 3061 assert(copyfunc_addr != NULL, "generic arraycopy stub required"); 3062 3063 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3064 #ifdef _LP64 3065 // The arguments are in java calling convention so we can trivially shift them to C 3066 // convention 3067 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3068 __ mov(c_rarg0, j_rarg0); 3069 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3070 __ mov(c_rarg1, j_rarg1); 3071 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3072 __ mov(c_rarg2, j_rarg2); 3073 assert_different_registers(c_rarg3, j_rarg4); 3074 __ mov(c_rarg3, j_rarg3); 3075 #ifdef _WIN64 3076 // Allocate abi space for args but be sure to keep stack aligned 3077 __ subptr(rsp, 6*wordSize); 3078 store_parameter(j_rarg4, 4); 3079 #ifndef PRODUCT 3080 if (PrintC1Statistics) { 3081 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3082 } 3083 #endif 3084 __ call(RuntimeAddress(copyfunc_addr)); 3085 __ addptr(rsp, 6*wordSize); 3086 #else 3087 __ mov(c_rarg4, j_rarg4); 3088 #ifndef PRODUCT 3089 if (PrintC1Statistics) { 3090 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3091 } 3092 #endif 3093 __ call(RuntimeAddress(copyfunc_addr)); 3094 #endif // _WIN64 3095 #else 3096 __ push(length); 3097 __ push(dst_pos); 3098 __ push(dst); 3099 __ push(src_pos); 3100 __ push(src); 3101 3102 #ifndef PRODUCT 3103 if (PrintC1Statistics) { 3104 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3105 } 3106 #endif 3107 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack 3108 3109 #endif // _LP64 3110 3111 __ cmpl(rax, 0); 3112 __ jcc(Assembler::equal, *stub->continuation()); 3113 3114 __ mov(tmp, rax); 3115 __ xorl(tmp, -1); 3116 3117 // Reload values from the stack so they are where the stub 3118 // expects them. 3119 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3120 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3121 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3122 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3123 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3124 3125 __ subl(length, tmp); 3126 __ addl(src_pos, tmp); 3127 __ addl(dst_pos, tmp); 3128 __ jmp(*stub->entry()); 3129 3130 __ bind(*stub->continuation()); 3131 return; 3132 } 3133 3134 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3135 3136 int elem_size = type2aelembytes(basic_type); 3137 Address::ScaleFactor scale; 3138 3139 switch (elem_size) { 3140 case 1 : 3141 scale = Address::times_1; 3142 break; 3143 case 2 : 3144 scale = Address::times_2; 3145 break; 3146 case 4 : 3147 scale = Address::times_4; 3148 break; 3149 case 8 : 3150 scale = Address::times_8; 3151 break; 3152 default: 3153 scale = Address::no_scale; 3154 ShouldNotReachHere(); 3155 } 3156 3157 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3158 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3159 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3160 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3161 3162 // length and pos's are all sign extended at this point on 64bit 3163 3164 // test for NULL 3165 if (flags & LIR_OpArrayCopy::src_null_check) { 3166 __ testptr(src, src); 3167 __ jcc(Assembler::zero, *stub->entry()); 3168 } 3169 if (flags & LIR_OpArrayCopy::dst_null_check) { 3170 __ testptr(dst, dst); 3171 __ jcc(Assembler::zero, *stub->entry()); 3172 } 3173 3174 // If the compiler was not able to prove that exact type of the source or the destination 3175 // of the arraycopy is an array type, check at runtime if the source or the destination is 3176 // an instance type. 3177 if (flags & LIR_OpArrayCopy::type_check) { 3178 if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3179 __ load_klass(tmp, dst); 3180 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3181 __ jcc(Assembler::greaterEqual, *stub->entry()); 3182 } 3183 3184 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3185 __ load_klass(tmp, src); 3186 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3187 __ jcc(Assembler::greaterEqual, *stub->entry()); 3188 } 3189 } 3190 3191 // check if negative 3192 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3193 __ testl(src_pos, src_pos); 3194 __ jcc(Assembler::less, *stub->entry()); 3195 } 3196 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3197 __ testl(dst_pos, dst_pos); 3198 __ jcc(Assembler::less, *stub->entry()); 3199 } 3200 3201 if (flags & LIR_OpArrayCopy::src_range_check) { 3202 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3203 __ cmpl(tmp, src_length_addr); 3204 __ jcc(Assembler::above, *stub->entry()); 3205 } 3206 if (flags & LIR_OpArrayCopy::dst_range_check) { 3207 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3208 __ cmpl(tmp, dst_length_addr); 3209 __ jcc(Assembler::above, *stub->entry()); 3210 } 3211 3212 if (flags & LIR_OpArrayCopy::length_positive_check) { 3213 __ testl(length, length); 3214 __ jcc(Assembler::less, *stub->entry()); 3215 } 3216 3217 #ifdef _LP64 3218 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3219 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3220 #endif 3221 3222 if (flags & LIR_OpArrayCopy::type_check) { 3223 // We don't know the array types are compatible 3224 if (basic_type != T_OBJECT) { 3225 // Simple test for basic type arrays 3226 if (UseCompressedClassPointers) { 3227 __ movl(tmp, src_klass_addr); 3228 __ cmpl(tmp, dst_klass_addr); 3229 } else { 3230 __ movptr(tmp, src_klass_addr); 3231 __ cmpptr(tmp, dst_klass_addr); 3232 } 3233 __ jcc(Assembler::notEqual, *stub->entry()); 3234 } else { 3235 // For object arrays, if src is a sub class of dst then we can 3236 // safely do the copy. 3237 Label cont, slow; 3238 3239 __ push(src); 3240 __ push(dst); 3241 3242 __ load_klass(src, src); 3243 __ load_klass(dst, dst); 3244 3245 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); 3246 3247 __ push(src); 3248 __ push(dst); 3249 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 3250 __ pop(dst); 3251 __ pop(src); 3252 3253 __ cmpl(src, 0); 3254 __ jcc(Assembler::notEqual, cont); 3255 3256 __ bind(slow); 3257 __ pop(dst); 3258 __ pop(src); 3259 3260 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 3261 if (copyfunc_addr != NULL) { // use stub if available 3262 // src is not a sub class of dst so we have to do a 3263 // per-element check. 3264 3265 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 3266 if ((flags & mask) != mask) { 3267 // Check that at least both of them object arrays. 3268 assert(flags & mask, "one of the two should be known to be an object array"); 3269 3270 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3271 __ load_klass(tmp, src); 3272 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3273 __ load_klass(tmp, dst); 3274 } 3275 int lh_offset = in_bytes(Klass::layout_helper_offset()); 3276 Address klass_lh_addr(tmp, lh_offset); 3277 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 3278 __ cmpl(klass_lh_addr, objArray_lh); 3279 __ jcc(Assembler::notEqual, *stub->entry()); 3280 } 3281 3282 // Spill because stubs can use any register they like and it's 3283 // easier to restore just those that we care about. 3284 store_parameter(dst, 0); 3285 store_parameter(dst_pos, 1); 3286 store_parameter(length, 2); 3287 store_parameter(src_pos, 3); 3288 store_parameter(src, 4); 3289 3290 #ifndef _LP64 3291 __ movptr(tmp, dst_klass_addr); 3292 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset())); 3293 __ push(tmp); 3294 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); 3295 __ push(tmp); 3296 __ push(length); 3297 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3298 __ push(tmp); 3299 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3300 __ push(tmp); 3301 3302 __ call_VM_leaf(copyfunc_addr, 5); 3303 #else 3304 __ movl2ptr(length, length); //higher 32bits must be null 3305 3306 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3307 assert_different_registers(c_rarg0, dst, dst_pos, length); 3308 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3309 assert_different_registers(c_rarg1, dst, length); 3310 3311 __ mov(c_rarg2, length); 3312 assert_different_registers(c_rarg2, dst); 3313 3314 #ifdef _WIN64 3315 // Allocate abi space for args but be sure to keep stack aligned 3316 __ subptr(rsp, 6*wordSize); 3317 __ load_klass(c_rarg3, dst); 3318 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset())); 3319 store_parameter(c_rarg3, 4); 3320 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); 3321 __ call(RuntimeAddress(copyfunc_addr)); 3322 __ addptr(rsp, 6*wordSize); 3323 #else 3324 __ load_klass(c_rarg4, dst); 3325 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); 3326 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 3327 __ call(RuntimeAddress(copyfunc_addr)); 3328 #endif 3329 3330 #endif 3331 3332 #ifndef PRODUCT 3333 if (PrintC1Statistics) { 3334 Label failed; 3335 __ testl(rax, rax); 3336 __ jcc(Assembler::notZero, failed); 3337 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); 3338 __ bind(failed); 3339 } 3340 #endif 3341 3342 __ testl(rax, rax); 3343 __ jcc(Assembler::zero, *stub->continuation()); 3344 3345 #ifndef PRODUCT 3346 if (PrintC1Statistics) { 3347 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); 3348 } 3349 #endif 3350 3351 __ mov(tmp, rax); 3352 3353 __ xorl(tmp, -1); 3354 3355 // Restore previously spilled arguments 3356 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3357 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3358 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3359 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3360 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3361 3362 3363 __ subl(length, tmp); 3364 __ addl(src_pos, tmp); 3365 __ addl(dst_pos, tmp); 3366 } 3367 3368 __ jmp(*stub->entry()); 3369 3370 __ bind(cont); 3371 __ pop(dst); 3372 __ pop(src); 3373 } 3374 } 3375 3376 #ifdef ASSERT 3377 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3378 // Sanity check the known type with the incoming class. For the 3379 // primitive case the types must match exactly with src.klass and 3380 // dst.klass each exactly matching the default type. For the 3381 // object array case, if no type check is needed then either the 3382 // dst type is exactly the expected type and the src type is a 3383 // subtype which we can't check or src is the same array as dst 3384 // but not necessarily exactly of type default_type. 3385 Label known_ok, halt; 3386 __ mov_metadata(tmp, default_type->constant_encoding()); 3387 #ifdef _LP64 3388 if (UseCompressedClassPointers) { 3389 __ encode_klass_not_null(tmp); 3390 } 3391 #endif 3392 3393 if (basic_type != T_OBJECT) { 3394 3395 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3396 else __ cmpptr(tmp, dst_klass_addr); 3397 __ jcc(Assembler::notEqual, halt); 3398 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr); 3399 else __ cmpptr(tmp, src_klass_addr); 3400 __ jcc(Assembler::equal, known_ok); 3401 } else { 3402 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3403 else __ cmpptr(tmp, dst_klass_addr); 3404 __ jcc(Assembler::equal, known_ok); 3405 __ cmpptr(src, dst); 3406 __ jcc(Assembler::equal, known_ok); 3407 } 3408 __ bind(halt); 3409 __ stop("incorrect type information in arraycopy"); 3410 __ bind(known_ok); 3411 } 3412 #endif 3413 3414 #ifndef PRODUCT 3415 if (PrintC1Statistics) { 3416 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); 3417 } 3418 #endif 3419 3420 #ifdef _LP64 3421 assert_different_registers(c_rarg0, dst, dst_pos, length); 3422 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3423 assert_different_registers(c_rarg1, length); 3424 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3425 __ mov(c_rarg2, length); 3426 3427 #else 3428 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3429 store_parameter(tmp, 0); 3430 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3431 store_parameter(tmp, 1); 3432 store_parameter(length, 2); 3433 #endif // _LP64 3434 3435 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 3436 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 3437 const char *name; 3438 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 3439 __ call_VM_leaf(entry, 0); 3440 3441 __ bind(*stub->continuation()); 3442 } 3443 3444 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3445 assert(op->crc()->is_single_cpu(), "crc must be register"); 3446 assert(op->val()->is_single_cpu(), "byte value must be register"); 3447 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3448 Register crc = op->crc()->as_register(); 3449 Register val = op->val()->as_register(); 3450 Register res = op->result_opr()->as_register(); 3451 3452 assert_different_registers(val, crc, res); 3453 3454 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr())); 3455 __ notl(crc); // ~crc 3456 __ update_byte_crc32(crc, val, res); 3457 __ notl(crc); // ~crc 3458 __ mov(res, crc); 3459 } 3460 3461 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3462 Register obj = op->obj_opr()->as_register(); // may not be an oop 3463 Register hdr = op->hdr_opr()->as_register(); 3464 Register lock = op->lock_opr()->as_register(); 3465 if (!UseFastLocking) { 3466 __ jmp(*op->stub()->entry()); 3467 } else if (op->code() == lir_lock) { 3468 Register scratch = noreg; 3469 if (UseBiasedLocking) { 3470 scratch = op->scratch_opr()->as_register(); 3471 } 3472 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3473 // add debug info for NullPointerException only if one is possible 3474 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); 3475 if (op->info() != NULL) { 3476 add_debug_info_for_null_check(null_check_offset, op->info()); 3477 } 3478 // done 3479 } else if (op->code() == lir_unlock) { 3480 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3481 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3482 } else { 3483 Unimplemented(); 3484 } 3485 __ bind(*op->stub()->continuation()); 3486 } 3487 3488 3489 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3490 ciMethod* method = op->profiled_method(); 3491 int bci = op->profiled_bci(); 3492 ciMethod* callee = op->profiled_callee(); 3493 3494 // Update counter for all call types 3495 ciMethodData* md = method->method_data_or_null(); 3496 assert(md != NULL, "Sanity"); 3497 ciProfileData* data = md->bci_to_data(bci); 3498 assert(data != NULL && data->is_CounterData(), "need CounterData for calls"); 3499 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3500 Register mdo = op->mdo()->as_register(); 3501 __ mov_metadata(mdo, md->constant_encoding()); 3502 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3503 // Perform additional virtual call profiling for invokevirtual and 3504 // invokeinterface bytecodes 3505 if (op->should_profile_receiver_type()) { 3506 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3507 Register recv = op->recv()->as_register(); 3508 assert_different_registers(mdo, recv); 3509 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3510 ciKlass* known_klass = op->known_holder(); 3511 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 3512 // We know the type that will be seen at this call site; we can 3513 // statically update the MethodData* rather than needing to do 3514 // dynamic tests on the receiver type 3515 3516 // NOTE: we should probably put a lock around this search to 3517 // avoid collisions by concurrent compilations 3518 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3519 uint i; 3520 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3521 ciKlass* receiver = vc_data->receiver(i); 3522 if (known_klass->equals(receiver)) { 3523 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3524 __ addptr(data_addr, DataLayout::counter_increment); 3525 return; 3526 } 3527 } 3528 3529 // Receiver type not found in profile data; select an empty slot 3530 3531 // Note that this is less efficient than it should be because it 3532 // always does a write to the receiver part of the 3533 // VirtualCallData rather than just the first time 3534 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3535 ciKlass* receiver = vc_data->receiver(i); 3536 if (receiver == NULL) { 3537 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3538 __ mov_metadata(recv_addr, known_klass->constant_encoding()); 3539 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3540 __ addptr(data_addr, DataLayout::counter_increment); 3541 return; 3542 } 3543 } 3544 } else { 3545 __ load_klass(recv, recv); 3546 Label update_done; 3547 type_profile_helper(mdo, md, data, recv, &update_done); 3548 // Receiver did not match any saved receiver and there is no empty row for it. 3549 // Increment total counter to indicate polymorphic case. 3550 __ addptr(counter_addr, DataLayout::counter_increment); 3551 3552 __ bind(update_done); 3553 } 3554 } else { 3555 // Static call 3556 __ addptr(counter_addr, DataLayout::counter_increment); 3557 } 3558 } 3559 3560 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 3561 Register obj = op->obj()->as_register(); 3562 Register tmp = op->tmp()->as_pointer_register(); 3563 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 3564 ciKlass* exact_klass = op->exact_klass(); 3565 intptr_t current_klass = op->current_klass(); 3566 bool not_null = op->not_null(); 3567 bool no_conflict = op->no_conflict(); 3568 3569 Label update, next, none; 3570 3571 bool do_null = !not_null; 3572 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 3573 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 3574 3575 assert(do_null || do_update, "why are we here?"); 3576 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 3577 3578 __ verify_oop(obj); 3579 3580 if (tmp != obj) { 3581 __ mov(tmp, obj); 3582 } 3583 if (do_null) { 3584 __ testptr(tmp, tmp); 3585 __ jccb(Assembler::notZero, update); 3586 if (!TypeEntries::was_null_seen(current_klass)) { 3587 __ orptr(mdo_addr, TypeEntries::null_seen); 3588 } 3589 if (do_update) { 3590 #ifndef ASSERT 3591 __ jmpb(next); 3592 } 3593 #else 3594 __ jmp(next); 3595 } 3596 } else { 3597 __ testptr(tmp, tmp); 3598 __ jccb(Assembler::notZero, update); 3599 __ stop("unexpect null obj"); 3600 #endif 3601 } 3602 3603 __ bind(update); 3604 3605 if (do_update) { 3606 #ifdef ASSERT 3607 if (exact_klass != NULL) { 3608 Label ok; 3609 __ load_klass(tmp, tmp); 3610 __ push(tmp); 3611 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3612 __ cmpptr(tmp, Address(rsp, 0)); 3613 __ jccb(Assembler::equal, ok); 3614 __ stop("exact klass and actual klass differ"); 3615 __ bind(ok); 3616 __ pop(tmp); 3617 } 3618 #endif 3619 if (!no_conflict) { 3620 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 3621 if (exact_klass != NULL) { 3622 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3623 } else { 3624 __ load_klass(tmp, tmp); 3625 } 3626 3627 __ xorptr(tmp, mdo_addr); 3628 __ testptr(tmp, TypeEntries::type_klass_mask); 3629 // klass seen before, nothing to do. The unknown bit may have been 3630 // set already but no need to check. 3631 __ jccb(Assembler::zero, next); 3632 3633 __ testptr(tmp, TypeEntries::type_unknown); 3634 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3635 3636 if (TypeEntries::is_type_none(current_klass)) { 3637 __ cmpptr(mdo_addr, 0); 3638 __ jccb(Assembler::equal, none); 3639 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3640 __ jccb(Assembler::equal, none); 3641 // There is a chance that the checks above (re-reading profiling 3642 // data from memory) fail if another thread has just set the 3643 // profiling to this obj's klass 3644 __ xorptr(tmp, mdo_addr); 3645 __ testptr(tmp, TypeEntries::type_klass_mask); 3646 __ jccb(Assembler::zero, next); 3647 } 3648 } else { 3649 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3650 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 3651 3652 __ movptr(tmp, mdo_addr); 3653 __ testptr(tmp, TypeEntries::type_unknown); 3654 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3655 } 3656 3657 // different than before. Cannot keep accurate profile. 3658 __ orptr(mdo_addr, TypeEntries::type_unknown); 3659 3660 if (TypeEntries::is_type_none(current_klass)) { 3661 __ jmpb(next); 3662 3663 __ bind(none); 3664 // first time here. Set profile type. 3665 __ movptr(mdo_addr, tmp); 3666 } 3667 } else { 3668 // There's a single possible klass at this profile point 3669 assert(exact_klass != NULL, "should be"); 3670 if (TypeEntries::is_type_none(current_klass)) { 3671 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3672 __ xorptr(tmp, mdo_addr); 3673 __ testptr(tmp, TypeEntries::type_klass_mask); 3674 #ifdef ASSERT 3675 __ jcc(Assembler::zero, next); 3676 3677 { 3678 Label ok; 3679 __ push(tmp); 3680 __ cmpptr(mdo_addr, 0); 3681 __ jcc(Assembler::equal, ok); 3682 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3683 __ jcc(Assembler::equal, ok); 3684 // may have been set by another thread 3685 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3686 __ xorptr(tmp, mdo_addr); 3687 __ testptr(tmp, TypeEntries::type_mask); 3688 __ jcc(Assembler::zero, ok); 3689 3690 __ stop("unexpected profiling mismatch"); 3691 __ bind(ok); 3692 __ pop(tmp); 3693 } 3694 #else 3695 __ jccb(Assembler::zero, next); 3696 #endif 3697 // first time here. Set profile type. 3698 __ movptr(mdo_addr, tmp); 3699 } else { 3700 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3701 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3702 3703 __ movptr(tmp, mdo_addr); 3704 __ testptr(tmp, TypeEntries::type_unknown); 3705 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3706 3707 __ orptr(mdo_addr, TypeEntries::type_unknown); 3708 } 3709 } 3710 3711 __ bind(next); 3712 } 3713 } 3714 3715 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3716 Unimplemented(); 3717 } 3718 3719 3720 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3721 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3722 } 3723 3724 3725 void LIR_Assembler::align_backward_branch_target() { 3726 __ align(BytesPerWord); 3727 } 3728 3729 3730 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3731 if (left->is_single_cpu()) { 3732 __ negl(left->as_register()); 3733 move_regs(left->as_register(), dest->as_register()); 3734 3735 } else if (left->is_double_cpu()) { 3736 Register lo = left->as_register_lo(); 3737 #ifdef _LP64 3738 Register dst = dest->as_register_lo(); 3739 __ movptr(dst, lo); 3740 __ negptr(dst); 3741 #else 3742 Register hi = left->as_register_hi(); 3743 __ lneg(hi, lo); 3744 if (dest->as_register_lo() == hi) { 3745 assert(dest->as_register_hi() != lo, "destroying register"); 3746 move_regs(hi, dest->as_register_hi()); 3747 move_regs(lo, dest->as_register_lo()); 3748 } else { 3749 move_regs(lo, dest->as_register_lo()); 3750 move_regs(hi, dest->as_register_hi()); 3751 } 3752 #endif // _LP64 3753 3754 } else if (dest->is_single_xmm()) { 3755 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3756 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3757 } 3758 if (UseAVX > 0) { 3759 __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(), 3760 ExternalAddress((address)float_signflip_pool)); 3761 } else { 3762 __ xorps(dest->as_xmm_float_reg(), 3763 ExternalAddress((address)float_signflip_pool)); 3764 } 3765 } else if (dest->is_double_xmm()) { 3766 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3767 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3768 } 3769 if (UseAVX > 0) { 3770 __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(), 3771 ExternalAddress((address)double_signflip_pool)); 3772 } else { 3773 __ xorpd(dest->as_xmm_double_reg(), 3774 ExternalAddress((address)double_signflip_pool)); 3775 } 3776 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3777 assert(left->fpu() == 0, "arg must be on TOS"); 3778 assert(dest->fpu() == 0, "dest must be TOS"); 3779 __ fchs(); 3780 3781 } else { 3782 ShouldNotReachHere(); 3783 } 3784 } 3785 3786 3787 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { 3788 assert(addr->is_address() && dest->is_register(), "check"); 3789 Register reg; 3790 reg = dest->as_pointer_register(); 3791 __ lea(reg, as_Address(addr->as_address_ptr())); 3792 } 3793 3794 3795 3796 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3797 assert(!tmp->is_valid(), "don't need temporary"); 3798 __ call(RuntimeAddress(dest)); 3799 if (info != NULL) { 3800 add_call_info_here(info); 3801 } 3802 } 3803 3804 3805 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3806 assert(type == T_LONG, "only for volatile long fields"); 3807 3808 if (info != NULL) { 3809 add_debug_info_for_null_check_here(info); 3810 } 3811 3812 if (src->is_double_xmm()) { 3813 if (dest->is_double_cpu()) { 3814 #ifdef _LP64 3815 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3816 #else 3817 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3818 __ psrlq(src->as_xmm_double_reg(), 32); 3819 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3820 #endif // _LP64 3821 } else if (dest->is_double_stack()) { 3822 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3823 } else if (dest->is_address()) { 3824 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3825 } else { 3826 ShouldNotReachHere(); 3827 } 3828 3829 } else if (dest->is_double_xmm()) { 3830 if (src->is_double_stack()) { 3831 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3832 } else if (src->is_address()) { 3833 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3834 } else { 3835 ShouldNotReachHere(); 3836 } 3837 3838 } else if (src->is_double_fpu()) { 3839 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3840 if (dest->is_double_stack()) { 3841 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3842 } else if (dest->is_address()) { 3843 __ fistp_d(as_Address(dest->as_address_ptr())); 3844 } else { 3845 ShouldNotReachHere(); 3846 } 3847 3848 } else if (dest->is_double_fpu()) { 3849 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3850 if (src->is_double_stack()) { 3851 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3852 } else if (src->is_address()) { 3853 __ fild_d(as_Address(src->as_address_ptr())); 3854 } else { 3855 ShouldNotReachHere(); 3856 } 3857 } else { 3858 ShouldNotReachHere(); 3859 } 3860 } 3861 3862 #ifdef ASSERT 3863 // emit run-time assertion 3864 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 3865 assert(op->code() == lir_assert, "must be"); 3866 3867 if (op->in_opr1()->is_valid()) { 3868 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 3869 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 3870 } else { 3871 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 3872 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 3873 } 3874 3875 Label ok; 3876 if (op->condition() != lir_cond_always) { 3877 Assembler::Condition acond = Assembler::zero; 3878 switch (op->condition()) { 3879 case lir_cond_equal: acond = Assembler::equal; break; 3880 case lir_cond_notEqual: acond = Assembler::notEqual; break; 3881 case lir_cond_less: acond = Assembler::less; break; 3882 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 3883 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 3884 case lir_cond_greater: acond = Assembler::greater; break; 3885 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 3886 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 3887 default: ShouldNotReachHere(); 3888 } 3889 __ jcc(acond, ok); 3890 } 3891 if (op->halt()) { 3892 const char* str = __ code_string(op->msg()); 3893 __ stop(str); 3894 } else { 3895 breakpoint(); 3896 } 3897 __ bind(ok); 3898 } 3899 #endif 3900 3901 void LIR_Assembler::membar() { 3902 // QQQ sparc TSO uses this, 3903 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3904 } 3905 3906 void LIR_Assembler::membar_acquire() { 3907 // No x86 machines currently require load fences 3908 } 3909 3910 void LIR_Assembler::membar_release() { 3911 // No x86 machines currently require store fences 3912 } 3913 3914 void LIR_Assembler::membar_loadload() { 3915 // no-op 3916 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 3917 } 3918 3919 void LIR_Assembler::membar_storestore() { 3920 // no-op 3921 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 3922 } 3923 3924 void LIR_Assembler::membar_loadstore() { 3925 // no-op 3926 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 3927 } 3928 3929 void LIR_Assembler::membar_storeload() { 3930 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3931 } 3932 3933 void LIR_Assembler::on_spin_wait() { 3934 __ pause (); 3935 } 3936 3937 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3938 assert(result_reg->is_register(), "check"); 3939 #ifdef _LP64 3940 // __ get_thread(result_reg->as_register_lo()); 3941 __ mov(result_reg->as_register(), r15_thread); 3942 #else 3943 __ get_thread(result_reg->as_register()); 3944 #endif // _LP64 3945 } 3946 3947 3948 void LIR_Assembler::peephole(LIR_List*) { 3949 // do nothing for now 3950 } 3951 3952 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 3953 assert(data == dest, "xchg/xadd uses only 2 operands"); 3954 3955 if (data->type() == T_INT) { 3956 if (code == lir_xadd) { 3957 if (os::is_MP()) { 3958 __ lock(); 3959 } 3960 __ xaddl(as_Address(src->as_address_ptr()), data->as_register()); 3961 } else { 3962 __ xchgl(data->as_register(), as_Address(src->as_address_ptr())); 3963 } 3964 } else if (data->is_oop()) { 3965 assert (code == lir_xchg, "xadd for oops"); 3966 Register obj = data->as_register(); 3967 #ifdef _LP64 3968 if (UseCompressedOops) { 3969 __ encode_heap_oop(obj); 3970 __ xchgl(obj, as_Address(src->as_address_ptr())); 3971 __ decode_heap_oop(obj); 3972 } else { 3973 __ xchgptr(obj, as_Address(src->as_address_ptr())); 3974 } 3975 #else 3976 __ xchgl(obj, as_Address(src->as_address_ptr())); 3977 #endif 3978 } else if (data->type() == T_LONG) { 3979 #ifdef _LP64 3980 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register"); 3981 if (code == lir_xadd) { 3982 if (os::is_MP()) { 3983 __ lock(); 3984 } 3985 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo()); 3986 } else { 3987 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr())); 3988 } 3989 #else 3990 ShouldNotReachHere(); 3991 #endif 3992 } else { 3993 ShouldNotReachHere(); 3994 } 3995 } 3996 3997 #undef __