1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "gc/shared/barrierSet.hpp"
37 #include "gc/shared/cardTableModRefBS.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "nativeInst_x86.hpp"
40 #include "oops/objArrayKlass.hpp"
41 #include "runtime/sharedRuntime.hpp"
42 #include "vmreg_x86.inline.hpp"
43
44
45 // These masks are used to provide 128-bit aligned bitmasks to the XMM
46 // instructions, to allow sign-masking or sign-bit flipping. They allow
47 // fast versions of NegF/NegD and AbsF/AbsD.
48
49 // Note: 'double' and 'long long' have 32-bits alignment on x86.
50 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
51 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
52 // of 128-bits operands for SSE instructions.
53 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
54 // Store the value to a 128-bits operand.
55 operand[0] = lo;
56 operand[1] = hi;
57 return operand;
58 }
59
60 // Buffer for 128-bits masks used by SSE instructions.
61 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
62
63 // Static initialization during VM startup.
64 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
65 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
66 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
67 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
68
69
70
71 NEEDS_CLEANUP // remove this definitions ?
72 const Register IC_Klass = rax; // where the IC klass is cached
73 const Register SYNC_header = rax; // synchronization header
74 const Register SHIFT_count = rcx; // where count for shift operations must be
75
76 #define __ _masm->
77
78
79 static void select_different_registers(Register preserve,
80 Register extra,
81 Register &tmp1,
82 Register &tmp2) {
83 if (tmp1 == preserve) {
84 assert_different_registers(tmp1, tmp2, extra);
85 tmp1 = extra;
86 } else if (tmp2 == preserve) {
87 assert_different_registers(tmp1, tmp2, extra);
88 tmp2 = extra;
89 }
90 assert_different_registers(preserve, tmp1, tmp2);
91 }
92
93
94
95 static void select_different_registers(Register preserve,
96 Register extra,
97 Register &tmp1,
98 Register &tmp2,
99 Register &tmp3) {
100 if (tmp1 == preserve) {
101 assert_different_registers(tmp1, tmp2, tmp3, extra);
102 tmp1 = extra;
103 } else if (tmp2 == preserve) {
104 assert_different_registers(tmp1, tmp2, tmp3, extra);
105 tmp2 = extra;
106 } else if (tmp3 == preserve) {
107 assert_different_registers(tmp1, tmp2, tmp3, extra);
108 tmp3 = extra;
109 }
110 assert_different_registers(preserve, tmp1, tmp2, tmp3);
111 }
112
113
114
115 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
116 if (opr->is_constant()) {
117 LIR_Const* constant = opr->as_constant_ptr();
118 switch (constant->type()) {
119 case T_INT: {
120 return true;
121 }
122
123 default:
124 return false;
125 }
126 }
127 return false;
128 }
129
130
131 LIR_Opr LIR_Assembler::receiverOpr() {
132 return FrameMap::receiver_opr;
133 }
134
135 LIR_Opr LIR_Assembler::osrBufferPointer() {
136 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
137 }
138
139 //--------------fpu register translations-----------------------
140
141
142 address LIR_Assembler::float_constant(float f) {
143 address const_addr = __ float_constant(f);
144 if (const_addr == NULL) {
145 bailout("const section overflow");
146 return __ code()->consts()->start();
147 } else {
148 return const_addr;
149 }
150 }
151
152
153 address LIR_Assembler::double_constant(double d) {
154 address const_addr = __ double_constant(d);
155 if (const_addr == NULL) {
156 bailout("const section overflow");
157 return __ code()->consts()->start();
158 } else {
159 return const_addr;
160 }
161 }
162
163
164 void LIR_Assembler::set_24bit_FPU() {
165 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
166 }
167
168 void LIR_Assembler::reset_FPU() {
169 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
170 }
171
172 void LIR_Assembler::fpop() {
173 __ fpop();
174 }
175
176 void LIR_Assembler::fxch(int i) {
177 __ fxch(i);
178 }
179
180 void LIR_Assembler::fld(int i) {
181 __ fld_s(i);
182 }
183
184 void LIR_Assembler::ffree(int i) {
185 __ ffree(i);
186 }
187
188 void LIR_Assembler::breakpoint() {
189 __ int3();
190 }
191
192 void LIR_Assembler::push(LIR_Opr opr) {
193 if (opr->is_single_cpu()) {
194 __ push_reg(opr->as_register());
195 } else if (opr->is_double_cpu()) {
196 NOT_LP64(__ push_reg(opr->as_register_hi()));
197 __ push_reg(opr->as_register_lo());
198 } else if (opr->is_stack()) {
199 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
200 } else if (opr->is_constant()) {
201 LIR_Const* const_opr = opr->as_constant_ptr();
202 if (const_opr->type() == T_OBJECT) {
203 __ push_oop(const_opr->as_jobject());
204 } else if (const_opr->type() == T_INT) {
205 __ push_jint(const_opr->as_jint());
206 } else {
207 ShouldNotReachHere();
208 }
209
210 } else {
211 ShouldNotReachHere();
212 }
213 }
214
215 void LIR_Assembler::pop(LIR_Opr opr) {
216 if (opr->is_single_cpu()) {
217 __ pop_reg(opr->as_register());
218 } else {
219 ShouldNotReachHere();
220 }
221 }
222
223 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
224 return addr->base()->is_illegal() && addr->index()->is_illegal();
225 }
226
227 //-------------------------------------------
228
229 Address LIR_Assembler::as_Address(LIR_Address* addr) {
230 return as_Address(addr, rscratch1);
231 }
232
233 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
234 if (addr->base()->is_illegal()) {
235 assert(addr->index()->is_illegal(), "must be illegal too");
236 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
237 if (! __ reachable(laddr)) {
238 __ movptr(tmp, laddr.addr());
239 Address res(tmp, 0);
240 return res;
241 } else {
242 return __ as_Address(laddr);
243 }
244 }
245
246 Register base = addr->base()->as_pointer_register();
247
248 if (addr->index()->is_illegal()) {
249 return Address( base, addr->disp());
250 } else if (addr->index()->is_cpu_register()) {
251 Register index = addr->index()->as_pointer_register();
252 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
253 } else if (addr->index()->is_constant()) {
254 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
255 assert(Assembler::is_simm32(addr_offset), "must be");
256
257 return Address(base, addr_offset);
258 } else {
259 Unimplemented();
260 return Address();
261 }
262 }
263
264
265 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
266 Address base = as_Address(addr);
267 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
268 }
269
270
271 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
272 return as_Address(addr);
273 }
274
275
276 void LIR_Assembler::osr_entry() {
277 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
278 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
279 ValueStack* entry_state = osr_entry->state();
280 int number_of_locks = entry_state->locks_size();
281
282 // we jump here if osr happens with the interpreter
283 // state set up to continue at the beginning of the
284 // loop that triggered osr - in particular, we have
285 // the following registers setup:
286 //
287 // rcx: osr buffer
288 //
289
290 // build frame
291 ciMethod* m = compilation()->method();
292 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
293
294 // OSR buffer is
295 //
296 // locals[nlocals-1..0]
297 // monitors[0..number_of_locks]
298 //
299 // locals is a direct copy of the interpreter frame so in the osr buffer
300 // so first slot in the local array is the last local from the interpreter
301 // and last slot is local[0] (receiver) from the interpreter
302 //
303 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
304 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
305 // in the interpreter frame (the method lock if a sync method)
306
307 // Initialize monitors in the compiled activation.
308 // rcx: pointer to osr buffer
309 //
310 // All other registers are dead at this point and the locals will be
311 // copied into place by code emitted in the IR.
312
313 Register OSR_buf = osrBufferPointer()->as_pointer_register();
314 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
315 int monitor_offset = BytesPerWord * method()->max_locals() +
316 (2 * BytesPerWord) * (number_of_locks - 1);
317 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
318 // the OSR buffer using 2 word entries: first the lock and then
319 // the oop.
320 for (int i = 0; i < number_of_locks; i++) {
321 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
322 #ifdef ASSERT
323 // verify the interpreter's monitor has a non-null object
324 {
325 Label L;
326 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
327 __ jcc(Assembler::notZero, L);
328 __ stop("locked object is NULL");
329 __ bind(L);
330 }
331 #endif
332 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
333 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
334 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
335 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
336 }
337 }
338 }
339
340
341 // inline cache check; done before the frame is built.
342 int LIR_Assembler::check_icache() {
343 Register receiver = FrameMap::receiver_opr->as_register();
344 Register ic_klass = IC_Klass;
345 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
346 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
347 if (!do_post_padding) {
348 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
349 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
350 __ nop();
351 }
352 }
353 int offset = __ offset();
354 __ inline_cache_check(receiver, IC_Klass);
355 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
356 if (do_post_padding) {
357 // force alignment after the cache check.
358 // It's been verified to be aligned if !VerifyOops
359 __ align(CodeEntryAlignment);
360 }
361 return offset;
362 }
363
364
365 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
366 jobject o = NULL;
367 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
368 __ movoop(reg, o);
369 patching_epilog(patch, lir_patch_normal, reg, info);
370 }
371
372 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
373 Metadata* o = NULL;
374 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
375 __ mov_metadata(reg, o);
376 patching_epilog(patch, lir_patch_normal, reg, info);
377 }
378
379 // This specifies the rsp decrement needed to build the frame
380 int LIR_Assembler::initial_frame_size_in_bytes() const {
381 // if rounding, must let FrameMap know!
382
383 // The frame_map records size in slots (32bit word)
384
385 // subtract two words to account for return address and link
386 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
387 }
388
389
390 int LIR_Assembler::emit_exception_handler() {
391 // if the last instruction is a call (typically to do a throw which
392 // is coming at the end after block reordering) the return address
393 // must still point into the code area in order to avoid assertion
394 // failures when searching for the corresponding bci => add a nop
395 // (was bug 5/14/1999 - gri)
396 __ nop();
397
398 // generate code for exception handler
399 address handler_base = __ start_a_stub(exception_handler_size);
400 if (handler_base == NULL) {
401 // not enough space left for the handler
402 bailout("exception handler overflow");
403 return -1;
404 }
405
406 int offset = code_offset();
407
408 // the exception oop and pc are in rax, and rdx
409 // no other registers need to be preserved, so invalidate them
410 __ invalidate_registers(false, true, true, false, true, true);
411
412 // check that there is really an exception
413 __ verify_not_null_oop(rax);
414
415 // search an exception handler (rax: exception oop, rdx: throwing pc)
416 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
417 __ should_not_reach_here();
418 guarantee(code_offset() - offset <= exception_handler_size, "overflow");
419 __ end_a_stub();
420
421 return offset;
422 }
423
424
425 // Emit the code to remove the frame from the stack in the exception
426 // unwind path.
427 int LIR_Assembler::emit_unwind_handler() {
428 #ifndef PRODUCT
429 if (CommentedAssembly) {
430 _masm->block_comment("Unwind handler");
431 }
432 #endif
433
434 int offset = code_offset();
435
436 // Fetch the exception from TLS and clear out exception related thread state
437 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
438 NOT_LP64(__ get_thread(rsi));
439 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
440 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
441 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
442
443 __ bind(_unwind_handler_entry);
444 __ verify_not_null_oop(rax);
445 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
446 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
447 }
448
449 // Preform needed unlocking
450 MonitorExitStub* stub = NULL;
451 if (method()->is_synchronized()) {
452 monitor_address(0, FrameMap::rax_opr);
453 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
454 __ unlock_object(rdi, rsi, rax, *stub->entry());
455 __ bind(*stub->continuation());
456 }
457
458 if (compilation()->env()->dtrace_method_probes()) {
459 #ifdef _LP64
460 __ mov(rdi, r15_thread);
461 __ mov_metadata(rsi, method()->constant_encoding());
462 #else
463 __ get_thread(rax);
464 __ movptr(Address(rsp, 0), rax);
465 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
466 #endif
467 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
468 }
469
470 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
471 __ mov(rax, rbx); // Restore the exception
472 }
473
474 // remove the activation and dispatch to the unwind handler
475 __ remove_frame(initial_frame_size_in_bytes());
476 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
477
478 // Emit the slow path assembly
479 if (stub != NULL) {
480 stub->emit_code(this);
481 }
482
483 return offset;
484 }
485
486
487 int LIR_Assembler::emit_deopt_handler() {
488 // if the last instruction is a call (typically to do a throw which
489 // is coming at the end after block reordering) the return address
490 // must still point into the code area in order to avoid assertion
491 // failures when searching for the corresponding bci => add a nop
492 // (was bug 5/14/1999 - gri)
493 __ nop();
494
495 // generate code for exception handler
496 address handler_base = __ start_a_stub(deopt_handler_size);
497 if (handler_base == NULL) {
498 // not enough space left for the handler
499 bailout("deopt handler overflow");
500 return -1;
501 }
502
503 int offset = code_offset();
504 InternalAddress here(__ pc());
505
506 __ pushptr(here.addr());
507 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
508 guarantee(code_offset() - offset <= deopt_handler_size, "overflow");
509 __ end_a_stub();
510
511 return offset;
512 }
513
514
515 // This is the fast version of java.lang.String.compare; it has not
516 // OSR-entry and therefore, we generate a slow version for OSR's
517 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, C1ThreadLocalSafepoint *tls_stub, CodeEmitInfo* info) {
518 __ movptr (rbx, rcx); // receiver is in rcx
519 __ movptr (rax, arg1->as_register());
520
521 // Get addresses of first characters from both Strings
522 __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
523 if (java_lang_String::has_offset_field()) {
524 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
525 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
526 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
527 } else {
528 __ movl (rax, Address(rsi, arrayOopDesc::length_offset_in_bytes()));
529 __ lea (rsi, Address(rsi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
530 }
531
532 // rbx, may be NULL
533 add_debug_info_for_null_check_here(info);
534 __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
535 if (java_lang_String::has_offset_field()) {
536 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
537 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
538 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
539 } else {
540 __ movl (rbx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
541 __ lea (rdi, Address(rdi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
542 }
543
544 // compute minimum length (in rax) and difference of lengths (on top of stack)
545 __ mov (rcx, rbx);
546 __ subptr(rbx, rax); // subtract lengths
547 __ push (rbx); // result
548 __ cmov (Assembler::lessEqual, rax, rcx);
549
550 // is minimum length 0?
551 Label noLoop, haveResult;
552 __ testptr (rax, rax);
553 __ jcc (Assembler::zero, noLoop);
554
555 // compare first characters
556 __ load_unsigned_short(rcx, Address(rdi, 0));
557 __ load_unsigned_short(rbx, Address(rsi, 0));
558 __ subl(rcx, rbx);
559 __ jcc(Assembler::notZero, haveResult);
560 // starting loop
561 __ decrement(rax); // we already tested index: skip one
562 __ jcc(Assembler::zero, noLoop);
563
564 // set rsi.edi to the end of the arrays (arrays have same length)
565 // negate the index
566
567 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
568 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
569 __ negptr(rax);
570
571 // compare the strings in a loop
572
573 Label loop;
574 __ align(wordSize);
575 __ bind(loop);
576 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
577 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
578 __ subl(rcx, rbx);
579 __ jcc(Assembler::notZero, haveResult);
580 __ increment(rax);
581 __ jcc(Assembler::notZero, loop);
582
583 // strings are equal up to min length
584
585 __ bind(noLoop);
586 __ pop(rax);
587 return_op(LIR_OprFact::illegalOpr, tls_stub);
588
589 __ bind(haveResult);
590 // leave instruction is going to discard the TOS value
591 __ mov (rax, rcx); // result of call is in rax,
592 }
593
594
595 void LIR_Assembler::return_op(LIR_Opr result, C1ThreadLocalSafepoint *code_stub) {
596 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
597 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
598 assert(result->fpu() == 0, "result must already be on TOS");
599 }
600
601 // Pop the stack before the safepoint code
602 __ remove_frame(initial_frame_size_in_bytes());
603
604 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
605
606 // Note: we do not need to round double result; float result has the right precision
607 // the poll sets the condition code, but no data registers
608
609 if (!ThreadLocalSafepoints) {
610 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
611
612 if (Assembler::is_polling_page_far()) {
613 __ lea(rscratch1, polling_page);
614 __ relocate(relocInfo::poll_return_type);
615 __ testl(rax, Address(rscratch1, 0));
616 } else {
617 __ testl(rax, polling_page);
618 }
619 } else {
620 #ifdef _LP64
621 code_stub->set_safepoint_pc(__ pc());
622 __ relocate(relocInfo::poll_return_type);
623 __ testb(Address(r15_thread, Thread::yieldpoint_offset()), 2);
624 __ jcc(Assembler::equal, *code_stub->entry());
625 #else
626 ShouldNotReachHere();
627 #endif
628 }
629 __ ret(0);
630 }
631
632
633 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, C1ThreadLocalSafepoint *code_stub, CodeEmitInfo* info) {
634 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
635 guarantee(info != NULL, "Shouldn't be NULL");
636 int offset = __ offset();
637 if (!ThreadLocalSafepoints) {
638 if (Assembler::is_polling_page_far()) {
639 __ lea(rscratch1, polling_page);
640 offset = __ offset();
641 add_debug_info_for_branch(info);
642 __ relocate(relocInfo::poll_type);
643 __ testl(rax, Address(rscratch1, 0));
644 } else {
645 add_debug_info_for_branch(info);
646 __ testl(rax, polling_page);
647 }
648 } else {
649 #ifdef _LP64
650 add_debug_info_for_branch(info);
651 code_stub->set_safepoint_pc(__ pc());
652 __ relocate(relocInfo::poll_type);
653 __ testb(Address(r15_thread, Thread::yieldpoint_offset()), 1);
654 __ jcc(Assembler::equal, *code_stub->entry());
655 #else
656 ShouldNotReachHere();
657 #endif
658 }
659
660 return offset;
661 }
662
663
664 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
665 if (from_reg != to_reg) __ mov(to_reg, from_reg);
666 }
667
668 void LIR_Assembler::swap_reg(Register a, Register b) {
669 __ xchgptr(a, b);
670 }
671
672
673 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
674 assert(src->is_constant(), "should not call otherwise");
675 assert(dest->is_register(), "should not call otherwise");
676 LIR_Const* c = src->as_constant_ptr();
677
678 switch (c->type()) {
679 case T_INT: {
680 assert(patch_code == lir_patch_none, "no patching handled here");
681 __ movl(dest->as_register(), c->as_jint());
682 break;
683 }
684
685 case T_ADDRESS: {
686 assert(patch_code == lir_patch_none, "no patching handled here");
687 __ movptr(dest->as_register(), c->as_jint());
688 break;
689 }
690
691 case T_LONG: {
692 assert(patch_code == lir_patch_none, "no patching handled here");
693 #ifdef _LP64
694 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
695 #else
696 __ movptr(dest->as_register_lo(), c->as_jint_lo());
697 __ movptr(dest->as_register_hi(), c->as_jint_hi());
698 #endif // _LP64
699 break;
700 }
701
702 case T_OBJECT: {
703 if (patch_code != lir_patch_none) {
704 jobject2reg_with_patching(dest->as_register(), info);
705 } else {
706 __ movoop(dest->as_register(), c->as_jobject());
707 }
708 break;
709 }
710
711 case T_METADATA: {
712 if (patch_code != lir_patch_none) {
713 klass2reg_with_patching(dest->as_register(), info);
714 } else {
715 __ mov_metadata(dest->as_register(), c->as_metadata());
716 }
717 break;
718 }
719
720 case T_FLOAT: {
721 if (dest->is_single_xmm()) {
722 if (c->is_zero_float()) {
723 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
724 } else {
725 __ movflt(dest->as_xmm_float_reg(),
726 InternalAddress(float_constant(c->as_jfloat())));
727 }
728 } else {
729 assert(dest->is_single_fpu(), "must be");
730 assert(dest->fpu_regnr() == 0, "dest must be TOS");
731 if (c->is_zero_float()) {
732 __ fldz();
733 } else if (c->is_one_float()) {
734 __ fld1();
735 } else {
736 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
737 }
738 }
739 break;
740 }
741
742 case T_DOUBLE: {
743 if (dest->is_double_xmm()) {
744 if (c->is_zero_double()) {
745 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
746 } else {
747 __ movdbl(dest->as_xmm_double_reg(),
748 InternalAddress(double_constant(c->as_jdouble())));
749 }
750 } else {
751 assert(dest->is_double_fpu(), "must be");
752 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
753 if (c->is_zero_double()) {
754 __ fldz();
755 } else if (c->is_one_double()) {
756 __ fld1();
757 } else {
758 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
759 }
760 }
761 break;
762 }
763
764 default:
765 ShouldNotReachHere();
766 }
767 }
768
769 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
770 assert(src->is_constant(), "should not call otherwise");
771 assert(dest->is_stack(), "should not call otherwise");
772 LIR_Const* c = src->as_constant_ptr();
773
774 switch (c->type()) {
775 case T_INT: // fall through
776 case T_FLOAT:
777 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
778 break;
779
780 case T_ADDRESS:
781 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
782 break;
783
784 case T_OBJECT:
785 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
786 break;
787
788 case T_LONG: // fall through
789 case T_DOUBLE:
790 #ifdef _LP64
791 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
792 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
793 #else
794 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
795 lo_word_offset_in_bytes), c->as_jint_lo_bits());
796 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
797 hi_word_offset_in_bytes), c->as_jint_hi_bits());
798 #endif // _LP64
799 break;
800
801 default:
802 ShouldNotReachHere();
803 }
804 }
805
806 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
807 assert(src->is_constant(), "should not call otherwise");
808 assert(dest->is_address(), "should not call otherwise");
809 LIR_Const* c = src->as_constant_ptr();
810 LIR_Address* addr = dest->as_address_ptr();
811
812 int null_check_here = code_offset();
813 switch (type) {
814 case T_INT: // fall through
815 case T_FLOAT:
816 __ movl(as_Address(addr), c->as_jint_bits());
817 break;
818
819 case T_ADDRESS:
820 __ movptr(as_Address(addr), c->as_jint_bits());
821 break;
822
823 case T_OBJECT: // fall through
824 case T_ARRAY:
825 if (c->as_jobject() == NULL) {
826 if (UseCompressedOops && !wide) {
827 __ movl(as_Address(addr), (int32_t)NULL_WORD);
828 } else {
829 #ifdef _LP64
830 __ xorptr(rscratch1, rscratch1);
831 null_check_here = code_offset();
832 __ movptr(as_Address(addr), rscratch1);
833 #else
834 __ movptr(as_Address(addr), NULL_WORD);
835 #endif
836 }
837 } else {
838 if (is_literal_address(addr)) {
839 ShouldNotReachHere();
840 __ movoop(as_Address(addr, noreg), c->as_jobject());
841 } else {
842 #ifdef _LP64
843 __ movoop(rscratch1, c->as_jobject());
844 if (UseCompressedOops && !wide) {
845 __ encode_heap_oop(rscratch1);
846 null_check_here = code_offset();
847 __ movl(as_Address_lo(addr), rscratch1);
848 } else {
849 null_check_here = code_offset();
850 __ movptr(as_Address_lo(addr), rscratch1);
851 }
852 #else
853 __ movoop(as_Address(addr), c->as_jobject());
854 #endif
855 }
856 }
857 break;
858
859 case T_LONG: // fall through
860 case T_DOUBLE:
861 #ifdef _LP64
862 if (is_literal_address(addr)) {
863 ShouldNotReachHere();
864 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
865 } else {
866 __ movptr(r10, (intptr_t)c->as_jlong_bits());
867 null_check_here = code_offset();
868 __ movptr(as_Address_lo(addr), r10);
869 }
870 #else
871 // Always reachable in 32bit so this doesn't produce useless move literal
872 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
873 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
874 #endif // _LP64
875 break;
876
877 case T_BOOLEAN: // fall through
878 case T_BYTE:
879 __ movb(as_Address(addr), c->as_jint() & 0xFF);
880 break;
881
882 case T_CHAR: // fall through
883 case T_SHORT:
884 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
885 break;
886
887 default:
888 ShouldNotReachHere();
889 };
890
891 if (info != NULL) {
892 add_debug_info_for_null_check(null_check_here, info);
893 }
894 }
895
896
897 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
898 assert(src->is_register(), "should not call otherwise");
899 assert(dest->is_register(), "should not call otherwise");
900
901 // move between cpu-registers
902 if (dest->is_single_cpu()) {
903 #ifdef _LP64
904 if (src->type() == T_LONG) {
905 // Can do LONG -> OBJECT
906 move_regs(src->as_register_lo(), dest->as_register());
907 return;
908 }
909 #endif
910 assert(src->is_single_cpu(), "must match");
911 if (src->type() == T_OBJECT) {
912 __ verify_oop(src->as_register());
913 }
914 move_regs(src->as_register(), dest->as_register());
915
916 } else if (dest->is_double_cpu()) {
917 #ifdef _LP64
918 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
919 // Surprising to me but we can see move of a long to t_object
920 __ verify_oop(src->as_register());
921 move_regs(src->as_register(), dest->as_register_lo());
922 return;
923 }
924 #endif
925 assert(src->is_double_cpu(), "must match");
926 Register f_lo = src->as_register_lo();
927 Register f_hi = src->as_register_hi();
928 Register t_lo = dest->as_register_lo();
929 Register t_hi = dest->as_register_hi();
930 #ifdef _LP64
931 assert(f_hi == f_lo, "must be same");
932 assert(t_hi == t_lo, "must be same");
933 move_regs(f_lo, t_lo);
934 #else
935 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
936
937
938 if (f_lo == t_hi && f_hi == t_lo) {
939 swap_reg(f_lo, f_hi);
940 } else if (f_hi == t_lo) {
941 assert(f_lo != t_hi, "overwriting register");
942 move_regs(f_hi, t_hi);
943 move_regs(f_lo, t_lo);
944 } else {
945 assert(f_hi != t_lo, "overwriting register");
946 move_regs(f_lo, t_lo);
947 move_regs(f_hi, t_hi);
948 }
949 #endif // LP64
950
951 // special moves from fpu-register to xmm-register
952 // necessary for method results
953 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
954 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
955 __ fld_s(Address(rsp, 0));
956 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
957 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
958 __ fld_d(Address(rsp, 0));
959 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
960 __ fstp_s(Address(rsp, 0));
961 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
962 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
963 __ fstp_d(Address(rsp, 0));
964 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
965
966 // move between xmm-registers
967 } else if (dest->is_single_xmm()) {
968 assert(src->is_single_xmm(), "must match");
969 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
970 } else if (dest->is_double_xmm()) {
971 assert(src->is_double_xmm(), "must match");
972 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
973
974 // move between fpu-registers (no instruction necessary because of fpu-stack)
975 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
976 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
977 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
978 } else {
979 ShouldNotReachHere();
980 }
981 }
982
983 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
984 assert(src->is_register(), "should not call otherwise");
985 assert(dest->is_stack(), "should not call otherwise");
986
987 if (src->is_single_cpu()) {
988 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
989 if (type == T_OBJECT || type == T_ARRAY) {
990 __ verify_oop(src->as_register());
991 __ movptr (dst, src->as_register());
992 } else if (type == T_METADATA) {
993 __ movptr (dst, src->as_register());
994 } else {
995 __ movl (dst, src->as_register());
996 }
997
998 } else if (src->is_double_cpu()) {
999 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
1000 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
1001 __ movptr (dstLO, src->as_register_lo());
1002 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
1003
1004 } else if (src->is_single_xmm()) {
1005 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
1006 __ movflt(dst_addr, src->as_xmm_float_reg());
1007
1008 } else if (src->is_double_xmm()) {
1009 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
1010 __ movdbl(dst_addr, src->as_xmm_double_reg());
1011
1012 } else if (src->is_single_fpu()) {
1013 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1014 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
1015 if (pop_fpu_stack) __ fstp_s (dst_addr);
1016 else __ fst_s (dst_addr);
1017
1018 } else if (src->is_double_fpu()) {
1019 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1020 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
1021 if (pop_fpu_stack) __ fstp_d (dst_addr);
1022 else __ fst_d (dst_addr);
1023
1024 } else {
1025 ShouldNotReachHere();
1026 }
1027 }
1028
1029
1030 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
1031 LIR_Address* to_addr = dest->as_address_ptr();
1032 PatchingStub* patch = NULL;
1033 Register compressed_src = rscratch1;
1034
1035 if (type == T_ARRAY || type == T_OBJECT) {
1036 __ verify_oop(src->as_register());
1037 #ifdef _LP64
1038 if (UseCompressedOops && !wide) {
1039 __ movptr(compressed_src, src->as_register());
1040 __ encode_heap_oop(compressed_src);
1041 if (patch_code != lir_patch_none) {
1042 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
1043 }
1044 }
1045 #endif
1046 }
1047
1048 if (patch_code != lir_patch_none) {
1049 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1050 Address toa = as_Address(to_addr);
1051 assert(toa.disp() != 0, "must have");
1052 }
1053
1054 int null_check_here = code_offset();
1055 switch (type) {
1056 case T_FLOAT: {
1057 if (src->is_single_xmm()) {
1058 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1059 } else {
1060 assert(src->is_single_fpu(), "must be");
1061 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1062 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1063 else __ fst_s (as_Address(to_addr));
1064 }
1065 break;
1066 }
1067
1068 case T_DOUBLE: {
1069 if (src->is_double_xmm()) {
1070 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1071 } else {
1072 assert(src->is_double_fpu(), "must be");
1073 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1074 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1075 else __ fst_d (as_Address(to_addr));
1076 }
1077 break;
1078 }
1079
1080 case T_ARRAY: // fall through
1081 case T_OBJECT: // fall through
1082 if (UseCompressedOops && !wide) {
1083 __ movl(as_Address(to_addr), compressed_src);
1084 } else {
1085 __ movptr(as_Address(to_addr), src->as_register());
1086 }
1087 break;
1088 case T_METADATA:
1089 // We get here to store a method pointer to the stack to pass to
1090 // a dtrace runtime call. This can't work on 64 bit with
1091 // compressed klass ptrs: T_METADATA can be a compressed klass
1092 // ptr or a 64 bit method pointer.
1093 LP64_ONLY(ShouldNotReachHere());
1094 __ movptr(as_Address(to_addr), src->as_register());
1095 break;
1096 case T_ADDRESS:
1097 __ movptr(as_Address(to_addr), src->as_register());
1098 break;
1099 case T_INT:
1100 __ movl(as_Address(to_addr), src->as_register());
1101 break;
1102
1103 case T_LONG: {
1104 Register from_lo = src->as_register_lo();
1105 Register from_hi = src->as_register_hi();
1106 #ifdef _LP64
1107 __ movptr(as_Address_lo(to_addr), from_lo);
1108 #else
1109 Register base = to_addr->base()->as_register();
1110 Register index = noreg;
1111 if (to_addr->index()->is_register()) {
1112 index = to_addr->index()->as_register();
1113 }
1114 if (base == from_lo || index == from_lo) {
1115 assert(base != from_hi, "can't be");
1116 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1117 __ movl(as_Address_hi(to_addr), from_hi);
1118 if (patch != NULL) {
1119 patching_epilog(patch, lir_patch_high, base, info);
1120 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1121 patch_code = lir_patch_low;
1122 }
1123 __ movl(as_Address_lo(to_addr), from_lo);
1124 } else {
1125 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1126 __ movl(as_Address_lo(to_addr), from_lo);
1127 if (patch != NULL) {
1128 patching_epilog(patch, lir_patch_low, base, info);
1129 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1130 patch_code = lir_patch_high;
1131 }
1132 __ movl(as_Address_hi(to_addr), from_hi);
1133 }
1134 #endif // _LP64
1135 break;
1136 }
1137
1138 case T_BYTE: // fall through
1139 case T_BOOLEAN: {
1140 Register src_reg = src->as_register();
1141 Address dst_addr = as_Address(to_addr);
1142 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1143 __ movb(dst_addr, src_reg);
1144 break;
1145 }
1146
1147 case T_CHAR: // fall through
1148 case T_SHORT:
1149 __ movw(as_Address(to_addr), src->as_register());
1150 break;
1151
1152 default:
1153 ShouldNotReachHere();
1154 }
1155 if (info != NULL) {
1156 add_debug_info_for_null_check(null_check_here, info);
1157 }
1158
1159 if (patch_code != lir_patch_none) {
1160 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1161 }
1162 }
1163
1164
1165 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1166 assert(src->is_stack(), "should not call otherwise");
1167 assert(dest->is_register(), "should not call otherwise");
1168
1169 if (dest->is_single_cpu()) {
1170 if (type == T_ARRAY || type == T_OBJECT) {
1171 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1172 __ verify_oop(dest->as_register());
1173 } else if (type == T_METADATA) {
1174 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1175 } else {
1176 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1177 }
1178
1179 } else if (dest->is_double_cpu()) {
1180 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1181 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1182 __ movptr(dest->as_register_lo(), src_addr_LO);
1183 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1184
1185 } else if (dest->is_single_xmm()) {
1186 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1187 __ movflt(dest->as_xmm_float_reg(), src_addr);
1188
1189 } else if (dest->is_double_xmm()) {
1190 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1191 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1192
1193 } else if (dest->is_single_fpu()) {
1194 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1195 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1196 __ fld_s(src_addr);
1197
1198 } else if (dest->is_double_fpu()) {
1199 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1200 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1201 __ fld_d(src_addr);
1202
1203 } else {
1204 ShouldNotReachHere();
1205 }
1206 }
1207
1208
1209 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1210 if (src->is_single_stack()) {
1211 if (type == T_OBJECT || type == T_ARRAY) {
1212 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1213 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1214 } else {
1215 #ifndef _LP64
1216 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1217 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1218 #else
1219 //no pushl on 64bits
1220 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1221 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1222 #endif
1223 }
1224
1225 } else if (src->is_double_stack()) {
1226 #ifdef _LP64
1227 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1228 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1229 #else
1230 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1231 // push and pop the part at src + wordSize, adding wordSize for the previous push
1232 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1233 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1234 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1235 #endif // _LP64
1236
1237 } else {
1238 ShouldNotReachHere();
1239 }
1240 }
1241
1242
1243 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1244 assert(src->is_address(), "should not call otherwise");
1245 assert(dest->is_register(), "should not call otherwise");
1246
1247 LIR_Address* addr = src->as_address_ptr();
1248 Address from_addr = as_Address(addr);
1249
1250 if (addr->base()->type() == T_OBJECT) {
1251 __ verify_oop(addr->base()->as_pointer_register());
1252 }
1253
1254 switch (type) {
1255 case T_BOOLEAN: // fall through
1256 case T_BYTE: // fall through
1257 case T_CHAR: // fall through
1258 case T_SHORT:
1259 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1260 // on pre P6 processors we may get partial register stalls
1261 // so blow away the value of to_rinfo before loading a
1262 // partial word into it. Do it here so that it precedes
1263 // the potential patch point below.
1264 __ xorptr(dest->as_register(), dest->as_register());
1265 }
1266 break;
1267 }
1268
1269 PatchingStub* patch = NULL;
1270 if (patch_code != lir_patch_none) {
1271 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1272 assert(from_addr.disp() != 0, "must have");
1273 }
1274 if (info != NULL) {
1275 add_debug_info_for_null_check_here(info);
1276 }
1277
1278 switch (type) {
1279 case T_FLOAT: {
1280 if (dest->is_single_xmm()) {
1281 __ movflt(dest->as_xmm_float_reg(), from_addr);
1282 } else {
1283 assert(dest->is_single_fpu(), "must be");
1284 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1285 __ fld_s(from_addr);
1286 }
1287 break;
1288 }
1289
1290 case T_DOUBLE: {
1291 if (dest->is_double_xmm()) {
1292 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1293 } else {
1294 assert(dest->is_double_fpu(), "must be");
1295 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1296 __ fld_d(from_addr);
1297 }
1298 break;
1299 }
1300
1301 case T_OBJECT: // fall through
1302 case T_ARRAY: // fall through
1303 if (UseCompressedOops && !wide) {
1304 __ movl(dest->as_register(), from_addr);
1305 } else {
1306 __ movptr(dest->as_register(), from_addr);
1307 }
1308 break;
1309
1310 case T_ADDRESS:
1311 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1312 __ movl(dest->as_register(), from_addr);
1313 } else {
1314 __ movptr(dest->as_register(), from_addr);
1315 }
1316 break;
1317 case T_INT:
1318 __ movl(dest->as_register(), from_addr);
1319 break;
1320
1321 case T_LONG: {
1322 Register to_lo = dest->as_register_lo();
1323 Register to_hi = dest->as_register_hi();
1324 #ifdef _LP64
1325 __ movptr(to_lo, as_Address_lo(addr));
1326 #else
1327 Register base = addr->base()->as_register();
1328 Register index = noreg;
1329 if (addr->index()->is_register()) {
1330 index = addr->index()->as_register();
1331 }
1332 if ((base == to_lo && index == to_hi) ||
1333 (base == to_hi && index == to_lo)) {
1334 // addresses with 2 registers are only formed as a result of
1335 // array access so this code will never have to deal with
1336 // patches or null checks.
1337 assert(info == NULL && patch == NULL, "must be");
1338 __ lea(to_hi, as_Address(addr));
1339 __ movl(to_lo, Address(to_hi, 0));
1340 __ movl(to_hi, Address(to_hi, BytesPerWord));
1341 } else if (base == to_lo || index == to_lo) {
1342 assert(base != to_hi, "can't be");
1343 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1344 __ movl(to_hi, as_Address_hi(addr));
1345 if (patch != NULL) {
1346 patching_epilog(patch, lir_patch_high, base, info);
1347 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1348 patch_code = lir_patch_low;
1349 }
1350 __ movl(to_lo, as_Address_lo(addr));
1351 } else {
1352 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1353 __ movl(to_lo, as_Address_lo(addr));
1354 if (patch != NULL) {
1355 patching_epilog(patch, lir_patch_low, base, info);
1356 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1357 patch_code = lir_patch_high;
1358 }
1359 __ movl(to_hi, as_Address_hi(addr));
1360 }
1361 #endif // _LP64
1362 break;
1363 }
1364
1365 case T_BOOLEAN: // fall through
1366 case T_BYTE: {
1367 Register dest_reg = dest->as_register();
1368 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1369 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1370 __ movsbl(dest_reg, from_addr);
1371 } else {
1372 __ movb(dest_reg, from_addr);
1373 __ shll(dest_reg, 24);
1374 __ sarl(dest_reg, 24);
1375 }
1376 break;
1377 }
1378
1379 case T_CHAR: {
1380 Register dest_reg = dest->as_register();
1381 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1382 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1383 __ movzwl(dest_reg, from_addr);
1384 } else {
1385 __ movw(dest_reg, from_addr);
1386 }
1387 break;
1388 }
1389
1390 case T_SHORT: {
1391 Register dest_reg = dest->as_register();
1392 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1393 __ movswl(dest_reg, from_addr);
1394 } else {
1395 __ movw(dest_reg, from_addr);
1396 __ shll(dest_reg, 16);
1397 __ sarl(dest_reg, 16);
1398 }
1399 break;
1400 }
1401
1402 default:
1403 ShouldNotReachHere();
1404 }
1405
1406 if (patch != NULL) {
1407 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1408 }
1409
1410 if (type == T_ARRAY || type == T_OBJECT) {
1411 #ifdef _LP64
1412 if (UseCompressedOops && !wide) {
1413 __ decode_heap_oop(dest->as_register());
1414 }
1415 #endif
1416 __ verify_oop(dest->as_register());
1417 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1418 #ifdef _LP64
1419 if (UseCompressedClassPointers) {
1420 __ decode_klass_not_null(dest->as_register());
1421 }
1422 #endif
1423 }
1424 }
1425
1426
1427 NEEDS_CLEANUP; // This could be static?
1428 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1429 int elem_size = type2aelembytes(type);
1430 switch (elem_size) {
1431 case 1: return Address::times_1;
1432 case 2: return Address::times_2;
1433 case 4: return Address::times_4;
1434 case 8: return Address::times_8;
1435 }
1436 ShouldNotReachHere();
1437 return Address::no_scale;
1438 }
1439
1440
1441 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1442 switch (op->code()) {
1443 case lir_idiv:
1444 case lir_irem:
1445 arithmetic_idiv(op->code(),
1446 op->in_opr1(),
1447 op->in_opr2(),
1448 op->in_opr3(),
1449 op->result_opr(),
1450 op->info());
1451 break;
1452 default: ShouldNotReachHere(); break;
1453 }
1454 }
1455
1456 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1457 #ifdef ASSERT
1458 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1459 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1460 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1461 #endif
1462
1463 if (op->cond() == lir_cond_always) {
1464 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1465 __ jmp (*(op->label()));
1466 } else {
1467 Assembler::Condition acond = Assembler::zero;
1468 if (op->code() == lir_cond_float_branch) {
1469 assert(op->ublock() != NULL, "must have unordered successor");
1470 __ jcc(Assembler::parity, *(op->ublock()->label()));
1471 switch(op->cond()) {
1472 case lir_cond_equal: acond = Assembler::equal; break;
1473 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1474 case lir_cond_less: acond = Assembler::below; break;
1475 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1476 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1477 case lir_cond_greater: acond = Assembler::above; break;
1478 default: ShouldNotReachHere();
1479 }
1480 } else {
1481 switch (op->cond()) {
1482 case lir_cond_equal: acond = Assembler::equal; break;
1483 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1484 case lir_cond_less: acond = Assembler::less; break;
1485 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1486 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1487 case lir_cond_greater: acond = Assembler::greater; break;
1488 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1489 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1490 default: ShouldNotReachHere();
1491 }
1492 }
1493 __ jcc(acond,*(op->label()));
1494 }
1495 }
1496
1497 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1498 LIR_Opr src = op->in_opr();
1499 LIR_Opr dest = op->result_opr();
1500
1501 switch (op->bytecode()) {
1502 case Bytecodes::_i2l:
1503 #ifdef _LP64
1504 __ movl2ptr(dest->as_register_lo(), src->as_register());
1505 #else
1506 move_regs(src->as_register(), dest->as_register_lo());
1507 move_regs(src->as_register(), dest->as_register_hi());
1508 __ sarl(dest->as_register_hi(), 31);
1509 #endif // LP64
1510 break;
1511
1512 case Bytecodes::_l2i:
1513 #ifdef _LP64
1514 __ movl(dest->as_register(), src->as_register_lo());
1515 #else
1516 move_regs(src->as_register_lo(), dest->as_register());
1517 #endif
1518 break;
1519
1520 case Bytecodes::_i2b:
1521 move_regs(src->as_register(), dest->as_register());
1522 __ sign_extend_byte(dest->as_register());
1523 break;
1524
1525 case Bytecodes::_i2c:
1526 move_regs(src->as_register(), dest->as_register());
1527 __ andl(dest->as_register(), 0xFFFF);
1528 break;
1529
1530 case Bytecodes::_i2s:
1531 move_regs(src->as_register(), dest->as_register());
1532 __ sign_extend_short(dest->as_register());
1533 break;
1534
1535
1536 case Bytecodes::_f2d:
1537 case Bytecodes::_d2f:
1538 if (dest->is_single_xmm()) {
1539 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1540 } else if (dest->is_double_xmm()) {
1541 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1542 } else {
1543 assert(src->fpu() == dest->fpu(), "register must be equal");
1544 // do nothing (float result is rounded later through spilling)
1545 }
1546 break;
1547
1548 case Bytecodes::_i2f:
1549 case Bytecodes::_i2d:
1550 if (dest->is_single_xmm()) {
1551 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1552 } else if (dest->is_double_xmm()) {
1553 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1554 } else {
1555 assert(dest->fpu() == 0, "result must be on TOS");
1556 __ movl(Address(rsp, 0), src->as_register());
1557 __ fild_s(Address(rsp, 0));
1558 }
1559 break;
1560
1561 case Bytecodes::_f2i:
1562 case Bytecodes::_d2i:
1563 if (src->is_single_xmm()) {
1564 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1565 } else if (src->is_double_xmm()) {
1566 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1567 } else {
1568 assert(src->fpu() == 0, "input must be on TOS");
1569 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1570 __ fist_s(Address(rsp, 0));
1571 __ movl(dest->as_register(), Address(rsp, 0));
1572 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1573 }
1574
1575 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1576 assert(op->stub() != NULL, "stub required");
1577 __ cmpl(dest->as_register(), 0x80000000);
1578 __ jcc(Assembler::equal, *op->stub()->entry());
1579 __ bind(*op->stub()->continuation());
1580 break;
1581
1582 case Bytecodes::_l2f:
1583 case Bytecodes::_l2d:
1584 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1585 assert(dest->fpu() == 0, "result must be on TOS");
1586
1587 __ movptr(Address(rsp, 0), src->as_register_lo());
1588 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1589 __ fild_d(Address(rsp, 0));
1590 // float result is rounded later through spilling
1591 break;
1592
1593 case Bytecodes::_f2l:
1594 case Bytecodes::_d2l:
1595 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1596 assert(src->fpu() == 0, "input must be on TOS");
1597 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1598
1599 // instruction sequence too long to inline it here
1600 {
1601 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1602 }
1603 break;
1604
1605 default: ShouldNotReachHere();
1606 }
1607 }
1608
1609 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1610 if (op->init_check()) {
1611 __ cmpb(Address(op->klass()->as_register(),
1612 InstanceKlass::init_state_offset()),
1613 InstanceKlass::fully_initialized);
1614 add_debug_info_for_null_check_here(op->stub()->info());
1615 __ jcc(Assembler::notEqual, *op->stub()->entry());
1616 }
1617 __ allocate_object(op->obj()->as_register(),
1618 op->tmp1()->as_register(),
1619 op->tmp2()->as_register(),
1620 op->header_size(),
1621 op->object_size(),
1622 op->klass()->as_register(),
1623 *op->stub()->entry());
1624 __ bind(*op->stub()->continuation());
1625 }
1626
1627 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1628 Register len = op->len()->as_register();
1629 LP64_ONLY( __ movslq(len, len); )
1630
1631 if (UseSlowPath ||
1632 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1633 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1634 __ jmp(*op->stub()->entry());
1635 } else {
1636 Register tmp1 = op->tmp1()->as_register();
1637 Register tmp2 = op->tmp2()->as_register();
1638 Register tmp3 = op->tmp3()->as_register();
1639 if (len == tmp1) {
1640 tmp1 = tmp3;
1641 } else if (len == tmp2) {
1642 tmp2 = tmp3;
1643 } else if (len == tmp3) {
1644 // everything is ok
1645 } else {
1646 __ mov(tmp3, len);
1647 }
1648 __ allocate_array(op->obj()->as_register(),
1649 len,
1650 tmp1,
1651 tmp2,
1652 arrayOopDesc::header_size(op->type()),
1653 array_element_size(op->type()),
1654 op->klass()->as_register(),
1655 *op->stub()->entry());
1656 }
1657 __ bind(*op->stub()->continuation());
1658 }
1659
1660 void LIR_Assembler::type_profile_helper(Register mdo,
1661 ciMethodData *md, ciProfileData *data,
1662 Register recv, Label* update_done) {
1663 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1664 Label next_test;
1665 // See if the receiver is receiver[n].
1666 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1667 __ jccb(Assembler::notEqual, next_test);
1668 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1669 __ addptr(data_addr, DataLayout::counter_increment);
1670 __ jmp(*update_done);
1671 __ bind(next_test);
1672 }
1673
1674 // Didn't find receiver; find next empty slot and fill it in
1675 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1676 Label next_test;
1677 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1678 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1679 __ jccb(Assembler::notEqual, next_test);
1680 __ movptr(recv_addr, recv);
1681 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1682 __ jmp(*update_done);
1683 __ bind(next_test);
1684 }
1685 }
1686
1687 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1688 // we always need a stub for the failure case.
1689 CodeStub* stub = op->stub();
1690 Register obj = op->object()->as_register();
1691 Register k_RInfo = op->tmp1()->as_register();
1692 Register klass_RInfo = op->tmp2()->as_register();
1693 Register dst = op->result_opr()->as_register();
1694 ciKlass* k = op->klass();
1695 Register Rtmp1 = noreg;
1696
1697 // check if it needs to be profiled
1698 ciMethodData* md;
1699 ciProfileData* data;
1700
1701 if (op->should_profile()) {
1702 ciMethod* method = op->profiled_method();
1703 assert(method != NULL, "Should have method");
1704 int bci = op->profiled_bci();
1705 md = method->method_data_or_null();
1706 assert(md != NULL, "Sanity");
1707 data = md->bci_to_data(bci);
1708 assert(data != NULL, "need data for type check");
1709 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1710 }
1711 Label profile_cast_success, profile_cast_failure;
1712 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1713 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1714
1715 if (obj == k_RInfo) {
1716 k_RInfo = dst;
1717 } else if (obj == klass_RInfo) {
1718 klass_RInfo = dst;
1719 }
1720 if (k->is_loaded() && !UseCompressedClassPointers) {
1721 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1722 } else {
1723 Rtmp1 = op->tmp3()->as_register();
1724 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1725 }
1726
1727 assert_different_registers(obj, k_RInfo, klass_RInfo);
1728
1729 __ cmpptr(obj, (int32_t)NULL_WORD);
1730 if (op->should_profile()) {
1731 Label not_null;
1732 __ jccb(Assembler::notEqual, not_null);
1733 // Object is null; update MDO and exit
1734 Register mdo = klass_RInfo;
1735 __ mov_metadata(mdo, md->constant_encoding());
1736 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1737 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1738 __ orl(data_addr, header_bits);
1739 __ jmp(*obj_is_null);
1740 __ bind(not_null);
1741 } else {
1742 __ jcc(Assembler::equal, *obj_is_null);
1743 }
1744
1745 if (!k->is_loaded()) {
1746 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1747 } else {
1748 #ifdef _LP64
1749 __ mov_metadata(k_RInfo, k->constant_encoding());
1750 #endif // _LP64
1751 }
1752 __ verify_oop(obj);
1753
1754 if (op->fast_check()) {
1755 // get object class
1756 // not a safepoint as obj null check happens earlier
1757 #ifdef _LP64
1758 if (UseCompressedClassPointers) {
1759 __ load_klass(Rtmp1, obj);
1760 __ cmpptr(k_RInfo, Rtmp1);
1761 } else {
1762 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1763 }
1764 #else
1765 if (k->is_loaded()) {
1766 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1767 } else {
1768 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1769 }
1770 #endif
1771 __ jcc(Assembler::notEqual, *failure_target);
1772 // successful cast, fall through to profile or jump
1773 } else {
1774 // get object class
1775 // not a safepoint as obj null check happens earlier
1776 __ load_klass(klass_RInfo, obj);
1777 if (k->is_loaded()) {
1778 // See if we get an immediate positive hit
1779 #ifdef _LP64
1780 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1781 #else
1782 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1783 #endif // _LP64
1784 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1785 __ jcc(Assembler::notEqual, *failure_target);
1786 // successful cast, fall through to profile or jump
1787 } else {
1788 // See if we get an immediate positive hit
1789 __ jcc(Assembler::equal, *success_target);
1790 // check for self
1791 #ifdef _LP64
1792 __ cmpptr(klass_RInfo, k_RInfo);
1793 #else
1794 __ cmpklass(klass_RInfo, k->constant_encoding());
1795 #endif // _LP64
1796 __ jcc(Assembler::equal, *success_target);
1797
1798 __ push(klass_RInfo);
1799 #ifdef _LP64
1800 __ push(k_RInfo);
1801 #else
1802 __ pushklass(k->constant_encoding());
1803 #endif // _LP64
1804 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1805 __ pop(klass_RInfo);
1806 __ pop(klass_RInfo);
1807 // result is a boolean
1808 __ cmpl(klass_RInfo, 0);
1809 __ jcc(Assembler::equal, *failure_target);
1810 // successful cast, fall through to profile or jump
1811 }
1812 } else {
1813 // perform the fast part of the checking logic
1814 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1815 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1816 __ push(klass_RInfo);
1817 __ push(k_RInfo);
1818 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1819 __ pop(klass_RInfo);
1820 __ pop(k_RInfo);
1821 // result is a boolean
1822 __ cmpl(k_RInfo, 0);
1823 __ jcc(Assembler::equal, *failure_target);
1824 // successful cast, fall through to profile or jump
1825 }
1826 }
1827 if (op->should_profile()) {
1828 Register mdo = klass_RInfo, recv = k_RInfo;
1829 __ bind(profile_cast_success);
1830 __ mov_metadata(mdo, md->constant_encoding());
1831 __ load_klass(recv, obj);
1832 Label update_done;
1833 type_profile_helper(mdo, md, data, recv, success);
1834 __ jmp(*success);
1835
1836 __ bind(profile_cast_failure);
1837 __ mov_metadata(mdo, md->constant_encoding());
1838 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1839 __ subptr(counter_addr, DataLayout::counter_increment);
1840 __ jmp(*failure);
1841 }
1842 __ jmp(*success);
1843 }
1844
1845
1846 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1847 LIR_Code code = op->code();
1848 if (code == lir_store_check) {
1849 Register value = op->object()->as_register();
1850 Register array = op->array()->as_register();
1851 Register k_RInfo = op->tmp1()->as_register();
1852 Register klass_RInfo = op->tmp2()->as_register();
1853 Register Rtmp1 = op->tmp3()->as_register();
1854
1855 CodeStub* stub = op->stub();
1856
1857 // check if it needs to be profiled
1858 ciMethodData* md;
1859 ciProfileData* data;
1860
1861 if (op->should_profile()) {
1862 ciMethod* method = op->profiled_method();
1863 assert(method != NULL, "Should have method");
1864 int bci = op->profiled_bci();
1865 md = method->method_data_or_null();
1866 assert(md != NULL, "Sanity");
1867 data = md->bci_to_data(bci);
1868 assert(data != NULL, "need data for type check");
1869 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1870 }
1871 Label profile_cast_success, profile_cast_failure, done;
1872 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1873 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1874
1875 __ cmpptr(value, (int32_t)NULL_WORD);
1876 if (op->should_profile()) {
1877 Label not_null;
1878 __ jccb(Assembler::notEqual, not_null);
1879 // Object is null; update MDO and exit
1880 Register mdo = klass_RInfo;
1881 __ mov_metadata(mdo, md->constant_encoding());
1882 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1883 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1884 __ orl(data_addr, header_bits);
1885 __ jmp(done);
1886 __ bind(not_null);
1887 } else {
1888 __ jcc(Assembler::equal, done);
1889 }
1890
1891 add_debug_info_for_null_check_here(op->info_for_exception());
1892 __ load_klass(k_RInfo, array);
1893 __ load_klass(klass_RInfo, value);
1894
1895 // get instance klass (it's already uncompressed)
1896 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1897 // perform the fast part of the checking logic
1898 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1899 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1900 __ push(klass_RInfo);
1901 __ push(k_RInfo);
1902 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1903 __ pop(klass_RInfo);
1904 __ pop(k_RInfo);
1905 // result is a boolean
1906 __ cmpl(k_RInfo, 0);
1907 __ jcc(Assembler::equal, *failure_target);
1908 // fall through to the success case
1909
1910 if (op->should_profile()) {
1911 Register mdo = klass_RInfo, recv = k_RInfo;
1912 __ bind(profile_cast_success);
1913 __ mov_metadata(mdo, md->constant_encoding());
1914 __ load_klass(recv, value);
1915 Label update_done;
1916 type_profile_helper(mdo, md, data, recv, &done);
1917 __ jmpb(done);
1918
1919 __ bind(profile_cast_failure);
1920 __ mov_metadata(mdo, md->constant_encoding());
1921 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1922 __ subptr(counter_addr, DataLayout::counter_increment);
1923 __ jmp(*stub->entry());
1924 }
1925
1926 __ bind(done);
1927 } else
1928 if (code == lir_checkcast) {
1929 Register obj = op->object()->as_register();
1930 Register dst = op->result_opr()->as_register();
1931 Label success;
1932 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1933 __ bind(success);
1934 if (dst != obj) {
1935 __ mov(dst, obj);
1936 }
1937 } else
1938 if (code == lir_instanceof) {
1939 Register obj = op->object()->as_register();
1940 Register dst = op->result_opr()->as_register();
1941 Label success, failure, done;
1942 emit_typecheck_helper(op, &success, &failure, &failure);
1943 __ bind(failure);
1944 __ xorptr(dst, dst);
1945 __ jmpb(done);
1946 __ bind(success);
1947 __ movptr(dst, 1);
1948 __ bind(done);
1949 } else {
1950 ShouldNotReachHere();
1951 }
1952
1953 }
1954
1955
1956 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1957 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1958 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1959 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1960 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1961 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1962 Register addr = op->addr()->as_register();
1963 if (os::is_MP()) {
1964 __ lock();
1965 }
1966 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1967
1968 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1969 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1970 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1971 Register newval = op->new_value()->as_register();
1972 Register cmpval = op->cmp_value()->as_register();
1973 assert(cmpval == rax, "wrong register");
1974 assert(newval != NULL, "new val must be register");
1975 assert(cmpval != newval, "cmp and new values must be in different registers");
1976 assert(cmpval != addr, "cmp and addr must be in different registers");
1977 assert(newval != addr, "new value and addr must be in different registers");
1978
1979 if ( op->code() == lir_cas_obj) {
1980 #ifdef _LP64
1981 if (UseCompressedOops) {
1982 __ encode_heap_oop(cmpval);
1983 __ mov(rscratch1, newval);
1984 __ encode_heap_oop(rscratch1);
1985 if (os::is_MP()) {
1986 __ lock();
1987 }
1988 // cmpval (rax) is implicitly used by this instruction
1989 __ cmpxchgl(rscratch1, Address(addr, 0));
1990 } else
1991 #endif
1992 {
1993 if (os::is_MP()) {
1994 __ lock();
1995 }
1996 __ cmpxchgptr(newval, Address(addr, 0));
1997 }
1998 } else {
1999 assert(op->code() == lir_cas_int, "lir_cas_int expected");
2000 if (os::is_MP()) {
2001 __ lock();
2002 }
2003 __ cmpxchgl(newval, Address(addr, 0));
2004 }
2005 #ifdef _LP64
2006 } else if (op->code() == lir_cas_long) {
2007 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2008 Register newval = op->new_value()->as_register_lo();
2009 Register cmpval = op->cmp_value()->as_register_lo();
2010 assert(cmpval == rax, "wrong register");
2011 assert(newval != NULL, "new val must be register");
2012 assert(cmpval != newval, "cmp and new values must be in different registers");
2013 assert(cmpval != addr, "cmp and addr must be in different registers");
2014 assert(newval != addr, "new value and addr must be in different registers");
2015 if (os::is_MP()) {
2016 __ lock();
2017 }
2018 __ cmpxchgq(newval, Address(addr, 0));
2019 #endif // _LP64
2020 } else {
2021 Unimplemented();
2022 }
2023 }
2024
2025 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
2026 Assembler::Condition acond, ncond;
2027 switch (condition) {
2028 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2029 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2030 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2031 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2032 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2033 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2034 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2035 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2036 default: ShouldNotReachHere();
2037 }
2038
2039 if (opr1->is_cpu_register()) {
2040 reg2reg(opr1, result);
2041 } else if (opr1->is_stack()) {
2042 stack2reg(opr1, result, result->type());
2043 } else if (opr1->is_constant()) {
2044 const2reg(opr1, result, lir_patch_none, NULL);
2045 } else {
2046 ShouldNotReachHere();
2047 }
2048
2049 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2050 // optimized version that does not require a branch
2051 if (opr2->is_single_cpu()) {
2052 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2053 __ cmov(ncond, result->as_register(), opr2->as_register());
2054 } else if (opr2->is_double_cpu()) {
2055 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2056 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2057 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2058 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2059 } else if (opr2->is_single_stack()) {
2060 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2061 } else if (opr2->is_double_stack()) {
2062 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2063 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2064 } else {
2065 ShouldNotReachHere();
2066 }
2067
2068 } else {
2069 Label skip;
2070 __ jcc (acond, skip);
2071 if (opr2->is_cpu_register()) {
2072 reg2reg(opr2, result);
2073 } else if (opr2->is_stack()) {
2074 stack2reg(opr2, result, result->type());
2075 } else if (opr2->is_constant()) {
2076 const2reg(opr2, result, lir_patch_none, NULL);
2077 } else {
2078 ShouldNotReachHere();
2079 }
2080 __ bind(skip);
2081 }
2082 }
2083
2084
2085 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2086 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2087
2088 if (left->is_single_cpu()) {
2089 assert(left == dest, "left and dest must be equal");
2090 Register lreg = left->as_register();
2091
2092 if (right->is_single_cpu()) {
2093 // cpu register - cpu register
2094 Register rreg = right->as_register();
2095 switch (code) {
2096 case lir_add: __ addl (lreg, rreg); break;
2097 case lir_sub: __ subl (lreg, rreg); break;
2098 case lir_mul: __ imull(lreg, rreg); break;
2099 default: ShouldNotReachHere();
2100 }
2101
2102 } else if (right->is_stack()) {
2103 // cpu register - stack
2104 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2105 switch (code) {
2106 case lir_add: __ addl(lreg, raddr); break;
2107 case lir_sub: __ subl(lreg, raddr); break;
2108 default: ShouldNotReachHere();
2109 }
2110
2111 } else if (right->is_constant()) {
2112 // cpu register - constant
2113 jint c = right->as_constant_ptr()->as_jint();
2114 switch (code) {
2115 case lir_add: {
2116 __ incrementl(lreg, c);
2117 break;
2118 }
2119 case lir_sub: {
2120 __ decrementl(lreg, c);
2121 break;
2122 }
2123 default: ShouldNotReachHere();
2124 }
2125
2126 } else {
2127 ShouldNotReachHere();
2128 }
2129
2130 } else if (left->is_double_cpu()) {
2131 assert(left == dest, "left and dest must be equal");
2132 Register lreg_lo = left->as_register_lo();
2133 Register lreg_hi = left->as_register_hi();
2134
2135 if (right->is_double_cpu()) {
2136 // cpu register - cpu register
2137 Register rreg_lo = right->as_register_lo();
2138 Register rreg_hi = right->as_register_hi();
2139 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2140 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2141 switch (code) {
2142 case lir_add:
2143 __ addptr(lreg_lo, rreg_lo);
2144 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2145 break;
2146 case lir_sub:
2147 __ subptr(lreg_lo, rreg_lo);
2148 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2149 break;
2150 case lir_mul:
2151 #ifdef _LP64
2152 __ imulq(lreg_lo, rreg_lo);
2153 #else
2154 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2155 __ imull(lreg_hi, rreg_lo);
2156 __ imull(rreg_hi, lreg_lo);
2157 __ addl (rreg_hi, lreg_hi);
2158 __ mull (rreg_lo);
2159 __ addl (lreg_hi, rreg_hi);
2160 #endif // _LP64
2161 break;
2162 default:
2163 ShouldNotReachHere();
2164 }
2165
2166 } else if (right->is_constant()) {
2167 // cpu register - constant
2168 #ifdef _LP64
2169 jlong c = right->as_constant_ptr()->as_jlong_bits();
2170 __ movptr(r10, (intptr_t) c);
2171 switch (code) {
2172 case lir_add:
2173 __ addptr(lreg_lo, r10);
2174 break;
2175 case lir_sub:
2176 __ subptr(lreg_lo, r10);
2177 break;
2178 default:
2179 ShouldNotReachHere();
2180 }
2181 #else
2182 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2183 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2184 switch (code) {
2185 case lir_add:
2186 __ addptr(lreg_lo, c_lo);
2187 __ adcl(lreg_hi, c_hi);
2188 break;
2189 case lir_sub:
2190 __ subptr(lreg_lo, c_lo);
2191 __ sbbl(lreg_hi, c_hi);
2192 break;
2193 default:
2194 ShouldNotReachHere();
2195 }
2196 #endif // _LP64
2197
2198 } else {
2199 ShouldNotReachHere();
2200 }
2201
2202 } else if (left->is_single_xmm()) {
2203 assert(left == dest, "left and dest must be equal");
2204 XMMRegister lreg = left->as_xmm_float_reg();
2205
2206 if (right->is_single_xmm()) {
2207 XMMRegister rreg = right->as_xmm_float_reg();
2208 switch (code) {
2209 case lir_add: __ addss(lreg, rreg); break;
2210 case lir_sub: __ subss(lreg, rreg); break;
2211 case lir_mul_strictfp: // fall through
2212 case lir_mul: __ mulss(lreg, rreg); break;
2213 case lir_div_strictfp: // fall through
2214 case lir_div: __ divss(lreg, rreg); break;
2215 default: ShouldNotReachHere();
2216 }
2217 } else {
2218 Address raddr;
2219 if (right->is_single_stack()) {
2220 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2221 } else if (right->is_constant()) {
2222 // hack for now
2223 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2224 } else {
2225 ShouldNotReachHere();
2226 }
2227 switch (code) {
2228 case lir_add: __ addss(lreg, raddr); break;
2229 case lir_sub: __ subss(lreg, raddr); break;
2230 case lir_mul_strictfp: // fall through
2231 case lir_mul: __ mulss(lreg, raddr); break;
2232 case lir_div_strictfp: // fall through
2233 case lir_div: __ divss(lreg, raddr); break;
2234 default: ShouldNotReachHere();
2235 }
2236 }
2237
2238 } else if (left->is_double_xmm()) {
2239 assert(left == dest, "left and dest must be equal");
2240
2241 XMMRegister lreg = left->as_xmm_double_reg();
2242 if (right->is_double_xmm()) {
2243 XMMRegister rreg = right->as_xmm_double_reg();
2244 switch (code) {
2245 case lir_add: __ addsd(lreg, rreg); break;
2246 case lir_sub: __ subsd(lreg, rreg); break;
2247 case lir_mul_strictfp: // fall through
2248 case lir_mul: __ mulsd(lreg, rreg); break;
2249 case lir_div_strictfp: // fall through
2250 case lir_div: __ divsd(lreg, rreg); break;
2251 default: ShouldNotReachHere();
2252 }
2253 } else {
2254 Address raddr;
2255 if (right->is_double_stack()) {
2256 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2257 } else if (right->is_constant()) {
2258 // hack for now
2259 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2260 } else {
2261 ShouldNotReachHere();
2262 }
2263 switch (code) {
2264 case lir_add: __ addsd(lreg, raddr); break;
2265 case lir_sub: __ subsd(lreg, raddr); break;
2266 case lir_mul_strictfp: // fall through
2267 case lir_mul: __ mulsd(lreg, raddr); break;
2268 case lir_div_strictfp: // fall through
2269 case lir_div: __ divsd(lreg, raddr); break;
2270 default: ShouldNotReachHere();
2271 }
2272 }
2273
2274 } else if (left->is_single_fpu()) {
2275 assert(dest->is_single_fpu(), "fpu stack allocation required");
2276
2277 if (right->is_single_fpu()) {
2278 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2279
2280 } else {
2281 assert(left->fpu_regnr() == 0, "left must be on TOS");
2282 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2283
2284 Address raddr;
2285 if (right->is_single_stack()) {
2286 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2287 } else if (right->is_constant()) {
2288 address const_addr = float_constant(right->as_jfloat());
2289 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2290 // hack for now
2291 raddr = __ as_Address(InternalAddress(const_addr));
2292 } else {
2293 ShouldNotReachHere();
2294 }
2295
2296 switch (code) {
2297 case lir_add: __ fadd_s(raddr); break;
2298 case lir_sub: __ fsub_s(raddr); break;
2299 case lir_mul_strictfp: // fall through
2300 case lir_mul: __ fmul_s(raddr); break;
2301 case lir_div_strictfp: // fall through
2302 case lir_div: __ fdiv_s(raddr); break;
2303 default: ShouldNotReachHere();
2304 }
2305 }
2306
2307 } else if (left->is_double_fpu()) {
2308 assert(dest->is_double_fpu(), "fpu stack allocation required");
2309
2310 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2311 // Double values require special handling for strictfp mul/div on x86
2312 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2313 __ fmulp(left->fpu_regnrLo() + 1);
2314 }
2315
2316 if (right->is_double_fpu()) {
2317 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2318
2319 } else {
2320 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2321 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2322
2323 Address raddr;
2324 if (right->is_double_stack()) {
2325 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2326 } else if (right->is_constant()) {
2327 // hack for now
2328 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2329 } else {
2330 ShouldNotReachHere();
2331 }
2332
2333 switch (code) {
2334 case lir_add: __ fadd_d(raddr); break;
2335 case lir_sub: __ fsub_d(raddr); break;
2336 case lir_mul_strictfp: // fall through
2337 case lir_mul: __ fmul_d(raddr); break;
2338 case lir_div_strictfp: // fall through
2339 case lir_div: __ fdiv_d(raddr); break;
2340 default: ShouldNotReachHere();
2341 }
2342 }
2343
2344 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2345 // Double values require special handling for strictfp mul/div on x86
2346 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2347 __ fmulp(dest->fpu_regnrLo() + 1);
2348 }
2349
2350 } else if (left->is_single_stack() || left->is_address()) {
2351 assert(left == dest, "left and dest must be equal");
2352
2353 Address laddr;
2354 if (left->is_single_stack()) {
2355 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2356 } else if (left->is_address()) {
2357 laddr = as_Address(left->as_address_ptr());
2358 } else {
2359 ShouldNotReachHere();
2360 }
2361
2362 if (right->is_single_cpu()) {
2363 Register rreg = right->as_register();
2364 switch (code) {
2365 case lir_add: __ addl(laddr, rreg); break;
2366 case lir_sub: __ subl(laddr, rreg); break;
2367 default: ShouldNotReachHere();
2368 }
2369 } else if (right->is_constant()) {
2370 jint c = right->as_constant_ptr()->as_jint();
2371 switch (code) {
2372 case lir_add: {
2373 __ incrementl(laddr, c);
2374 break;
2375 }
2376 case lir_sub: {
2377 __ decrementl(laddr, c);
2378 break;
2379 }
2380 default: ShouldNotReachHere();
2381 }
2382 } else {
2383 ShouldNotReachHere();
2384 }
2385
2386 } else {
2387 ShouldNotReachHere();
2388 }
2389 }
2390
2391 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2392 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2393 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2394 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2395
2396 bool left_is_tos = (left_index == 0);
2397 bool dest_is_tos = (dest_index == 0);
2398 int non_tos_index = (left_is_tos ? right_index : left_index);
2399
2400 switch (code) {
2401 case lir_add:
2402 if (pop_fpu_stack) __ faddp(non_tos_index);
2403 else if (dest_is_tos) __ fadd (non_tos_index);
2404 else __ fadda(non_tos_index);
2405 break;
2406
2407 case lir_sub:
2408 if (left_is_tos) {
2409 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2410 else if (dest_is_tos) __ fsub (non_tos_index);
2411 else __ fsubra(non_tos_index);
2412 } else {
2413 if (pop_fpu_stack) __ fsubp (non_tos_index);
2414 else if (dest_is_tos) __ fsubr (non_tos_index);
2415 else __ fsuba (non_tos_index);
2416 }
2417 break;
2418
2419 case lir_mul_strictfp: // fall through
2420 case lir_mul:
2421 if (pop_fpu_stack) __ fmulp(non_tos_index);
2422 else if (dest_is_tos) __ fmul (non_tos_index);
2423 else __ fmula(non_tos_index);
2424 break;
2425
2426 case lir_div_strictfp: // fall through
2427 case lir_div:
2428 if (left_is_tos) {
2429 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2430 else if (dest_is_tos) __ fdiv (non_tos_index);
2431 else __ fdivra(non_tos_index);
2432 } else {
2433 if (pop_fpu_stack) __ fdivp (non_tos_index);
2434 else if (dest_is_tos) __ fdivr (non_tos_index);
2435 else __ fdiva (non_tos_index);
2436 }
2437 break;
2438
2439 case lir_rem:
2440 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2441 __ fremr(noreg);
2442 break;
2443
2444 default:
2445 ShouldNotReachHere();
2446 }
2447 }
2448
2449
2450 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2451 if (value->is_double_xmm()) {
2452 switch(code) {
2453 case lir_abs :
2454 {
2455 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2456 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2457 }
2458 __ andpd(dest->as_xmm_double_reg(),
2459 ExternalAddress((address)double_signmask_pool));
2460 }
2461 break;
2462
2463 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2464 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2465 default : ShouldNotReachHere();
2466 }
2467
2468 } else if (value->is_double_fpu()) {
2469 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2470 switch(code) {
2471 case lir_log : __ flog() ; break;
2472 case lir_log10 : __ flog10() ; break;
2473 case lir_abs : __ fabs() ; break;
2474 case lir_sqrt : __ fsqrt(); break;
2475 case lir_sin :
2476 // Should consider not saving rbx, if not necessary
2477 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2478 break;
2479 case lir_cos :
2480 // Should consider not saving rbx, if not necessary
2481 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2482 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2483 break;
2484 case lir_tan :
2485 // Should consider not saving rbx, if not necessary
2486 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2487 break;
2488 case lir_exp :
2489 __ exp_with_fallback(op->as_Op2()->fpu_stack_size());
2490 break;
2491 case lir_pow :
2492 __ pow_with_fallback(op->as_Op2()->fpu_stack_size());
2493 break;
2494 default : ShouldNotReachHere();
2495 }
2496 } else {
2497 Unimplemented();
2498 }
2499 }
2500
2501 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2502 // assert(left->destroys_register(), "check");
2503 if (left->is_single_cpu()) {
2504 Register reg = left->as_register();
2505 if (right->is_constant()) {
2506 int val = right->as_constant_ptr()->as_jint();
2507 switch (code) {
2508 case lir_logic_and: __ andl (reg, val); break;
2509 case lir_logic_or: __ orl (reg, val); break;
2510 case lir_logic_xor: __ xorl (reg, val); break;
2511 default: ShouldNotReachHere();
2512 }
2513 } else if (right->is_stack()) {
2514 // added support for stack operands
2515 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2516 switch (code) {
2517 case lir_logic_and: __ andl (reg, raddr); break;
2518 case lir_logic_or: __ orl (reg, raddr); break;
2519 case lir_logic_xor: __ xorl (reg, raddr); break;
2520 default: ShouldNotReachHere();
2521 }
2522 } else {
2523 Register rright = right->as_register();
2524 switch (code) {
2525 case lir_logic_and: __ andptr (reg, rright); break;
2526 case lir_logic_or : __ orptr (reg, rright); break;
2527 case lir_logic_xor: __ xorptr (reg, rright); break;
2528 default: ShouldNotReachHere();
2529 }
2530 }
2531 move_regs(reg, dst->as_register());
2532 } else {
2533 Register l_lo = left->as_register_lo();
2534 Register l_hi = left->as_register_hi();
2535 if (right->is_constant()) {
2536 #ifdef _LP64
2537 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2538 switch (code) {
2539 case lir_logic_and:
2540 __ andq(l_lo, rscratch1);
2541 break;
2542 case lir_logic_or:
2543 __ orq(l_lo, rscratch1);
2544 break;
2545 case lir_logic_xor:
2546 __ xorq(l_lo, rscratch1);
2547 break;
2548 default: ShouldNotReachHere();
2549 }
2550 #else
2551 int r_lo = right->as_constant_ptr()->as_jint_lo();
2552 int r_hi = right->as_constant_ptr()->as_jint_hi();
2553 switch (code) {
2554 case lir_logic_and:
2555 __ andl(l_lo, r_lo);
2556 __ andl(l_hi, r_hi);
2557 break;
2558 case lir_logic_or:
2559 __ orl(l_lo, r_lo);
2560 __ orl(l_hi, r_hi);
2561 break;
2562 case lir_logic_xor:
2563 __ xorl(l_lo, r_lo);
2564 __ xorl(l_hi, r_hi);
2565 break;
2566 default: ShouldNotReachHere();
2567 }
2568 #endif // _LP64
2569 } else {
2570 #ifdef _LP64
2571 Register r_lo;
2572 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2573 r_lo = right->as_register();
2574 } else {
2575 r_lo = right->as_register_lo();
2576 }
2577 #else
2578 Register r_lo = right->as_register_lo();
2579 Register r_hi = right->as_register_hi();
2580 assert(l_lo != r_hi, "overwriting registers");
2581 #endif
2582 switch (code) {
2583 case lir_logic_and:
2584 __ andptr(l_lo, r_lo);
2585 NOT_LP64(__ andptr(l_hi, r_hi);)
2586 break;
2587 case lir_logic_or:
2588 __ orptr(l_lo, r_lo);
2589 NOT_LP64(__ orptr(l_hi, r_hi);)
2590 break;
2591 case lir_logic_xor:
2592 __ xorptr(l_lo, r_lo);
2593 NOT_LP64(__ xorptr(l_hi, r_hi);)
2594 break;
2595 default: ShouldNotReachHere();
2596 }
2597 }
2598
2599 Register dst_lo = dst->as_register_lo();
2600 Register dst_hi = dst->as_register_hi();
2601
2602 #ifdef _LP64
2603 move_regs(l_lo, dst_lo);
2604 #else
2605 if (dst_lo == l_hi) {
2606 assert(dst_hi != l_lo, "overwriting registers");
2607 move_regs(l_hi, dst_hi);
2608 move_regs(l_lo, dst_lo);
2609 } else {
2610 assert(dst_lo != l_hi, "overwriting registers");
2611 move_regs(l_lo, dst_lo);
2612 move_regs(l_hi, dst_hi);
2613 }
2614 #endif // _LP64
2615 }
2616 }
2617
2618
2619 // we assume that rax, and rdx can be overwritten
2620 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2621
2622 assert(left->is_single_cpu(), "left must be register");
2623 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2624 assert(result->is_single_cpu(), "result must be register");
2625
2626 // assert(left->destroys_register(), "check");
2627 // assert(right->destroys_register(), "check");
2628
2629 Register lreg = left->as_register();
2630 Register dreg = result->as_register();
2631
2632 if (right->is_constant()) {
2633 int divisor = right->as_constant_ptr()->as_jint();
2634 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2635 if (code == lir_idiv) {
2636 assert(lreg == rax, "must be rax,");
2637 assert(temp->as_register() == rdx, "tmp register must be rdx");
2638 __ cdql(); // sign extend into rdx:rax
2639 if (divisor == 2) {
2640 __ subl(lreg, rdx);
2641 } else {
2642 __ andl(rdx, divisor - 1);
2643 __ addl(lreg, rdx);
2644 }
2645 __ sarl(lreg, log2_intptr(divisor));
2646 move_regs(lreg, dreg);
2647 } else if (code == lir_irem) {
2648 Label done;
2649 __ mov(dreg, lreg);
2650 __ andl(dreg, 0x80000000 | (divisor - 1));
2651 __ jcc(Assembler::positive, done);
2652 __ decrement(dreg);
2653 __ orl(dreg, ~(divisor - 1));
2654 __ increment(dreg);
2655 __ bind(done);
2656 } else {
2657 ShouldNotReachHere();
2658 }
2659 } else {
2660 Register rreg = right->as_register();
2661 assert(lreg == rax, "left register must be rax,");
2662 assert(rreg != rdx, "right register must not be rdx");
2663 assert(temp->as_register() == rdx, "tmp register must be rdx");
2664
2665 move_regs(lreg, rax);
2666
2667 int idivl_offset = __ corrected_idivl(rreg);
2668 add_debug_info_for_div0(idivl_offset, info);
2669 if (code == lir_irem) {
2670 move_regs(rdx, dreg); // result is in rdx
2671 } else {
2672 move_regs(rax, dreg);
2673 }
2674 }
2675 }
2676
2677
2678 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2679 if (opr1->is_single_cpu()) {
2680 Register reg1 = opr1->as_register();
2681 if (opr2->is_single_cpu()) {
2682 // cpu register - cpu register
2683 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2684 __ cmpptr(reg1, opr2->as_register());
2685 } else {
2686 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2687 __ cmpl(reg1, opr2->as_register());
2688 }
2689 } else if (opr2->is_stack()) {
2690 // cpu register - stack
2691 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2692 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2693 } else {
2694 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2695 }
2696 } else if (opr2->is_constant()) {
2697 // cpu register - constant
2698 LIR_Const* c = opr2->as_constant_ptr();
2699 if (c->type() == T_INT) {
2700 __ cmpl(reg1, c->as_jint());
2701 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2702 // In 64bit oops are single register
2703 jobject o = c->as_jobject();
2704 if (o == NULL) {
2705 __ cmpptr(reg1, (int32_t)NULL_WORD);
2706 } else {
2707 #ifdef _LP64
2708 __ movoop(rscratch1, o);
2709 __ cmpptr(reg1, rscratch1);
2710 #else
2711 __ cmpoop(reg1, c->as_jobject());
2712 #endif // _LP64
2713 }
2714 } else {
2715 fatal(err_msg("unexpected type: %s", basictype_to_str(c->type())));
2716 }
2717 // cpu register - address
2718 } else if (opr2->is_address()) {
2719 if (op->info() != NULL) {
2720 add_debug_info_for_null_check_here(op->info());
2721 }
2722 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2723 } else {
2724 ShouldNotReachHere();
2725 }
2726
2727 } else if(opr1->is_double_cpu()) {
2728 Register xlo = opr1->as_register_lo();
2729 Register xhi = opr1->as_register_hi();
2730 if (opr2->is_double_cpu()) {
2731 #ifdef _LP64
2732 __ cmpptr(xlo, opr2->as_register_lo());
2733 #else
2734 // cpu register - cpu register
2735 Register ylo = opr2->as_register_lo();
2736 Register yhi = opr2->as_register_hi();
2737 __ subl(xlo, ylo);
2738 __ sbbl(xhi, yhi);
2739 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2740 __ orl(xhi, xlo);
2741 }
2742 #endif // _LP64
2743 } else if (opr2->is_constant()) {
2744 // cpu register - constant 0
2745 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2746 #ifdef _LP64
2747 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2748 #else
2749 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2750 __ orl(xhi, xlo);
2751 #endif // _LP64
2752 } else {
2753 ShouldNotReachHere();
2754 }
2755
2756 } else if (opr1->is_single_xmm()) {
2757 XMMRegister reg1 = opr1->as_xmm_float_reg();
2758 if (opr2->is_single_xmm()) {
2759 // xmm register - xmm register
2760 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2761 } else if (opr2->is_stack()) {
2762 // xmm register - stack
2763 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2764 } else if (opr2->is_constant()) {
2765 // xmm register - constant
2766 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2767 } else if (opr2->is_address()) {
2768 // xmm register - address
2769 if (op->info() != NULL) {
2770 add_debug_info_for_null_check_here(op->info());
2771 }
2772 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2773 } else {
2774 ShouldNotReachHere();
2775 }
2776
2777 } else if (opr1->is_double_xmm()) {
2778 XMMRegister reg1 = opr1->as_xmm_double_reg();
2779 if (opr2->is_double_xmm()) {
2780 // xmm register - xmm register
2781 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2782 } else if (opr2->is_stack()) {
2783 // xmm register - stack
2784 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2785 } else if (opr2->is_constant()) {
2786 // xmm register - constant
2787 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2788 } else if (opr2->is_address()) {
2789 // xmm register - address
2790 if (op->info() != NULL) {
2791 add_debug_info_for_null_check_here(op->info());
2792 }
2793 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2794 } else {
2795 ShouldNotReachHere();
2796 }
2797
2798 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2799 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2800 assert(opr2->is_fpu_register(), "both must be registers");
2801 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2802
2803 } else if (opr1->is_address() && opr2->is_constant()) {
2804 LIR_Const* c = opr2->as_constant_ptr();
2805 #ifdef _LP64
2806 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2807 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2808 __ movoop(rscratch1, c->as_jobject());
2809 }
2810 #endif // LP64
2811 if (op->info() != NULL) {
2812 add_debug_info_for_null_check_here(op->info());
2813 }
2814 // special case: address - constant
2815 LIR_Address* addr = opr1->as_address_ptr();
2816 if (c->type() == T_INT) {
2817 __ cmpl(as_Address(addr), c->as_jint());
2818 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2819 #ifdef _LP64
2820 // %%% Make this explode if addr isn't reachable until we figure out a
2821 // better strategy by giving noreg as the temp for as_Address
2822 __ cmpptr(rscratch1, as_Address(addr, noreg));
2823 #else
2824 __ cmpoop(as_Address(addr), c->as_jobject());
2825 #endif // _LP64
2826 } else {
2827 ShouldNotReachHere();
2828 }
2829
2830 } else {
2831 ShouldNotReachHere();
2832 }
2833 }
2834
2835 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2836 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2837 if (left->is_single_xmm()) {
2838 assert(right->is_single_xmm(), "must match");
2839 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2840 } else if (left->is_double_xmm()) {
2841 assert(right->is_double_xmm(), "must match");
2842 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2843
2844 } else {
2845 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2846 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2847
2848 assert(left->fpu() == 0, "left must be on TOS");
2849 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2850 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2851 }
2852 } else {
2853 assert(code == lir_cmp_l2i, "check");
2854 #ifdef _LP64
2855 Label done;
2856 Register dest = dst->as_register();
2857 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2858 __ movl(dest, -1);
2859 __ jccb(Assembler::less, done);
2860 __ set_byte_if_not_zero(dest);
2861 __ movzbl(dest, dest);
2862 __ bind(done);
2863 #else
2864 __ lcmp2int(left->as_register_hi(),
2865 left->as_register_lo(),
2866 right->as_register_hi(),
2867 right->as_register_lo());
2868 move_regs(left->as_register_hi(), dst->as_register());
2869 #endif // _LP64
2870 }
2871 }
2872
2873
2874 void LIR_Assembler::align_call(LIR_Code code) {
2875 if (os::is_MP()) {
2876 // make sure that the displacement word of the call ends up word aligned
2877 int offset = __ offset();
2878 switch (code) {
2879 case lir_static_call:
2880 case lir_optvirtual_call:
2881 case lir_dynamic_call:
2882 offset += NativeCall::displacement_offset;
2883 break;
2884 case lir_icvirtual_call:
2885 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2886 break;
2887 case lir_virtual_call: // currently, sparc-specific for niagara
2888 default: ShouldNotReachHere();
2889 }
2890 while (offset++ % BytesPerWord != 0) {
2891 __ nop();
2892 }
2893 }
2894 }
2895
2896
2897 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2898 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2899 "must be aligned");
2900 __ call(AddressLiteral(op->addr(), rtype));
2901 add_call_info(code_offset(), op->info());
2902 }
2903
2904
2905 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2906 __ ic_call(op->addr());
2907 add_call_info(code_offset(), op->info());
2908 assert(!os::is_MP() ||
2909 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2910 "must be aligned");
2911 }
2912
2913
2914 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2915 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2916 ShouldNotReachHere();
2917 }
2918
2919
2920 void LIR_Assembler::emit_static_call_stub() {
2921 address call_pc = __ pc();
2922 address stub = __ start_a_stub(call_stub_size);
2923 if (stub == NULL) {
2924 bailout("static call stub overflow");
2925 return;
2926 }
2927
2928 int start = __ offset();
2929 if (os::is_MP()) {
2930 // make sure that the displacement word of the call ends up word aligned
2931 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset;
2932 while (offset++ % BytesPerWord != 0) {
2933 __ nop();
2934 }
2935 }
2936 __ relocate(static_stub_Relocation::spec(call_pc));
2937 __ mov_metadata(rbx, (Metadata*)NULL);
2938 // must be set to -1 at code generation time
2939 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2940 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2941 __ jump(RuntimeAddress(__ pc()));
2942
2943 assert(__ offset() - start <= call_stub_size, "stub too big");
2944 __ end_a_stub();
2945 }
2946
2947
2948 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2949 assert(exceptionOop->as_register() == rax, "must match");
2950 assert(exceptionPC->as_register() == rdx, "must match");
2951
2952 // exception object is not added to oop map by LinearScan
2953 // (LinearScan assumes that no oops are in fixed registers)
2954 info->add_register_oop(exceptionOop);
2955 Runtime1::StubID unwind_id;
2956
2957 // get current pc information
2958 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2959 int pc_for_athrow_offset = __ offset();
2960 InternalAddress pc_for_athrow(__ pc());
2961 __ lea(exceptionPC->as_register(), pc_for_athrow);
2962 add_call_info(pc_for_athrow_offset, info); // for exception handler
2963
2964 __ verify_not_null_oop(rax);
2965 // search an exception handler (rax: exception oop, rdx: throwing pc)
2966 if (compilation()->has_fpu_code()) {
2967 unwind_id = Runtime1::handle_exception_id;
2968 } else {
2969 unwind_id = Runtime1::handle_exception_nofpu_id;
2970 }
2971 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2972
2973 // enough room for two byte trap
2974 __ nop();
2975 }
2976
2977
2978 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2979 assert(exceptionOop->as_register() == rax, "must match");
2980
2981 __ jmp(_unwind_handler_entry);
2982 }
2983
2984
2985 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2986
2987 // optimized version for linear scan:
2988 // * count must be already in ECX (guaranteed by LinearScan)
2989 // * left and dest must be equal
2990 // * tmp must be unused
2991 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2992 assert(left == dest, "left and dest must be equal");
2993 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2994
2995 if (left->is_single_cpu()) {
2996 Register value = left->as_register();
2997 assert(value != SHIFT_count, "left cannot be ECX");
2998
2999 switch (code) {
3000 case lir_shl: __ shll(value); break;
3001 case lir_shr: __ sarl(value); break;
3002 case lir_ushr: __ shrl(value); break;
3003 default: ShouldNotReachHere();
3004 }
3005 } else if (left->is_double_cpu()) {
3006 Register lo = left->as_register_lo();
3007 Register hi = left->as_register_hi();
3008 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
3009 #ifdef _LP64
3010 switch (code) {
3011 case lir_shl: __ shlptr(lo); break;
3012 case lir_shr: __ sarptr(lo); break;
3013 case lir_ushr: __ shrptr(lo); break;
3014 default: ShouldNotReachHere();
3015 }
3016 #else
3017
3018 switch (code) {
3019 case lir_shl: __ lshl(hi, lo); break;
3020 case lir_shr: __ lshr(hi, lo, true); break;
3021 case lir_ushr: __ lshr(hi, lo, false); break;
3022 default: ShouldNotReachHere();
3023 }
3024 #endif // LP64
3025 } else {
3026 ShouldNotReachHere();
3027 }
3028 }
3029
3030
3031 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
3032 if (dest->is_single_cpu()) {
3033 // first move left into dest so that left is not destroyed by the shift
3034 Register value = dest->as_register();
3035 count = count & 0x1F; // Java spec
3036
3037 move_regs(left->as_register(), value);
3038 switch (code) {
3039 case lir_shl: __ shll(value, count); break;
3040 case lir_shr: __ sarl(value, count); break;
3041 case lir_ushr: __ shrl(value, count); break;
3042 default: ShouldNotReachHere();
3043 }
3044 } else if (dest->is_double_cpu()) {
3045 #ifndef _LP64
3046 Unimplemented();
3047 #else
3048 // first move left into dest so that left is not destroyed by the shift
3049 Register value = dest->as_register_lo();
3050 count = count & 0x1F; // Java spec
3051
3052 move_regs(left->as_register_lo(), value);
3053 switch (code) {
3054 case lir_shl: __ shlptr(value, count); break;
3055 case lir_shr: __ sarptr(value, count); break;
3056 case lir_ushr: __ shrptr(value, count); break;
3057 default: ShouldNotReachHere();
3058 }
3059 #endif // _LP64
3060 } else {
3061 ShouldNotReachHere();
3062 }
3063 }
3064
3065
3066 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3067 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3068 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3069 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3070 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3071 }
3072
3073
3074 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3075 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3076 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3077 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3078 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3079 }
3080
3081
3082 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3083 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3084 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3085 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3086 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3087 }
3088
3089
3090 // This code replaces a call to arraycopy; no exception may
3091 // be thrown in this code, they must be thrown in the System.arraycopy
3092 // activation frame; we could save some checks if this would not be the case
3093 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3094 ciArrayKlass* default_type = op->expected_type();
3095 Register src = op->src()->as_register();
3096 Register dst = op->dst()->as_register();
3097 Register src_pos = op->src_pos()->as_register();
3098 Register dst_pos = op->dst_pos()->as_register();
3099 Register length = op->length()->as_register();
3100 Register tmp = op->tmp()->as_register();
3101
3102 CodeStub* stub = op->stub();
3103 int flags = op->flags();
3104 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3105 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3106
3107 // if we don't know anything, just go through the generic arraycopy
3108 if (default_type == NULL) {
3109 Label done;
3110 // save outgoing arguments on stack in case call to System.arraycopy is needed
3111 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3112 // for interpreter calling conventions. Now we have to do it in new style conventions.
3113 // For the moment until C1 gets the new register allocator I just force all the
3114 // args to the right place (except the register args) and then on the back side
3115 // reload the register args properly if we go slow path. Yuck
3116
3117 // These are proper for the calling convention
3118 store_parameter(length, 2);
3119 store_parameter(dst_pos, 1);
3120 store_parameter(dst, 0);
3121
3122 // these are just temporary placements until we need to reload
3123 store_parameter(src_pos, 3);
3124 store_parameter(src, 4);
3125 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3126
3127 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3128
3129 address copyfunc_addr = StubRoutines::generic_arraycopy();
3130
3131 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3132 #ifdef _LP64
3133 // The arguments are in java calling convention so we can trivially shift them to C
3134 // convention
3135 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3136 __ mov(c_rarg0, j_rarg0);
3137 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3138 __ mov(c_rarg1, j_rarg1);
3139 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3140 __ mov(c_rarg2, j_rarg2);
3141 assert_different_registers(c_rarg3, j_rarg4);
3142 __ mov(c_rarg3, j_rarg3);
3143 #ifdef _WIN64
3144 // Allocate abi space for args but be sure to keep stack aligned
3145 __ subptr(rsp, 6*wordSize);
3146 store_parameter(j_rarg4, 4);
3147 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3148 __ call(RuntimeAddress(C_entry));
3149 } else {
3150 #ifndef PRODUCT
3151 if (PrintC1Statistics) {
3152 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3153 }
3154 #endif
3155 __ call(RuntimeAddress(copyfunc_addr));
3156 }
3157 __ addptr(rsp, 6*wordSize);
3158 #else
3159 __ mov(c_rarg4, j_rarg4);
3160 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3161 __ call(RuntimeAddress(C_entry));
3162 } else {
3163 #ifndef PRODUCT
3164 if (PrintC1Statistics) {
3165 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3166 }
3167 #endif
3168 __ call(RuntimeAddress(copyfunc_addr));
3169 }
3170 #endif // _WIN64
3171 #else
3172 __ push(length);
3173 __ push(dst_pos);
3174 __ push(dst);
3175 __ push(src_pos);
3176 __ push(src);
3177
3178 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3179 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack
3180 } else {
3181 #ifndef PRODUCT
3182 if (PrintC1Statistics) {
3183 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3184 }
3185 #endif
3186 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3187 }
3188
3189 #endif // _LP64
3190
3191 __ cmpl(rax, 0);
3192 __ jcc(Assembler::equal, *stub->continuation());
3193
3194 if (copyfunc_addr != NULL) {
3195 __ mov(tmp, rax);
3196 __ xorl(tmp, -1);
3197 }
3198
3199 // Reload values from the stack so they are where the stub
3200 // expects them.
3201 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3202 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3203 __ movptr (length, Address(rsp, 2*BytesPerWord));
3204 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3205 __ movptr (src, Address(rsp, 4*BytesPerWord));
3206
3207 if (copyfunc_addr != NULL) {
3208 __ subl(length, tmp);
3209 __ addl(src_pos, tmp);
3210 __ addl(dst_pos, tmp);
3211 }
3212 __ jmp(*stub->entry());
3213
3214 __ bind(*stub->continuation());
3215 return;
3216 }
3217
3218 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3219
3220 int elem_size = type2aelembytes(basic_type);
3221 int shift_amount;
3222 Address::ScaleFactor scale;
3223
3224 switch (elem_size) {
3225 case 1 :
3226 shift_amount = 0;
3227 scale = Address::times_1;
3228 break;
3229 case 2 :
3230 shift_amount = 1;
3231 scale = Address::times_2;
3232 break;
3233 case 4 :
3234 shift_amount = 2;
3235 scale = Address::times_4;
3236 break;
3237 case 8 :
3238 shift_amount = 3;
3239 scale = Address::times_8;
3240 break;
3241 default:
3242 ShouldNotReachHere();
3243 }
3244
3245 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3246 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3247 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3248 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3249
3250 // length and pos's are all sign extended at this point on 64bit
3251
3252 // test for NULL
3253 if (flags & LIR_OpArrayCopy::src_null_check) {
3254 __ testptr(src, src);
3255 __ jcc(Assembler::zero, *stub->entry());
3256 }
3257 if (flags & LIR_OpArrayCopy::dst_null_check) {
3258 __ testptr(dst, dst);
3259 __ jcc(Assembler::zero, *stub->entry());
3260 }
3261
3262 // check if negative
3263 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3264 __ testl(src_pos, src_pos);
3265 __ jcc(Assembler::less, *stub->entry());
3266 }
3267 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3268 __ testl(dst_pos, dst_pos);
3269 __ jcc(Assembler::less, *stub->entry());
3270 }
3271
3272 if (flags & LIR_OpArrayCopy::src_range_check) {
3273 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3274 __ cmpl(tmp, src_length_addr);
3275 __ jcc(Assembler::above, *stub->entry());
3276 }
3277 if (flags & LIR_OpArrayCopy::dst_range_check) {
3278 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3279 __ cmpl(tmp, dst_length_addr);
3280 __ jcc(Assembler::above, *stub->entry());
3281 }
3282
3283 if (flags & LIR_OpArrayCopy::length_positive_check) {
3284 __ testl(length, length);
3285 __ jcc(Assembler::less, *stub->entry());
3286 __ jcc(Assembler::zero, *stub->continuation());
3287 }
3288
3289 #ifdef _LP64
3290 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3291 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3292 #endif
3293
3294 if (flags & LIR_OpArrayCopy::type_check) {
3295 // We don't know the array types are compatible
3296 if (basic_type != T_OBJECT) {
3297 // Simple test for basic type arrays
3298 if (UseCompressedClassPointers) {
3299 __ movl(tmp, src_klass_addr);
3300 __ cmpl(tmp, dst_klass_addr);
3301 } else {
3302 __ movptr(tmp, src_klass_addr);
3303 __ cmpptr(tmp, dst_klass_addr);
3304 }
3305 __ jcc(Assembler::notEqual, *stub->entry());
3306 } else {
3307 // For object arrays, if src is a sub class of dst then we can
3308 // safely do the copy.
3309 Label cont, slow;
3310
3311 __ push(src);
3312 __ push(dst);
3313
3314 __ load_klass(src, src);
3315 __ load_klass(dst, dst);
3316
3317 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3318
3319 __ push(src);
3320 __ push(dst);
3321 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3322 __ pop(dst);
3323 __ pop(src);
3324
3325 __ cmpl(src, 0);
3326 __ jcc(Assembler::notEqual, cont);
3327
3328 __ bind(slow);
3329 __ pop(dst);
3330 __ pop(src);
3331
3332 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3333 if (copyfunc_addr != NULL) { // use stub if available
3334 // src is not a sub class of dst so we have to do a
3335 // per-element check.
3336
3337 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3338 if ((flags & mask) != mask) {
3339 // Check that at least both of them object arrays.
3340 assert(flags & mask, "one of the two should be known to be an object array");
3341
3342 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3343 __ load_klass(tmp, src);
3344 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3345 __ load_klass(tmp, dst);
3346 }
3347 int lh_offset = in_bytes(Klass::layout_helper_offset());
3348 Address klass_lh_addr(tmp, lh_offset);
3349 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3350 __ cmpl(klass_lh_addr, objArray_lh);
3351 __ jcc(Assembler::notEqual, *stub->entry());
3352 }
3353
3354 // Spill because stubs can use any register they like and it's
3355 // easier to restore just those that we care about.
3356 store_parameter(dst, 0);
3357 store_parameter(dst_pos, 1);
3358 store_parameter(length, 2);
3359 store_parameter(src_pos, 3);
3360 store_parameter(src, 4);
3361
3362 #ifndef _LP64
3363 __ movptr(tmp, dst_klass_addr);
3364 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3365 __ push(tmp);
3366 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3367 __ push(tmp);
3368 __ push(length);
3369 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3370 __ push(tmp);
3371 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3372 __ push(tmp);
3373
3374 __ call_VM_leaf(copyfunc_addr, 5);
3375 #else
3376 __ movl2ptr(length, length); //higher 32bits must be null
3377
3378 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3379 assert_different_registers(c_rarg0, dst, dst_pos, length);
3380 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3381 assert_different_registers(c_rarg1, dst, length);
3382
3383 __ mov(c_rarg2, length);
3384 assert_different_registers(c_rarg2, dst);
3385
3386 #ifdef _WIN64
3387 // Allocate abi space for args but be sure to keep stack aligned
3388 __ subptr(rsp, 6*wordSize);
3389 __ load_klass(c_rarg3, dst);
3390 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3391 store_parameter(c_rarg3, 4);
3392 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3393 __ call(RuntimeAddress(copyfunc_addr));
3394 __ addptr(rsp, 6*wordSize);
3395 #else
3396 __ load_klass(c_rarg4, dst);
3397 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3398 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3399 __ call(RuntimeAddress(copyfunc_addr));
3400 #endif
3401
3402 #endif
3403
3404 #ifndef PRODUCT
3405 if (PrintC1Statistics) {
3406 Label failed;
3407 __ testl(rax, rax);
3408 __ jcc(Assembler::notZero, failed);
3409 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3410 __ bind(failed);
3411 }
3412 #endif
3413
3414 __ testl(rax, rax);
3415 __ jcc(Assembler::zero, *stub->continuation());
3416
3417 #ifndef PRODUCT
3418 if (PrintC1Statistics) {
3419 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3420 }
3421 #endif
3422
3423 __ mov(tmp, rax);
3424
3425 __ xorl(tmp, -1);
3426
3427 // Restore previously spilled arguments
3428 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3429 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3430 __ movptr (length, Address(rsp, 2*BytesPerWord));
3431 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3432 __ movptr (src, Address(rsp, 4*BytesPerWord));
3433
3434
3435 __ subl(length, tmp);
3436 __ addl(src_pos, tmp);
3437 __ addl(dst_pos, tmp);
3438 }
3439
3440 __ jmp(*stub->entry());
3441
3442 __ bind(cont);
3443 __ pop(dst);
3444 __ pop(src);
3445 }
3446 }
3447
3448 #ifdef ASSERT
3449 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3450 // Sanity check the known type with the incoming class. For the
3451 // primitive case the types must match exactly with src.klass and
3452 // dst.klass each exactly matching the default type. For the
3453 // object array case, if no type check is needed then either the
3454 // dst type is exactly the expected type and the src type is a
3455 // subtype which we can't check or src is the same array as dst
3456 // but not necessarily exactly of type default_type.
3457 Label known_ok, halt;
3458 __ mov_metadata(tmp, default_type->constant_encoding());
3459 #ifdef _LP64
3460 if (UseCompressedClassPointers) {
3461 __ encode_klass_not_null(tmp);
3462 }
3463 #endif
3464
3465 if (basic_type != T_OBJECT) {
3466
3467 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3468 else __ cmpptr(tmp, dst_klass_addr);
3469 __ jcc(Assembler::notEqual, halt);
3470 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3471 else __ cmpptr(tmp, src_klass_addr);
3472 __ jcc(Assembler::equal, known_ok);
3473 } else {
3474 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3475 else __ cmpptr(tmp, dst_klass_addr);
3476 __ jcc(Assembler::equal, known_ok);
3477 __ cmpptr(src, dst);
3478 __ jcc(Assembler::equal, known_ok);
3479 }
3480 __ bind(halt);
3481 __ stop("incorrect type information in arraycopy");
3482 __ bind(known_ok);
3483 }
3484 #endif
3485
3486 #ifndef PRODUCT
3487 if (PrintC1Statistics) {
3488 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3489 }
3490 #endif
3491
3492 #ifdef _LP64
3493 assert_different_registers(c_rarg0, dst, dst_pos, length);
3494 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3495 assert_different_registers(c_rarg1, length);
3496 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3497 __ mov(c_rarg2, length);
3498
3499 #else
3500 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3501 store_parameter(tmp, 0);
3502 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3503 store_parameter(tmp, 1);
3504 store_parameter(length, 2);
3505 #endif // _LP64
3506
3507 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3508 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3509 const char *name;
3510 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3511 __ call_VM_leaf(entry, 0);
3512
3513 __ bind(*stub->continuation());
3514 }
3515
3516 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3517 assert(op->crc()->is_single_cpu(), "crc must be register");
3518 assert(op->val()->is_single_cpu(), "byte value must be register");
3519 assert(op->result_opr()->is_single_cpu(), "result must be register");
3520 Register crc = op->crc()->as_register();
3521 Register val = op->val()->as_register();
3522 Register res = op->result_opr()->as_register();
3523
3524 assert_different_registers(val, crc, res);
3525
3526 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3527 __ notl(crc); // ~crc
3528 __ update_byte_crc32(crc, val, res);
3529 __ notl(crc); // ~crc
3530 __ mov(res, crc);
3531 }
3532
3533 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3534 Register obj = op->obj_opr()->as_register(); // may not be an oop
3535 Register hdr = op->hdr_opr()->as_register();
3536 Register lock = op->lock_opr()->as_register();
3537 if (!UseFastLocking) {
3538 __ jmp(*op->stub()->entry());
3539 } else if (op->code() == lir_lock) {
3540 Register scratch = noreg;
3541 if (UseBiasedLocking) {
3542 scratch = op->scratch_opr()->as_register();
3543 }
3544 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3545 // add debug info for NullPointerException only if one is possible
3546 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3547 if (op->info() != NULL) {
3548 add_debug_info_for_null_check(null_check_offset, op->info());
3549 }
3550 // done
3551 } else if (op->code() == lir_unlock) {
3552 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3553 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3554 } else {
3555 Unimplemented();
3556 }
3557 __ bind(*op->stub()->continuation());
3558 }
3559
3560
3561 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3562 ciMethod* method = op->profiled_method();
3563 int bci = op->profiled_bci();
3564 ciMethod* callee = op->profiled_callee();
3565
3566 // Update counter for all call types
3567 ciMethodData* md = method->method_data_or_null();
3568 assert(md != NULL, "Sanity");
3569 ciProfileData* data = md->bci_to_data(bci);
3570 assert(data->is_CounterData(), "need CounterData for calls");
3571 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3572 Register mdo = op->mdo()->as_register();
3573 __ mov_metadata(mdo, md->constant_encoding());
3574 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3575 Bytecodes::Code bc = method->java_code_at_bci(bci);
3576 const bool callee_is_static = callee->is_loaded() && callee->is_static();
3577 // Perform additional virtual call profiling for invokevirtual and
3578 // invokeinterface bytecodes
3579 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3580 !callee_is_static && // required for optimized MH invokes
3581 C1ProfileVirtualCalls) {
3582 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3583 Register recv = op->recv()->as_register();
3584 assert_different_registers(mdo, recv);
3585 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3586 ciKlass* known_klass = op->known_holder();
3587 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3588 // We know the type that will be seen at this call site; we can
3589 // statically update the MethodData* rather than needing to do
3590 // dynamic tests on the receiver type
3591
3592 // NOTE: we should probably put a lock around this search to
3593 // avoid collisions by concurrent compilations
3594 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3595 uint i;
3596 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3597 ciKlass* receiver = vc_data->receiver(i);
3598 if (known_klass->equals(receiver)) {
3599 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3600 __ addptr(data_addr, DataLayout::counter_increment);
3601 return;
3602 }
3603 }
3604
3605 // Receiver type not found in profile data; select an empty slot
3606
3607 // Note that this is less efficient than it should be because it
3608 // always does a write to the receiver part of the
3609 // VirtualCallData rather than just the first time
3610 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3611 ciKlass* receiver = vc_data->receiver(i);
3612 if (receiver == NULL) {
3613 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3614 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3615 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3616 __ addptr(data_addr, DataLayout::counter_increment);
3617 return;
3618 }
3619 }
3620 } else {
3621 __ load_klass(recv, recv);
3622 Label update_done;
3623 type_profile_helper(mdo, md, data, recv, &update_done);
3624 // Receiver did not match any saved receiver and there is no empty row for it.
3625 // Increment total counter to indicate polymorphic case.
3626 __ addptr(counter_addr, DataLayout::counter_increment);
3627
3628 __ bind(update_done);
3629 }
3630 } else {
3631 // Static call
3632 __ addptr(counter_addr, DataLayout::counter_increment);
3633 }
3634 }
3635
3636 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3637 Register obj = op->obj()->as_register();
3638 Register tmp = op->tmp()->as_pointer_register();
3639 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3640 ciKlass* exact_klass = op->exact_klass();
3641 intptr_t current_klass = op->current_klass();
3642 bool not_null = op->not_null();
3643 bool no_conflict = op->no_conflict();
3644
3645 Label update, next, none;
3646
3647 bool do_null = !not_null;
3648 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3649 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3650
3651 assert(do_null || do_update, "why are we here?");
3652 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3653
3654 __ verify_oop(obj);
3655
3656 if (tmp != obj) {
3657 __ mov(tmp, obj);
3658 }
3659 if (do_null) {
3660 __ testptr(tmp, tmp);
3661 __ jccb(Assembler::notZero, update);
3662 if (!TypeEntries::was_null_seen(current_klass)) {
3663 __ orptr(mdo_addr, TypeEntries::null_seen);
3664 }
3665 if (do_update) {
3666 #ifndef ASSERT
3667 __ jmpb(next);
3668 }
3669 #else
3670 __ jmp(next);
3671 }
3672 } else {
3673 __ testptr(tmp, tmp);
3674 __ jccb(Assembler::notZero, update);
3675 __ stop("unexpect null obj");
3676 #endif
3677 }
3678
3679 __ bind(update);
3680
3681 if (do_update) {
3682 #ifdef ASSERT
3683 if (exact_klass != NULL) {
3684 Label ok;
3685 __ load_klass(tmp, tmp);
3686 __ push(tmp);
3687 __ mov_metadata(tmp, exact_klass->constant_encoding());
3688 __ cmpptr(tmp, Address(rsp, 0));
3689 __ jccb(Assembler::equal, ok);
3690 __ stop("exact klass and actual klass differ");
3691 __ bind(ok);
3692 __ pop(tmp);
3693 }
3694 #endif
3695 if (!no_conflict) {
3696 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3697 if (exact_klass != NULL) {
3698 __ mov_metadata(tmp, exact_klass->constant_encoding());
3699 } else {
3700 __ load_klass(tmp, tmp);
3701 }
3702
3703 __ xorptr(tmp, mdo_addr);
3704 __ testptr(tmp, TypeEntries::type_klass_mask);
3705 // klass seen before, nothing to do. The unknown bit may have been
3706 // set already but no need to check.
3707 __ jccb(Assembler::zero, next);
3708
3709 __ testptr(tmp, TypeEntries::type_unknown);
3710 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3711
3712 if (TypeEntries::is_type_none(current_klass)) {
3713 __ cmpptr(mdo_addr, 0);
3714 __ jccb(Assembler::equal, none);
3715 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3716 __ jccb(Assembler::equal, none);
3717 // There is a chance that the checks above (re-reading profiling
3718 // data from memory) fail if another thread has just set the
3719 // profiling to this obj's klass
3720 __ xorptr(tmp, mdo_addr);
3721 __ testptr(tmp, TypeEntries::type_klass_mask);
3722 __ jccb(Assembler::zero, next);
3723 }
3724 } else {
3725 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3726 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3727
3728 __ movptr(tmp, mdo_addr);
3729 __ testptr(tmp, TypeEntries::type_unknown);
3730 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3731 }
3732
3733 // different than before. Cannot keep accurate profile.
3734 __ orptr(mdo_addr, TypeEntries::type_unknown);
3735
3736 if (TypeEntries::is_type_none(current_klass)) {
3737 __ jmpb(next);
3738
3739 __ bind(none);
3740 // first time here. Set profile type.
3741 __ movptr(mdo_addr, tmp);
3742 }
3743 } else {
3744 // There's a single possible klass at this profile point
3745 assert(exact_klass != NULL, "should be");
3746 if (TypeEntries::is_type_none(current_klass)) {
3747 __ mov_metadata(tmp, exact_klass->constant_encoding());
3748 __ xorptr(tmp, mdo_addr);
3749 __ testptr(tmp, TypeEntries::type_klass_mask);
3750 #ifdef ASSERT
3751 __ jcc(Assembler::zero, next);
3752
3753 {
3754 Label ok;
3755 __ push(tmp);
3756 __ cmpptr(mdo_addr, 0);
3757 __ jcc(Assembler::equal, ok);
3758 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3759 __ jcc(Assembler::equal, ok);
3760 // may have been set by another thread
3761 __ mov_metadata(tmp, exact_klass->constant_encoding());
3762 __ xorptr(tmp, mdo_addr);
3763 __ testptr(tmp, TypeEntries::type_mask);
3764 __ jcc(Assembler::zero, ok);
3765
3766 __ stop("unexpected profiling mismatch");
3767 __ bind(ok);
3768 __ pop(tmp);
3769 }
3770 #else
3771 __ jccb(Assembler::zero, next);
3772 #endif
3773 // first time here. Set profile type.
3774 __ movptr(mdo_addr, tmp);
3775 } else {
3776 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3777 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3778
3779 __ movptr(tmp, mdo_addr);
3780 __ testptr(tmp, TypeEntries::type_unknown);
3781 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3782
3783 __ orptr(mdo_addr, TypeEntries::type_unknown);
3784 }
3785 }
3786
3787 __ bind(next);
3788 }
3789 }
3790
3791 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3792 Unimplemented();
3793 }
3794
3795
3796 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3797 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3798 }
3799
3800
3801 void LIR_Assembler::align_backward_branch_target() {
3802 __ align(BytesPerWord);
3803 }
3804
3805
3806 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3807 if (left->is_single_cpu()) {
3808 __ negl(left->as_register());
3809 move_regs(left->as_register(), dest->as_register());
3810
3811 } else if (left->is_double_cpu()) {
3812 Register lo = left->as_register_lo();
3813 #ifdef _LP64
3814 Register dst = dest->as_register_lo();
3815 __ movptr(dst, lo);
3816 __ negptr(dst);
3817 #else
3818 Register hi = left->as_register_hi();
3819 __ lneg(hi, lo);
3820 if (dest->as_register_lo() == hi) {
3821 assert(dest->as_register_hi() != lo, "destroying register");
3822 move_regs(hi, dest->as_register_hi());
3823 move_regs(lo, dest->as_register_lo());
3824 } else {
3825 move_regs(lo, dest->as_register_lo());
3826 move_regs(hi, dest->as_register_hi());
3827 }
3828 #endif // _LP64
3829
3830 } else if (dest->is_single_xmm()) {
3831 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3832 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3833 }
3834 __ xorps(dest->as_xmm_float_reg(),
3835 ExternalAddress((address)float_signflip_pool));
3836
3837 } else if (dest->is_double_xmm()) {
3838 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3839 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3840 }
3841 __ xorpd(dest->as_xmm_double_reg(),
3842 ExternalAddress((address)double_signflip_pool));
3843
3844 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3845 assert(left->fpu() == 0, "arg must be on TOS");
3846 assert(dest->fpu() == 0, "dest must be TOS");
3847 __ fchs();
3848
3849 } else {
3850 ShouldNotReachHere();
3851 }
3852 }
3853
3854
3855 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3856 assert(addr->is_address() && dest->is_register(), "check");
3857 Register reg;
3858 reg = dest->as_pointer_register();
3859 __ lea(reg, as_Address(addr->as_address_ptr()));
3860 }
3861
3862
3863
3864 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3865 assert(!tmp->is_valid(), "don't need temporary");
3866 __ call(RuntimeAddress(dest));
3867 if (info != NULL) {
3868 add_call_info_here(info);
3869 }
3870 }
3871
3872
3873 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3874 assert(type == T_LONG, "only for volatile long fields");
3875
3876 if (info != NULL) {
3877 add_debug_info_for_null_check_here(info);
3878 }
3879
3880 if (src->is_double_xmm()) {
3881 if (dest->is_double_cpu()) {
3882 #ifdef _LP64
3883 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3884 #else
3885 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3886 __ psrlq(src->as_xmm_double_reg(), 32);
3887 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3888 #endif // _LP64
3889 } else if (dest->is_double_stack()) {
3890 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3891 } else if (dest->is_address()) {
3892 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3893 } else {
3894 ShouldNotReachHere();
3895 }
3896
3897 } else if (dest->is_double_xmm()) {
3898 if (src->is_double_stack()) {
3899 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3900 } else if (src->is_address()) {
3901 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3902 } else {
3903 ShouldNotReachHere();
3904 }
3905
3906 } else if (src->is_double_fpu()) {
3907 assert(src->fpu_regnrLo() == 0, "must be TOS");
3908 if (dest->is_double_stack()) {
3909 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3910 } else if (dest->is_address()) {
3911 __ fistp_d(as_Address(dest->as_address_ptr()));
3912 } else {
3913 ShouldNotReachHere();
3914 }
3915
3916 } else if (dest->is_double_fpu()) {
3917 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3918 if (src->is_double_stack()) {
3919 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3920 } else if (src->is_address()) {
3921 __ fild_d(as_Address(src->as_address_ptr()));
3922 } else {
3923 ShouldNotReachHere();
3924 }
3925 } else {
3926 ShouldNotReachHere();
3927 }
3928 }
3929
3930 #ifdef ASSERT
3931 // emit run-time assertion
3932 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3933 assert(op->code() == lir_assert, "must be");
3934
3935 if (op->in_opr1()->is_valid()) {
3936 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3937 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3938 } else {
3939 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3940 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3941 }
3942
3943 Label ok;
3944 if (op->condition() != lir_cond_always) {
3945 Assembler::Condition acond = Assembler::zero;
3946 switch (op->condition()) {
3947 case lir_cond_equal: acond = Assembler::equal; break;
3948 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3949 case lir_cond_less: acond = Assembler::less; break;
3950 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3951 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3952 case lir_cond_greater: acond = Assembler::greater; break;
3953 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3954 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3955 default: ShouldNotReachHere();
3956 }
3957 __ jcc(acond, ok);
3958 }
3959 if (op->halt()) {
3960 const char* str = __ code_string(op->msg());
3961 __ stop(str);
3962 } else {
3963 breakpoint();
3964 }
3965 __ bind(ok);
3966 }
3967 #endif
3968
3969 void LIR_Assembler::membar() {
3970 // QQQ sparc TSO uses this,
3971 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3972 }
3973
3974 void LIR_Assembler::membar_acquire() {
3975 // No x86 machines currently require load fences
3976 }
3977
3978 void LIR_Assembler::membar_release() {
3979 // No x86 machines currently require store fences
3980 }
3981
3982 void LIR_Assembler::membar_loadload() {
3983 // no-op
3984 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3985 }
3986
3987 void LIR_Assembler::membar_storestore() {
3988 // no-op
3989 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3990 }
3991
3992 void LIR_Assembler::membar_loadstore() {
3993 // no-op
3994 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3995 }
3996
3997 void LIR_Assembler::membar_storeload() {
3998 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3999 }
4000
4001 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4002 assert(result_reg->is_register(), "check");
4003 #ifdef _LP64
4004 // __ get_thread(result_reg->as_register_lo());
4005 __ mov(result_reg->as_register(), r15_thread);
4006 #else
4007 __ get_thread(result_reg->as_register());
4008 #endif // _LP64
4009 }
4010
4011
4012 void LIR_Assembler::peephole(LIR_List*) {
4013 // do nothing for now
4014 }
4015
4016 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4017 assert(data == dest, "xchg/xadd uses only 2 operands");
4018
4019 if (data->type() == T_INT) {
4020 if (code == lir_xadd) {
4021 if (os::is_MP()) {
4022 __ lock();
4023 }
4024 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4025 } else {
4026 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4027 }
4028 } else if (data->is_oop()) {
4029 assert (code == lir_xchg, "xadd for oops");
4030 Register obj = data->as_register();
4031 #ifdef _LP64
4032 if (UseCompressedOops) {
4033 __ encode_heap_oop(obj);
4034 __ xchgl(obj, as_Address(src->as_address_ptr()));
4035 __ decode_heap_oop(obj);
4036 } else {
4037 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4038 }
4039 #else
4040 __ xchgl(obj, as_Address(src->as_address_ptr()));
4041 #endif
4042 } else if (data->type() == T_LONG) {
4043 #ifdef _LP64
4044 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4045 if (code == lir_xadd) {
4046 if (os::is_MP()) {
4047 __ lock();
4048 }
4049 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4050 } else {
4051 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4052 }
4053 #else
4054 ShouldNotReachHere();
4055 #endif
4056 } else {
4057 ShouldNotReachHere();
4058 }
4059 }
4060
4061 #undef __