1 /* 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "compiler/disassembler.hpp" 29 #include "gc/shared/cardTableModRefBS.hpp" 30 #include "gc/shared/collectedHeap.inline.hpp" 31 #include "interpreter/interpreter.hpp" 32 #include "memory/resourceArea.hpp" 33 #include "memory/universe.hpp" 34 #include "oops/klass.inline.hpp" 35 #include "prims/methodHandles.hpp" 36 #include "runtime/biasedLocking.hpp" 37 #include "runtime/interfaceSupport.hpp" 38 #include "runtime/objectMonitor.hpp" 39 #include "runtime/os.hpp" 40 #include "runtime/sharedRuntime.hpp" 41 #include "runtime/stubRoutines.hpp" 42 #include "utilities/macros.hpp" 43 #if INCLUDE_ALL_GCS 44 #include "gc/g1/g1CollectedHeap.inline.hpp" 45 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 46 #include "gc/g1/heapRegion.hpp" 47 #endif // INCLUDE_ALL_GCS 48 49 #ifdef PRODUCT 50 #define BLOCK_COMMENT(str) /* nothing */ 51 #define STOP(error) stop(error) 52 #else 53 #define BLOCK_COMMENT(str) block_comment(str) 54 #define STOP(error) block_comment(error); stop(error) 55 #endif 56 57 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 58 59 PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC 60 61 #ifdef ASSERT 62 bool AbstractAssembler::pd_check_instruction_mark() { return true; } 63 #endif 64 65 static Assembler::Condition reverse[] = { 66 Assembler::noOverflow /* overflow = 0x0 */ , 67 Assembler::overflow /* noOverflow = 0x1 */ , 68 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , 69 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , 70 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , 71 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , 72 Assembler::above /* belowEqual = 0x6 */ , 73 Assembler::belowEqual /* above = 0x7 */ , 74 Assembler::positive /* negative = 0x8 */ , 75 Assembler::negative /* positive = 0x9 */ , 76 Assembler::noParity /* parity = 0xa */ , 77 Assembler::parity /* noParity = 0xb */ , 78 Assembler::greaterEqual /* less = 0xc */ , 79 Assembler::less /* greaterEqual = 0xd */ , 80 Assembler::greater /* lessEqual = 0xe */ , 81 Assembler::lessEqual /* greater = 0xf, */ 82 83 }; 84 85 86 // Implementation of MacroAssembler 87 88 // First all the versions that have distinct versions depending on 32/64 bit 89 // Unless the difference is trivial (1 line or so). 90 91 #ifndef _LP64 92 93 // 32bit versions 94 95 Address MacroAssembler::as_Address(AddressLiteral adr) { 96 return Address(adr.target(), adr.rspec()); 97 } 98 99 Address MacroAssembler::as_Address(ArrayAddress adr) { 100 return Address::make_array(adr); 101 } 102 103 void MacroAssembler::call_VM_leaf_base(address entry_point, 104 int number_of_arguments) { 105 call(RuntimeAddress(entry_point)); 106 increment(rsp, number_of_arguments * wordSize); 107 } 108 109 void MacroAssembler::cmpklass(Address src1, Metadata* obj) { 110 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 111 } 112 113 void MacroAssembler::cmpklass(Register src1, Metadata* obj) { 114 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 115 } 116 117 void MacroAssembler::cmpoop(Address src1, jobject obj) { 118 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 119 } 120 121 void MacroAssembler::cmpoop(Register src1, jobject obj) { 122 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 123 } 124 125 void MacroAssembler::extend_sign(Register hi, Register lo) { 126 // According to Intel Doc. AP-526, "Integer Divide", p.18. 127 if (VM_Version::is_P6() && hi == rdx && lo == rax) { 128 cdql(); 129 } else { 130 movl(hi, lo); 131 sarl(hi, 31); 132 } 133 } 134 135 void MacroAssembler::jC2(Register tmp, Label& L) { 136 // set parity bit if FPU flag C2 is set (via rax) 137 save_rax(tmp); 138 fwait(); fnstsw_ax(); 139 sahf(); 140 restore_rax(tmp); 141 // branch 142 jcc(Assembler::parity, L); 143 } 144 145 void MacroAssembler::jnC2(Register tmp, Label& L) { 146 // set parity bit if FPU flag C2 is set (via rax) 147 save_rax(tmp); 148 fwait(); fnstsw_ax(); 149 sahf(); 150 restore_rax(tmp); 151 // branch 152 jcc(Assembler::noParity, L); 153 } 154 155 // 32bit can do a case table jump in one instruction but we no longer allow the base 156 // to be installed in the Address class 157 void MacroAssembler::jump(ArrayAddress entry) { 158 jmp(as_Address(entry)); 159 } 160 161 // Note: y_lo will be destroyed 162 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 163 // Long compare for Java (semantics as described in JVM spec.) 164 Label high, low, done; 165 166 cmpl(x_hi, y_hi); 167 jcc(Assembler::less, low); 168 jcc(Assembler::greater, high); 169 // x_hi is the return register 170 xorl(x_hi, x_hi); 171 cmpl(x_lo, y_lo); 172 jcc(Assembler::below, low); 173 jcc(Assembler::equal, done); 174 175 bind(high); 176 xorl(x_hi, x_hi); 177 increment(x_hi); 178 jmp(done); 179 180 bind(low); 181 xorl(x_hi, x_hi); 182 decrementl(x_hi); 183 184 bind(done); 185 } 186 187 void MacroAssembler::lea(Register dst, AddressLiteral src) { 188 mov_literal32(dst, (int32_t)src.target(), src.rspec()); 189 } 190 191 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 192 // leal(dst, as_Address(adr)); 193 // see note in movl as to why we must use a move 194 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); 195 } 196 197 void MacroAssembler::leave() { 198 mov(rsp, rbp); 199 pop(rbp); 200 } 201 202 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { 203 // Multiplication of two Java long values stored on the stack 204 // as illustrated below. Result is in rdx:rax. 205 // 206 // rsp ---> [ ?? ] \ \ 207 // .... | y_rsp_offset | 208 // [ y_lo ] / (in bytes) | x_rsp_offset 209 // [ y_hi ] | (in bytes) 210 // .... | 211 // [ x_lo ] / 212 // [ x_hi ] 213 // .... 214 // 215 // Basic idea: lo(result) = lo(x_lo * y_lo) 216 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 217 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); 218 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); 219 Label quick; 220 // load x_hi, y_hi and check if quick 221 // multiplication is possible 222 movl(rbx, x_hi); 223 movl(rcx, y_hi); 224 movl(rax, rbx); 225 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 226 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply 227 // do full multiplication 228 // 1st step 229 mull(y_lo); // x_hi * y_lo 230 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, 231 // 2nd step 232 movl(rax, x_lo); 233 mull(rcx); // x_lo * y_hi 234 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, 235 // 3rd step 236 bind(quick); // note: rbx, = 0 if quick multiply! 237 movl(rax, x_lo); 238 mull(y_lo); // x_lo * y_lo 239 addl(rdx, rbx); // correct hi(x_lo * y_lo) 240 } 241 242 void MacroAssembler::lneg(Register hi, Register lo) { 243 negl(lo); 244 adcl(hi, 0); 245 negl(hi); 246 } 247 248 void MacroAssembler::lshl(Register hi, Register lo) { 249 // Java shift left long support (semantics as described in JVM spec., p.305) 250 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) 251 // shift value is in rcx ! 252 assert(hi != rcx, "must not use rcx"); 253 assert(lo != rcx, "must not use rcx"); 254 const Register s = rcx; // shift count 255 const int n = BitsPerWord; 256 Label L; 257 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 258 cmpl(s, n); // if (s < n) 259 jcc(Assembler::less, L); // else (s >= n) 260 movl(hi, lo); // x := x << n 261 xorl(lo, lo); 262 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 263 bind(L); // s (mod n) < n 264 shldl(hi, lo); // x := x << s 265 shll(lo); 266 } 267 268 269 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { 270 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) 271 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) 272 assert(hi != rcx, "must not use rcx"); 273 assert(lo != rcx, "must not use rcx"); 274 const Register s = rcx; // shift count 275 const int n = BitsPerWord; 276 Label L; 277 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 278 cmpl(s, n); // if (s < n) 279 jcc(Assembler::less, L); // else (s >= n) 280 movl(lo, hi); // x := x >> n 281 if (sign_extension) sarl(hi, 31); 282 else xorl(hi, hi); 283 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 284 bind(L); // s (mod n) < n 285 shrdl(lo, hi); // x := x >> s 286 if (sign_extension) sarl(hi); 287 else shrl(hi); 288 } 289 290 void MacroAssembler::movoop(Register dst, jobject obj) { 291 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 292 } 293 294 void MacroAssembler::movoop(Address dst, jobject obj) { 295 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 296 } 297 298 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 299 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 300 } 301 302 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 303 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 304 } 305 306 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 307 // scratch register is not used, 308 // it is defined to match parameters of 64-bit version of this method. 309 if (src.is_lval()) { 310 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); 311 } else { 312 movl(dst, as_Address(src)); 313 } 314 } 315 316 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 317 movl(as_Address(dst), src); 318 } 319 320 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 321 movl(dst, as_Address(src)); 322 } 323 324 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 325 void MacroAssembler::movptr(Address dst, intptr_t src) { 326 movl(dst, src); 327 } 328 329 330 void MacroAssembler::pop_callee_saved_registers() { 331 pop(rcx); 332 pop(rdx); 333 pop(rdi); 334 pop(rsi); 335 } 336 337 void MacroAssembler::pop_fTOS() { 338 fld_d(Address(rsp, 0)); 339 addl(rsp, 2 * wordSize); 340 } 341 342 void MacroAssembler::push_callee_saved_registers() { 343 push(rsi); 344 push(rdi); 345 push(rdx); 346 push(rcx); 347 } 348 349 void MacroAssembler::push_fTOS() { 350 subl(rsp, 2 * wordSize); 351 fstp_d(Address(rsp, 0)); 352 } 353 354 355 void MacroAssembler::pushoop(jobject obj) { 356 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); 357 } 358 359 void MacroAssembler::pushklass(Metadata* obj) { 360 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); 361 } 362 363 void MacroAssembler::pushptr(AddressLiteral src) { 364 if (src.is_lval()) { 365 push_literal32((int32_t)src.target(), src.rspec()); 366 } else { 367 pushl(as_Address(src)); 368 } 369 } 370 371 void MacroAssembler::set_word_if_not_zero(Register dst) { 372 xorl(dst, dst); 373 set_byte_if_not_zero(dst); 374 } 375 376 static void pass_arg0(MacroAssembler* masm, Register arg) { 377 masm->push(arg); 378 } 379 380 static void pass_arg1(MacroAssembler* masm, Register arg) { 381 masm->push(arg); 382 } 383 384 static void pass_arg2(MacroAssembler* masm, Register arg) { 385 masm->push(arg); 386 } 387 388 static void pass_arg3(MacroAssembler* masm, Register arg) { 389 masm->push(arg); 390 } 391 392 #ifndef PRODUCT 393 extern "C" void findpc(intptr_t x); 394 #endif 395 396 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { 397 // In order to get locks to work, we need to fake a in_VM state 398 JavaThread* thread = JavaThread::current(); 399 JavaThreadState saved_state = thread->thread_state(); 400 thread->set_thread_state(_thread_in_vm); 401 if (ShowMessageBoxOnError) { 402 JavaThread* thread = JavaThread::current(); 403 JavaThreadState saved_state = thread->thread_state(); 404 thread->set_thread_state(_thread_in_vm); 405 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 406 ttyLocker ttyl; 407 BytecodeCounter::print(); 408 } 409 // To see where a verify_oop failed, get $ebx+40/X for this frame. 410 // This is the value of eip which points to where verify_oop will return. 411 if (os::message_box(msg, "Execution stopped, print registers?")) { 412 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); 413 BREAKPOINT; 414 } 415 } else { 416 ttyLocker ttyl; 417 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); 418 } 419 // Don't assert holding the ttyLock 420 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); 421 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 422 } 423 424 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { 425 ttyLocker ttyl; 426 FlagSetting fs(Debugging, true); 427 tty->print_cr("eip = 0x%08x", eip); 428 #ifndef PRODUCT 429 if ((WizardMode || Verbose) && PrintMiscellaneous) { 430 tty->cr(); 431 findpc(eip); 432 tty->cr(); 433 } 434 #endif 435 #define PRINT_REG(rax) \ 436 { tty->print("%s = ", #rax); os::print_location(tty, rax); } 437 PRINT_REG(rax); 438 PRINT_REG(rbx); 439 PRINT_REG(rcx); 440 PRINT_REG(rdx); 441 PRINT_REG(rdi); 442 PRINT_REG(rsi); 443 PRINT_REG(rbp); 444 PRINT_REG(rsp); 445 #undef PRINT_REG 446 // Print some words near top of staack. 447 int* dump_sp = (int*) rsp; 448 for (int col1 = 0; col1 < 8; col1++) { 449 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 450 os::print_location(tty, *dump_sp++); 451 } 452 for (int row = 0; row < 16; row++) { 453 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 454 for (int col = 0; col < 8; col++) { 455 tty->print(" 0x%08x", *dump_sp++); 456 } 457 tty->cr(); 458 } 459 // Print some instructions around pc: 460 Disassembler::decode((address)eip-64, (address)eip); 461 tty->print_cr("--------"); 462 Disassembler::decode((address)eip, (address)eip+32); 463 } 464 465 void MacroAssembler::stop(const char* msg) { 466 ExternalAddress message((address)msg); 467 // push address of message 468 pushptr(message.addr()); 469 { Label L; call(L, relocInfo::none); bind(L); } // push eip 470 pusha(); // push registers 471 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); 472 hlt(); 473 } 474 475 void MacroAssembler::warn(const char* msg) { 476 push_CPU_state(); 477 478 ExternalAddress message((address) msg); 479 // push address of message 480 pushptr(message.addr()); 481 482 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); 483 addl(rsp, wordSize); // discard argument 484 pop_CPU_state(); 485 } 486 487 void MacroAssembler::print_state() { 488 { Label L; call(L, relocInfo::none); bind(L); } // push eip 489 pusha(); // push registers 490 491 push_CPU_state(); 492 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); 493 pop_CPU_state(); 494 495 popa(); 496 addl(rsp, wordSize); 497 } 498 499 #else // _LP64 500 501 // 64 bit versions 502 503 Address MacroAssembler::as_Address(AddressLiteral adr) { 504 // amd64 always does this as a pc-rel 505 // we can be absolute or disp based on the instruction type 506 // jmp/call are displacements others are absolute 507 assert(!adr.is_lval(), "must be rval"); 508 assert(reachable(adr), "must be"); 509 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); 510 511 } 512 513 Address MacroAssembler::as_Address(ArrayAddress adr) { 514 AddressLiteral base = adr.base(); 515 lea(rscratch1, base); 516 Address index = adr.index(); 517 assert(index._disp == 0, "must not have disp"); // maybe it can? 518 Address array(rscratch1, index._index, index._scale, index._disp); 519 return array; 520 } 521 522 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { 523 Label L, E; 524 525 #ifdef _WIN64 526 // Windows always allocates space for it's register args 527 assert(num_args <= 4, "only register arguments supported"); 528 subq(rsp, frame::arg_reg_save_area_bytes); 529 #endif 530 531 // Align stack if necessary 532 testl(rsp, 15); 533 jcc(Assembler::zero, L); 534 535 subq(rsp, 8); 536 { 537 call(RuntimeAddress(entry_point)); 538 } 539 addq(rsp, 8); 540 jmp(E); 541 542 bind(L); 543 { 544 call(RuntimeAddress(entry_point)); 545 } 546 547 bind(E); 548 549 #ifdef _WIN64 550 // restore stack pointer 551 addq(rsp, frame::arg_reg_save_area_bytes); 552 #endif 553 554 } 555 556 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { 557 assert(!src2.is_lval(), "should use cmpptr"); 558 559 if (reachable(src2)) { 560 cmpq(src1, as_Address(src2)); 561 } else { 562 lea(rscratch1, src2); 563 Assembler::cmpq(src1, Address(rscratch1, 0)); 564 } 565 } 566 567 int MacroAssembler::corrected_idivq(Register reg) { 568 // Full implementation of Java ldiv and lrem; checks for special 569 // case as described in JVM spec., p.243 & p.271. The function 570 // returns the (pc) offset of the idivl instruction - may be needed 571 // for implicit exceptions. 572 // 573 // normal case special case 574 // 575 // input : rax: dividend min_long 576 // reg: divisor (may not be eax/edx) -1 577 // 578 // output: rax: quotient (= rax idiv reg) min_long 579 // rdx: remainder (= rax irem reg) 0 580 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); 581 static const int64_t min_long = 0x8000000000000000; 582 Label normal_case, special_case; 583 584 // check for special case 585 cmp64(rax, ExternalAddress((address) &min_long)); 586 jcc(Assembler::notEqual, normal_case); 587 xorl(rdx, rdx); // prepare rdx for possible special case (where 588 // remainder = 0) 589 cmpq(reg, -1); 590 jcc(Assembler::equal, special_case); 591 592 // handle normal case 593 bind(normal_case); 594 cdqq(); 595 int idivq_offset = offset(); 596 idivq(reg); 597 598 // normal and special case exit 599 bind(special_case); 600 601 return idivq_offset; 602 } 603 604 void MacroAssembler::decrementq(Register reg, int value) { 605 if (value == min_jint) { subq(reg, value); return; } 606 if (value < 0) { incrementq(reg, -value); return; } 607 if (value == 0) { ; return; } 608 if (value == 1 && UseIncDec) { decq(reg) ; return; } 609 /* else */ { subq(reg, value) ; return; } 610 } 611 612 void MacroAssembler::decrementq(Address dst, int value) { 613 if (value == min_jint) { subq(dst, value); return; } 614 if (value < 0) { incrementq(dst, -value); return; } 615 if (value == 0) { ; return; } 616 if (value == 1 && UseIncDec) { decq(dst) ; return; } 617 /* else */ { subq(dst, value) ; return; } 618 } 619 620 void MacroAssembler::incrementq(AddressLiteral dst) { 621 if (reachable(dst)) { 622 incrementq(as_Address(dst)); 623 } else { 624 lea(rscratch1, dst); 625 incrementq(Address(rscratch1, 0)); 626 } 627 } 628 629 void MacroAssembler::incrementq(Register reg, int value) { 630 if (value == min_jint) { addq(reg, value); return; } 631 if (value < 0) { decrementq(reg, -value); return; } 632 if (value == 0) { ; return; } 633 if (value == 1 && UseIncDec) { incq(reg) ; return; } 634 /* else */ { addq(reg, value) ; return; } 635 } 636 637 void MacroAssembler::incrementq(Address dst, int value) { 638 if (value == min_jint) { addq(dst, value); return; } 639 if (value < 0) { decrementq(dst, -value); return; } 640 if (value == 0) { ; return; } 641 if (value == 1 && UseIncDec) { incq(dst) ; return; } 642 /* else */ { addq(dst, value) ; return; } 643 } 644 645 // 32bit can do a case table jump in one instruction but we no longer allow the base 646 // to be installed in the Address class 647 void MacroAssembler::jump(ArrayAddress entry) { 648 lea(rscratch1, entry.base()); 649 Address dispatch = entry.index(); 650 assert(dispatch._base == noreg, "must be"); 651 dispatch._base = rscratch1; 652 jmp(dispatch); 653 } 654 655 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 656 ShouldNotReachHere(); // 64bit doesn't use two regs 657 cmpq(x_lo, y_lo); 658 } 659 660 void MacroAssembler::lea(Register dst, AddressLiteral src) { 661 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 662 } 663 664 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 665 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); 666 movptr(dst, rscratch1); 667 } 668 669 void MacroAssembler::leave() { 670 // %%% is this really better? Why not on 32bit too? 671 emit_int8((unsigned char)0xC9); // LEAVE 672 } 673 674 void MacroAssembler::lneg(Register hi, Register lo) { 675 ShouldNotReachHere(); // 64bit doesn't use two regs 676 negq(lo); 677 } 678 679 void MacroAssembler::movoop(Register dst, jobject obj) { 680 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 681 } 682 683 void MacroAssembler::movoop(Address dst, jobject obj) { 684 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 685 movq(dst, rscratch1); 686 } 687 688 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 689 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 690 } 691 692 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 693 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 694 movq(dst, rscratch1); 695 } 696 697 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 698 if (src.is_lval()) { 699 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 700 } else { 701 if (reachable(src)) { 702 movq(dst, as_Address(src)); 703 } else { 704 lea(scratch, src); 705 movq(dst, Address(scratch, 0)); 706 } 707 } 708 } 709 710 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 711 movq(as_Address(dst), src); 712 } 713 714 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 715 movq(dst, as_Address(src)); 716 } 717 718 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 719 void MacroAssembler::movptr(Address dst, intptr_t src) { 720 mov64(rscratch1, src); 721 movq(dst, rscratch1); 722 } 723 724 // These are mostly for initializing NULL 725 void MacroAssembler::movptr(Address dst, int32_t src) { 726 movslq(dst, src); 727 } 728 729 void MacroAssembler::movptr(Register dst, int32_t src) { 730 mov64(dst, (intptr_t)src); 731 } 732 733 void MacroAssembler::pushoop(jobject obj) { 734 movoop(rscratch1, obj); 735 push(rscratch1); 736 } 737 738 void MacroAssembler::pushklass(Metadata* obj) { 739 mov_metadata(rscratch1, obj); 740 push(rscratch1); 741 } 742 743 void MacroAssembler::pushptr(AddressLiteral src) { 744 lea(rscratch1, src); 745 if (src.is_lval()) { 746 push(rscratch1); 747 } else { 748 pushq(Address(rscratch1, 0)); 749 } 750 } 751 752 void MacroAssembler::reset_last_Java_frame(bool clear_fp, 753 bool clear_pc) { 754 // we must set sp to zero to clear frame 755 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 756 // must clear fp, so that compiled frames are not confused; it is 757 // possible that we need it only for debugging 758 if (clear_fp) { 759 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 760 } 761 762 if (clear_pc) { 763 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 764 } 765 } 766 767 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 768 Register last_java_fp, 769 address last_java_pc) { 770 // determine last_java_sp register 771 if (!last_java_sp->is_valid()) { 772 last_java_sp = rsp; 773 } 774 775 // last_java_fp is optional 776 if (last_java_fp->is_valid()) { 777 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), 778 last_java_fp); 779 } 780 781 // last_java_pc is optional 782 if (last_java_pc != NULL) { 783 Address java_pc(r15_thread, 784 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); 785 lea(rscratch1, InternalAddress(last_java_pc)); 786 movptr(java_pc, rscratch1); 787 } 788 789 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 790 } 791 792 static void pass_arg0(MacroAssembler* masm, Register arg) { 793 if (c_rarg0 != arg ) { 794 masm->mov(c_rarg0, arg); 795 } 796 } 797 798 static void pass_arg1(MacroAssembler* masm, Register arg) { 799 if (c_rarg1 != arg ) { 800 masm->mov(c_rarg1, arg); 801 } 802 } 803 804 static void pass_arg2(MacroAssembler* masm, Register arg) { 805 if (c_rarg2 != arg ) { 806 masm->mov(c_rarg2, arg); 807 } 808 } 809 810 static void pass_arg3(MacroAssembler* masm, Register arg) { 811 if (c_rarg3 != arg ) { 812 masm->mov(c_rarg3, arg); 813 } 814 } 815 816 void MacroAssembler::stop(const char* msg) { 817 address rip = pc(); 818 pusha(); // get regs on stack 819 lea(c_rarg0, ExternalAddress((address) msg)); 820 lea(c_rarg1, InternalAddress(rip)); 821 movq(c_rarg2, rsp); // pass pointer to regs array 822 andq(rsp, -16); // align stack as required by ABI 823 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); 824 hlt(); 825 } 826 827 void MacroAssembler::warn(const char* msg) { 828 push(rbp); 829 movq(rbp, rsp); 830 andq(rsp, -16); // align stack as required by push_CPU_state and call 831 push_CPU_state(); // keeps alignment at 16 bytes 832 lea(c_rarg0, ExternalAddress((address) msg)); 833 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); 834 pop_CPU_state(); 835 mov(rsp, rbp); 836 pop(rbp); 837 } 838 839 void MacroAssembler::print_state() { 840 address rip = pc(); 841 pusha(); // get regs on stack 842 push(rbp); 843 movq(rbp, rsp); 844 andq(rsp, -16); // align stack as required by push_CPU_state and call 845 push_CPU_state(); // keeps alignment at 16 bytes 846 847 lea(c_rarg0, InternalAddress(rip)); 848 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array 849 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); 850 851 pop_CPU_state(); 852 mov(rsp, rbp); 853 pop(rbp); 854 popa(); 855 } 856 857 #ifndef PRODUCT 858 extern "C" void findpc(intptr_t x); 859 #endif 860 861 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { 862 // In order to get locks to work, we need to fake a in_VM state 863 if (ShowMessageBoxOnError) { 864 JavaThread* thread = JavaThread::current(); 865 JavaThreadState saved_state = thread->thread_state(); 866 thread->set_thread_state(_thread_in_vm); 867 #ifndef PRODUCT 868 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 869 ttyLocker ttyl; 870 BytecodeCounter::print(); 871 } 872 #endif 873 // To see where a verify_oop failed, get $ebx+40/X for this frame. 874 // XXX correct this offset for amd64 875 // This is the value of eip which points to where verify_oop will return. 876 if (os::message_box(msg, "Execution stopped, print registers?")) { 877 print_state64(pc, regs); 878 BREAKPOINT; 879 assert(false, "start up GDB"); 880 } 881 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 882 } else { 883 ttyLocker ttyl; 884 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 885 msg); 886 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); 887 } 888 } 889 890 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { 891 ttyLocker ttyl; 892 FlagSetting fs(Debugging, true); 893 tty->print_cr("rip = 0x%016lx", pc); 894 #ifndef PRODUCT 895 tty->cr(); 896 findpc(pc); 897 tty->cr(); 898 #endif 899 #define PRINT_REG(rax, value) \ 900 { tty->print("%s = ", #rax); os::print_location(tty, value); } 901 PRINT_REG(rax, regs[15]); 902 PRINT_REG(rbx, regs[12]); 903 PRINT_REG(rcx, regs[14]); 904 PRINT_REG(rdx, regs[13]); 905 PRINT_REG(rdi, regs[8]); 906 PRINT_REG(rsi, regs[9]); 907 PRINT_REG(rbp, regs[10]); 908 PRINT_REG(rsp, regs[11]); 909 PRINT_REG(r8 , regs[7]); 910 PRINT_REG(r9 , regs[6]); 911 PRINT_REG(r10, regs[5]); 912 PRINT_REG(r11, regs[4]); 913 PRINT_REG(r12, regs[3]); 914 PRINT_REG(r13, regs[2]); 915 PRINT_REG(r14, regs[1]); 916 PRINT_REG(r15, regs[0]); 917 #undef PRINT_REG 918 // Print some words near top of staack. 919 int64_t* rsp = (int64_t*) regs[11]; 920 int64_t* dump_sp = rsp; 921 for (int col1 = 0; col1 < 8; col1++) { 922 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 923 os::print_location(tty, *dump_sp++); 924 } 925 for (int row = 0; row < 25; row++) { 926 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 927 for (int col = 0; col < 4; col++) { 928 tty->print(" 0x%016lx", *dump_sp++); 929 } 930 tty->cr(); 931 } 932 // Print some instructions around pc: 933 Disassembler::decode((address)pc-64, (address)pc); 934 tty->print_cr("--------"); 935 Disassembler::decode((address)pc, (address)pc+32); 936 } 937 938 #endif // _LP64 939 940 // Now versions that are common to 32/64 bit 941 942 void MacroAssembler::addptr(Register dst, int32_t imm32) { 943 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); 944 } 945 946 void MacroAssembler::addptr(Register dst, Register src) { 947 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 948 } 949 950 void MacroAssembler::addptr(Address dst, Register src) { 951 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 952 } 953 954 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { 955 if (reachable(src)) { 956 Assembler::addsd(dst, as_Address(src)); 957 } else { 958 lea(rscratch1, src); 959 Assembler::addsd(dst, Address(rscratch1, 0)); 960 } 961 } 962 963 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { 964 if (reachable(src)) { 965 addss(dst, as_Address(src)); 966 } else { 967 lea(rscratch1, src); 968 addss(dst, Address(rscratch1, 0)); 969 } 970 } 971 972 void MacroAssembler::align(int modulus) { 973 if (offset() % modulus != 0) { 974 nop(modulus - (offset() % modulus)); 975 } 976 } 977 978 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { 979 // Used in sign-masking with aligned address. 980 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 981 if (reachable(src)) { 982 Assembler::andpd(dst, as_Address(src)); 983 } else { 984 lea(rscratch1, src); 985 Assembler::andpd(dst, Address(rscratch1, 0)); 986 } 987 } 988 989 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { 990 // Used in sign-masking with aligned address. 991 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 992 if (reachable(src)) { 993 Assembler::andps(dst, as_Address(src)); 994 } else { 995 lea(rscratch1, src); 996 Assembler::andps(dst, Address(rscratch1, 0)); 997 } 998 } 999 1000 void MacroAssembler::andptr(Register dst, int32_t imm32) { 1001 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); 1002 } 1003 1004 void MacroAssembler::atomic_incl(Address counter_addr) { 1005 if (os::is_MP()) 1006 lock(); 1007 incrementl(counter_addr); 1008 } 1009 1010 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) { 1011 if (reachable(counter_addr)) { 1012 atomic_incl(as_Address(counter_addr)); 1013 } else { 1014 lea(scr, counter_addr); 1015 atomic_incl(Address(scr, 0)); 1016 } 1017 } 1018 1019 #ifdef _LP64 1020 void MacroAssembler::atomic_incq(Address counter_addr) { 1021 if (os::is_MP()) 1022 lock(); 1023 incrementq(counter_addr); 1024 } 1025 1026 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) { 1027 if (reachable(counter_addr)) { 1028 atomic_incq(as_Address(counter_addr)); 1029 } else { 1030 lea(scr, counter_addr); 1031 atomic_incq(Address(scr, 0)); 1032 } 1033 } 1034 #endif 1035 1036 // Writes to stack successive pages until offset reached to check for 1037 // stack overflow + shadow pages. This clobbers tmp. 1038 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 1039 movptr(tmp, rsp); 1040 // Bang stack for total size given plus shadow page size. 1041 // Bang one page at a time because large size can bang beyond yellow and 1042 // red zones. 1043 Label loop; 1044 bind(loop); 1045 movl(Address(tmp, (-os::vm_page_size())), size ); 1046 subptr(tmp, os::vm_page_size()); 1047 subl(size, os::vm_page_size()); 1048 jcc(Assembler::greater, loop); 1049 1050 // Bang down shadow pages too. 1051 // At this point, (tmp-0) is the last address touched, so don't 1052 // touch it again. (It was touched as (tmp-pagesize) but then tmp 1053 // was post-decremented.) Skip this address by starting at i=1, and 1054 // touch a few more pages below. N.B. It is important to touch all 1055 // the way down to and including i=StackShadowPages. 1056 for (int i = 1; i < StackShadowPages; i++) { 1057 // this could be any sized move but this is can be a debugging crumb 1058 // so the bigger the better. 1059 movptr(Address(tmp, (-i*os::vm_page_size())), size ); 1060 } 1061 } 1062 1063 int MacroAssembler::biased_locking_enter(Register lock_reg, 1064 Register obj_reg, 1065 Register swap_reg, 1066 Register tmp_reg, 1067 bool swap_reg_contains_mark, 1068 Label& done, 1069 Label* slow_case, 1070 BiasedLockingCounters* counters) { 1071 assert(UseBiasedLocking, "why call this otherwise?"); 1072 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); 1073 assert(tmp_reg != noreg, "tmp_reg must be supplied"); 1074 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); 1075 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 1076 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 1077 Address saved_mark_addr(lock_reg, 0); 1078 1079 if (PrintBiasedLockingStatistics && counters == NULL) { 1080 counters = BiasedLocking::counters(); 1081 } 1082 // Biased locking 1083 // See whether the lock is currently biased toward our thread and 1084 // whether the epoch is still valid 1085 // Note that the runtime guarantees sufficient alignment of JavaThread 1086 // pointers to allow age to be placed into low bits 1087 // First check to see whether biasing is even enabled for this object 1088 Label cas_label; 1089 int null_check_offset = -1; 1090 if (!swap_reg_contains_mark) { 1091 null_check_offset = offset(); 1092 movptr(swap_reg, mark_addr); 1093 } 1094 movptr(tmp_reg, swap_reg); 1095 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place); 1096 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern); 1097 jcc(Assembler::notEqual, cas_label); 1098 // The bias pattern is present in the object's header. Need to check 1099 // whether the bias owner and the epoch are both still current. 1100 #ifndef _LP64 1101 // Note that because there is no current thread register on x86_32 we 1102 // need to store off the mark word we read out of the object to 1103 // avoid reloading it and needing to recheck invariants below. This 1104 // store is unfortunate but it makes the overall code shorter and 1105 // simpler. 1106 movptr(saved_mark_addr, swap_reg); 1107 #endif 1108 if (swap_reg_contains_mark) { 1109 null_check_offset = offset(); 1110 } 1111 load_prototype_header(tmp_reg, obj_reg); 1112 #ifdef _LP64 1113 orptr(tmp_reg, r15_thread); 1114 xorptr(tmp_reg, swap_reg); 1115 Register header_reg = tmp_reg; 1116 #else 1117 xorptr(tmp_reg, swap_reg); 1118 get_thread(swap_reg); 1119 xorptr(swap_reg, tmp_reg); 1120 Register header_reg = swap_reg; 1121 #endif 1122 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place)); 1123 if (counters != NULL) { 1124 cond_inc32(Assembler::zero, 1125 ExternalAddress((address) counters->biased_lock_entry_count_addr())); 1126 } 1127 jcc(Assembler::equal, done); 1128 1129 Label try_revoke_bias; 1130 Label try_rebias; 1131 1132 // At this point we know that the header has the bias pattern and 1133 // that we are not the bias owner in the current epoch. We need to 1134 // figure out more details about the state of the header in order to 1135 // know what operations can be legally performed on the object's 1136 // header. 1137 1138 // If the low three bits in the xor result aren't clear, that means 1139 // the prototype header is no longer biased and we have to revoke 1140 // the bias on this object. 1141 testptr(header_reg, markOopDesc::biased_lock_mask_in_place); 1142 jccb(Assembler::notZero, try_revoke_bias); 1143 1144 // Biasing is still enabled for this data type. See whether the 1145 // epoch of the current bias is still valid, meaning that the epoch 1146 // bits of the mark word are equal to the epoch bits of the 1147 // prototype header. (Note that the prototype header's epoch bits 1148 // only change at a safepoint.) If not, attempt to rebias the object 1149 // toward the current thread. Note that we must be absolutely sure 1150 // that the current epoch is invalid in order to do this because 1151 // otherwise the manipulations it performs on the mark word are 1152 // illegal. 1153 testptr(header_reg, markOopDesc::epoch_mask_in_place); 1154 jccb(Assembler::notZero, try_rebias); 1155 1156 // The epoch of the current bias is still valid but we know nothing 1157 // about the owner; it might be set or it might be clear. Try to 1158 // acquire the bias of the object using an atomic operation. If this 1159 // fails we will go in to the runtime to revoke the object's bias. 1160 // Note that we first construct the presumed unbiased header so we 1161 // don't accidentally blow away another thread's valid bias. 1162 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1163 andptr(swap_reg, 1164 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 1165 #ifdef _LP64 1166 movptr(tmp_reg, swap_reg); 1167 orptr(tmp_reg, r15_thread); 1168 #else 1169 get_thread(tmp_reg); 1170 orptr(tmp_reg, swap_reg); 1171 #endif 1172 if (os::is_MP()) { 1173 lock(); 1174 } 1175 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1176 // If the biasing toward our thread failed, this means that 1177 // another thread succeeded in biasing it toward itself and we 1178 // need to revoke that bias. The revocation will occur in the 1179 // interpreter runtime in the slow case. 1180 if (counters != NULL) { 1181 cond_inc32(Assembler::zero, 1182 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); 1183 } 1184 if (slow_case != NULL) { 1185 jcc(Assembler::notZero, *slow_case); 1186 } 1187 jmp(done); 1188 1189 bind(try_rebias); 1190 // At this point we know the epoch has expired, meaning that the 1191 // current "bias owner", if any, is actually invalid. Under these 1192 // circumstances _only_, we are allowed to use the current header's 1193 // value as the comparison value when doing the cas to acquire the 1194 // bias in the current epoch. In other words, we allow transfer of 1195 // the bias from one thread to another directly in this situation. 1196 // 1197 // FIXME: due to a lack of registers we currently blow away the age 1198 // bits in this situation. Should attempt to preserve them. 1199 load_prototype_header(tmp_reg, obj_reg); 1200 #ifdef _LP64 1201 orptr(tmp_reg, r15_thread); 1202 #else 1203 get_thread(swap_reg); 1204 orptr(tmp_reg, swap_reg); 1205 movptr(swap_reg, saved_mark_addr); 1206 #endif 1207 if (os::is_MP()) { 1208 lock(); 1209 } 1210 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1211 // If the biasing toward our thread failed, then another thread 1212 // succeeded in biasing it toward itself and we need to revoke that 1213 // bias. The revocation will occur in the runtime in the slow case. 1214 if (counters != NULL) { 1215 cond_inc32(Assembler::zero, 1216 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); 1217 } 1218 if (slow_case != NULL) { 1219 jcc(Assembler::notZero, *slow_case); 1220 } 1221 jmp(done); 1222 1223 bind(try_revoke_bias); 1224 // The prototype mark in the klass doesn't have the bias bit set any 1225 // more, indicating that objects of this data type are not supposed 1226 // to be biased any more. We are going to try to reset the mark of 1227 // this object to the prototype value and fall through to the 1228 // CAS-based locking scheme. Note that if our CAS fails, it means 1229 // that another thread raced us for the privilege of revoking the 1230 // bias of this particular object, so it's okay to continue in the 1231 // normal locking code. 1232 // 1233 // FIXME: due to a lack of registers we currently blow away the age 1234 // bits in this situation. Should attempt to preserve them. 1235 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1236 load_prototype_header(tmp_reg, obj_reg); 1237 if (os::is_MP()) { 1238 lock(); 1239 } 1240 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1241 // Fall through to the normal CAS-based lock, because no matter what 1242 // the result of the above CAS, some thread must have succeeded in 1243 // removing the bias bit from the object's header. 1244 if (counters != NULL) { 1245 cond_inc32(Assembler::zero, 1246 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); 1247 } 1248 1249 bind(cas_label); 1250 1251 return null_check_offset; 1252 } 1253 1254 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 1255 assert(UseBiasedLocking, "why call this otherwise?"); 1256 1257 // Check for biased locking unlock case, which is a no-op 1258 // Note: we do not have to check the thread ID for two reasons. 1259 // First, the interpreter checks for IllegalMonitorStateException at 1260 // a higher level. Second, if the bias was revoked while we held the 1261 // lock, the object could not be rebiased toward another thread, so 1262 // the bias bit would be clear. 1263 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 1264 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); 1265 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); 1266 jcc(Assembler::equal, done); 1267 } 1268 1269 #ifdef COMPILER2 1270 1271 #if INCLUDE_RTM_OPT 1272 1273 // Update rtm_counters based on abort status 1274 // input: abort_status 1275 // rtm_counters (RTMLockingCounters*) 1276 // flags are killed 1277 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) { 1278 1279 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset())); 1280 if (PrintPreciseRTMLockingStatistics) { 1281 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) { 1282 Label check_abort; 1283 testl(abort_status, (1<<i)); 1284 jccb(Assembler::equal, check_abort); 1285 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx)))); 1286 bind(check_abort); 1287 } 1288 } 1289 } 1290 1291 // Branch if (random & (count-1) != 0), count is 2^n 1292 // tmp, scr and flags are killed 1293 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) { 1294 assert(tmp == rax, ""); 1295 assert(scr == rdx, ""); 1296 rdtsc(); // modifies EDX:EAX 1297 andptr(tmp, count-1); 1298 jccb(Assembler::notZero, brLabel); 1299 } 1300 1301 // Perform abort ratio calculation, set no_rtm bit if high ratio 1302 // input: rtm_counters_Reg (RTMLockingCounters* address) 1303 // tmpReg, rtm_counters_Reg and flags are killed 1304 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg, 1305 Register rtm_counters_Reg, 1306 RTMLockingCounters* rtm_counters, 1307 Metadata* method_data) { 1308 Label L_done, L_check_always_rtm1, L_check_always_rtm2; 1309 1310 if (RTMLockingCalculationDelay > 0) { 1311 // Delay calculation 1312 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg); 1313 testptr(tmpReg, tmpReg); 1314 jccb(Assembler::equal, L_done); 1315 } 1316 // Abort ratio calculation only if abort_count > RTMAbortThreshold 1317 // Aborted transactions = abort_count * 100 1318 // All transactions = total_count * RTMTotalCountIncrRate 1319 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio) 1320 1321 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset())); 1322 cmpptr(tmpReg, RTMAbortThreshold); 1323 jccb(Assembler::below, L_check_always_rtm2); 1324 imulptr(tmpReg, tmpReg, 100); 1325 1326 Register scrReg = rtm_counters_Reg; 1327 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1328 imulptr(scrReg, scrReg, RTMTotalCountIncrRate); 1329 imulptr(scrReg, scrReg, RTMAbortRatio); 1330 cmpptr(tmpReg, scrReg); 1331 jccb(Assembler::below, L_check_always_rtm1); 1332 if (method_data != NULL) { 1333 // set rtm_state to "no rtm" in MDO 1334 mov_metadata(tmpReg, method_data); 1335 if (os::is_MP()) { 1336 lock(); 1337 } 1338 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM); 1339 } 1340 jmpb(L_done); 1341 bind(L_check_always_rtm1); 1342 // Reload RTMLockingCounters* address 1343 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1344 bind(L_check_always_rtm2); 1345 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1346 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate); 1347 jccb(Assembler::below, L_done); 1348 if (method_data != NULL) { 1349 // set rtm_state to "always rtm" in MDO 1350 mov_metadata(tmpReg, method_data); 1351 if (os::is_MP()) { 1352 lock(); 1353 } 1354 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM); 1355 } 1356 bind(L_done); 1357 } 1358 1359 // Update counters and perform abort ratio calculation 1360 // input: abort_status_Reg 1361 // rtm_counters_Reg, flags are killed 1362 void MacroAssembler::rtm_profiling(Register abort_status_Reg, 1363 Register rtm_counters_Reg, 1364 RTMLockingCounters* rtm_counters, 1365 Metadata* method_data, 1366 bool profile_rtm) { 1367 1368 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1369 // update rtm counters based on rax value at abort 1370 // reads abort_status_Reg, updates flags 1371 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1372 rtm_counters_update(abort_status_Reg, rtm_counters_Reg); 1373 if (profile_rtm) { 1374 // Save abort status because abort_status_Reg is used by following code. 1375 if (RTMRetryCount > 0) { 1376 push(abort_status_Reg); 1377 } 1378 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1379 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data); 1380 // restore abort status 1381 if (RTMRetryCount > 0) { 1382 pop(abort_status_Reg); 1383 } 1384 } 1385 } 1386 1387 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4) 1388 // inputs: retry_count_Reg 1389 // : abort_status_Reg 1390 // output: retry_count_Reg decremented by 1 1391 // flags are killed 1392 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) { 1393 Label doneRetry; 1394 assert(abort_status_Reg == rax, ""); 1395 // The abort reason bits are in eax (see all states in rtmLocking.hpp) 1396 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4) 1397 // if reason is in 0x6 and retry count != 0 then retry 1398 andptr(abort_status_Reg, 0x6); 1399 jccb(Assembler::zero, doneRetry); 1400 testl(retry_count_Reg, retry_count_Reg); 1401 jccb(Assembler::zero, doneRetry); 1402 pause(); 1403 decrementl(retry_count_Reg); 1404 jmp(retryLabel); 1405 bind(doneRetry); 1406 } 1407 1408 // Spin and retry if lock is busy, 1409 // inputs: box_Reg (monitor address) 1410 // : retry_count_Reg 1411 // output: retry_count_Reg decremented by 1 1412 // : clear z flag if retry count exceeded 1413 // tmp_Reg, scr_Reg, flags are killed 1414 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg, 1415 Register tmp_Reg, Register scr_Reg, Label& retryLabel) { 1416 Label SpinLoop, SpinExit, doneRetry; 1417 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1418 1419 testl(retry_count_Reg, retry_count_Reg); 1420 jccb(Assembler::zero, doneRetry); 1421 decrementl(retry_count_Reg); 1422 movptr(scr_Reg, RTMSpinLoopCount); 1423 1424 bind(SpinLoop); 1425 pause(); 1426 decrementl(scr_Reg); 1427 jccb(Assembler::lessEqual, SpinExit); 1428 movptr(tmp_Reg, Address(box_Reg, owner_offset)); 1429 testptr(tmp_Reg, tmp_Reg); 1430 jccb(Assembler::notZero, SpinLoop); 1431 1432 bind(SpinExit); 1433 jmp(retryLabel); 1434 bind(doneRetry); 1435 incrementl(retry_count_Reg); // clear z flag 1436 } 1437 1438 // Use RTM for normal stack locks 1439 // Input: objReg (object to lock) 1440 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg, 1441 Register retry_on_abort_count_Reg, 1442 RTMLockingCounters* stack_rtm_counters, 1443 Metadata* method_data, bool profile_rtm, 1444 Label& DONE_LABEL, Label& IsInflated) { 1445 assert(UseRTMForStackLocks, "why call this otherwise?"); 1446 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1447 assert(tmpReg == rax, ""); 1448 assert(scrReg == rdx, ""); 1449 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1450 1451 if (RTMRetryCount > 0) { 1452 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1453 bind(L_rtm_retry); 1454 } 1455 movptr(tmpReg, Address(objReg, 0)); 1456 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1457 jcc(Assembler::notZero, IsInflated); 1458 1459 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1460 Label L_noincrement; 1461 if (RTMTotalCountIncrRate > 1) { 1462 // tmpReg, scrReg and flags are killed 1463 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1464 } 1465 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM"); 1466 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg); 1467 bind(L_noincrement); 1468 } 1469 xbegin(L_on_abort); 1470 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1471 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1472 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1473 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked 1474 1475 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1476 if (UseRTMXendForLockBusy) { 1477 xend(); 1478 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry) 1479 jmp(L_decrement_retry); 1480 } 1481 else { 1482 xabort(0); 1483 } 1484 bind(L_on_abort); 1485 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1486 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm); 1487 } 1488 bind(L_decrement_retry); 1489 if (RTMRetryCount > 0) { 1490 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1491 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1492 } 1493 } 1494 1495 // Use RTM for inflating locks 1496 // inputs: objReg (object to lock) 1497 // boxReg (on-stack box address (displaced header location) - KILLED) 1498 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value) 1499 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg, 1500 Register scrReg, Register retry_on_busy_count_Reg, 1501 Register retry_on_abort_count_Reg, 1502 RTMLockingCounters* rtm_counters, 1503 Metadata* method_data, bool profile_rtm, 1504 Label& DONE_LABEL) { 1505 assert(UseRTMLocking, "why call this otherwise?"); 1506 assert(tmpReg == rax, ""); 1507 assert(scrReg == rdx, ""); 1508 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1509 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1510 1511 // Without cast to int32_t a movptr will destroy r10 which is typically obj 1512 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1513 movptr(boxReg, tmpReg); // Save ObjectMonitor address 1514 1515 if (RTMRetryCount > 0) { 1516 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy 1517 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1518 bind(L_rtm_retry); 1519 } 1520 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1521 Label L_noincrement; 1522 if (RTMTotalCountIncrRate > 1) { 1523 // tmpReg, scrReg and flags are killed 1524 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1525 } 1526 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1527 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg); 1528 bind(L_noincrement); 1529 } 1530 xbegin(L_on_abort); 1531 movptr(tmpReg, Address(objReg, 0)); 1532 movptr(tmpReg, Address(tmpReg, owner_offset)); 1533 testptr(tmpReg, tmpReg); 1534 jcc(Assembler::zero, DONE_LABEL); 1535 if (UseRTMXendForLockBusy) { 1536 xend(); 1537 jmp(L_decrement_retry); 1538 } 1539 else { 1540 xabort(0); 1541 } 1542 bind(L_on_abort); 1543 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1544 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1545 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm); 1546 } 1547 if (RTMRetryCount > 0) { 1548 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1549 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1550 } 1551 1552 movptr(tmpReg, Address(boxReg, owner_offset)) ; 1553 testptr(tmpReg, tmpReg) ; 1554 jccb(Assembler::notZero, L_decrement_retry) ; 1555 1556 // Appears unlocked - try to swing _owner from null to non-null. 1557 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1558 #ifdef _LP64 1559 Register threadReg = r15_thread; 1560 #else 1561 get_thread(scrReg); 1562 Register threadReg = scrReg; 1563 #endif 1564 if (os::is_MP()) { 1565 lock(); 1566 } 1567 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg 1568 1569 if (RTMRetryCount > 0) { 1570 // success done else retry 1571 jccb(Assembler::equal, DONE_LABEL) ; 1572 bind(L_decrement_retry); 1573 // Spin and retry if lock is busy. 1574 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry); 1575 } 1576 else { 1577 bind(L_decrement_retry); 1578 } 1579 } 1580 1581 #endif // INCLUDE_RTM_OPT 1582 1583 // Fast_Lock and Fast_Unlock used by C2 1584 1585 // Because the transitions from emitted code to the runtime 1586 // monitorenter/exit helper stubs are so slow it's critical that 1587 // we inline both the stack-locking fast-path and the inflated fast path. 1588 // 1589 // See also: cmpFastLock and cmpFastUnlock. 1590 // 1591 // What follows is a specialized inline transliteration of the code 1592 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat 1593 // another option would be to emit TrySlowEnter and TrySlowExit methods 1594 // at startup-time. These methods would accept arguments as 1595 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure 1596 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply 1597 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. 1598 // In practice, however, the # of lock sites is bounded and is usually small. 1599 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer 1600 // if the processor uses simple bimodal branch predictors keyed by EIP 1601 // Since the helper routines would be called from multiple synchronization 1602 // sites. 1603 // 1604 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" 1605 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites 1606 // to those specialized methods. That'd give us a mostly platform-independent 1607 // implementation that the JITs could optimize and inline at their pleasure. 1608 // Done correctly, the only time we'd need to cross to native could would be 1609 // to park() or unpark() threads. We'd also need a few more unsafe operators 1610 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and 1611 // (b) explicit barriers or fence operations. 1612 // 1613 // TODO: 1614 // 1615 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). 1616 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. 1617 // Given TLAB allocation, Self is usually manifested in a register, so passing it into 1618 // the lock operators would typically be faster than reifying Self. 1619 // 1620 // * Ideally I'd define the primitives as: 1621 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. 1622 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED 1623 // Unfortunately ADLC bugs prevent us from expressing the ideal form. 1624 // Instead, we're stuck with a rather awkward and brittle register assignments below. 1625 // Furthermore the register assignments are overconstrained, possibly resulting in 1626 // sub-optimal code near the synchronization site. 1627 // 1628 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. 1629 // Alternately, use a better sp-proximity test. 1630 // 1631 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. 1632 // Either one is sufficient to uniquely identify a thread. 1633 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. 1634 // 1635 // * Intrinsify notify() and notifyAll() for the common cases where the 1636 // object is locked by the calling thread but the waitlist is empty. 1637 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). 1638 // 1639 // * use jccb and jmpb instead of jcc and jmp to improve code density. 1640 // But beware of excessive branch density on AMD Opterons. 1641 // 1642 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success 1643 // or failure of the fast-path. If the fast-path fails then we pass 1644 // control to the slow-path, typically in C. In Fast_Lock and 1645 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 1646 // will emit a conditional branch immediately after the node. 1647 // So we have branches to branches and lots of ICC.ZF games. 1648 // Instead, it might be better to have C2 pass a "FailureLabel" 1649 // into Fast_Lock and Fast_Unlock. In the case of success, control 1650 // will drop through the node. ICC.ZF is undefined at exit. 1651 // In the case of failure, the node will branch directly to the 1652 // FailureLabel 1653 1654 1655 // obj: object to lock 1656 // box: on-stack box address (displaced header location) - KILLED 1657 // rax,: tmp -- KILLED 1658 // scr: tmp -- KILLED 1659 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg, 1660 Register scrReg, Register cx1Reg, Register cx2Reg, 1661 BiasedLockingCounters* counters, 1662 RTMLockingCounters* rtm_counters, 1663 RTMLockingCounters* stack_rtm_counters, 1664 Metadata* method_data, 1665 bool use_rtm, bool profile_rtm) { 1666 // Ensure the register assignents are disjoint 1667 assert(tmpReg == rax, ""); 1668 1669 if (use_rtm) { 1670 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg); 1671 } else { 1672 assert(cx1Reg == noreg, ""); 1673 assert(cx2Reg == noreg, ""); 1674 assert_different_registers(objReg, boxReg, tmpReg, scrReg); 1675 } 1676 1677 if (counters != NULL) { 1678 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg); 1679 } 1680 if (EmitSync & 1) { 1681 // set box->dhw = markOopDesc::unused_mark() 1682 // Force all sync thru slow-path: slow_enter() and slow_exit() 1683 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1684 cmpptr (rsp, (int32_t)NULL_WORD); 1685 } else { 1686 // Possible cases that we'll encounter in fast_lock 1687 // ------------------------------------------------ 1688 // * Inflated 1689 // -- unlocked 1690 // -- Locked 1691 // = by self 1692 // = by other 1693 // * biased 1694 // -- by Self 1695 // -- by other 1696 // * neutral 1697 // * stack-locked 1698 // -- by self 1699 // = sp-proximity test hits 1700 // = sp-proximity test generates false-negative 1701 // -- by other 1702 // 1703 1704 Label IsInflated, DONE_LABEL; 1705 1706 // it's stack-locked, biased or neutral 1707 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage 1708 // order to reduce the number of conditional branches in the most common cases. 1709 // Beware -- there's a subtle invariant that fetch of the markword 1710 // at [FETCH], below, will never observe a biased encoding (*101b). 1711 // If this invariant is not held we risk exclusion (safety) failure. 1712 if (UseBiasedLocking && !UseOptoBiasInlining) { 1713 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters); 1714 } 1715 1716 #if INCLUDE_RTM_OPT 1717 if (UseRTMForStackLocks && use_rtm) { 1718 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg, 1719 stack_rtm_counters, method_data, profile_rtm, 1720 DONE_LABEL, IsInflated); 1721 } 1722 #endif // INCLUDE_RTM_OPT 1723 1724 movptr(tmpReg, Address(objReg, 0)); // [FETCH] 1725 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1726 jccb(Assembler::notZero, IsInflated); 1727 1728 // Attempt stack-locking ... 1729 orptr (tmpReg, markOopDesc::unlocked_value); 1730 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 1731 if (os::is_MP()) { 1732 lock(); 1733 } 1734 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg 1735 if (counters != NULL) { 1736 cond_inc32(Assembler::equal, 1737 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1738 } 1739 jcc(Assembler::equal, DONE_LABEL); // Success 1740 1741 // Recursive locking. 1742 // The object is stack-locked: markword contains stack pointer to BasicLock. 1743 // Locked by current thread if difference with current SP is less than one page. 1744 subptr(tmpReg, rsp); 1745 // Next instruction set ZFlag == 1 (Success) if difference is less then one page. 1746 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) ); 1747 movptr(Address(boxReg, 0), tmpReg); 1748 if (counters != NULL) { 1749 cond_inc32(Assembler::equal, 1750 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1751 } 1752 jmp(DONE_LABEL); 1753 1754 bind(IsInflated); 1755 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value 1756 1757 #if INCLUDE_RTM_OPT 1758 // Use the same RTM locking code in 32- and 64-bit VM. 1759 if (use_rtm) { 1760 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg, 1761 rtm_counters, method_data, profile_rtm, DONE_LABEL); 1762 } else { 1763 #endif // INCLUDE_RTM_OPT 1764 1765 #ifndef _LP64 1766 // The object is inflated. 1767 1768 // boxReg refers to the on-stack BasicLock in the current frame. 1769 // We'd like to write: 1770 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices. 1771 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers 1772 // additional latency as we have another ST in the store buffer that must drain. 1773 1774 if (EmitSync & 8192) { 1775 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty 1776 get_thread (scrReg); 1777 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1778 movptr(tmpReg, NULL_WORD); // consider: xor vs mov 1779 if (os::is_MP()) { 1780 lock(); 1781 } 1782 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1783 } else 1784 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 1785 // register juggle because we need tmpReg for cmpxchgptr below 1786 movptr(scrReg, boxReg); 1787 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1788 1789 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1790 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1791 // prefetchw [eax + Offset(_owner)-2] 1792 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1793 } 1794 1795 if ((EmitSync & 64) == 0) { 1796 // Optimistic form: consider XORL tmpReg,tmpReg 1797 movptr(tmpReg, NULL_WORD); 1798 } else { 1799 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1800 // Test-And-CAS instead of CAS 1801 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1802 testptr(tmpReg, tmpReg); // Locked ? 1803 jccb (Assembler::notZero, DONE_LABEL); 1804 } 1805 1806 // Appears unlocked - try to swing _owner from null to non-null. 1807 // Ideally, I'd manifest "Self" with get_thread and then attempt 1808 // to CAS the register containing Self into m->Owner. 1809 // But we don't have enough registers, so instead we can either try to CAS 1810 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds 1811 // we later store "Self" into m->Owner. Transiently storing a stack address 1812 // (rsp or the address of the box) into m->owner is harmless. 1813 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1814 if (os::is_MP()) { 1815 lock(); 1816 } 1817 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1818 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3 1819 // If we weren't able to swing _owner from NULL to the BasicLock 1820 // then take the slow path. 1821 jccb (Assembler::notZero, DONE_LABEL); 1822 // update _owner from BasicLock to thread 1823 get_thread (scrReg); // beware: clobbers ICCs 1824 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg); 1825 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success 1826 1827 // If the CAS fails we can either retry or pass control to the slow-path. 1828 // We use the latter tactic. 1829 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1830 // If the CAS was successful ... 1831 // Self has acquired the lock 1832 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1833 // Intentional fall-through into DONE_LABEL ... 1834 } else { 1835 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty 1836 movptr(boxReg, tmpReg); 1837 1838 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1839 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1840 // prefetchw [eax + Offset(_owner)-2] 1841 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1842 } 1843 1844 if ((EmitSync & 64) == 0) { 1845 // Optimistic form 1846 xorptr (tmpReg, tmpReg); 1847 } else { 1848 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1849 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1850 testptr(tmpReg, tmpReg); // Locked ? 1851 jccb (Assembler::notZero, DONE_LABEL); 1852 } 1853 1854 // Appears unlocked - try to swing _owner from null to non-null. 1855 // Use either "Self" (in scr) or rsp as thread identity in _owner. 1856 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1857 get_thread (scrReg); 1858 if (os::is_MP()) { 1859 lock(); 1860 } 1861 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1862 1863 // If the CAS fails we can either retry or pass control to the slow-path. 1864 // We use the latter tactic. 1865 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1866 // If the CAS was successful ... 1867 // Self has acquired the lock 1868 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1869 // Intentional fall-through into DONE_LABEL ... 1870 } 1871 #else // _LP64 1872 // It's inflated 1873 movq(scrReg, tmpReg); 1874 xorq(tmpReg, tmpReg); 1875 1876 if (os::is_MP()) { 1877 lock(); 1878 } 1879 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1880 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark(). 1881 // Without cast to int32_t movptr will destroy r10 which is typically obj. 1882 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1883 // Intentional fall-through into DONE_LABEL ... 1884 // Propagate ICC.ZF from CAS above into DONE_LABEL. 1885 #endif // _LP64 1886 #if INCLUDE_RTM_OPT 1887 } // use_rtm() 1888 #endif 1889 // DONE_LABEL is a hot target - we'd really like to place it at the 1890 // start of cache line by padding with NOPs. 1891 // See the AMD and Intel software optimization manuals for the 1892 // most efficient "long" NOP encodings. 1893 // Unfortunately none of our alignment mechanisms suffice. 1894 bind(DONE_LABEL); 1895 1896 // At DONE_LABEL the icc ZFlag is set as follows ... 1897 // Fast_Unlock uses the same protocol. 1898 // ZFlag == 1 -> Success 1899 // ZFlag == 0 -> Failure - force control through the slow-path 1900 } 1901 } 1902 1903 // obj: object to unlock 1904 // box: box address (displaced header location), killed. Must be EAX. 1905 // tmp: killed, cannot be obj nor box. 1906 // 1907 // Some commentary on balanced locking: 1908 // 1909 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. 1910 // Methods that don't have provably balanced locking are forced to run in the 1911 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. 1912 // The interpreter provides two properties: 1913 // I1: At return-time the interpreter automatically and quietly unlocks any 1914 // objects acquired the current activation (frame). Recall that the 1915 // interpreter maintains an on-stack list of locks currently held by 1916 // a frame. 1917 // I2: If a method attempts to unlock an object that is not held by the 1918 // the frame the interpreter throws IMSX. 1919 // 1920 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). 1921 // B() doesn't have provably balanced locking so it runs in the interpreter. 1922 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O 1923 // is still locked by A(). 1924 // 1925 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: 1926 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter 1927 // should not be unlocked by "normal" java-level locking and vice-versa. The specification 1928 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. 1929 // Arguably given that the spec legislates the JNI case as undefined our implementation 1930 // could reasonably *avoid* checking owner in Fast_Unlock(). 1931 // In the interest of performance we elide m->Owner==Self check in unlock. 1932 // A perfectly viable alternative is to elide the owner check except when 1933 // Xcheck:jni is enabled. 1934 1935 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) { 1936 assert(boxReg == rax, ""); 1937 assert_different_registers(objReg, boxReg, tmpReg); 1938 1939 if (EmitSync & 4) { 1940 // Disable - inhibit all inlining. Force control through the slow-path 1941 cmpptr (rsp, 0); 1942 } else { 1943 Label DONE_LABEL, Stacked, CheckSucc; 1944 1945 // Critically, the biased locking test must have precedence over 1946 // and appear before the (box->dhw == 0) recursive stack-lock test. 1947 if (UseBiasedLocking && !UseOptoBiasInlining) { 1948 biased_locking_exit(objReg, tmpReg, DONE_LABEL); 1949 } 1950 1951 #if INCLUDE_RTM_OPT 1952 if (UseRTMForStackLocks && use_rtm) { 1953 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1954 Label L_regular_unlock; 1955 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1956 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1957 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1958 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock 1959 xend(); // otherwise end... 1960 jmp(DONE_LABEL); // ... and we're done 1961 bind(L_regular_unlock); 1962 } 1963 #endif 1964 1965 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header 1966 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock 1967 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword 1968 testptr(tmpReg, markOopDesc::monitor_value); // Inflated? 1969 jccb (Assembler::zero, Stacked); 1970 1971 // It's inflated. 1972 #if INCLUDE_RTM_OPT 1973 if (use_rtm) { 1974 Label L_regular_inflated_unlock; 1975 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1976 movptr(boxReg, Address(tmpReg, owner_offset)); 1977 testptr(boxReg, boxReg); 1978 jccb(Assembler::notZero, L_regular_inflated_unlock); 1979 xend(); 1980 jmpb(DONE_LABEL); 1981 bind(L_regular_inflated_unlock); 1982 } 1983 #endif 1984 1985 // Despite our balanced locking property we still check that m->_owner == Self 1986 // as java routines or native JNI code called by this thread might 1987 // have released the lock. 1988 // Refer to the comments in synchronizer.cpp for how we might encode extra 1989 // state in _succ so we can avoid fetching EntryList|cxq. 1990 // 1991 // I'd like to add more cases in fast_lock() and fast_unlock() -- 1992 // such as recursive enter and exit -- but we have to be wary of 1993 // I$ bloat, T$ effects and BP$ effects. 1994 // 1995 // If there's no contention try a 1-0 exit. That is, exit without 1996 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how 1997 // we detect and recover from the race that the 1-0 exit admits. 1998 // 1999 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier 2000 // before it STs null into _owner, releasing the lock. Updates 2001 // to data protected by the critical section must be visible before 2002 // we drop the lock (and thus before any other thread could acquire 2003 // the lock and observe the fields protected by the lock). 2004 // IA32's memory-model is SPO, so STs are ordered with respect to 2005 // each other and there's no need for an explicit barrier (fence). 2006 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 2007 #ifndef _LP64 2008 get_thread (boxReg); 2009 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 2010 // prefetchw [ebx + Offset(_owner)-2] 2011 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2012 } 2013 2014 // Note that we could employ various encoding schemes to reduce 2015 // the number of loads below (currently 4) to just 2 or 3. 2016 // Refer to the comments in synchronizer.cpp. 2017 // In practice the chain of fetches doesn't seem to impact performance, however. 2018 xorptr(boxReg, boxReg); 2019 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { 2020 // Attempt to reduce branch density - AMD's branch predictor. 2021 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2022 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2023 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2024 jccb (Assembler::notZero, DONE_LABEL); 2025 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2026 jmpb (DONE_LABEL); 2027 } else { 2028 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2029 jccb (Assembler::notZero, DONE_LABEL); 2030 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2031 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2032 jccb (Assembler::notZero, CheckSucc); 2033 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2034 jmpb (DONE_LABEL); 2035 } 2036 2037 // The Following code fragment (EmitSync & 65536) improves the performance of 2038 // contended applications and contended synchronization microbenchmarks. 2039 // Unfortunately the emission of the code - even though not executed - causes regressions 2040 // in scimark and jetstream, evidently because of $ effects. Replacing the code 2041 // with an equal number of never-executed NOPs results in the same regression. 2042 // We leave it off by default. 2043 2044 if ((EmitSync & 65536) != 0) { 2045 Label LSuccess, LGoSlowPath ; 2046 2047 bind (CheckSucc); 2048 2049 // Optional pre-test ... it's safe to elide this 2050 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2051 jccb(Assembler::zero, LGoSlowPath); 2052 2053 // We have a classic Dekker-style idiom: 2054 // ST m->_owner = 0 ; MEMBAR; LD m->_succ 2055 // There are a number of ways to implement the barrier: 2056 // (1) lock:andl &m->_owner, 0 2057 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. 2058 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 2059 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 2060 // (2) If supported, an explicit MFENCE is appealing. 2061 // In older IA32 processors MFENCE is slower than lock:add or xchg 2062 // particularly if the write-buffer is full as might be the case if 2063 // if stores closely precede the fence or fence-equivalent instruction. 2064 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2065 // as the situation has changed with Nehalem and Shanghai. 2066 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack 2067 // The $lines underlying the top-of-stack should be in M-state. 2068 // The locked add instruction is serializing, of course. 2069 // (4) Use xchg, which is serializing 2070 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works 2071 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. 2072 // The integer condition codes will tell us if succ was 0. 2073 // Since _succ and _owner should reside in the same $line and 2074 // we just stored into _owner, it's likely that the $line 2075 // remains in M-state for the lock:orl. 2076 // 2077 // We currently use (3), although it's likely that switching to (2) 2078 // is correct for the future. 2079 2080 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2081 if (os::is_MP()) { 2082 lock(); addptr(Address(rsp, 0), 0); 2083 } 2084 // Ratify _succ remains non-null 2085 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0); 2086 jccb (Assembler::notZero, LSuccess); 2087 2088 xorptr(boxReg, boxReg); // box is really EAX 2089 if (os::is_MP()) { lock(); } 2090 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2091 // There's no successor so we tried to regrab the lock with the 2092 // placeholder value. If that didn't work, then another thread 2093 // grabbed the lock so we're done (and exit was a success). 2094 jccb (Assembler::notEqual, LSuccess); 2095 // Since we're low on registers we installed rsp as a placeholding in _owner. 2096 // Now install Self over rsp. This is safe as we're transitioning from 2097 // non-null to non=null 2098 get_thread (boxReg); 2099 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg); 2100 // Intentional fall-through into LGoSlowPath ... 2101 2102 bind (LGoSlowPath); 2103 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure 2104 jmpb (DONE_LABEL); 2105 2106 bind (LSuccess); 2107 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success 2108 jmpb (DONE_LABEL); 2109 } 2110 2111 bind (Stacked); 2112 // It's not inflated and it's not recursively stack-locked and it's not biased. 2113 // It must be stack-locked. 2114 // Try to reset the header to displaced header. 2115 // The "box" value on the stack is stable, so we can reload 2116 // and be assured we observe the same value as above. 2117 movptr(tmpReg, Address(boxReg, 0)); 2118 if (os::is_MP()) { 2119 lock(); 2120 } 2121 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2122 // Intention fall-thru into DONE_LABEL 2123 2124 // DONE_LABEL is a hot target - we'd really like to place it at the 2125 // start of cache line by padding with NOPs. 2126 // See the AMD and Intel software optimization manuals for the 2127 // most efficient "long" NOP encodings. 2128 // Unfortunately none of our alignment mechanisms suffice. 2129 if ((EmitSync & 65536) == 0) { 2130 bind (CheckSucc); 2131 } 2132 #else // _LP64 2133 // It's inflated 2134 if (EmitSync & 1024) { 2135 // Emit code to check that _owner == Self 2136 // We could fold the _owner test into subsequent code more efficiently 2137 // than using a stand-alone check, but since _owner checking is off by 2138 // default we don't bother. We also might consider predicating the 2139 // _owner==Self check on Xcheck:jni or running on a debug build. 2140 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2141 xorptr(boxReg, r15_thread); 2142 } else { 2143 xorptr(boxReg, boxReg); 2144 } 2145 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2146 jccb (Assembler::notZero, DONE_LABEL); 2147 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2148 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2149 jccb (Assembler::notZero, CheckSucc); 2150 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2151 jmpb (DONE_LABEL); 2152 2153 if ((EmitSync & 65536) == 0) { 2154 // Try to avoid passing control into the slow_path ... 2155 Label LSuccess, LGoSlowPath ; 2156 bind (CheckSucc); 2157 2158 // The following optional optimization can be elided if necessary 2159 // Effectively: if (succ == null) goto SlowPath 2160 // The code reduces the window for a race, however, 2161 // and thus benefits performance. 2162 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2163 jccb (Assembler::zero, LGoSlowPath); 2164 2165 if ((EmitSync & 16) && os::is_MP()) { 2166 orptr(boxReg, boxReg); 2167 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2168 } else { 2169 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2170 if (os::is_MP()) { 2171 // Memory barrier/fence 2172 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ 2173 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack. 2174 // This is faster on Nehalem and AMD Shanghai/Barcelona. 2175 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2176 // We might also restructure (ST Owner=0;barrier;LD _Succ) to 2177 // (mov box,0; xchgq box, &m->Owner; LD _succ) . 2178 lock(); addl(Address(rsp, 0), 0); 2179 } 2180 } 2181 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2182 jccb (Assembler::notZero, LSuccess); 2183 2184 // Rare inopportune interleaving - race. 2185 // The successor vanished in the small window above. 2186 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor. 2187 // We need to ensure progress and succession. 2188 // Try to reacquire the lock. 2189 // If that fails then the new owner is responsible for succession and this 2190 // thread needs to take no further action and can exit via the fast path (success). 2191 // If the re-acquire succeeds then pass control into the slow path. 2192 // As implemented, this latter mode is horrible because we generated more 2193 // coherence traffic on the lock *and* artifically extended the critical section 2194 // length while by virtue of passing control into the slow path. 2195 2196 // box is really RAX -- the following CMPXCHG depends on that binding 2197 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R) 2198 movptr(boxReg, (int32_t)NULL_WORD); 2199 if (os::is_MP()) { lock(); } 2200 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2201 // There's no successor so we tried to regrab the lock. 2202 // If that didn't work, then another thread grabbed the 2203 // lock so we're done (and exit was a success). 2204 jccb (Assembler::notEqual, LSuccess); 2205 // Intentional fall-through into slow-path 2206 2207 bind (LGoSlowPath); 2208 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure 2209 jmpb (DONE_LABEL); 2210 2211 bind (LSuccess); 2212 testl (boxReg, 0); // set ICC.ZF=1 to indicate success 2213 jmpb (DONE_LABEL); 2214 } 2215 2216 bind (Stacked); 2217 movptr(tmpReg, Address (boxReg, 0)); // re-fetch 2218 if (os::is_MP()) { lock(); } 2219 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2220 2221 if (EmitSync & 65536) { 2222 bind (CheckSucc); 2223 } 2224 #endif 2225 bind(DONE_LABEL); 2226 } 2227 } 2228 #endif // COMPILER2 2229 2230 void MacroAssembler::c2bool(Register x) { 2231 // implements x == 0 ? 0 : 1 2232 // note: must only look at least-significant byte of x 2233 // since C-style booleans are stored in one byte 2234 // only! (was bug) 2235 andl(x, 0xFF); 2236 setb(Assembler::notZero, x); 2237 } 2238 2239 // Wouldn't need if AddressLiteral version had new name 2240 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { 2241 Assembler::call(L, rtype); 2242 } 2243 2244 void MacroAssembler::call(Register entry) { 2245 Assembler::call(entry); 2246 } 2247 2248 void MacroAssembler::call(AddressLiteral entry) { 2249 if (reachable(entry)) { 2250 Assembler::call_literal(entry.target(), entry.rspec()); 2251 } else { 2252 lea(rscratch1, entry); 2253 Assembler::call(rscratch1); 2254 } 2255 } 2256 2257 void MacroAssembler::ic_call(address entry) { 2258 RelocationHolder rh = virtual_call_Relocation::spec(pc()); 2259 movptr(rax, (intptr_t)Universe::non_oop_word()); 2260 call(AddressLiteral(entry, rh)); 2261 } 2262 2263 // Implementation of call_VM versions 2264 2265 void MacroAssembler::call_VM(Register oop_result, 2266 address entry_point, 2267 bool check_exceptions) { 2268 Label C, E; 2269 call(C, relocInfo::none); 2270 jmp(E); 2271 2272 bind(C); 2273 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 2274 ret(0); 2275 2276 bind(E); 2277 } 2278 2279 void MacroAssembler::call_VM(Register oop_result, 2280 address entry_point, 2281 Register arg_1, 2282 bool check_exceptions) { 2283 Label C, E; 2284 call(C, relocInfo::none); 2285 jmp(E); 2286 2287 bind(C); 2288 pass_arg1(this, arg_1); 2289 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 2290 ret(0); 2291 2292 bind(E); 2293 } 2294 2295 void MacroAssembler::call_VM(Register oop_result, 2296 address entry_point, 2297 Register arg_1, 2298 Register arg_2, 2299 bool check_exceptions) { 2300 Label C, E; 2301 call(C, relocInfo::none); 2302 jmp(E); 2303 2304 bind(C); 2305 2306 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2307 2308 pass_arg2(this, arg_2); 2309 pass_arg1(this, arg_1); 2310 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 2311 ret(0); 2312 2313 bind(E); 2314 } 2315 2316 void MacroAssembler::call_VM(Register oop_result, 2317 address entry_point, 2318 Register arg_1, 2319 Register arg_2, 2320 Register arg_3, 2321 bool check_exceptions) { 2322 Label C, E; 2323 call(C, relocInfo::none); 2324 jmp(E); 2325 2326 bind(C); 2327 2328 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2329 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2330 pass_arg3(this, arg_3); 2331 2332 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2333 pass_arg2(this, arg_2); 2334 2335 pass_arg1(this, arg_1); 2336 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 2337 ret(0); 2338 2339 bind(E); 2340 } 2341 2342 void MacroAssembler::call_VM(Register oop_result, 2343 Register last_java_sp, 2344 address entry_point, 2345 int number_of_arguments, 2346 bool check_exceptions) { 2347 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2348 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2349 } 2350 2351 void MacroAssembler::call_VM(Register oop_result, 2352 Register last_java_sp, 2353 address entry_point, 2354 Register arg_1, 2355 bool check_exceptions) { 2356 pass_arg1(this, arg_1); 2357 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2358 } 2359 2360 void MacroAssembler::call_VM(Register oop_result, 2361 Register last_java_sp, 2362 address entry_point, 2363 Register arg_1, 2364 Register arg_2, 2365 bool check_exceptions) { 2366 2367 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2368 pass_arg2(this, arg_2); 2369 pass_arg1(this, arg_1); 2370 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2371 } 2372 2373 void MacroAssembler::call_VM(Register oop_result, 2374 Register last_java_sp, 2375 address entry_point, 2376 Register arg_1, 2377 Register arg_2, 2378 Register arg_3, 2379 bool check_exceptions) { 2380 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2381 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2382 pass_arg3(this, arg_3); 2383 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2384 pass_arg2(this, arg_2); 2385 pass_arg1(this, arg_1); 2386 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2387 } 2388 2389 void MacroAssembler::super_call_VM(Register oop_result, 2390 Register last_java_sp, 2391 address entry_point, 2392 int number_of_arguments, 2393 bool check_exceptions) { 2394 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2395 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2396 } 2397 2398 void MacroAssembler::super_call_VM(Register oop_result, 2399 Register last_java_sp, 2400 address entry_point, 2401 Register arg_1, 2402 bool check_exceptions) { 2403 pass_arg1(this, arg_1); 2404 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2405 } 2406 2407 void MacroAssembler::super_call_VM(Register oop_result, 2408 Register last_java_sp, 2409 address entry_point, 2410 Register arg_1, 2411 Register arg_2, 2412 bool check_exceptions) { 2413 2414 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2415 pass_arg2(this, arg_2); 2416 pass_arg1(this, arg_1); 2417 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2418 } 2419 2420 void MacroAssembler::super_call_VM(Register oop_result, 2421 Register last_java_sp, 2422 address entry_point, 2423 Register arg_1, 2424 Register arg_2, 2425 Register arg_3, 2426 bool check_exceptions) { 2427 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2428 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2429 pass_arg3(this, arg_3); 2430 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2431 pass_arg2(this, arg_2); 2432 pass_arg1(this, arg_1); 2433 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2434 } 2435 2436 void MacroAssembler::call_VM_base(Register oop_result, 2437 Register java_thread, 2438 Register last_java_sp, 2439 address entry_point, 2440 int number_of_arguments, 2441 bool check_exceptions) { 2442 // determine java_thread register 2443 if (!java_thread->is_valid()) { 2444 #ifdef _LP64 2445 java_thread = r15_thread; 2446 #else 2447 java_thread = rdi; 2448 get_thread(java_thread); 2449 #endif // LP64 2450 } 2451 // determine last_java_sp register 2452 if (!last_java_sp->is_valid()) { 2453 last_java_sp = rsp; 2454 } 2455 // debugging support 2456 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 2457 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); 2458 #ifdef ASSERT 2459 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 2460 // r12 is the heapbase. 2461 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) 2462 #endif // ASSERT 2463 2464 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 2465 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 2466 2467 // push java thread (becomes first argument of C function) 2468 2469 NOT_LP64(push(java_thread); number_of_arguments++); 2470 LP64_ONLY(mov(c_rarg0, r15_thread)); 2471 2472 // set last Java frame before call 2473 assert(last_java_sp != rbp, "can't use ebp/rbp"); 2474 2475 // Only interpreter should have to set fp 2476 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); 2477 2478 // do the call, remove parameters 2479 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); 2480 2481 // restore the thread (cannot use the pushed argument since arguments 2482 // may be overwritten by C code generated by an optimizing compiler); 2483 // however can use the register value directly if it is callee saved. 2484 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { 2485 // rdi & rsi (also r15) are callee saved -> nothing to do 2486 #ifdef ASSERT 2487 guarantee(java_thread != rax, "change this code"); 2488 push(rax); 2489 { Label L; 2490 get_thread(rax); 2491 cmpptr(java_thread, rax); 2492 jcc(Assembler::equal, L); 2493 STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); 2494 bind(L); 2495 } 2496 pop(rax); 2497 #endif 2498 } else { 2499 get_thread(java_thread); 2500 } 2501 // reset last Java frame 2502 // Only interpreter should have to clear fp 2503 reset_last_Java_frame(java_thread, true, false); 2504 2505 #ifndef CC_INTERP 2506 // C++ interp handles this in the interpreter 2507 check_and_handle_popframe(java_thread); 2508 check_and_handle_earlyret(java_thread); 2509 #endif /* CC_INTERP */ 2510 2511 if (check_exceptions) { 2512 // check for pending exceptions (java_thread is set upon return) 2513 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); 2514 #ifndef _LP64 2515 jump_cc(Assembler::notEqual, 2516 RuntimeAddress(StubRoutines::forward_exception_entry())); 2517 #else 2518 // This used to conditionally jump to forward_exception however it is 2519 // possible if we relocate that the branch will not reach. So we must jump 2520 // around so we can always reach 2521 2522 Label ok; 2523 jcc(Assembler::equal, ok); 2524 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 2525 bind(ok); 2526 #endif // LP64 2527 } 2528 2529 // get oop result if there is one and reset the value in the thread 2530 if (oop_result->is_valid()) { 2531 get_vm_result(oop_result, java_thread); 2532 } 2533 } 2534 2535 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 2536 2537 // Calculate the value for last_Java_sp 2538 // somewhat subtle. call_VM does an intermediate call 2539 // which places a return address on the stack just under the 2540 // stack pointer as the user finsihed with it. This allows 2541 // use to retrieve last_Java_pc from last_Java_sp[-1]. 2542 // On 32bit we then have to push additional args on the stack to accomplish 2543 // the actual requested call. On 64bit call_VM only can use register args 2544 // so the only extra space is the return address that call_VM created. 2545 // This hopefully explains the calculations here. 2546 2547 #ifdef _LP64 2548 // We've pushed one address, correct last_Java_sp 2549 lea(rax, Address(rsp, wordSize)); 2550 #else 2551 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); 2552 #endif // LP64 2553 2554 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); 2555 2556 } 2557 2558 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 2559 call_VM_leaf_base(entry_point, number_of_arguments); 2560 } 2561 2562 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 2563 pass_arg0(this, arg_0); 2564 call_VM_leaf(entry_point, 1); 2565 } 2566 2567 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2568 2569 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2570 pass_arg1(this, arg_1); 2571 pass_arg0(this, arg_0); 2572 call_VM_leaf(entry_point, 2); 2573 } 2574 2575 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2576 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2577 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2578 pass_arg2(this, arg_2); 2579 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2580 pass_arg1(this, arg_1); 2581 pass_arg0(this, arg_0); 2582 call_VM_leaf(entry_point, 3); 2583 } 2584 2585 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 2586 pass_arg0(this, arg_0); 2587 MacroAssembler::call_VM_leaf_base(entry_point, 1); 2588 } 2589 2590 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2591 2592 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2593 pass_arg1(this, arg_1); 2594 pass_arg0(this, arg_0); 2595 MacroAssembler::call_VM_leaf_base(entry_point, 2); 2596 } 2597 2598 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2599 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2600 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2601 pass_arg2(this, arg_2); 2602 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2603 pass_arg1(this, arg_1); 2604 pass_arg0(this, arg_0); 2605 MacroAssembler::call_VM_leaf_base(entry_point, 3); 2606 } 2607 2608 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 2609 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); 2610 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2611 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2612 pass_arg3(this, arg_3); 2613 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2614 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2615 pass_arg2(this, arg_2); 2616 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2617 pass_arg1(this, arg_1); 2618 pass_arg0(this, arg_0); 2619 MacroAssembler::call_VM_leaf_base(entry_point, 4); 2620 } 2621 2622 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 2623 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 2624 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); 2625 verify_oop(oop_result, "broken oop in call_VM_base"); 2626 } 2627 2628 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 2629 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 2630 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); 2631 } 2632 2633 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { 2634 } 2635 2636 void MacroAssembler::check_and_handle_popframe(Register java_thread) { 2637 } 2638 2639 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { 2640 if (reachable(src1)) { 2641 cmpl(as_Address(src1), imm); 2642 } else { 2643 lea(rscratch1, src1); 2644 cmpl(Address(rscratch1, 0), imm); 2645 } 2646 } 2647 2648 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { 2649 assert(!src2.is_lval(), "use cmpptr"); 2650 if (reachable(src2)) { 2651 cmpl(src1, as_Address(src2)); 2652 } else { 2653 lea(rscratch1, src2); 2654 cmpl(src1, Address(rscratch1, 0)); 2655 } 2656 } 2657 2658 void MacroAssembler::cmp32(Register src1, int32_t imm) { 2659 Assembler::cmpl(src1, imm); 2660 } 2661 2662 void MacroAssembler::cmp32(Register src1, Address src2) { 2663 Assembler::cmpl(src1, src2); 2664 } 2665 2666 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2667 ucomisd(opr1, opr2); 2668 2669 Label L; 2670 if (unordered_is_less) { 2671 movl(dst, -1); 2672 jcc(Assembler::parity, L); 2673 jcc(Assembler::below , L); 2674 movl(dst, 0); 2675 jcc(Assembler::equal , L); 2676 increment(dst); 2677 } else { // unordered is greater 2678 movl(dst, 1); 2679 jcc(Assembler::parity, L); 2680 jcc(Assembler::above , L); 2681 movl(dst, 0); 2682 jcc(Assembler::equal , L); 2683 decrementl(dst); 2684 } 2685 bind(L); 2686 } 2687 2688 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2689 ucomiss(opr1, opr2); 2690 2691 Label L; 2692 if (unordered_is_less) { 2693 movl(dst, -1); 2694 jcc(Assembler::parity, L); 2695 jcc(Assembler::below , L); 2696 movl(dst, 0); 2697 jcc(Assembler::equal , L); 2698 increment(dst); 2699 } else { // unordered is greater 2700 movl(dst, 1); 2701 jcc(Assembler::parity, L); 2702 jcc(Assembler::above , L); 2703 movl(dst, 0); 2704 jcc(Assembler::equal , L); 2705 decrementl(dst); 2706 } 2707 bind(L); 2708 } 2709 2710 2711 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { 2712 if (reachable(src1)) { 2713 cmpb(as_Address(src1), imm); 2714 } else { 2715 lea(rscratch1, src1); 2716 cmpb(Address(rscratch1, 0), imm); 2717 } 2718 } 2719 2720 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { 2721 #ifdef _LP64 2722 if (src2.is_lval()) { 2723 movptr(rscratch1, src2); 2724 Assembler::cmpq(src1, rscratch1); 2725 } else if (reachable(src2)) { 2726 cmpq(src1, as_Address(src2)); 2727 } else { 2728 lea(rscratch1, src2); 2729 Assembler::cmpq(src1, Address(rscratch1, 0)); 2730 } 2731 #else 2732 if (src2.is_lval()) { 2733 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2734 } else { 2735 cmpl(src1, as_Address(src2)); 2736 } 2737 #endif // _LP64 2738 } 2739 2740 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { 2741 assert(src2.is_lval(), "not a mem-mem compare"); 2742 #ifdef _LP64 2743 // moves src2's literal address 2744 movptr(rscratch1, src2); 2745 Assembler::cmpq(src1, rscratch1); 2746 #else 2747 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2748 #endif // _LP64 2749 } 2750 2751 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { 2752 if (reachable(adr)) { 2753 if (os::is_MP()) 2754 lock(); 2755 cmpxchgptr(reg, as_Address(adr)); 2756 } else { 2757 lea(rscratch1, adr); 2758 if (os::is_MP()) 2759 lock(); 2760 cmpxchgptr(reg, Address(rscratch1, 0)); 2761 } 2762 } 2763 2764 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { 2765 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); 2766 } 2767 2768 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { 2769 if (reachable(src)) { 2770 Assembler::comisd(dst, as_Address(src)); 2771 } else { 2772 lea(rscratch1, src); 2773 Assembler::comisd(dst, Address(rscratch1, 0)); 2774 } 2775 } 2776 2777 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { 2778 if (reachable(src)) { 2779 Assembler::comiss(dst, as_Address(src)); 2780 } else { 2781 lea(rscratch1, src); 2782 Assembler::comiss(dst, Address(rscratch1, 0)); 2783 } 2784 } 2785 2786 2787 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { 2788 Condition negated_cond = negate_condition(cond); 2789 Label L; 2790 jcc(negated_cond, L); 2791 pushf(); // Preserve flags 2792 atomic_incl(counter_addr); 2793 popf(); 2794 bind(L); 2795 } 2796 2797 int MacroAssembler::corrected_idivl(Register reg) { 2798 // Full implementation of Java idiv and irem; checks for 2799 // special case as described in JVM spec., p.243 & p.271. 2800 // The function returns the (pc) offset of the idivl 2801 // instruction - may be needed for implicit exceptions. 2802 // 2803 // normal case special case 2804 // 2805 // input : rax,: dividend min_int 2806 // reg: divisor (may not be rax,/rdx) -1 2807 // 2808 // output: rax,: quotient (= rax, idiv reg) min_int 2809 // rdx: remainder (= rax, irem reg) 0 2810 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); 2811 const int min_int = 0x80000000; 2812 Label normal_case, special_case; 2813 2814 // check for special case 2815 cmpl(rax, min_int); 2816 jcc(Assembler::notEqual, normal_case); 2817 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) 2818 cmpl(reg, -1); 2819 jcc(Assembler::equal, special_case); 2820 2821 // handle normal case 2822 bind(normal_case); 2823 cdql(); 2824 int idivl_offset = offset(); 2825 idivl(reg); 2826 2827 // normal and special case exit 2828 bind(special_case); 2829 2830 return idivl_offset; 2831 } 2832 2833 2834 2835 void MacroAssembler::decrementl(Register reg, int value) { 2836 if (value == min_jint) {subl(reg, value) ; return; } 2837 if (value < 0) { incrementl(reg, -value); return; } 2838 if (value == 0) { ; return; } 2839 if (value == 1 && UseIncDec) { decl(reg) ; return; } 2840 /* else */ { subl(reg, value) ; return; } 2841 } 2842 2843 void MacroAssembler::decrementl(Address dst, int value) { 2844 if (value == min_jint) {subl(dst, value) ; return; } 2845 if (value < 0) { incrementl(dst, -value); return; } 2846 if (value == 0) { ; return; } 2847 if (value == 1 && UseIncDec) { decl(dst) ; return; } 2848 /* else */ { subl(dst, value) ; return; } 2849 } 2850 2851 void MacroAssembler::division_with_shift (Register reg, int shift_value) { 2852 assert (shift_value > 0, "illegal shift value"); 2853 Label _is_positive; 2854 testl (reg, reg); 2855 jcc (Assembler::positive, _is_positive); 2856 int offset = (1 << shift_value) - 1 ; 2857 2858 if (offset == 1) { 2859 incrementl(reg); 2860 } else { 2861 addl(reg, offset); 2862 } 2863 2864 bind (_is_positive); 2865 sarl(reg, shift_value); 2866 } 2867 2868 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { 2869 if (reachable(src)) { 2870 Assembler::divsd(dst, as_Address(src)); 2871 } else { 2872 lea(rscratch1, src); 2873 Assembler::divsd(dst, Address(rscratch1, 0)); 2874 } 2875 } 2876 2877 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { 2878 if (reachable(src)) { 2879 Assembler::divss(dst, as_Address(src)); 2880 } else { 2881 lea(rscratch1, src); 2882 Assembler::divss(dst, Address(rscratch1, 0)); 2883 } 2884 } 2885 2886 // !defined(COMPILER2) is because of stupid core builds 2887 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) 2888 void MacroAssembler::empty_FPU_stack() { 2889 if (VM_Version::supports_mmx()) { 2890 emms(); 2891 } else { 2892 for (int i = 8; i-- > 0; ) ffree(i); 2893 } 2894 } 2895 #endif // !LP64 || C1 || !C2 2896 2897 2898 // Defines obj, preserves var_size_in_bytes 2899 void MacroAssembler::eden_allocate(Register obj, 2900 Register var_size_in_bytes, 2901 int con_size_in_bytes, 2902 Register t1, 2903 Label& slow_case) { 2904 assert(obj == rax, "obj must be in rax, for cmpxchg"); 2905 assert_different_registers(obj, var_size_in_bytes, t1); 2906 if (!Universe::heap()->supports_inline_contig_alloc()) { 2907 jmp(slow_case); 2908 } else { 2909 Register end = t1; 2910 Label retry; 2911 bind(retry); 2912 ExternalAddress heap_top((address) Universe::heap()->top_addr()); 2913 movptr(obj, heap_top); 2914 if (var_size_in_bytes == noreg) { 2915 lea(end, Address(obj, con_size_in_bytes)); 2916 } else { 2917 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 2918 } 2919 // if end < obj then we wrapped around => object too long => slow case 2920 cmpptr(end, obj); 2921 jcc(Assembler::below, slow_case); 2922 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); 2923 jcc(Assembler::above, slow_case); 2924 // Compare obj with the top addr, and if still equal, store the new top addr in 2925 // end at the address of the top addr pointer. Sets ZF if was equal, and clears 2926 // it otherwise. Use lock prefix for atomicity on MPs. 2927 locked_cmpxchgptr(end, heap_top); 2928 jcc(Assembler::notEqual, retry); 2929 } 2930 } 2931 2932 void MacroAssembler::enter() { 2933 push(rbp); 2934 mov(rbp, rsp); 2935 } 2936 2937 // A 5 byte nop that is safe for patching (see patch_verified_entry) 2938 void MacroAssembler::fat_nop() { 2939 if (UseAddressNop) { 2940 addr_nop_5(); 2941 } else { 2942 emit_int8(0x26); // es: 2943 emit_int8(0x2e); // cs: 2944 emit_int8(0x64); // fs: 2945 emit_int8(0x65); // gs: 2946 emit_int8((unsigned char)0x90); 2947 } 2948 } 2949 2950 void MacroAssembler::fcmp(Register tmp) { 2951 fcmp(tmp, 1, true, true); 2952 } 2953 2954 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { 2955 assert(!pop_right || pop_left, "usage error"); 2956 if (VM_Version::supports_cmov()) { 2957 assert(tmp == noreg, "unneeded temp"); 2958 if (pop_left) { 2959 fucomip(index); 2960 } else { 2961 fucomi(index); 2962 } 2963 if (pop_right) { 2964 fpop(); 2965 } 2966 } else { 2967 assert(tmp != noreg, "need temp"); 2968 if (pop_left) { 2969 if (pop_right) { 2970 fcompp(); 2971 } else { 2972 fcomp(index); 2973 } 2974 } else { 2975 fcom(index); 2976 } 2977 // convert FPU condition into eflags condition via rax, 2978 save_rax(tmp); 2979 fwait(); fnstsw_ax(); 2980 sahf(); 2981 restore_rax(tmp); 2982 } 2983 // condition codes set as follows: 2984 // 2985 // CF (corresponds to C0) if x < y 2986 // PF (corresponds to C2) if unordered 2987 // ZF (corresponds to C3) if x = y 2988 } 2989 2990 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { 2991 fcmp2int(dst, unordered_is_less, 1, true, true); 2992 } 2993 2994 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { 2995 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); 2996 Label L; 2997 if (unordered_is_less) { 2998 movl(dst, -1); 2999 jcc(Assembler::parity, L); 3000 jcc(Assembler::below , L); 3001 movl(dst, 0); 3002 jcc(Assembler::equal , L); 3003 increment(dst); 3004 } else { // unordered is greater 3005 movl(dst, 1); 3006 jcc(Assembler::parity, L); 3007 jcc(Assembler::above , L); 3008 movl(dst, 0); 3009 jcc(Assembler::equal , L); 3010 decrementl(dst); 3011 } 3012 bind(L); 3013 } 3014 3015 void MacroAssembler::fld_d(AddressLiteral src) { 3016 fld_d(as_Address(src)); 3017 } 3018 3019 void MacroAssembler::fld_s(AddressLiteral src) { 3020 fld_s(as_Address(src)); 3021 } 3022 3023 void MacroAssembler::fld_x(AddressLiteral src) { 3024 Assembler::fld_x(as_Address(src)); 3025 } 3026 3027 void MacroAssembler::fldcw(AddressLiteral src) { 3028 Assembler::fldcw(as_Address(src)); 3029 } 3030 3031 void MacroAssembler::pow_exp_core_encoding() { 3032 // kills rax, rcx, rdx 3033 subptr(rsp,sizeof(jdouble)); 3034 // computes 2^X. Stack: X ... 3035 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and 3036 // keep it on the thread's stack to compute 2^int(X) later 3037 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1) 3038 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X)) 3039 fld_s(0); // Stack: X X ... 3040 frndint(); // Stack: int(X) X ... 3041 fsuba(1); // Stack: int(X) X-int(X) ... 3042 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ... 3043 f2xm1(); // Stack: 2^(X-int(X))-1 ... 3044 fld1(); // Stack: 1 2^(X-int(X))-1 ... 3045 faddp(1); // Stack: 2^(X-int(X)) 3046 // computes 2^(int(X)): add exponent bias (1023) to int(X), then 3047 // shift int(X)+1023 to exponent position. 3048 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11 3049 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent 3050 // values so detect them and set result to NaN. 3051 movl(rax,Address(rsp,0)); 3052 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding 3053 addl(rax, 1023); 3054 movl(rdx,rax); 3055 shll(rax,20); 3056 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN. 3057 addl(rdx,1); 3058 // Check that 1 < int(X)+1023+1 < 2048 3059 // in 3 steps: 3060 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048 3061 // 2- (int(X)+1023+1)&-2048 != 0 3062 // 3- (int(X)+1023+1)&-2048 != 1 3063 // Do 2- first because addl just updated the flags. 3064 cmov32(Assembler::equal,rax,rcx); 3065 cmpl(rdx,1); 3066 cmov32(Assembler::equal,rax,rcx); 3067 testl(rdx,rcx); 3068 cmov32(Assembler::notEqual,rax,rcx); 3069 movl(Address(rsp,4),rax); 3070 movl(Address(rsp,0),0); 3071 fmul_d(Address(rsp,0)); // Stack: 2^X ... 3072 addptr(rsp,sizeof(jdouble)); 3073 } 3074 3075 void MacroAssembler::increase_precision() { 3076 subptr(rsp, BytesPerWord); 3077 fnstcw(Address(rsp, 0)); 3078 movl(rax, Address(rsp, 0)); 3079 orl(rax, 0x300); 3080 push(rax); 3081 fldcw(Address(rsp, 0)); 3082 pop(rax); 3083 } 3084 3085 void MacroAssembler::restore_precision() { 3086 fldcw(Address(rsp, 0)); 3087 addptr(rsp, BytesPerWord); 3088 } 3089 3090 void MacroAssembler::fast_pow() { 3091 // computes X^Y = 2^(Y * log2(X)) 3092 // if fast computation is not possible, result is NaN. Requires 3093 // fallback from user of this macro. 3094 // increase precision for intermediate steps of the computation 3095 BLOCK_COMMENT("fast_pow {"); 3096 increase_precision(); 3097 fyl2x(); // Stack: (Y*log2(X)) ... 3098 pow_exp_core_encoding(); // Stack: exp(X) ... 3099 restore_precision(); 3100 BLOCK_COMMENT("} fast_pow"); 3101 } 3102 3103 void MacroAssembler::fast_exp() { 3104 // computes exp(X) = 2^(X * log2(e)) 3105 // if fast computation is not possible, result is NaN. Requires 3106 // fallback from user of this macro. 3107 // increase precision for intermediate steps of the computation 3108 increase_precision(); 3109 fldl2e(); // Stack: log2(e) X ... 3110 fmulp(1); // Stack: (X*log2(e)) ... 3111 pow_exp_core_encoding(); // Stack: exp(X) ... 3112 restore_precision(); 3113 } 3114 3115 void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) { 3116 // kills rax, rcx, rdx 3117 // pow and exp needs 2 extra registers on the fpu stack. 3118 Label slow_case, done; 3119 Register tmp = noreg; 3120 if (!VM_Version::supports_cmov()) { 3121 // fcmp needs a temporary so preserve rdx, 3122 tmp = rdx; 3123 } 3124 Register tmp2 = rax; 3125 Register tmp3 = rcx; 3126 3127 if (is_exp) { 3128 // Stack: X 3129 fld_s(0); // duplicate argument for runtime call. Stack: X X 3130 fast_exp(); // Stack: exp(X) X 3131 fcmp(tmp, 0, false, false); // Stack: exp(X) X 3132 // exp(X) not equal to itself: exp(X) is NaN go to slow case. 3133 jcc(Assembler::parity, slow_case); 3134 // get rid of duplicate argument. Stack: exp(X) 3135 if (num_fpu_regs_in_use > 0) { 3136 fxch(); 3137 fpop(); 3138 } else { 3139 ffree(1); 3140 } 3141 jmp(done); 3142 } else { 3143 // Stack: X Y 3144 Label x_negative, y_not_2; 3145 3146 static double two = 2.0; 3147 ExternalAddress two_addr((address)&two); 3148 3149 // constant maybe too far on 64 bit 3150 lea(tmp2, two_addr); 3151 fld_d(Address(tmp2, 0)); // Stack: 2 X Y 3152 fcmp(tmp, 2, true, false); // Stack: X Y 3153 jcc(Assembler::parity, y_not_2); 3154 jcc(Assembler::notEqual, y_not_2); 3155 3156 fxch(); fpop(); // Stack: X 3157 fmul(0); // Stack: X*X 3158 3159 jmp(done); 3160 3161 bind(y_not_2); 3162 3163 fldz(); // Stack: 0 X Y 3164 fcmp(tmp, 1, true, false); // Stack: X Y 3165 jcc(Assembler::above, x_negative); 3166 3167 // X >= 0 3168 3169 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y 3170 fld_s(1); // Stack: X Y X Y 3171 fast_pow(); // Stack: X^Y X Y 3172 fcmp(tmp, 0, false, false); // Stack: X^Y X Y 3173 // X^Y not equal to itself: X^Y is NaN go to slow case. 3174 jcc(Assembler::parity, slow_case); 3175 // get rid of duplicate arguments. Stack: X^Y 3176 if (num_fpu_regs_in_use > 0) { 3177 fxch(); fpop(); 3178 fxch(); fpop(); 3179 } else { 3180 ffree(2); 3181 ffree(1); 3182 } 3183 jmp(done); 3184 3185 // X <= 0 3186 bind(x_negative); 3187 3188 fld_s(1); // Stack: Y X Y 3189 frndint(); // Stack: int(Y) X Y 3190 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y 3191 jcc(Assembler::notEqual, slow_case); 3192 3193 subptr(rsp, 8); 3194 3195 // For X^Y, when X < 0, Y has to be an integer and the final 3196 // result depends on whether it's odd or even. We just checked 3197 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit 3198 // integer to test its parity. If int(Y) is huge and doesn't fit 3199 // in the 64 bit integer range, the integer indefinite value will 3200 // end up in the gp registers. Huge numbers are all even, the 3201 // integer indefinite number is even so it's fine. 3202 3203 #ifdef ASSERT 3204 // Let's check we don't end up with an integer indefinite number 3205 // when not expected. First test for huge numbers: check whether 3206 // int(Y)+1 == int(Y) which is true for very large numbers and 3207 // those are all even. A 64 bit integer is guaranteed to not 3208 // overflow for numbers where y+1 != y (when precision is set to 3209 // double precision). 3210 Label y_not_huge; 3211 3212 fld1(); // Stack: 1 int(Y) X Y 3213 fadd(1); // Stack: 1+int(Y) int(Y) X Y 3214 3215 #ifdef _LP64 3216 // trip to memory to force the precision down from double extended 3217 // precision 3218 fstp_d(Address(rsp, 0)); 3219 fld_d(Address(rsp, 0)); 3220 #endif 3221 3222 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y 3223 #endif 3224 3225 // move int(Y) as 64 bit integer to thread's stack 3226 fistp_d(Address(rsp,0)); // Stack: X Y 3227 3228 #ifdef ASSERT 3229 jcc(Assembler::notEqual, y_not_huge); 3230 3231 // Y is huge so we know it's even. It may not fit in a 64 bit 3232 // integer and we don't want the debug code below to see the 3233 // integer indefinite value so overwrite int(Y) on the thread's 3234 // stack with 0. 3235 movl(Address(rsp, 0), 0); 3236 movl(Address(rsp, 4), 0); 3237 3238 bind(y_not_huge); 3239 #endif 3240 3241 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y 3242 fld_s(1); // Stack: X Y X Y 3243 fabs(); // Stack: abs(X) Y X Y 3244 fast_pow(); // Stack: abs(X)^Y X Y 3245 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y 3246 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case. 3247 3248 pop(tmp2); 3249 NOT_LP64(pop(tmp3)); 3250 jcc(Assembler::parity, slow_case); 3251 3252 #ifdef ASSERT 3253 // Check that int(Y) is not integer indefinite value (int 3254 // overflow). Shouldn't happen because for values that would 3255 // overflow, 1+int(Y)==Y which was tested earlier. 3256 #ifndef _LP64 3257 { 3258 Label integer; 3259 testl(tmp2, tmp2); 3260 jcc(Assembler::notZero, integer); 3261 cmpl(tmp3, 0x80000000); 3262 jcc(Assembler::notZero, integer); 3263 STOP("integer indefinite value shouldn't be seen here"); 3264 bind(integer); 3265 } 3266 #else 3267 { 3268 Label integer; 3269 mov(tmp3, tmp2); // preserve tmp2 for parity check below 3270 shlq(tmp3, 1); 3271 jcc(Assembler::carryClear, integer); 3272 jcc(Assembler::notZero, integer); 3273 STOP("integer indefinite value shouldn't be seen here"); 3274 bind(integer); 3275 } 3276 #endif 3277 #endif 3278 3279 // get rid of duplicate arguments. Stack: X^Y 3280 if (num_fpu_regs_in_use > 0) { 3281 fxch(); fpop(); 3282 fxch(); fpop(); 3283 } else { 3284 ffree(2); 3285 ffree(1); 3286 } 3287 3288 testl(tmp2, 1); 3289 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y 3290 // X <= 0, Y even: X^Y = -abs(X)^Y 3291 3292 fchs(); // Stack: -abs(X)^Y Y 3293 jmp(done); 3294 } 3295 3296 // slow case: runtime call 3297 bind(slow_case); 3298 3299 fpop(); // pop incorrect result or int(Y) 3300 3301 fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow), 3302 is_exp ? 1 : 2, num_fpu_regs_in_use); 3303 3304 // Come here with result in F-TOS 3305 bind(done); 3306 } 3307 3308 void MacroAssembler::fpop() { 3309 ffree(); 3310 fincstp(); 3311 } 3312 3313 void MacroAssembler::fremr(Register tmp) { 3314 save_rax(tmp); 3315 { Label L; 3316 bind(L); 3317 fprem(); 3318 fwait(); fnstsw_ax(); 3319 #ifdef _LP64 3320 testl(rax, 0x400); 3321 jcc(Assembler::notEqual, L); 3322 #else 3323 sahf(); 3324 jcc(Assembler::parity, L); 3325 #endif // _LP64 3326 } 3327 restore_rax(tmp); 3328 // Result is in ST0. 3329 // Note: fxch & fpop to get rid of ST1 3330 // (otherwise FPU stack could overflow eventually) 3331 fxch(1); 3332 fpop(); 3333 } 3334 3335 3336 void MacroAssembler::incrementl(AddressLiteral dst) { 3337 if (reachable(dst)) { 3338 incrementl(as_Address(dst)); 3339 } else { 3340 lea(rscratch1, dst); 3341 incrementl(Address(rscratch1, 0)); 3342 } 3343 } 3344 3345 void MacroAssembler::incrementl(ArrayAddress dst) { 3346 incrementl(as_Address(dst)); 3347 } 3348 3349 void MacroAssembler::incrementl(Register reg, int value) { 3350 if (value == min_jint) {addl(reg, value) ; return; } 3351 if (value < 0) { decrementl(reg, -value); return; } 3352 if (value == 0) { ; return; } 3353 if (value == 1 && UseIncDec) { incl(reg) ; return; } 3354 /* else */ { addl(reg, value) ; return; } 3355 } 3356 3357 void MacroAssembler::incrementl(Address dst, int value) { 3358 if (value == min_jint) {addl(dst, value) ; return; } 3359 if (value < 0) { decrementl(dst, -value); return; } 3360 if (value == 0) { ; return; } 3361 if (value == 1 && UseIncDec) { incl(dst) ; return; } 3362 /* else */ { addl(dst, value) ; return; } 3363 } 3364 3365 void MacroAssembler::jump(AddressLiteral dst) { 3366 if (reachable(dst)) { 3367 jmp_literal(dst.target(), dst.rspec()); 3368 } else { 3369 lea(rscratch1, dst); 3370 jmp(rscratch1); 3371 } 3372 } 3373 3374 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { 3375 if (reachable(dst)) { 3376 InstructionMark im(this); 3377 relocate(dst.reloc()); 3378 const int short_size = 2; 3379 const int long_size = 6; 3380 int offs = (intptr_t)dst.target() - ((intptr_t)pc()); 3381 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { 3382 // 0111 tttn #8-bit disp 3383 emit_int8(0x70 | cc); 3384 emit_int8((offs - short_size) & 0xFF); 3385 } else { 3386 // 0000 1111 1000 tttn #32-bit disp 3387 emit_int8(0x0F); 3388 emit_int8((unsigned char)(0x80 | cc)); 3389 emit_int32(offs - long_size); 3390 } 3391 } else { 3392 #ifdef ASSERT 3393 warning("reversing conditional branch"); 3394 #endif /* ASSERT */ 3395 Label skip; 3396 jccb(reverse[cc], skip); 3397 lea(rscratch1, dst); 3398 Assembler::jmp(rscratch1); 3399 bind(skip); 3400 } 3401 } 3402 3403 void MacroAssembler::ldmxcsr(AddressLiteral src) { 3404 if (reachable(src)) { 3405 Assembler::ldmxcsr(as_Address(src)); 3406 } else { 3407 lea(rscratch1, src); 3408 Assembler::ldmxcsr(Address(rscratch1, 0)); 3409 } 3410 } 3411 3412 int MacroAssembler::load_signed_byte(Register dst, Address src) { 3413 int off; 3414 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3415 off = offset(); 3416 movsbl(dst, src); // movsxb 3417 } else { 3418 off = load_unsigned_byte(dst, src); 3419 shll(dst, 24); 3420 sarl(dst, 24); 3421 } 3422 return off; 3423 } 3424 3425 // Note: load_signed_short used to be called load_signed_word. 3426 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler 3427 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. 3428 // The term "word" in HotSpot means a 32- or 64-bit machine word. 3429 int MacroAssembler::load_signed_short(Register dst, Address src) { 3430 int off; 3431 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3432 // This is dubious to me since it seems safe to do a signed 16 => 64 bit 3433 // version but this is what 64bit has always done. This seems to imply 3434 // that users are only using 32bits worth. 3435 off = offset(); 3436 movswl(dst, src); // movsxw 3437 } else { 3438 off = load_unsigned_short(dst, src); 3439 shll(dst, 16); 3440 sarl(dst, 16); 3441 } 3442 return off; 3443 } 3444 3445 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 3446 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3447 // and "3.9 Partial Register Penalties", p. 22). 3448 int off; 3449 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { 3450 off = offset(); 3451 movzbl(dst, src); // movzxb 3452 } else { 3453 xorl(dst, dst); 3454 off = offset(); 3455 movb(dst, src); 3456 } 3457 return off; 3458 } 3459 3460 // Note: load_unsigned_short used to be called load_unsigned_word. 3461 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 3462 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3463 // and "3.9 Partial Register Penalties", p. 22). 3464 int off; 3465 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { 3466 off = offset(); 3467 movzwl(dst, src); // movzxw 3468 } else { 3469 xorl(dst, dst); 3470 off = offset(); 3471 movw(dst, src); 3472 } 3473 return off; 3474 } 3475 3476 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 3477 switch (size_in_bytes) { 3478 #ifndef _LP64 3479 case 8: 3480 assert(dst2 != noreg, "second dest register required"); 3481 movl(dst, src); 3482 movl(dst2, src.plus_disp(BytesPerInt)); 3483 break; 3484 #else 3485 case 8: movq(dst, src); break; 3486 #endif 3487 case 4: movl(dst, src); break; 3488 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 3489 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 3490 default: ShouldNotReachHere(); 3491 } 3492 } 3493 3494 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 3495 switch (size_in_bytes) { 3496 #ifndef _LP64 3497 case 8: 3498 assert(src2 != noreg, "second source register required"); 3499 movl(dst, src); 3500 movl(dst.plus_disp(BytesPerInt), src2); 3501 break; 3502 #else 3503 case 8: movq(dst, src); break; 3504 #endif 3505 case 4: movl(dst, src); break; 3506 case 2: movw(dst, src); break; 3507 case 1: movb(dst, src); break; 3508 default: ShouldNotReachHere(); 3509 } 3510 } 3511 3512 void MacroAssembler::mov32(AddressLiteral dst, Register src) { 3513 if (reachable(dst)) { 3514 movl(as_Address(dst), src); 3515 } else { 3516 lea(rscratch1, dst); 3517 movl(Address(rscratch1, 0), src); 3518 } 3519 } 3520 3521 void MacroAssembler::mov32(Register dst, AddressLiteral src) { 3522 if (reachable(src)) { 3523 movl(dst, as_Address(src)); 3524 } else { 3525 lea(rscratch1, src); 3526 movl(dst, Address(rscratch1, 0)); 3527 } 3528 } 3529 3530 // C++ bool manipulation 3531 3532 void MacroAssembler::movbool(Register dst, Address src) { 3533 if(sizeof(bool) == 1) 3534 movb(dst, src); 3535 else if(sizeof(bool) == 2) 3536 movw(dst, src); 3537 else if(sizeof(bool) == 4) 3538 movl(dst, src); 3539 else 3540 // unsupported 3541 ShouldNotReachHere(); 3542 } 3543 3544 void MacroAssembler::movbool(Address dst, bool boolconst) { 3545 if(sizeof(bool) == 1) 3546 movb(dst, (int) boolconst); 3547 else if(sizeof(bool) == 2) 3548 movw(dst, (int) boolconst); 3549 else if(sizeof(bool) == 4) 3550 movl(dst, (int) boolconst); 3551 else 3552 // unsupported 3553 ShouldNotReachHere(); 3554 } 3555 3556 void MacroAssembler::movbool(Address dst, Register src) { 3557 if(sizeof(bool) == 1) 3558 movb(dst, src); 3559 else if(sizeof(bool) == 2) 3560 movw(dst, src); 3561 else if(sizeof(bool) == 4) 3562 movl(dst, src); 3563 else 3564 // unsupported 3565 ShouldNotReachHere(); 3566 } 3567 3568 void MacroAssembler::movbyte(ArrayAddress dst, int src) { 3569 movb(as_Address(dst), src); 3570 } 3571 3572 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) { 3573 if (reachable(src)) { 3574 movdl(dst, as_Address(src)); 3575 } else { 3576 lea(rscratch1, src); 3577 movdl(dst, Address(rscratch1, 0)); 3578 } 3579 } 3580 3581 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) { 3582 if (reachable(src)) { 3583 movq(dst, as_Address(src)); 3584 } else { 3585 lea(rscratch1, src); 3586 movq(dst, Address(rscratch1, 0)); 3587 } 3588 } 3589 3590 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { 3591 if (reachable(src)) { 3592 if (UseXmmLoadAndClearUpper) { 3593 movsd (dst, as_Address(src)); 3594 } else { 3595 movlpd(dst, as_Address(src)); 3596 } 3597 } else { 3598 lea(rscratch1, src); 3599 if (UseXmmLoadAndClearUpper) { 3600 movsd (dst, Address(rscratch1, 0)); 3601 } else { 3602 movlpd(dst, Address(rscratch1, 0)); 3603 } 3604 } 3605 } 3606 3607 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { 3608 if (reachable(src)) { 3609 movss(dst, as_Address(src)); 3610 } else { 3611 lea(rscratch1, src); 3612 movss(dst, Address(rscratch1, 0)); 3613 } 3614 } 3615 3616 void MacroAssembler::movptr(Register dst, Register src) { 3617 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3618 } 3619 3620 void MacroAssembler::movptr(Register dst, Address src) { 3621 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3622 } 3623 3624 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 3625 void MacroAssembler::movptr(Register dst, intptr_t src) { 3626 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); 3627 } 3628 3629 void MacroAssembler::movptr(Address dst, Register src) { 3630 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3631 } 3632 3633 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) { 3634 if (reachable(src)) { 3635 Assembler::movdqu(dst, as_Address(src)); 3636 } else { 3637 lea(rscratch1, src); 3638 Assembler::movdqu(dst, Address(rscratch1, 0)); 3639 } 3640 } 3641 3642 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) { 3643 if (reachable(src)) { 3644 Assembler::movdqa(dst, as_Address(src)); 3645 } else { 3646 lea(rscratch1, src); 3647 Assembler::movdqa(dst, Address(rscratch1, 0)); 3648 } 3649 } 3650 3651 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { 3652 if (reachable(src)) { 3653 Assembler::movsd(dst, as_Address(src)); 3654 } else { 3655 lea(rscratch1, src); 3656 Assembler::movsd(dst, Address(rscratch1, 0)); 3657 } 3658 } 3659 3660 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { 3661 if (reachable(src)) { 3662 Assembler::movss(dst, as_Address(src)); 3663 } else { 3664 lea(rscratch1, src); 3665 Assembler::movss(dst, Address(rscratch1, 0)); 3666 } 3667 } 3668 3669 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { 3670 if (reachable(src)) { 3671 Assembler::mulsd(dst, as_Address(src)); 3672 } else { 3673 lea(rscratch1, src); 3674 Assembler::mulsd(dst, Address(rscratch1, 0)); 3675 } 3676 } 3677 3678 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { 3679 if (reachable(src)) { 3680 Assembler::mulss(dst, as_Address(src)); 3681 } else { 3682 lea(rscratch1, src); 3683 Assembler::mulss(dst, Address(rscratch1, 0)); 3684 } 3685 } 3686 3687 void MacroAssembler::null_check(Register reg, int offset) { 3688 if (needs_explicit_null_check(offset)) { 3689 // provoke OS NULL exception if reg = NULL by 3690 // accessing M[reg] w/o changing any (non-CC) registers 3691 // NOTE: cmpl is plenty here to provoke a segv 3692 cmpptr(rax, Address(reg, 0)); 3693 // Note: should probably use testl(rax, Address(reg, 0)); 3694 // may be shorter code (however, this version of 3695 // testl needs to be implemented first) 3696 } else { 3697 // nothing to do, (later) access of M[reg + offset] 3698 // will provoke OS NULL exception if reg = NULL 3699 } 3700 } 3701 3702 void MacroAssembler::os_breakpoint() { 3703 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability 3704 // (e.g., MSVC can't call ps() otherwise) 3705 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); 3706 } 3707 3708 void MacroAssembler::pop_CPU_state() { 3709 pop_FPU_state(); 3710 pop_IU_state(); 3711 } 3712 3713 void MacroAssembler::pop_FPU_state() { 3714 NOT_LP64(frstor(Address(rsp, 0));) 3715 LP64_ONLY(fxrstor(Address(rsp, 0));) 3716 addptr(rsp, FPUStateSizeInWords * wordSize); 3717 } 3718 3719 void MacroAssembler::pop_IU_state() { 3720 popa(); 3721 LP64_ONLY(addq(rsp, 8)); 3722 popf(); 3723 } 3724 3725 // Save Integer and Float state 3726 // Warning: Stack must be 16 byte aligned (64bit) 3727 void MacroAssembler::push_CPU_state() { 3728 push_IU_state(); 3729 push_FPU_state(); 3730 } 3731 3732 void MacroAssembler::push_FPU_state() { 3733 subptr(rsp, FPUStateSizeInWords * wordSize); 3734 #ifndef _LP64 3735 fnsave(Address(rsp, 0)); 3736 fwait(); 3737 #else 3738 fxsave(Address(rsp, 0)); 3739 #endif // LP64 3740 } 3741 3742 void MacroAssembler::push_IU_state() { 3743 // Push flags first because pusha kills them 3744 pushf(); 3745 // Make sure rsp stays 16-byte aligned 3746 LP64_ONLY(subq(rsp, 8)); 3747 pusha(); 3748 } 3749 3750 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { 3751 // determine java_thread register 3752 if (!java_thread->is_valid()) { 3753 java_thread = rdi; 3754 get_thread(java_thread); 3755 } 3756 // we must set sp to zero to clear frame 3757 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 3758 if (clear_fp) { 3759 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 3760 } 3761 3762 if (clear_pc) 3763 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 3764 3765 } 3766 3767 void MacroAssembler::restore_rax(Register tmp) { 3768 if (tmp == noreg) pop(rax); 3769 else if (tmp != rax) mov(rax, tmp); 3770 } 3771 3772 void MacroAssembler::round_to(Register reg, int modulus) { 3773 addptr(reg, modulus - 1); 3774 andptr(reg, -modulus); 3775 } 3776 3777 void MacroAssembler::save_rax(Register tmp) { 3778 if (tmp == noreg) push(rax); 3779 else if (tmp != rax) mov(tmp, rax); 3780 } 3781 3782 // Write serialization page so VM thread can do a pseudo remote membar. 3783 // We use the current thread pointer to calculate a thread specific 3784 // offset to write to within the page. This minimizes bus traffic 3785 // due to cache line collision. 3786 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 3787 movl(tmp, thread); 3788 shrl(tmp, os::get_serialize_page_shift_count()); 3789 andl(tmp, (os::vm_page_size() - sizeof(int))); 3790 3791 Address index(noreg, tmp, Address::times_1); 3792 ExternalAddress page(os::get_memory_serialize_page()); 3793 3794 // Size of store must match masking code above 3795 movl(as_Address(ArrayAddress(page, index)), tmp); 3796 } 3797 3798 // Calls to C land 3799 // 3800 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded 3801 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 3802 // has to be reset to 0. This is required to allow proper stack traversal. 3803 void MacroAssembler::set_last_Java_frame(Register java_thread, 3804 Register last_java_sp, 3805 Register last_java_fp, 3806 address last_java_pc) { 3807 // determine java_thread register 3808 if (!java_thread->is_valid()) { 3809 java_thread = rdi; 3810 get_thread(java_thread); 3811 } 3812 // determine last_java_sp register 3813 if (!last_java_sp->is_valid()) { 3814 last_java_sp = rsp; 3815 } 3816 3817 // last_java_fp is optional 3818 3819 if (last_java_fp->is_valid()) { 3820 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); 3821 } 3822 3823 // last_java_pc is optional 3824 3825 if (last_java_pc != NULL) { 3826 lea(Address(java_thread, 3827 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), 3828 InternalAddress(last_java_pc)); 3829 3830 } 3831 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 3832 } 3833 3834 void MacroAssembler::shlptr(Register dst, int imm8) { 3835 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); 3836 } 3837 3838 void MacroAssembler::shrptr(Register dst, int imm8) { 3839 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); 3840 } 3841 3842 void MacroAssembler::sign_extend_byte(Register reg) { 3843 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { 3844 movsbl(reg, reg); // movsxb 3845 } else { 3846 shll(reg, 24); 3847 sarl(reg, 24); 3848 } 3849 } 3850 3851 void MacroAssembler::sign_extend_short(Register reg) { 3852 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3853 movswl(reg, reg); // movsxw 3854 } else { 3855 shll(reg, 16); 3856 sarl(reg, 16); 3857 } 3858 } 3859 3860 void MacroAssembler::testl(Register dst, AddressLiteral src) { 3861 assert(reachable(src), "Address should be reachable"); 3862 testl(dst, as_Address(src)); 3863 } 3864 3865 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { 3866 if (reachable(src)) { 3867 Assembler::sqrtsd(dst, as_Address(src)); 3868 } else { 3869 lea(rscratch1, src); 3870 Assembler::sqrtsd(dst, Address(rscratch1, 0)); 3871 } 3872 } 3873 3874 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { 3875 if (reachable(src)) { 3876 Assembler::sqrtss(dst, as_Address(src)); 3877 } else { 3878 lea(rscratch1, src); 3879 Assembler::sqrtss(dst, Address(rscratch1, 0)); 3880 } 3881 } 3882 3883 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { 3884 if (reachable(src)) { 3885 Assembler::subsd(dst, as_Address(src)); 3886 } else { 3887 lea(rscratch1, src); 3888 Assembler::subsd(dst, Address(rscratch1, 0)); 3889 } 3890 } 3891 3892 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { 3893 if (reachable(src)) { 3894 Assembler::subss(dst, as_Address(src)); 3895 } else { 3896 lea(rscratch1, src); 3897 Assembler::subss(dst, Address(rscratch1, 0)); 3898 } 3899 } 3900 3901 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { 3902 if (reachable(src)) { 3903 Assembler::ucomisd(dst, as_Address(src)); 3904 } else { 3905 lea(rscratch1, src); 3906 Assembler::ucomisd(dst, Address(rscratch1, 0)); 3907 } 3908 } 3909 3910 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { 3911 if (reachable(src)) { 3912 Assembler::ucomiss(dst, as_Address(src)); 3913 } else { 3914 lea(rscratch1, src); 3915 Assembler::ucomiss(dst, Address(rscratch1, 0)); 3916 } 3917 } 3918 3919 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { 3920 // Used in sign-bit flipping with aligned address. 3921 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 3922 if (reachable(src)) { 3923 Assembler::xorpd(dst, as_Address(src)); 3924 } else { 3925 lea(rscratch1, src); 3926 Assembler::xorpd(dst, Address(rscratch1, 0)); 3927 } 3928 } 3929 3930 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { 3931 // Used in sign-bit flipping with aligned address. 3932 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 3933 if (reachable(src)) { 3934 Assembler::xorps(dst, as_Address(src)); 3935 } else { 3936 lea(rscratch1, src); 3937 Assembler::xorps(dst, Address(rscratch1, 0)); 3938 } 3939 } 3940 3941 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) { 3942 // Used in sign-bit flipping with aligned address. 3943 bool aligned_adr = (((intptr_t)src.target() & 15) == 0); 3944 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); 3945 if (reachable(src)) { 3946 Assembler::pshufb(dst, as_Address(src)); 3947 } else { 3948 lea(rscratch1, src); 3949 Assembler::pshufb(dst, Address(rscratch1, 0)); 3950 } 3951 } 3952 3953 // AVX 3-operands instructions 3954 3955 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3956 if (reachable(src)) { 3957 vaddsd(dst, nds, as_Address(src)); 3958 } else { 3959 lea(rscratch1, src); 3960 vaddsd(dst, nds, Address(rscratch1, 0)); 3961 } 3962 } 3963 3964 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3965 if (reachable(src)) { 3966 vaddss(dst, nds, as_Address(src)); 3967 } else { 3968 lea(rscratch1, src); 3969 vaddss(dst, nds, Address(rscratch1, 0)); 3970 } 3971 } 3972 3973 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 3974 if (reachable(src)) { 3975 vandpd(dst, nds, as_Address(src), vector_len); 3976 } else { 3977 lea(rscratch1, src); 3978 vandpd(dst, nds, Address(rscratch1, 0), vector_len); 3979 } 3980 } 3981 3982 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 3983 if (reachable(src)) { 3984 vandps(dst, nds, as_Address(src), vector_len); 3985 } else { 3986 lea(rscratch1, src); 3987 vandps(dst, nds, Address(rscratch1, 0), vector_len); 3988 } 3989 } 3990 3991 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3992 if (reachable(src)) { 3993 vdivsd(dst, nds, as_Address(src)); 3994 } else { 3995 lea(rscratch1, src); 3996 vdivsd(dst, nds, Address(rscratch1, 0)); 3997 } 3998 } 3999 4000 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4001 if (reachable(src)) { 4002 vdivss(dst, nds, as_Address(src)); 4003 } else { 4004 lea(rscratch1, src); 4005 vdivss(dst, nds, Address(rscratch1, 0)); 4006 } 4007 } 4008 4009 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4010 if (reachable(src)) { 4011 vmulsd(dst, nds, as_Address(src)); 4012 } else { 4013 lea(rscratch1, src); 4014 vmulsd(dst, nds, Address(rscratch1, 0)); 4015 } 4016 } 4017 4018 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4019 if (reachable(src)) { 4020 vmulss(dst, nds, as_Address(src)); 4021 } else { 4022 lea(rscratch1, src); 4023 vmulss(dst, nds, Address(rscratch1, 0)); 4024 } 4025 } 4026 4027 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4028 if (reachable(src)) { 4029 vsubsd(dst, nds, as_Address(src)); 4030 } else { 4031 lea(rscratch1, src); 4032 vsubsd(dst, nds, Address(rscratch1, 0)); 4033 } 4034 } 4035 4036 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4037 if (reachable(src)) { 4038 vsubss(dst, nds, as_Address(src)); 4039 } else { 4040 lea(rscratch1, src); 4041 vsubss(dst, nds, Address(rscratch1, 0)); 4042 } 4043 } 4044 4045 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4046 if (reachable(src)) { 4047 vxorpd(dst, nds, as_Address(src), vector_len); 4048 } else { 4049 lea(rscratch1, src); 4050 vxorpd(dst, nds, Address(rscratch1, 0), vector_len); 4051 } 4052 } 4053 4054 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4055 if (reachable(src)) { 4056 vxorps(dst, nds, as_Address(src), vector_len); 4057 } else { 4058 lea(rscratch1, src); 4059 vxorps(dst, nds, Address(rscratch1, 0), vector_len); 4060 } 4061 } 4062 4063 4064 ////////////////////////////////////////////////////////////////////////////////// 4065 #if INCLUDE_ALL_GCS 4066 4067 void MacroAssembler::g1_write_barrier_pre(Register obj, 4068 Register pre_val, 4069 Register thread, 4070 Register tmp, 4071 bool tosca_live, 4072 bool expand_call) { 4073 4074 // If expand_call is true then we expand the call_VM_leaf macro 4075 // directly to skip generating the check by 4076 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. 4077 4078 #ifdef _LP64 4079 assert(thread == r15_thread, "must be"); 4080 #endif // _LP64 4081 4082 Label done; 4083 Label runtime; 4084 4085 assert(pre_val != noreg, "check this code"); 4086 4087 if (obj != noreg) { 4088 assert_different_registers(obj, pre_val, tmp); 4089 assert(pre_val != rax, "check this code"); 4090 } 4091 4092 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 4093 PtrQueue::byte_offset_of_active())); 4094 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 4095 PtrQueue::byte_offset_of_index())); 4096 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 4097 PtrQueue::byte_offset_of_buf())); 4098 4099 4100 // Is marking active? 4101 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { 4102 cmpl(in_progress, 0); 4103 } else { 4104 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); 4105 cmpb(in_progress, 0); 4106 } 4107 jcc(Assembler::equal, done); 4108 4109 // Do we need to load the previous value? 4110 if (obj != noreg) { 4111 load_heap_oop(pre_val, Address(obj, 0)); 4112 } 4113 4114 // Is the previous value null? 4115 cmpptr(pre_val, (int32_t) NULL_WORD); 4116 jcc(Assembler::equal, done); 4117 4118 // Can we store original value in the thread's buffer? 4119 // Is index == 0? 4120 // (The index field is typed as size_t.) 4121 4122 movptr(tmp, index); // tmp := *index_adr 4123 cmpptr(tmp, 0); // tmp == 0? 4124 jcc(Assembler::equal, runtime); // If yes, goto runtime 4125 4126 subptr(tmp, wordSize); // tmp := tmp - wordSize 4127 movptr(index, tmp); // *index_adr := tmp 4128 addptr(tmp, buffer); // tmp := tmp + *buffer_adr 4129 4130 // Record the previous value 4131 movptr(Address(tmp, 0), pre_val); 4132 jmp(done); 4133 4134 bind(runtime); 4135 // save the live input values 4136 if(tosca_live) push(rax); 4137 4138 if (obj != noreg && obj != rax) 4139 push(obj); 4140 4141 if (pre_val != rax) 4142 push(pre_val); 4143 4144 // Calling the runtime using the regular call_VM_leaf mechanism generates 4145 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) 4146 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. 4147 // 4148 // If we care generating the pre-barrier without a frame (e.g. in the 4149 // intrinsified Reference.get() routine) then ebp might be pointing to 4150 // the caller frame and so this check will most likely fail at runtime. 4151 // 4152 // Expanding the call directly bypasses the generation of the check. 4153 // So when we do not have have a full interpreter frame on the stack 4154 // expand_call should be passed true. 4155 4156 NOT_LP64( push(thread); ) 4157 4158 if (expand_call) { 4159 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) 4160 pass_arg1(this, thread); 4161 pass_arg0(this, pre_val); 4162 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); 4163 } else { 4164 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); 4165 } 4166 4167 NOT_LP64( pop(thread); ) 4168 4169 // save the live input values 4170 if (pre_val != rax) 4171 pop(pre_val); 4172 4173 if (obj != noreg && obj != rax) 4174 pop(obj); 4175 4176 if(tosca_live) pop(rax); 4177 4178 bind(done); 4179 } 4180 4181 void MacroAssembler::g1_write_barrier_post(Register store_addr, 4182 Register new_val, 4183 Register thread, 4184 Register tmp, 4185 Register tmp2) { 4186 #ifdef _LP64 4187 assert(thread == r15_thread, "must be"); 4188 #endif // _LP64 4189 4190 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 4191 PtrQueue::byte_offset_of_index())); 4192 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 4193 PtrQueue::byte_offset_of_buf())); 4194 4195 CardTableModRefBS* ct = 4196 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set()); 4197 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 4198 4199 Label done; 4200 Label runtime; 4201 4202 // Does store cross heap regions? 4203 4204 movptr(tmp, store_addr); 4205 xorptr(tmp, new_val); 4206 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); 4207 jcc(Assembler::equal, done); 4208 4209 // crosses regions, storing NULL? 4210 4211 cmpptr(new_val, (int32_t) NULL_WORD); 4212 jcc(Assembler::equal, done); 4213 4214 // storing region crossing non-NULL, is card already dirty? 4215 4216 const Register card_addr = tmp; 4217 const Register cardtable = tmp2; 4218 4219 movptr(card_addr, store_addr); 4220 shrptr(card_addr, CardTableModRefBS::card_shift); 4221 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT 4222 // a valid address and therefore is not properly handled by the relocation code. 4223 movptr(cardtable, (intptr_t)ct->byte_map_base); 4224 addptr(card_addr, cardtable); 4225 4226 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val()); 4227 jcc(Assembler::equal, done); 4228 4229 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 4230 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 4231 jcc(Assembler::equal, done); 4232 4233 4234 // storing a region crossing, non-NULL oop, card is clean. 4235 // dirty card and log. 4236 4237 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 4238 4239 cmpl(queue_index, 0); 4240 jcc(Assembler::equal, runtime); 4241 subl(queue_index, wordSize); 4242 movptr(tmp2, buffer); 4243 #ifdef _LP64 4244 movslq(rscratch1, queue_index); 4245 addq(tmp2, rscratch1); 4246 movq(Address(tmp2, 0), card_addr); 4247 #else 4248 addl(tmp2, queue_index); 4249 movl(Address(tmp2, 0), card_addr); 4250 #endif 4251 jmp(done); 4252 4253 bind(runtime); 4254 // save the live input values 4255 push(store_addr); 4256 push(new_val); 4257 #ifdef _LP64 4258 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); 4259 #else 4260 push(thread); 4261 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 4262 pop(thread); 4263 #endif 4264 pop(new_val); 4265 pop(store_addr); 4266 4267 bind(done); 4268 } 4269 4270 #endif // INCLUDE_ALL_GCS 4271 ////////////////////////////////////////////////////////////////////////////////// 4272 4273 4274 void MacroAssembler::store_check(Register obj, Address dst) { 4275 store_check(obj); 4276 } 4277 4278 void MacroAssembler::store_check(Register obj) { 4279 // Does a store check for the oop in register obj. The content of 4280 // register obj is destroyed afterwards. 4281 4282 BarrierSet* bs = Universe::heap()->barrier_set(); 4283 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); 4284 4285 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs); 4286 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 4287 4288 shrptr(obj, CardTableModRefBS::card_shift); 4289 4290 Address card_addr; 4291 4292 // The calculation for byte_map_base is as follows: 4293 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); 4294 // So this essentially converts an address to a displacement and it will 4295 // never need to be relocated. On 64bit however the value may be too 4296 // large for a 32bit displacement. 4297 intptr_t disp = (intptr_t) ct->byte_map_base; 4298 if (is_simm32(disp)) { 4299 card_addr = Address(noreg, obj, Address::times_1, disp); 4300 } else { 4301 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative 4302 // displacement and done in a single instruction given favorable mapping and a 4303 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation 4304 // entry and that entry is not properly handled by the relocation code. 4305 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none); 4306 Address index(noreg, obj, Address::times_1); 4307 card_addr = as_Address(ArrayAddress(cardtable, index)); 4308 } 4309 4310 int dirty = CardTableModRefBS::dirty_card_val(); 4311 if (UseCondCardMark) { 4312 Label L_already_dirty; 4313 if (UseConcMarkSweepGC) { 4314 membar(Assembler::StoreLoad); 4315 } 4316 cmpb(card_addr, dirty); 4317 jcc(Assembler::equal, L_already_dirty); 4318 movb(card_addr, dirty); 4319 bind(L_already_dirty); 4320 } else { 4321 movb(card_addr, dirty); 4322 } 4323 } 4324 4325 void MacroAssembler::subptr(Register dst, int32_t imm32) { 4326 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); 4327 } 4328 4329 // Force generation of a 4 byte immediate value even if it fits into 8bit 4330 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { 4331 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); 4332 } 4333 4334 void MacroAssembler::subptr(Register dst, Register src) { 4335 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); 4336 } 4337 4338 // C++ bool manipulation 4339 void MacroAssembler::testbool(Register dst) { 4340 if(sizeof(bool) == 1) 4341 testb(dst, 0xff); 4342 else if(sizeof(bool) == 2) { 4343 // testw implementation needed for two byte bools 4344 ShouldNotReachHere(); 4345 } else if(sizeof(bool) == 4) 4346 testl(dst, dst); 4347 else 4348 // unsupported 4349 ShouldNotReachHere(); 4350 } 4351 4352 void MacroAssembler::testptr(Register dst, Register src) { 4353 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); 4354 } 4355 4356 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 4357 void MacroAssembler::tlab_allocate(Register obj, 4358 Register var_size_in_bytes, 4359 int con_size_in_bytes, 4360 Register t1, 4361 Register t2, 4362 Label& slow_case) { 4363 assert_different_registers(obj, t1, t2); 4364 assert_different_registers(obj, var_size_in_bytes, t1); 4365 Register end = t2; 4366 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); 4367 4368 verify_tlab(); 4369 4370 NOT_LP64(get_thread(thread)); 4371 4372 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); 4373 if (var_size_in_bytes == noreg) { 4374 lea(end, Address(obj, con_size_in_bytes)); 4375 } else { 4376 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 4377 } 4378 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); 4379 jcc(Assembler::above, slow_case); 4380 4381 // update the tlab top pointer 4382 movptr(Address(thread, JavaThread::tlab_top_offset()), end); 4383 4384 // recover var_size_in_bytes if necessary 4385 if (var_size_in_bytes == end) { 4386 subptr(var_size_in_bytes, obj); 4387 } 4388 verify_tlab(); 4389 } 4390 4391 // Preserves rbx, and rdx. 4392 Register MacroAssembler::tlab_refill(Label& retry, 4393 Label& try_eden, 4394 Label& slow_case) { 4395 Register top = rax; 4396 Register t1 = rcx; 4397 Register t2 = rsi; 4398 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); 4399 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); 4400 Label do_refill, discard_tlab; 4401 4402 if (!Universe::heap()->supports_inline_contig_alloc()) { 4403 // No allocation in the shared eden. 4404 jmp(slow_case); 4405 } 4406 4407 NOT_LP64(get_thread(thread_reg)); 4408 4409 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 4410 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 4411 4412 // calculate amount of free space 4413 subptr(t1, top); 4414 shrptr(t1, LogHeapWordSize); 4415 4416 // Retain tlab and allocate object in shared space if 4417 // the amount free in the tlab is too large to discard. 4418 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 4419 jcc(Assembler::lessEqual, discard_tlab); 4420 4421 // Retain 4422 // %%% yuck as movptr... 4423 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); 4424 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); 4425 if (TLABStats) { 4426 // increment number of slow_allocations 4427 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); 4428 } 4429 jmp(try_eden); 4430 4431 bind(discard_tlab); 4432 if (TLABStats) { 4433 // increment number of refills 4434 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); 4435 // accumulate wastage -- t1 is amount free in tlab 4436 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); 4437 } 4438 4439 // if tlab is currently allocated (top or end != null) then 4440 // fill [top, end + alignment_reserve) with array object 4441 testptr(top, top); 4442 jcc(Assembler::zero, do_refill); 4443 4444 // set up the mark word 4445 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); 4446 // set the length to the remaining space 4447 subptr(t1, typeArrayOopDesc::header_size(T_INT)); 4448 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); 4449 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); 4450 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); 4451 // set klass to intArrayKlass 4452 // dubious reloc why not an oop reloc? 4453 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); 4454 // store klass last. concurrent gcs assumes klass length is valid if 4455 // klass field is not null. 4456 store_klass(top, t1); 4457 4458 movptr(t1, top); 4459 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 4460 incr_allocated_bytes(thread_reg, t1, 0); 4461 4462 // refill the tlab with an eden allocation 4463 bind(do_refill); 4464 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 4465 shlptr(t1, LogHeapWordSize); 4466 // allocate new tlab, address returned in top 4467 eden_allocate(top, t1, 0, t2, slow_case); 4468 4469 // Check that t1 was preserved in eden_allocate. 4470 #ifdef ASSERT 4471 if (UseTLAB) { 4472 Label ok; 4473 Register tsize = rsi; 4474 assert_different_registers(tsize, thread_reg, t1); 4475 push(tsize); 4476 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 4477 shlptr(tsize, LogHeapWordSize); 4478 cmpptr(t1, tsize); 4479 jcc(Assembler::equal, ok); 4480 STOP("assert(t1 != tlab size)"); 4481 should_not_reach_here(); 4482 4483 bind(ok); 4484 pop(tsize); 4485 } 4486 #endif 4487 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); 4488 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); 4489 addptr(top, t1); 4490 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); 4491 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); 4492 verify_tlab(); 4493 jmp(retry); 4494 4495 return thread_reg; // for use by caller 4496 } 4497 4498 void MacroAssembler::incr_allocated_bytes(Register thread, 4499 Register var_size_in_bytes, 4500 int con_size_in_bytes, 4501 Register t1) { 4502 if (!thread->is_valid()) { 4503 #ifdef _LP64 4504 thread = r15_thread; 4505 #else 4506 assert(t1->is_valid(), "need temp reg"); 4507 thread = t1; 4508 get_thread(thread); 4509 #endif 4510 } 4511 4512 #ifdef _LP64 4513 if (var_size_in_bytes->is_valid()) { 4514 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 4515 } else { 4516 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 4517 } 4518 #else 4519 if (var_size_in_bytes->is_valid()) { 4520 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 4521 } else { 4522 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 4523 } 4524 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); 4525 #endif 4526 } 4527 4528 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) { 4529 pusha(); 4530 4531 // if we are coming from c1, xmm registers may be live 4532 int off = 0; 4533 if (UseSSE == 1) { 4534 subptr(rsp, sizeof(jdouble)*8); 4535 movflt(Address(rsp,off++*sizeof(jdouble)),xmm0); 4536 movflt(Address(rsp,off++*sizeof(jdouble)),xmm1); 4537 movflt(Address(rsp,off++*sizeof(jdouble)),xmm2); 4538 movflt(Address(rsp,off++*sizeof(jdouble)),xmm3); 4539 movflt(Address(rsp,off++*sizeof(jdouble)),xmm4); 4540 movflt(Address(rsp,off++*sizeof(jdouble)),xmm5); 4541 movflt(Address(rsp,off++*sizeof(jdouble)),xmm6); 4542 movflt(Address(rsp,off++*sizeof(jdouble)),xmm7); 4543 } else if (UseSSE >= 2) { 4544 if (UseAVX > 2) { 4545 movl(rbx, 0xffff); 4546 #ifdef _LP64 4547 kmovql(k1, rbx); 4548 #else 4549 kmovdl(k1, rbx); 4550 #endif 4551 } 4552 #ifdef COMPILER2 4553 if (MaxVectorSize > 16) { 4554 assert(UseAVX > 0, "256bit vectors are supported only with AVX"); 4555 // Save upper half of YMM registes 4556 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); 4557 vextractf128h(Address(rsp, 0),xmm0); 4558 vextractf128h(Address(rsp, 16),xmm1); 4559 vextractf128h(Address(rsp, 32),xmm2); 4560 vextractf128h(Address(rsp, 48),xmm3); 4561 vextractf128h(Address(rsp, 64),xmm4); 4562 vextractf128h(Address(rsp, 80),xmm5); 4563 vextractf128h(Address(rsp, 96),xmm6); 4564 vextractf128h(Address(rsp,112),xmm7); 4565 #ifdef _LP64 4566 vextractf128h(Address(rsp,128),xmm8); 4567 vextractf128h(Address(rsp,144),xmm9); 4568 vextractf128h(Address(rsp,160),xmm10); 4569 vextractf128h(Address(rsp,176),xmm11); 4570 vextractf128h(Address(rsp,192),xmm12); 4571 vextractf128h(Address(rsp,208),xmm13); 4572 vextractf128h(Address(rsp,224),xmm14); 4573 vextractf128h(Address(rsp,240),xmm15); 4574 #endif 4575 } 4576 #endif 4577 // Save whole 128bit (16 bytes) XMM regiters 4578 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); 4579 movdqu(Address(rsp,off++*16),xmm0); 4580 movdqu(Address(rsp,off++*16),xmm1); 4581 movdqu(Address(rsp,off++*16),xmm2); 4582 movdqu(Address(rsp,off++*16),xmm3); 4583 movdqu(Address(rsp,off++*16),xmm4); 4584 movdqu(Address(rsp,off++*16),xmm5); 4585 movdqu(Address(rsp,off++*16),xmm6); 4586 movdqu(Address(rsp,off++*16),xmm7); 4587 #ifdef _LP64 4588 movdqu(Address(rsp,off++*16),xmm8); 4589 movdqu(Address(rsp,off++*16),xmm9); 4590 movdqu(Address(rsp,off++*16),xmm10); 4591 movdqu(Address(rsp,off++*16),xmm11); 4592 movdqu(Address(rsp,off++*16),xmm12); 4593 movdqu(Address(rsp,off++*16),xmm13); 4594 movdqu(Address(rsp,off++*16),xmm14); 4595 movdqu(Address(rsp,off++*16),xmm15); 4596 #endif 4597 } 4598 4599 // Preserve registers across runtime call 4600 int incoming_argument_and_return_value_offset = -1; 4601 if (num_fpu_regs_in_use > 1) { 4602 // Must preserve all other FPU regs (could alternatively convert 4603 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash 4604 // FPU state, but can not trust C compiler) 4605 NEEDS_CLEANUP; 4606 // NOTE that in this case we also push the incoming argument(s) to 4607 // the stack and restore it later; we also use this stack slot to 4608 // hold the return value from dsin, dcos etc. 4609 for (int i = 0; i < num_fpu_regs_in_use; i++) { 4610 subptr(rsp, sizeof(jdouble)); 4611 fstp_d(Address(rsp, 0)); 4612 } 4613 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); 4614 for (int i = nb_args-1; i >= 0; i--) { 4615 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble))); 4616 } 4617 } 4618 4619 subptr(rsp, nb_args*sizeof(jdouble)); 4620 for (int i = 0; i < nb_args; i++) { 4621 fstp_d(Address(rsp, i*sizeof(jdouble))); 4622 } 4623 4624 #ifdef _LP64 4625 if (nb_args > 0) { 4626 movdbl(xmm0, Address(rsp, 0)); 4627 } 4628 if (nb_args > 1) { 4629 movdbl(xmm1, Address(rsp, sizeof(jdouble))); 4630 } 4631 assert(nb_args <= 2, "unsupported number of args"); 4632 #endif // _LP64 4633 4634 // NOTE: we must not use call_VM_leaf here because that requires a 4635 // complete interpreter frame in debug mode -- same bug as 4387334 4636 // MacroAssembler::call_VM_leaf_base is perfectly safe and will 4637 // do proper 64bit abi 4638 4639 NEEDS_CLEANUP; 4640 // Need to add stack banging before this runtime call if it needs to 4641 // be taken; however, there is no generic stack banging routine at 4642 // the MacroAssembler level 4643 4644 MacroAssembler::call_VM_leaf_base(runtime_entry, 0); 4645 4646 #ifdef _LP64 4647 movsd(Address(rsp, 0), xmm0); 4648 fld_d(Address(rsp, 0)); 4649 #endif // _LP64 4650 addptr(rsp, sizeof(jdouble) * nb_args); 4651 if (num_fpu_regs_in_use > 1) { 4652 // Must save return value to stack and then restore entire FPU 4653 // stack except incoming arguments 4654 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); 4655 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) { 4656 fld_d(Address(rsp, 0)); 4657 addptr(rsp, sizeof(jdouble)); 4658 } 4659 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble))); 4660 addptr(rsp, sizeof(jdouble) * nb_args); 4661 } 4662 4663 off = 0; 4664 if (UseSSE == 1) { 4665 movflt(xmm0, Address(rsp,off++*sizeof(jdouble))); 4666 movflt(xmm1, Address(rsp,off++*sizeof(jdouble))); 4667 movflt(xmm2, Address(rsp,off++*sizeof(jdouble))); 4668 movflt(xmm3, Address(rsp,off++*sizeof(jdouble))); 4669 movflt(xmm4, Address(rsp,off++*sizeof(jdouble))); 4670 movflt(xmm5, Address(rsp,off++*sizeof(jdouble))); 4671 movflt(xmm6, Address(rsp,off++*sizeof(jdouble))); 4672 movflt(xmm7, Address(rsp,off++*sizeof(jdouble))); 4673 addptr(rsp, sizeof(jdouble)*8); 4674 } else if (UseSSE >= 2) { 4675 // Restore whole 128bit (16 bytes) XMM regiters 4676 movdqu(xmm0, Address(rsp,off++*16)); 4677 movdqu(xmm1, Address(rsp,off++*16)); 4678 movdqu(xmm2, Address(rsp,off++*16)); 4679 movdqu(xmm3, Address(rsp,off++*16)); 4680 movdqu(xmm4, Address(rsp,off++*16)); 4681 movdqu(xmm5, Address(rsp,off++*16)); 4682 movdqu(xmm6, Address(rsp,off++*16)); 4683 movdqu(xmm7, Address(rsp,off++*16)); 4684 #ifdef _LP64 4685 movdqu(xmm8, Address(rsp,off++*16)); 4686 movdqu(xmm9, Address(rsp,off++*16)); 4687 movdqu(xmm10, Address(rsp,off++*16)); 4688 movdqu(xmm11, Address(rsp,off++*16)); 4689 movdqu(xmm12, Address(rsp,off++*16)); 4690 movdqu(xmm13, Address(rsp,off++*16)); 4691 movdqu(xmm14, Address(rsp,off++*16)); 4692 movdqu(xmm15, Address(rsp,off++*16)); 4693 #endif 4694 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); 4695 #ifdef COMPILER2 4696 if (MaxVectorSize > 16) { 4697 // Restore upper half of YMM registes. 4698 vinsertf128h(xmm0, Address(rsp, 0)); 4699 vinsertf128h(xmm1, Address(rsp, 16)); 4700 vinsertf128h(xmm2, Address(rsp, 32)); 4701 vinsertf128h(xmm3, Address(rsp, 48)); 4702 vinsertf128h(xmm4, Address(rsp, 64)); 4703 vinsertf128h(xmm5, Address(rsp, 80)); 4704 vinsertf128h(xmm6, Address(rsp, 96)); 4705 vinsertf128h(xmm7, Address(rsp,112)); 4706 #ifdef _LP64 4707 vinsertf128h(xmm8, Address(rsp,128)); 4708 vinsertf128h(xmm9, Address(rsp,144)); 4709 vinsertf128h(xmm10, Address(rsp,160)); 4710 vinsertf128h(xmm11, Address(rsp,176)); 4711 vinsertf128h(xmm12, Address(rsp,192)); 4712 vinsertf128h(xmm13, Address(rsp,208)); 4713 vinsertf128h(xmm14, Address(rsp,224)); 4714 vinsertf128h(xmm15, Address(rsp,240)); 4715 #endif 4716 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); 4717 } 4718 #endif 4719 } 4720 popa(); 4721 } 4722 4723 static const double pi_4 = 0.7853981633974483; 4724 4725 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { 4726 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) 4727 // was attempted in this code; unfortunately it appears that the 4728 // switch to 80-bit precision and back causes this to be 4729 // unprofitable compared with simply performing a runtime call if 4730 // the argument is out of the (-pi/4, pi/4) range. 4731 4732 Register tmp = noreg; 4733 if (!VM_Version::supports_cmov()) { 4734 // fcmp needs a temporary so preserve rbx, 4735 tmp = rbx; 4736 push(tmp); 4737 } 4738 4739 Label slow_case, done; 4740 4741 ExternalAddress pi4_adr = (address)&pi_4; 4742 if (reachable(pi4_adr)) { 4743 // x ?<= pi/4 4744 fld_d(pi4_adr); 4745 fld_s(1); // Stack: X PI/4 X 4746 fabs(); // Stack: |X| PI/4 X 4747 fcmp(tmp); 4748 jcc(Assembler::above, slow_case); 4749 4750 // fastest case: -pi/4 <= x <= pi/4 4751 switch(trig) { 4752 case 's': 4753 fsin(); 4754 break; 4755 case 'c': 4756 fcos(); 4757 break; 4758 case 't': 4759 ftan(); 4760 break; 4761 default: 4762 assert(false, "bad intrinsic"); 4763 break; 4764 } 4765 jmp(done); 4766 } 4767 4768 // slow case: runtime call 4769 bind(slow_case); 4770 4771 switch(trig) { 4772 case 's': 4773 { 4774 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use); 4775 } 4776 break; 4777 case 'c': 4778 { 4779 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use); 4780 } 4781 break; 4782 case 't': 4783 { 4784 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use); 4785 } 4786 break; 4787 default: 4788 assert(false, "bad intrinsic"); 4789 break; 4790 } 4791 4792 // Come here with result in F-TOS 4793 bind(done); 4794 4795 if (tmp != noreg) { 4796 pop(tmp); 4797 } 4798 } 4799 4800 4801 // Look up the method for a megamorphic invokeinterface call. 4802 // The target method is determined by <intf_klass, itable_index>. 4803 // The receiver klass is in recv_klass. 4804 // On success, the result will be in method_result, and execution falls through. 4805 // On failure, execution transfers to the given label. 4806 void MacroAssembler::lookup_interface_method(Register recv_klass, 4807 Register intf_klass, 4808 RegisterOrConstant itable_index, 4809 Register method_result, 4810 Register scan_temp, 4811 Label& L_no_such_interface) { 4812 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); 4813 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 4814 "caller must use same register for non-constant itable index as for method"); 4815 4816 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 4817 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize; 4818 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 4819 int scan_step = itableOffsetEntry::size() * wordSize; 4820 int vte_size = vtableEntry::size() * wordSize; 4821 Address::ScaleFactor times_vte_scale = Address::times_ptr; 4822 assert(vte_size == wordSize, "else adjust times_vte_scale"); 4823 4824 movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize)); 4825 4826 // %%% Could store the aligned, prescaled offset in the klassoop. 4827 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 4828 if (HeapWordsPerLong > 1) { 4829 // Round up to align_object_offset boundary 4830 // see code for InstanceKlass::start_of_itable! 4831 round_to(scan_temp, BytesPerLong); 4832 } 4833 4834 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 4835 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 4836 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 4837 4838 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 4839 // if (scan->interface() == intf) { 4840 // result = (klass + scan->offset() + itable_index); 4841 // } 4842 // } 4843 Label search, found_method; 4844 4845 for (int peel = 1; peel >= 0; peel--) { 4846 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 4847 cmpptr(intf_klass, method_result); 4848 4849 if (peel) { 4850 jccb(Assembler::equal, found_method); 4851 } else { 4852 jccb(Assembler::notEqual, search); 4853 // (invert the test to fall through to found_method...) 4854 } 4855 4856 if (!peel) break; 4857 4858 bind(search); 4859 4860 // Check that the previous entry is non-null. A null entry means that 4861 // the receiver class doesn't implement the interface, and wasn't the 4862 // same as when the caller was compiled. 4863 testptr(method_result, method_result); 4864 jcc(Assembler::zero, L_no_such_interface); 4865 addptr(scan_temp, scan_step); 4866 } 4867 4868 bind(found_method); 4869 4870 // Got a hit. 4871 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 4872 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); 4873 } 4874 4875 4876 // virtual method calling 4877 void MacroAssembler::lookup_virtual_method(Register recv_klass, 4878 RegisterOrConstant vtable_index, 4879 Register method_result) { 4880 const int base = InstanceKlass::vtable_start_offset() * wordSize; 4881 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); 4882 Address vtable_entry_addr(recv_klass, 4883 vtable_index, Address::times_ptr, 4884 base + vtableEntry::method_offset_in_bytes()); 4885 movptr(method_result, vtable_entry_addr); 4886 } 4887 4888 4889 void MacroAssembler::check_klass_subtype(Register sub_klass, 4890 Register super_klass, 4891 Register temp_reg, 4892 Label& L_success) { 4893 Label L_failure; 4894 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 4895 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 4896 bind(L_failure); 4897 } 4898 4899 4900 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 4901 Register super_klass, 4902 Register temp_reg, 4903 Label* L_success, 4904 Label* L_failure, 4905 Label* L_slow_path, 4906 RegisterOrConstant super_check_offset) { 4907 assert_different_registers(sub_klass, super_klass, temp_reg); 4908 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 4909 if (super_check_offset.is_register()) { 4910 assert_different_registers(sub_klass, super_klass, 4911 super_check_offset.as_register()); 4912 } else if (must_load_sco) { 4913 assert(temp_reg != noreg, "supply either a temp or a register offset"); 4914 } 4915 4916 Label L_fallthrough; 4917 int label_nulls = 0; 4918 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 4919 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 4920 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 4921 assert(label_nulls <= 1, "at most one NULL in the batch"); 4922 4923 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 4924 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 4925 Address super_check_offset_addr(super_klass, sco_offset); 4926 4927 // Hacked jcc, which "knows" that L_fallthrough, at least, is in 4928 // range of a jccb. If this routine grows larger, reconsider at 4929 // least some of these. 4930 #define local_jcc(assembler_cond, label) \ 4931 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ 4932 else jcc( assembler_cond, label) /*omit semi*/ 4933 4934 // Hacked jmp, which may only be used just before L_fallthrough. 4935 #define final_jmp(label) \ 4936 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 4937 else jmp(label) /*omit semi*/ 4938 4939 // If the pointers are equal, we are done (e.g., String[] elements). 4940 // This self-check enables sharing of secondary supertype arrays among 4941 // non-primary types such as array-of-interface. Otherwise, each such 4942 // type would need its own customized SSA. 4943 // We move this check to the front of the fast path because many 4944 // type checks are in fact trivially successful in this manner, 4945 // so we get a nicely predicted branch right at the start of the check. 4946 cmpptr(sub_klass, super_klass); 4947 local_jcc(Assembler::equal, *L_success); 4948 4949 // Check the supertype display: 4950 if (must_load_sco) { 4951 // Positive movl does right thing on LP64. 4952 movl(temp_reg, super_check_offset_addr); 4953 super_check_offset = RegisterOrConstant(temp_reg); 4954 } 4955 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); 4956 cmpptr(super_klass, super_check_addr); // load displayed supertype 4957 4958 // This check has worked decisively for primary supers. 4959 // Secondary supers are sought in the super_cache ('super_cache_addr'). 4960 // (Secondary supers are interfaces and very deeply nested subtypes.) 4961 // This works in the same check above because of a tricky aliasing 4962 // between the super_cache and the primary super display elements. 4963 // (The 'super_check_addr' can address either, as the case requires.) 4964 // Note that the cache is updated below if it does not help us find 4965 // what we need immediately. 4966 // So if it was a primary super, we can just fail immediately. 4967 // Otherwise, it's the slow path for us (no success at this point). 4968 4969 if (super_check_offset.is_register()) { 4970 local_jcc(Assembler::equal, *L_success); 4971 cmpl(super_check_offset.as_register(), sc_offset); 4972 if (L_failure == &L_fallthrough) { 4973 local_jcc(Assembler::equal, *L_slow_path); 4974 } else { 4975 local_jcc(Assembler::notEqual, *L_failure); 4976 final_jmp(*L_slow_path); 4977 } 4978 } else if (super_check_offset.as_constant() == sc_offset) { 4979 // Need a slow path; fast failure is impossible. 4980 if (L_slow_path == &L_fallthrough) { 4981 local_jcc(Assembler::equal, *L_success); 4982 } else { 4983 local_jcc(Assembler::notEqual, *L_slow_path); 4984 final_jmp(*L_success); 4985 } 4986 } else { 4987 // No slow path; it's a fast decision. 4988 if (L_failure == &L_fallthrough) { 4989 local_jcc(Assembler::equal, *L_success); 4990 } else { 4991 local_jcc(Assembler::notEqual, *L_failure); 4992 final_jmp(*L_success); 4993 } 4994 } 4995 4996 bind(L_fallthrough); 4997 4998 #undef local_jcc 4999 #undef final_jmp 5000 } 5001 5002 5003 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 5004 Register super_klass, 5005 Register temp_reg, 5006 Register temp2_reg, 5007 Label* L_success, 5008 Label* L_failure, 5009 bool set_cond_codes) { 5010 assert_different_registers(sub_klass, super_klass, temp_reg); 5011 if (temp2_reg != noreg) 5012 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); 5013 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 5014 5015 Label L_fallthrough; 5016 int label_nulls = 0; 5017 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5018 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5019 assert(label_nulls <= 1, "at most one NULL in the batch"); 5020 5021 // a couple of useful fields in sub_klass: 5022 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 5023 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5024 Address secondary_supers_addr(sub_klass, ss_offset); 5025 Address super_cache_addr( sub_klass, sc_offset); 5026 5027 // Do a linear scan of the secondary super-klass chain. 5028 // This code is rarely used, so simplicity is a virtue here. 5029 // The repne_scan instruction uses fixed registers, which we must spill. 5030 // Don't worry too much about pre-existing connections with the input regs. 5031 5032 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) 5033 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) 5034 5035 // Get super_klass value into rax (even if it was in rdi or rcx). 5036 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; 5037 if (super_klass != rax || UseCompressedOops) { 5038 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } 5039 mov(rax, super_klass); 5040 } 5041 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } 5042 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } 5043 5044 #ifndef PRODUCT 5045 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; 5046 ExternalAddress pst_counter_addr((address) pst_counter); 5047 NOT_LP64( incrementl(pst_counter_addr) ); 5048 LP64_ONLY( lea(rcx, pst_counter_addr) ); 5049 LP64_ONLY( incrementl(Address(rcx, 0)) ); 5050 #endif //PRODUCT 5051 5052 // We will consult the secondary-super array. 5053 movptr(rdi, secondary_supers_addr); 5054 // Load the array length. (Positive movl does right thing on LP64.) 5055 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes())); 5056 // Skip to start of data. 5057 addptr(rdi, Array<Klass*>::base_offset_in_bytes()); 5058 5059 // Scan RCX words at [RDI] for an occurrence of RAX. 5060 // Set NZ/Z based on last compare. 5061 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does 5062 // not change flags (only scas instruction which is repeated sets flags). 5063 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. 5064 5065 testptr(rax,rax); // Set Z = 0 5066 repne_scan(); 5067 5068 // Unspill the temp. registers: 5069 if (pushed_rdi) pop(rdi); 5070 if (pushed_rcx) pop(rcx); 5071 if (pushed_rax) pop(rax); 5072 5073 if (set_cond_codes) { 5074 // Special hack for the AD files: rdi is guaranteed non-zero. 5075 assert(!pushed_rdi, "rdi must be left non-NULL"); 5076 // Also, the condition codes are properly set Z/NZ on succeed/failure. 5077 } 5078 5079 if (L_failure == &L_fallthrough) 5080 jccb(Assembler::notEqual, *L_failure); 5081 else jcc(Assembler::notEqual, *L_failure); 5082 5083 // Success. Cache the super we found and proceed in triumph. 5084 movptr(super_cache_addr, super_klass); 5085 5086 if (L_success != &L_fallthrough) { 5087 jmp(*L_success); 5088 } 5089 5090 #undef IS_A_TEMP 5091 5092 bind(L_fallthrough); 5093 } 5094 5095 5096 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { 5097 if (VM_Version::supports_cmov()) { 5098 cmovl(cc, dst, src); 5099 } else { 5100 Label L; 5101 jccb(negate_condition(cc), L); 5102 movl(dst, src); 5103 bind(L); 5104 } 5105 } 5106 5107 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { 5108 if (VM_Version::supports_cmov()) { 5109 cmovl(cc, dst, src); 5110 } else { 5111 Label L; 5112 jccb(negate_condition(cc), L); 5113 movl(dst, src); 5114 bind(L); 5115 } 5116 } 5117 5118 void MacroAssembler::verify_oop(Register reg, const char* s) { 5119 if (!VerifyOops) return; 5120 5121 // Pass register number to verify_oop_subroutine 5122 const char* b = NULL; 5123 { 5124 ResourceMark rm; 5125 stringStream ss; 5126 ss.print("verify_oop: %s: %s", reg->name(), s); 5127 b = code_string(ss.as_string()); 5128 } 5129 BLOCK_COMMENT("verify_oop {"); 5130 #ifdef _LP64 5131 push(rscratch1); // save r10, trashed by movptr() 5132 #endif 5133 push(rax); // save rax, 5134 push(reg); // pass register argument 5135 ExternalAddress buffer((address) b); 5136 // avoid using pushptr, as it modifies scratch registers 5137 // and our contract is not to modify anything 5138 movptr(rax, buffer.addr()); 5139 push(rax); 5140 // call indirectly to solve generation ordering problem 5141 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 5142 call(rax); 5143 // Caller pops the arguments (oop, message) and restores rax, r10 5144 BLOCK_COMMENT("} verify_oop"); 5145 } 5146 5147 5148 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 5149 Register tmp, 5150 int offset) { 5151 intptr_t value = *delayed_value_addr; 5152 if (value != 0) 5153 return RegisterOrConstant(value + offset); 5154 5155 // load indirectly to solve generation ordering problem 5156 movptr(tmp, ExternalAddress((address) delayed_value_addr)); 5157 5158 #ifdef ASSERT 5159 { Label L; 5160 testptr(tmp, tmp); 5161 if (WizardMode) { 5162 const char* buf = NULL; 5163 { 5164 ResourceMark rm; 5165 stringStream ss; 5166 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]); 5167 buf = code_string(ss.as_string()); 5168 } 5169 jcc(Assembler::notZero, L); 5170 STOP(buf); 5171 } else { 5172 jccb(Assembler::notZero, L); 5173 hlt(); 5174 } 5175 bind(L); 5176 } 5177 #endif 5178 5179 if (offset != 0) 5180 addptr(tmp, offset); 5181 5182 return RegisterOrConstant(tmp); 5183 } 5184 5185 5186 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 5187 int extra_slot_offset) { 5188 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 5189 int stackElementSize = Interpreter::stackElementSize; 5190 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 5191 #ifdef ASSERT 5192 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 5193 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 5194 #endif 5195 Register scale_reg = noreg; 5196 Address::ScaleFactor scale_factor = Address::no_scale; 5197 if (arg_slot.is_constant()) { 5198 offset += arg_slot.as_constant() * stackElementSize; 5199 } else { 5200 scale_reg = arg_slot.as_register(); 5201 scale_factor = Address::times(stackElementSize); 5202 } 5203 offset += wordSize; // return PC is on stack 5204 return Address(rsp, scale_reg, scale_factor, offset); 5205 } 5206 5207 5208 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 5209 if (!VerifyOops) return; 5210 5211 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); 5212 // Pass register number to verify_oop_subroutine 5213 const char* b = NULL; 5214 { 5215 ResourceMark rm; 5216 stringStream ss; 5217 ss.print("verify_oop_addr: %s", s); 5218 b = code_string(ss.as_string()); 5219 } 5220 #ifdef _LP64 5221 push(rscratch1); // save r10, trashed by movptr() 5222 #endif 5223 push(rax); // save rax, 5224 // addr may contain rsp so we will have to adjust it based on the push 5225 // we just did (and on 64 bit we do two pushes) 5226 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which 5227 // stores rax into addr which is backwards of what was intended. 5228 if (addr.uses(rsp)) { 5229 lea(rax, addr); 5230 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); 5231 } else { 5232 pushptr(addr); 5233 } 5234 5235 ExternalAddress buffer((address) b); 5236 // pass msg argument 5237 // avoid using pushptr, as it modifies scratch registers 5238 // and our contract is not to modify anything 5239 movptr(rax, buffer.addr()); 5240 push(rax); 5241 5242 // call indirectly to solve generation ordering problem 5243 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 5244 call(rax); 5245 // Caller pops the arguments (addr, message) and restores rax, r10. 5246 } 5247 5248 void MacroAssembler::verify_tlab() { 5249 #ifdef ASSERT 5250 if (UseTLAB && VerifyOops) { 5251 Label next, ok; 5252 Register t1 = rsi; 5253 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); 5254 5255 push(t1); 5256 NOT_LP64(push(thread_reg)); 5257 NOT_LP64(get_thread(thread_reg)); 5258 5259 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 5260 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5261 jcc(Assembler::aboveEqual, next); 5262 STOP("assert(top >= start)"); 5263 should_not_reach_here(); 5264 5265 bind(next); 5266 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 5267 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 5268 jcc(Assembler::aboveEqual, ok); 5269 STOP("assert(top <= end)"); 5270 should_not_reach_here(); 5271 5272 bind(ok); 5273 NOT_LP64(pop(thread_reg)); 5274 pop(t1); 5275 } 5276 #endif 5277 } 5278 5279 class ControlWord { 5280 public: 5281 int32_t _value; 5282 5283 int rounding_control() const { return (_value >> 10) & 3 ; } 5284 int precision_control() const { return (_value >> 8) & 3 ; } 5285 bool precision() const { return ((_value >> 5) & 1) != 0; } 5286 bool underflow() const { return ((_value >> 4) & 1) != 0; } 5287 bool overflow() const { return ((_value >> 3) & 1) != 0; } 5288 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 5289 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 5290 bool invalid() const { return ((_value >> 0) & 1) != 0; } 5291 5292 void print() const { 5293 // rounding control 5294 const char* rc; 5295 switch (rounding_control()) { 5296 case 0: rc = "round near"; break; 5297 case 1: rc = "round down"; break; 5298 case 2: rc = "round up "; break; 5299 case 3: rc = "chop "; break; 5300 }; 5301 // precision control 5302 const char* pc; 5303 switch (precision_control()) { 5304 case 0: pc = "24 bits "; break; 5305 case 1: pc = "reserved"; break; 5306 case 2: pc = "53 bits "; break; 5307 case 3: pc = "64 bits "; break; 5308 }; 5309 // flags 5310 char f[9]; 5311 f[0] = ' '; 5312 f[1] = ' '; 5313 f[2] = (precision ()) ? 'P' : 'p'; 5314 f[3] = (underflow ()) ? 'U' : 'u'; 5315 f[4] = (overflow ()) ? 'O' : 'o'; 5316 f[5] = (zero_divide ()) ? 'Z' : 'z'; 5317 f[6] = (denormalized()) ? 'D' : 'd'; 5318 f[7] = (invalid ()) ? 'I' : 'i'; 5319 f[8] = '\x0'; 5320 // output 5321 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); 5322 } 5323 5324 }; 5325 5326 class StatusWord { 5327 public: 5328 int32_t _value; 5329 5330 bool busy() const { return ((_value >> 15) & 1) != 0; } 5331 bool C3() const { return ((_value >> 14) & 1) != 0; } 5332 bool C2() const { return ((_value >> 10) & 1) != 0; } 5333 bool C1() const { return ((_value >> 9) & 1) != 0; } 5334 bool C0() const { return ((_value >> 8) & 1) != 0; } 5335 int top() const { return (_value >> 11) & 7 ; } 5336 bool error_status() const { return ((_value >> 7) & 1) != 0; } 5337 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } 5338 bool precision() const { return ((_value >> 5) & 1) != 0; } 5339 bool underflow() const { return ((_value >> 4) & 1) != 0; } 5340 bool overflow() const { return ((_value >> 3) & 1) != 0; } 5341 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 5342 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 5343 bool invalid() const { return ((_value >> 0) & 1) != 0; } 5344 5345 void print() const { 5346 // condition codes 5347 char c[5]; 5348 c[0] = (C3()) ? '3' : '-'; 5349 c[1] = (C2()) ? '2' : '-'; 5350 c[2] = (C1()) ? '1' : '-'; 5351 c[3] = (C0()) ? '0' : '-'; 5352 c[4] = '\x0'; 5353 // flags 5354 char f[9]; 5355 f[0] = (error_status()) ? 'E' : '-'; 5356 f[1] = (stack_fault ()) ? 'S' : '-'; 5357 f[2] = (precision ()) ? 'P' : '-'; 5358 f[3] = (underflow ()) ? 'U' : '-'; 5359 f[4] = (overflow ()) ? 'O' : '-'; 5360 f[5] = (zero_divide ()) ? 'Z' : '-'; 5361 f[6] = (denormalized()) ? 'D' : '-'; 5362 f[7] = (invalid ()) ? 'I' : '-'; 5363 f[8] = '\x0'; 5364 // output 5365 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); 5366 } 5367 5368 }; 5369 5370 class TagWord { 5371 public: 5372 int32_t _value; 5373 5374 int tag_at(int i) const { return (_value >> (i*2)) & 3; } 5375 5376 void print() const { 5377 printf("%04x", _value & 0xFFFF); 5378 } 5379 5380 }; 5381 5382 class FPU_Register { 5383 public: 5384 int32_t _m0; 5385 int32_t _m1; 5386 int16_t _ex; 5387 5388 bool is_indefinite() const { 5389 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; 5390 } 5391 5392 void print() const { 5393 char sign = (_ex < 0) ? '-' : '+'; 5394 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; 5395 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); 5396 }; 5397 5398 }; 5399 5400 class FPU_State { 5401 public: 5402 enum { 5403 register_size = 10, 5404 number_of_registers = 8, 5405 register_mask = 7 5406 }; 5407 5408 ControlWord _control_word; 5409 StatusWord _status_word; 5410 TagWord _tag_word; 5411 int32_t _error_offset; 5412 int32_t _error_selector; 5413 int32_t _data_offset; 5414 int32_t _data_selector; 5415 int8_t _register[register_size * number_of_registers]; 5416 5417 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } 5418 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } 5419 5420 const char* tag_as_string(int tag) const { 5421 switch (tag) { 5422 case 0: return "valid"; 5423 case 1: return "zero"; 5424 case 2: return "special"; 5425 case 3: return "empty"; 5426 } 5427 ShouldNotReachHere(); 5428 return NULL; 5429 } 5430 5431 void print() const { 5432 // print computation registers 5433 { int t = _status_word.top(); 5434 for (int i = 0; i < number_of_registers; i++) { 5435 int j = (i - t) & register_mask; 5436 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); 5437 st(j)->print(); 5438 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); 5439 } 5440 } 5441 printf("\n"); 5442 // print control registers 5443 printf("ctrl = "); _control_word.print(); printf("\n"); 5444 printf("stat = "); _status_word .print(); printf("\n"); 5445 printf("tags = "); _tag_word .print(); printf("\n"); 5446 } 5447 5448 }; 5449 5450 class Flag_Register { 5451 public: 5452 int32_t _value; 5453 5454 bool overflow() const { return ((_value >> 11) & 1) != 0; } 5455 bool direction() const { return ((_value >> 10) & 1) != 0; } 5456 bool sign() const { return ((_value >> 7) & 1) != 0; } 5457 bool zero() const { return ((_value >> 6) & 1) != 0; } 5458 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } 5459 bool parity() const { return ((_value >> 2) & 1) != 0; } 5460 bool carry() const { return ((_value >> 0) & 1) != 0; } 5461 5462 void print() const { 5463 // flags 5464 char f[8]; 5465 f[0] = (overflow ()) ? 'O' : '-'; 5466 f[1] = (direction ()) ? 'D' : '-'; 5467 f[2] = (sign ()) ? 'S' : '-'; 5468 f[3] = (zero ()) ? 'Z' : '-'; 5469 f[4] = (auxiliary_carry()) ? 'A' : '-'; 5470 f[5] = (parity ()) ? 'P' : '-'; 5471 f[6] = (carry ()) ? 'C' : '-'; 5472 f[7] = '\x0'; 5473 // output 5474 printf("%08x flags = %s", _value, f); 5475 } 5476 5477 }; 5478 5479 class IU_Register { 5480 public: 5481 int32_t _value; 5482 5483 void print() const { 5484 printf("%08x %11d", _value, _value); 5485 } 5486 5487 }; 5488 5489 class IU_State { 5490 public: 5491 Flag_Register _eflags; 5492 IU_Register _rdi; 5493 IU_Register _rsi; 5494 IU_Register _rbp; 5495 IU_Register _rsp; 5496 IU_Register _rbx; 5497 IU_Register _rdx; 5498 IU_Register _rcx; 5499 IU_Register _rax; 5500 5501 void print() const { 5502 // computation registers 5503 printf("rax, = "); _rax.print(); printf("\n"); 5504 printf("rbx, = "); _rbx.print(); printf("\n"); 5505 printf("rcx = "); _rcx.print(); printf("\n"); 5506 printf("rdx = "); _rdx.print(); printf("\n"); 5507 printf("rdi = "); _rdi.print(); printf("\n"); 5508 printf("rsi = "); _rsi.print(); printf("\n"); 5509 printf("rbp, = "); _rbp.print(); printf("\n"); 5510 printf("rsp = "); _rsp.print(); printf("\n"); 5511 printf("\n"); 5512 // control registers 5513 printf("flgs = "); _eflags.print(); printf("\n"); 5514 } 5515 }; 5516 5517 5518 class CPU_State { 5519 public: 5520 FPU_State _fpu_state; 5521 IU_State _iu_state; 5522 5523 void print() const { 5524 printf("--------------------------------------------------\n"); 5525 _iu_state .print(); 5526 printf("\n"); 5527 _fpu_state.print(); 5528 printf("--------------------------------------------------\n"); 5529 } 5530 5531 }; 5532 5533 5534 static void _print_CPU_state(CPU_State* state) { 5535 state->print(); 5536 }; 5537 5538 5539 void MacroAssembler::print_CPU_state() { 5540 push_CPU_state(); 5541 push(rsp); // pass CPU state 5542 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); 5543 addptr(rsp, wordSize); // discard argument 5544 pop_CPU_state(); 5545 } 5546 5547 5548 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { 5549 static int counter = 0; 5550 FPU_State* fs = &state->_fpu_state; 5551 counter++; 5552 // For leaf calls, only verify that the top few elements remain empty. 5553 // We only need 1 empty at the top for C2 code. 5554 if( stack_depth < 0 ) { 5555 if( fs->tag_for_st(7) != 3 ) { 5556 printf("FPR7 not empty\n"); 5557 state->print(); 5558 assert(false, "error"); 5559 return false; 5560 } 5561 return true; // All other stack states do not matter 5562 } 5563 5564 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, 5565 "bad FPU control word"); 5566 5567 // compute stack depth 5568 int i = 0; 5569 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; 5570 int d = i; 5571 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; 5572 // verify findings 5573 if (i != FPU_State::number_of_registers) { 5574 // stack not contiguous 5575 printf("%s: stack not contiguous at ST%d\n", s, i); 5576 state->print(); 5577 assert(false, "error"); 5578 return false; 5579 } 5580 // check if computed stack depth corresponds to expected stack depth 5581 if (stack_depth < 0) { 5582 // expected stack depth is -stack_depth or less 5583 if (d > -stack_depth) { 5584 // too many elements on the stack 5585 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); 5586 state->print(); 5587 assert(false, "error"); 5588 return false; 5589 } 5590 } else { 5591 // expected stack depth is stack_depth 5592 if (d != stack_depth) { 5593 // wrong stack depth 5594 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); 5595 state->print(); 5596 assert(false, "error"); 5597 return false; 5598 } 5599 } 5600 // everything is cool 5601 return true; 5602 } 5603 5604 5605 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 5606 if (!VerifyFPU) return; 5607 push_CPU_state(); 5608 push(rsp); // pass CPU state 5609 ExternalAddress msg((address) s); 5610 // pass message string s 5611 pushptr(msg.addr()); 5612 push(stack_depth); // pass stack depth 5613 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); 5614 addptr(rsp, 3 * wordSize); // discard arguments 5615 // check for error 5616 { Label L; 5617 testl(rax, rax); 5618 jcc(Assembler::notZero, L); 5619 int3(); // break if error condition 5620 bind(L); 5621 } 5622 pop_CPU_state(); 5623 } 5624 5625 void MacroAssembler::restore_cpu_control_state_after_jni() { 5626 // Either restore the MXCSR register after returning from the JNI Call 5627 // or verify that it wasn't changed (with -Xcheck:jni flag). 5628 if (VM_Version::supports_sse()) { 5629 if (RestoreMXCSROnJNICalls) { 5630 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std())); 5631 } else if (CheckJNICalls) { 5632 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry())); 5633 } 5634 } 5635 if (VM_Version::supports_avx()) { 5636 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty. 5637 vzeroupper(); 5638 } 5639 5640 #ifndef _LP64 5641 // Either restore the x87 floating pointer control word after returning 5642 // from the JNI call or verify that it wasn't changed. 5643 if (CheckJNICalls) { 5644 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry())); 5645 } 5646 #endif // _LP64 5647 } 5648 5649 5650 void MacroAssembler::load_klass(Register dst, Register src) { 5651 #ifdef _LP64 5652 if (UseCompressedClassPointers) { 5653 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); 5654 decode_klass_not_null(dst); 5655 } else 5656 #endif 5657 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 5658 } 5659 5660 void MacroAssembler::load_prototype_header(Register dst, Register src) { 5661 load_klass(dst, src); 5662 movptr(dst, Address(dst, Klass::prototype_header_offset())); 5663 } 5664 5665 void MacroAssembler::store_klass(Register dst, Register src) { 5666 #ifdef _LP64 5667 if (UseCompressedClassPointers) { 5668 encode_klass_not_null(src); 5669 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); 5670 } else 5671 #endif 5672 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); 5673 } 5674 5675 void MacroAssembler::load_heap_oop(Register dst, Address src) { 5676 #ifdef _LP64 5677 // FIXME: Must change all places where we try to load the klass. 5678 if (UseCompressedOops) { 5679 movl(dst, src); 5680 decode_heap_oop(dst); 5681 } else 5682 #endif 5683 movptr(dst, src); 5684 } 5685 5686 // Doesn't do verfication, generates fixed size code 5687 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { 5688 #ifdef _LP64 5689 if (UseCompressedOops) { 5690 movl(dst, src); 5691 decode_heap_oop_not_null(dst); 5692 } else 5693 #endif 5694 movptr(dst, src); 5695 } 5696 5697 void MacroAssembler::store_heap_oop(Address dst, Register src) { 5698 #ifdef _LP64 5699 if (UseCompressedOops) { 5700 assert(!dst.uses(src), "not enough registers"); 5701 encode_heap_oop(src); 5702 movl(dst, src); 5703 } else 5704 #endif 5705 movptr(dst, src); 5706 } 5707 5708 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) { 5709 assert_different_registers(src1, tmp); 5710 #ifdef _LP64 5711 if (UseCompressedOops) { 5712 bool did_push = false; 5713 if (tmp == noreg) { 5714 tmp = rax; 5715 push(tmp); 5716 did_push = true; 5717 assert(!src2.uses(rsp), "can't push"); 5718 } 5719 load_heap_oop(tmp, src2); 5720 cmpptr(src1, tmp); 5721 if (did_push) pop(tmp); 5722 } else 5723 #endif 5724 cmpptr(src1, src2); 5725 } 5726 5727 // Used for storing NULLs. 5728 void MacroAssembler::store_heap_oop_null(Address dst) { 5729 #ifdef _LP64 5730 if (UseCompressedOops) { 5731 movl(dst, (int32_t)NULL_WORD); 5732 } else { 5733 movslq(dst, (int32_t)NULL_WORD); 5734 } 5735 #else 5736 movl(dst, (int32_t)NULL_WORD); 5737 #endif 5738 } 5739 5740 #ifdef _LP64 5741 void MacroAssembler::store_klass_gap(Register dst, Register src) { 5742 if (UseCompressedClassPointers) { 5743 // Store to klass gap in destination 5744 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); 5745 } 5746 } 5747 5748 #ifdef ASSERT 5749 void MacroAssembler::verify_heapbase(const char* msg) { 5750 assert (UseCompressedOops, "should be compressed"); 5751 assert (Universe::heap() != NULL, "java heap should be initialized"); 5752 if (CheckCompressedOops) { 5753 Label ok; 5754 push(rscratch1); // cmpptr trashes rscratch1 5755 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 5756 jcc(Assembler::equal, ok); 5757 STOP(msg); 5758 bind(ok); 5759 pop(rscratch1); 5760 } 5761 } 5762 #endif 5763 5764 // Algorithm must match oop.inline.hpp encode_heap_oop. 5765 void MacroAssembler::encode_heap_oop(Register r) { 5766 #ifdef ASSERT 5767 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 5768 #endif 5769 verify_oop(r, "broken oop in encode_heap_oop"); 5770 if (Universe::narrow_oop_base() == NULL) { 5771 if (Universe::narrow_oop_shift() != 0) { 5772 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5773 shrq(r, LogMinObjAlignmentInBytes); 5774 } 5775 return; 5776 } 5777 testq(r, r); 5778 cmovq(Assembler::equal, r, r12_heapbase); 5779 subq(r, r12_heapbase); 5780 shrq(r, LogMinObjAlignmentInBytes); 5781 } 5782 5783 void MacroAssembler::encode_heap_oop_not_null(Register r) { 5784 #ifdef ASSERT 5785 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 5786 if (CheckCompressedOops) { 5787 Label ok; 5788 testq(r, r); 5789 jcc(Assembler::notEqual, ok); 5790 STOP("null oop passed to encode_heap_oop_not_null"); 5791 bind(ok); 5792 } 5793 #endif 5794 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 5795 if (Universe::narrow_oop_base() != NULL) { 5796 subq(r, r12_heapbase); 5797 } 5798 if (Universe::narrow_oop_shift() != 0) { 5799 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5800 shrq(r, LogMinObjAlignmentInBytes); 5801 } 5802 } 5803 5804 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 5805 #ifdef ASSERT 5806 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 5807 if (CheckCompressedOops) { 5808 Label ok; 5809 testq(src, src); 5810 jcc(Assembler::notEqual, ok); 5811 STOP("null oop passed to encode_heap_oop_not_null2"); 5812 bind(ok); 5813 } 5814 #endif 5815 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 5816 if (dst != src) { 5817 movq(dst, src); 5818 } 5819 if (Universe::narrow_oop_base() != NULL) { 5820 subq(dst, r12_heapbase); 5821 } 5822 if (Universe::narrow_oop_shift() != 0) { 5823 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5824 shrq(dst, LogMinObjAlignmentInBytes); 5825 } 5826 } 5827 5828 void MacroAssembler::decode_heap_oop(Register r) { 5829 #ifdef ASSERT 5830 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 5831 #endif 5832 if (Universe::narrow_oop_base() == NULL) { 5833 if (Universe::narrow_oop_shift() != 0) { 5834 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5835 shlq(r, LogMinObjAlignmentInBytes); 5836 } 5837 } else { 5838 Label done; 5839 shlq(r, LogMinObjAlignmentInBytes); 5840 jccb(Assembler::equal, done); 5841 addq(r, r12_heapbase); 5842 bind(done); 5843 } 5844 verify_oop(r, "broken oop in decode_heap_oop"); 5845 } 5846 5847 void MacroAssembler::decode_heap_oop_not_null(Register r) { 5848 // Note: it will change flags 5849 assert (UseCompressedOops, "should only be used for compressed headers"); 5850 assert (Universe::heap() != NULL, "java heap should be initialized"); 5851 // Cannot assert, unverified entry point counts instructions (see .ad file) 5852 // vtableStubs also counts instructions in pd_code_size_limit. 5853 // Also do not verify_oop as this is called by verify_oop. 5854 if (Universe::narrow_oop_shift() != 0) { 5855 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5856 shlq(r, LogMinObjAlignmentInBytes); 5857 if (Universe::narrow_oop_base() != NULL) { 5858 addq(r, r12_heapbase); 5859 } 5860 } else { 5861 assert (Universe::narrow_oop_base() == NULL, "sanity"); 5862 } 5863 } 5864 5865 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 5866 // Note: it will change flags 5867 assert (UseCompressedOops, "should only be used for compressed headers"); 5868 assert (Universe::heap() != NULL, "java heap should be initialized"); 5869 // Cannot assert, unverified entry point counts instructions (see .ad file) 5870 // vtableStubs also counts instructions in pd_code_size_limit. 5871 // Also do not verify_oop as this is called by verify_oop. 5872 if (Universe::narrow_oop_shift() != 0) { 5873 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 5874 if (LogMinObjAlignmentInBytes == Address::times_8) { 5875 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); 5876 } else { 5877 if (dst != src) { 5878 movq(dst, src); 5879 } 5880 shlq(dst, LogMinObjAlignmentInBytes); 5881 if (Universe::narrow_oop_base() != NULL) { 5882 addq(dst, r12_heapbase); 5883 } 5884 } 5885 } else { 5886 assert (Universe::narrow_oop_base() == NULL, "sanity"); 5887 if (dst != src) { 5888 movq(dst, src); 5889 } 5890 } 5891 } 5892 5893 void MacroAssembler::encode_klass_not_null(Register r) { 5894 if (Universe::narrow_klass_base() != NULL) { 5895 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 5896 assert(r != r12_heapbase, "Encoding a klass in r12"); 5897 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 5898 subq(r, r12_heapbase); 5899 } 5900 if (Universe::narrow_klass_shift() != 0) { 5901 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 5902 shrq(r, LogKlassAlignmentInBytes); 5903 } 5904 if (Universe::narrow_klass_base() != NULL) { 5905 reinit_heapbase(); 5906 } 5907 } 5908 5909 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 5910 if (dst == src) { 5911 encode_klass_not_null(src); 5912 } else { 5913 if (Universe::narrow_klass_base() != NULL) { 5914 mov64(dst, (int64_t)Universe::narrow_klass_base()); 5915 negq(dst); 5916 addq(dst, src); 5917 } else { 5918 movptr(dst, src); 5919 } 5920 if (Universe::narrow_klass_shift() != 0) { 5921 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 5922 shrq(dst, LogKlassAlignmentInBytes); 5923 } 5924 } 5925 } 5926 5927 // Function instr_size_for_decode_klass_not_null() counts the instructions 5928 // generated by decode_klass_not_null(register r) and reinit_heapbase(), 5929 // when (Universe::heap() != NULL). Hence, if the instructions they 5930 // generate change, then this method needs to be updated. 5931 int MacroAssembler::instr_size_for_decode_klass_not_null() { 5932 assert (UseCompressedClassPointers, "only for compressed klass ptrs"); 5933 if (Universe::narrow_klass_base() != NULL) { 5934 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()). 5935 return (Universe::narrow_klass_shift() == 0 ? 20 : 24); 5936 } else { 5937 // longest load decode klass function, mov64, leaq 5938 return 16; 5939 } 5940 } 5941 5942 // !!! If the instructions that get generated here change then function 5943 // instr_size_for_decode_klass_not_null() needs to get updated. 5944 void MacroAssembler::decode_klass_not_null(Register r) { 5945 // Note: it will change flags 5946 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 5947 assert(r != r12_heapbase, "Decoding a klass in r12"); 5948 // Cannot assert, unverified entry point counts instructions (see .ad file) 5949 // vtableStubs also counts instructions in pd_code_size_limit. 5950 // Also do not verify_oop as this is called by verify_oop. 5951 if (Universe::narrow_klass_shift() != 0) { 5952 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 5953 shlq(r, LogKlassAlignmentInBytes); 5954 } 5955 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 5956 if (Universe::narrow_klass_base() != NULL) { 5957 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 5958 addq(r, r12_heapbase); 5959 reinit_heapbase(); 5960 } 5961 } 5962 5963 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 5964 // Note: it will change flags 5965 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 5966 if (dst == src) { 5967 decode_klass_not_null(dst); 5968 } else { 5969 // Cannot assert, unverified entry point counts instructions (see .ad file) 5970 // vtableStubs also counts instructions in pd_code_size_limit. 5971 // Also do not verify_oop as this is called by verify_oop. 5972 mov64(dst, (int64_t)Universe::narrow_klass_base()); 5973 if (Universe::narrow_klass_shift() != 0) { 5974 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 5975 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); 5976 leaq(dst, Address(dst, src, Address::times_8, 0)); 5977 } else { 5978 addq(dst, src); 5979 } 5980 } 5981 } 5982 5983 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 5984 assert (UseCompressedOops, "should only be used for compressed headers"); 5985 assert (Universe::heap() != NULL, "java heap should be initialized"); 5986 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 5987 int oop_index = oop_recorder()->find_index(obj); 5988 RelocationHolder rspec = oop_Relocation::spec(oop_index); 5989 mov_narrow_oop(dst, oop_index, rspec); 5990 } 5991 5992 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { 5993 assert (UseCompressedOops, "should only be used for compressed headers"); 5994 assert (Universe::heap() != NULL, "java heap should be initialized"); 5995 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 5996 int oop_index = oop_recorder()->find_index(obj); 5997 RelocationHolder rspec = oop_Relocation::spec(oop_index); 5998 mov_narrow_oop(dst, oop_index, rspec); 5999 } 6000 6001 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 6002 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6003 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6004 int klass_index = oop_recorder()->find_index(k); 6005 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6006 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 6007 } 6008 6009 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { 6010 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6011 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6012 int klass_index = oop_recorder()->find_index(k); 6013 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6014 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 6015 } 6016 6017 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { 6018 assert (UseCompressedOops, "should only be used for compressed headers"); 6019 assert (Universe::heap() != NULL, "java heap should be initialized"); 6020 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6021 int oop_index = oop_recorder()->find_index(obj); 6022 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6023 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 6024 } 6025 6026 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { 6027 assert (UseCompressedOops, "should only be used for compressed headers"); 6028 assert (Universe::heap() != NULL, "java heap should be initialized"); 6029 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6030 int oop_index = oop_recorder()->find_index(obj); 6031 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6032 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 6033 } 6034 6035 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { 6036 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6037 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6038 int klass_index = oop_recorder()->find_index(k); 6039 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6040 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 6041 } 6042 6043 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { 6044 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6045 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6046 int klass_index = oop_recorder()->find_index(k); 6047 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6048 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 6049 } 6050 6051 void MacroAssembler::reinit_heapbase() { 6052 if (UseCompressedOops || UseCompressedClassPointers) { 6053 if (Universe::heap() != NULL) { 6054 if (Universe::narrow_oop_base() == NULL) { 6055 MacroAssembler::xorptr(r12_heapbase, r12_heapbase); 6056 } else { 6057 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base()); 6058 } 6059 } else { 6060 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 6061 } 6062 } 6063 } 6064 6065 #endif // _LP64 6066 6067 6068 // C2 compiled method's prolog code. 6069 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) { 6070 6071 // WARNING: Initial instruction MUST be 5 bytes or longer so that 6072 // NativeJump::patch_verified_entry will be able to patch out the entry 6073 // code safely. The push to verify stack depth is ok at 5 bytes, 6074 // the frame allocation can be either 3 or 6 bytes. So if we don't do 6075 // stack bang then we must use the 6 byte frame allocation even if 6076 // we have no frame. :-( 6077 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect"); 6078 6079 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 6080 // Remove word for return addr 6081 framesize -= wordSize; 6082 stack_bang_size -= wordSize; 6083 6084 // Calls to C2R adapters often do not accept exceptional returns. 6085 // We require that their callers must bang for them. But be careful, because 6086 // some VM calls (such as call site linkage) can use several kilobytes of 6087 // stack. But the stack safety zone should account for that. 6088 // See bugs 4446381, 4468289, 4497237. 6089 if (stack_bang_size > 0) { 6090 generate_stack_overflow_check(stack_bang_size); 6091 6092 // We always push rbp, so that on return to interpreter rbp, will be 6093 // restored correctly and we can correct the stack. 6094 push(rbp); 6095 // Save caller's stack pointer into RBP if the frame pointer is preserved. 6096 if (PreserveFramePointer) { 6097 mov(rbp, rsp); 6098 } 6099 // Remove word for ebp 6100 framesize -= wordSize; 6101 6102 // Create frame 6103 if (framesize) { 6104 subptr(rsp, framesize); 6105 } 6106 } else { 6107 // Create frame (force generation of a 4 byte immediate value) 6108 subptr_imm32(rsp, framesize); 6109 6110 // Save RBP register now. 6111 framesize -= wordSize; 6112 movptr(Address(rsp, framesize), rbp); 6113 // Save caller's stack pointer into RBP if the frame pointer is preserved. 6114 if (PreserveFramePointer) { 6115 movptr(rbp, rsp); 6116 addptr(rbp, framesize + wordSize); 6117 } 6118 } 6119 6120 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth 6121 framesize -= wordSize; 6122 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); 6123 } 6124 6125 #ifndef _LP64 6126 // If method sets FPU control word do it now 6127 if (fp_mode_24b) { 6128 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 6129 } 6130 if (UseSSE >= 2 && VerifyFPU) { 6131 verify_FPU(0, "FPU stack must be clean on entry"); 6132 } 6133 #endif 6134 6135 #ifdef ASSERT 6136 if (VerifyStackAtCalls) { 6137 Label L; 6138 push(rax); 6139 mov(rax, rsp); 6140 andptr(rax, StackAlignmentInBytes-1); 6141 cmpptr(rax, StackAlignmentInBytes-wordSize); 6142 pop(rax); 6143 jcc(Assembler::equal, L); 6144 STOP("Stack is not properly aligned!"); 6145 bind(L); 6146 } 6147 #endif 6148 6149 } 6150 6151 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) { 6152 // cnt - number of qwords (8-byte words). 6153 // base - start address, qword aligned. 6154 assert(base==rdi, "base register must be edi for rep stos"); 6155 assert(tmp==rax, "tmp register must be eax for rep stos"); 6156 assert(cnt==rcx, "cnt register must be ecx for rep stos"); 6157 6158 xorptr(tmp, tmp); 6159 if (UseFastStosb) { 6160 shlptr(cnt,3); // convert to number of bytes 6161 rep_stosb(); 6162 } else { 6163 NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM 6164 rep_stos(); 6165 } 6166 } 6167 6168 // IndexOf for constant substrings with size >= 8 chars 6169 // which don't need to be loaded through stack. 6170 void MacroAssembler::string_indexofC8(Register str1, Register str2, 6171 Register cnt1, Register cnt2, 6172 int int_cnt2, Register result, 6173 XMMRegister vec, Register tmp) { 6174 ShortBranchVerifier sbv(this); 6175 assert(UseSSE42Intrinsics, "SSE4.2 is required"); 6176 6177 // This method uses pcmpestri instruction with bound registers 6178 // inputs: 6179 // xmm - substring 6180 // rax - substring length (elements count) 6181 // mem - scanned string 6182 // rdx - string length (elements count) 6183 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 6184 // outputs: 6185 // rcx - matched index in string 6186 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 6187 6188 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, 6189 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, 6190 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; 6191 6192 // Note, inline_string_indexOf() generates checks: 6193 // if (substr.count > string.count) return -1; 6194 // if (substr.count == 0) return 0; 6195 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars"); 6196 6197 // Load substring. 6198 movdqu(vec, Address(str2, 0)); 6199 movl(cnt2, int_cnt2); 6200 movptr(result, str1); // string addr 6201 6202 if (int_cnt2 > 8) { 6203 jmpb(SCAN_TO_SUBSTR); 6204 6205 // Reload substr for rescan, this code 6206 // is executed only for large substrings (> 8 chars) 6207 bind(RELOAD_SUBSTR); 6208 movdqu(vec, Address(str2, 0)); 6209 negptr(cnt2); // Jumped here with negative cnt2, convert to positive 6210 6211 bind(RELOAD_STR); 6212 // We came here after the beginning of the substring was 6213 // matched but the rest of it was not so we need to search 6214 // again. Start from the next element after the previous match. 6215 6216 // cnt2 is number of substring reminding elements and 6217 // cnt1 is number of string reminding elements when cmp failed. 6218 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 6219 subl(cnt1, cnt2); 6220 addl(cnt1, int_cnt2); 6221 movl(cnt2, int_cnt2); // Now restore cnt2 6222 6223 decrementl(cnt1); // Shift to next element 6224 cmpl(cnt1, cnt2); 6225 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 6226 6227 addptr(result, 2); 6228 6229 } // (int_cnt2 > 8) 6230 6231 // Scan string for start of substr in 16-byte vectors 6232 bind(SCAN_TO_SUBSTR); 6233 pcmpestri(vec, Address(result, 0), 0x0d); 6234 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 6235 subl(cnt1, 8); 6236 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 6237 cmpl(cnt1, cnt2); 6238 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 6239 addptr(result, 16); 6240 jmpb(SCAN_TO_SUBSTR); 6241 6242 // Found a potential substr 6243 bind(FOUND_CANDIDATE); 6244 // Matched whole vector if first element matched (tmp(rcx) == 0). 6245 if (int_cnt2 == 8) { 6246 jccb(Assembler::overflow, RET_FOUND); // OF == 1 6247 } else { // int_cnt2 > 8 6248 jccb(Assembler::overflow, FOUND_SUBSTR); 6249 } 6250 // After pcmpestri tmp(rcx) contains matched element index 6251 // Compute start addr of substr 6252 lea(result, Address(result, tmp, Address::times_2)); 6253 6254 // Make sure string is still long enough 6255 subl(cnt1, tmp); 6256 cmpl(cnt1, cnt2); 6257 if (int_cnt2 == 8) { 6258 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 6259 } else { // int_cnt2 > 8 6260 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); 6261 } 6262 // Left less then substring. 6263 6264 bind(RET_NOT_FOUND); 6265 movl(result, -1); 6266 jmpb(EXIT); 6267 6268 if (int_cnt2 > 8) { 6269 // This code is optimized for the case when whole substring 6270 // is matched if its head is matched. 6271 bind(MATCH_SUBSTR_HEAD); 6272 pcmpestri(vec, Address(result, 0), 0x0d); 6273 // Reload only string if does not match 6274 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0 6275 6276 Label CONT_SCAN_SUBSTR; 6277 // Compare the rest of substring (> 8 chars). 6278 bind(FOUND_SUBSTR); 6279 // First 8 chars are already matched. 6280 negptr(cnt2); 6281 addptr(cnt2, 8); 6282 6283 bind(SCAN_SUBSTR); 6284 subl(cnt1, 8); 6285 cmpl(cnt2, -8); // Do not read beyond substring 6286 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); 6287 // Back-up strings to avoid reading beyond substring: 6288 // cnt1 = cnt1 - cnt2 + 8 6289 addl(cnt1, cnt2); // cnt2 is negative 6290 addl(cnt1, 8); 6291 movl(cnt2, 8); negptr(cnt2); 6292 bind(CONT_SCAN_SUBSTR); 6293 if (int_cnt2 < (int)G) { 6294 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2)); 6295 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d); 6296 } else { 6297 // calculate index in register to avoid integer overflow (int_cnt2*2) 6298 movl(tmp, int_cnt2); 6299 addptr(tmp, cnt2); 6300 movdqu(vec, Address(str2, tmp, Address::times_2, 0)); 6301 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d); 6302 } 6303 // Need to reload strings pointers if not matched whole vector 6304 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 6305 addptr(cnt2, 8); 6306 jcc(Assembler::negative, SCAN_SUBSTR); 6307 // Fall through if found full substring 6308 6309 } // (int_cnt2 > 8) 6310 6311 bind(RET_FOUND); 6312 // Found result if we matched full small substring. 6313 // Compute substr offset 6314 subptr(result, str1); 6315 shrl(result, 1); // index 6316 bind(EXIT); 6317 6318 } // string_indexofC8 6319 6320 // Small strings are loaded through stack if they cross page boundary. 6321 void MacroAssembler::string_indexof(Register str1, Register str2, 6322 Register cnt1, Register cnt2, 6323 int int_cnt2, Register result, 6324 XMMRegister vec, Register tmp) { 6325 ShortBranchVerifier sbv(this); 6326 assert(UseSSE42Intrinsics, "SSE4.2 is required"); 6327 // 6328 // int_cnt2 is length of small (< 8 chars) constant substring 6329 // or (-1) for non constant substring in which case its length 6330 // is in cnt2 register. 6331 // 6332 // Note, inline_string_indexOf() generates checks: 6333 // if (substr.count > string.count) return -1; 6334 // if (substr.count == 0) return 0; 6335 // 6336 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0"); 6337 6338 // This method uses pcmpestri instruction with bound registers 6339 // inputs: 6340 // xmm - substring 6341 // rax - substring length (elements count) 6342 // mem - scanned string 6343 // rdx - string length (elements count) 6344 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 6345 // outputs: 6346 // rcx - matched index in string 6347 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 6348 6349 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, 6350 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, 6351 FOUND_CANDIDATE; 6352 6353 { //======================================================== 6354 // We don't know where these strings are located 6355 // and we can't read beyond them. Load them through stack. 6356 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; 6357 6358 movptr(tmp, rsp); // save old SP 6359 6360 if (int_cnt2 > 0) { // small (< 8 chars) constant substring 6361 if (int_cnt2 == 1) { // One char 6362 load_unsigned_short(result, Address(str2, 0)); 6363 movdl(vec, result); // move 32 bits 6364 } else if (int_cnt2 == 2) { // Two chars 6365 movdl(vec, Address(str2, 0)); // move 32 bits 6366 } else if (int_cnt2 == 4) { // Four chars 6367 movq(vec, Address(str2, 0)); // move 64 bits 6368 } else { // cnt2 = { 3, 5, 6, 7 } 6369 // Array header size is 12 bytes in 32-bit VM 6370 // + 6 bytes for 3 chars == 18 bytes, 6371 // enough space to load vec and shift. 6372 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity"); 6373 movdqu(vec, Address(str2, (int_cnt2*2)-16)); 6374 psrldq(vec, 16-(int_cnt2*2)); 6375 } 6376 } else { // not constant substring 6377 cmpl(cnt2, 8); 6378 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough 6379 6380 // We can read beyond string if srt+16 does not cross page boundary 6381 // since heaps are aligned and mapped by pages. 6382 assert(os::vm_page_size() < (int)G, "default page should be small"); 6383 movl(result, str2); // We need only low 32 bits 6384 andl(result, (os::vm_page_size()-1)); 6385 cmpl(result, (os::vm_page_size()-16)); 6386 jccb(Assembler::belowEqual, CHECK_STR); 6387 6388 // Move small strings to stack to allow load 16 bytes into vec. 6389 subptr(rsp, 16); 6390 int stk_offset = wordSize-2; 6391 push(cnt2); 6392 6393 bind(COPY_SUBSTR); 6394 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2)); 6395 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); 6396 decrement(cnt2); 6397 jccb(Assembler::notZero, COPY_SUBSTR); 6398 6399 pop(cnt2); 6400 movptr(str2, rsp); // New substring address 6401 } // non constant 6402 6403 bind(CHECK_STR); 6404 cmpl(cnt1, 8); 6405 jccb(Assembler::aboveEqual, BIG_STRINGS); 6406 6407 // Check cross page boundary. 6408 movl(result, str1); // We need only low 32 bits 6409 andl(result, (os::vm_page_size()-1)); 6410 cmpl(result, (os::vm_page_size()-16)); 6411 jccb(Assembler::belowEqual, BIG_STRINGS); 6412 6413 subptr(rsp, 16); 6414 int stk_offset = -2; 6415 if (int_cnt2 < 0) { // not constant 6416 push(cnt2); 6417 stk_offset += wordSize; 6418 } 6419 movl(cnt2, cnt1); 6420 6421 bind(COPY_STR); 6422 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2)); 6423 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); 6424 decrement(cnt2); 6425 jccb(Assembler::notZero, COPY_STR); 6426 6427 if (int_cnt2 < 0) { // not constant 6428 pop(cnt2); 6429 } 6430 movptr(str1, rsp); // New string address 6431 6432 bind(BIG_STRINGS); 6433 // Load substring. 6434 if (int_cnt2 < 0) { // -1 6435 movdqu(vec, Address(str2, 0)); 6436 push(cnt2); // substr count 6437 push(str2); // substr addr 6438 push(str1); // string addr 6439 } else { 6440 // Small (< 8 chars) constant substrings are loaded already. 6441 movl(cnt2, int_cnt2); 6442 } 6443 push(tmp); // original SP 6444 6445 } // Finished loading 6446 6447 //======================================================== 6448 // Start search 6449 // 6450 6451 movptr(result, str1); // string addr 6452 6453 if (int_cnt2 < 0) { // Only for non constant substring 6454 jmpb(SCAN_TO_SUBSTR); 6455 6456 // SP saved at sp+0 6457 // String saved at sp+1*wordSize 6458 // Substr saved at sp+2*wordSize 6459 // Substr count saved at sp+3*wordSize 6460 6461 // Reload substr for rescan, this code 6462 // is executed only for large substrings (> 8 chars) 6463 bind(RELOAD_SUBSTR); 6464 movptr(str2, Address(rsp, 2*wordSize)); 6465 movl(cnt2, Address(rsp, 3*wordSize)); 6466 movdqu(vec, Address(str2, 0)); 6467 // We came here after the beginning of the substring was 6468 // matched but the rest of it was not so we need to search 6469 // again. Start from the next element after the previous match. 6470 subptr(str1, result); // Restore counter 6471 shrl(str1, 1); 6472 addl(cnt1, str1); 6473 decrementl(cnt1); // Shift to next element 6474 cmpl(cnt1, cnt2); 6475 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 6476 6477 addptr(result, 2); 6478 } // non constant 6479 6480 // Scan string for start of substr in 16-byte vectors 6481 bind(SCAN_TO_SUBSTR); 6482 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 6483 pcmpestri(vec, Address(result, 0), 0x0d); 6484 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 6485 subl(cnt1, 8); 6486 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 6487 cmpl(cnt1, cnt2); 6488 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 6489 addptr(result, 16); 6490 6491 bind(ADJUST_STR); 6492 cmpl(cnt1, 8); // Do not read beyond string 6493 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 6494 // Back-up string to avoid reading beyond string. 6495 lea(result, Address(result, cnt1, Address::times_2, -16)); 6496 movl(cnt1, 8); 6497 jmpb(SCAN_TO_SUBSTR); 6498 6499 // Found a potential substr 6500 bind(FOUND_CANDIDATE); 6501 // After pcmpestri tmp(rcx) contains matched element index 6502 6503 // Make sure string is still long enough 6504 subl(cnt1, tmp); 6505 cmpl(cnt1, cnt2); 6506 jccb(Assembler::greaterEqual, FOUND_SUBSTR); 6507 // Left less then substring. 6508 6509 bind(RET_NOT_FOUND); 6510 movl(result, -1); 6511 jmpb(CLEANUP); 6512 6513 bind(FOUND_SUBSTR); 6514 // Compute start addr of substr 6515 lea(result, Address(result, tmp, Address::times_2)); 6516 6517 if (int_cnt2 > 0) { // Constant substring 6518 // Repeat search for small substring (< 8 chars) 6519 // from new point without reloading substring. 6520 // Have to check that we don't read beyond string. 6521 cmpl(tmp, 8-int_cnt2); 6522 jccb(Assembler::greater, ADJUST_STR); 6523 // Fall through if matched whole substring. 6524 } else { // non constant 6525 assert(int_cnt2 == -1, "should be != 0"); 6526 6527 addl(tmp, cnt2); 6528 // Found result if we matched whole substring. 6529 cmpl(tmp, 8); 6530 jccb(Assembler::lessEqual, RET_FOUND); 6531 6532 // Repeat search for small substring (<= 8 chars) 6533 // from new point 'str1' without reloading substring. 6534 cmpl(cnt2, 8); 6535 // Have to check that we don't read beyond string. 6536 jccb(Assembler::lessEqual, ADJUST_STR); 6537 6538 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; 6539 // Compare the rest of substring (> 8 chars). 6540 movptr(str1, result); 6541 6542 cmpl(tmp, cnt2); 6543 // First 8 chars are already matched. 6544 jccb(Assembler::equal, CHECK_NEXT); 6545 6546 bind(SCAN_SUBSTR); 6547 pcmpestri(vec, Address(str1, 0), 0x0d); 6548 // Need to reload strings pointers if not matched whole vector 6549 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 6550 6551 bind(CHECK_NEXT); 6552 subl(cnt2, 8); 6553 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring 6554 addptr(str1, 16); 6555 addptr(str2, 16); 6556 subl(cnt1, 8); 6557 cmpl(cnt2, 8); // Do not read beyond substring 6558 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); 6559 // Back-up strings to avoid reading beyond substring. 6560 lea(str2, Address(str2, cnt2, Address::times_2, -16)); 6561 lea(str1, Address(str1, cnt2, Address::times_2, -16)); 6562 subl(cnt1, cnt2); 6563 movl(cnt2, 8); 6564 addl(cnt1, 8); 6565 bind(CONT_SCAN_SUBSTR); 6566 movdqu(vec, Address(str2, 0)); 6567 jmpb(SCAN_SUBSTR); 6568 6569 bind(RET_FOUND_LONG); 6570 movptr(str1, Address(rsp, wordSize)); 6571 } // non constant 6572 6573 bind(RET_FOUND); 6574 // Compute substr offset 6575 subptr(result, str1); 6576 shrl(result, 1); // index 6577 6578 bind(CLEANUP); 6579 pop(rsp); // restore SP 6580 6581 } // string_indexof 6582 6583 // Compare strings. 6584 void MacroAssembler::string_compare(Register str1, Register str2, 6585 Register cnt1, Register cnt2, Register result, 6586 XMMRegister vec1) { 6587 ShortBranchVerifier sbv(this); 6588 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; 6589 6590 // Compute the minimum of the string lengths and the 6591 // difference of the string lengths (stack). 6592 // Do the conditional move stuff 6593 movl(result, cnt1); 6594 subl(cnt1, cnt2); 6595 push(cnt1); 6596 cmov32(Assembler::lessEqual, cnt2, result); 6597 6598 // Is the minimum length zero? 6599 testl(cnt2, cnt2); 6600 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 6601 6602 // Compare first characters 6603 load_unsigned_short(result, Address(str1, 0)); 6604 load_unsigned_short(cnt1, Address(str2, 0)); 6605 subl(result, cnt1); 6606 jcc(Assembler::notZero, POP_LABEL); 6607 cmpl(cnt2, 1); 6608 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 6609 6610 // Check if the strings start at the same location. 6611 cmpptr(str1, str2); 6612 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 6613 6614 Address::ScaleFactor scale = Address::times_2; 6615 int stride = 8; 6616 6617 if (UseAVX >= 2 && UseSSE42Intrinsics) { 6618 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR; 6619 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR; 6620 Label COMPARE_TAIL_LONG; 6621 int pcmpmask = 0x19; 6622 6623 // Setup to compare 16-chars (32-bytes) vectors, 6624 // start from first character again because it has aligned address. 6625 int stride2 = 16; 6626 int adr_stride = stride << scale; 6627 6628 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 6629 // rax and rdx are used by pcmpestri as elements counters 6630 movl(result, cnt2); 6631 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count 6632 jcc(Assembler::zero, COMPARE_TAIL_LONG); 6633 6634 // fast path : compare first 2 8-char vectors. 6635 bind(COMPARE_16_CHARS); 6636 movdqu(vec1, Address(str1, 0)); 6637 pcmpestri(vec1, Address(str2, 0), pcmpmask); 6638 jccb(Assembler::below, COMPARE_INDEX_CHAR); 6639 6640 movdqu(vec1, Address(str1, adr_stride)); 6641 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask); 6642 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS); 6643 addl(cnt1, stride); 6644 6645 // Compare the characters at index in cnt1 6646 bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character 6647 load_unsigned_short(result, Address(str1, cnt1, scale)); 6648 load_unsigned_short(cnt2, Address(str2, cnt1, scale)); 6649 subl(result, cnt2); 6650 jmp(POP_LABEL); 6651 6652 // Setup the registers to start vector comparison loop 6653 bind(COMPARE_WIDE_VECTORS); 6654 lea(str1, Address(str1, result, scale)); 6655 lea(str2, Address(str2, result, scale)); 6656 subl(result, stride2); 6657 subl(cnt2, stride2); 6658 jccb(Assembler::zero, COMPARE_WIDE_TAIL); 6659 negptr(result); 6660 6661 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest) 6662 bind(COMPARE_WIDE_VECTORS_LOOP); 6663 vmovdqu(vec1, Address(str1, result, scale)); 6664 vpxor(vec1, Address(str2, result, scale)); 6665 vptest(vec1, vec1); 6666 jccb(Assembler::notZero, VECTOR_NOT_EQUAL); 6667 addptr(result, stride2); 6668 subl(cnt2, stride2); 6669 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP); 6670 // clean upper bits of YMM registers 6671 vpxor(vec1, vec1); 6672 6673 // compare wide vectors tail 6674 bind(COMPARE_WIDE_TAIL); 6675 testptr(result, result); 6676 jccb(Assembler::zero, LENGTH_DIFF_LABEL); 6677 6678 movl(result, stride2); 6679 movl(cnt2, result); 6680 negptr(result); 6681 jmpb(COMPARE_WIDE_VECTORS_LOOP); 6682 6683 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors. 6684 bind(VECTOR_NOT_EQUAL); 6685 // clean upper bits of YMM registers 6686 vpxor(vec1, vec1); 6687 lea(str1, Address(str1, result, scale)); 6688 lea(str2, Address(str2, result, scale)); 6689 jmp(COMPARE_16_CHARS); 6690 6691 // Compare tail chars, length between 1 to 15 chars 6692 bind(COMPARE_TAIL_LONG); 6693 movl(cnt2, result); 6694 cmpl(cnt2, stride); 6695 jccb(Assembler::less, COMPARE_SMALL_STR); 6696 6697 movdqu(vec1, Address(str1, 0)); 6698 pcmpestri(vec1, Address(str2, 0), pcmpmask); 6699 jcc(Assembler::below, COMPARE_INDEX_CHAR); 6700 subptr(cnt2, stride); 6701 jccb(Assembler::zero, LENGTH_DIFF_LABEL); 6702 lea(str1, Address(str1, result, scale)); 6703 lea(str2, Address(str2, result, scale)); 6704 negptr(cnt2); 6705 jmpb(WHILE_HEAD_LABEL); 6706 6707 bind(COMPARE_SMALL_STR); 6708 } else if (UseSSE42Intrinsics) { 6709 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; 6710 int pcmpmask = 0x19; 6711 // Setup to compare 8-char (16-byte) vectors, 6712 // start from first character again because it has aligned address. 6713 movl(result, cnt2); 6714 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count 6715 jccb(Assembler::zero, COMPARE_TAIL); 6716 6717 lea(str1, Address(str1, result, scale)); 6718 lea(str2, Address(str2, result, scale)); 6719 negptr(result); 6720 6721 // pcmpestri 6722 // inputs: 6723 // vec1- substring 6724 // rax - negative string length (elements count) 6725 // mem - scanned string 6726 // rdx - string length (elements count) 6727 // pcmpmask - cmp mode: 11000 (string compare with negated result) 6728 // + 00 (unsigned bytes) or + 01 (unsigned shorts) 6729 // outputs: 6730 // rcx - first mismatched element index 6731 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 6732 6733 bind(COMPARE_WIDE_VECTORS); 6734 movdqu(vec1, Address(str1, result, scale)); 6735 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 6736 // After pcmpestri cnt1(rcx) contains mismatched element index 6737 6738 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 6739 addptr(result, stride); 6740 subptr(cnt2, stride); 6741 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); 6742 6743 // compare wide vectors tail 6744 testptr(result, result); 6745 jccb(Assembler::zero, LENGTH_DIFF_LABEL); 6746 6747 movl(cnt2, stride); 6748 movl(result, stride); 6749 negptr(result); 6750 movdqu(vec1, Address(str1, result, scale)); 6751 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 6752 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); 6753 6754 // Mismatched characters in the vectors 6755 bind(VECTOR_NOT_EQUAL); 6756 addptr(cnt1, result); 6757 load_unsigned_short(result, Address(str1, cnt1, scale)); 6758 load_unsigned_short(cnt2, Address(str2, cnt1, scale)); 6759 subl(result, cnt2); 6760 jmpb(POP_LABEL); 6761 6762 bind(COMPARE_TAIL); // limit is zero 6763 movl(cnt2, result); 6764 // Fallthru to tail compare 6765 } 6766 // Shift str2 and str1 to the end of the arrays, negate min 6767 lea(str1, Address(str1, cnt2, scale)); 6768 lea(str2, Address(str2, cnt2, scale)); 6769 decrementl(cnt2); // first character was compared already 6770 negptr(cnt2); 6771 6772 // Compare the rest of the elements 6773 bind(WHILE_HEAD_LABEL); 6774 load_unsigned_short(result, Address(str1, cnt2, scale, 0)); 6775 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0)); 6776 subl(result, cnt1); 6777 jccb(Assembler::notZero, POP_LABEL); 6778 increment(cnt2); 6779 jccb(Assembler::notZero, WHILE_HEAD_LABEL); 6780 6781 // Strings are equal up to min length. Return the length difference. 6782 bind(LENGTH_DIFF_LABEL); 6783 pop(result); 6784 jmpb(DONE_LABEL); 6785 6786 // Discard the stored length difference 6787 bind(POP_LABEL); 6788 pop(cnt1); 6789 6790 // That's it 6791 bind(DONE_LABEL); 6792 } 6793 6794 // Compare char[] arrays aligned to 4 bytes or substrings. 6795 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, 6796 Register limit, Register result, Register chr, 6797 XMMRegister vec1, XMMRegister vec2) { 6798 ShortBranchVerifier sbv(this); 6799 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; 6800 6801 int length_offset = arrayOopDesc::length_offset_in_bytes(); 6802 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 6803 6804 // Check the input args 6805 cmpptr(ary1, ary2); 6806 jcc(Assembler::equal, TRUE_LABEL); 6807 6808 if (is_array_equ) { 6809 // Need additional checks for arrays_equals. 6810 testptr(ary1, ary1); 6811 jcc(Assembler::zero, FALSE_LABEL); 6812 testptr(ary2, ary2); 6813 jcc(Assembler::zero, FALSE_LABEL); 6814 6815 // Check the lengths 6816 movl(limit, Address(ary1, length_offset)); 6817 cmpl(limit, Address(ary2, length_offset)); 6818 jcc(Assembler::notEqual, FALSE_LABEL); 6819 } 6820 6821 // count == 0 6822 testl(limit, limit); 6823 jcc(Assembler::zero, TRUE_LABEL); 6824 6825 if (is_array_equ) { 6826 // Load array address 6827 lea(ary1, Address(ary1, base_offset)); 6828 lea(ary2, Address(ary2, base_offset)); 6829 } 6830 6831 shll(limit, 1); // byte count != 0 6832 movl(result, limit); // copy 6833 6834 if (UseAVX >= 2) { 6835 // With AVX2, use 32-byte vector compare 6836 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 6837 6838 // Compare 32-byte vectors 6839 andl(result, 0x0000001e); // tail count (in bytes) 6840 andl(limit, 0xffffffe0); // vector count (in bytes) 6841 jccb(Assembler::zero, COMPARE_TAIL); 6842 6843 lea(ary1, Address(ary1, limit, Address::times_1)); 6844 lea(ary2, Address(ary2, limit, Address::times_1)); 6845 negptr(limit); 6846 6847 bind(COMPARE_WIDE_VECTORS); 6848 vmovdqu(vec1, Address(ary1, limit, Address::times_1)); 6849 vmovdqu(vec2, Address(ary2, limit, Address::times_1)); 6850 vpxor(vec1, vec2); 6851 6852 vptest(vec1, vec1); 6853 jccb(Assembler::notZero, FALSE_LABEL); 6854 addptr(limit, 32); 6855 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 6856 6857 testl(result, result); 6858 jccb(Assembler::zero, TRUE_LABEL); 6859 6860 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 6861 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32)); 6862 vpxor(vec1, vec2); 6863 6864 vptest(vec1, vec1); 6865 jccb(Assembler::notZero, FALSE_LABEL); 6866 jmpb(TRUE_LABEL); 6867 6868 bind(COMPARE_TAIL); // limit is zero 6869 movl(limit, result); 6870 // Fallthru to tail compare 6871 } else if (UseSSE42Intrinsics) { 6872 // With SSE4.2, use double quad vector compare 6873 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 6874 6875 // Compare 16-byte vectors 6876 andl(result, 0x0000000e); // tail count (in bytes) 6877 andl(limit, 0xfffffff0); // vector count (in bytes) 6878 jccb(Assembler::zero, COMPARE_TAIL); 6879 6880 lea(ary1, Address(ary1, limit, Address::times_1)); 6881 lea(ary2, Address(ary2, limit, Address::times_1)); 6882 negptr(limit); 6883 6884 bind(COMPARE_WIDE_VECTORS); 6885 movdqu(vec1, Address(ary1, limit, Address::times_1)); 6886 movdqu(vec2, Address(ary2, limit, Address::times_1)); 6887 pxor(vec1, vec2); 6888 6889 ptest(vec1, vec1); 6890 jccb(Assembler::notZero, FALSE_LABEL); 6891 addptr(limit, 16); 6892 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 6893 6894 testl(result, result); 6895 jccb(Assembler::zero, TRUE_LABEL); 6896 6897 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 6898 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); 6899 pxor(vec1, vec2); 6900 6901 ptest(vec1, vec1); 6902 jccb(Assembler::notZero, FALSE_LABEL); 6903 jmpb(TRUE_LABEL); 6904 6905 bind(COMPARE_TAIL); // limit is zero 6906 movl(limit, result); 6907 // Fallthru to tail compare 6908 } 6909 6910 // Compare 4-byte vectors 6911 andl(limit, 0xfffffffc); // vector count (in bytes) 6912 jccb(Assembler::zero, COMPARE_CHAR); 6913 6914 lea(ary1, Address(ary1, limit, Address::times_1)); 6915 lea(ary2, Address(ary2, limit, Address::times_1)); 6916 negptr(limit); 6917 6918 bind(COMPARE_VECTORS); 6919 movl(chr, Address(ary1, limit, Address::times_1)); 6920 cmpl(chr, Address(ary2, limit, Address::times_1)); 6921 jccb(Assembler::notEqual, FALSE_LABEL); 6922 addptr(limit, 4); 6923 jcc(Assembler::notZero, COMPARE_VECTORS); 6924 6925 // Compare trailing char (final 2 bytes), if any 6926 bind(COMPARE_CHAR); 6927 testl(result, 0x2); // tail char 6928 jccb(Assembler::zero, TRUE_LABEL); 6929 load_unsigned_short(chr, Address(ary1, 0)); 6930 load_unsigned_short(limit, Address(ary2, 0)); 6931 cmpl(chr, limit); 6932 jccb(Assembler::notEqual, FALSE_LABEL); 6933 6934 bind(TRUE_LABEL); 6935 movl(result, 1); // return true 6936 jmpb(DONE); 6937 6938 bind(FALSE_LABEL); 6939 xorl(result, result); // return false 6940 6941 // That's it 6942 bind(DONE); 6943 if (UseAVX >= 2) { 6944 // clean upper bits of YMM registers 6945 vpxor(vec1, vec1); 6946 vpxor(vec2, vec2); 6947 } 6948 } 6949 6950 void MacroAssembler::generate_fill(BasicType t, bool aligned, 6951 Register to, Register value, Register count, 6952 Register rtmp, XMMRegister xtmp) { 6953 ShortBranchVerifier sbv(this); 6954 assert_different_registers(to, value, count, rtmp); 6955 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; 6956 Label L_fill_2_bytes, L_fill_4_bytes; 6957 6958 int shift = -1; 6959 switch (t) { 6960 case T_BYTE: 6961 shift = 2; 6962 break; 6963 case T_SHORT: 6964 shift = 1; 6965 break; 6966 case T_INT: 6967 shift = 0; 6968 break; 6969 default: ShouldNotReachHere(); 6970 } 6971 6972 if (t == T_BYTE) { 6973 andl(value, 0xff); 6974 movl(rtmp, value); 6975 shll(rtmp, 8); 6976 orl(value, rtmp); 6977 } 6978 if (t == T_SHORT) { 6979 andl(value, 0xffff); 6980 } 6981 if (t == T_BYTE || t == T_SHORT) { 6982 movl(rtmp, value); 6983 shll(rtmp, 16); 6984 orl(value, rtmp); 6985 } 6986 6987 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element 6988 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp 6989 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { 6990 // align source address at 4 bytes address boundary 6991 if (t == T_BYTE) { 6992 // One byte misalignment happens only for byte arrays 6993 testptr(to, 1); 6994 jccb(Assembler::zero, L_skip_align1); 6995 movb(Address(to, 0), value); 6996 increment(to); 6997 decrement(count); 6998 BIND(L_skip_align1); 6999 } 7000 // Two bytes misalignment happens only for byte and short (char) arrays 7001 testptr(to, 2); 7002 jccb(Assembler::zero, L_skip_align2); 7003 movw(Address(to, 0), value); 7004 addptr(to, 2); 7005 subl(count, 1<<(shift-1)); 7006 BIND(L_skip_align2); 7007 } 7008 if (UseSSE < 2) { 7009 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 7010 // Fill 32-byte chunks 7011 subl(count, 8 << shift); 7012 jcc(Assembler::less, L_check_fill_8_bytes); 7013 align(16); 7014 7015 BIND(L_fill_32_bytes_loop); 7016 7017 for (int i = 0; i < 32; i += 4) { 7018 movl(Address(to, i), value); 7019 } 7020 7021 addptr(to, 32); 7022 subl(count, 8 << shift); 7023 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 7024 BIND(L_check_fill_8_bytes); 7025 addl(count, 8 << shift); 7026 jccb(Assembler::zero, L_exit); 7027 jmpb(L_fill_8_bytes); 7028 7029 // 7030 // length is too short, just fill qwords 7031 // 7032 BIND(L_fill_8_bytes_loop); 7033 movl(Address(to, 0), value); 7034 movl(Address(to, 4), value); 7035 addptr(to, 8); 7036 BIND(L_fill_8_bytes); 7037 subl(count, 1 << (shift + 1)); 7038 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 7039 // fall through to fill 4 bytes 7040 } else { 7041 Label L_fill_32_bytes; 7042 if (!UseUnalignedLoadStores) { 7043 // align to 8 bytes, we know we are 4 byte aligned to start 7044 testptr(to, 4); 7045 jccb(Assembler::zero, L_fill_32_bytes); 7046 movl(Address(to, 0), value); 7047 addptr(to, 4); 7048 subl(count, 1<<shift); 7049 } 7050 BIND(L_fill_32_bytes); 7051 { 7052 assert( UseSSE >= 2, "supported cpu only" ); 7053 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 7054 if (UseAVX > 2) { 7055 movl(rtmp, 0xffff); 7056 #ifdef _LP64 7057 kmovql(k1, rtmp); 7058 #else 7059 kmovdl(k1, rtmp); 7060 #endif 7061 } 7062 movdl(xtmp, value); 7063 if (UseAVX > 2 && UseUnalignedLoadStores) { 7064 // Fill 64-byte chunks 7065 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 7066 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit); 7067 7068 subl(count, 16 << shift); 7069 jcc(Assembler::less, L_check_fill_32_bytes); 7070 align(16); 7071 7072 BIND(L_fill_64_bytes_loop); 7073 evmovdqu(Address(to, 0), xtmp, Assembler::AVX_512bit); 7074 addptr(to, 64); 7075 subl(count, 16 << shift); 7076 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 7077 7078 BIND(L_check_fill_32_bytes); 7079 addl(count, 8 << shift); 7080 jccb(Assembler::less, L_check_fill_8_bytes); 7081 evmovdqu(Address(to, 0), xtmp, Assembler::AVX_256bit); 7082 addptr(to, 32); 7083 subl(count, 8 << shift); 7084 7085 BIND(L_check_fill_8_bytes); 7086 } else if (UseAVX == 2 && UseUnalignedLoadStores) { 7087 // Fill 64-byte chunks 7088 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 7089 vpbroadcastd(xtmp, xtmp); 7090 7091 subl(count, 16 << shift); 7092 jcc(Assembler::less, L_check_fill_32_bytes); 7093 align(16); 7094 7095 BIND(L_fill_64_bytes_loop); 7096 vmovdqu(Address(to, 0), xtmp); 7097 vmovdqu(Address(to, 32), xtmp); 7098 addptr(to, 64); 7099 subl(count, 16 << shift); 7100 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 7101 7102 BIND(L_check_fill_32_bytes); 7103 addl(count, 8 << shift); 7104 jccb(Assembler::less, L_check_fill_8_bytes); 7105 vmovdqu(Address(to, 0), xtmp); 7106 addptr(to, 32); 7107 subl(count, 8 << shift); 7108 7109 BIND(L_check_fill_8_bytes); 7110 // clean upper bits of YMM registers 7111 movdl(xtmp, value); 7112 pshufd(xtmp, xtmp, 0); 7113 } else { 7114 // Fill 32-byte chunks 7115 pshufd(xtmp, xtmp, 0); 7116 7117 subl(count, 8 << shift); 7118 jcc(Assembler::less, L_check_fill_8_bytes); 7119 align(16); 7120 7121 BIND(L_fill_32_bytes_loop); 7122 7123 if (UseUnalignedLoadStores) { 7124 movdqu(Address(to, 0), xtmp); 7125 movdqu(Address(to, 16), xtmp); 7126 } else { 7127 movq(Address(to, 0), xtmp); 7128 movq(Address(to, 8), xtmp); 7129 movq(Address(to, 16), xtmp); 7130 movq(Address(to, 24), xtmp); 7131 } 7132 7133 addptr(to, 32); 7134 subl(count, 8 << shift); 7135 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 7136 7137 BIND(L_check_fill_8_bytes); 7138 } 7139 addl(count, 8 << shift); 7140 jccb(Assembler::zero, L_exit); 7141 jmpb(L_fill_8_bytes); 7142 7143 // 7144 // length is too short, just fill qwords 7145 // 7146 BIND(L_fill_8_bytes_loop); 7147 movq(Address(to, 0), xtmp); 7148 addptr(to, 8); 7149 BIND(L_fill_8_bytes); 7150 subl(count, 1 << (shift + 1)); 7151 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 7152 } 7153 } 7154 // fill trailing 4 bytes 7155 BIND(L_fill_4_bytes); 7156 testl(count, 1<<shift); 7157 jccb(Assembler::zero, L_fill_2_bytes); 7158 movl(Address(to, 0), value); 7159 if (t == T_BYTE || t == T_SHORT) { 7160 addptr(to, 4); 7161 BIND(L_fill_2_bytes); 7162 // fill trailing 2 bytes 7163 testl(count, 1<<(shift-1)); 7164 jccb(Assembler::zero, L_fill_byte); 7165 movw(Address(to, 0), value); 7166 if (t == T_BYTE) { 7167 addptr(to, 2); 7168 BIND(L_fill_byte); 7169 // fill trailing byte 7170 testl(count, 1); 7171 jccb(Assembler::zero, L_exit); 7172 movb(Address(to, 0), value); 7173 } else { 7174 BIND(L_fill_byte); 7175 } 7176 } else { 7177 BIND(L_fill_2_bytes); 7178 } 7179 BIND(L_exit); 7180 } 7181 7182 // encode char[] to byte[] in ISO_8859_1 7183 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len, 7184 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 7185 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 7186 Register tmp5, Register result) { 7187 // rsi: src 7188 // rdi: dst 7189 // rdx: len 7190 // rcx: tmp5 7191 // rax: result 7192 ShortBranchVerifier sbv(this); 7193 assert_different_registers(src, dst, len, tmp5, result); 7194 Label L_done, L_copy_1_char, L_copy_1_char_exit; 7195 7196 // set result 7197 xorl(result, result); 7198 // check for zero length 7199 testl(len, len); 7200 jcc(Assembler::zero, L_done); 7201 movl(result, len); 7202 7203 // Setup pointers 7204 lea(src, Address(src, len, Address::times_2)); // char[] 7205 lea(dst, Address(dst, len, Address::times_1)); // byte[] 7206 negptr(len); 7207 7208 if (UseSSE42Intrinsics || UseAVX >= 2) { 7209 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit; 7210 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit; 7211 7212 if (UseAVX >= 2) { 7213 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit; 7214 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 7215 movdl(tmp1Reg, tmp5); 7216 vpbroadcastd(tmp1Reg, tmp1Reg); 7217 jmpb(L_chars_32_check); 7218 7219 bind(L_copy_32_chars); 7220 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64)); 7221 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32)); 7222 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 7223 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 7224 jccb(Assembler::notZero, L_copy_32_chars_exit); 7225 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 7226 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1); 7227 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg); 7228 7229 bind(L_chars_32_check); 7230 addptr(len, 32); 7231 jccb(Assembler::lessEqual, L_copy_32_chars); 7232 7233 bind(L_copy_32_chars_exit); 7234 subptr(len, 16); 7235 jccb(Assembler::greater, L_copy_16_chars_exit); 7236 7237 } else if (UseSSE42Intrinsics) { 7238 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 7239 movdl(tmp1Reg, tmp5); 7240 pshufd(tmp1Reg, tmp1Reg, 0); 7241 jmpb(L_chars_16_check); 7242 } 7243 7244 bind(L_copy_16_chars); 7245 if (UseAVX >= 2) { 7246 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32)); 7247 vptest(tmp2Reg, tmp1Reg); 7248 jccb(Assembler::notZero, L_copy_16_chars_exit); 7249 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1); 7250 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1); 7251 } else { 7252 if (UseAVX > 0) { 7253 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 7254 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 7255 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0); 7256 } else { 7257 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 7258 por(tmp2Reg, tmp3Reg); 7259 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 7260 por(tmp2Reg, tmp4Reg); 7261 } 7262 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 7263 jccb(Assembler::notZero, L_copy_16_chars_exit); 7264 packuswb(tmp3Reg, tmp4Reg); 7265 } 7266 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg); 7267 7268 bind(L_chars_16_check); 7269 addptr(len, 16); 7270 jccb(Assembler::lessEqual, L_copy_16_chars); 7271 7272 bind(L_copy_16_chars_exit); 7273 if (UseAVX >= 2) { 7274 // clean upper bits of YMM registers 7275 vpxor(tmp2Reg, tmp2Reg); 7276 vpxor(tmp3Reg, tmp3Reg); 7277 vpxor(tmp4Reg, tmp4Reg); 7278 movdl(tmp1Reg, tmp5); 7279 pshufd(tmp1Reg, tmp1Reg, 0); 7280 } 7281 subptr(len, 8); 7282 jccb(Assembler::greater, L_copy_8_chars_exit); 7283 7284 bind(L_copy_8_chars); 7285 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16)); 7286 ptest(tmp3Reg, tmp1Reg); 7287 jccb(Assembler::notZero, L_copy_8_chars_exit); 7288 packuswb(tmp3Reg, tmp1Reg); 7289 movq(Address(dst, len, Address::times_1, -8), tmp3Reg); 7290 addptr(len, 8); 7291 jccb(Assembler::lessEqual, L_copy_8_chars); 7292 7293 bind(L_copy_8_chars_exit); 7294 subptr(len, 8); 7295 jccb(Assembler::zero, L_done); 7296 } 7297 7298 bind(L_copy_1_char); 7299 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0)); 7300 testl(tmp5, 0xff00); // check if Unicode char 7301 jccb(Assembler::notZero, L_copy_1_char_exit); 7302 movb(Address(dst, len, Address::times_1, 0), tmp5); 7303 addptr(len, 1); 7304 jccb(Assembler::less, L_copy_1_char); 7305 7306 bind(L_copy_1_char_exit); 7307 addptr(result, len); // len is negative count of not processed elements 7308 bind(L_done); 7309 } 7310 7311 #ifdef _LP64 7312 /** 7313 * Helper for multiply_to_len(). 7314 */ 7315 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 7316 addq(dest_lo, src1); 7317 adcq(dest_hi, 0); 7318 addq(dest_lo, src2); 7319 adcq(dest_hi, 0); 7320 } 7321 7322 /** 7323 * Multiply 64 bit by 64 bit first loop. 7324 */ 7325 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 7326 Register y, Register y_idx, Register z, 7327 Register carry, Register product, 7328 Register idx, Register kdx) { 7329 // 7330 // jlong carry, x[], y[], z[]; 7331 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 7332 // huge_128 product = y[idx] * x[xstart] + carry; 7333 // z[kdx] = (jlong)product; 7334 // carry = (jlong)(product >>> 64); 7335 // } 7336 // z[xstart] = carry; 7337 // 7338 7339 Label L_first_loop, L_first_loop_exit; 7340 Label L_one_x, L_one_y, L_multiply; 7341 7342 decrementl(xstart); 7343 jcc(Assembler::negative, L_one_x); 7344 7345 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 7346 rorq(x_xstart, 32); // convert big-endian to little-endian 7347 7348 bind(L_first_loop); 7349 decrementl(idx); 7350 jcc(Assembler::negative, L_first_loop_exit); 7351 decrementl(idx); 7352 jcc(Assembler::negative, L_one_y); 7353 movq(y_idx, Address(y, idx, Address::times_4, 0)); 7354 rorq(y_idx, 32); // convert big-endian to little-endian 7355 bind(L_multiply); 7356 movq(product, x_xstart); 7357 mulq(y_idx); // product(rax) * y_idx -> rdx:rax 7358 addq(product, carry); 7359 adcq(rdx, 0); 7360 subl(kdx, 2); 7361 movl(Address(z, kdx, Address::times_4, 4), product); 7362 shrq(product, 32); 7363 movl(Address(z, kdx, Address::times_4, 0), product); 7364 movq(carry, rdx); 7365 jmp(L_first_loop); 7366 7367 bind(L_one_y); 7368 movl(y_idx, Address(y, 0)); 7369 jmp(L_multiply); 7370 7371 bind(L_one_x); 7372 movl(x_xstart, Address(x, 0)); 7373 jmp(L_first_loop); 7374 7375 bind(L_first_loop_exit); 7376 } 7377 7378 /** 7379 * Multiply 64 bit by 64 bit and add 128 bit. 7380 */ 7381 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z, 7382 Register yz_idx, Register idx, 7383 Register carry, Register product, int offset) { 7384 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry; 7385 // z[kdx] = (jlong)product; 7386 7387 movq(yz_idx, Address(y, idx, Address::times_4, offset)); 7388 rorq(yz_idx, 32); // convert big-endian to little-endian 7389 movq(product, x_xstart); 7390 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 7391 movq(yz_idx, Address(z, idx, Address::times_4, offset)); 7392 rorq(yz_idx, 32); // convert big-endian to little-endian 7393 7394 add2_with_carry(rdx, product, carry, yz_idx); 7395 7396 movl(Address(z, idx, Address::times_4, offset+4), product); 7397 shrq(product, 32); 7398 movl(Address(z, idx, Address::times_4, offset), product); 7399 7400 } 7401 7402 /** 7403 * Multiply 128 bit by 128 bit. Unrolled inner loop. 7404 */ 7405 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 7406 Register yz_idx, Register idx, Register jdx, 7407 Register carry, Register product, 7408 Register carry2) { 7409 // jlong carry, x[], y[], z[]; 7410 // int kdx = ystart+1; 7411 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 7412 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry; 7413 // z[kdx+idx+1] = (jlong)product; 7414 // jlong carry2 = (jlong)(product >>> 64); 7415 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2; 7416 // z[kdx+idx] = (jlong)product; 7417 // carry = (jlong)(product >>> 64); 7418 // } 7419 // idx += 2; 7420 // if (idx > 0) { 7421 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry; 7422 // z[kdx+idx] = (jlong)product; 7423 // carry = (jlong)(product >>> 64); 7424 // } 7425 // 7426 7427 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 7428 7429 movl(jdx, idx); 7430 andl(jdx, 0xFFFFFFFC); 7431 shrl(jdx, 2); 7432 7433 bind(L_third_loop); 7434 subl(jdx, 1); 7435 jcc(Assembler::negative, L_third_loop_exit); 7436 subl(idx, 4); 7437 7438 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8); 7439 movq(carry2, rdx); 7440 7441 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0); 7442 movq(carry, rdx); 7443 jmp(L_third_loop); 7444 7445 bind (L_third_loop_exit); 7446 7447 andl (idx, 0x3); 7448 jcc(Assembler::zero, L_post_third_loop_done); 7449 7450 Label L_check_1; 7451 subl(idx, 2); 7452 jcc(Assembler::negative, L_check_1); 7453 7454 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0); 7455 movq(carry, rdx); 7456 7457 bind (L_check_1); 7458 addl (idx, 0x2); 7459 andl (idx, 0x1); 7460 subl(idx, 1); 7461 jcc(Assembler::negative, L_post_third_loop_done); 7462 7463 movl(yz_idx, Address(y, idx, Address::times_4, 0)); 7464 movq(product, x_xstart); 7465 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 7466 movl(yz_idx, Address(z, idx, Address::times_4, 0)); 7467 7468 add2_with_carry(rdx, product, yz_idx, carry); 7469 7470 movl(Address(z, idx, Address::times_4, 0), product); 7471 shrq(product, 32); 7472 7473 shlq(rdx, 32); 7474 orq(product, rdx); 7475 movq(carry, product); 7476 7477 bind(L_post_third_loop_done); 7478 } 7479 7480 /** 7481 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop. 7482 * 7483 */ 7484 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z, 7485 Register carry, Register carry2, 7486 Register idx, Register jdx, 7487 Register yz_idx1, Register yz_idx2, 7488 Register tmp, Register tmp3, Register tmp4) { 7489 assert(UseBMI2Instructions, "should be used only when BMI2 is available"); 7490 7491 // jlong carry, x[], y[], z[]; 7492 // int kdx = ystart+1; 7493 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 7494 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry; 7495 // jlong carry2 = (jlong)(tmp3 >>> 64); 7496 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2; 7497 // carry = (jlong)(tmp4 >>> 64); 7498 // z[kdx+idx+1] = (jlong)tmp3; 7499 // z[kdx+idx] = (jlong)tmp4; 7500 // } 7501 // idx += 2; 7502 // if (idx > 0) { 7503 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry; 7504 // z[kdx+idx] = (jlong)yz_idx1; 7505 // carry = (jlong)(yz_idx1 >>> 64); 7506 // } 7507 // 7508 7509 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 7510 7511 movl(jdx, idx); 7512 andl(jdx, 0xFFFFFFFC); 7513 shrl(jdx, 2); 7514 7515 bind(L_third_loop); 7516 subl(jdx, 1); 7517 jcc(Assembler::negative, L_third_loop_exit); 7518 subl(idx, 4); 7519 7520 movq(yz_idx1, Address(y, idx, Address::times_4, 8)); 7521 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 7522 movq(yz_idx2, Address(y, idx, Address::times_4, 0)); 7523 rorxq(yz_idx2, yz_idx2, 32); 7524 7525 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 7526 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp 7527 7528 movq(yz_idx1, Address(z, idx, Address::times_4, 8)); 7529 rorxq(yz_idx1, yz_idx1, 32); 7530 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 7531 rorxq(yz_idx2, yz_idx2, 32); 7532 7533 if (VM_Version::supports_adx()) { 7534 adcxq(tmp3, carry); 7535 adoxq(tmp3, yz_idx1); 7536 7537 adcxq(tmp4, tmp); 7538 adoxq(tmp4, yz_idx2); 7539 7540 movl(carry, 0); // does not affect flags 7541 adcxq(carry2, carry); 7542 adoxq(carry2, carry); 7543 } else { 7544 add2_with_carry(tmp4, tmp3, carry, yz_idx1); 7545 add2_with_carry(carry2, tmp4, tmp, yz_idx2); 7546 } 7547 movq(carry, carry2); 7548 7549 movl(Address(z, idx, Address::times_4, 12), tmp3); 7550 shrq(tmp3, 32); 7551 movl(Address(z, idx, Address::times_4, 8), tmp3); 7552 7553 movl(Address(z, idx, Address::times_4, 4), tmp4); 7554 shrq(tmp4, 32); 7555 movl(Address(z, idx, Address::times_4, 0), tmp4); 7556 7557 jmp(L_third_loop); 7558 7559 bind (L_third_loop_exit); 7560 7561 andl (idx, 0x3); 7562 jcc(Assembler::zero, L_post_third_loop_done); 7563 7564 Label L_check_1; 7565 subl(idx, 2); 7566 jcc(Assembler::negative, L_check_1); 7567 7568 movq(yz_idx1, Address(y, idx, Address::times_4, 0)); 7569 rorxq(yz_idx1, yz_idx1, 32); 7570 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 7571 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 7572 rorxq(yz_idx2, yz_idx2, 32); 7573 7574 add2_with_carry(tmp4, tmp3, carry, yz_idx2); 7575 7576 movl(Address(z, idx, Address::times_4, 4), tmp3); 7577 shrq(tmp3, 32); 7578 movl(Address(z, idx, Address::times_4, 0), tmp3); 7579 movq(carry, tmp4); 7580 7581 bind (L_check_1); 7582 addl (idx, 0x2); 7583 andl (idx, 0x1); 7584 subl(idx, 1); 7585 jcc(Assembler::negative, L_post_third_loop_done); 7586 movl(tmp4, Address(y, idx, Address::times_4, 0)); 7587 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3 7588 movl(tmp4, Address(z, idx, Address::times_4, 0)); 7589 7590 add2_with_carry(carry2, tmp3, tmp4, carry); 7591 7592 movl(Address(z, idx, Address::times_4, 0), tmp3); 7593 shrq(tmp3, 32); 7594 7595 shlq(carry2, 32); 7596 orq(tmp3, carry2); 7597 movq(carry, tmp3); 7598 7599 bind(L_post_third_loop_done); 7600 } 7601 7602 /** 7603 * Code for BigInteger::multiplyToLen() instrinsic. 7604 * 7605 * rdi: x 7606 * rax: xlen 7607 * rsi: y 7608 * rcx: ylen 7609 * r8: z 7610 * r11: zlen 7611 * r12: tmp1 7612 * r13: tmp2 7613 * r14: tmp3 7614 * r15: tmp4 7615 * rbx: tmp5 7616 * 7617 */ 7618 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 7619 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) { 7620 ShortBranchVerifier sbv(this); 7621 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx); 7622 7623 push(tmp1); 7624 push(tmp2); 7625 push(tmp3); 7626 push(tmp4); 7627 push(tmp5); 7628 7629 push(xlen); 7630 push(zlen); 7631 7632 const Register idx = tmp1; 7633 const Register kdx = tmp2; 7634 const Register xstart = tmp3; 7635 7636 const Register y_idx = tmp4; 7637 const Register carry = tmp5; 7638 const Register product = xlen; 7639 const Register x_xstart = zlen; // reuse register 7640 7641 // First Loop. 7642 // 7643 // final static long LONG_MASK = 0xffffffffL; 7644 // int xstart = xlen - 1; 7645 // int ystart = ylen - 1; 7646 // long carry = 0; 7647 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 7648 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 7649 // z[kdx] = (int)product; 7650 // carry = product >>> 32; 7651 // } 7652 // z[xstart] = (int)carry; 7653 // 7654 7655 movl(idx, ylen); // idx = ylen; 7656 movl(kdx, zlen); // kdx = xlen+ylen; 7657 xorq(carry, carry); // carry = 0; 7658 7659 Label L_done; 7660 7661 movl(xstart, xlen); 7662 decrementl(xstart); 7663 jcc(Assembler::negative, L_done); 7664 7665 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 7666 7667 Label L_second_loop; 7668 testl(kdx, kdx); 7669 jcc(Assembler::zero, L_second_loop); 7670 7671 Label L_carry; 7672 subl(kdx, 1); 7673 jcc(Assembler::zero, L_carry); 7674 7675 movl(Address(z, kdx, Address::times_4, 0), carry); 7676 shrq(carry, 32); 7677 subl(kdx, 1); 7678 7679 bind(L_carry); 7680 movl(Address(z, kdx, Address::times_4, 0), carry); 7681 7682 // Second and third (nested) loops. 7683 // 7684 // for (int i = xstart-1; i >= 0; i--) { // Second loop 7685 // carry = 0; 7686 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 7687 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 7688 // (z[k] & LONG_MASK) + carry; 7689 // z[k] = (int)product; 7690 // carry = product >>> 32; 7691 // } 7692 // z[i] = (int)carry; 7693 // } 7694 // 7695 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx 7696 7697 const Register jdx = tmp1; 7698 7699 bind(L_second_loop); 7700 xorl(carry, carry); // carry = 0; 7701 movl(jdx, ylen); // j = ystart+1 7702 7703 subl(xstart, 1); // i = xstart-1; 7704 jcc(Assembler::negative, L_done); 7705 7706 push (z); 7707 7708 Label L_last_x; 7709 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j 7710 subl(xstart, 1); // i = xstart-1; 7711 jcc(Assembler::negative, L_last_x); 7712 7713 if (UseBMI2Instructions) { 7714 movq(rdx, Address(x, xstart, Address::times_4, 0)); 7715 rorxq(rdx, rdx, 32); // convert big-endian to little-endian 7716 } else { 7717 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 7718 rorq(x_xstart, 32); // convert big-endian to little-endian 7719 } 7720 7721 Label L_third_loop_prologue; 7722 bind(L_third_loop_prologue); 7723 7724 push (x); 7725 push (xstart); 7726 push (ylen); 7727 7728 7729 if (UseBMI2Instructions) { 7730 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4); 7731 } else { // !UseBMI2Instructions 7732 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x); 7733 } 7734 7735 pop(ylen); 7736 pop(xlen); 7737 pop(x); 7738 pop(z); 7739 7740 movl(tmp3, xlen); 7741 addl(tmp3, 1); 7742 movl(Address(z, tmp3, Address::times_4, 0), carry); 7743 subl(tmp3, 1); 7744 jccb(Assembler::negative, L_done); 7745 7746 shrq(carry, 32); 7747 movl(Address(z, tmp3, Address::times_4, 0), carry); 7748 jmp(L_second_loop); 7749 7750 // Next infrequent code is moved outside loops. 7751 bind(L_last_x); 7752 if (UseBMI2Instructions) { 7753 movl(rdx, Address(x, 0)); 7754 } else { 7755 movl(x_xstart, Address(x, 0)); 7756 } 7757 jmp(L_third_loop_prologue); 7758 7759 bind(L_done); 7760 7761 pop(zlen); 7762 pop(xlen); 7763 7764 pop(tmp5); 7765 pop(tmp4); 7766 pop(tmp3); 7767 pop(tmp2); 7768 pop(tmp1); 7769 } 7770 7771 //Helper functions for square_to_len() 7772 7773 /** 7774 * Store the squares of x[], right shifted one bit (divided by 2) into z[] 7775 * Preserves x and z and modifies rest of the registers. 7776 */ 7777 7778 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 7779 // Perform square and right shift by 1 7780 // Handle odd xlen case first, then for even xlen do the following 7781 // jlong carry = 0; 7782 // for (int j=0, i=0; j < xlen; j+=2, i+=4) { 7783 // huge_128 product = x[j:j+1] * x[j:j+1]; 7784 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65); 7785 // z[i+2:i+3] = (jlong)(product >>> 1); 7786 // carry = (jlong)product; 7787 // } 7788 7789 xorq(tmp5, tmp5); // carry 7790 xorq(rdxReg, rdxReg); 7791 xorl(tmp1, tmp1); // index for x 7792 xorl(tmp4, tmp4); // index for z 7793 7794 Label L_first_loop, L_first_loop_exit; 7795 7796 testl(xlen, 1); 7797 jccb(Assembler::zero, L_first_loop); //jump if xlen is even 7798 7799 // Square and right shift by 1 the odd element using 32 bit multiply 7800 movl(raxReg, Address(x, tmp1, Address::times_4, 0)); 7801 imulq(raxReg, raxReg); 7802 shrq(raxReg, 1); 7803 adcq(tmp5, 0); 7804 movq(Address(z, tmp4, Address::times_4, 0), raxReg); 7805 incrementl(tmp1); 7806 addl(tmp4, 2); 7807 7808 // Square and right shift by 1 the rest using 64 bit multiply 7809 bind(L_first_loop); 7810 cmpptr(tmp1, xlen); 7811 jccb(Assembler::equal, L_first_loop_exit); 7812 7813 // Square 7814 movq(raxReg, Address(x, tmp1, Address::times_4, 0)); 7815 rorq(raxReg, 32); // convert big-endian to little-endian 7816 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax 7817 7818 // Right shift by 1 and save carry 7819 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1 7820 rcrq(rdxReg, 1); 7821 rcrq(raxReg, 1); 7822 adcq(tmp5, 0); 7823 7824 // Store result in z 7825 movq(Address(z, tmp4, Address::times_4, 0), rdxReg); 7826 movq(Address(z, tmp4, Address::times_4, 8), raxReg); 7827 7828 // Update indices for x and z 7829 addl(tmp1, 2); 7830 addl(tmp4, 4); 7831 jmp(L_first_loop); 7832 7833 bind(L_first_loop_exit); 7834 } 7835 7836 7837 /** 7838 * Perform the following multiply add operation using BMI2 instructions 7839 * carry:sum = sum + op1*op2 + carry 7840 * op2 should be in rdx 7841 * op2 is preserved, all other registers are modified 7842 */ 7843 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) { 7844 // assert op2 is rdx 7845 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1 7846 addq(sum, carry); 7847 adcq(tmp2, 0); 7848 addq(sum, op1); 7849 adcq(tmp2, 0); 7850 movq(carry, tmp2); 7851 } 7852 7853 /** 7854 * Perform the following multiply add operation: 7855 * carry:sum = sum + op1*op2 + carry 7856 * Preserves op1, op2 and modifies rest of registers 7857 */ 7858 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) { 7859 // rdx:rax = op1 * op2 7860 movq(raxReg, op2); 7861 mulq(op1); 7862 7863 // rdx:rax = sum + carry + rdx:rax 7864 addq(sum, carry); 7865 adcq(rdxReg, 0); 7866 addq(sum, raxReg); 7867 adcq(rdxReg, 0); 7868 7869 // carry:sum = rdx:sum 7870 movq(carry, rdxReg); 7871 } 7872 7873 /** 7874 * Add 64 bit long carry into z[] with carry propogation. 7875 * Preserves z and carry register values and modifies rest of registers. 7876 * 7877 */ 7878 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) { 7879 Label L_fourth_loop, L_fourth_loop_exit; 7880 7881 movl(tmp1, 1); 7882 subl(zlen, 2); 7883 addq(Address(z, zlen, Address::times_4, 0), carry); 7884 7885 bind(L_fourth_loop); 7886 jccb(Assembler::carryClear, L_fourth_loop_exit); 7887 subl(zlen, 2); 7888 jccb(Assembler::negative, L_fourth_loop_exit); 7889 addq(Address(z, zlen, Address::times_4, 0), tmp1); 7890 jmp(L_fourth_loop); 7891 bind(L_fourth_loop_exit); 7892 } 7893 7894 /** 7895 * Shift z[] left by 1 bit. 7896 * Preserves x, len, z and zlen registers and modifies rest of the registers. 7897 * 7898 */ 7899 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) { 7900 7901 Label L_fifth_loop, L_fifth_loop_exit; 7902 7903 // Fifth loop 7904 // Perform primitiveLeftShift(z, zlen, 1) 7905 7906 const Register prev_carry = tmp1; 7907 const Register new_carry = tmp4; 7908 const Register value = tmp2; 7909 const Register zidx = tmp3; 7910 7911 // int zidx, carry; 7912 // long value; 7913 // carry = 0; 7914 // for (zidx = zlen-2; zidx >=0; zidx -= 2) { 7915 // (carry:value) = (z[i] << 1) | carry ; 7916 // z[i] = value; 7917 // } 7918 7919 movl(zidx, zlen); 7920 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register 7921 7922 bind(L_fifth_loop); 7923 decl(zidx); // Use decl to preserve carry flag 7924 decl(zidx); 7925 jccb(Assembler::negative, L_fifth_loop_exit); 7926 7927 if (UseBMI2Instructions) { 7928 movq(value, Address(z, zidx, Address::times_4, 0)); 7929 rclq(value, 1); 7930 rorxq(value, value, 32); 7931 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 7932 } 7933 else { 7934 // clear new_carry 7935 xorl(new_carry, new_carry); 7936 7937 // Shift z[i] by 1, or in previous carry and save new carry 7938 movq(value, Address(z, zidx, Address::times_4, 0)); 7939 shlq(value, 1); 7940 adcl(new_carry, 0); 7941 7942 orq(value, prev_carry); 7943 rorq(value, 0x20); 7944 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 7945 7946 // Set previous carry = new carry 7947 movl(prev_carry, new_carry); 7948 } 7949 jmp(L_fifth_loop); 7950 7951 bind(L_fifth_loop_exit); 7952 } 7953 7954 7955 /** 7956 * Code for BigInteger::squareToLen() intrinsic 7957 * 7958 * rdi: x 7959 * rsi: len 7960 * r8: z 7961 * rcx: zlen 7962 * r12: tmp1 7963 * r13: tmp2 7964 * r14: tmp3 7965 * r15: tmp4 7966 * rbx: tmp5 7967 * 7968 */ 7969 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 7970 7971 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply; 7972 push(tmp1); 7973 push(tmp2); 7974 push(tmp3); 7975 push(tmp4); 7976 push(tmp5); 7977 7978 // First loop 7979 // Store the squares, right shifted one bit (i.e., divided by 2). 7980 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg); 7981 7982 // Add in off-diagonal sums. 7983 // 7984 // Second, third (nested) and fourth loops. 7985 // zlen +=2; 7986 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) { 7987 // carry = 0; 7988 // long op2 = x[xidx:xidx+1]; 7989 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) { 7990 // k -= 2; 7991 // long op1 = x[j:j+1]; 7992 // long sum = z[k:k+1]; 7993 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs); 7994 // z[k:k+1] = sum; 7995 // } 7996 // add_one_64(z, k, carry, tmp_regs); 7997 // } 7998 7999 const Register carry = tmp5; 8000 const Register sum = tmp3; 8001 const Register op1 = tmp4; 8002 Register op2 = tmp2; 8003 8004 push(zlen); 8005 push(len); 8006 addl(zlen,2); 8007 bind(L_second_loop); 8008 xorq(carry, carry); 8009 subl(zlen, 4); 8010 subl(len, 2); 8011 push(zlen); 8012 push(len); 8013 cmpl(len, 0); 8014 jccb(Assembler::lessEqual, L_second_loop_exit); 8015 8016 // Multiply an array by one 64 bit long. 8017 if (UseBMI2Instructions) { 8018 op2 = rdxReg; 8019 movq(op2, Address(x, len, Address::times_4, 0)); 8020 rorxq(op2, op2, 32); 8021 } 8022 else { 8023 movq(op2, Address(x, len, Address::times_4, 0)); 8024 rorq(op2, 32); 8025 } 8026 8027 bind(L_third_loop); 8028 decrementl(len); 8029 jccb(Assembler::negative, L_third_loop_exit); 8030 decrementl(len); 8031 jccb(Assembler::negative, L_last_x); 8032 8033 movq(op1, Address(x, len, Address::times_4, 0)); 8034 rorq(op1, 32); 8035 8036 bind(L_multiply); 8037 subl(zlen, 2); 8038 movq(sum, Address(z, zlen, Address::times_4, 0)); 8039 8040 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry. 8041 if (UseBMI2Instructions) { 8042 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2); 8043 } 8044 else { 8045 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 8046 } 8047 8048 movq(Address(z, zlen, Address::times_4, 0), sum); 8049 8050 jmp(L_third_loop); 8051 bind(L_third_loop_exit); 8052 8053 // Fourth loop 8054 // Add 64 bit long carry into z with carry propogation. 8055 // Uses offsetted zlen. 8056 add_one_64(z, zlen, carry, tmp1); 8057 8058 pop(len); 8059 pop(zlen); 8060 jmp(L_second_loop); 8061 8062 // Next infrequent code is moved outside loops. 8063 bind(L_last_x); 8064 movl(op1, Address(x, 0)); 8065 jmp(L_multiply); 8066 8067 bind(L_second_loop_exit); 8068 pop(len); 8069 pop(zlen); 8070 pop(len); 8071 pop(zlen); 8072 8073 // Fifth loop 8074 // Shift z left 1 bit. 8075 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4); 8076 8077 // z[zlen-1] |= x[len-1] & 1; 8078 movl(tmp3, Address(x, len, Address::times_4, -4)); 8079 andl(tmp3, 1); 8080 orl(Address(z, zlen, Address::times_4, -4), tmp3); 8081 8082 pop(tmp5); 8083 pop(tmp4); 8084 pop(tmp3); 8085 pop(tmp2); 8086 pop(tmp1); 8087 } 8088 8089 /** 8090 * Helper function for mul_add() 8091 * Multiply the in[] by int k and add to out[] starting at offset offs using 8092 * 128 bit by 32 bit multiply and return the carry in tmp5. 8093 * Only quad int aligned length of in[] is operated on in this function. 8094 * k is in rdxReg for BMI2Instructions, for others it is in tmp2. 8095 * This function preserves out, in and k registers. 8096 * len and offset point to the appropriate index in "in" & "out" correspondingly 8097 * tmp5 has the carry. 8098 * other registers are temporary and are modified. 8099 * 8100 */ 8101 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in, 8102 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3, 8103 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 8104 8105 Label L_first_loop, L_first_loop_exit; 8106 8107 movl(tmp1, len); 8108 shrl(tmp1, 2); 8109 8110 bind(L_first_loop); 8111 subl(tmp1, 1); 8112 jccb(Assembler::negative, L_first_loop_exit); 8113 8114 subl(len, 4); 8115 subl(offset, 4); 8116 8117 Register op2 = tmp2; 8118 const Register sum = tmp3; 8119 const Register op1 = tmp4; 8120 const Register carry = tmp5; 8121 8122 if (UseBMI2Instructions) { 8123 op2 = rdxReg; 8124 } 8125 8126 movq(op1, Address(in, len, Address::times_4, 8)); 8127 rorq(op1, 32); 8128 movq(sum, Address(out, offset, Address::times_4, 8)); 8129 rorq(sum, 32); 8130 if (UseBMI2Instructions) { 8131 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 8132 } 8133 else { 8134 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 8135 } 8136 // Store back in big endian from little endian 8137 rorq(sum, 0x20); 8138 movq(Address(out, offset, Address::times_4, 8), sum); 8139 8140 movq(op1, Address(in, len, Address::times_4, 0)); 8141 rorq(op1, 32); 8142 movq(sum, Address(out, offset, Address::times_4, 0)); 8143 rorq(sum, 32); 8144 if (UseBMI2Instructions) { 8145 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 8146 } 8147 else { 8148 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 8149 } 8150 // Store back in big endian from little endian 8151 rorq(sum, 0x20); 8152 movq(Address(out, offset, Address::times_4, 0), sum); 8153 8154 jmp(L_first_loop); 8155 bind(L_first_loop_exit); 8156 } 8157 8158 /** 8159 * Code for BigInteger::mulAdd() intrinsic 8160 * 8161 * rdi: out 8162 * rsi: in 8163 * r11: offs (out.length - offset) 8164 * rcx: len 8165 * r8: k 8166 * r12: tmp1 8167 * r13: tmp2 8168 * r14: tmp3 8169 * r15: tmp4 8170 * rbx: tmp5 8171 * Multiply the in[] by word k and add to out[], return the carry in rax 8172 */ 8173 void MacroAssembler::mul_add(Register out, Register in, Register offs, 8174 Register len, Register k, Register tmp1, Register tmp2, Register tmp3, 8175 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 8176 8177 Label L_carry, L_last_in, L_done; 8178 8179 // carry = 0; 8180 // for (int j=len-1; j >= 0; j--) { 8181 // long product = (in[j] & LONG_MASK) * kLong + 8182 // (out[offs] & LONG_MASK) + carry; 8183 // out[offs--] = (int)product; 8184 // carry = product >>> 32; 8185 // } 8186 // 8187 push(tmp1); 8188 push(tmp2); 8189 push(tmp3); 8190 push(tmp4); 8191 push(tmp5); 8192 8193 Register op2 = tmp2; 8194 const Register sum = tmp3; 8195 const Register op1 = tmp4; 8196 const Register carry = tmp5; 8197 8198 if (UseBMI2Instructions) { 8199 op2 = rdxReg; 8200 movl(op2, k); 8201 } 8202 else { 8203 movl(op2, k); 8204 } 8205 8206 xorq(carry, carry); 8207 8208 //First loop 8209 8210 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply 8211 //The carry is in tmp5 8212 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg); 8213 8214 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any 8215 decrementl(len); 8216 jccb(Assembler::negative, L_carry); 8217 decrementl(len); 8218 jccb(Assembler::negative, L_last_in); 8219 8220 movq(op1, Address(in, len, Address::times_4, 0)); 8221 rorq(op1, 32); 8222 8223 subl(offs, 2); 8224 movq(sum, Address(out, offs, Address::times_4, 0)); 8225 rorq(sum, 32); 8226 8227 if (UseBMI2Instructions) { 8228 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 8229 } 8230 else { 8231 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 8232 } 8233 8234 // Store back in big endian from little endian 8235 rorq(sum, 0x20); 8236 movq(Address(out, offs, Address::times_4, 0), sum); 8237 8238 testl(len, len); 8239 jccb(Assembler::zero, L_carry); 8240 8241 //Multiply the last in[] entry, if any 8242 bind(L_last_in); 8243 movl(op1, Address(in, 0)); 8244 movl(sum, Address(out, offs, Address::times_4, -4)); 8245 8246 movl(raxReg, k); 8247 mull(op1); //tmp4 * eax -> edx:eax 8248 addl(sum, carry); 8249 adcl(rdxReg, 0); 8250 addl(sum, raxReg); 8251 adcl(rdxReg, 0); 8252 movl(carry, rdxReg); 8253 8254 movl(Address(out, offs, Address::times_4, -4), sum); 8255 8256 bind(L_carry); 8257 //return tmp5/carry as carry in rax 8258 movl(rax, carry); 8259 8260 bind(L_done); 8261 pop(tmp5); 8262 pop(tmp4); 8263 pop(tmp3); 8264 pop(tmp2); 8265 pop(tmp1); 8266 } 8267 #endif 8268 8269 /** 8270 * Emits code to update CRC-32 with a byte value according to constants in table 8271 * 8272 * @param [in,out]crc Register containing the crc. 8273 * @param [in]val Register containing the byte to fold into the CRC. 8274 * @param [in]table Register containing the table of crc constants. 8275 * 8276 * uint32_t crc; 8277 * val = crc_table[(val ^ crc) & 0xFF]; 8278 * crc = val ^ (crc >> 8); 8279 * 8280 */ 8281 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 8282 xorl(val, crc); 8283 andl(val, 0xFF); 8284 shrl(crc, 8); // unsigned shift 8285 xorl(crc, Address(table, val, Address::times_4, 0)); 8286 } 8287 8288 /** 8289 * Fold 128-bit data chunk 8290 */ 8291 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { 8292 if (UseAVX > 0) { 8293 vpclmulhdq(xtmp, xK, xcrc); // [123:64] 8294 vpclmulldq(xcrc, xK, xcrc); // [63:0] 8295 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */); 8296 pxor(xcrc, xtmp); 8297 } else { 8298 movdqa(xtmp, xcrc); 8299 pclmulhdq(xtmp, xK); // [123:64] 8300 pclmulldq(xcrc, xK); // [63:0] 8301 pxor(xcrc, xtmp); 8302 movdqu(xtmp, Address(buf, offset)); 8303 pxor(xcrc, xtmp); 8304 } 8305 } 8306 8307 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) { 8308 if (UseAVX > 0) { 8309 vpclmulhdq(xtmp, xK, xcrc); 8310 vpclmulldq(xcrc, xK, xcrc); 8311 pxor(xcrc, xbuf); 8312 pxor(xcrc, xtmp); 8313 } else { 8314 movdqa(xtmp, xcrc); 8315 pclmulhdq(xtmp, xK); 8316 pclmulldq(xcrc, xK); 8317 pxor(xcrc, xbuf); 8318 pxor(xcrc, xtmp); 8319 } 8320 } 8321 8322 /** 8323 * 8-bit folds to compute 32-bit CRC 8324 * 8325 * uint64_t xcrc; 8326 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8); 8327 */ 8328 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) { 8329 movdl(tmp, xcrc); 8330 andl(tmp, 0xFF); 8331 movdl(xtmp, Address(table, tmp, Address::times_4, 0)); 8332 psrldq(xcrc, 1); // unsigned shift one byte 8333 pxor(xcrc, xtmp); 8334 } 8335 8336 /** 8337 * uint32_t crc; 8338 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8); 8339 */ 8340 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) { 8341 movl(tmp, crc); 8342 andl(tmp, 0xFF); 8343 shrl(crc, 8); 8344 xorl(crc, Address(table, tmp, Address::times_4, 0)); 8345 } 8346 8347 /** 8348 * @param crc register containing existing CRC (32-bit) 8349 * @param buf register pointing to input byte buffer (byte*) 8350 * @param len register containing number of bytes 8351 * @param table register that will contain address of CRC table 8352 * @param tmp scratch register 8353 */ 8354 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) { 8355 assert_different_registers(crc, buf, len, table, tmp, rax); 8356 8357 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; 8358 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; 8359 8360 lea(table, ExternalAddress(StubRoutines::crc_table_addr())); 8361 notl(crc); // ~crc 8362 cmpl(len, 16); 8363 jcc(Assembler::less, L_tail); 8364 8365 // Align buffer to 16 bytes 8366 movl(tmp, buf); 8367 andl(tmp, 0xF); 8368 jccb(Assembler::zero, L_aligned); 8369 subl(tmp, 16); 8370 addl(len, tmp); 8371 8372 align(4); 8373 BIND(L_align_loop); 8374 movsbl(rax, Address(buf, 0)); // load byte with sign extension 8375 update_byte_crc32(crc, rax, table); 8376 increment(buf); 8377 incrementl(tmp); 8378 jccb(Assembler::less, L_align_loop); 8379 8380 BIND(L_aligned); 8381 movl(tmp, len); // save 8382 shrl(len, 4); 8383 jcc(Assembler::zero, L_tail_restore); 8384 8385 // Fold crc into first bytes of vector 8386 movdqa(xmm1, Address(buf, 0)); 8387 movdl(rax, xmm1); 8388 xorl(crc, rax); 8389 pinsrd(xmm1, crc, 0); 8390 addptr(buf, 16); 8391 subl(len, 4); // len > 0 8392 jcc(Assembler::less, L_fold_tail); 8393 8394 movdqa(xmm2, Address(buf, 0)); 8395 movdqa(xmm3, Address(buf, 16)); 8396 movdqa(xmm4, Address(buf, 32)); 8397 addptr(buf, 48); 8398 subl(len, 3); 8399 jcc(Assembler::lessEqual, L_fold_512b); 8400 8401 // Fold total 512 bits of polynomial on each iteration, 8402 // 128 bits per each of 4 parallel streams. 8403 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32)); 8404 8405 align(32); 8406 BIND(L_fold_512b_loop); 8407 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 8408 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16); 8409 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32); 8410 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48); 8411 addptr(buf, 64); 8412 subl(len, 4); 8413 jcc(Assembler::greater, L_fold_512b_loop); 8414 8415 // Fold 512 bits to 128 bits. 8416 BIND(L_fold_512b); 8417 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 8418 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2); 8419 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3); 8420 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4); 8421 8422 // Fold the rest of 128 bits data chunks 8423 BIND(L_fold_tail); 8424 addl(len, 3); 8425 jccb(Assembler::lessEqual, L_fold_128b); 8426 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 8427 8428 BIND(L_fold_tail_loop); 8429 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 8430 addptr(buf, 16); 8431 decrementl(len); 8432 jccb(Assembler::greater, L_fold_tail_loop); 8433 8434 // Fold 128 bits in xmm1 down into 32 bits in crc register. 8435 BIND(L_fold_128b); 8436 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr())); 8437 if (UseAVX > 0) { 8438 vpclmulqdq(xmm2, xmm0, xmm1, 0x1); 8439 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */); 8440 vpclmulqdq(xmm0, xmm0, xmm3, 0x1); 8441 } else { 8442 movdqa(xmm2, xmm0); 8443 pclmulqdq(xmm2, xmm1, 0x1); 8444 movdqa(xmm3, xmm0); 8445 pand(xmm3, xmm2); 8446 pclmulqdq(xmm0, xmm3, 0x1); 8447 } 8448 psrldq(xmm1, 8); 8449 psrldq(xmm2, 4); 8450 pxor(xmm0, xmm1); 8451 pxor(xmm0, xmm2); 8452 8453 // 8 8-bit folds to compute 32-bit CRC. 8454 for (int j = 0; j < 4; j++) { 8455 fold_8bit_crc32(xmm0, table, xmm1, rax); 8456 } 8457 movdl(crc, xmm0); // mov 32 bits to general register 8458 for (int j = 0; j < 4; j++) { 8459 fold_8bit_crc32(crc, table, rax); 8460 } 8461 8462 BIND(L_tail_restore); 8463 movl(len, tmp); // restore 8464 BIND(L_tail); 8465 andl(len, 0xf); 8466 jccb(Assembler::zero, L_exit); 8467 8468 // Fold the rest of bytes 8469 align(4); 8470 BIND(L_tail_loop); 8471 movsbl(rax, Address(buf, 0)); // load byte with sign extension 8472 update_byte_crc32(crc, rax, table); 8473 increment(buf); 8474 decrementl(len); 8475 jccb(Assembler::greater, L_tail_loop); 8476 8477 BIND(L_exit); 8478 notl(crc); // ~c 8479 } 8480 8481 #undef BIND 8482 #undef BLOCK_COMMENT 8483 8484 8485 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 8486 switch (cond) { 8487 // Note some conditions are synonyms for others 8488 case Assembler::zero: return Assembler::notZero; 8489 case Assembler::notZero: return Assembler::zero; 8490 case Assembler::less: return Assembler::greaterEqual; 8491 case Assembler::lessEqual: return Assembler::greater; 8492 case Assembler::greater: return Assembler::lessEqual; 8493 case Assembler::greaterEqual: return Assembler::less; 8494 case Assembler::below: return Assembler::aboveEqual; 8495 case Assembler::belowEqual: return Assembler::above; 8496 case Assembler::above: return Assembler::belowEqual; 8497 case Assembler::aboveEqual: return Assembler::below; 8498 case Assembler::overflow: return Assembler::noOverflow; 8499 case Assembler::noOverflow: return Assembler::overflow; 8500 case Assembler::negative: return Assembler::positive; 8501 case Assembler::positive: return Assembler::negative; 8502 case Assembler::parity: return Assembler::noParity; 8503 case Assembler::noParity: return Assembler::parity; 8504 } 8505 ShouldNotReachHere(); return Assembler::overflow; 8506 } 8507 8508 SkipIfEqual::SkipIfEqual( 8509 MacroAssembler* masm, const bool* flag_addr, bool value) { 8510 _masm = masm; 8511 _masm->cmp8(ExternalAddress((address)flag_addr), value); 8512 _masm->jcc(Assembler::equal, _label); 8513 } 8514 8515 SkipIfEqual::~SkipIfEqual() { 8516 _masm->bind(_label); 8517 }