1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc/shared/cardTableModRefBS.hpp"
30 #include "gc/shared/collectedHeap.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "oops/klass.inline.hpp"
35 #include "prims/methodHandles.hpp"
36 #include "runtime/biasedLocking.hpp"
37 #include "runtime/interfaceSupport.hpp"
38 #include "runtime/objectMonitor.hpp"
39 #include "runtime/os.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "runtime/stubRoutines.hpp"
42 #include "utilities/macros.hpp"
43 #if INCLUDE_ALL_GCS
44 #include "gc/g1/g1CollectedHeap.inline.hpp"
45 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
46 #include "gc/g1/heapRegion.hpp"
47 #endif // INCLUDE_ALL_GCS
48
49 #ifdef PRODUCT
50 #define BLOCK_COMMENT(str) /* nothing */
51 #define STOP(error) stop(error)
52 #else
53 #define BLOCK_COMMENT(str) block_comment(str)
54 #define STOP(error) block_comment(error); stop(error)
55 #endif
56
57 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
58
59 PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC
60
61 #ifdef ASSERT
62 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
63 #endif
64
65 static Assembler::Condition reverse[] = {
66 Assembler::noOverflow /* overflow = 0x0 */ ,
67 Assembler::overflow /* noOverflow = 0x1 */ ,
68 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
69 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
70 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
71 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
72 Assembler::above /* belowEqual = 0x6 */ ,
73 Assembler::belowEqual /* above = 0x7 */ ,
74 Assembler::positive /* negative = 0x8 */ ,
75 Assembler::negative /* positive = 0x9 */ ,
76 Assembler::noParity /* parity = 0xa */ ,
77 Assembler::parity /* noParity = 0xb */ ,
78 Assembler::greaterEqual /* less = 0xc */ ,
79 Assembler::less /* greaterEqual = 0xd */ ,
80 Assembler::greater /* lessEqual = 0xe */ ,
81 Assembler::lessEqual /* greater = 0xf, */
82
83 };
84
85
86 // Implementation of MacroAssembler
87
88 // First all the versions that have distinct versions depending on 32/64 bit
89 // Unless the difference is trivial (1 line or so).
90
91 #ifndef _LP64
92
93 // 32bit versions
94
95 Address MacroAssembler::as_Address(AddressLiteral adr) {
96 return Address(adr.target(), adr.rspec());
97 }
98
99 Address MacroAssembler::as_Address(ArrayAddress adr) {
100 return Address::make_array(adr);
101 }
102
103 void MacroAssembler::call_VM_leaf_base(address entry_point,
104 int number_of_arguments) {
105 call(RuntimeAddress(entry_point));
106 increment(rsp, number_of_arguments * wordSize);
107 }
108
109 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
110 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
111 }
112
113 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
114 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
115 }
116
117 void MacroAssembler::cmpoop(Address src1, jobject obj) {
118 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
119 }
120
121 void MacroAssembler::cmpoop(Register src1, jobject obj) {
122 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
123 }
124
125 void MacroAssembler::extend_sign(Register hi, Register lo) {
126 // According to Intel Doc. AP-526, "Integer Divide", p.18.
127 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
128 cdql();
129 } else {
130 movl(hi, lo);
131 sarl(hi, 31);
132 }
133 }
134
135 void MacroAssembler::jC2(Register tmp, Label& L) {
136 // set parity bit if FPU flag C2 is set (via rax)
137 save_rax(tmp);
138 fwait(); fnstsw_ax();
139 sahf();
140 restore_rax(tmp);
141 // branch
142 jcc(Assembler::parity, L);
143 }
144
145 void MacroAssembler::jnC2(Register tmp, Label& L) {
146 // set parity bit if FPU flag C2 is set (via rax)
147 save_rax(tmp);
148 fwait(); fnstsw_ax();
149 sahf();
150 restore_rax(tmp);
151 // branch
152 jcc(Assembler::noParity, L);
153 }
154
155 // 32bit can do a case table jump in one instruction but we no longer allow the base
156 // to be installed in the Address class
157 void MacroAssembler::jump(ArrayAddress entry) {
158 jmp(as_Address(entry));
159 }
160
161 // Note: y_lo will be destroyed
162 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
163 // Long compare for Java (semantics as described in JVM spec.)
164 Label high, low, done;
165
166 cmpl(x_hi, y_hi);
167 jcc(Assembler::less, low);
168 jcc(Assembler::greater, high);
169 // x_hi is the return register
170 xorl(x_hi, x_hi);
171 cmpl(x_lo, y_lo);
172 jcc(Assembler::below, low);
173 jcc(Assembler::equal, done);
174
175 bind(high);
176 xorl(x_hi, x_hi);
177 increment(x_hi);
178 jmp(done);
179
180 bind(low);
181 xorl(x_hi, x_hi);
182 decrementl(x_hi);
183
184 bind(done);
185 }
186
187 void MacroAssembler::lea(Register dst, AddressLiteral src) {
188 mov_literal32(dst, (int32_t)src.target(), src.rspec());
189 }
190
191 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
192 // leal(dst, as_Address(adr));
193 // see note in movl as to why we must use a move
194 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
195 }
196
197 void MacroAssembler::leave() {
198 mov(rsp, rbp);
199 pop(rbp);
200 }
201
202 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
203 // Multiplication of two Java long values stored on the stack
204 // as illustrated below. Result is in rdx:rax.
205 //
206 // rsp ---> [ ?? ] \ \
207 // .... | y_rsp_offset |
208 // [ y_lo ] / (in bytes) | x_rsp_offset
209 // [ y_hi ] | (in bytes)
210 // .... |
211 // [ x_lo ] /
212 // [ x_hi ]
213 // ....
214 //
215 // Basic idea: lo(result) = lo(x_lo * y_lo)
216 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
217 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
218 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
219 Label quick;
220 // load x_hi, y_hi and check if quick
221 // multiplication is possible
222 movl(rbx, x_hi);
223 movl(rcx, y_hi);
224 movl(rax, rbx);
225 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
226 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
227 // do full multiplication
228 // 1st step
229 mull(y_lo); // x_hi * y_lo
230 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
231 // 2nd step
232 movl(rax, x_lo);
233 mull(rcx); // x_lo * y_hi
234 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
235 // 3rd step
236 bind(quick); // note: rbx, = 0 if quick multiply!
237 movl(rax, x_lo);
238 mull(y_lo); // x_lo * y_lo
239 addl(rdx, rbx); // correct hi(x_lo * y_lo)
240 }
241
242 void MacroAssembler::lneg(Register hi, Register lo) {
243 negl(lo);
244 adcl(hi, 0);
245 negl(hi);
246 }
247
248 void MacroAssembler::lshl(Register hi, Register lo) {
249 // Java shift left long support (semantics as described in JVM spec., p.305)
250 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
251 // shift value is in rcx !
252 assert(hi != rcx, "must not use rcx");
253 assert(lo != rcx, "must not use rcx");
254 const Register s = rcx; // shift count
255 const int n = BitsPerWord;
256 Label L;
257 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
258 cmpl(s, n); // if (s < n)
259 jcc(Assembler::less, L); // else (s >= n)
260 movl(hi, lo); // x := x << n
261 xorl(lo, lo);
262 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
263 bind(L); // s (mod n) < n
264 shldl(hi, lo); // x := x << s
265 shll(lo);
266 }
267
268
269 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
270 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
271 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
272 assert(hi != rcx, "must not use rcx");
273 assert(lo != rcx, "must not use rcx");
274 const Register s = rcx; // shift count
275 const int n = BitsPerWord;
276 Label L;
277 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
278 cmpl(s, n); // if (s < n)
279 jcc(Assembler::less, L); // else (s >= n)
280 movl(lo, hi); // x := x >> n
281 if (sign_extension) sarl(hi, 31);
282 else xorl(hi, hi);
283 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
284 bind(L); // s (mod n) < n
285 shrdl(lo, hi); // x := x >> s
286 if (sign_extension) sarl(hi);
287 else shrl(hi);
288 }
289
290 void MacroAssembler::movoop(Register dst, jobject obj) {
291 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
292 }
293
294 void MacroAssembler::movoop(Address dst, jobject obj) {
295 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
296 }
297
298 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
299 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
300 }
301
302 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
303 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
304 }
305
306 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
307 // scratch register is not used,
308 // it is defined to match parameters of 64-bit version of this method.
309 if (src.is_lval()) {
310 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
311 } else {
312 movl(dst, as_Address(src));
313 }
314 }
315
316 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
317 movl(as_Address(dst), src);
318 }
319
320 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
321 movl(dst, as_Address(src));
322 }
323
324 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
325 void MacroAssembler::movptr(Address dst, intptr_t src) {
326 movl(dst, src);
327 }
328
329
330 void MacroAssembler::pop_callee_saved_registers() {
331 pop(rcx);
332 pop(rdx);
333 pop(rdi);
334 pop(rsi);
335 }
336
337 void MacroAssembler::pop_fTOS() {
338 fld_d(Address(rsp, 0));
339 addl(rsp, 2 * wordSize);
340 }
341
342 void MacroAssembler::push_callee_saved_registers() {
343 push(rsi);
344 push(rdi);
345 push(rdx);
346 push(rcx);
347 }
348
349 void MacroAssembler::push_fTOS() {
350 subl(rsp, 2 * wordSize);
351 fstp_d(Address(rsp, 0));
352 }
353
354
355 void MacroAssembler::pushoop(jobject obj) {
356 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
357 }
358
359 void MacroAssembler::pushklass(Metadata* obj) {
360 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
361 }
362
363 void MacroAssembler::pushptr(AddressLiteral src) {
364 if (src.is_lval()) {
365 push_literal32((int32_t)src.target(), src.rspec());
366 } else {
367 pushl(as_Address(src));
368 }
369 }
370
371 void MacroAssembler::set_word_if_not_zero(Register dst) {
372 xorl(dst, dst);
373 set_byte_if_not_zero(dst);
374 }
375
376 static void pass_arg0(MacroAssembler* masm, Register arg) {
377 masm->push(arg);
378 }
379
380 static void pass_arg1(MacroAssembler* masm, Register arg) {
381 masm->push(arg);
382 }
383
384 static void pass_arg2(MacroAssembler* masm, Register arg) {
385 masm->push(arg);
386 }
387
388 static void pass_arg3(MacroAssembler* masm, Register arg) {
389 masm->push(arg);
390 }
391
392 #ifndef PRODUCT
393 extern "C" void findpc(intptr_t x);
394 #endif
395
396 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
397 // In order to get locks to work, we need to fake a in_VM state
398 JavaThread* thread = JavaThread::current();
399 JavaThreadState saved_state = thread->thread_state();
400 thread->set_thread_state(_thread_in_vm);
401 if (ShowMessageBoxOnError) {
402 JavaThread* thread = JavaThread::current();
403 JavaThreadState saved_state = thread->thread_state();
404 thread->set_thread_state(_thread_in_vm);
405 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
406 ttyLocker ttyl;
407 BytecodeCounter::print();
408 }
409 // To see where a verify_oop failed, get $ebx+40/X for this frame.
410 // This is the value of eip which points to where verify_oop will return.
411 if (os::message_box(msg, "Execution stopped, print registers?")) {
412 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
413 BREAKPOINT;
414 }
415 } else {
416 ttyLocker ttyl;
417 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
418 }
419 // Don't assert holding the ttyLock
420 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
421 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
422 }
423
424 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
425 ttyLocker ttyl;
426 FlagSetting fs(Debugging, true);
427 tty->print_cr("eip = 0x%08x", eip);
428 #ifndef PRODUCT
429 if ((WizardMode || Verbose) && PrintMiscellaneous) {
430 tty->cr();
431 findpc(eip);
432 tty->cr();
433 }
434 #endif
435 #define PRINT_REG(rax) \
436 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
437 PRINT_REG(rax);
438 PRINT_REG(rbx);
439 PRINT_REG(rcx);
440 PRINT_REG(rdx);
441 PRINT_REG(rdi);
442 PRINT_REG(rsi);
443 PRINT_REG(rbp);
444 PRINT_REG(rsp);
445 #undef PRINT_REG
446 // Print some words near top of staack.
447 int* dump_sp = (int*) rsp;
448 for (int col1 = 0; col1 < 8; col1++) {
449 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
450 os::print_location(tty, *dump_sp++);
451 }
452 for (int row = 0; row < 16; row++) {
453 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
454 for (int col = 0; col < 8; col++) {
455 tty->print(" 0x%08x", *dump_sp++);
456 }
457 tty->cr();
458 }
459 // Print some instructions around pc:
460 Disassembler::decode((address)eip-64, (address)eip);
461 tty->print_cr("--------");
462 Disassembler::decode((address)eip, (address)eip+32);
463 }
464
465 void MacroAssembler::stop(const char* msg) {
466 ExternalAddress message((address)msg);
467 // push address of message
468 pushptr(message.addr());
469 { Label L; call(L, relocInfo::none); bind(L); } // push eip
470 pusha(); // push registers
471 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
472 hlt();
473 }
474
475 void MacroAssembler::warn(const char* msg) {
476 push_CPU_state();
477
478 ExternalAddress message((address) msg);
479 // push address of message
480 pushptr(message.addr());
481
482 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
483 addl(rsp, wordSize); // discard argument
484 pop_CPU_state();
485 }
486
487 void MacroAssembler::print_state() {
488 { Label L; call(L, relocInfo::none); bind(L); } // push eip
489 pusha(); // push registers
490
491 push_CPU_state();
492 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
493 pop_CPU_state();
494
495 popa();
496 addl(rsp, wordSize);
497 }
498
499 #else // _LP64
500
501 // 64 bit versions
502
503 Address MacroAssembler::as_Address(AddressLiteral adr) {
504 // amd64 always does this as a pc-rel
505 // we can be absolute or disp based on the instruction type
506 // jmp/call are displacements others are absolute
507 assert(!adr.is_lval(), "must be rval");
508 assert(reachable(adr), "must be");
509 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
510
511 }
512
513 Address MacroAssembler::as_Address(ArrayAddress adr) {
514 AddressLiteral base = adr.base();
515 lea(rscratch1, base);
516 Address index = adr.index();
517 assert(index._disp == 0, "must not have disp"); // maybe it can?
518 Address array(rscratch1, index._index, index._scale, index._disp);
519 return array;
520 }
521
522 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
523 Label L, E;
524
525 #ifdef _WIN64
526 // Windows always allocates space for it's register args
527 assert(num_args <= 4, "only register arguments supported");
528 subq(rsp, frame::arg_reg_save_area_bytes);
529 #endif
530
531 // Align stack if necessary
532 testl(rsp, 15);
533 jcc(Assembler::zero, L);
534
535 subq(rsp, 8);
536 {
537 call(RuntimeAddress(entry_point));
538 }
539 addq(rsp, 8);
540 jmp(E);
541
542 bind(L);
543 {
544 call(RuntimeAddress(entry_point));
545 }
546
547 bind(E);
548
549 #ifdef _WIN64
550 // restore stack pointer
551 addq(rsp, frame::arg_reg_save_area_bytes);
552 #endif
553
554 }
555
556 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
557 assert(!src2.is_lval(), "should use cmpptr");
558
559 if (reachable(src2)) {
560 cmpq(src1, as_Address(src2));
561 } else {
562 lea(rscratch1, src2);
563 Assembler::cmpq(src1, Address(rscratch1, 0));
564 }
565 }
566
567 int MacroAssembler::corrected_idivq(Register reg) {
568 // Full implementation of Java ldiv and lrem; checks for special
569 // case as described in JVM spec., p.243 & p.271. The function
570 // returns the (pc) offset of the idivl instruction - may be needed
571 // for implicit exceptions.
572 //
573 // normal case special case
574 //
575 // input : rax: dividend min_long
576 // reg: divisor (may not be eax/edx) -1
577 //
578 // output: rax: quotient (= rax idiv reg) min_long
579 // rdx: remainder (= rax irem reg) 0
580 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
581 static const int64_t min_long = 0x8000000000000000;
582 Label normal_case, special_case;
583
584 // check for special case
585 cmp64(rax, ExternalAddress((address) &min_long));
586 jcc(Assembler::notEqual, normal_case);
587 xorl(rdx, rdx); // prepare rdx for possible special case (where
588 // remainder = 0)
589 cmpq(reg, -1);
590 jcc(Assembler::equal, special_case);
591
592 // handle normal case
593 bind(normal_case);
594 cdqq();
595 int idivq_offset = offset();
596 idivq(reg);
597
598 // normal and special case exit
599 bind(special_case);
600
601 return idivq_offset;
602 }
603
604 void MacroAssembler::decrementq(Register reg, int value) {
605 if (value == min_jint) { subq(reg, value); return; }
606 if (value < 0) { incrementq(reg, -value); return; }
607 if (value == 0) { ; return; }
608 if (value == 1 && UseIncDec) { decq(reg) ; return; }
609 /* else */ { subq(reg, value) ; return; }
610 }
611
612 void MacroAssembler::decrementq(Address dst, int value) {
613 if (value == min_jint) { subq(dst, value); return; }
614 if (value < 0) { incrementq(dst, -value); return; }
615 if (value == 0) { ; return; }
616 if (value == 1 && UseIncDec) { decq(dst) ; return; }
617 /* else */ { subq(dst, value) ; return; }
618 }
619
620 void MacroAssembler::incrementq(AddressLiteral dst) {
621 if (reachable(dst)) {
622 incrementq(as_Address(dst));
623 } else {
624 lea(rscratch1, dst);
625 incrementq(Address(rscratch1, 0));
626 }
627 }
628
629 void MacroAssembler::incrementq(Register reg, int value) {
630 if (value == min_jint) { addq(reg, value); return; }
631 if (value < 0) { decrementq(reg, -value); return; }
632 if (value == 0) { ; return; }
633 if (value == 1 && UseIncDec) { incq(reg) ; return; }
634 /* else */ { addq(reg, value) ; return; }
635 }
636
637 void MacroAssembler::incrementq(Address dst, int value) {
638 if (value == min_jint) { addq(dst, value); return; }
639 if (value < 0) { decrementq(dst, -value); return; }
640 if (value == 0) { ; return; }
641 if (value == 1 && UseIncDec) { incq(dst) ; return; }
642 /* else */ { addq(dst, value) ; return; }
643 }
644
645 // 32bit can do a case table jump in one instruction but we no longer allow the base
646 // to be installed in the Address class
647 void MacroAssembler::jump(ArrayAddress entry) {
648 lea(rscratch1, entry.base());
649 Address dispatch = entry.index();
650 assert(dispatch._base == noreg, "must be");
651 dispatch._base = rscratch1;
652 jmp(dispatch);
653 }
654
655 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
656 ShouldNotReachHere(); // 64bit doesn't use two regs
657 cmpq(x_lo, y_lo);
658 }
659
660 void MacroAssembler::lea(Register dst, AddressLiteral src) {
661 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
662 }
663
664 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
665 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
666 movptr(dst, rscratch1);
667 }
668
669 void MacroAssembler::leave() {
670 // %%% is this really better? Why not on 32bit too?
671 emit_int8((unsigned char)0xC9); // LEAVE
672 }
673
674 void MacroAssembler::lneg(Register hi, Register lo) {
675 ShouldNotReachHere(); // 64bit doesn't use two regs
676 negq(lo);
677 }
678
679 void MacroAssembler::movoop(Register dst, jobject obj) {
680 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
681 }
682
683 void MacroAssembler::movoop(Address dst, jobject obj) {
684 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
685 movq(dst, rscratch1);
686 }
687
688 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
689 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
690 }
691
692 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
693 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
694 movq(dst, rscratch1);
695 }
696
697 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
698 if (src.is_lval()) {
699 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
700 } else {
701 if (reachable(src)) {
702 movq(dst, as_Address(src));
703 } else {
704 lea(scratch, src);
705 movq(dst, Address(scratch, 0));
706 }
707 }
708 }
709
710 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
711 movq(as_Address(dst), src);
712 }
713
714 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
715 movq(dst, as_Address(src));
716 }
717
718 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
719 void MacroAssembler::movptr(Address dst, intptr_t src) {
720 mov64(rscratch1, src);
721 movq(dst, rscratch1);
722 }
723
724 // These are mostly for initializing NULL
725 void MacroAssembler::movptr(Address dst, int32_t src) {
726 movslq(dst, src);
727 }
728
729 void MacroAssembler::movptr(Register dst, int32_t src) {
730 mov64(dst, (intptr_t)src);
731 }
732
733 void MacroAssembler::pushoop(jobject obj) {
734 movoop(rscratch1, obj);
735 push(rscratch1);
736 }
737
738 void MacroAssembler::pushklass(Metadata* obj) {
739 mov_metadata(rscratch1, obj);
740 push(rscratch1);
741 }
742
743 void MacroAssembler::pushptr(AddressLiteral src) {
744 lea(rscratch1, src);
745 if (src.is_lval()) {
746 push(rscratch1);
747 } else {
748 pushq(Address(rscratch1, 0));
749 }
750 }
751
752 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
753 bool clear_pc) {
754 // we must set sp to zero to clear frame
755 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
756 // must clear fp, so that compiled frames are not confused; it is
757 // possible that we need it only for debugging
758 if (clear_fp) {
759 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
760 }
761
762 if (clear_pc) {
763 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
764 }
765 }
766
767 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
768 Register last_java_fp,
769 address last_java_pc) {
770 // determine last_java_sp register
771 if (!last_java_sp->is_valid()) {
772 last_java_sp = rsp;
773 }
774
775 // last_java_fp is optional
776 if (last_java_fp->is_valid()) {
777 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
778 last_java_fp);
779 }
780
781 // last_java_pc is optional
782 if (last_java_pc != NULL) {
783 Address java_pc(r15_thread,
784 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
785 lea(rscratch1, InternalAddress(last_java_pc));
786 movptr(java_pc, rscratch1);
787 }
788
789 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
790 }
791
792 static void pass_arg0(MacroAssembler* masm, Register arg) {
793 if (c_rarg0 != arg ) {
794 masm->mov(c_rarg0, arg);
795 }
796 }
797
798 static void pass_arg1(MacroAssembler* masm, Register arg) {
799 if (c_rarg1 != arg ) {
800 masm->mov(c_rarg1, arg);
801 }
802 }
803
804 static void pass_arg2(MacroAssembler* masm, Register arg) {
805 if (c_rarg2 != arg ) {
806 masm->mov(c_rarg2, arg);
807 }
808 }
809
810 static void pass_arg3(MacroAssembler* masm, Register arg) {
811 if (c_rarg3 != arg ) {
812 masm->mov(c_rarg3, arg);
813 }
814 }
815
816 void MacroAssembler::stop(const char* msg) {
817 address rip = pc();
818 pusha(); // get regs on stack
819 lea(c_rarg0, ExternalAddress((address) msg));
820 lea(c_rarg1, InternalAddress(rip));
821 movq(c_rarg2, rsp); // pass pointer to regs array
822 andq(rsp, -16); // align stack as required by ABI
823 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
824 hlt();
825 }
826
827 void MacroAssembler::warn(const char* msg) {
828 push(rbp);
829 movq(rbp, rsp);
830 andq(rsp, -16); // align stack as required by push_CPU_state and call
831 push_CPU_state(); // keeps alignment at 16 bytes
832 lea(c_rarg0, ExternalAddress((address) msg));
833 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
834 pop_CPU_state();
835 mov(rsp, rbp);
836 pop(rbp);
837 }
838
839 void MacroAssembler::print_state() {
840 address rip = pc();
841 pusha(); // get regs on stack
842 push(rbp);
843 movq(rbp, rsp);
844 andq(rsp, -16); // align stack as required by push_CPU_state and call
845 push_CPU_state(); // keeps alignment at 16 bytes
846
847 lea(c_rarg0, InternalAddress(rip));
848 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
849 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
850
851 pop_CPU_state();
852 mov(rsp, rbp);
853 pop(rbp);
854 popa();
855 }
856
857 #ifndef PRODUCT
858 extern "C" void findpc(intptr_t x);
859 #endif
860
861 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
862 // In order to get locks to work, we need to fake a in_VM state
863 if (ShowMessageBoxOnError) {
864 JavaThread* thread = JavaThread::current();
865 JavaThreadState saved_state = thread->thread_state();
866 thread->set_thread_state(_thread_in_vm);
867 #ifndef PRODUCT
868 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
869 ttyLocker ttyl;
870 BytecodeCounter::print();
871 }
872 #endif
873 // To see where a verify_oop failed, get $ebx+40/X for this frame.
874 // XXX correct this offset for amd64
875 // This is the value of eip which points to where verify_oop will return.
876 if (os::message_box(msg, "Execution stopped, print registers?")) {
877 print_state64(pc, regs);
878 BREAKPOINT;
879 assert(false, "start up GDB");
880 }
881 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
882 } else {
883 ttyLocker ttyl;
884 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
885 msg);
886 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
887 }
888 }
889
890 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
891 ttyLocker ttyl;
892 FlagSetting fs(Debugging, true);
893 tty->print_cr("rip = 0x%016lx", pc);
894 #ifndef PRODUCT
895 tty->cr();
896 findpc(pc);
897 tty->cr();
898 #endif
899 #define PRINT_REG(rax, value) \
900 { tty->print("%s = ", #rax); os::print_location(tty, value); }
901 PRINT_REG(rax, regs[15]);
902 PRINT_REG(rbx, regs[12]);
903 PRINT_REG(rcx, regs[14]);
904 PRINT_REG(rdx, regs[13]);
905 PRINT_REG(rdi, regs[8]);
906 PRINT_REG(rsi, regs[9]);
907 PRINT_REG(rbp, regs[10]);
908 PRINT_REG(rsp, regs[11]);
909 PRINT_REG(r8 , regs[7]);
910 PRINT_REG(r9 , regs[6]);
911 PRINT_REG(r10, regs[5]);
912 PRINT_REG(r11, regs[4]);
913 PRINT_REG(r12, regs[3]);
914 PRINT_REG(r13, regs[2]);
915 PRINT_REG(r14, regs[1]);
916 PRINT_REG(r15, regs[0]);
917 #undef PRINT_REG
918 // Print some words near top of staack.
919 int64_t* rsp = (int64_t*) regs[11];
920 int64_t* dump_sp = rsp;
921 for (int col1 = 0; col1 < 8; col1++) {
922 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
923 os::print_location(tty, *dump_sp++);
924 }
925 for (int row = 0; row < 25; row++) {
926 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
927 for (int col = 0; col < 4; col++) {
928 tty->print(" 0x%016lx", *dump_sp++);
929 }
930 tty->cr();
931 }
932 // Print some instructions around pc:
933 Disassembler::decode((address)pc-64, (address)pc);
934 tty->print_cr("--------");
935 Disassembler::decode((address)pc, (address)pc+32);
936 }
937
938 #endif // _LP64
939
940 // Now versions that are common to 32/64 bit
941
942 void MacroAssembler::addptr(Register dst, int32_t imm32) {
943 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
944 }
945
946 void MacroAssembler::addptr(Register dst, Register src) {
947 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
948 }
949
950 void MacroAssembler::addptr(Address dst, Register src) {
951 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
952 }
953
954 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
955 if (reachable(src)) {
956 Assembler::addsd(dst, as_Address(src));
957 } else {
958 lea(rscratch1, src);
959 Assembler::addsd(dst, Address(rscratch1, 0));
960 }
961 }
962
963 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
964 if (reachable(src)) {
965 addss(dst, as_Address(src));
966 } else {
967 lea(rscratch1, src);
968 addss(dst, Address(rscratch1, 0));
969 }
970 }
971
972 void MacroAssembler::align(int modulus) {
973 if (offset() % modulus != 0) {
974 nop(modulus - (offset() % modulus));
975 }
976 }
977
978 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
979 // Used in sign-masking with aligned address.
980 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
981 if (reachable(src)) {
982 Assembler::andpd(dst, as_Address(src));
983 } else {
984 lea(rscratch1, src);
985 Assembler::andpd(dst, Address(rscratch1, 0));
986 }
987 }
988
989 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
990 // Used in sign-masking with aligned address.
991 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
992 if (reachable(src)) {
993 Assembler::andps(dst, as_Address(src));
994 } else {
995 lea(rscratch1, src);
996 Assembler::andps(dst, Address(rscratch1, 0));
997 }
998 }
999
1000 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1001 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1002 }
1003
1004 void MacroAssembler::atomic_incl(Address counter_addr) {
1005 if (os::is_MP())
1006 lock();
1007 incrementl(counter_addr);
1008 }
1009
1010 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1011 if (reachable(counter_addr)) {
1012 atomic_incl(as_Address(counter_addr));
1013 } else {
1014 lea(scr, counter_addr);
1015 atomic_incl(Address(scr, 0));
1016 }
1017 }
1018
1019 #ifdef _LP64
1020 void MacroAssembler::atomic_incq(Address counter_addr) {
1021 if (os::is_MP())
1022 lock();
1023 incrementq(counter_addr);
1024 }
1025
1026 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1027 if (reachable(counter_addr)) {
1028 atomic_incq(as_Address(counter_addr));
1029 } else {
1030 lea(scr, counter_addr);
1031 atomic_incq(Address(scr, 0));
1032 }
1033 }
1034 #endif
1035
1036 // Writes to stack successive pages until offset reached to check for
1037 // stack overflow + shadow pages. This clobbers tmp.
1038 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1039 movptr(tmp, rsp);
1040 // Bang stack for total size given plus shadow page size.
1041 // Bang one page at a time because large size can bang beyond yellow and
1042 // red zones.
1043 Label loop;
1044 bind(loop);
1045 movl(Address(tmp, (-os::vm_page_size())), size );
1046 subptr(tmp, os::vm_page_size());
1047 subl(size, os::vm_page_size());
1048 jcc(Assembler::greater, loop);
1049
1050 // Bang down shadow pages too.
1051 // At this point, (tmp-0) is the last address touched, so don't
1052 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1053 // was post-decremented.) Skip this address by starting at i=1, and
1054 // touch a few more pages below. N.B. It is important to touch all
1055 // the way down to and including i=StackShadowPages.
1056 for (int i = 1; i < StackShadowPages; i++) {
1057 // this could be any sized move but this is can be a debugging crumb
1058 // so the bigger the better.
1059 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1060 }
1061 }
1062
1063 int MacroAssembler::biased_locking_enter(Register lock_reg,
1064 Register obj_reg,
1065 Register swap_reg,
1066 Register tmp_reg,
1067 bool swap_reg_contains_mark,
1068 Label& done,
1069 Label* slow_case,
1070 BiasedLockingCounters* counters) {
1071 assert(UseBiasedLocking, "why call this otherwise?");
1072 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1073 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1074 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1075 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1076 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1077 Address saved_mark_addr(lock_reg, 0);
1078
1079 if (PrintBiasedLockingStatistics && counters == NULL) {
1080 counters = BiasedLocking::counters();
1081 }
1082 // Biased locking
1083 // See whether the lock is currently biased toward our thread and
1084 // whether the epoch is still valid
1085 // Note that the runtime guarantees sufficient alignment of JavaThread
1086 // pointers to allow age to be placed into low bits
1087 // First check to see whether biasing is even enabled for this object
1088 Label cas_label;
1089 int null_check_offset = -1;
1090 if (!swap_reg_contains_mark) {
1091 null_check_offset = offset();
1092 movptr(swap_reg, mark_addr);
1093 }
1094 movptr(tmp_reg, swap_reg);
1095 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1096 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1097 jcc(Assembler::notEqual, cas_label);
1098 // The bias pattern is present in the object's header. Need to check
1099 // whether the bias owner and the epoch are both still current.
1100 #ifndef _LP64
1101 // Note that because there is no current thread register on x86_32 we
1102 // need to store off the mark word we read out of the object to
1103 // avoid reloading it and needing to recheck invariants below. This
1104 // store is unfortunate but it makes the overall code shorter and
1105 // simpler.
1106 movptr(saved_mark_addr, swap_reg);
1107 #endif
1108 if (swap_reg_contains_mark) {
1109 null_check_offset = offset();
1110 }
1111 load_prototype_header(tmp_reg, obj_reg);
1112 #ifdef _LP64
1113 orptr(tmp_reg, r15_thread);
1114 xorptr(tmp_reg, swap_reg);
1115 Register header_reg = tmp_reg;
1116 #else
1117 xorptr(tmp_reg, swap_reg);
1118 get_thread(swap_reg);
1119 xorptr(swap_reg, tmp_reg);
1120 Register header_reg = swap_reg;
1121 #endif
1122 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1123 if (counters != NULL) {
1124 cond_inc32(Assembler::zero,
1125 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1126 }
1127 jcc(Assembler::equal, done);
1128
1129 Label try_revoke_bias;
1130 Label try_rebias;
1131
1132 // At this point we know that the header has the bias pattern and
1133 // that we are not the bias owner in the current epoch. We need to
1134 // figure out more details about the state of the header in order to
1135 // know what operations can be legally performed on the object's
1136 // header.
1137
1138 // If the low three bits in the xor result aren't clear, that means
1139 // the prototype header is no longer biased and we have to revoke
1140 // the bias on this object.
1141 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1142 jccb(Assembler::notZero, try_revoke_bias);
1143
1144 // Biasing is still enabled for this data type. See whether the
1145 // epoch of the current bias is still valid, meaning that the epoch
1146 // bits of the mark word are equal to the epoch bits of the
1147 // prototype header. (Note that the prototype header's epoch bits
1148 // only change at a safepoint.) If not, attempt to rebias the object
1149 // toward the current thread. Note that we must be absolutely sure
1150 // that the current epoch is invalid in order to do this because
1151 // otherwise the manipulations it performs on the mark word are
1152 // illegal.
1153 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1154 jccb(Assembler::notZero, try_rebias);
1155
1156 // The epoch of the current bias is still valid but we know nothing
1157 // about the owner; it might be set or it might be clear. Try to
1158 // acquire the bias of the object using an atomic operation. If this
1159 // fails we will go in to the runtime to revoke the object's bias.
1160 // Note that we first construct the presumed unbiased header so we
1161 // don't accidentally blow away another thread's valid bias.
1162 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1163 andptr(swap_reg,
1164 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1165 #ifdef _LP64
1166 movptr(tmp_reg, swap_reg);
1167 orptr(tmp_reg, r15_thread);
1168 #else
1169 get_thread(tmp_reg);
1170 orptr(tmp_reg, swap_reg);
1171 #endif
1172 if (os::is_MP()) {
1173 lock();
1174 }
1175 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1176 // If the biasing toward our thread failed, this means that
1177 // another thread succeeded in biasing it toward itself and we
1178 // need to revoke that bias. The revocation will occur in the
1179 // interpreter runtime in the slow case.
1180 if (counters != NULL) {
1181 cond_inc32(Assembler::zero,
1182 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1183 }
1184 if (slow_case != NULL) {
1185 jcc(Assembler::notZero, *slow_case);
1186 }
1187 jmp(done);
1188
1189 bind(try_rebias);
1190 // At this point we know the epoch has expired, meaning that the
1191 // current "bias owner", if any, is actually invalid. Under these
1192 // circumstances _only_, we are allowed to use the current header's
1193 // value as the comparison value when doing the cas to acquire the
1194 // bias in the current epoch. In other words, we allow transfer of
1195 // the bias from one thread to another directly in this situation.
1196 //
1197 // FIXME: due to a lack of registers we currently blow away the age
1198 // bits in this situation. Should attempt to preserve them.
1199 load_prototype_header(tmp_reg, obj_reg);
1200 #ifdef _LP64
1201 orptr(tmp_reg, r15_thread);
1202 #else
1203 get_thread(swap_reg);
1204 orptr(tmp_reg, swap_reg);
1205 movptr(swap_reg, saved_mark_addr);
1206 #endif
1207 if (os::is_MP()) {
1208 lock();
1209 }
1210 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1211 // If the biasing toward our thread failed, then another thread
1212 // succeeded in biasing it toward itself and we need to revoke that
1213 // bias. The revocation will occur in the runtime in the slow case.
1214 if (counters != NULL) {
1215 cond_inc32(Assembler::zero,
1216 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1217 }
1218 if (slow_case != NULL) {
1219 jcc(Assembler::notZero, *slow_case);
1220 }
1221 jmp(done);
1222
1223 bind(try_revoke_bias);
1224 // The prototype mark in the klass doesn't have the bias bit set any
1225 // more, indicating that objects of this data type are not supposed
1226 // to be biased any more. We are going to try to reset the mark of
1227 // this object to the prototype value and fall through to the
1228 // CAS-based locking scheme. Note that if our CAS fails, it means
1229 // that another thread raced us for the privilege of revoking the
1230 // bias of this particular object, so it's okay to continue in the
1231 // normal locking code.
1232 //
1233 // FIXME: due to a lack of registers we currently blow away the age
1234 // bits in this situation. Should attempt to preserve them.
1235 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1236 load_prototype_header(tmp_reg, obj_reg);
1237 if (os::is_MP()) {
1238 lock();
1239 }
1240 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1241 // Fall through to the normal CAS-based lock, because no matter what
1242 // the result of the above CAS, some thread must have succeeded in
1243 // removing the bias bit from the object's header.
1244 if (counters != NULL) {
1245 cond_inc32(Assembler::zero,
1246 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1247 }
1248
1249 bind(cas_label);
1250
1251 return null_check_offset;
1252 }
1253
1254 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1255 assert(UseBiasedLocking, "why call this otherwise?");
1256
1257 // Check for biased locking unlock case, which is a no-op
1258 // Note: we do not have to check the thread ID for two reasons.
1259 // First, the interpreter checks for IllegalMonitorStateException at
1260 // a higher level. Second, if the bias was revoked while we held the
1261 // lock, the object could not be rebiased toward another thread, so
1262 // the bias bit would be clear.
1263 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1264 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1265 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1266 jcc(Assembler::equal, done);
1267 }
1268
1269 #ifdef COMPILER2
1270
1271 #if INCLUDE_RTM_OPT
1272
1273 // Update rtm_counters based on abort status
1274 // input: abort_status
1275 // rtm_counters (RTMLockingCounters*)
1276 // flags are killed
1277 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1278
1279 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1280 if (PrintPreciseRTMLockingStatistics) {
1281 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1282 Label check_abort;
1283 testl(abort_status, (1<<i));
1284 jccb(Assembler::equal, check_abort);
1285 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1286 bind(check_abort);
1287 }
1288 }
1289 }
1290
1291 // Branch if (random & (count-1) != 0), count is 2^n
1292 // tmp, scr and flags are killed
1293 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1294 assert(tmp == rax, "");
1295 assert(scr == rdx, "");
1296 rdtsc(); // modifies EDX:EAX
1297 andptr(tmp, count-1);
1298 jccb(Assembler::notZero, brLabel);
1299 }
1300
1301 // Perform abort ratio calculation, set no_rtm bit if high ratio
1302 // input: rtm_counters_Reg (RTMLockingCounters* address)
1303 // tmpReg, rtm_counters_Reg and flags are killed
1304 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1305 Register rtm_counters_Reg,
1306 RTMLockingCounters* rtm_counters,
1307 Metadata* method_data) {
1308 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1309
1310 if (RTMLockingCalculationDelay > 0) {
1311 // Delay calculation
1312 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1313 testptr(tmpReg, tmpReg);
1314 jccb(Assembler::equal, L_done);
1315 }
1316 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1317 // Aborted transactions = abort_count * 100
1318 // All transactions = total_count * RTMTotalCountIncrRate
1319 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1320
1321 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1322 cmpptr(tmpReg, RTMAbortThreshold);
1323 jccb(Assembler::below, L_check_always_rtm2);
1324 imulptr(tmpReg, tmpReg, 100);
1325
1326 Register scrReg = rtm_counters_Reg;
1327 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1328 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1329 imulptr(scrReg, scrReg, RTMAbortRatio);
1330 cmpptr(tmpReg, scrReg);
1331 jccb(Assembler::below, L_check_always_rtm1);
1332 if (method_data != NULL) {
1333 // set rtm_state to "no rtm" in MDO
1334 mov_metadata(tmpReg, method_data);
1335 if (os::is_MP()) {
1336 lock();
1337 }
1338 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1339 }
1340 jmpb(L_done);
1341 bind(L_check_always_rtm1);
1342 // Reload RTMLockingCounters* address
1343 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1344 bind(L_check_always_rtm2);
1345 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1346 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1347 jccb(Assembler::below, L_done);
1348 if (method_data != NULL) {
1349 // set rtm_state to "always rtm" in MDO
1350 mov_metadata(tmpReg, method_data);
1351 if (os::is_MP()) {
1352 lock();
1353 }
1354 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1355 }
1356 bind(L_done);
1357 }
1358
1359 // Update counters and perform abort ratio calculation
1360 // input: abort_status_Reg
1361 // rtm_counters_Reg, flags are killed
1362 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1363 Register rtm_counters_Reg,
1364 RTMLockingCounters* rtm_counters,
1365 Metadata* method_data,
1366 bool profile_rtm) {
1367
1368 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1369 // update rtm counters based on rax value at abort
1370 // reads abort_status_Reg, updates flags
1371 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1372 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1373 if (profile_rtm) {
1374 // Save abort status because abort_status_Reg is used by following code.
1375 if (RTMRetryCount > 0) {
1376 push(abort_status_Reg);
1377 }
1378 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1379 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1380 // restore abort status
1381 if (RTMRetryCount > 0) {
1382 pop(abort_status_Reg);
1383 }
1384 }
1385 }
1386
1387 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1388 // inputs: retry_count_Reg
1389 // : abort_status_Reg
1390 // output: retry_count_Reg decremented by 1
1391 // flags are killed
1392 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1393 Label doneRetry;
1394 assert(abort_status_Reg == rax, "");
1395 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1396 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1397 // if reason is in 0x6 and retry count != 0 then retry
1398 andptr(abort_status_Reg, 0x6);
1399 jccb(Assembler::zero, doneRetry);
1400 testl(retry_count_Reg, retry_count_Reg);
1401 jccb(Assembler::zero, doneRetry);
1402 pause();
1403 decrementl(retry_count_Reg);
1404 jmp(retryLabel);
1405 bind(doneRetry);
1406 }
1407
1408 // Spin and retry if lock is busy,
1409 // inputs: box_Reg (monitor address)
1410 // : retry_count_Reg
1411 // output: retry_count_Reg decremented by 1
1412 // : clear z flag if retry count exceeded
1413 // tmp_Reg, scr_Reg, flags are killed
1414 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1415 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1416 Label SpinLoop, SpinExit, doneRetry;
1417 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1418
1419 testl(retry_count_Reg, retry_count_Reg);
1420 jccb(Assembler::zero, doneRetry);
1421 decrementl(retry_count_Reg);
1422 movptr(scr_Reg, RTMSpinLoopCount);
1423
1424 bind(SpinLoop);
1425 pause();
1426 decrementl(scr_Reg);
1427 jccb(Assembler::lessEqual, SpinExit);
1428 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1429 testptr(tmp_Reg, tmp_Reg);
1430 jccb(Assembler::notZero, SpinLoop);
1431
1432 bind(SpinExit);
1433 jmp(retryLabel);
1434 bind(doneRetry);
1435 incrementl(retry_count_Reg); // clear z flag
1436 }
1437
1438 // Use RTM for normal stack locks
1439 // Input: objReg (object to lock)
1440 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1441 Register retry_on_abort_count_Reg,
1442 RTMLockingCounters* stack_rtm_counters,
1443 Metadata* method_data, bool profile_rtm,
1444 Label& DONE_LABEL, Label& IsInflated) {
1445 assert(UseRTMForStackLocks, "why call this otherwise?");
1446 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1447 assert(tmpReg == rax, "");
1448 assert(scrReg == rdx, "");
1449 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1450
1451 if (RTMRetryCount > 0) {
1452 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1453 bind(L_rtm_retry);
1454 }
1455 movptr(tmpReg, Address(objReg, 0));
1456 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1457 jcc(Assembler::notZero, IsInflated);
1458
1459 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1460 Label L_noincrement;
1461 if (RTMTotalCountIncrRate > 1) {
1462 // tmpReg, scrReg and flags are killed
1463 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1464 }
1465 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1466 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1467 bind(L_noincrement);
1468 }
1469 xbegin(L_on_abort);
1470 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1471 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1472 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1473 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1474
1475 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1476 if (UseRTMXendForLockBusy) {
1477 xend();
1478 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1479 jmp(L_decrement_retry);
1480 }
1481 else {
1482 xabort(0);
1483 }
1484 bind(L_on_abort);
1485 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1486 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1487 }
1488 bind(L_decrement_retry);
1489 if (RTMRetryCount > 0) {
1490 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1491 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1492 }
1493 }
1494
1495 // Use RTM for inflating locks
1496 // inputs: objReg (object to lock)
1497 // boxReg (on-stack box address (displaced header location) - KILLED)
1498 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1499 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1500 Register scrReg, Register retry_on_busy_count_Reg,
1501 Register retry_on_abort_count_Reg,
1502 RTMLockingCounters* rtm_counters,
1503 Metadata* method_data, bool profile_rtm,
1504 Label& DONE_LABEL) {
1505 assert(UseRTMLocking, "why call this otherwise?");
1506 assert(tmpReg == rax, "");
1507 assert(scrReg == rdx, "");
1508 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1509 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1510
1511 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1512 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1513 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1514
1515 if (RTMRetryCount > 0) {
1516 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1517 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1518 bind(L_rtm_retry);
1519 }
1520 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1521 Label L_noincrement;
1522 if (RTMTotalCountIncrRate > 1) {
1523 // tmpReg, scrReg and flags are killed
1524 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1525 }
1526 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1527 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1528 bind(L_noincrement);
1529 }
1530 xbegin(L_on_abort);
1531 movptr(tmpReg, Address(objReg, 0));
1532 movptr(tmpReg, Address(tmpReg, owner_offset));
1533 testptr(tmpReg, tmpReg);
1534 jcc(Assembler::zero, DONE_LABEL);
1535 if (UseRTMXendForLockBusy) {
1536 xend();
1537 jmp(L_decrement_retry);
1538 }
1539 else {
1540 xabort(0);
1541 }
1542 bind(L_on_abort);
1543 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1544 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1545 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1546 }
1547 if (RTMRetryCount > 0) {
1548 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1549 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1550 }
1551
1552 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1553 testptr(tmpReg, tmpReg) ;
1554 jccb(Assembler::notZero, L_decrement_retry) ;
1555
1556 // Appears unlocked - try to swing _owner from null to non-null.
1557 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1558 #ifdef _LP64
1559 Register threadReg = r15_thread;
1560 #else
1561 get_thread(scrReg);
1562 Register threadReg = scrReg;
1563 #endif
1564 if (os::is_MP()) {
1565 lock();
1566 }
1567 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1568
1569 if (RTMRetryCount > 0) {
1570 // success done else retry
1571 jccb(Assembler::equal, DONE_LABEL) ;
1572 bind(L_decrement_retry);
1573 // Spin and retry if lock is busy.
1574 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1575 }
1576 else {
1577 bind(L_decrement_retry);
1578 }
1579 }
1580
1581 #endif // INCLUDE_RTM_OPT
1582
1583 // Fast_Lock and Fast_Unlock used by C2
1584
1585 // Because the transitions from emitted code to the runtime
1586 // monitorenter/exit helper stubs are so slow it's critical that
1587 // we inline both the stack-locking fast-path and the inflated fast path.
1588 //
1589 // See also: cmpFastLock and cmpFastUnlock.
1590 //
1591 // What follows is a specialized inline transliteration of the code
1592 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1593 // another option would be to emit TrySlowEnter and TrySlowExit methods
1594 // at startup-time. These methods would accept arguments as
1595 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1596 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1597 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1598 // In practice, however, the # of lock sites is bounded and is usually small.
1599 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1600 // if the processor uses simple bimodal branch predictors keyed by EIP
1601 // Since the helper routines would be called from multiple synchronization
1602 // sites.
1603 //
1604 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1605 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1606 // to those specialized methods. That'd give us a mostly platform-independent
1607 // implementation that the JITs could optimize and inline at their pleasure.
1608 // Done correctly, the only time we'd need to cross to native could would be
1609 // to park() or unpark() threads. We'd also need a few more unsafe operators
1610 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1611 // (b) explicit barriers or fence operations.
1612 //
1613 // TODO:
1614 //
1615 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1616 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1617 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1618 // the lock operators would typically be faster than reifying Self.
1619 //
1620 // * Ideally I'd define the primitives as:
1621 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1622 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1623 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1624 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1625 // Furthermore the register assignments are overconstrained, possibly resulting in
1626 // sub-optimal code near the synchronization site.
1627 //
1628 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1629 // Alternately, use a better sp-proximity test.
1630 //
1631 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1632 // Either one is sufficient to uniquely identify a thread.
1633 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1634 //
1635 // * Intrinsify notify() and notifyAll() for the common cases where the
1636 // object is locked by the calling thread but the waitlist is empty.
1637 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1638 //
1639 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1640 // But beware of excessive branch density on AMD Opterons.
1641 //
1642 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1643 // or failure of the fast-path. If the fast-path fails then we pass
1644 // control to the slow-path, typically in C. In Fast_Lock and
1645 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1646 // will emit a conditional branch immediately after the node.
1647 // So we have branches to branches and lots of ICC.ZF games.
1648 // Instead, it might be better to have C2 pass a "FailureLabel"
1649 // into Fast_Lock and Fast_Unlock. In the case of success, control
1650 // will drop through the node. ICC.ZF is undefined at exit.
1651 // In the case of failure, the node will branch directly to the
1652 // FailureLabel
1653
1654
1655 // obj: object to lock
1656 // box: on-stack box address (displaced header location) - KILLED
1657 // rax,: tmp -- KILLED
1658 // scr: tmp -- KILLED
1659 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1660 Register scrReg, Register cx1Reg, Register cx2Reg,
1661 BiasedLockingCounters* counters,
1662 RTMLockingCounters* rtm_counters,
1663 RTMLockingCounters* stack_rtm_counters,
1664 Metadata* method_data,
1665 bool use_rtm, bool profile_rtm) {
1666 // Ensure the register assignents are disjoint
1667 assert(tmpReg == rax, "");
1668
1669 if (use_rtm) {
1670 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1671 } else {
1672 assert(cx1Reg == noreg, "");
1673 assert(cx2Reg == noreg, "");
1674 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1675 }
1676
1677 if (counters != NULL) {
1678 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1679 }
1680 if (EmitSync & 1) {
1681 // set box->dhw = markOopDesc::unused_mark()
1682 // Force all sync thru slow-path: slow_enter() and slow_exit()
1683 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1684 cmpptr (rsp, (int32_t)NULL_WORD);
1685 } else {
1686 // Possible cases that we'll encounter in fast_lock
1687 // ------------------------------------------------
1688 // * Inflated
1689 // -- unlocked
1690 // -- Locked
1691 // = by self
1692 // = by other
1693 // * biased
1694 // -- by Self
1695 // -- by other
1696 // * neutral
1697 // * stack-locked
1698 // -- by self
1699 // = sp-proximity test hits
1700 // = sp-proximity test generates false-negative
1701 // -- by other
1702 //
1703
1704 Label IsInflated, DONE_LABEL;
1705
1706 // it's stack-locked, biased or neutral
1707 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1708 // order to reduce the number of conditional branches in the most common cases.
1709 // Beware -- there's a subtle invariant that fetch of the markword
1710 // at [FETCH], below, will never observe a biased encoding (*101b).
1711 // If this invariant is not held we risk exclusion (safety) failure.
1712 if (UseBiasedLocking && !UseOptoBiasInlining) {
1713 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1714 }
1715
1716 #if INCLUDE_RTM_OPT
1717 if (UseRTMForStackLocks && use_rtm) {
1718 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1719 stack_rtm_counters, method_data, profile_rtm,
1720 DONE_LABEL, IsInflated);
1721 }
1722 #endif // INCLUDE_RTM_OPT
1723
1724 movptr(tmpReg, Address(objReg, 0)); // [FETCH]
1725 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1726 jccb(Assembler::notZero, IsInflated);
1727
1728 // Attempt stack-locking ...
1729 orptr (tmpReg, markOopDesc::unlocked_value);
1730 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1731 if (os::is_MP()) {
1732 lock();
1733 }
1734 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1735 if (counters != NULL) {
1736 cond_inc32(Assembler::equal,
1737 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1738 }
1739 jcc(Assembler::equal, DONE_LABEL); // Success
1740
1741 // Recursive locking.
1742 // The object is stack-locked: markword contains stack pointer to BasicLock.
1743 // Locked by current thread if difference with current SP is less than one page.
1744 subptr(tmpReg, rsp);
1745 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1746 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1747 movptr(Address(boxReg, 0), tmpReg);
1748 if (counters != NULL) {
1749 cond_inc32(Assembler::equal,
1750 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1751 }
1752 jmp(DONE_LABEL);
1753
1754 bind(IsInflated);
1755 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1756
1757 #if INCLUDE_RTM_OPT
1758 // Use the same RTM locking code in 32- and 64-bit VM.
1759 if (use_rtm) {
1760 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1761 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1762 } else {
1763 #endif // INCLUDE_RTM_OPT
1764
1765 #ifndef _LP64
1766 // The object is inflated.
1767
1768 // boxReg refers to the on-stack BasicLock in the current frame.
1769 // We'd like to write:
1770 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1771 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1772 // additional latency as we have another ST in the store buffer that must drain.
1773
1774 if (EmitSync & 8192) {
1775 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1776 get_thread (scrReg);
1777 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1778 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1779 if (os::is_MP()) {
1780 lock();
1781 }
1782 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1783 } else
1784 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1785 // register juggle because we need tmpReg for cmpxchgptr below
1786 movptr(scrReg, boxReg);
1787 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1788
1789 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1790 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1791 // prefetchw [eax + Offset(_owner)-2]
1792 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1793 }
1794
1795 if ((EmitSync & 64) == 0) {
1796 // Optimistic form: consider XORL tmpReg,tmpReg
1797 movptr(tmpReg, NULL_WORD);
1798 } else {
1799 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1800 // Test-And-CAS instead of CAS
1801 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1802 testptr(tmpReg, tmpReg); // Locked ?
1803 jccb (Assembler::notZero, DONE_LABEL);
1804 }
1805
1806 // Appears unlocked - try to swing _owner from null to non-null.
1807 // Ideally, I'd manifest "Self" with get_thread and then attempt
1808 // to CAS the register containing Self into m->Owner.
1809 // But we don't have enough registers, so instead we can either try to CAS
1810 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1811 // we later store "Self" into m->Owner. Transiently storing a stack address
1812 // (rsp or the address of the box) into m->owner is harmless.
1813 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1814 if (os::is_MP()) {
1815 lock();
1816 }
1817 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1818 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1819 // If we weren't able to swing _owner from NULL to the BasicLock
1820 // then take the slow path.
1821 jccb (Assembler::notZero, DONE_LABEL);
1822 // update _owner from BasicLock to thread
1823 get_thread (scrReg); // beware: clobbers ICCs
1824 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1825 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1826
1827 // If the CAS fails we can either retry or pass control to the slow-path.
1828 // We use the latter tactic.
1829 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1830 // If the CAS was successful ...
1831 // Self has acquired the lock
1832 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1833 // Intentional fall-through into DONE_LABEL ...
1834 } else {
1835 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1836 movptr(boxReg, tmpReg);
1837
1838 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1839 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1840 // prefetchw [eax + Offset(_owner)-2]
1841 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1842 }
1843
1844 if ((EmitSync & 64) == 0) {
1845 // Optimistic form
1846 xorptr (tmpReg, tmpReg);
1847 } else {
1848 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1849 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1850 testptr(tmpReg, tmpReg); // Locked ?
1851 jccb (Assembler::notZero, DONE_LABEL);
1852 }
1853
1854 // Appears unlocked - try to swing _owner from null to non-null.
1855 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1856 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1857 get_thread (scrReg);
1858 if (os::is_MP()) {
1859 lock();
1860 }
1861 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1862
1863 // If the CAS fails we can either retry or pass control to the slow-path.
1864 // We use the latter tactic.
1865 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1866 // If the CAS was successful ...
1867 // Self has acquired the lock
1868 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1869 // Intentional fall-through into DONE_LABEL ...
1870 }
1871 #else // _LP64
1872 // It's inflated
1873 movq(scrReg, tmpReg);
1874 xorq(tmpReg, tmpReg);
1875
1876 if (os::is_MP()) {
1877 lock();
1878 }
1879 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1880 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1881 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1882 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1883 // Intentional fall-through into DONE_LABEL ...
1884 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1885 #endif // _LP64
1886 #if INCLUDE_RTM_OPT
1887 } // use_rtm()
1888 #endif
1889 // DONE_LABEL is a hot target - we'd really like to place it at the
1890 // start of cache line by padding with NOPs.
1891 // See the AMD and Intel software optimization manuals for the
1892 // most efficient "long" NOP encodings.
1893 // Unfortunately none of our alignment mechanisms suffice.
1894 bind(DONE_LABEL);
1895
1896 // At DONE_LABEL the icc ZFlag is set as follows ...
1897 // Fast_Unlock uses the same protocol.
1898 // ZFlag == 1 -> Success
1899 // ZFlag == 0 -> Failure - force control through the slow-path
1900 }
1901 }
1902
1903 // obj: object to unlock
1904 // box: box address (displaced header location), killed. Must be EAX.
1905 // tmp: killed, cannot be obj nor box.
1906 //
1907 // Some commentary on balanced locking:
1908 //
1909 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1910 // Methods that don't have provably balanced locking are forced to run in the
1911 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1912 // The interpreter provides two properties:
1913 // I1: At return-time the interpreter automatically and quietly unlocks any
1914 // objects acquired the current activation (frame). Recall that the
1915 // interpreter maintains an on-stack list of locks currently held by
1916 // a frame.
1917 // I2: If a method attempts to unlock an object that is not held by the
1918 // the frame the interpreter throws IMSX.
1919 //
1920 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1921 // B() doesn't have provably balanced locking so it runs in the interpreter.
1922 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1923 // is still locked by A().
1924 //
1925 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1926 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1927 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1928 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1929 // Arguably given that the spec legislates the JNI case as undefined our implementation
1930 // could reasonably *avoid* checking owner in Fast_Unlock().
1931 // In the interest of performance we elide m->Owner==Self check in unlock.
1932 // A perfectly viable alternative is to elide the owner check except when
1933 // Xcheck:jni is enabled.
1934
1935 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1936 assert(boxReg == rax, "");
1937 assert_different_registers(objReg, boxReg, tmpReg);
1938
1939 if (EmitSync & 4) {
1940 // Disable - inhibit all inlining. Force control through the slow-path
1941 cmpptr (rsp, 0);
1942 } else {
1943 Label DONE_LABEL, Stacked, CheckSucc;
1944
1945 // Critically, the biased locking test must have precedence over
1946 // and appear before the (box->dhw == 0) recursive stack-lock test.
1947 if (UseBiasedLocking && !UseOptoBiasInlining) {
1948 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1949 }
1950
1951 #if INCLUDE_RTM_OPT
1952 if (UseRTMForStackLocks && use_rtm) {
1953 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1954 Label L_regular_unlock;
1955 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1956 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1957 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1958 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1959 xend(); // otherwise end...
1960 jmp(DONE_LABEL); // ... and we're done
1961 bind(L_regular_unlock);
1962 }
1963 #endif
1964
1965 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1966 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
1967 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword
1968 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
1969 jccb (Assembler::zero, Stacked);
1970
1971 // It's inflated.
1972 #if INCLUDE_RTM_OPT
1973 if (use_rtm) {
1974 Label L_regular_inflated_unlock;
1975 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1976 movptr(boxReg, Address(tmpReg, owner_offset));
1977 testptr(boxReg, boxReg);
1978 jccb(Assembler::notZero, L_regular_inflated_unlock);
1979 xend();
1980 jmpb(DONE_LABEL);
1981 bind(L_regular_inflated_unlock);
1982 }
1983 #endif
1984
1985 // Despite our balanced locking property we still check that m->_owner == Self
1986 // as java routines or native JNI code called by this thread might
1987 // have released the lock.
1988 // Refer to the comments in synchronizer.cpp for how we might encode extra
1989 // state in _succ so we can avoid fetching EntryList|cxq.
1990 //
1991 // I'd like to add more cases in fast_lock() and fast_unlock() --
1992 // such as recursive enter and exit -- but we have to be wary of
1993 // I$ bloat, T$ effects and BP$ effects.
1994 //
1995 // If there's no contention try a 1-0 exit. That is, exit without
1996 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
1997 // we detect and recover from the race that the 1-0 exit admits.
1998 //
1999 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2000 // before it STs null into _owner, releasing the lock. Updates
2001 // to data protected by the critical section must be visible before
2002 // we drop the lock (and thus before any other thread could acquire
2003 // the lock and observe the fields protected by the lock).
2004 // IA32's memory-model is SPO, so STs are ordered with respect to
2005 // each other and there's no need for an explicit barrier (fence).
2006 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2007 #ifndef _LP64
2008 get_thread (boxReg);
2009 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2010 // prefetchw [ebx + Offset(_owner)-2]
2011 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2012 }
2013
2014 // Note that we could employ various encoding schemes to reduce
2015 // the number of loads below (currently 4) to just 2 or 3.
2016 // Refer to the comments in synchronizer.cpp.
2017 // In practice the chain of fetches doesn't seem to impact performance, however.
2018 xorptr(boxReg, boxReg);
2019 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2020 // Attempt to reduce branch density - AMD's branch predictor.
2021 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2022 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2023 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2024 jccb (Assembler::notZero, DONE_LABEL);
2025 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2026 jmpb (DONE_LABEL);
2027 } else {
2028 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2029 jccb (Assembler::notZero, DONE_LABEL);
2030 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2031 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2032 jccb (Assembler::notZero, CheckSucc);
2033 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2034 jmpb (DONE_LABEL);
2035 }
2036
2037 // The Following code fragment (EmitSync & 65536) improves the performance of
2038 // contended applications and contended synchronization microbenchmarks.
2039 // Unfortunately the emission of the code - even though not executed - causes regressions
2040 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2041 // with an equal number of never-executed NOPs results in the same regression.
2042 // We leave it off by default.
2043
2044 if ((EmitSync & 65536) != 0) {
2045 Label LSuccess, LGoSlowPath ;
2046
2047 bind (CheckSucc);
2048
2049 // Optional pre-test ... it's safe to elide this
2050 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2051 jccb(Assembler::zero, LGoSlowPath);
2052
2053 // We have a classic Dekker-style idiom:
2054 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2055 // There are a number of ways to implement the barrier:
2056 // (1) lock:andl &m->_owner, 0
2057 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2058 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2059 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2060 // (2) If supported, an explicit MFENCE is appealing.
2061 // In older IA32 processors MFENCE is slower than lock:add or xchg
2062 // particularly if the write-buffer is full as might be the case if
2063 // if stores closely precede the fence or fence-equivalent instruction.
2064 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2065 // as the situation has changed with Nehalem and Shanghai.
2066 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2067 // The $lines underlying the top-of-stack should be in M-state.
2068 // The locked add instruction is serializing, of course.
2069 // (4) Use xchg, which is serializing
2070 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2071 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2072 // The integer condition codes will tell us if succ was 0.
2073 // Since _succ and _owner should reside in the same $line and
2074 // we just stored into _owner, it's likely that the $line
2075 // remains in M-state for the lock:orl.
2076 //
2077 // We currently use (3), although it's likely that switching to (2)
2078 // is correct for the future.
2079
2080 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2081 if (os::is_MP()) {
2082 lock(); addptr(Address(rsp, 0), 0);
2083 }
2084 // Ratify _succ remains non-null
2085 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2086 jccb (Assembler::notZero, LSuccess);
2087
2088 xorptr(boxReg, boxReg); // box is really EAX
2089 if (os::is_MP()) { lock(); }
2090 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2091 // There's no successor so we tried to regrab the lock with the
2092 // placeholder value. If that didn't work, then another thread
2093 // grabbed the lock so we're done (and exit was a success).
2094 jccb (Assembler::notEqual, LSuccess);
2095 // Since we're low on registers we installed rsp as a placeholding in _owner.
2096 // Now install Self over rsp. This is safe as we're transitioning from
2097 // non-null to non=null
2098 get_thread (boxReg);
2099 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2100 // Intentional fall-through into LGoSlowPath ...
2101
2102 bind (LGoSlowPath);
2103 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2104 jmpb (DONE_LABEL);
2105
2106 bind (LSuccess);
2107 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2108 jmpb (DONE_LABEL);
2109 }
2110
2111 bind (Stacked);
2112 // It's not inflated and it's not recursively stack-locked and it's not biased.
2113 // It must be stack-locked.
2114 // Try to reset the header to displaced header.
2115 // The "box" value on the stack is stable, so we can reload
2116 // and be assured we observe the same value as above.
2117 movptr(tmpReg, Address(boxReg, 0));
2118 if (os::is_MP()) {
2119 lock();
2120 }
2121 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2122 // Intention fall-thru into DONE_LABEL
2123
2124 // DONE_LABEL is a hot target - we'd really like to place it at the
2125 // start of cache line by padding with NOPs.
2126 // See the AMD and Intel software optimization manuals for the
2127 // most efficient "long" NOP encodings.
2128 // Unfortunately none of our alignment mechanisms suffice.
2129 if ((EmitSync & 65536) == 0) {
2130 bind (CheckSucc);
2131 }
2132 #else // _LP64
2133 // It's inflated
2134 if (EmitSync & 1024) {
2135 // Emit code to check that _owner == Self
2136 // We could fold the _owner test into subsequent code more efficiently
2137 // than using a stand-alone check, but since _owner checking is off by
2138 // default we don't bother. We also might consider predicating the
2139 // _owner==Self check on Xcheck:jni or running on a debug build.
2140 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2141 xorptr(boxReg, r15_thread);
2142 } else {
2143 xorptr(boxReg, boxReg);
2144 }
2145 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2146 jccb (Assembler::notZero, DONE_LABEL);
2147 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2148 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2149 jccb (Assembler::notZero, CheckSucc);
2150 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2151 jmpb (DONE_LABEL);
2152
2153 if ((EmitSync & 65536) == 0) {
2154 // Try to avoid passing control into the slow_path ...
2155 Label LSuccess, LGoSlowPath ;
2156 bind (CheckSucc);
2157
2158 // The following optional optimization can be elided if necessary
2159 // Effectively: if (succ == null) goto SlowPath
2160 // The code reduces the window for a race, however,
2161 // and thus benefits performance.
2162 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2163 jccb (Assembler::zero, LGoSlowPath);
2164
2165 if ((EmitSync & 16) && os::is_MP()) {
2166 orptr(boxReg, boxReg);
2167 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2168 } else {
2169 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2170 if (os::is_MP()) {
2171 // Memory barrier/fence
2172 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2173 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2174 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2175 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2176 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2177 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2178 lock(); addl(Address(rsp, 0), 0);
2179 }
2180 }
2181 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2182 jccb (Assembler::notZero, LSuccess);
2183
2184 // Rare inopportune interleaving - race.
2185 // The successor vanished in the small window above.
2186 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2187 // We need to ensure progress and succession.
2188 // Try to reacquire the lock.
2189 // If that fails then the new owner is responsible for succession and this
2190 // thread needs to take no further action and can exit via the fast path (success).
2191 // If the re-acquire succeeds then pass control into the slow path.
2192 // As implemented, this latter mode is horrible because we generated more
2193 // coherence traffic on the lock *and* artifically extended the critical section
2194 // length while by virtue of passing control into the slow path.
2195
2196 // box is really RAX -- the following CMPXCHG depends on that binding
2197 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2198 movptr(boxReg, (int32_t)NULL_WORD);
2199 if (os::is_MP()) { lock(); }
2200 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2201 // There's no successor so we tried to regrab the lock.
2202 // If that didn't work, then another thread grabbed the
2203 // lock so we're done (and exit was a success).
2204 jccb (Assembler::notEqual, LSuccess);
2205 // Intentional fall-through into slow-path
2206
2207 bind (LGoSlowPath);
2208 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2209 jmpb (DONE_LABEL);
2210
2211 bind (LSuccess);
2212 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2213 jmpb (DONE_LABEL);
2214 }
2215
2216 bind (Stacked);
2217 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2218 if (os::is_MP()) { lock(); }
2219 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2220
2221 if (EmitSync & 65536) {
2222 bind (CheckSucc);
2223 }
2224 #endif
2225 bind(DONE_LABEL);
2226 }
2227 }
2228 #endif // COMPILER2
2229
2230 void MacroAssembler::c2bool(Register x) {
2231 // implements x == 0 ? 0 : 1
2232 // note: must only look at least-significant byte of x
2233 // since C-style booleans are stored in one byte
2234 // only! (was bug)
2235 andl(x, 0xFF);
2236 setb(Assembler::notZero, x);
2237 }
2238
2239 // Wouldn't need if AddressLiteral version had new name
2240 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2241 Assembler::call(L, rtype);
2242 }
2243
2244 void MacroAssembler::call(Register entry) {
2245 Assembler::call(entry);
2246 }
2247
2248 void MacroAssembler::call(AddressLiteral entry) {
2249 if (reachable(entry)) {
2250 Assembler::call_literal(entry.target(), entry.rspec());
2251 } else {
2252 lea(rscratch1, entry);
2253 Assembler::call(rscratch1);
2254 }
2255 }
2256
2257 void MacroAssembler::ic_call(address entry) {
2258 RelocationHolder rh = virtual_call_Relocation::spec(pc());
2259 movptr(rax, (intptr_t)Universe::non_oop_word());
2260 call(AddressLiteral(entry, rh));
2261 }
2262
2263 // Implementation of call_VM versions
2264
2265 void MacroAssembler::call_VM(Register oop_result,
2266 address entry_point,
2267 bool check_exceptions) {
2268 Label C, E;
2269 call(C, relocInfo::none);
2270 jmp(E);
2271
2272 bind(C);
2273 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2274 ret(0);
2275
2276 bind(E);
2277 }
2278
2279 void MacroAssembler::call_VM(Register oop_result,
2280 address entry_point,
2281 Register arg_1,
2282 bool check_exceptions) {
2283 Label C, E;
2284 call(C, relocInfo::none);
2285 jmp(E);
2286
2287 bind(C);
2288 pass_arg1(this, arg_1);
2289 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2290 ret(0);
2291
2292 bind(E);
2293 }
2294
2295 void MacroAssembler::call_VM(Register oop_result,
2296 address entry_point,
2297 Register arg_1,
2298 Register arg_2,
2299 bool check_exceptions) {
2300 Label C, E;
2301 call(C, relocInfo::none);
2302 jmp(E);
2303
2304 bind(C);
2305
2306 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2307
2308 pass_arg2(this, arg_2);
2309 pass_arg1(this, arg_1);
2310 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2311 ret(0);
2312
2313 bind(E);
2314 }
2315
2316 void MacroAssembler::call_VM(Register oop_result,
2317 address entry_point,
2318 Register arg_1,
2319 Register arg_2,
2320 Register arg_3,
2321 bool check_exceptions) {
2322 Label C, E;
2323 call(C, relocInfo::none);
2324 jmp(E);
2325
2326 bind(C);
2327
2328 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2329 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2330 pass_arg3(this, arg_3);
2331
2332 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2333 pass_arg2(this, arg_2);
2334
2335 pass_arg1(this, arg_1);
2336 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2337 ret(0);
2338
2339 bind(E);
2340 }
2341
2342 void MacroAssembler::call_VM(Register oop_result,
2343 Register last_java_sp,
2344 address entry_point,
2345 int number_of_arguments,
2346 bool check_exceptions) {
2347 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2348 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2349 }
2350
2351 void MacroAssembler::call_VM(Register oop_result,
2352 Register last_java_sp,
2353 address entry_point,
2354 Register arg_1,
2355 bool check_exceptions) {
2356 pass_arg1(this, arg_1);
2357 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2358 }
2359
2360 void MacroAssembler::call_VM(Register oop_result,
2361 Register last_java_sp,
2362 address entry_point,
2363 Register arg_1,
2364 Register arg_2,
2365 bool check_exceptions) {
2366
2367 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2368 pass_arg2(this, arg_2);
2369 pass_arg1(this, arg_1);
2370 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2371 }
2372
2373 void MacroAssembler::call_VM(Register oop_result,
2374 Register last_java_sp,
2375 address entry_point,
2376 Register arg_1,
2377 Register arg_2,
2378 Register arg_3,
2379 bool check_exceptions) {
2380 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2381 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2382 pass_arg3(this, arg_3);
2383 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2384 pass_arg2(this, arg_2);
2385 pass_arg1(this, arg_1);
2386 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2387 }
2388
2389 void MacroAssembler::super_call_VM(Register oop_result,
2390 Register last_java_sp,
2391 address entry_point,
2392 int number_of_arguments,
2393 bool check_exceptions) {
2394 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2395 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2396 }
2397
2398 void MacroAssembler::super_call_VM(Register oop_result,
2399 Register last_java_sp,
2400 address entry_point,
2401 Register arg_1,
2402 bool check_exceptions) {
2403 pass_arg1(this, arg_1);
2404 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2405 }
2406
2407 void MacroAssembler::super_call_VM(Register oop_result,
2408 Register last_java_sp,
2409 address entry_point,
2410 Register arg_1,
2411 Register arg_2,
2412 bool check_exceptions) {
2413
2414 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2415 pass_arg2(this, arg_2);
2416 pass_arg1(this, arg_1);
2417 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2418 }
2419
2420 void MacroAssembler::super_call_VM(Register oop_result,
2421 Register last_java_sp,
2422 address entry_point,
2423 Register arg_1,
2424 Register arg_2,
2425 Register arg_3,
2426 bool check_exceptions) {
2427 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2428 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2429 pass_arg3(this, arg_3);
2430 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2431 pass_arg2(this, arg_2);
2432 pass_arg1(this, arg_1);
2433 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2434 }
2435
2436 void MacroAssembler::call_VM_base(Register oop_result,
2437 Register java_thread,
2438 Register last_java_sp,
2439 address entry_point,
2440 int number_of_arguments,
2441 bool check_exceptions) {
2442 // determine java_thread register
2443 if (!java_thread->is_valid()) {
2444 #ifdef _LP64
2445 java_thread = r15_thread;
2446 #else
2447 java_thread = rdi;
2448 get_thread(java_thread);
2449 #endif // LP64
2450 }
2451 // determine last_java_sp register
2452 if (!last_java_sp->is_valid()) {
2453 last_java_sp = rsp;
2454 }
2455 // debugging support
2456 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2457 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2458 #ifdef ASSERT
2459 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2460 // r12 is the heapbase.
2461 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2462 #endif // ASSERT
2463
2464 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2465 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2466
2467 // push java thread (becomes first argument of C function)
2468
2469 NOT_LP64(push(java_thread); number_of_arguments++);
2470 LP64_ONLY(mov(c_rarg0, r15_thread));
2471
2472 // set last Java frame before call
2473 assert(last_java_sp != rbp, "can't use ebp/rbp");
2474
2475 // Only interpreter should have to set fp
2476 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2477
2478 // do the call, remove parameters
2479 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2480
2481 // restore the thread (cannot use the pushed argument since arguments
2482 // may be overwritten by C code generated by an optimizing compiler);
2483 // however can use the register value directly if it is callee saved.
2484 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2485 // rdi & rsi (also r15) are callee saved -> nothing to do
2486 #ifdef ASSERT
2487 guarantee(java_thread != rax, "change this code");
2488 push(rax);
2489 { Label L;
2490 get_thread(rax);
2491 cmpptr(java_thread, rax);
2492 jcc(Assembler::equal, L);
2493 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2494 bind(L);
2495 }
2496 pop(rax);
2497 #endif
2498 } else {
2499 get_thread(java_thread);
2500 }
2501 // reset last Java frame
2502 // Only interpreter should have to clear fp
2503 reset_last_Java_frame(java_thread, true, false);
2504
2505 #ifndef CC_INTERP
2506 // C++ interp handles this in the interpreter
2507 check_and_handle_popframe(java_thread);
2508 check_and_handle_earlyret(java_thread);
2509 #endif /* CC_INTERP */
2510
2511 if (check_exceptions) {
2512 // check for pending exceptions (java_thread is set upon return)
2513 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2514 #ifndef _LP64
2515 jump_cc(Assembler::notEqual,
2516 RuntimeAddress(StubRoutines::forward_exception_entry()));
2517 #else
2518 // This used to conditionally jump to forward_exception however it is
2519 // possible if we relocate that the branch will not reach. So we must jump
2520 // around so we can always reach
2521
2522 Label ok;
2523 jcc(Assembler::equal, ok);
2524 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2525 bind(ok);
2526 #endif // LP64
2527 }
2528
2529 // get oop result if there is one and reset the value in the thread
2530 if (oop_result->is_valid()) {
2531 get_vm_result(oop_result, java_thread);
2532 }
2533 }
2534
2535 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2536
2537 // Calculate the value for last_Java_sp
2538 // somewhat subtle. call_VM does an intermediate call
2539 // which places a return address on the stack just under the
2540 // stack pointer as the user finsihed with it. This allows
2541 // use to retrieve last_Java_pc from last_Java_sp[-1].
2542 // On 32bit we then have to push additional args on the stack to accomplish
2543 // the actual requested call. On 64bit call_VM only can use register args
2544 // so the only extra space is the return address that call_VM created.
2545 // This hopefully explains the calculations here.
2546
2547 #ifdef _LP64
2548 // We've pushed one address, correct last_Java_sp
2549 lea(rax, Address(rsp, wordSize));
2550 #else
2551 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2552 #endif // LP64
2553
2554 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2555
2556 }
2557
2558 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2559 call_VM_leaf_base(entry_point, number_of_arguments);
2560 }
2561
2562 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2563 pass_arg0(this, arg_0);
2564 call_VM_leaf(entry_point, 1);
2565 }
2566
2567 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2568
2569 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2570 pass_arg1(this, arg_1);
2571 pass_arg0(this, arg_0);
2572 call_VM_leaf(entry_point, 2);
2573 }
2574
2575 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2576 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2577 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2578 pass_arg2(this, arg_2);
2579 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2580 pass_arg1(this, arg_1);
2581 pass_arg0(this, arg_0);
2582 call_VM_leaf(entry_point, 3);
2583 }
2584
2585 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2586 pass_arg0(this, arg_0);
2587 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2588 }
2589
2590 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2591
2592 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2593 pass_arg1(this, arg_1);
2594 pass_arg0(this, arg_0);
2595 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2596 }
2597
2598 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2599 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2600 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2601 pass_arg2(this, arg_2);
2602 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2603 pass_arg1(this, arg_1);
2604 pass_arg0(this, arg_0);
2605 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2606 }
2607
2608 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2609 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2610 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2611 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2612 pass_arg3(this, arg_3);
2613 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2614 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2615 pass_arg2(this, arg_2);
2616 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2617 pass_arg1(this, arg_1);
2618 pass_arg0(this, arg_0);
2619 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2620 }
2621
2622 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2623 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2624 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2625 verify_oop(oop_result, "broken oop in call_VM_base");
2626 }
2627
2628 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2629 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2630 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2631 }
2632
2633 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2634 }
2635
2636 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2637 }
2638
2639 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2640 if (reachable(src1)) {
2641 cmpl(as_Address(src1), imm);
2642 } else {
2643 lea(rscratch1, src1);
2644 cmpl(Address(rscratch1, 0), imm);
2645 }
2646 }
2647
2648 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2649 assert(!src2.is_lval(), "use cmpptr");
2650 if (reachable(src2)) {
2651 cmpl(src1, as_Address(src2));
2652 } else {
2653 lea(rscratch1, src2);
2654 cmpl(src1, Address(rscratch1, 0));
2655 }
2656 }
2657
2658 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2659 Assembler::cmpl(src1, imm);
2660 }
2661
2662 void MacroAssembler::cmp32(Register src1, Address src2) {
2663 Assembler::cmpl(src1, src2);
2664 }
2665
2666 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2667 ucomisd(opr1, opr2);
2668
2669 Label L;
2670 if (unordered_is_less) {
2671 movl(dst, -1);
2672 jcc(Assembler::parity, L);
2673 jcc(Assembler::below , L);
2674 movl(dst, 0);
2675 jcc(Assembler::equal , L);
2676 increment(dst);
2677 } else { // unordered is greater
2678 movl(dst, 1);
2679 jcc(Assembler::parity, L);
2680 jcc(Assembler::above , L);
2681 movl(dst, 0);
2682 jcc(Assembler::equal , L);
2683 decrementl(dst);
2684 }
2685 bind(L);
2686 }
2687
2688 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2689 ucomiss(opr1, opr2);
2690
2691 Label L;
2692 if (unordered_is_less) {
2693 movl(dst, -1);
2694 jcc(Assembler::parity, L);
2695 jcc(Assembler::below , L);
2696 movl(dst, 0);
2697 jcc(Assembler::equal , L);
2698 increment(dst);
2699 } else { // unordered is greater
2700 movl(dst, 1);
2701 jcc(Assembler::parity, L);
2702 jcc(Assembler::above , L);
2703 movl(dst, 0);
2704 jcc(Assembler::equal , L);
2705 decrementl(dst);
2706 }
2707 bind(L);
2708 }
2709
2710
2711 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2712 if (reachable(src1)) {
2713 cmpb(as_Address(src1), imm);
2714 } else {
2715 lea(rscratch1, src1);
2716 cmpb(Address(rscratch1, 0), imm);
2717 }
2718 }
2719
2720 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2721 #ifdef _LP64
2722 if (src2.is_lval()) {
2723 movptr(rscratch1, src2);
2724 Assembler::cmpq(src1, rscratch1);
2725 } else if (reachable(src2)) {
2726 cmpq(src1, as_Address(src2));
2727 } else {
2728 lea(rscratch1, src2);
2729 Assembler::cmpq(src1, Address(rscratch1, 0));
2730 }
2731 #else
2732 if (src2.is_lval()) {
2733 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2734 } else {
2735 cmpl(src1, as_Address(src2));
2736 }
2737 #endif // _LP64
2738 }
2739
2740 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2741 assert(src2.is_lval(), "not a mem-mem compare");
2742 #ifdef _LP64
2743 // moves src2's literal address
2744 movptr(rscratch1, src2);
2745 Assembler::cmpq(src1, rscratch1);
2746 #else
2747 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2748 #endif // _LP64
2749 }
2750
2751 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2752 if (reachable(adr)) {
2753 if (os::is_MP())
2754 lock();
2755 cmpxchgptr(reg, as_Address(adr));
2756 } else {
2757 lea(rscratch1, adr);
2758 if (os::is_MP())
2759 lock();
2760 cmpxchgptr(reg, Address(rscratch1, 0));
2761 }
2762 }
2763
2764 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2765 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2766 }
2767
2768 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2769 if (reachable(src)) {
2770 Assembler::comisd(dst, as_Address(src));
2771 } else {
2772 lea(rscratch1, src);
2773 Assembler::comisd(dst, Address(rscratch1, 0));
2774 }
2775 }
2776
2777 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2778 if (reachable(src)) {
2779 Assembler::comiss(dst, as_Address(src));
2780 } else {
2781 lea(rscratch1, src);
2782 Assembler::comiss(dst, Address(rscratch1, 0));
2783 }
2784 }
2785
2786
2787 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2788 Condition negated_cond = negate_condition(cond);
2789 Label L;
2790 jcc(negated_cond, L);
2791 pushf(); // Preserve flags
2792 atomic_incl(counter_addr);
2793 popf();
2794 bind(L);
2795 }
2796
2797 int MacroAssembler::corrected_idivl(Register reg) {
2798 // Full implementation of Java idiv and irem; checks for
2799 // special case as described in JVM spec., p.243 & p.271.
2800 // The function returns the (pc) offset of the idivl
2801 // instruction - may be needed for implicit exceptions.
2802 //
2803 // normal case special case
2804 //
2805 // input : rax,: dividend min_int
2806 // reg: divisor (may not be rax,/rdx) -1
2807 //
2808 // output: rax,: quotient (= rax, idiv reg) min_int
2809 // rdx: remainder (= rax, irem reg) 0
2810 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2811 const int min_int = 0x80000000;
2812 Label normal_case, special_case;
2813
2814 // check for special case
2815 cmpl(rax, min_int);
2816 jcc(Assembler::notEqual, normal_case);
2817 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2818 cmpl(reg, -1);
2819 jcc(Assembler::equal, special_case);
2820
2821 // handle normal case
2822 bind(normal_case);
2823 cdql();
2824 int idivl_offset = offset();
2825 idivl(reg);
2826
2827 // normal and special case exit
2828 bind(special_case);
2829
2830 return idivl_offset;
2831 }
2832
2833
2834
2835 void MacroAssembler::decrementl(Register reg, int value) {
2836 if (value == min_jint) {subl(reg, value) ; return; }
2837 if (value < 0) { incrementl(reg, -value); return; }
2838 if (value == 0) { ; return; }
2839 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2840 /* else */ { subl(reg, value) ; return; }
2841 }
2842
2843 void MacroAssembler::decrementl(Address dst, int value) {
2844 if (value == min_jint) {subl(dst, value) ; return; }
2845 if (value < 0) { incrementl(dst, -value); return; }
2846 if (value == 0) { ; return; }
2847 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2848 /* else */ { subl(dst, value) ; return; }
2849 }
2850
2851 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2852 assert (shift_value > 0, "illegal shift value");
2853 Label _is_positive;
2854 testl (reg, reg);
2855 jcc (Assembler::positive, _is_positive);
2856 int offset = (1 << shift_value) - 1 ;
2857
2858 if (offset == 1) {
2859 incrementl(reg);
2860 } else {
2861 addl(reg, offset);
2862 }
2863
2864 bind (_is_positive);
2865 sarl(reg, shift_value);
2866 }
2867
2868 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2869 if (reachable(src)) {
2870 Assembler::divsd(dst, as_Address(src));
2871 } else {
2872 lea(rscratch1, src);
2873 Assembler::divsd(dst, Address(rscratch1, 0));
2874 }
2875 }
2876
2877 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2878 if (reachable(src)) {
2879 Assembler::divss(dst, as_Address(src));
2880 } else {
2881 lea(rscratch1, src);
2882 Assembler::divss(dst, Address(rscratch1, 0));
2883 }
2884 }
2885
2886 // !defined(COMPILER2) is because of stupid core builds
2887 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
2888 void MacroAssembler::empty_FPU_stack() {
2889 if (VM_Version::supports_mmx()) {
2890 emms();
2891 } else {
2892 for (int i = 8; i-- > 0; ) ffree(i);
2893 }
2894 }
2895 #endif // !LP64 || C1 || !C2
2896
2897
2898 // Defines obj, preserves var_size_in_bytes
2899 void MacroAssembler::eden_allocate(Register obj,
2900 Register var_size_in_bytes,
2901 int con_size_in_bytes,
2902 Register t1,
2903 Label& slow_case) {
2904 assert(obj == rax, "obj must be in rax, for cmpxchg");
2905 assert_different_registers(obj, var_size_in_bytes, t1);
2906 if (!Universe::heap()->supports_inline_contig_alloc()) {
2907 jmp(slow_case);
2908 } else {
2909 Register end = t1;
2910 Label retry;
2911 bind(retry);
2912 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2913 movptr(obj, heap_top);
2914 if (var_size_in_bytes == noreg) {
2915 lea(end, Address(obj, con_size_in_bytes));
2916 } else {
2917 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2918 }
2919 // if end < obj then we wrapped around => object too long => slow case
2920 cmpptr(end, obj);
2921 jcc(Assembler::below, slow_case);
2922 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2923 jcc(Assembler::above, slow_case);
2924 // Compare obj with the top addr, and if still equal, store the new top addr in
2925 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2926 // it otherwise. Use lock prefix for atomicity on MPs.
2927 locked_cmpxchgptr(end, heap_top);
2928 jcc(Assembler::notEqual, retry);
2929 }
2930 }
2931
2932 void MacroAssembler::enter() {
2933 push(rbp);
2934 mov(rbp, rsp);
2935 }
2936
2937 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2938 void MacroAssembler::fat_nop() {
2939 if (UseAddressNop) {
2940 addr_nop_5();
2941 } else {
2942 emit_int8(0x26); // es:
2943 emit_int8(0x2e); // cs:
2944 emit_int8(0x64); // fs:
2945 emit_int8(0x65); // gs:
2946 emit_int8((unsigned char)0x90);
2947 }
2948 }
2949
2950 void MacroAssembler::fcmp(Register tmp) {
2951 fcmp(tmp, 1, true, true);
2952 }
2953
2954 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2955 assert(!pop_right || pop_left, "usage error");
2956 if (VM_Version::supports_cmov()) {
2957 assert(tmp == noreg, "unneeded temp");
2958 if (pop_left) {
2959 fucomip(index);
2960 } else {
2961 fucomi(index);
2962 }
2963 if (pop_right) {
2964 fpop();
2965 }
2966 } else {
2967 assert(tmp != noreg, "need temp");
2968 if (pop_left) {
2969 if (pop_right) {
2970 fcompp();
2971 } else {
2972 fcomp(index);
2973 }
2974 } else {
2975 fcom(index);
2976 }
2977 // convert FPU condition into eflags condition via rax,
2978 save_rax(tmp);
2979 fwait(); fnstsw_ax();
2980 sahf();
2981 restore_rax(tmp);
2982 }
2983 // condition codes set as follows:
2984 //
2985 // CF (corresponds to C0) if x < y
2986 // PF (corresponds to C2) if unordered
2987 // ZF (corresponds to C3) if x = y
2988 }
2989
2990 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2991 fcmp2int(dst, unordered_is_less, 1, true, true);
2992 }
2993
2994 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2995 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2996 Label L;
2997 if (unordered_is_less) {
2998 movl(dst, -1);
2999 jcc(Assembler::parity, L);
3000 jcc(Assembler::below , L);
3001 movl(dst, 0);
3002 jcc(Assembler::equal , L);
3003 increment(dst);
3004 } else { // unordered is greater
3005 movl(dst, 1);
3006 jcc(Assembler::parity, L);
3007 jcc(Assembler::above , L);
3008 movl(dst, 0);
3009 jcc(Assembler::equal , L);
3010 decrementl(dst);
3011 }
3012 bind(L);
3013 }
3014
3015 void MacroAssembler::fld_d(AddressLiteral src) {
3016 fld_d(as_Address(src));
3017 }
3018
3019 void MacroAssembler::fld_s(AddressLiteral src) {
3020 fld_s(as_Address(src));
3021 }
3022
3023 void MacroAssembler::fld_x(AddressLiteral src) {
3024 Assembler::fld_x(as_Address(src));
3025 }
3026
3027 void MacroAssembler::fldcw(AddressLiteral src) {
3028 Assembler::fldcw(as_Address(src));
3029 }
3030
3031 void MacroAssembler::pow_exp_core_encoding() {
3032 // kills rax, rcx, rdx
3033 subptr(rsp,sizeof(jdouble));
3034 // computes 2^X. Stack: X ...
3035 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and
3036 // keep it on the thread's stack to compute 2^int(X) later
3037 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1)
3038 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X))
3039 fld_s(0); // Stack: X X ...
3040 frndint(); // Stack: int(X) X ...
3041 fsuba(1); // Stack: int(X) X-int(X) ...
3042 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ...
3043 f2xm1(); // Stack: 2^(X-int(X))-1 ...
3044 fld1(); // Stack: 1 2^(X-int(X))-1 ...
3045 faddp(1); // Stack: 2^(X-int(X))
3046 // computes 2^(int(X)): add exponent bias (1023) to int(X), then
3047 // shift int(X)+1023 to exponent position.
3048 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11
3049 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent
3050 // values so detect them and set result to NaN.
3051 movl(rax,Address(rsp,0));
3052 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding
3053 addl(rax, 1023);
3054 movl(rdx,rax);
3055 shll(rax,20);
3056 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN.
3057 addl(rdx,1);
3058 // Check that 1 < int(X)+1023+1 < 2048
3059 // in 3 steps:
3060 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048
3061 // 2- (int(X)+1023+1)&-2048 != 0
3062 // 3- (int(X)+1023+1)&-2048 != 1
3063 // Do 2- first because addl just updated the flags.
3064 cmov32(Assembler::equal,rax,rcx);
3065 cmpl(rdx,1);
3066 cmov32(Assembler::equal,rax,rcx);
3067 testl(rdx,rcx);
3068 cmov32(Assembler::notEqual,rax,rcx);
3069 movl(Address(rsp,4),rax);
3070 movl(Address(rsp,0),0);
3071 fmul_d(Address(rsp,0)); // Stack: 2^X ...
3072 addptr(rsp,sizeof(jdouble));
3073 }
3074
3075 void MacroAssembler::increase_precision() {
3076 subptr(rsp, BytesPerWord);
3077 fnstcw(Address(rsp, 0));
3078 movl(rax, Address(rsp, 0));
3079 orl(rax, 0x300);
3080 push(rax);
3081 fldcw(Address(rsp, 0));
3082 pop(rax);
3083 }
3084
3085 void MacroAssembler::restore_precision() {
3086 fldcw(Address(rsp, 0));
3087 addptr(rsp, BytesPerWord);
3088 }
3089
3090 void MacroAssembler::fast_pow() {
3091 // computes X^Y = 2^(Y * log2(X))
3092 // if fast computation is not possible, result is NaN. Requires
3093 // fallback from user of this macro.
3094 // increase precision for intermediate steps of the computation
3095 BLOCK_COMMENT("fast_pow {");
3096 increase_precision();
3097 fyl2x(); // Stack: (Y*log2(X)) ...
3098 pow_exp_core_encoding(); // Stack: exp(X) ...
3099 restore_precision();
3100 BLOCK_COMMENT("} fast_pow");
3101 }
3102
3103 void MacroAssembler::fast_exp() {
3104 // computes exp(X) = 2^(X * log2(e))
3105 // if fast computation is not possible, result is NaN. Requires
3106 // fallback from user of this macro.
3107 // increase precision for intermediate steps of the computation
3108 increase_precision();
3109 fldl2e(); // Stack: log2(e) X ...
3110 fmulp(1); // Stack: (X*log2(e)) ...
3111 pow_exp_core_encoding(); // Stack: exp(X) ...
3112 restore_precision();
3113 }
3114
3115 void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) {
3116 // kills rax, rcx, rdx
3117 // pow and exp needs 2 extra registers on the fpu stack.
3118 Label slow_case, done;
3119 Register tmp = noreg;
3120 if (!VM_Version::supports_cmov()) {
3121 // fcmp needs a temporary so preserve rdx,
3122 tmp = rdx;
3123 }
3124 Register tmp2 = rax;
3125 Register tmp3 = rcx;
3126
3127 if (is_exp) {
3128 // Stack: X
3129 fld_s(0); // duplicate argument for runtime call. Stack: X X
3130 fast_exp(); // Stack: exp(X) X
3131 fcmp(tmp, 0, false, false); // Stack: exp(X) X
3132 // exp(X) not equal to itself: exp(X) is NaN go to slow case.
3133 jcc(Assembler::parity, slow_case);
3134 // get rid of duplicate argument. Stack: exp(X)
3135 if (num_fpu_regs_in_use > 0) {
3136 fxch();
3137 fpop();
3138 } else {
3139 ffree(1);
3140 }
3141 jmp(done);
3142 } else {
3143 // Stack: X Y
3144 Label x_negative, y_not_2;
3145
3146 static double two = 2.0;
3147 ExternalAddress two_addr((address)&two);
3148
3149 // constant maybe too far on 64 bit
3150 lea(tmp2, two_addr);
3151 fld_d(Address(tmp2, 0)); // Stack: 2 X Y
3152 fcmp(tmp, 2, true, false); // Stack: X Y
3153 jcc(Assembler::parity, y_not_2);
3154 jcc(Assembler::notEqual, y_not_2);
3155
3156 fxch(); fpop(); // Stack: X
3157 fmul(0); // Stack: X*X
3158
3159 jmp(done);
3160
3161 bind(y_not_2);
3162
3163 fldz(); // Stack: 0 X Y
3164 fcmp(tmp, 1, true, false); // Stack: X Y
3165 jcc(Assembler::above, x_negative);
3166
3167 // X >= 0
3168
3169 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3170 fld_s(1); // Stack: X Y X Y
3171 fast_pow(); // Stack: X^Y X Y
3172 fcmp(tmp, 0, false, false); // Stack: X^Y X Y
3173 // X^Y not equal to itself: X^Y is NaN go to slow case.
3174 jcc(Assembler::parity, slow_case);
3175 // get rid of duplicate arguments. Stack: X^Y
3176 if (num_fpu_regs_in_use > 0) {
3177 fxch(); fpop();
3178 fxch(); fpop();
3179 } else {
3180 ffree(2);
3181 ffree(1);
3182 }
3183 jmp(done);
3184
3185 // X <= 0
3186 bind(x_negative);
3187
3188 fld_s(1); // Stack: Y X Y
3189 frndint(); // Stack: int(Y) X Y
3190 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y
3191 jcc(Assembler::notEqual, slow_case);
3192
3193 subptr(rsp, 8);
3194
3195 // For X^Y, when X < 0, Y has to be an integer and the final
3196 // result depends on whether it's odd or even. We just checked
3197 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit
3198 // integer to test its parity. If int(Y) is huge and doesn't fit
3199 // in the 64 bit integer range, the integer indefinite value will
3200 // end up in the gp registers. Huge numbers are all even, the
3201 // integer indefinite number is even so it's fine.
3202
3203 #ifdef ASSERT
3204 // Let's check we don't end up with an integer indefinite number
3205 // when not expected. First test for huge numbers: check whether
3206 // int(Y)+1 == int(Y) which is true for very large numbers and
3207 // those are all even. A 64 bit integer is guaranteed to not
3208 // overflow for numbers where y+1 != y (when precision is set to
3209 // double precision).
3210 Label y_not_huge;
3211
3212 fld1(); // Stack: 1 int(Y) X Y
3213 fadd(1); // Stack: 1+int(Y) int(Y) X Y
3214
3215 #ifdef _LP64
3216 // trip to memory to force the precision down from double extended
3217 // precision
3218 fstp_d(Address(rsp, 0));
3219 fld_d(Address(rsp, 0));
3220 #endif
3221
3222 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y
3223 #endif
3224
3225 // move int(Y) as 64 bit integer to thread's stack
3226 fistp_d(Address(rsp,0)); // Stack: X Y
3227
3228 #ifdef ASSERT
3229 jcc(Assembler::notEqual, y_not_huge);
3230
3231 // Y is huge so we know it's even. It may not fit in a 64 bit
3232 // integer and we don't want the debug code below to see the
3233 // integer indefinite value so overwrite int(Y) on the thread's
3234 // stack with 0.
3235 movl(Address(rsp, 0), 0);
3236 movl(Address(rsp, 4), 0);
3237
3238 bind(y_not_huge);
3239 #endif
3240
3241 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3242 fld_s(1); // Stack: X Y X Y
3243 fabs(); // Stack: abs(X) Y X Y
3244 fast_pow(); // Stack: abs(X)^Y X Y
3245 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y
3246 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case.
3247
3248 pop(tmp2);
3249 NOT_LP64(pop(tmp3));
3250 jcc(Assembler::parity, slow_case);
3251
3252 #ifdef ASSERT
3253 // Check that int(Y) is not integer indefinite value (int
3254 // overflow). Shouldn't happen because for values that would
3255 // overflow, 1+int(Y)==Y which was tested earlier.
3256 #ifndef _LP64
3257 {
3258 Label integer;
3259 testl(tmp2, tmp2);
3260 jcc(Assembler::notZero, integer);
3261 cmpl(tmp3, 0x80000000);
3262 jcc(Assembler::notZero, integer);
3263 STOP("integer indefinite value shouldn't be seen here");
3264 bind(integer);
3265 }
3266 #else
3267 {
3268 Label integer;
3269 mov(tmp3, tmp2); // preserve tmp2 for parity check below
3270 shlq(tmp3, 1);
3271 jcc(Assembler::carryClear, integer);
3272 jcc(Assembler::notZero, integer);
3273 STOP("integer indefinite value shouldn't be seen here");
3274 bind(integer);
3275 }
3276 #endif
3277 #endif
3278
3279 // get rid of duplicate arguments. Stack: X^Y
3280 if (num_fpu_regs_in_use > 0) {
3281 fxch(); fpop();
3282 fxch(); fpop();
3283 } else {
3284 ffree(2);
3285 ffree(1);
3286 }
3287
3288 testl(tmp2, 1);
3289 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y
3290 // X <= 0, Y even: X^Y = -abs(X)^Y
3291
3292 fchs(); // Stack: -abs(X)^Y Y
3293 jmp(done);
3294 }
3295
3296 // slow case: runtime call
3297 bind(slow_case);
3298
3299 fpop(); // pop incorrect result or int(Y)
3300
3301 fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow),
3302 is_exp ? 1 : 2, num_fpu_regs_in_use);
3303
3304 // Come here with result in F-TOS
3305 bind(done);
3306 }
3307
3308 void MacroAssembler::fpop() {
3309 ffree();
3310 fincstp();
3311 }
3312
3313 void MacroAssembler::fremr(Register tmp) {
3314 save_rax(tmp);
3315 { Label L;
3316 bind(L);
3317 fprem();
3318 fwait(); fnstsw_ax();
3319 #ifdef _LP64
3320 testl(rax, 0x400);
3321 jcc(Assembler::notEqual, L);
3322 #else
3323 sahf();
3324 jcc(Assembler::parity, L);
3325 #endif // _LP64
3326 }
3327 restore_rax(tmp);
3328 // Result is in ST0.
3329 // Note: fxch & fpop to get rid of ST1
3330 // (otherwise FPU stack could overflow eventually)
3331 fxch(1);
3332 fpop();
3333 }
3334
3335
3336 void MacroAssembler::incrementl(AddressLiteral dst) {
3337 if (reachable(dst)) {
3338 incrementl(as_Address(dst));
3339 } else {
3340 lea(rscratch1, dst);
3341 incrementl(Address(rscratch1, 0));
3342 }
3343 }
3344
3345 void MacroAssembler::incrementl(ArrayAddress dst) {
3346 incrementl(as_Address(dst));
3347 }
3348
3349 void MacroAssembler::incrementl(Register reg, int value) {
3350 if (value == min_jint) {addl(reg, value) ; return; }
3351 if (value < 0) { decrementl(reg, -value); return; }
3352 if (value == 0) { ; return; }
3353 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3354 /* else */ { addl(reg, value) ; return; }
3355 }
3356
3357 void MacroAssembler::incrementl(Address dst, int value) {
3358 if (value == min_jint) {addl(dst, value) ; return; }
3359 if (value < 0) { decrementl(dst, -value); return; }
3360 if (value == 0) { ; return; }
3361 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3362 /* else */ { addl(dst, value) ; return; }
3363 }
3364
3365 void MacroAssembler::jump(AddressLiteral dst) {
3366 if (reachable(dst)) {
3367 jmp_literal(dst.target(), dst.rspec());
3368 } else {
3369 lea(rscratch1, dst);
3370 jmp(rscratch1);
3371 }
3372 }
3373
3374 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3375 if (reachable(dst)) {
3376 InstructionMark im(this);
3377 relocate(dst.reloc());
3378 const int short_size = 2;
3379 const int long_size = 6;
3380 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3381 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3382 // 0111 tttn #8-bit disp
3383 emit_int8(0x70 | cc);
3384 emit_int8((offs - short_size) & 0xFF);
3385 } else {
3386 // 0000 1111 1000 tttn #32-bit disp
3387 emit_int8(0x0F);
3388 emit_int8((unsigned char)(0x80 | cc));
3389 emit_int32(offs - long_size);
3390 }
3391 } else {
3392 #ifdef ASSERT
3393 warning("reversing conditional branch");
3394 #endif /* ASSERT */
3395 Label skip;
3396 jccb(reverse[cc], skip);
3397 lea(rscratch1, dst);
3398 Assembler::jmp(rscratch1);
3399 bind(skip);
3400 }
3401 }
3402
3403 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3404 if (reachable(src)) {
3405 Assembler::ldmxcsr(as_Address(src));
3406 } else {
3407 lea(rscratch1, src);
3408 Assembler::ldmxcsr(Address(rscratch1, 0));
3409 }
3410 }
3411
3412 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3413 int off;
3414 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3415 off = offset();
3416 movsbl(dst, src); // movsxb
3417 } else {
3418 off = load_unsigned_byte(dst, src);
3419 shll(dst, 24);
3420 sarl(dst, 24);
3421 }
3422 return off;
3423 }
3424
3425 // Note: load_signed_short used to be called load_signed_word.
3426 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3427 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3428 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3429 int MacroAssembler::load_signed_short(Register dst, Address src) {
3430 int off;
3431 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3432 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3433 // version but this is what 64bit has always done. This seems to imply
3434 // that users are only using 32bits worth.
3435 off = offset();
3436 movswl(dst, src); // movsxw
3437 } else {
3438 off = load_unsigned_short(dst, src);
3439 shll(dst, 16);
3440 sarl(dst, 16);
3441 }
3442 return off;
3443 }
3444
3445 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3446 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3447 // and "3.9 Partial Register Penalties", p. 22).
3448 int off;
3449 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3450 off = offset();
3451 movzbl(dst, src); // movzxb
3452 } else {
3453 xorl(dst, dst);
3454 off = offset();
3455 movb(dst, src);
3456 }
3457 return off;
3458 }
3459
3460 // Note: load_unsigned_short used to be called load_unsigned_word.
3461 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3462 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3463 // and "3.9 Partial Register Penalties", p. 22).
3464 int off;
3465 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3466 off = offset();
3467 movzwl(dst, src); // movzxw
3468 } else {
3469 xorl(dst, dst);
3470 off = offset();
3471 movw(dst, src);
3472 }
3473 return off;
3474 }
3475
3476 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3477 switch (size_in_bytes) {
3478 #ifndef _LP64
3479 case 8:
3480 assert(dst2 != noreg, "second dest register required");
3481 movl(dst, src);
3482 movl(dst2, src.plus_disp(BytesPerInt));
3483 break;
3484 #else
3485 case 8: movq(dst, src); break;
3486 #endif
3487 case 4: movl(dst, src); break;
3488 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3489 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3490 default: ShouldNotReachHere();
3491 }
3492 }
3493
3494 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3495 switch (size_in_bytes) {
3496 #ifndef _LP64
3497 case 8:
3498 assert(src2 != noreg, "second source register required");
3499 movl(dst, src);
3500 movl(dst.plus_disp(BytesPerInt), src2);
3501 break;
3502 #else
3503 case 8: movq(dst, src); break;
3504 #endif
3505 case 4: movl(dst, src); break;
3506 case 2: movw(dst, src); break;
3507 case 1: movb(dst, src); break;
3508 default: ShouldNotReachHere();
3509 }
3510 }
3511
3512 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3513 if (reachable(dst)) {
3514 movl(as_Address(dst), src);
3515 } else {
3516 lea(rscratch1, dst);
3517 movl(Address(rscratch1, 0), src);
3518 }
3519 }
3520
3521 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3522 if (reachable(src)) {
3523 movl(dst, as_Address(src));
3524 } else {
3525 lea(rscratch1, src);
3526 movl(dst, Address(rscratch1, 0));
3527 }
3528 }
3529
3530 // C++ bool manipulation
3531
3532 void MacroAssembler::movbool(Register dst, Address src) {
3533 if(sizeof(bool) == 1)
3534 movb(dst, src);
3535 else if(sizeof(bool) == 2)
3536 movw(dst, src);
3537 else if(sizeof(bool) == 4)
3538 movl(dst, src);
3539 else
3540 // unsupported
3541 ShouldNotReachHere();
3542 }
3543
3544 void MacroAssembler::movbool(Address dst, bool boolconst) {
3545 if(sizeof(bool) == 1)
3546 movb(dst, (int) boolconst);
3547 else if(sizeof(bool) == 2)
3548 movw(dst, (int) boolconst);
3549 else if(sizeof(bool) == 4)
3550 movl(dst, (int) boolconst);
3551 else
3552 // unsupported
3553 ShouldNotReachHere();
3554 }
3555
3556 void MacroAssembler::movbool(Address dst, Register src) {
3557 if(sizeof(bool) == 1)
3558 movb(dst, src);
3559 else if(sizeof(bool) == 2)
3560 movw(dst, src);
3561 else if(sizeof(bool) == 4)
3562 movl(dst, src);
3563 else
3564 // unsupported
3565 ShouldNotReachHere();
3566 }
3567
3568 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3569 movb(as_Address(dst), src);
3570 }
3571
3572 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3573 if (reachable(src)) {
3574 movdl(dst, as_Address(src));
3575 } else {
3576 lea(rscratch1, src);
3577 movdl(dst, Address(rscratch1, 0));
3578 }
3579 }
3580
3581 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3582 if (reachable(src)) {
3583 movq(dst, as_Address(src));
3584 } else {
3585 lea(rscratch1, src);
3586 movq(dst, Address(rscratch1, 0));
3587 }
3588 }
3589
3590 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3591 if (reachable(src)) {
3592 if (UseXmmLoadAndClearUpper) {
3593 movsd (dst, as_Address(src));
3594 } else {
3595 movlpd(dst, as_Address(src));
3596 }
3597 } else {
3598 lea(rscratch1, src);
3599 if (UseXmmLoadAndClearUpper) {
3600 movsd (dst, Address(rscratch1, 0));
3601 } else {
3602 movlpd(dst, Address(rscratch1, 0));
3603 }
3604 }
3605 }
3606
3607 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3608 if (reachable(src)) {
3609 movss(dst, as_Address(src));
3610 } else {
3611 lea(rscratch1, src);
3612 movss(dst, Address(rscratch1, 0));
3613 }
3614 }
3615
3616 void MacroAssembler::movptr(Register dst, Register src) {
3617 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3618 }
3619
3620 void MacroAssembler::movptr(Register dst, Address src) {
3621 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3622 }
3623
3624 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3625 void MacroAssembler::movptr(Register dst, intptr_t src) {
3626 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3627 }
3628
3629 void MacroAssembler::movptr(Address dst, Register src) {
3630 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3631 }
3632
3633 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
3634 if (reachable(src)) {
3635 Assembler::movdqu(dst, as_Address(src));
3636 } else {
3637 lea(rscratch1, src);
3638 Assembler::movdqu(dst, Address(rscratch1, 0));
3639 }
3640 }
3641
3642 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3643 if (reachable(src)) {
3644 Assembler::movdqa(dst, as_Address(src));
3645 } else {
3646 lea(rscratch1, src);
3647 Assembler::movdqa(dst, Address(rscratch1, 0));
3648 }
3649 }
3650
3651 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3652 if (reachable(src)) {
3653 Assembler::movsd(dst, as_Address(src));
3654 } else {
3655 lea(rscratch1, src);
3656 Assembler::movsd(dst, Address(rscratch1, 0));
3657 }
3658 }
3659
3660 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3661 if (reachable(src)) {
3662 Assembler::movss(dst, as_Address(src));
3663 } else {
3664 lea(rscratch1, src);
3665 Assembler::movss(dst, Address(rscratch1, 0));
3666 }
3667 }
3668
3669 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3670 if (reachable(src)) {
3671 Assembler::mulsd(dst, as_Address(src));
3672 } else {
3673 lea(rscratch1, src);
3674 Assembler::mulsd(dst, Address(rscratch1, 0));
3675 }
3676 }
3677
3678 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3679 if (reachable(src)) {
3680 Assembler::mulss(dst, as_Address(src));
3681 } else {
3682 lea(rscratch1, src);
3683 Assembler::mulss(dst, Address(rscratch1, 0));
3684 }
3685 }
3686
3687 void MacroAssembler::null_check(Register reg, int offset) {
3688 if (needs_explicit_null_check(offset)) {
3689 // provoke OS NULL exception if reg = NULL by
3690 // accessing M[reg] w/o changing any (non-CC) registers
3691 // NOTE: cmpl is plenty here to provoke a segv
3692 cmpptr(rax, Address(reg, 0));
3693 // Note: should probably use testl(rax, Address(reg, 0));
3694 // may be shorter code (however, this version of
3695 // testl needs to be implemented first)
3696 } else {
3697 // nothing to do, (later) access of M[reg + offset]
3698 // will provoke OS NULL exception if reg = NULL
3699 }
3700 }
3701
3702 void MacroAssembler::os_breakpoint() {
3703 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3704 // (e.g., MSVC can't call ps() otherwise)
3705 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3706 }
3707
3708 void MacroAssembler::pop_CPU_state() {
3709 pop_FPU_state();
3710 pop_IU_state();
3711 }
3712
3713 void MacroAssembler::pop_FPU_state() {
3714 NOT_LP64(frstor(Address(rsp, 0));)
3715 LP64_ONLY(fxrstor(Address(rsp, 0));)
3716 addptr(rsp, FPUStateSizeInWords * wordSize);
3717 }
3718
3719 void MacroAssembler::pop_IU_state() {
3720 popa();
3721 LP64_ONLY(addq(rsp, 8));
3722 popf();
3723 }
3724
3725 // Save Integer and Float state
3726 // Warning: Stack must be 16 byte aligned (64bit)
3727 void MacroAssembler::push_CPU_state() {
3728 push_IU_state();
3729 push_FPU_state();
3730 }
3731
3732 void MacroAssembler::push_FPU_state() {
3733 subptr(rsp, FPUStateSizeInWords * wordSize);
3734 #ifndef _LP64
3735 fnsave(Address(rsp, 0));
3736 fwait();
3737 #else
3738 fxsave(Address(rsp, 0));
3739 #endif // LP64
3740 }
3741
3742 void MacroAssembler::push_IU_state() {
3743 // Push flags first because pusha kills them
3744 pushf();
3745 // Make sure rsp stays 16-byte aligned
3746 LP64_ONLY(subq(rsp, 8));
3747 pusha();
3748 }
3749
3750 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
3751 // determine java_thread register
3752 if (!java_thread->is_valid()) {
3753 java_thread = rdi;
3754 get_thread(java_thread);
3755 }
3756 // we must set sp to zero to clear frame
3757 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3758 if (clear_fp) {
3759 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3760 }
3761
3762 if (clear_pc)
3763 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3764
3765 }
3766
3767 void MacroAssembler::restore_rax(Register tmp) {
3768 if (tmp == noreg) pop(rax);
3769 else if (tmp != rax) mov(rax, tmp);
3770 }
3771
3772 void MacroAssembler::round_to(Register reg, int modulus) {
3773 addptr(reg, modulus - 1);
3774 andptr(reg, -modulus);
3775 }
3776
3777 void MacroAssembler::save_rax(Register tmp) {
3778 if (tmp == noreg) push(rax);
3779 else if (tmp != rax) mov(tmp, rax);
3780 }
3781
3782 // Write serialization page so VM thread can do a pseudo remote membar.
3783 // We use the current thread pointer to calculate a thread specific
3784 // offset to write to within the page. This minimizes bus traffic
3785 // due to cache line collision.
3786 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3787 movl(tmp, thread);
3788 shrl(tmp, os::get_serialize_page_shift_count());
3789 andl(tmp, (os::vm_page_size() - sizeof(int)));
3790
3791 Address index(noreg, tmp, Address::times_1);
3792 ExternalAddress page(os::get_memory_serialize_page());
3793
3794 // Size of store must match masking code above
3795 movl(as_Address(ArrayAddress(page, index)), tmp);
3796 }
3797
3798 // Calls to C land
3799 //
3800 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3801 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3802 // has to be reset to 0. This is required to allow proper stack traversal.
3803 void MacroAssembler::set_last_Java_frame(Register java_thread,
3804 Register last_java_sp,
3805 Register last_java_fp,
3806 address last_java_pc) {
3807 // determine java_thread register
3808 if (!java_thread->is_valid()) {
3809 java_thread = rdi;
3810 get_thread(java_thread);
3811 }
3812 // determine last_java_sp register
3813 if (!last_java_sp->is_valid()) {
3814 last_java_sp = rsp;
3815 }
3816
3817 // last_java_fp is optional
3818
3819 if (last_java_fp->is_valid()) {
3820 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3821 }
3822
3823 // last_java_pc is optional
3824
3825 if (last_java_pc != NULL) {
3826 lea(Address(java_thread,
3827 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3828 InternalAddress(last_java_pc));
3829
3830 }
3831 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3832 }
3833
3834 void MacroAssembler::shlptr(Register dst, int imm8) {
3835 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3836 }
3837
3838 void MacroAssembler::shrptr(Register dst, int imm8) {
3839 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3840 }
3841
3842 void MacroAssembler::sign_extend_byte(Register reg) {
3843 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3844 movsbl(reg, reg); // movsxb
3845 } else {
3846 shll(reg, 24);
3847 sarl(reg, 24);
3848 }
3849 }
3850
3851 void MacroAssembler::sign_extend_short(Register reg) {
3852 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3853 movswl(reg, reg); // movsxw
3854 } else {
3855 shll(reg, 16);
3856 sarl(reg, 16);
3857 }
3858 }
3859
3860 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3861 assert(reachable(src), "Address should be reachable");
3862 testl(dst, as_Address(src));
3863 }
3864
3865 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3866 if (reachable(src)) {
3867 Assembler::sqrtsd(dst, as_Address(src));
3868 } else {
3869 lea(rscratch1, src);
3870 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3871 }
3872 }
3873
3874 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3875 if (reachable(src)) {
3876 Assembler::sqrtss(dst, as_Address(src));
3877 } else {
3878 lea(rscratch1, src);
3879 Assembler::sqrtss(dst, Address(rscratch1, 0));
3880 }
3881 }
3882
3883 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3884 if (reachable(src)) {
3885 Assembler::subsd(dst, as_Address(src));
3886 } else {
3887 lea(rscratch1, src);
3888 Assembler::subsd(dst, Address(rscratch1, 0));
3889 }
3890 }
3891
3892 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3893 if (reachable(src)) {
3894 Assembler::subss(dst, as_Address(src));
3895 } else {
3896 lea(rscratch1, src);
3897 Assembler::subss(dst, Address(rscratch1, 0));
3898 }
3899 }
3900
3901 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3902 if (reachable(src)) {
3903 Assembler::ucomisd(dst, as_Address(src));
3904 } else {
3905 lea(rscratch1, src);
3906 Assembler::ucomisd(dst, Address(rscratch1, 0));
3907 }
3908 }
3909
3910 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3911 if (reachable(src)) {
3912 Assembler::ucomiss(dst, as_Address(src));
3913 } else {
3914 lea(rscratch1, src);
3915 Assembler::ucomiss(dst, Address(rscratch1, 0));
3916 }
3917 }
3918
3919 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
3920 // Used in sign-bit flipping with aligned address.
3921 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3922 if (reachable(src)) {
3923 Assembler::xorpd(dst, as_Address(src));
3924 } else {
3925 lea(rscratch1, src);
3926 Assembler::xorpd(dst, Address(rscratch1, 0));
3927 }
3928 }
3929
3930 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
3931 // Used in sign-bit flipping with aligned address.
3932 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3933 if (reachable(src)) {
3934 Assembler::xorps(dst, as_Address(src));
3935 } else {
3936 lea(rscratch1, src);
3937 Assembler::xorps(dst, Address(rscratch1, 0));
3938 }
3939 }
3940
3941 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3942 // Used in sign-bit flipping with aligned address.
3943 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3944 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3945 if (reachable(src)) {
3946 Assembler::pshufb(dst, as_Address(src));
3947 } else {
3948 lea(rscratch1, src);
3949 Assembler::pshufb(dst, Address(rscratch1, 0));
3950 }
3951 }
3952
3953 // AVX 3-operands instructions
3954
3955 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3956 if (reachable(src)) {
3957 vaddsd(dst, nds, as_Address(src));
3958 } else {
3959 lea(rscratch1, src);
3960 vaddsd(dst, nds, Address(rscratch1, 0));
3961 }
3962 }
3963
3964 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3965 if (reachable(src)) {
3966 vaddss(dst, nds, as_Address(src));
3967 } else {
3968 lea(rscratch1, src);
3969 vaddss(dst, nds, Address(rscratch1, 0));
3970 }
3971 }
3972
3973 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
3974 if (reachable(src)) {
3975 vandpd(dst, nds, as_Address(src), vector_len);
3976 } else {
3977 lea(rscratch1, src);
3978 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
3979 }
3980 }
3981
3982 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
3983 if (reachable(src)) {
3984 vandps(dst, nds, as_Address(src), vector_len);
3985 } else {
3986 lea(rscratch1, src);
3987 vandps(dst, nds, Address(rscratch1, 0), vector_len);
3988 }
3989 }
3990
3991 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3992 if (reachable(src)) {
3993 vdivsd(dst, nds, as_Address(src));
3994 } else {
3995 lea(rscratch1, src);
3996 vdivsd(dst, nds, Address(rscratch1, 0));
3997 }
3998 }
3999
4000 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4001 if (reachable(src)) {
4002 vdivss(dst, nds, as_Address(src));
4003 } else {
4004 lea(rscratch1, src);
4005 vdivss(dst, nds, Address(rscratch1, 0));
4006 }
4007 }
4008
4009 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4010 if (reachable(src)) {
4011 vmulsd(dst, nds, as_Address(src));
4012 } else {
4013 lea(rscratch1, src);
4014 vmulsd(dst, nds, Address(rscratch1, 0));
4015 }
4016 }
4017
4018 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4019 if (reachable(src)) {
4020 vmulss(dst, nds, as_Address(src));
4021 } else {
4022 lea(rscratch1, src);
4023 vmulss(dst, nds, Address(rscratch1, 0));
4024 }
4025 }
4026
4027 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4028 if (reachable(src)) {
4029 vsubsd(dst, nds, as_Address(src));
4030 } else {
4031 lea(rscratch1, src);
4032 vsubsd(dst, nds, Address(rscratch1, 0));
4033 }
4034 }
4035
4036 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4037 if (reachable(src)) {
4038 vsubss(dst, nds, as_Address(src));
4039 } else {
4040 lea(rscratch1, src);
4041 vsubss(dst, nds, Address(rscratch1, 0));
4042 }
4043 }
4044
4045 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4046 if (reachable(src)) {
4047 vxorpd(dst, nds, as_Address(src), vector_len);
4048 } else {
4049 lea(rscratch1, src);
4050 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
4051 }
4052 }
4053
4054 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4055 if (reachable(src)) {
4056 vxorps(dst, nds, as_Address(src), vector_len);
4057 } else {
4058 lea(rscratch1, src);
4059 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
4060 }
4061 }
4062
4063
4064 //////////////////////////////////////////////////////////////////////////////////
4065 #if INCLUDE_ALL_GCS
4066
4067 void MacroAssembler::g1_write_barrier_pre(Register obj,
4068 Register pre_val,
4069 Register thread,
4070 Register tmp,
4071 bool tosca_live,
4072 bool expand_call) {
4073
4074 // If expand_call is true then we expand the call_VM_leaf macro
4075 // directly to skip generating the check by
4076 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
4077
4078 #ifdef _LP64
4079 assert(thread == r15_thread, "must be");
4080 #endif // _LP64
4081
4082 Label done;
4083 Label runtime;
4084
4085 assert(pre_val != noreg, "check this code");
4086
4087 if (obj != noreg) {
4088 assert_different_registers(obj, pre_val, tmp);
4089 assert(pre_val != rax, "check this code");
4090 }
4091
4092 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4093 PtrQueue::byte_offset_of_active()));
4094 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4095 PtrQueue::byte_offset_of_index()));
4096 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4097 PtrQueue::byte_offset_of_buf()));
4098
4099
4100 // Is marking active?
4101 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4102 cmpl(in_progress, 0);
4103 } else {
4104 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
4105 cmpb(in_progress, 0);
4106 }
4107 jcc(Assembler::equal, done);
4108
4109 // Do we need to load the previous value?
4110 if (obj != noreg) {
4111 load_heap_oop(pre_val, Address(obj, 0));
4112 }
4113
4114 // Is the previous value null?
4115 cmpptr(pre_val, (int32_t) NULL_WORD);
4116 jcc(Assembler::equal, done);
4117
4118 // Can we store original value in the thread's buffer?
4119 // Is index == 0?
4120 // (The index field is typed as size_t.)
4121
4122 movptr(tmp, index); // tmp := *index_adr
4123 cmpptr(tmp, 0); // tmp == 0?
4124 jcc(Assembler::equal, runtime); // If yes, goto runtime
4125
4126 subptr(tmp, wordSize); // tmp := tmp - wordSize
4127 movptr(index, tmp); // *index_adr := tmp
4128 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
4129
4130 // Record the previous value
4131 movptr(Address(tmp, 0), pre_val);
4132 jmp(done);
4133
4134 bind(runtime);
4135 // save the live input values
4136 if(tosca_live) push(rax);
4137
4138 if (obj != noreg && obj != rax)
4139 push(obj);
4140
4141 if (pre_val != rax)
4142 push(pre_val);
4143
4144 // Calling the runtime using the regular call_VM_leaf mechanism generates
4145 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
4146 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
4147 //
4148 // If we care generating the pre-barrier without a frame (e.g. in the
4149 // intrinsified Reference.get() routine) then ebp might be pointing to
4150 // the caller frame and so this check will most likely fail at runtime.
4151 //
4152 // Expanding the call directly bypasses the generation of the check.
4153 // So when we do not have have a full interpreter frame on the stack
4154 // expand_call should be passed true.
4155
4156 NOT_LP64( push(thread); )
4157
4158 if (expand_call) {
4159 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
4160 pass_arg1(this, thread);
4161 pass_arg0(this, pre_val);
4162 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
4163 } else {
4164 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
4165 }
4166
4167 NOT_LP64( pop(thread); )
4168
4169 // save the live input values
4170 if (pre_val != rax)
4171 pop(pre_val);
4172
4173 if (obj != noreg && obj != rax)
4174 pop(obj);
4175
4176 if(tosca_live) pop(rax);
4177
4178 bind(done);
4179 }
4180
4181 void MacroAssembler::g1_write_barrier_post(Register store_addr,
4182 Register new_val,
4183 Register thread,
4184 Register tmp,
4185 Register tmp2) {
4186 #ifdef _LP64
4187 assert(thread == r15_thread, "must be");
4188 #endif // _LP64
4189
4190 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4191 PtrQueue::byte_offset_of_index()));
4192 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4193 PtrQueue::byte_offset_of_buf()));
4194
4195 CardTableModRefBS* ct =
4196 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set());
4197 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4198
4199 Label done;
4200 Label runtime;
4201
4202 // Does store cross heap regions?
4203
4204 movptr(tmp, store_addr);
4205 xorptr(tmp, new_val);
4206 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
4207 jcc(Assembler::equal, done);
4208
4209 // crosses regions, storing NULL?
4210
4211 cmpptr(new_val, (int32_t) NULL_WORD);
4212 jcc(Assembler::equal, done);
4213
4214 // storing region crossing non-NULL, is card already dirty?
4215
4216 const Register card_addr = tmp;
4217 const Register cardtable = tmp2;
4218
4219 movptr(card_addr, store_addr);
4220 shrptr(card_addr, CardTableModRefBS::card_shift);
4221 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
4222 // a valid address and therefore is not properly handled by the relocation code.
4223 movptr(cardtable, (intptr_t)ct->byte_map_base);
4224 addptr(card_addr, cardtable);
4225
4226 if (G1ElideMembar) {
4227 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::clean_card_val());
4228 jcc(Assembler::notEqual, done);
4229 } else {
4230 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
4231 jcc(Assembler::equal, done);
4232
4233 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4234 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4235 jcc(Assembler::equal, done);
4236 }
4237
4238 // storing a region crossing, non-NULL oop, card is clean.
4239 // dirty card and log.
4240
4241 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4242
4243 cmpl(queue_index, 0);
4244 jcc(Assembler::equal, runtime);
4245 subl(queue_index, wordSize);
4246 movptr(tmp2, buffer);
4247 #ifdef _LP64
4248 movslq(rscratch1, queue_index);
4249 addq(tmp2, rscratch1);
4250 movq(Address(tmp2, 0), card_addr);
4251 #else
4252 addl(tmp2, queue_index);
4253 movl(Address(tmp2, 0), card_addr);
4254 #endif
4255 jmp(done);
4256
4257 bind(runtime);
4258 // save the live input values
4259 push(store_addr);
4260 push(new_val);
4261 #ifdef _LP64
4262 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
4263 #else
4264 push(thread);
4265 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
4266 pop(thread);
4267 #endif
4268 pop(new_val);
4269 pop(store_addr);
4270
4271 bind(done);
4272 }
4273
4274 #endif // INCLUDE_ALL_GCS
4275 //////////////////////////////////////////////////////////////////////////////////
4276
4277
4278 void MacroAssembler::store_check(Register obj, Address dst) {
4279 store_check(obj);
4280 }
4281
4282 void MacroAssembler::store_check(Register obj) {
4283 // Does a store check for the oop in register obj. The content of
4284 // register obj is destroyed afterwards.
4285
4286 BarrierSet* bs = Universe::heap()->barrier_set();
4287 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4288
4289 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
4290 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4291
4292 shrptr(obj, CardTableModRefBS::card_shift);
4293
4294 Address card_addr;
4295
4296 // The calculation for byte_map_base is as follows:
4297 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
4298 // So this essentially converts an address to a displacement and it will
4299 // never need to be relocated. On 64bit however the value may be too
4300 // large for a 32bit displacement.
4301 intptr_t disp = (intptr_t) ct->byte_map_base;
4302 if (is_simm32(disp)) {
4303 card_addr = Address(noreg, obj, Address::times_1, disp);
4304 } else {
4305 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
4306 // displacement and done in a single instruction given favorable mapping and a
4307 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
4308 // entry and that entry is not properly handled by the relocation code.
4309 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
4310 Address index(noreg, obj, Address::times_1);
4311 card_addr = as_Address(ArrayAddress(cardtable, index));
4312 }
4313
4314 int dirty = CardTableModRefBS::dirty_card_val();
4315 if (UseCondCardMark) {
4316 Label L_already_dirty;
4317 if (UseConcMarkSweepGC) {
4318 membar(Assembler::StoreLoad);
4319 }
4320 cmpb(card_addr, dirty);
4321 jcc(Assembler::equal, L_already_dirty);
4322 movb(card_addr, dirty);
4323 bind(L_already_dirty);
4324 } else {
4325 movb(card_addr, dirty);
4326 }
4327 }
4328
4329 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4330 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4331 }
4332
4333 // Force generation of a 4 byte immediate value even if it fits into 8bit
4334 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4335 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4336 }
4337
4338 void MacroAssembler::subptr(Register dst, Register src) {
4339 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4340 }
4341
4342 // C++ bool manipulation
4343 void MacroAssembler::testbool(Register dst) {
4344 if(sizeof(bool) == 1)
4345 testb(dst, 0xff);
4346 else if(sizeof(bool) == 2) {
4347 // testw implementation needed for two byte bools
4348 ShouldNotReachHere();
4349 } else if(sizeof(bool) == 4)
4350 testl(dst, dst);
4351 else
4352 // unsupported
4353 ShouldNotReachHere();
4354 }
4355
4356 void MacroAssembler::testptr(Register dst, Register src) {
4357 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4358 }
4359
4360 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4361 void MacroAssembler::tlab_allocate(Register obj,
4362 Register var_size_in_bytes,
4363 int con_size_in_bytes,
4364 Register t1,
4365 Register t2,
4366 Label& slow_case) {
4367 assert_different_registers(obj, t1, t2);
4368 assert_different_registers(obj, var_size_in_bytes, t1);
4369 Register end = t2;
4370 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
4371
4372 verify_tlab();
4373
4374 NOT_LP64(get_thread(thread));
4375
4376 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
4377 if (var_size_in_bytes == noreg) {
4378 lea(end, Address(obj, con_size_in_bytes));
4379 } else {
4380 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
4381 }
4382 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
4383 jcc(Assembler::above, slow_case);
4384
4385 // update the tlab top pointer
4386 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
4387
4388 // recover var_size_in_bytes if necessary
4389 if (var_size_in_bytes == end) {
4390 subptr(var_size_in_bytes, obj);
4391 }
4392 verify_tlab();
4393 }
4394
4395 // Preserves rbx, and rdx.
4396 Register MacroAssembler::tlab_refill(Label& retry,
4397 Label& try_eden,
4398 Label& slow_case) {
4399 Register top = rax;
4400 Register t1 = rcx;
4401 Register t2 = rsi;
4402 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
4403 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
4404 Label do_refill, discard_tlab;
4405
4406 if (!Universe::heap()->supports_inline_contig_alloc()) {
4407 // No allocation in the shared eden.
4408 jmp(slow_case);
4409 }
4410
4411 NOT_LP64(get_thread(thread_reg));
4412
4413 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4414 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4415
4416 // calculate amount of free space
4417 subptr(t1, top);
4418 shrptr(t1, LogHeapWordSize);
4419
4420 // Retain tlab and allocate object in shared space if
4421 // the amount free in the tlab is too large to discard.
4422 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
4423 jcc(Assembler::lessEqual, discard_tlab);
4424
4425 // Retain
4426 // %%% yuck as movptr...
4427 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
4428 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
4429 if (TLABStats) {
4430 // increment number of slow_allocations
4431 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
4432 }
4433 jmp(try_eden);
4434
4435 bind(discard_tlab);
4436 if (TLABStats) {
4437 // increment number of refills
4438 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
4439 // accumulate wastage -- t1 is amount free in tlab
4440 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
4441 }
4442
4443 // if tlab is currently allocated (top or end != null) then
4444 // fill [top, end + alignment_reserve) with array object
4445 testptr(top, top);
4446 jcc(Assembler::zero, do_refill);
4447
4448 // set up the mark word
4449 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
4450 // set the length to the remaining space
4451 subptr(t1, typeArrayOopDesc::header_size(T_INT));
4452 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
4453 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
4454 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
4455 // set klass to intArrayKlass
4456 // dubious reloc why not an oop reloc?
4457 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
4458 // store klass last. concurrent gcs assumes klass length is valid if
4459 // klass field is not null.
4460 store_klass(top, t1);
4461
4462 movptr(t1, top);
4463 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4464 incr_allocated_bytes(thread_reg, t1, 0);
4465
4466 // refill the tlab with an eden allocation
4467 bind(do_refill);
4468 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4469 shlptr(t1, LogHeapWordSize);
4470 // allocate new tlab, address returned in top
4471 eden_allocate(top, t1, 0, t2, slow_case);
4472
4473 // Check that t1 was preserved in eden_allocate.
4474 #ifdef ASSERT
4475 if (UseTLAB) {
4476 Label ok;
4477 Register tsize = rsi;
4478 assert_different_registers(tsize, thread_reg, t1);
4479 push(tsize);
4480 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4481 shlptr(tsize, LogHeapWordSize);
4482 cmpptr(t1, tsize);
4483 jcc(Assembler::equal, ok);
4484 STOP("assert(t1 != tlab size)");
4485 should_not_reach_here();
4486
4487 bind(ok);
4488 pop(tsize);
4489 }
4490 #endif
4491 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
4492 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
4493 addptr(top, t1);
4494 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
4495 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
4496 verify_tlab();
4497 jmp(retry);
4498
4499 return thread_reg; // for use by caller
4500 }
4501
4502 void MacroAssembler::incr_allocated_bytes(Register thread,
4503 Register var_size_in_bytes,
4504 int con_size_in_bytes,
4505 Register t1) {
4506 if (!thread->is_valid()) {
4507 #ifdef _LP64
4508 thread = r15_thread;
4509 #else
4510 assert(t1->is_valid(), "need temp reg");
4511 thread = t1;
4512 get_thread(thread);
4513 #endif
4514 }
4515
4516 #ifdef _LP64
4517 if (var_size_in_bytes->is_valid()) {
4518 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4519 } else {
4520 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4521 }
4522 #else
4523 if (var_size_in_bytes->is_valid()) {
4524 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4525 } else {
4526 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4527 }
4528 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
4529 #endif
4530 }
4531
4532 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
4533 pusha();
4534
4535 // if we are coming from c1, xmm registers may be live
4536 int off = 0;
4537 if (UseSSE == 1) {
4538 subptr(rsp, sizeof(jdouble)*8);
4539 movflt(Address(rsp,off++*sizeof(jdouble)),xmm0);
4540 movflt(Address(rsp,off++*sizeof(jdouble)),xmm1);
4541 movflt(Address(rsp,off++*sizeof(jdouble)),xmm2);
4542 movflt(Address(rsp,off++*sizeof(jdouble)),xmm3);
4543 movflt(Address(rsp,off++*sizeof(jdouble)),xmm4);
4544 movflt(Address(rsp,off++*sizeof(jdouble)),xmm5);
4545 movflt(Address(rsp,off++*sizeof(jdouble)),xmm6);
4546 movflt(Address(rsp,off++*sizeof(jdouble)),xmm7);
4547 } else if (UseSSE >= 2) {
4548 if (UseAVX > 2) {
4549 movl(rbx, 0xffff);
4550 #ifdef _LP64
4551 kmovql(k1, rbx);
4552 #else
4553 kmovdl(k1, rbx);
4554 #endif
4555 }
4556 #ifdef COMPILER2
4557 if (MaxVectorSize > 16) {
4558 assert(UseAVX > 0, "256bit vectors are supported only with AVX");
4559 // Save upper half of YMM registes
4560 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4561 vextractf128h(Address(rsp, 0),xmm0);
4562 vextractf128h(Address(rsp, 16),xmm1);
4563 vextractf128h(Address(rsp, 32),xmm2);
4564 vextractf128h(Address(rsp, 48),xmm3);
4565 vextractf128h(Address(rsp, 64),xmm4);
4566 vextractf128h(Address(rsp, 80),xmm5);
4567 vextractf128h(Address(rsp, 96),xmm6);
4568 vextractf128h(Address(rsp,112),xmm7);
4569 #ifdef _LP64
4570 vextractf128h(Address(rsp,128),xmm8);
4571 vextractf128h(Address(rsp,144),xmm9);
4572 vextractf128h(Address(rsp,160),xmm10);
4573 vextractf128h(Address(rsp,176),xmm11);
4574 vextractf128h(Address(rsp,192),xmm12);
4575 vextractf128h(Address(rsp,208),xmm13);
4576 vextractf128h(Address(rsp,224),xmm14);
4577 vextractf128h(Address(rsp,240),xmm15);
4578 #endif
4579 }
4580 #endif
4581 // Save whole 128bit (16 bytes) XMM regiters
4582 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4583 movdqu(Address(rsp,off++*16),xmm0);
4584 movdqu(Address(rsp,off++*16),xmm1);
4585 movdqu(Address(rsp,off++*16),xmm2);
4586 movdqu(Address(rsp,off++*16),xmm3);
4587 movdqu(Address(rsp,off++*16),xmm4);
4588 movdqu(Address(rsp,off++*16),xmm5);
4589 movdqu(Address(rsp,off++*16),xmm6);
4590 movdqu(Address(rsp,off++*16),xmm7);
4591 #ifdef _LP64
4592 movdqu(Address(rsp,off++*16),xmm8);
4593 movdqu(Address(rsp,off++*16),xmm9);
4594 movdqu(Address(rsp,off++*16),xmm10);
4595 movdqu(Address(rsp,off++*16),xmm11);
4596 movdqu(Address(rsp,off++*16),xmm12);
4597 movdqu(Address(rsp,off++*16),xmm13);
4598 movdqu(Address(rsp,off++*16),xmm14);
4599 movdqu(Address(rsp,off++*16),xmm15);
4600 #endif
4601 }
4602
4603 // Preserve registers across runtime call
4604 int incoming_argument_and_return_value_offset = -1;
4605 if (num_fpu_regs_in_use > 1) {
4606 // Must preserve all other FPU regs (could alternatively convert
4607 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
4608 // FPU state, but can not trust C compiler)
4609 NEEDS_CLEANUP;
4610 // NOTE that in this case we also push the incoming argument(s) to
4611 // the stack and restore it later; we also use this stack slot to
4612 // hold the return value from dsin, dcos etc.
4613 for (int i = 0; i < num_fpu_regs_in_use; i++) {
4614 subptr(rsp, sizeof(jdouble));
4615 fstp_d(Address(rsp, 0));
4616 }
4617 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
4618 for (int i = nb_args-1; i >= 0; i--) {
4619 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
4620 }
4621 }
4622
4623 subptr(rsp, nb_args*sizeof(jdouble));
4624 for (int i = 0; i < nb_args; i++) {
4625 fstp_d(Address(rsp, i*sizeof(jdouble)));
4626 }
4627
4628 #ifdef _LP64
4629 if (nb_args > 0) {
4630 movdbl(xmm0, Address(rsp, 0));
4631 }
4632 if (nb_args > 1) {
4633 movdbl(xmm1, Address(rsp, sizeof(jdouble)));
4634 }
4635 assert(nb_args <= 2, "unsupported number of args");
4636 #endif // _LP64
4637
4638 // NOTE: we must not use call_VM_leaf here because that requires a
4639 // complete interpreter frame in debug mode -- same bug as 4387334
4640 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
4641 // do proper 64bit abi
4642
4643 NEEDS_CLEANUP;
4644 // Need to add stack banging before this runtime call if it needs to
4645 // be taken; however, there is no generic stack banging routine at
4646 // the MacroAssembler level
4647
4648 MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
4649
4650 #ifdef _LP64
4651 movsd(Address(rsp, 0), xmm0);
4652 fld_d(Address(rsp, 0));
4653 #endif // _LP64
4654 addptr(rsp, sizeof(jdouble) * nb_args);
4655 if (num_fpu_regs_in_use > 1) {
4656 // Must save return value to stack and then restore entire FPU
4657 // stack except incoming arguments
4658 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
4659 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
4660 fld_d(Address(rsp, 0));
4661 addptr(rsp, sizeof(jdouble));
4662 }
4663 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
4664 addptr(rsp, sizeof(jdouble) * nb_args);
4665 }
4666
4667 off = 0;
4668 if (UseSSE == 1) {
4669 movflt(xmm0, Address(rsp,off++*sizeof(jdouble)));
4670 movflt(xmm1, Address(rsp,off++*sizeof(jdouble)));
4671 movflt(xmm2, Address(rsp,off++*sizeof(jdouble)));
4672 movflt(xmm3, Address(rsp,off++*sizeof(jdouble)));
4673 movflt(xmm4, Address(rsp,off++*sizeof(jdouble)));
4674 movflt(xmm5, Address(rsp,off++*sizeof(jdouble)));
4675 movflt(xmm6, Address(rsp,off++*sizeof(jdouble)));
4676 movflt(xmm7, Address(rsp,off++*sizeof(jdouble)));
4677 addptr(rsp, sizeof(jdouble)*8);
4678 } else if (UseSSE >= 2) {
4679 // Restore whole 128bit (16 bytes) XMM regiters
4680 movdqu(xmm0, Address(rsp,off++*16));
4681 movdqu(xmm1, Address(rsp,off++*16));
4682 movdqu(xmm2, Address(rsp,off++*16));
4683 movdqu(xmm3, Address(rsp,off++*16));
4684 movdqu(xmm4, Address(rsp,off++*16));
4685 movdqu(xmm5, Address(rsp,off++*16));
4686 movdqu(xmm6, Address(rsp,off++*16));
4687 movdqu(xmm7, Address(rsp,off++*16));
4688 #ifdef _LP64
4689 movdqu(xmm8, Address(rsp,off++*16));
4690 movdqu(xmm9, Address(rsp,off++*16));
4691 movdqu(xmm10, Address(rsp,off++*16));
4692 movdqu(xmm11, Address(rsp,off++*16));
4693 movdqu(xmm12, Address(rsp,off++*16));
4694 movdqu(xmm13, Address(rsp,off++*16));
4695 movdqu(xmm14, Address(rsp,off++*16));
4696 movdqu(xmm15, Address(rsp,off++*16));
4697 #endif
4698 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4699 #ifdef COMPILER2
4700 if (MaxVectorSize > 16) {
4701 // Restore upper half of YMM registes.
4702 vinsertf128h(xmm0, Address(rsp, 0));
4703 vinsertf128h(xmm1, Address(rsp, 16));
4704 vinsertf128h(xmm2, Address(rsp, 32));
4705 vinsertf128h(xmm3, Address(rsp, 48));
4706 vinsertf128h(xmm4, Address(rsp, 64));
4707 vinsertf128h(xmm5, Address(rsp, 80));
4708 vinsertf128h(xmm6, Address(rsp, 96));
4709 vinsertf128h(xmm7, Address(rsp,112));
4710 #ifdef _LP64
4711 vinsertf128h(xmm8, Address(rsp,128));
4712 vinsertf128h(xmm9, Address(rsp,144));
4713 vinsertf128h(xmm10, Address(rsp,160));
4714 vinsertf128h(xmm11, Address(rsp,176));
4715 vinsertf128h(xmm12, Address(rsp,192));
4716 vinsertf128h(xmm13, Address(rsp,208));
4717 vinsertf128h(xmm14, Address(rsp,224));
4718 vinsertf128h(xmm15, Address(rsp,240));
4719 #endif
4720 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4721 }
4722 #endif
4723 }
4724 popa();
4725 }
4726
4727 static const double pi_4 = 0.7853981633974483;
4728
4729 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
4730 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
4731 // was attempted in this code; unfortunately it appears that the
4732 // switch to 80-bit precision and back causes this to be
4733 // unprofitable compared with simply performing a runtime call if
4734 // the argument is out of the (-pi/4, pi/4) range.
4735
4736 Register tmp = noreg;
4737 if (!VM_Version::supports_cmov()) {
4738 // fcmp needs a temporary so preserve rbx,
4739 tmp = rbx;
4740 push(tmp);
4741 }
4742
4743 Label slow_case, done;
4744
4745 ExternalAddress pi4_adr = (address)&pi_4;
4746 if (reachable(pi4_adr)) {
4747 // x ?<= pi/4
4748 fld_d(pi4_adr);
4749 fld_s(1); // Stack: X PI/4 X
4750 fabs(); // Stack: |X| PI/4 X
4751 fcmp(tmp);
4752 jcc(Assembler::above, slow_case);
4753
4754 // fastest case: -pi/4 <= x <= pi/4
4755 switch(trig) {
4756 case 's':
4757 fsin();
4758 break;
4759 case 'c':
4760 fcos();
4761 break;
4762 case 't':
4763 ftan();
4764 break;
4765 default:
4766 assert(false, "bad intrinsic");
4767 break;
4768 }
4769 jmp(done);
4770 }
4771
4772 // slow case: runtime call
4773 bind(slow_case);
4774
4775 switch(trig) {
4776 case 's':
4777 {
4778 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
4779 }
4780 break;
4781 case 'c':
4782 {
4783 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
4784 }
4785 break;
4786 case 't':
4787 {
4788 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
4789 }
4790 break;
4791 default:
4792 assert(false, "bad intrinsic");
4793 break;
4794 }
4795
4796 // Come here with result in F-TOS
4797 bind(done);
4798
4799 if (tmp != noreg) {
4800 pop(tmp);
4801 }
4802 }
4803
4804
4805 // Look up the method for a megamorphic invokeinterface call.
4806 // The target method is determined by <intf_klass, itable_index>.
4807 // The receiver klass is in recv_klass.
4808 // On success, the result will be in method_result, and execution falls through.
4809 // On failure, execution transfers to the given label.
4810 void MacroAssembler::lookup_interface_method(Register recv_klass,
4811 Register intf_klass,
4812 RegisterOrConstant itable_index,
4813 Register method_result,
4814 Register scan_temp,
4815 Label& L_no_such_interface) {
4816 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
4817 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4818 "caller must use same register for non-constant itable index as for method");
4819
4820 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4821 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
4822 int itentry_off = itableMethodEntry::method_offset_in_bytes();
4823 int scan_step = itableOffsetEntry::size() * wordSize;
4824 int vte_size = vtableEntry::size() * wordSize;
4825 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4826 assert(vte_size == wordSize, "else adjust times_vte_scale");
4827
4828 movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
4829
4830 // %%% Could store the aligned, prescaled offset in the klassoop.
4831 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4832 if (HeapWordsPerLong > 1) {
4833 // Round up to align_object_offset boundary
4834 // see code for InstanceKlass::start_of_itable!
4835 round_to(scan_temp, BytesPerLong);
4836 }
4837
4838 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4839 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4840 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4841
4842 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4843 // if (scan->interface() == intf) {
4844 // result = (klass + scan->offset() + itable_index);
4845 // }
4846 // }
4847 Label search, found_method;
4848
4849 for (int peel = 1; peel >= 0; peel--) {
4850 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4851 cmpptr(intf_klass, method_result);
4852
4853 if (peel) {
4854 jccb(Assembler::equal, found_method);
4855 } else {
4856 jccb(Assembler::notEqual, search);
4857 // (invert the test to fall through to found_method...)
4858 }
4859
4860 if (!peel) break;
4861
4862 bind(search);
4863
4864 // Check that the previous entry is non-null. A null entry means that
4865 // the receiver class doesn't implement the interface, and wasn't the
4866 // same as when the caller was compiled.
4867 testptr(method_result, method_result);
4868 jcc(Assembler::zero, L_no_such_interface);
4869 addptr(scan_temp, scan_step);
4870 }
4871
4872 bind(found_method);
4873
4874 // Got a hit.
4875 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4876 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4877 }
4878
4879
4880 // virtual method calling
4881 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4882 RegisterOrConstant vtable_index,
4883 Register method_result) {
4884 const int base = InstanceKlass::vtable_start_offset() * wordSize;
4885 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4886 Address vtable_entry_addr(recv_klass,
4887 vtable_index, Address::times_ptr,
4888 base + vtableEntry::method_offset_in_bytes());
4889 movptr(method_result, vtable_entry_addr);
4890 }
4891
4892
4893 void MacroAssembler::check_klass_subtype(Register sub_klass,
4894 Register super_klass,
4895 Register temp_reg,
4896 Label& L_success) {
4897 Label L_failure;
4898 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
4899 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4900 bind(L_failure);
4901 }
4902
4903
4904 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4905 Register super_klass,
4906 Register temp_reg,
4907 Label* L_success,
4908 Label* L_failure,
4909 Label* L_slow_path,
4910 RegisterOrConstant super_check_offset) {
4911 assert_different_registers(sub_klass, super_klass, temp_reg);
4912 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4913 if (super_check_offset.is_register()) {
4914 assert_different_registers(sub_klass, super_klass,
4915 super_check_offset.as_register());
4916 } else if (must_load_sco) {
4917 assert(temp_reg != noreg, "supply either a temp or a register offset");
4918 }
4919
4920 Label L_fallthrough;
4921 int label_nulls = 0;
4922 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4923 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4924 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4925 assert(label_nulls <= 1, "at most one NULL in the batch");
4926
4927 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4928 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4929 Address super_check_offset_addr(super_klass, sco_offset);
4930
4931 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4932 // range of a jccb. If this routine grows larger, reconsider at
4933 // least some of these.
4934 #define local_jcc(assembler_cond, label) \
4935 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4936 else jcc( assembler_cond, label) /*omit semi*/
4937
4938 // Hacked jmp, which may only be used just before L_fallthrough.
4939 #define final_jmp(label) \
4940 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4941 else jmp(label) /*omit semi*/
4942
4943 // If the pointers are equal, we are done (e.g., String[] elements).
4944 // This self-check enables sharing of secondary supertype arrays among
4945 // non-primary types such as array-of-interface. Otherwise, each such
4946 // type would need its own customized SSA.
4947 // We move this check to the front of the fast path because many
4948 // type checks are in fact trivially successful in this manner,
4949 // so we get a nicely predicted branch right at the start of the check.
4950 cmpptr(sub_klass, super_klass);
4951 local_jcc(Assembler::equal, *L_success);
4952
4953 // Check the supertype display:
4954 if (must_load_sco) {
4955 // Positive movl does right thing on LP64.
4956 movl(temp_reg, super_check_offset_addr);
4957 super_check_offset = RegisterOrConstant(temp_reg);
4958 }
4959 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4960 cmpptr(super_klass, super_check_addr); // load displayed supertype
4961
4962 // This check has worked decisively for primary supers.
4963 // Secondary supers are sought in the super_cache ('super_cache_addr').
4964 // (Secondary supers are interfaces and very deeply nested subtypes.)
4965 // This works in the same check above because of a tricky aliasing
4966 // between the super_cache and the primary super display elements.
4967 // (The 'super_check_addr' can address either, as the case requires.)
4968 // Note that the cache is updated below if it does not help us find
4969 // what we need immediately.
4970 // So if it was a primary super, we can just fail immediately.
4971 // Otherwise, it's the slow path for us (no success at this point).
4972
4973 if (super_check_offset.is_register()) {
4974 local_jcc(Assembler::equal, *L_success);
4975 cmpl(super_check_offset.as_register(), sc_offset);
4976 if (L_failure == &L_fallthrough) {
4977 local_jcc(Assembler::equal, *L_slow_path);
4978 } else {
4979 local_jcc(Assembler::notEqual, *L_failure);
4980 final_jmp(*L_slow_path);
4981 }
4982 } else if (super_check_offset.as_constant() == sc_offset) {
4983 // Need a slow path; fast failure is impossible.
4984 if (L_slow_path == &L_fallthrough) {
4985 local_jcc(Assembler::equal, *L_success);
4986 } else {
4987 local_jcc(Assembler::notEqual, *L_slow_path);
4988 final_jmp(*L_success);
4989 }
4990 } else {
4991 // No slow path; it's a fast decision.
4992 if (L_failure == &L_fallthrough) {
4993 local_jcc(Assembler::equal, *L_success);
4994 } else {
4995 local_jcc(Assembler::notEqual, *L_failure);
4996 final_jmp(*L_success);
4997 }
4998 }
4999
5000 bind(L_fallthrough);
5001
5002 #undef local_jcc
5003 #undef final_jmp
5004 }
5005
5006
5007 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5008 Register super_klass,
5009 Register temp_reg,
5010 Register temp2_reg,
5011 Label* L_success,
5012 Label* L_failure,
5013 bool set_cond_codes) {
5014 assert_different_registers(sub_klass, super_klass, temp_reg);
5015 if (temp2_reg != noreg)
5016 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5017 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5018
5019 Label L_fallthrough;
5020 int label_nulls = 0;
5021 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5022 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5023 assert(label_nulls <= 1, "at most one NULL in the batch");
5024
5025 // a couple of useful fields in sub_klass:
5026 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5027 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5028 Address secondary_supers_addr(sub_klass, ss_offset);
5029 Address super_cache_addr( sub_klass, sc_offset);
5030
5031 // Do a linear scan of the secondary super-klass chain.
5032 // This code is rarely used, so simplicity is a virtue here.
5033 // The repne_scan instruction uses fixed registers, which we must spill.
5034 // Don't worry too much about pre-existing connections with the input regs.
5035
5036 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5037 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5038
5039 // Get super_klass value into rax (even if it was in rdi or rcx).
5040 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5041 if (super_klass != rax || UseCompressedOops) {
5042 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5043 mov(rax, super_klass);
5044 }
5045 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5046 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5047
5048 #ifndef PRODUCT
5049 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5050 ExternalAddress pst_counter_addr((address) pst_counter);
5051 NOT_LP64( incrementl(pst_counter_addr) );
5052 LP64_ONLY( lea(rcx, pst_counter_addr) );
5053 LP64_ONLY( incrementl(Address(rcx, 0)) );
5054 #endif //PRODUCT
5055
5056 // We will consult the secondary-super array.
5057 movptr(rdi, secondary_supers_addr);
5058 // Load the array length. (Positive movl does right thing on LP64.)
5059 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5060 // Skip to start of data.
5061 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5062
5063 // Scan RCX words at [RDI] for an occurrence of RAX.
5064 // Set NZ/Z based on last compare.
5065 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5066 // not change flags (only scas instruction which is repeated sets flags).
5067 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5068
5069 testptr(rax,rax); // Set Z = 0
5070 repne_scan();
5071
5072 // Unspill the temp. registers:
5073 if (pushed_rdi) pop(rdi);
5074 if (pushed_rcx) pop(rcx);
5075 if (pushed_rax) pop(rax);
5076
5077 if (set_cond_codes) {
5078 // Special hack for the AD files: rdi is guaranteed non-zero.
5079 assert(!pushed_rdi, "rdi must be left non-NULL");
5080 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5081 }
5082
5083 if (L_failure == &L_fallthrough)
5084 jccb(Assembler::notEqual, *L_failure);
5085 else jcc(Assembler::notEqual, *L_failure);
5086
5087 // Success. Cache the super we found and proceed in triumph.
5088 movptr(super_cache_addr, super_klass);
5089
5090 if (L_success != &L_fallthrough) {
5091 jmp(*L_success);
5092 }
5093
5094 #undef IS_A_TEMP
5095
5096 bind(L_fallthrough);
5097 }
5098
5099
5100 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5101 if (VM_Version::supports_cmov()) {
5102 cmovl(cc, dst, src);
5103 } else {
5104 Label L;
5105 jccb(negate_condition(cc), L);
5106 movl(dst, src);
5107 bind(L);
5108 }
5109 }
5110
5111 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5112 if (VM_Version::supports_cmov()) {
5113 cmovl(cc, dst, src);
5114 } else {
5115 Label L;
5116 jccb(negate_condition(cc), L);
5117 movl(dst, src);
5118 bind(L);
5119 }
5120 }
5121
5122 void MacroAssembler::verify_oop(Register reg, const char* s) {
5123 if (!VerifyOops) return;
5124
5125 // Pass register number to verify_oop_subroutine
5126 const char* b = NULL;
5127 {
5128 ResourceMark rm;
5129 stringStream ss;
5130 ss.print("verify_oop: %s: %s", reg->name(), s);
5131 b = code_string(ss.as_string());
5132 }
5133 BLOCK_COMMENT("verify_oop {");
5134 #ifdef _LP64
5135 push(rscratch1); // save r10, trashed by movptr()
5136 #endif
5137 push(rax); // save rax,
5138 push(reg); // pass register argument
5139 ExternalAddress buffer((address) b);
5140 // avoid using pushptr, as it modifies scratch registers
5141 // and our contract is not to modify anything
5142 movptr(rax, buffer.addr());
5143 push(rax);
5144 // call indirectly to solve generation ordering problem
5145 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5146 call(rax);
5147 // Caller pops the arguments (oop, message) and restores rax, r10
5148 BLOCK_COMMENT("} verify_oop");
5149 }
5150
5151
5152 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
5153 Register tmp,
5154 int offset) {
5155 intptr_t value = *delayed_value_addr;
5156 if (value != 0)
5157 return RegisterOrConstant(value + offset);
5158
5159 // load indirectly to solve generation ordering problem
5160 movptr(tmp, ExternalAddress((address) delayed_value_addr));
5161
5162 #ifdef ASSERT
5163 { Label L;
5164 testptr(tmp, tmp);
5165 if (WizardMode) {
5166 const char* buf = NULL;
5167 {
5168 ResourceMark rm;
5169 stringStream ss;
5170 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
5171 buf = code_string(ss.as_string());
5172 }
5173 jcc(Assembler::notZero, L);
5174 STOP(buf);
5175 } else {
5176 jccb(Assembler::notZero, L);
5177 hlt();
5178 }
5179 bind(L);
5180 }
5181 #endif
5182
5183 if (offset != 0)
5184 addptr(tmp, offset);
5185
5186 return RegisterOrConstant(tmp);
5187 }
5188
5189
5190 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5191 int extra_slot_offset) {
5192 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5193 int stackElementSize = Interpreter::stackElementSize;
5194 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5195 #ifdef ASSERT
5196 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5197 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5198 #endif
5199 Register scale_reg = noreg;
5200 Address::ScaleFactor scale_factor = Address::no_scale;
5201 if (arg_slot.is_constant()) {
5202 offset += arg_slot.as_constant() * stackElementSize;
5203 } else {
5204 scale_reg = arg_slot.as_register();
5205 scale_factor = Address::times(stackElementSize);
5206 }
5207 offset += wordSize; // return PC is on stack
5208 return Address(rsp, scale_reg, scale_factor, offset);
5209 }
5210
5211
5212 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
5213 if (!VerifyOops) return;
5214
5215 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
5216 // Pass register number to verify_oop_subroutine
5217 const char* b = NULL;
5218 {
5219 ResourceMark rm;
5220 stringStream ss;
5221 ss.print("verify_oop_addr: %s", s);
5222 b = code_string(ss.as_string());
5223 }
5224 #ifdef _LP64
5225 push(rscratch1); // save r10, trashed by movptr()
5226 #endif
5227 push(rax); // save rax,
5228 // addr may contain rsp so we will have to adjust it based on the push
5229 // we just did (and on 64 bit we do two pushes)
5230 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5231 // stores rax into addr which is backwards of what was intended.
5232 if (addr.uses(rsp)) {
5233 lea(rax, addr);
5234 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5235 } else {
5236 pushptr(addr);
5237 }
5238
5239 ExternalAddress buffer((address) b);
5240 // pass msg argument
5241 // avoid using pushptr, as it modifies scratch registers
5242 // and our contract is not to modify anything
5243 movptr(rax, buffer.addr());
5244 push(rax);
5245
5246 // call indirectly to solve generation ordering problem
5247 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5248 call(rax);
5249 // Caller pops the arguments (addr, message) and restores rax, r10.
5250 }
5251
5252 void MacroAssembler::verify_tlab() {
5253 #ifdef ASSERT
5254 if (UseTLAB && VerifyOops) {
5255 Label next, ok;
5256 Register t1 = rsi;
5257 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5258
5259 push(t1);
5260 NOT_LP64(push(thread_reg));
5261 NOT_LP64(get_thread(thread_reg));
5262
5263 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5264 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5265 jcc(Assembler::aboveEqual, next);
5266 STOP("assert(top >= start)");
5267 should_not_reach_here();
5268
5269 bind(next);
5270 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5271 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5272 jcc(Assembler::aboveEqual, ok);
5273 STOP("assert(top <= end)");
5274 should_not_reach_here();
5275
5276 bind(ok);
5277 NOT_LP64(pop(thread_reg));
5278 pop(t1);
5279 }
5280 #endif
5281 }
5282
5283 class ControlWord {
5284 public:
5285 int32_t _value;
5286
5287 int rounding_control() const { return (_value >> 10) & 3 ; }
5288 int precision_control() const { return (_value >> 8) & 3 ; }
5289 bool precision() const { return ((_value >> 5) & 1) != 0; }
5290 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5291 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5292 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5293 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5294 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5295
5296 void print() const {
5297 // rounding control
5298 const char* rc;
5299 switch (rounding_control()) {
5300 case 0: rc = "round near"; break;
5301 case 1: rc = "round down"; break;
5302 case 2: rc = "round up "; break;
5303 case 3: rc = "chop "; break;
5304 };
5305 // precision control
5306 const char* pc;
5307 switch (precision_control()) {
5308 case 0: pc = "24 bits "; break;
5309 case 1: pc = "reserved"; break;
5310 case 2: pc = "53 bits "; break;
5311 case 3: pc = "64 bits "; break;
5312 };
5313 // flags
5314 char f[9];
5315 f[0] = ' ';
5316 f[1] = ' ';
5317 f[2] = (precision ()) ? 'P' : 'p';
5318 f[3] = (underflow ()) ? 'U' : 'u';
5319 f[4] = (overflow ()) ? 'O' : 'o';
5320 f[5] = (zero_divide ()) ? 'Z' : 'z';
5321 f[6] = (denormalized()) ? 'D' : 'd';
5322 f[7] = (invalid ()) ? 'I' : 'i';
5323 f[8] = '\x0';
5324 // output
5325 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5326 }
5327
5328 };
5329
5330 class StatusWord {
5331 public:
5332 int32_t _value;
5333
5334 bool busy() const { return ((_value >> 15) & 1) != 0; }
5335 bool C3() const { return ((_value >> 14) & 1) != 0; }
5336 bool C2() const { return ((_value >> 10) & 1) != 0; }
5337 bool C1() const { return ((_value >> 9) & 1) != 0; }
5338 bool C0() const { return ((_value >> 8) & 1) != 0; }
5339 int top() const { return (_value >> 11) & 7 ; }
5340 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5341 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5342 bool precision() const { return ((_value >> 5) & 1) != 0; }
5343 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5344 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5345 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5346 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5347 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5348
5349 void print() const {
5350 // condition codes
5351 char c[5];
5352 c[0] = (C3()) ? '3' : '-';
5353 c[1] = (C2()) ? '2' : '-';
5354 c[2] = (C1()) ? '1' : '-';
5355 c[3] = (C0()) ? '0' : '-';
5356 c[4] = '\x0';
5357 // flags
5358 char f[9];
5359 f[0] = (error_status()) ? 'E' : '-';
5360 f[1] = (stack_fault ()) ? 'S' : '-';
5361 f[2] = (precision ()) ? 'P' : '-';
5362 f[3] = (underflow ()) ? 'U' : '-';
5363 f[4] = (overflow ()) ? 'O' : '-';
5364 f[5] = (zero_divide ()) ? 'Z' : '-';
5365 f[6] = (denormalized()) ? 'D' : '-';
5366 f[7] = (invalid ()) ? 'I' : '-';
5367 f[8] = '\x0';
5368 // output
5369 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5370 }
5371
5372 };
5373
5374 class TagWord {
5375 public:
5376 int32_t _value;
5377
5378 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5379
5380 void print() const {
5381 printf("%04x", _value & 0xFFFF);
5382 }
5383
5384 };
5385
5386 class FPU_Register {
5387 public:
5388 int32_t _m0;
5389 int32_t _m1;
5390 int16_t _ex;
5391
5392 bool is_indefinite() const {
5393 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5394 }
5395
5396 void print() const {
5397 char sign = (_ex < 0) ? '-' : '+';
5398 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5399 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5400 };
5401
5402 };
5403
5404 class FPU_State {
5405 public:
5406 enum {
5407 register_size = 10,
5408 number_of_registers = 8,
5409 register_mask = 7
5410 };
5411
5412 ControlWord _control_word;
5413 StatusWord _status_word;
5414 TagWord _tag_word;
5415 int32_t _error_offset;
5416 int32_t _error_selector;
5417 int32_t _data_offset;
5418 int32_t _data_selector;
5419 int8_t _register[register_size * number_of_registers];
5420
5421 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5422 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5423
5424 const char* tag_as_string(int tag) const {
5425 switch (tag) {
5426 case 0: return "valid";
5427 case 1: return "zero";
5428 case 2: return "special";
5429 case 3: return "empty";
5430 }
5431 ShouldNotReachHere();
5432 return NULL;
5433 }
5434
5435 void print() const {
5436 // print computation registers
5437 { int t = _status_word.top();
5438 for (int i = 0; i < number_of_registers; i++) {
5439 int j = (i - t) & register_mask;
5440 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5441 st(j)->print();
5442 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5443 }
5444 }
5445 printf("\n");
5446 // print control registers
5447 printf("ctrl = "); _control_word.print(); printf("\n");
5448 printf("stat = "); _status_word .print(); printf("\n");
5449 printf("tags = "); _tag_word .print(); printf("\n");
5450 }
5451
5452 };
5453
5454 class Flag_Register {
5455 public:
5456 int32_t _value;
5457
5458 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5459 bool direction() const { return ((_value >> 10) & 1) != 0; }
5460 bool sign() const { return ((_value >> 7) & 1) != 0; }
5461 bool zero() const { return ((_value >> 6) & 1) != 0; }
5462 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5463 bool parity() const { return ((_value >> 2) & 1) != 0; }
5464 bool carry() const { return ((_value >> 0) & 1) != 0; }
5465
5466 void print() const {
5467 // flags
5468 char f[8];
5469 f[0] = (overflow ()) ? 'O' : '-';
5470 f[1] = (direction ()) ? 'D' : '-';
5471 f[2] = (sign ()) ? 'S' : '-';
5472 f[3] = (zero ()) ? 'Z' : '-';
5473 f[4] = (auxiliary_carry()) ? 'A' : '-';
5474 f[5] = (parity ()) ? 'P' : '-';
5475 f[6] = (carry ()) ? 'C' : '-';
5476 f[7] = '\x0';
5477 // output
5478 printf("%08x flags = %s", _value, f);
5479 }
5480
5481 };
5482
5483 class IU_Register {
5484 public:
5485 int32_t _value;
5486
5487 void print() const {
5488 printf("%08x %11d", _value, _value);
5489 }
5490
5491 };
5492
5493 class IU_State {
5494 public:
5495 Flag_Register _eflags;
5496 IU_Register _rdi;
5497 IU_Register _rsi;
5498 IU_Register _rbp;
5499 IU_Register _rsp;
5500 IU_Register _rbx;
5501 IU_Register _rdx;
5502 IU_Register _rcx;
5503 IU_Register _rax;
5504
5505 void print() const {
5506 // computation registers
5507 printf("rax, = "); _rax.print(); printf("\n");
5508 printf("rbx, = "); _rbx.print(); printf("\n");
5509 printf("rcx = "); _rcx.print(); printf("\n");
5510 printf("rdx = "); _rdx.print(); printf("\n");
5511 printf("rdi = "); _rdi.print(); printf("\n");
5512 printf("rsi = "); _rsi.print(); printf("\n");
5513 printf("rbp, = "); _rbp.print(); printf("\n");
5514 printf("rsp = "); _rsp.print(); printf("\n");
5515 printf("\n");
5516 // control registers
5517 printf("flgs = "); _eflags.print(); printf("\n");
5518 }
5519 };
5520
5521
5522 class CPU_State {
5523 public:
5524 FPU_State _fpu_state;
5525 IU_State _iu_state;
5526
5527 void print() const {
5528 printf("--------------------------------------------------\n");
5529 _iu_state .print();
5530 printf("\n");
5531 _fpu_state.print();
5532 printf("--------------------------------------------------\n");
5533 }
5534
5535 };
5536
5537
5538 static void _print_CPU_state(CPU_State* state) {
5539 state->print();
5540 };
5541
5542
5543 void MacroAssembler::print_CPU_state() {
5544 push_CPU_state();
5545 push(rsp); // pass CPU state
5546 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5547 addptr(rsp, wordSize); // discard argument
5548 pop_CPU_state();
5549 }
5550
5551
5552 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5553 static int counter = 0;
5554 FPU_State* fs = &state->_fpu_state;
5555 counter++;
5556 // For leaf calls, only verify that the top few elements remain empty.
5557 // We only need 1 empty at the top for C2 code.
5558 if( stack_depth < 0 ) {
5559 if( fs->tag_for_st(7) != 3 ) {
5560 printf("FPR7 not empty\n");
5561 state->print();
5562 assert(false, "error");
5563 return false;
5564 }
5565 return true; // All other stack states do not matter
5566 }
5567
5568 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5569 "bad FPU control word");
5570
5571 // compute stack depth
5572 int i = 0;
5573 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5574 int d = i;
5575 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5576 // verify findings
5577 if (i != FPU_State::number_of_registers) {
5578 // stack not contiguous
5579 printf("%s: stack not contiguous at ST%d\n", s, i);
5580 state->print();
5581 assert(false, "error");
5582 return false;
5583 }
5584 // check if computed stack depth corresponds to expected stack depth
5585 if (stack_depth < 0) {
5586 // expected stack depth is -stack_depth or less
5587 if (d > -stack_depth) {
5588 // too many elements on the stack
5589 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5590 state->print();
5591 assert(false, "error");
5592 return false;
5593 }
5594 } else {
5595 // expected stack depth is stack_depth
5596 if (d != stack_depth) {
5597 // wrong stack depth
5598 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5599 state->print();
5600 assert(false, "error");
5601 return false;
5602 }
5603 }
5604 // everything is cool
5605 return true;
5606 }
5607
5608
5609 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5610 if (!VerifyFPU) return;
5611 push_CPU_state();
5612 push(rsp); // pass CPU state
5613 ExternalAddress msg((address) s);
5614 // pass message string s
5615 pushptr(msg.addr());
5616 push(stack_depth); // pass stack depth
5617 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5618 addptr(rsp, 3 * wordSize); // discard arguments
5619 // check for error
5620 { Label L;
5621 testl(rax, rax);
5622 jcc(Assembler::notZero, L);
5623 int3(); // break if error condition
5624 bind(L);
5625 }
5626 pop_CPU_state();
5627 }
5628
5629 void MacroAssembler::restore_cpu_control_state_after_jni() {
5630 // Either restore the MXCSR register after returning from the JNI Call
5631 // or verify that it wasn't changed (with -Xcheck:jni flag).
5632 if (VM_Version::supports_sse()) {
5633 if (RestoreMXCSROnJNICalls) {
5634 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5635 } else if (CheckJNICalls) {
5636 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5637 }
5638 }
5639 if (VM_Version::supports_avx()) {
5640 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5641 vzeroupper();
5642 }
5643
5644 #ifndef _LP64
5645 // Either restore the x87 floating pointer control word after returning
5646 // from the JNI call or verify that it wasn't changed.
5647 if (CheckJNICalls) {
5648 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5649 }
5650 #endif // _LP64
5651 }
5652
5653
5654 void MacroAssembler::load_klass(Register dst, Register src) {
5655 #ifdef _LP64
5656 if (UseCompressedClassPointers) {
5657 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5658 decode_klass_not_null(dst);
5659 } else
5660 #endif
5661 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5662 }
5663
5664 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5665 load_klass(dst, src);
5666 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5667 }
5668
5669 void MacroAssembler::store_klass(Register dst, Register src) {
5670 #ifdef _LP64
5671 if (UseCompressedClassPointers) {
5672 encode_klass_not_null(src);
5673 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5674 } else
5675 #endif
5676 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5677 }
5678
5679 void MacroAssembler::load_heap_oop(Register dst, Address src) {
5680 #ifdef _LP64
5681 // FIXME: Must change all places where we try to load the klass.
5682 if (UseCompressedOops) {
5683 movl(dst, src);
5684 decode_heap_oop(dst);
5685 } else
5686 #endif
5687 movptr(dst, src);
5688 }
5689
5690 // Doesn't do verfication, generates fixed size code
5691 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
5692 #ifdef _LP64
5693 if (UseCompressedOops) {
5694 movl(dst, src);
5695 decode_heap_oop_not_null(dst);
5696 } else
5697 #endif
5698 movptr(dst, src);
5699 }
5700
5701 void MacroAssembler::store_heap_oop(Address dst, Register src) {
5702 #ifdef _LP64
5703 if (UseCompressedOops) {
5704 assert(!dst.uses(src), "not enough registers");
5705 encode_heap_oop(src);
5706 movl(dst, src);
5707 } else
5708 #endif
5709 movptr(dst, src);
5710 }
5711
5712 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
5713 assert_different_registers(src1, tmp);
5714 #ifdef _LP64
5715 if (UseCompressedOops) {
5716 bool did_push = false;
5717 if (tmp == noreg) {
5718 tmp = rax;
5719 push(tmp);
5720 did_push = true;
5721 assert(!src2.uses(rsp), "can't push");
5722 }
5723 load_heap_oop(tmp, src2);
5724 cmpptr(src1, tmp);
5725 if (did_push) pop(tmp);
5726 } else
5727 #endif
5728 cmpptr(src1, src2);
5729 }
5730
5731 // Used for storing NULLs.
5732 void MacroAssembler::store_heap_oop_null(Address dst) {
5733 #ifdef _LP64
5734 if (UseCompressedOops) {
5735 movl(dst, (int32_t)NULL_WORD);
5736 } else {
5737 movslq(dst, (int32_t)NULL_WORD);
5738 }
5739 #else
5740 movl(dst, (int32_t)NULL_WORD);
5741 #endif
5742 }
5743
5744 #ifdef _LP64
5745 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5746 if (UseCompressedClassPointers) {
5747 // Store to klass gap in destination
5748 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5749 }
5750 }
5751
5752 #ifdef ASSERT
5753 void MacroAssembler::verify_heapbase(const char* msg) {
5754 assert (UseCompressedOops, "should be compressed");
5755 assert (Universe::heap() != NULL, "java heap should be initialized");
5756 if (CheckCompressedOops) {
5757 Label ok;
5758 push(rscratch1); // cmpptr trashes rscratch1
5759 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5760 jcc(Assembler::equal, ok);
5761 STOP(msg);
5762 bind(ok);
5763 pop(rscratch1);
5764 }
5765 }
5766 #endif
5767
5768 // Algorithm must match oop.inline.hpp encode_heap_oop.
5769 void MacroAssembler::encode_heap_oop(Register r) {
5770 #ifdef ASSERT
5771 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5772 #endif
5773 verify_oop(r, "broken oop in encode_heap_oop");
5774 if (Universe::narrow_oop_base() == NULL) {
5775 if (Universe::narrow_oop_shift() != 0) {
5776 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5777 shrq(r, LogMinObjAlignmentInBytes);
5778 }
5779 return;
5780 }
5781 testq(r, r);
5782 cmovq(Assembler::equal, r, r12_heapbase);
5783 subq(r, r12_heapbase);
5784 shrq(r, LogMinObjAlignmentInBytes);
5785 }
5786
5787 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5788 #ifdef ASSERT
5789 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5790 if (CheckCompressedOops) {
5791 Label ok;
5792 testq(r, r);
5793 jcc(Assembler::notEqual, ok);
5794 STOP("null oop passed to encode_heap_oop_not_null");
5795 bind(ok);
5796 }
5797 #endif
5798 verify_oop(r, "broken oop in encode_heap_oop_not_null");
5799 if (Universe::narrow_oop_base() != NULL) {
5800 subq(r, r12_heapbase);
5801 }
5802 if (Universe::narrow_oop_shift() != 0) {
5803 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5804 shrq(r, LogMinObjAlignmentInBytes);
5805 }
5806 }
5807
5808 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5809 #ifdef ASSERT
5810 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5811 if (CheckCompressedOops) {
5812 Label ok;
5813 testq(src, src);
5814 jcc(Assembler::notEqual, ok);
5815 STOP("null oop passed to encode_heap_oop_not_null2");
5816 bind(ok);
5817 }
5818 #endif
5819 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5820 if (dst != src) {
5821 movq(dst, src);
5822 }
5823 if (Universe::narrow_oop_base() != NULL) {
5824 subq(dst, r12_heapbase);
5825 }
5826 if (Universe::narrow_oop_shift() != 0) {
5827 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5828 shrq(dst, LogMinObjAlignmentInBytes);
5829 }
5830 }
5831
5832 void MacroAssembler::decode_heap_oop(Register r) {
5833 #ifdef ASSERT
5834 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5835 #endif
5836 if (Universe::narrow_oop_base() == NULL) {
5837 if (Universe::narrow_oop_shift() != 0) {
5838 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5839 shlq(r, LogMinObjAlignmentInBytes);
5840 }
5841 } else {
5842 Label done;
5843 shlq(r, LogMinObjAlignmentInBytes);
5844 jccb(Assembler::equal, done);
5845 addq(r, r12_heapbase);
5846 bind(done);
5847 }
5848 verify_oop(r, "broken oop in decode_heap_oop");
5849 }
5850
5851 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5852 // Note: it will change flags
5853 assert (UseCompressedOops, "should only be used for compressed headers");
5854 assert (Universe::heap() != NULL, "java heap should be initialized");
5855 // Cannot assert, unverified entry point counts instructions (see .ad file)
5856 // vtableStubs also counts instructions in pd_code_size_limit.
5857 // Also do not verify_oop as this is called by verify_oop.
5858 if (Universe::narrow_oop_shift() != 0) {
5859 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5860 shlq(r, LogMinObjAlignmentInBytes);
5861 if (Universe::narrow_oop_base() != NULL) {
5862 addq(r, r12_heapbase);
5863 }
5864 } else {
5865 assert (Universe::narrow_oop_base() == NULL, "sanity");
5866 }
5867 }
5868
5869 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5870 // Note: it will change flags
5871 assert (UseCompressedOops, "should only be used for compressed headers");
5872 assert (Universe::heap() != NULL, "java heap should be initialized");
5873 // Cannot assert, unverified entry point counts instructions (see .ad file)
5874 // vtableStubs also counts instructions in pd_code_size_limit.
5875 // Also do not verify_oop as this is called by verify_oop.
5876 if (Universe::narrow_oop_shift() != 0) {
5877 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5878 if (LogMinObjAlignmentInBytes == Address::times_8) {
5879 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5880 } else {
5881 if (dst != src) {
5882 movq(dst, src);
5883 }
5884 shlq(dst, LogMinObjAlignmentInBytes);
5885 if (Universe::narrow_oop_base() != NULL) {
5886 addq(dst, r12_heapbase);
5887 }
5888 }
5889 } else {
5890 assert (Universe::narrow_oop_base() == NULL, "sanity");
5891 if (dst != src) {
5892 movq(dst, src);
5893 }
5894 }
5895 }
5896
5897 void MacroAssembler::encode_klass_not_null(Register r) {
5898 if (Universe::narrow_klass_base() != NULL) {
5899 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5900 assert(r != r12_heapbase, "Encoding a klass in r12");
5901 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5902 subq(r, r12_heapbase);
5903 }
5904 if (Universe::narrow_klass_shift() != 0) {
5905 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5906 shrq(r, LogKlassAlignmentInBytes);
5907 }
5908 if (Universe::narrow_klass_base() != NULL) {
5909 reinit_heapbase();
5910 }
5911 }
5912
5913 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5914 if (dst == src) {
5915 encode_klass_not_null(src);
5916 } else {
5917 if (Universe::narrow_klass_base() != NULL) {
5918 mov64(dst, (int64_t)Universe::narrow_klass_base());
5919 negq(dst);
5920 addq(dst, src);
5921 } else {
5922 movptr(dst, src);
5923 }
5924 if (Universe::narrow_klass_shift() != 0) {
5925 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5926 shrq(dst, LogKlassAlignmentInBytes);
5927 }
5928 }
5929 }
5930
5931 // Function instr_size_for_decode_klass_not_null() counts the instructions
5932 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5933 // when (Universe::heap() != NULL). Hence, if the instructions they
5934 // generate change, then this method needs to be updated.
5935 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5936 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5937 if (Universe::narrow_klass_base() != NULL) {
5938 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
5939 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
5940 } else {
5941 // longest load decode klass function, mov64, leaq
5942 return 16;
5943 }
5944 }
5945
5946 // !!! If the instructions that get generated here change then function
5947 // instr_size_for_decode_klass_not_null() needs to get updated.
5948 void MacroAssembler::decode_klass_not_null(Register r) {
5949 // Note: it will change flags
5950 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5951 assert(r != r12_heapbase, "Decoding a klass in r12");
5952 // Cannot assert, unverified entry point counts instructions (see .ad file)
5953 // vtableStubs also counts instructions in pd_code_size_limit.
5954 // Also do not verify_oop as this is called by verify_oop.
5955 if (Universe::narrow_klass_shift() != 0) {
5956 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5957 shlq(r, LogKlassAlignmentInBytes);
5958 }
5959 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5960 if (Universe::narrow_klass_base() != NULL) {
5961 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5962 addq(r, r12_heapbase);
5963 reinit_heapbase();
5964 }
5965 }
5966
5967 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5968 // Note: it will change flags
5969 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5970 if (dst == src) {
5971 decode_klass_not_null(dst);
5972 } else {
5973 // Cannot assert, unverified entry point counts instructions (see .ad file)
5974 // vtableStubs also counts instructions in pd_code_size_limit.
5975 // Also do not verify_oop as this is called by verify_oop.
5976 mov64(dst, (int64_t)Universe::narrow_klass_base());
5977 if (Universe::narrow_klass_shift() != 0) {
5978 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5979 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
5980 leaq(dst, Address(dst, src, Address::times_8, 0));
5981 } else {
5982 addq(dst, src);
5983 }
5984 }
5985 }
5986
5987 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5988 assert (UseCompressedOops, "should only be used for compressed headers");
5989 assert (Universe::heap() != NULL, "java heap should be initialized");
5990 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5991 int oop_index = oop_recorder()->find_index(obj);
5992 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5993 mov_narrow_oop(dst, oop_index, rspec);
5994 }
5995
5996 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5997 assert (UseCompressedOops, "should only be used for compressed headers");
5998 assert (Universe::heap() != NULL, "java heap should be initialized");
5999 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6000 int oop_index = oop_recorder()->find_index(obj);
6001 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6002 mov_narrow_oop(dst, oop_index, rspec);
6003 }
6004
6005 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6006 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6007 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6008 int klass_index = oop_recorder()->find_index(k);
6009 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6010 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6011 }
6012
6013 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6014 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6015 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6016 int klass_index = oop_recorder()->find_index(k);
6017 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6018 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6019 }
6020
6021 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6022 assert (UseCompressedOops, "should only be used for compressed headers");
6023 assert (Universe::heap() != NULL, "java heap should be initialized");
6024 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6025 int oop_index = oop_recorder()->find_index(obj);
6026 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6027 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6028 }
6029
6030 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6031 assert (UseCompressedOops, "should only be used for compressed headers");
6032 assert (Universe::heap() != NULL, "java heap should be initialized");
6033 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6034 int oop_index = oop_recorder()->find_index(obj);
6035 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6036 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6037 }
6038
6039 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6040 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6041 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6042 int klass_index = oop_recorder()->find_index(k);
6043 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6044 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6045 }
6046
6047 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6048 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6049 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6050 int klass_index = oop_recorder()->find_index(k);
6051 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6052 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6053 }
6054
6055 void MacroAssembler::reinit_heapbase() {
6056 if (UseCompressedOops || UseCompressedClassPointers) {
6057 if (Universe::heap() != NULL) {
6058 if (Universe::narrow_oop_base() == NULL) {
6059 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6060 } else {
6061 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6062 }
6063 } else {
6064 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6065 }
6066 }
6067 }
6068
6069 #endif // _LP64
6070
6071
6072 // C2 compiled method's prolog code.
6073 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6074
6075 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6076 // NativeJump::patch_verified_entry will be able to patch out the entry
6077 // code safely. The push to verify stack depth is ok at 5 bytes,
6078 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6079 // stack bang then we must use the 6 byte frame allocation even if
6080 // we have no frame. :-(
6081 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6082
6083 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6084 // Remove word for return addr
6085 framesize -= wordSize;
6086 stack_bang_size -= wordSize;
6087
6088 // Calls to C2R adapters often do not accept exceptional returns.
6089 // We require that their callers must bang for them. But be careful, because
6090 // some VM calls (such as call site linkage) can use several kilobytes of
6091 // stack. But the stack safety zone should account for that.
6092 // See bugs 4446381, 4468289, 4497237.
6093 if (stack_bang_size > 0) {
6094 generate_stack_overflow_check(stack_bang_size);
6095
6096 // We always push rbp, so that on return to interpreter rbp, will be
6097 // restored correctly and we can correct the stack.
6098 push(rbp);
6099 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6100 if (PreserveFramePointer) {
6101 mov(rbp, rsp);
6102 }
6103 // Remove word for ebp
6104 framesize -= wordSize;
6105
6106 // Create frame
6107 if (framesize) {
6108 subptr(rsp, framesize);
6109 }
6110 } else {
6111 // Create frame (force generation of a 4 byte immediate value)
6112 subptr_imm32(rsp, framesize);
6113
6114 // Save RBP register now.
6115 framesize -= wordSize;
6116 movptr(Address(rsp, framesize), rbp);
6117 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6118 if (PreserveFramePointer) {
6119 movptr(rbp, rsp);
6120 addptr(rbp, framesize + wordSize);
6121 }
6122 }
6123
6124 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6125 framesize -= wordSize;
6126 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6127 }
6128
6129 #ifndef _LP64
6130 // If method sets FPU control word do it now
6131 if (fp_mode_24b) {
6132 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6133 }
6134 if (UseSSE >= 2 && VerifyFPU) {
6135 verify_FPU(0, "FPU stack must be clean on entry");
6136 }
6137 #endif
6138
6139 #ifdef ASSERT
6140 if (VerifyStackAtCalls) {
6141 Label L;
6142 push(rax);
6143 mov(rax, rsp);
6144 andptr(rax, StackAlignmentInBytes-1);
6145 cmpptr(rax, StackAlignmentInBytes-wordSize);
6146 pop(rax);
6147 jcc(Assembler::equal, L);
6148 STOP("Stack is not properly aligned!");
6149 bind(L);
6150 }
6151 #endif
6152
6153 }
6154
6155 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) {
6156 // cnt - number of qwords (8-byte words).
6157 // base - start address, qword aligned.
6158 assert(base==rdi, "base register must be edi for rep stos");
6159 assert(tmp==rax, "tmp register must be eax for rep stos");
6160 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6161
6162 xorptr(tmp, tmp);
6163 if (UseFastStosb) {
6164 shlptr(cnt,3); // convert to number of bytes
6165 rep_stosb();
6166 } else {
6167 NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM
6168 rep_stos();
6169 }
6170 }
6171
6172 // IndexOf for constant substrings with size >= 8 chars
6173 // which don't need to be loaded through stack.
6174 void MacroAssembler::string_indexofC8(Register str1, Register str2,
6175 Register cnt1, Register cnt2,
6176 int int_cnt2, Register result,
6177 XMMRegister vec, Register tmp) {
6178 ShortBranchVerifier sbv(this);
6179 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6180
6181 // This method uses pcmpestri instruction with bound registers
6182 // inputs:
6183 // xmm - substring
6184 // rax - substring length (elements count)
6185 // mem - scanned string
6186 // rdx - string length (elements count)
6187 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6188 // outputs:
6189 // rcx - matched index in string
6190 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6191
6192 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
6193 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
6194 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
6195
6196 // Note, inline_string_indexOf() generates checks:
6197 // if (substr.count > string.count) return -1;
6198 // if (substr.count == 0) return 0;
6199 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars");
6200
6201 // Load substring.
6202 movdqu(vec, Address(str2, 0));
6203 movl(cnt2, int_cnt2);
6204 movptr(result, str1); // string addr
6205
6206 if (int_cnt2 > 8) {
6207 jmpb(SCAN_TO_SUBSTR);
6208
6209 // Reload substr for rescan, this code
6210 // is executed only for large substrings (> 8 chars)
6211 bind(RELOAD_SUBSTR);
6212 movdqu(vec, Address(str2, 0));
6213 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
6214
6215 bind(RELOAD_STR);
6216 // We came here after the beginning of the substring was
6217 // matched but the rest of it was not so we need to search
6218 // again. Start from the next element after the previous match.
6219
6220 // cnt2 is number of substring reminding elements and
6221 // cnt1 is number of string reminding elements when cmp failed.
6222 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
6223 subl(cnt1, cnt2);
6224 addl(cnt1, int_cnt2);
6225 movl(cnt2, int_cnt2); // Now restore cnt2
6226
6227 decrementl(cnt1); // Shift to next element
6228 cmpl(cnt1, cnt2);
6229 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6230
6231 addptr(result, 2);
6232
6233 } // (int_cnt2 > 8)
6234
6235 // Scan string for start of substr in 16-byte vectors
6236 bind(SCAN_TO_SUBSTR);
6237 pcmpestri(vec, Address(result, 0), 0x0d);
6238 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6239 subl(cnt1, 8);
6240 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6241 cmpl(cnt1, cnt2);
6242 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6243 addptr(result, 16);
6244 jmpb(SCAN_TO_SUBSTR);
6245
6246 // Found a potential substr
6247 bind(FOUND_CANDIDATE);
6248 // Matched whole vector if first element matched (tmp(rcx) == 0).
6249 if (int_cnt2 == 8) {
6250 jccb(Assembler::overflow, RET_FOUND); // OF == 1
6251 } else { // int_cnt2 > 8
6252 jccb(Assembler::overflow, FOUND_SUBSTR);
6253 }
6254 // After pcmpestri tmp(rcx) contains matched element index
6255 // Compute start addr of substr
6256 lea(result, Address(result, tmp, Address::times_2));
6257
6258 // Make sure string is still long enough
6259 subl(cnt1, tmp);
6260 cmpl(cnt1, cnt2);
6261 if (int_cnt2 == 8) {
6262 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6263 } else { // int_cnt2 > 8
6264 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
6265 }
6266 // Left less then substring.
6267
6268 bind(RET_NOT_FOUND);
6269 movl(result, -1);
6270 jmpb(EXIT);
6271
6272 if (int_cnt2 > 8) {
6273 // This code is optimized for the case when whole substring
6274 // is matched if its head is matched.
6275 bind(MATCH_SUBSTR_HEAD);
6276 pcmpestri(vec, Address(result, 0), 0x0d);
6277 // Reload only string if does not match
6278 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
6279
6280 Label CONT_SCAN_SUBSTR;
6281 // Compare the rest of substring (> 8 chars).
6282 bind(FOUND_SUBSTR);
6283 // First 8 chars are already matched.
6284 negptr(cnt2);
6285 addptr(cnt2, 8);
6286
6287 bind(SCAN_SUBSTR);
6288 subl(cnt1, 8);
6289 cmpl(cnt2, -8); // Do not read beyond substring
6290 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
6291 // Back-up strings to avoid reading beyond substring:
6292 // cnt1 = cnt1 - cnt2 + 8
6293 addl(cnt1, cnt2); // cnt2 is negative
6294 addl(cnt1, 8);
6295 movl(cnt2, 8); negptr(cnt2);
6296 bind(CONT_SCAN_SUBSTR);
6297 if (int_cnt2 < (int)G) {
6298 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2));
6299 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d);
6300 } else {
6301 // calculate index in register to avoid integer overflow (int_cnt2*2)
6302 movl(tmp, int_cnt2);
6303 addptr(tmp, cnt2);
6304 movdqu(vec, Address(str2, tmp, Address::times_2, 0));
6305 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d);
6306 }
6307 // Need to reload strings pointers if not matched whole vector
6308 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6309 addptr(cnt2, 8);
6310 jcc(Assembler::negative, SCAN_SUBSTR);
6311 // Fall through if found full substring
6312
6313 } // (int_cnt2 > 8)
6314
6315 bind(RET_FOUND);
6316 // Found result if we matched full small substring.
6317 // Compute substr offset
6318 subptr(result, str1);
6319 shrl(result, 1); // index
6320 bind(EXIT);
6321
6322 } // string_indexofC8
6323
6324 // Small strings are loaded through stack if they cross page boundary.
6325 void MacroAssembler::string_indexof(Register str1, Register str2,
6326 Register cnt1, Register cnt2,
6327 int int_cnt2, Register result,
6328 XMMRegister vec, Register tmp) {
6329 ShortBranchVerifier sbv(this);
6330 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6331 //
6332 // int_cnt2 is length of small (< 8 chars) constant substring
6333 // or (-1) for non constant substring in which case its length
6334 // is in cnt2 register.
6335 //
6336 // Note, inline_string_indexOf() generates checks:
6337 // if (substr.count > string.count) return -1;
6338 // if (substr.count == 0) return 0;
6339 //
6340 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0");
6341
6342 // This method uses pcmpestri instruction with bound registers
6343 // inputs:
6344 // xmm - substring
6345 // rax - substring length (elements count)
6346 // mem - scanned string
6347 // rdx - string length (elements count)
6348 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6349 // outputs:
6350 // rcx - matched index in string
6351 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6352
6353 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6354 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6355 FOUND_CANDIDATE;
6356
6357 { //========================================================
6358 // We don't know where these strings are located
6359 // and we can't read beyond them. Load them through stack.
6360 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6361
6362 movptr(tmp, rsp); // save old SP
6363
6364 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6365 if (int_cnt2 == 1) { // One char
6366 load_unsigned_short(result, Address(str2, 0));
6367 movdl(vec, result); // move 32 bits
6368 } else if (int_cnt2 == 2) { // Two chars
6369 movdl(vec, Address(str2, 0)); // move 32 bits
6370 } else if (int_cnt2 == 4) { // Four chars
6371 movq(vec, Address(str2, 0)); // move 64 bits
6372 } else { // cnt2 = { 3, 5, 6, 7 }
6373 // Array header size is 12 bytes in 32-bit VM
6374 // + 6 bytes for 3 chars == 18 bytes,
6375 // enough space to load vec and shift.
6376 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6377 movdqu(vec, Address(str2, (int_cnt2*2)-16));
6378 psrldq(vec, 16-(int_cnt2*2));
6379 }
6380 } else { // not constant substring
6381 cmpl(cnt2, 8);
6382 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6383
6384 // We can read beyond string if srt+16 does not cross page boundary
6385 // since heaps are aligned and mapped by pages.
6386 assert(os::vm_page_size() < (int)G, "default page should be small");
6387 movl(result, str2); // We need only low 32 bits
6388 andl(result, (os::vm_page_size()-1));
6389 cmpl(result, (os::vm_page_size()-16));
6390 jccb(Assembler::belowEqual, CHECK_STR);
6391
6392 // Move small strings to stack to allow load 16 bytes into vec.
6393 subptr(rsp, 16);
6394 int stk_offset = wordSize-2;
6395 push(cnt2);
6396
6397 bind(COPY_SUBSTR);
6398 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2));
6399 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6400 decrement(cnt2);
6401 jccb(Assembler::notZero, COPY_SUBSTR);
6402
6403 pop(cnt2);
6404 movptr(str2, rsp); // New substring address
6405 } // non constant
6406
6407 bind(CHECK_STR);
6408 cmpl(cnt1, 8);
6409 jccb(Assembler::aboveEqual, BIG_STRINGS);
6410
6411 // Check cross page boundary.
6412 movl(result, str1); // We need only low 32 bits
6413 andl(result, (os::vm_page_size()-1));
6414 cmpl(result, (os::vm_page_size()-16));
6415 jccb(Assembler::belowEqual, BIG_STRINGS);
6416
6417 subptr(rsp, 16);
6418 int stk_offset = -2;
6419 if (int_cnt2 < 0) { // not constant
6420 push(cnt2);
6421 stk_offset += wordSize;
6422 }
6423 movl(cnt2, cnt1);
6424
6425 bind(COPY_STR);
6426 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2));
6427 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6428 decrement(cnt2);
6429 jccb(Assembler::notZero, COPY_STR);
6430
6431 if (int_cnt2 < 0) { // not constant
6432 pop(cnt2);
6433 }
6434 movptr(str1, rsp); // New string address
6435
6436 bind(BIG_STRINGS);
6437 // Load substring.
6438 if (int_cnt2 < 0) { // -1
6439 movdqu(vec, Address(str2, 0));
6440 push(cnt2); // substr count
6441 push(str2); // substr addr
6442 push(str1); // string addr
6443 } else {
6444 // Small (< 8 chars) constant substrings are loaded already.
6445 movl(cnt2, int_cnt2);
6446 }
6447 push(tmp); // original SP
6448
6449 } // Finished loading
6450
6451 //========================================================
6452 // Start search
6453 //
6454
6455 movptr(result, str1); // string addr
6456
6457 if (int_cnt2 < 0) { // Only for non constant substring
6458 jmpb(SCAN_TO_SUBSTR);
6459
6460 // SP saved at sp+0
6461 // String saved at sp+1*wordSize
6462 // Substr saved at sp+2*wordSize
6463 // Substr count saved at sp+3*wordSize
6464
6465 // Reload substr for rescan, this code
6466 // is executed only for large substrings (> 8 chars)
6467 bind(RELOAD_SUBSTR);
6468 movptr(str2, Address(rsp, 2*wordSize));
6469 movl(cnt2, Address(rsp, 3*wordSize));
6470 movdqu(vec, Address(str2, 0));
6471 // We came here after the beginning of the substring was
6472 // matched but the rest of it was not so we need to search
6473 // again. Start from the next element after the previous match.
6474 subptr(str1, result); // Restore counter
6475 shrl(str1, 1);
6476 addl(cnt1, str1);
6477 decrementl(cnt1); // Shift to next element
6478 cmpl(cnt1, cnt2);
6479 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6480
6481 addptr(result, 2);
6482 } // non constant
6483
6484 // Scan string for start of substr in 16-byte vectors
6485 bind(SCAN_TO_SUBSTR);
6486 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6487 pcmpestri(vec, Address(result, 0), 0x0d);
6488 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6489 subl(cnt1, 8);
6490 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6491 cmpl(cnt1, cnt2);
6492 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6493 addptr(result, 16);
6494
6495 bind(ADJUST_STR);
6496 cmpl(cnt1, 8); // Do not read beyond string
6497 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6498 // Back-up string to avoid reading beyond string.
6499 lea(result, Address(result, cnt1, Address::times_2, -16));
6500 movl(cnt1, 8);
6501 jmpb(SCAN_TO_SUBSTR);
6502
6503 // Found a potential substr
6504 bind(FOUND_CANDIDATE);
6505 // After pcmpestri tmp(rcx) contains matched element index
6506
6507 // Make sure string is still long enough
6508 subl(cnt1, tmp);
6509 cmpl(cnt1, cnt2);
6510 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6511 // Left less then substring.
6512
6513 bind(RET_NOT_FOUND);
6514 movl(result, -1);
6515 jmpb(CLEANUP);
6516
6517 bind(FOUND_SUBSTR);
6518 // Compute start addr of substr
6519 lea(result, Address(result, tmp, Address::times_2));
6520
6521 if (int_cnt2 > 0) { // Constant substring
6522 // Repeat search for small substring (< 8 chars)
6523 // from new point without reloading substring.
6524 // Have to check that we don't read beyond string.
6525 cmpl(tmp, 8-int_cnt2);
6526 jccb(Assembler::greater, ADJUST_STR);
6527 // Fall through if matched whole substring.
6528 } else { // non constant
6529 assert(int_cnt2 == -1, "should be != 0");
6530
6531 addl(tmp, cnt2);
6532 // Found result if we matched whole substring.
6533 cmpl(tmp, 8);
6534 jccb(Assembler::lessEqual, RET_FOUND);
6535
6536 // Repeat search for small substring (<= 8 chars)
6537 // from new point 'str1' without reloading substring.
6538 cmpl(cnt2, 8);
6539 // Have to check that we don't read beyond string.
6540 jccb(Assembler::lessEqual, ADJUST_STR);
6541
6542 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6543 // Compare the rest of substring (> 8 chars).
6544 movptr(str1, result);
6545
6546 cmpl(tmp, cnt2);
6547 // First 8 chars are already matched.
6548 jccb(Assembler::equal, CHECK_NEXT);
6549
6550 bind(SCAN_SUBSTR);
6551 pcmpestri(vec, Address(str1, 0), 0x0d);
6552 // Need to reload strings pointers if not matched whole vector
6553 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6554
6555 bind(CHECK_NEXT);
6556 subl(cnt2, 8);
6557 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6558 addptr(str1, 16);
6559 addptr(str2, 16);
6560 subl(cnt1, 8);
6561 cmpl(cnt2, 8); // Do not read beyond substring
6562 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6563 // Back-up strings to avoid reading beyond substring.
6564 lea(str2, Address(str2, cnt2, Address::times_2, -16));
6565 lea(str1, Address(str1, cnt2, Address::times_2, -16));
6566 subl(cnt1, cnt2);
6567 movl(cnt2, 8);
6568 addl(cnt1, 8);
6569 bind(CONT_SCAN_SUBSTR);
6570 movdqu(vec, Address(str2, 0));
6571 jmpb(SCAN_SUBSTR);
6572
6573 bind(RET_FOUND_LONG);
6574 movptr(str1, Address(rsp, wordSize));
6575 } // non constant
6576
6577 bind(RET_FOUND);
6578 // Compute substr offset
6579 subptr(result, str1);
6580 shrl(result, 1); // index
6581
6582 bind(CLEANUP);
6583 pop(rsp); // restore SP
6584
6585 } // string_indexof
6586
6587 // Compare strings.
6588 void MacroAssembler::string_compare(Register str1, Register str2,
6589 Register cnt1, Register cnt2, Register result,
6590 XMMRegister vec1) {
6591 ShortBranchVerifier sbv(this);
6592 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6593
6594 // Compute the minimum of the string lengths and the
6595 // difference of the string lengths (stack).
6596 // Do the conditional move stuff
6597 movl(result, cnt1);
6598 subl(cnt1, cnt2);
6599 push(cnt1);
6600 cmov32(Assembler::lessEqual, cnt2, result);
6601
6602 // Is the minimum length zero?
6603 testl(cnt2, cnt2);
6604 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6605
6606 // Compare first characters
6607 load_unsigned_short(result, Address(str1, 0));
6608 load_unsigned_short(cnt1, Address(str2, 0));
6609 subl(result, cnt1);
6610 jcc(Assembler::notZero, POP_LABEL);
6611 cmpl(cnt2, 1);
6612 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6613
6614 // Check if the strings start at the same location.
6615 cmpptr(str1, str2);
6616 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6617
6618 Address::ScaleFactor scale = Address::times_2;
6619 int stride = 8;
6620
6621 if (UseAVX >= 2 && UseSSE42Intrinsics) {
6622 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6623 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6624 Label COMPARE_TAIL_LONG;
6625 int pcmpmask = 0x19;
6626
6627 // Setup to compare 16-chars (32-bytes) vectors,
6628 // start from first character again because it has aligned address.
6629 int stride2 = 16;
6630 int adr_stride = stride << scale;
6631
6632 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6633 // rax and rdx are used by pcmpestri as elements counters
6634 movl(result, cnt2);
6635 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
6636 jcc(Assembler::zero, COMPARE_TAIL_LONG);
6637
6638 // fast path : compare first 2 8-char vectors.
6639 bind(COMPARE_16_CHARS);
6640 movdqu(vec1, Address(str1, 0));
6641 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6642 jccb(Assembler::below, COMPARE_INDEX_CHAR);
6643
6644 movdqu(vec1, Address(str1, adr_stride));
6645 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6646 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6647 addl(cnt1, stride);
6648
6649 // Compare the characters at index in cnt1
6650 bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character
6651 load_unsigned_short(result, Address(str1, cnt1, scale));
6652 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6653 subl(result, cnt2);
6654 jmp(POP_LABEL);
6655
6656 // Setup the registers to start vector comparison loop
6657 bind(COMPARE_WIDE_VECTORS);
6658 lea(str1, Address(str1, result, scale));
6659 lea(str2, Address(str2, result, scale));
6660 subl(result, stride2);
6661 subl(cnt2, stride2);
6662 jccb(Assembler::zero, COMPARE_WIDE_TAIL);
6663 negptr(result);
6664
6665 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6666 bind(COMPARE_WIDE_VECTORS_LOOP);
6667 vmovdqu(vec1, Address(str1, result, scale));
6668 vpxor(vec1, Address(str2, result, scale));
6669 vptest(vec1, vec1);
6670 jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
6671 addptr(result, stride2);
6672 subl(cnt2, stride2);
6673 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6674 // clean upper bits of YMM registers
6675 vpxor(vec1, vec1);
6676
6677 // compare wide vectors tail
6678 bind(COMPARE_WIDE_TAIL);
6679 testptr(result, result);
6680 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6681
6682 movl(result, stride2);
6683 movl(cnt2, result);
6684 negptr(result);
6685 jmpb(COMPARE_WIDE_VECTORS_LOOP);
6686
6687 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6688 bind(VECTOR_NOT_EQUAL);
6689 // clean upper bits of YMM registers
6690 vpxor(vec1, vec1);
6691 lea(str1, Address(str1, result, scale));
6692 lea(str2, Address(str2, result, scale));
6693 jmp(COMPARE_16_CHARS);
6694
6695 // Compare tail chars, length between 1 to 15 chars
6696 bind(COMPARE_TAIL_LONG);
6697 movl(cnt2, result);
6698 cmpl(cnt2, stride);
6699 jccb(Assembler::less, COMPARE_SMALL_STR);
6700
6701 movdqu(vec1, Address(str1, 0));
6702 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6703 jcc(Assembler::below, COMPARE_INDEX_CHAR);
6704 subptr(cnt2, stride);
6705 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6706 lea(str1, Address(str1, result, scale));
6707 lea(str2, Address(str2, result, scale));
6708 negptr(cnt2);
6709 jmpb(WHILE_HEAD_LABEL);
6710
6711 bind(COMPARE_SMALL_STR);
6712 } else if (UseSSE42Intrinsics) {
6713 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6714 int pcmpmask = 0x19;
6715 // Setup to compare 8-char (16-byte) vectors,
6716 // start from first character again because it has aligned address.
6717 movl(result, cnt2);
6718 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
6719 jccb(Assembler::zero, COMPARE_TAIL);
6720
6721 lea(str1, Address(str1, result, scale));
6722 lea(str2, Address(str2, result, scale));
6723 negptr(result);
6724
6725 // pcmpestri
6726 // inputs:
6727 // vec1- substring
6728 // rax - negative string length (elements count)
6729 // mem - scanned string
6730 // rdx - string length (elements count)
6731 // pcmpmask - cmp mode: 11000 (string compare with negated result)
6732 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
6733 // outputs:
6734 // rcx - first mismatched element index
6735 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6736
6737 bind(COMPARE_WIDE_VECTORS);
6738 movdqu(vec1, Address(str1, result, scale));
6739 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6740 // After pcmpestri cnt1(rcx) contains mismatched element index
6741
6742 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
6743 addptr(result, stride);
6744 subptr(cnt2, stride);
6745 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6746
6747 // compare wide vectors tail
6748 testptr(result, result);
6749 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6750
6751 movl(cnt2, stride);
6752 movl(result, stride);
6753 negptr(result);
6754 movdqu(vec1, Address(str1, result, scale));
6755 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6756 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6757
6758 // Mismatched characters in the vectors
6759 bind(VECTOR_NOT_EQUAL);
6760 addptr(cnt1, result);
6761 load_unsigned_short(result, Address(str1, cnt1, scale));
6762 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6763 subl(result, cnt2);
6764 jmpb(POP_LABEL);
6765
6766 bind(COMPARE_TAIL); // limit is zero
6767 movl(cnt2, result);
6768 // Fallthru to tail compare
6769 }
6770 // Shift str2 and str1 to the end of the arrays, negate min
6771 lea(str1, Address(str1, cnt2, scale));
6772 lea(str2, Address(str2, cnt2, scale));
6773 decrementl(cnt2); // first character was compared already
6774 negptr(cnt2);
6775
6776 // Compare the rest of the elements
6777 bind(WHILE_HEAD_LABEL);
6778 load_unsigned_short(result, Address(str1, cnt2, scale, 0));
6779 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0));
6780 subl(result, cnt1);
6781 jccb(Assembler::notZero, POP_LABEL);
6782 increment(cnt2);
6783 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6784
6785 // Strings are equal up to min length. Return the length difference.
6786 bind(LENGTH_DIFF_LABEL);
6787 pop(result);
6788 jmpb(DONE_LABEL);
6789
6790 // Discard the stored length difference
6791 bind(POP_LABEL);
6792 pop(cnt1);
6793
6794 // That's it
6795 bind(DONE_LABEL);
6796 }
6797
6798 // Compare char[] arrays aligned to 4 bytes or substrings.
6799 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
6800 Register limit, Register result, Register chr,
6801 XMMRegister vec1, XMMRegister vec2) {
6802 ShortBranchVerifier sbv(this);
6803 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
6804
6805 int length_offset = arrayOopDesc::length_offset_in_bytes();
6806 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
6807
6808 // Check the input args
6809 cmpptr(ary1, ary2);
6810 jcc(Assembler::equal, TRUE_LABEL);
6811
6812 if (is_array_equ) {
6813 // Need additional checks for arrays_equals.
6814 testptr(ary1, ary1);
6815 jcc(Assembler::zero, FALSE_LABEL);
6816 testptr(ary2, ary2);
6817 jcc(Assembler::zero, FALSE_LABEL);
6818
6819 // Check the lengths
6820 movl(limit, Address(ary1, length_offset));
6821 cmpl(limit, Address(ary2, length_offset));
6822 jcc(Assembler::notEqual, FALSE_LABEL);
6823 }
6824
6825 // count == 0
6826 testl(limit, limit);
6827 jcc(Assembler::zero, TRUE_LABEL);
6828
6829 if (is_array_equ) {
6830 // Load array address
6831 lea(ary1, Address(ary1, base_offset));
6832 lea(ary2, Address(ary2, base_offset));
6833 }
6834
6835 shll(limit, 1); // byte count != 0
6836 movl(result, limit); // copy
6837
6838 if (UseAVX >= 2) {
6839 // With AVX2, use 32-byte vector compare
6840 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6841
6842 // Compare 32-byte vectors
6843 andl(result, 0x0000001e); // tail count (in bytes)
6844 andl(limit, 0xffffffe0); // vector count (in bytes)
6845 jccb(Assembler::zero, COMPARE_TAIL);
6846
6847 lea(ary1, Address(ary1, limit, Address::times_1));
6848 lea(ary2, Address(ary2, limit, Address::times_1));
6849 negptr(limit);
6850
6851 bind(COMPARE_WIDE_VECTORS);
6852 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
6853 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
6854 vpxor(vec1, vec2);
6855
6856 vptest(vec1, vec1);
6857 jccb(Assembler::notZero, FALSE_LABEL);
6858 addptr(limit, 32);
6859 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6860
6861 testl(result, result);
6862 jccb(Assembler::zero, TRUE_LABEL);
6863
6864 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6865 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
6866 vpxor(vec1, vec2);
6867
6868 vptest(vec1, vec1);
6869 jccb(Assembler::notZero, FALSE_LABEL);
6870 jmpb(TRUE_LABEL);
6871
6872 bind(COMPARE_TAIL); // limit is zero
6873 movl(limit, result);
6874 // Fallthru to tail compare
6875 } else if (UseSSE42Intrinsics) {
6876 // With SSE4.2, use double quad vector compare
6877 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6878
6879 // Compare 16-byte vectors
6880 andl(result, 0x0000000e); // tail count (in bytes)
6881 andl(limit, 0xfffffff0); // vector count (in bytes)
6882 jccb(Assembler::zero, COMPARE_TAIL);
6883
6884 lea(ary1, Address(ary1, limit, Address::times_1));
6885 lea(ary2, Address(ary2, limit, Address::times_1));
6886 negptr(limit);
6887
6888 bind(COMPARE_WIDE_VECTORS);
6889 movdqu(vec1, Address(ary1, limit, Address::times_1));
6890 movdqu(vec2, Address(ary2, limit, Address::times_1));
6891 pxor(vec1, vec2);
6892
6893 ptest(vec1, vec1);
6894 jccb(Assembler::notZero, FALSE_LABEL);
6895 addptr(limit, 16);
6896 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6897
6898 testl(result, result);
6899 jccb(Assembler::zero, TRUE_LABEL);
6900
6901 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
6902 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
6903 pxor(vec1, vec2);
6904
6905 ptest(vec1, vec1);
6906 jccb(Assembler::notZero, FALSE_LABEL);
6907 jmpb(TRUE_LABEL);
6908
6909 bind(COMPARE_TAIL); // limit is zero
6910 movl(limit, result);
6911 // Fallthru to tail compare
6912 }
6913
6914 // Compare 4-byte vectors
6915 andl(limit, 0xfffffffc); // vector count (in bytes)
6916 jccb(Assembler::zero, COMPARE_CHAR);
6917
6918 lea(ary1, Address(ary1, limit, Address::times_1));
6919 lea(ary2, Address(ary2, limit, Address::times_1));
6920 negptr(limit);
6921
6922 bind(COMPARE_VECTORS);
6923 movl(chr, Address(ary1, limit, Address::times_1));
6924 cmpl(chr, Address(ary2, limit, Address::times_1));
6925 jccb(Assembler::notEqual, FALSE_LABEL);
6926 addptr(limit, 4);
6927 jcc(Assembler::notZero, COMPARE_VECTORS);
6928
6929 // Compare trailing char (final 2 bytes), if any
6930 bind(COMPARE_CHAR);
6931 testl(result, 0x2); // tail char
6932 jccb(Assembler::zero, TRUE_LABEL);
6933 load_unsigned_short(chr, Address(ary1, 0));
6934 load_unsigned_short(limit, Address(ary2, 0));
6935 cmpl(chr, limit);
6936 jccb(Assembler::notEqual, FALSE_LABEL);
6937
6938 bind(TRUE_LABEL);
6939 movl(result, 1); // return true
6940 jmpb(DONE);
6941
6942 bind(FALSE_LABEL);
6943 xorl(result, result); // return false
6944
6945 // That's it
6946 bind(DONE);
6947 if (UseAVX >= 2) {
6948 // clean upper bits of YMM registers
6949 vpxor(vec1, vec1);
6950 vpxor(vec2, vec2);
6951 }
6952 }
6953
6954 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6955 Register to, Register value, Register count,
6956 Register rtmp, XMMRegister xtmp) {
6957 ShortBranchVerifier sbv(this);
6958 assert_different_registers(to, value, count, rtmp);
6959 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
6960 Label L_fill_2_bytes, L_fill_4_bytes;
6961
6962 int shift = -1;
6963 switch (t) {
6964 case T_BYTE:
6965 shift = 2;
6966 break;
6967 case T_SHORT:
6968 shift = 1;
6969 break;
6970 case T_INT:
6971 shift = 0;
6972 break;
6973 default: ShouldNotReachHere();
6974 }
6975
6976 if (t == T_BYTE) {
6977 andl(value, 0xff);
6978 movl(rtmp, value);
6979 shll(rtmp, 8);
6980 orl(value, rtmp);
6981 }
6982 if (t == T_SHORT) {
6983 andl(value, 0xffff);
6984 }
6985 if (t == T_BYTE || t == T_SHORT) {
6986 movl(rtmp, value);
6987 shll(rtmp, 16);
6988 orl(value, rtmp);
6989 }
6990
6991 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
6992 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6993 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6994 // align source address at 4 bytes address boundary
6995 if (t == T_BYTE) {
6996 // One byte misalignment happens only for byte arrays
6997 testptr(to, 1);
6998 jccb(Assembler::zero, L_skip_align1);
6999 movb(Address(to, 0), value);
7000 increment(to);
7001 decrement(count);
7002 BIND(L_skip_align1);
7003 }
7004 // Two bytes misalignment happens only for byte and short (char) arrays
7005 testptr(to, 2);
7006 jccb(Assembler::zero, L_skip_align2);
7007 movw(Address(to, 0), value);
7008 addptr(to, 2);
7009 subl(count, 1<<(shift-1));
7010 BIND(L_skip_align2);
7011 }
7012 if (UseSSE < 2) {
7013 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7014 // Fill 32-byte chunks
7015 subl(count, 8 << shift);
7016 jcc(Assembler::less, L_check_fill_8_bytes);
7017 align(16);
7018
7019 BIND(L_fill_32_bytes_loop);
7020
7021 for (int i = 0; i < 32; i += 4) {
7022 movl(Address(to, i), value);
7023 }
7024
7025 addptr(to, 32);
7026 subl(count, 8 << shift);
7027 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7028 BIND(L_check_fill_8_bytes);
7029 addl(count, 8 << shift);
7030 jccb(Assembler::zero, L_exit);
7031 jmpb(L_fill_8_bytes);
7032
7033 //
7034 // length is too short, just fill qwords
7035 //
7036 BIND(L_fill_8_bytes_loop);
7037 movl(Address(to, 0), value);
7038 movl(Address(to, 4), value);
7039 addptr(to, 8);
7040 BIND(L_fill_8_bytes);
7041 subl(count, 1 << (shift + 1));
7042 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7043 // fall through to fill 4 bytes
7044 } else {
7045 Label L_fill_32_bytes;
7046 if (!UseUnalignedLoadStores) {
7047 // align to 8 bytes, we know we are 4 byte aligned to start
7048 testptr(to, 4);
7049 jccb(Assembler::zero, L_fill_32_bytes);
7050 movl(Address(to, 0), value);
7051 addptr(to, 4);
7052 subl(count, 1<<shift);
7053 }
7054 BIND(L_fill_32_bytes);
7055 {
7056 assert( UseSSE >= 2, "supported cpu only" );
7057 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7058 if (UseAVX > 2) {
7059 movl(rtmp, 0xffff);
7060 #ifdef _LP64
7061 kmovql(k1, rtmp);
7062 #else
7063 kmovdl(k1, rtmp);
7064 #endif
7065 }
7066 movdl(xtmp, value);
7067 if (UseAVX > 2 && UseUnalignedLoadStores) {
7068 // Fill 64-byte chunks
7069 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7070 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
7071
7072 subl(count, 16 << shift);
7073 jcc(Assembler::less, L_check_fill_32_bytes);
7074 align(16);
7075
7076 BIND(L_fill_64_bytes_loop);
7077 evmovdqu(Address(to, 0), xtmp, Assembler::AVX_512bit);
7078 addptr(to, 64);
7079 subl(count, 16 << shift);
7080 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7081
7082 BIND(L_check_fill_32_bytes);
7083 addl(count, 8 << shift);
7084 jccb(Assembler::less, L_check_fill_8_bytes);
7085 evmovdqu(Address(to, 0), xtmp, Assembler::AVX_256bit);
7086 addptr(to, 32);
7087 subl(count, 8 << shift);
7088
7089 BIND(L_check_fill_8_bytes);
7090 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
7091 // Fill 64-byte chunks
7092 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7093 vpbroadcastd(xtmp, xtmp);
7094
7095 subl(count, 16 << shift);
7096 jcc(Assembler::less, L_check_fill_32_bytes);
7097 align(16);
7098
7099 BIND(L_fill_64_bytes_loop);
7100 vmovdqu(Address(to, 0), xtmp);
7101 vmovdqu(Address(to, 32), xtmp);
7102 addptr(to, 64);
7103 subl(count, 16 << shift);
7104 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7105
7106 BIND(L_check_fill_32_bytes);
7107 addl(count, 8 << shift);
7108 jccb(Assembler::less, L_check_fill_8_bytes);
7109 vmovdqu(Address(to, 0), xtmp);
7110 addptr(to, 32);
7111 subl(count, 8 << shift);
7112
7113 BIND(L_check_fill_8_bytes);
7114 // clean upper bits of YMM registers
7115 movdl(xtmp, value);
7116 pshufd(xtmp, xtmp, 0);
7117 } else {
7118 // Fill 32-byte chunks
7119 pshufd(xtmp, xtmp, 0);
7120
7121 subl(count, 8 << shift);
7122 jcc(Assembler::less, L_check_fill_8_bytes);
7123 align(16);
7124
7125 BIND(L_fill_32_bytes_loop);
7126
7127 if (UseUnalignedLoadStores) {
7128 movdqu(Address(to, 0), xtmp);
7129 movdqu(Address(to, 16), xtmp);
7130 } else {
7131 movq(Address(to, 0), xtmp);
7132 movq(Address(to, 8), xtmp);
7133 movq(Address(to, 16), xtmp);
7134 movq(Address(to, 24), xtmp);
7135 }
7136
7137 addptr(to, 32);
7138 subl(count, 8 << shift);
7139 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7140
7141 BIND(L_check_fill_8_bytes);
7142 }
7143 addl(count, 8 << shift);
7144 jccb(Assembler::zero, L_exit);
7145 jmpb(L_fill_8_bytes);
7146
7147 //
7148 // length is too short, just fill qwords
7149 //
7150 BIND(L_fill_8_bytes_loop);
7151 movq(Address(to, 0), xtmp);
7152 addptr(to, 8);
7153 BIND(L_fill_8_bytes);
7154 subl(count, 1 << (shift + 1));
7155 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7156 }
7157 }
7158 // fill trailing 4 bytes
7159 BIND(L_fill_4_bytes);
7160 testl(count, 1<<shift);
7161 jccb(Assembler::zero, L_fill_2_bytes);
7162 movl(Address(to, 0), value);
7163 if (t == T_BYTE || t == T_SHORT) {
7164 addptr(to, 4);
7165 BIND(L_fill_2_bytes);
7166 // fill trailing 2 bytes
7167 testl(count, 1<<(shift-1));
7168 jccb(Assembler::zero, L_fill_byte);
7169 movw(Address(to, 0), value);
7170 if (t == T_BYTE) {
7171 addptr(to, 2);
7172 BIND(L_fill_byte);
7173 // fill trailing byte
7174 testl(count, 1);
7175 jccb(Assembler::zero, L_exit);
7176 movb(Address(to, 0), value);
7177 } else {
7178 BIND(L_fill_byte);
7179 }
7180 } else {
7181 BIND(L_fill_2_bytes);
7182 }
7183 BIND(L_exit);
7184 }
7185
7186 // encode char[] to byte[] in ISO_8859_1
7187 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7188 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7189 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7190 Register tmp5, Register result) {
7191 // rsi: src
7192 // rdi: dst
7193 // rdx: len
7194 // rcx: tmp5
7195 // rax: result
7196 ShortBranchVerifier sbv(this);
7197 assert_different_registers(src, dst, len, tmp5, result);
7198 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7199
7200 // set result
7201 xorl(result, result);
7202 // check for zero length
7203 testl(len, len);
7204 jcc(Assembler::zero, L_done);
7205 movl(result, len);
7206
7207 // Setup pointers
7208 lea(src, Address(src, len, Address::times_2)); // char[]
7209 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7210 negptr(len);
7211
7212 if (UseSSE42Intrinsics || UseAVX >= 2) {
7213 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
7214 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7215
7216 if (UseAVX >= 2) {
7217 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7218 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7219 movdl(tmp1Reg, tmp5);
7220 vpbroadcastd(tmp1Reg, tmp1Reg);
7221 jmpb(L_chars_32_check);
7222
7223 bind(L_copy_32_chars);
7224 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7225 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7226 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7227 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7228 jccb(Assembler::notZero, L_copy_32_chars_exit);
7229 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7230 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7231 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7232
7233 bind(L_chars_32_check);
7234 addptr(len, 32);
7235 jccb(Assembler::lessEqual, L_copy_32_chars);
7236
7237 bind(L_copy_32_chars_exit);
7238 subptr(len, 16);
7239 jccb(Assembler::greater, L_copy_16_chars_exit);
7240
7241 } else if (UseSSE42Intrinsics) {
7242 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7243 movdl(tmp1Reg, tmp5);
7244 pshufd(tmp1Reg, tmp1Reg, 0);
7245 jmpb(L_chars_16_check);
7246 }
7247
7248 bind(L_copy_16_chars);
7249 if (UseAVX >= 2) {
7250 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7251 vptest(tmp2Reg, tmp1Reg);
7252 jccb(Assembler::notZero, L_copy_16_chars_exit);
7253 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7254 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7255 } else {
7256 if (UseAVX > 0) {
7257 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7258 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7259 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7260 } else {
7261 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7262 por(tmp2Reg, tmp3Reg);
7263 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7264 por(tmp2Reg, tmp4Reg);
7265 }
7266 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7267 jccb(Assembler::notZero, L_copy_16_chars_exit);
7268 packuswb(tmp3Reg, tmp4Reg);
7269 }
7270 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7271
7272 bind(L_chars_16_check);
7273 addptr(len, 16);
7274 jccb(Assembler::lessEqual, L_copy_16_chars);
7275
7276 bind(L_copy_16_chars_exit);
7277 if (UseAVX >= 2) {
7278 // clean upper bits of YMM registers
7279 vpxor(tmp2Reg, tmp2Reg);
7280 vpxor(tmp3Reg, tmp3Reg);
7281 vpxor(tmp4Reg, tmp4Reg);
7282 movdl(tmp1Reg, tmp5);
7283 pshufd(tmp1Reg, tmp1Reg, 0);
7284 }
7285 subptr(len, 8);
7286 jccb(Assembler::greater, L_copy_8_chars_exit);
7287
7288 bind(L_copy_8_chars);
7289 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7290 ptest(tmp3Reg, tmp1Reg);
7291 jccb(Assembler::notZero, L_copy_8_chars_exit);
7292 packuswb(tmp3Reg, tmp1Reg);
7293 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7294 addptr(len, 8);
7295 jccb(Assembler::lessEqual, L_copy_8_chars);
7296
7297 bind(L_copy_8_chars_exit);
7298 subptr(len, 8);
7299 jccb(Assembler::zero, L_done);
7300 }
7301
7302 bind(L_copy_1_char);
7303 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7304 testl(tmp5, 0xff00); // check if Unicode char
7305 jccb(Assembler::notZero, L_copy_1_char_exit);
7306 movb(Address(dst, len, Address::times_1, 0), tmp5);
7307 addptr(len, 1);
7308 jccb(Assembler::less, L_copy_1_char);
7309
7310 bind(L_copy_1_char_exit);
7311 addptr(result, len); // len is negative count of not processed elements
7312 bind(L_done);
7313 }
7314
7315 #ifdef _LP64
7316 /**
7317 * Helper for multiply_to_len().
7318 */
7319 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7320 addq(dest_lo, src1);
7321 adcq(dest_hi, 0);
7322 addq(dest_lo, src2);
7323 adcq(dest_hi, 0);
7324 }
7325
7326 /**
7327 * Multiply 64 bit by 64 bit first loop.
7328 */
7329 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7330 Register y, Register y_idx, Register z,
7331 Register carry, Register product,
7332 Register idx, Register kdx) {
7333 //
7334 // jlong carry, x[], y[], z[];
7335 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7336 // huge_128 product = y[idx] * x[xstart] + carry;
7337 // z[kdx] = (jlong)product;
7338 // carry = (jlong)(product >>> 64);
7339 // }
7340 // z[xstart] = carry;
7341 //
7342
7343 Label L_first_loop, L_first_loop_exit;
7344 Label L_one_x, L_one_y, L_multiply;
7345
7346 decrementl(xstart);
7347 jcc(Assembler::negative, L_one_x);
7348
7349 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7350 rorq(x_xstart, 32); // convert big-endian to little-endian
7351
7352 bind(L_first_loop);
7353 decrementl(idx);
7354 jcc(Assembler::negative, L_first_loop_exit);
7355 decrementl(idx);
7356 jcc(Assembler::negative, L_one_y);
7357 movq(y_idx, Address(y, idx, Address::times_4, 0));
7358 rorq(y_idx, 32); // convert big-endian to little-endian
7359 bind(L_multiply);
7360 movq(product, x_xstart);
7361 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7362 addq(product, carry);
7363 adcq(rdx, 0);
7364 subl(kdx, 2);
7365 movl(Address(z, kdx, Address::times_4, 4), product);
7366 shrq(product, 32);
7367 movl(Address(z, kdx, Address::times_4, 0), product);
7368 movq(carry, rdx);
7369 jmp(L_first_loop);
7370
7371 bind(L_one_y);
7372 movl(y_idx, Address(y, 0));
7373 jmp(L_multiply);
7374
7375 bind(L_one_x);
7376 movl(x_xstart, Address(x, 0));
7377 jmp(L_first_loop);
7378
7379 bind(L_first_loop_exit);
7380 }
7381
7382 /**
7383 * Multiply 64 bit by 64 bit and add 128 bit.
7384 */
7385 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7386 Register yz_idx, Register idx,
7387 Register carry, Register product, int offset) {
7388 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7389 // z[kdx] = (jlong)product;
7390
7391 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7392 rorq(yz_idx, 32); // convert big-endian to little-endian
7393 movq(product, x_xstart);
7394 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7395 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7396 rorq(yz_idx, 32); // convert big-endian to little-endian
7397
7398 add2_with_carry(rdx, product, carry, yz_idx);
7399
7400 movl(Address(z, idx, Address::times_4, offset+4), product);
7401 shrq(product, 32);
7402 movl(Address(z, idx, Address::times_4, offset), product);
7403
7404 }
7405
7406 /**
7407 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7408 */
7409 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7410 Register yz_idx, Register idx, Register jdx,
7411 Register carry, Register product,
7412 Register carry2) {
7413 // jlong carry, x[], y[], z[];
7414 // int kdx = ystart+1;
7415 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7416 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7417 // z[kdx+idx+1] = (jlong)product;
7418 // jlong carry2 = (jlong)(product >>> 64);
7419 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7420 // z[kdx+idx] = (jlong)product;
7421 // carry = (jlong)(product >>> 64);
7422 // }
7423 // idx += 2;
7424 // if (idx > 0) {
7425 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7426 // z[kdx+idx] = (jlong)product;
7427 // carry = (jlong)(product >>> 64);
7428 // }
7429 //
7430
7431 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7432
7433 movl(jdx, idx);
7434 andl(jdx, 0xFFFFFFFC);
7435 shrl(jdx, 2);
7436
7437 bind(L_third_loop);
7438 subl(jdx, 1);
7439 jcc(Assembler::negative, L_third_loop_exit);
7440 subl(idx, 4);
7441
7442 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7443 movq(carry2, rdx);
7444
7445 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7446 movq(carry, rdx);
7447 jmp(L_third_loop);
7448
7449 bind (L_third_loop_exit);
7450
7451 andl (idx, 0x3);
7452 jcc(Assembler::zero, L_post_third_loop_done);
7453
7454 Label L_check_1;
7455 subl(idx, 2);
7456 jcc(Assembler::negative, L_check_1);
7457
7458 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7459 movq(carry, rdx);
7460
7461 bind (L_check_1);
7462 addl (idx, 0x2);
7463 andl (idx, 0x1);
7464 subl(idx, 1);
7465 jcc(Assembler::negative, L_post_third_loop_done);
7466
7467 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7468 movq(product, x_xstart);
7469 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7470 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7471
7472 add2_with_carry(rdx, product, yz_idx, carry);
7473
7474 movl(Address(z, idx, Address::times_4, 0), product);
7475 shrq(product, 32);
7476
7477 shlq(rdx, 32);
7478 orq(product, rdx);
7479 movq(carry, product);
7480
7481 bind(L_post_third_loop_done);
7482 }
7483
7484 /**
7485 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7486 *
7487 */
7488 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7489 Register carry, Register carry2,
7490 Register idx, Register jdx,
7491 Register yz_idx1, Register yz_idx2,
7492 Register tmp, Register tmp3, Register tmp4) {
7493 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7494
7495 // jlong carry, x[], y[], z[];
7496 // int kdx = ystart+1;
7497 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7498 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7499 // jlong carry2 = (jlong)(tmp3 >>> 64);
7500 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7501 // carry = (jlong)(tmp4 >>> 64);
7502 // z[kdx+idx+1] = (jlong)tmp3;
7503 // z[kdx+idx] = (jlong)tmp4;
7504 // }
7505 // idx += 2;
7506 // if (idx > 0) {
7507 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7508 // z[kdx+idx] = (jlong)yz_idx1;
7509 // carry = (jlong)(yz_idx1 >>> 64);
7510 // }
7511 //
7512
7513 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7514
7515 movl(jdx, idx);
7516 andl(jdx, 0xFFFFFFFC);
7517 shrl(jdx, 2);
7518
7519 bind(L_third_loop);
7520 subl(jdx, 1);
7521 jcc(Assembler::negative, L_third_loop_exit);
7522 subl(idx, 4);
7523
7524 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7525 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7526 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7527 rorxq(yz_idx2, yz_idx2, 32);
7528
7529 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7530 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7531
7532 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7533 rorxq(yz_idx1, yz_idx1, 32);
7534 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7535 rorxq(yz_idx2, yz_idx2, 32);
7536
7537 if (VM_Version::supports_adx()) {
7538 adcxq(tmp3, carry);
7539 adoxq(tmp3, yz_idx1);
7540
7541 adcxq(tmp4, tmp);
7542 adoxq(tmp4, yz_idx2);
7543
7544 movl(carry, 0); // does not affect flags
7545 adcxq(carry2, carry);
7546 adoxq(carry2, carry);
7547 } else {
7548 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7549 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7550 }
7551 movq(carry, carry2);
7552
7553 movl(Address(z, idx, Address::times_4, 12), tmp3);
7554 shrq(tmp3, 32);
7555 movl(Address(z, idx, Address::times_4, 8), tmp3);
7556
7557 movl(Address(z, idx, Address::times_4, 4), tmp4);
7558 shrq(tmp4, 32);
7559 movl(Address(z, idx, Address::times_4, 0), tmp4);
7560
7561 jmp(L_third_loop);
7562
7563 bind (L_third_loop_exit);
7564
7565 andl (idx, 0x3);
7566 jcc(Assembler::zero, L_post_third_loop_done);
7567
7568 Label L_check_1;
7569 subl(idx, 2);
7570 jcc(Assembler::negative, L_check_1);
7571
7572 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7573 rorxq(yz_idx1, yz_idx1, 32);
7574 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7575 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7576 rorxq(yz_idx2, yz_idx2, 32);
7577
7578 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7579
7580 movl(Address(z, idx, Address::times_4, 4), tmp3);
7581 shrq(tmp3, 32);
7582 movl(Address(z, idx, Address::times_4, 0), tmp3);
7583 movq(carry, tmp4);
7584
7585 bind (L_check_1);
7586 addl (idx, 0x2);
7587 andl (idx, 0x1);
7588 subl(idx, 1);
7589 jcc(Assembler::negative, L_post_third_loop_done);
7590 movl(tmp4, Address(y, idx, Address::times_4, 0));
7591 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7592 movl(tmp4, Address(z, idx, Address::times_4, 0));
7593
7594 add2_with_carry(carry2, tmp3, tmp4, carry);
7595
7596 movl(Address(z, idx, Address::times_4, 0), tmp3);
7597 shrq(tmp3, 32);
7598
7599 shlq(carry2, 32);
7600 orq(tmp3, carry2);
7601 movq(carry, tmp3);
7602
7603 bind(L_post_third_loop_done);
7604 }
7605
7606 /**
7607 * Code for BigInteger::multiplyToLen() instrinsic.
7608 *
7609 * rdi: x
7610 * rax: xlen
7611 * rsi: y
7612 * rcx: ylen
7613 * r8: z
7614 * r11: zlen
7615 * r12: tmp1
7616 * r13: tmp2
7617 * r14: tmp3
7618 * r15: tmp4
7619 * rbx: tmp5
7620 *
7621 */
7622 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
7623 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7624 ShortBranchVerifier sbv(this);
7625 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7626
7627 push(tmp1);
7628 push(tmp2);
7629 push(tmp3);
7630 push(tmp4);
7631 push(tmp5);
7632
7633 push(xlen);
7634 push(zlen);
7635
7636 const Register idx = tmp1;
7637 const Register kdx = tmp2;
7638 const Register xstart = tmp3;
7639
7640 const Register y_idx = tmp4;
7641 const Register carry = tmp5;
7642 const Register product = xlen;
7643 const Register x_xstart = zlen; // reuse register
7644
7645 // First Loop.
7646 //
7647 // final static long LONG_MASK = 0xffffffffL;
7648 // int xstart = xlen - 1;
7649 // int ystart = ylen - 1;
7650 // long carry = 0;
7651 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7652 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7653 // z[kdx] = (int)product;
7654 // carry = product >>> 32;
7655 // }
7656 // z[xstart] = (int)carry;
7657 //
7658
7659 movl(idx, ylen); // idx = ylen;
7660 movl(kdx, zlen); // kdx = xlen+ylen;
7661 xorq(carry, carry); // carry = 0;
7662
7663 Label L_done;
7664
7665 movl(xstart, xlen);
7666 decrementl(xstart);
7667 jcc(Assembler::negative, L_done);
7668
7669 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7670
7671 Label L_second_loop;
7672 testl(kdx, kdx);
7673 jcc(Assembler::zero, L_second_loop);
7674
7675 Label L_carry;
7676 subl(kdx, 1);
7677 jcc(Assembler::zero, L_carry);
7678
7679 movl(Address(z, kdx, Address::times_4, 0), carry);
7680 shrq(carry, 32);
7681 subl(kdx, 1);
7682
7683 bind(L_carry);
7684 movl(Address(z, kdx, Address::times_4, 0), carry);
7685
7686 // Second and third (nested) loops.
7687 //
7688 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7689 // carry = 0;
7690 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7691 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7692 // (z[k] & LONG_MASK) + carry;
7693 // z[k] = (int)product;
7694 // carry = product >>> 32;
7695 // }
7696 // z[i] = (int)carry;
7697 // }
7698 //
7699 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7700
7701 const Register jdx = tmp1;
7702
7703 bind(L_second_loop);
7704 xorl(carry, carry); // carry = 0;
7705 movl(jdx, ylen); // j = ystart+1
7706
7707 subl(xstart, 1); // i = xstart-1;
7708 jcc(Assembler::negative, L_done);
7709
7710 push (z);
7711
7712 Label L_last_x;
7713 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7714 subl(xstart, 1); // i = xstart-1;
7715 jcc(Assembler::negative, L_last_x);
7716
7717 if (UseBMI2Instructions) {
7718 movq(rdx, Address(x, xstart, Address::times_4, 0));
7719 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7720 } else {
7721 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7722 rorq(x_xstart, 32); // convert big-endian to little-endian
7723 }
7724
7725 Label L_third_loop_prologue;
7726 bind(L_third_loop_prologue);
7727
7728 push (x);
7729 push (xstart);
7730 push (ylen);
7731
7732
7733 if (UseBMI2Instructions) {
7734 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7735 } else { // !UseBMI2Instructions
7736 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7737 }
7738
7739 pop(ylen);
7740 pop(xlen);
7741 pop(x);
7742 pop(z);
7743
7744 movl(tmp3, xlen);
7745 addl(tmp3, 1);
7746 movl(Address(z, tmp3, Address::times_4, 0), carry);
7747 subl(tmp3, 1);
7748 jccb(Assembler::negative, L_done);
7749
7750 shrq(carry, 32);
7751 movl(Address(z, tmp3, Address::times_4, 0), carry);
7752 jmp(L_second_loop);
7753
7754 // Next infrequent code is moved outside loops.
7755 bind(L_last_x);
7756 if (UseBMI2Instructions) {
7757 movl(rdx, Address(x, 0));
7758 } else {
7759 movl(x_xstart, Address(x, 0));
7760 }
7761 jmp(L_third_loop_prologue);
7762
7763 bind(L_done);
7764
7765 pop(zlen);
7766 pop(xlen);
7767
7768 pop(tmp5);
7769 pop(tmp4);
7770 pop(tmp3);
7771 pop(tmp2);
7772 pop(tmp1);
7773 }
7774
7775 //Helper functions for square_to_len()
7776
7777 /**
7778 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7779 * Preserves x and z and modifies rest of the registers.
7780 */
7781
7782 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7783 // Perform square and right shift by 1
7784 // Handle odd xlen case first, then for even xlen do the following
7785 // jlong carry = 0;
7786 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7787 // huge_128 product = x[j:j+1] * x[j:j+1];
7788 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7789 // z[i+2:i+3] = (jlong)(product >>> 1);
7790 // carry = (jlong)product;
7791 // }
7792
7793 xorq(tmp5, tmp5); // carry
7794 xorq(rdxReg, rdxReg);
7795 xorl(tmp1, tmp1); // index for x
7796 xorl(tmp4, tmp4); // index for z
7797
7798 Label L_first_loop, L_first_loop_exit;
7799
7800 testl(xlen, 1);
7801 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7802
7803 // Square and right shift by 1 the odd element using 32 bit multiply
7804 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7805 imulq(raxReg, raxReg);
7806 shrq(raxReg, 1);
7807 adcq(tmp5, 0);
7808 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7809 incrementl(tmp1);
7810 addl(tmp4, 2);
7811
7812 // Square and right shift by 1 the rest using 64 bit multiply
7813 bind(L_first_loop);
7814 cmpptr(tmp1, xlen);
7815 jccb(Assembler::equal, L_first_loop_exit);
7816
7817 // Square
7818 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7819 rorq(raxReg, 32); // convert big-endian to little-endian
7820 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7821
7822 // Right shift by 1 and save carry
7823 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7824 rcrq(rdxReg, 1);
7825 rcrq(raxReg, 1);
7826 adcq(tmp5, 0);
7827
7828 // Store result in z
7829 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7830 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7831
7832 // Update indices for x and z
7833 addl(tmp1, 2);
7834 addl(tmp4, 4);
7835 jmp(L_first_loop);
7836
7837 bind(L_first_loop_exit);
7838 }
7839
7840
7841 /**
7842 * Perform the following multiply add operation using BMI2 instructions
7843 * carry:sum = sum + op1*op2 + carry
7844 * op2 should be in rdx
7845 * op2 is preserved, all other registers are modified
7846 */
7847 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7848 // assert op2 is rdx
7849 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7850 addq(sum, carry);
7851 adcq(tmp2, 0);
7852 addq(sum, op1);
7853 adcq(tmp2, 0);
7854 movq(carry, tmp2);
7855 }
7856
7857 /**
7858 * Perform the following multiply add operation:
7859 * carry:sum = sum + op1*op2 + carry
7860 * Preserves op1, op2 and modifies rest of registers
7861 */
7862 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7863 // rdx:rax = op1 * op2
7864 movq(raxReg, op2);
7865 mulq(op1);
7866
7867 // rdx:rax = sum + carry + rdx:rax
7868 addq(sum, carry);
7869 adcq(rdxReg, 0);
7870 addq(sum, raxReg);
7871 adcq(rdxReg, 0);
7872
7873 // carry:sum = rdx:sum
7874 movq(carry, rdxReg);
7875 }
7876
7877 /**
7878 * Add 64 bit long carry into z[] with carry propogation.
7879 * Preserves z and carry register values and modifies rest of registers.
7880 *
7881 */
7882 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7883 Label L_fourth_loop, L_fourth_loop_exit;
7884
7885 movl(tmp1, 1);
7886 subl(zlen, 2);
7887 addq(Address(z, zlen, Address::times_4, 0), carry);
7888
7889 bind(L_fourth_loop);
7890 jccb(Assembler::carryClear, L_fourth_loop_exit);
7891 subl(zlen, 2);
7892 jccb(Assembler::negative, L_fourth_loop_exit);
7893 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7894 jmp(L_fourth_loop);
7895 bind(L_fourth_loop_exit);
7896 }
7897
7898 /**
7899 * Shift z[] left by 1 bit.
7900 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7901 *
7902 */
7903 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7904
7905 Label L_fifth_loop, L_fifth_loop_exit;
7906
7907 // Fifth loop
7908 // Perform primitiveLeftShift(z, zlen, 1)
7909
7910 const Register prev_carry = tmp1;
7911 const Register new_carry = tmp4;
7912 const Register value = tmp2;
7913 const Register zidx = tmp3;
7914
7915 // int zidx, carry;
7916 // long value;
7917 // carry = 0;
7918 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7919 // (carry:value) = (z[i] << 1) | carry ;
7920 // z[i] = value;
7921 // }
7922
7923 movl(zidx, zlen);
7924 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7925
7926 bind(L_fifth_loop);
7927 decl(zidx); // Use decl to preserve carry flag
7928 decl(zidx);
7929 jccb(Assembler::negative, L_fifth_loop_exit);
7930
7931 if (UseBMI2Instructions) {
7932 movq(value, Address(z, zidx, Address::times_4, 0));
7933 rclq(value, 1);
7934 rorxq(value, value, 32);
7935 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7936 }
7937 else {
7938 // clear new_carry
7939 xorl(new_carry, new_carry);
7940
7941 // Shift z[i] by 1, or in previous carry and save new carry
7942 movq(value, Address(z, zidx, Address::times_4, 0));
7943 shlq(value, 1);
7944 adcl(new_carry, 0);
7945
7946 orq(value, prev_carry);
7947 rorq(value, 0x20);
7948 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7949
7950 // Set previous carry = new carry
7951 movl(prev_carry, new_carry);
7952 }
7953 jmp(L_fifth_loop);
7954
7955 bind(L_fifth_loop_exit);
7956 }
7957
7958
7959 /**
7960 * Code for BigInteger::squareToLen() intrinsic
7961 *
7962 * rdi: x
7963 * rsi: len
7964 * r8: z
7965 * rcx: zlen
7966 * r12: tmp1
7967 * r13: tmp2
7968 * r14: tmp3
7969 * r15: tmp4
7970 * rbx: tmp5
7971 *
7972 */
7973 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7974
7975 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
7976 push(tmp1);
7977 push(tmp2);
7978 push(tmp3);
7979 push(tmp4);
7980 push(tmp5);
7981
7982 // First loop
7983 // Store the squares, right shifted one bit (i.e., divided by 2).
7984 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7985
7986 // Add in off-diagonal sums.
7987 //
7988 // Second, third (nested) and fourth loops.
7989 // zlen +=2;
7990 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7991 // carry = 0;
7992 // long op2 = x[xidx:xidx+1];
7993 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7994 // k -= 2;
7995 // long op1 = x[j:j+1];
7996 // long sum = z[k:k+1];
7997 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7998 // z[k:k+1] = sum;
7999 // }
8000 // add_one_64(z, k, carry, tmp_regs);
8001 // }
8002
8003 const Register carry = tmp5;
8004 const Register sum = tmp3;
8005 const Register op1 = tmp4;
8006 Register op2 = tmp2;
8007
8008 push(zlen);
8009 push(len);
8010 addl(zlen,2);
8011 bind(L_second_loop);
8012 xorq(carry, carry);
8013 subl(zlen, 4);
8014 subl(len, 2);
8015 push(zlen);
8016 push(len);
8017 cmpl(len, 0);
8018 jccb(Assembler::lessEqual, L_second_loop_exit);
8019
8020 // Multiply an array by one 64 bit long.
8021 if (UseBMI2Instructions) {
8022 op2 = rdxReg;
8023 movq(op2, Address(x, len, Address::times_4, 0));
8024 rorxq(op2, op2, 32);
8025 }
8026 else {
8027 movq(op2, Address(x, len, Address::times_4, 0));
8028 rorq(op2, 32);
8029 }
8030
8031 bind(L_third_loop);
8032 decrementl(len);
8033 jccb(Assembler::negative, L_third_loop_exit);
8034 decrementl(len);
8035 jccb(Assembler::negative, L_last_x);
8036
8037 movq(op1, Address(x, len, Address::times_4, 0));
8038 rorq(op1, 32);
8039
8040 bind(L_multiply);
8041 subl(zlen, 2);
8042 movq(sum, Address(z, zlen, Address::times_4, 0));
8043
8044 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8045 if (UseBMI2Instructions) {
8046 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8047 }
8048 else {
8049 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8050 }
8051
8052 movq(Address(z, zlen, Address::times_4, 0), sum);
8053
8054 jmp(L_third_loop);
8055 bind(L_third_loop_exit);
8056
8057 // Fourth loop
8058 // Add 64 bit long carry into z with carry propogation.
8059 // Uses offsetted zlen.
8060 add_one_64(z, zlen, carry, tmp1);
8061
8062 pop(len);
8063 pop(zlen);
8064 jmp(L_second_loop);
8065
8066 // Next infrequent code is moved outside loops.
8067 bind(L_last_x);
8068 movl(op1, Address(x, 0));
8069 jmp(L_multiply);
8070
8071 bind(L_second_loop_exit);
8072 pop(len);
8073 pop(zlen);
8074 pop(len);
8075 pop(zlen);
8076
8077 // Fifth loop
8078 // Shift z left 1 bit.
8079 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8080
8081 // z[zlen-1] |= x[len-1] & 1;
8082 movl(tmp3, Address(x, len, Address::times_4, -4));
8083 andl(tmp3, 1);
8084 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8085
8086 pop(tmp5);
8087 pop(tmp4);
8088 pop(tmp3);
8089 pop(tmp2);
8090 pop(tmp1);
8091 }
8092
8093 /**
8094 * Helper function for mul_add()
8095 * Multiply the in[] by int k and add to out[] starting at offset offs using
8096 * 128 bit by 32 bit multiply and return the carry in tmp5.
8097 * Only quad int aligned length of in[] is operated on in this function.
8098 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8099 * This function preserves out, in and k registers.
8100 * len and offset point to the appropriate index in "in" & "out" correspondingly
8101 * tmp5 has the carry.
8102 * other registers are temporary and are modified.
8103 *
8104 */
8105 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8106 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8107 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8108
8109 Label L_first_loop, L_first_loop_exit;
8110
8111 movl(tmp1, len);
8112 shrl(tmp1, 2);
8113
8114 bind(L_first_loop);
8115 subl(tmp1, 1);
8116 jccb(Assembler::negative, L_first_loop_exit);
8117
8118 subl(len, 4);
8119 subl(offset, 4);
8120
8121 Register op2 = tmp2;
8122 const Register sum = tmp3;
8123 const Register op1 = tmp4;
8124 const Register carry = tmp5;
8125
8126 if (UseBMI2Instructions) {
8127 op2 = rdxReg;
8128 }
8129
8130 movq(op1, Address(in, len, Address::times_4, 8));
8131 rorq(op1, 32);
8132 movq(sum, Address(out, offset, Address::times_4, 8));
8133 rorq(sum, 32);
8134 if (UseBMI2Instructions) {
8135 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8136 }
8137 else {
8138 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8139 }
8140 // Store back in big endian from little endian
8141 rorq(sum, 0x20);
8142 movq(Address(out, offset, Address::times_4, 8), sum);
8143
8144 movq(op1, Address(in, len, Address::times_4, 0));
8145 rorq(op1, 32);
8146 movq(sum, Address(out, offset, Address::times_4, 0));
8147 rorq(sum, 32);
8148 if (UseBMI2Instructions) {
8149 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8150 }
8151 else {
8152 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8153 }
8154 // Store back in big endian from little endian
8155 rorq(sum, 0x20);
8156 movq(Address(out, offset, Address::times_4, 0), sum);
8157
8158 jmp(L_first_loop);
8159 bind(L_first_loop_exit);
8160 }
8161
8162 /**
8163 * Code for BigInteger::mulAdd() intrinsic
8164 *
8165 * rdi: out
8166 * rsi: in
8167 * r11: offs (out.length - offset)
8168 * rcx: len
8169 * r8: k
8170 * r12: tmp1
8171 * r13: tmp2
8172 * r14: tmp3
8173 * r15: tmp4
8174 * rbx: tmp5
8175 * Multiply the in[] by word k and add to out[], return the carry in rax
8176 */
8177 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8178 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8179 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8180
8181 Label L_carry, L_last_in, L_done;
8182
8183 // carry = 0;
8184 // for (int j=len-1; j >= 0; j--) {
8185 // long product = (in[j] & LONG_MASK) * kLong +
8186 // (out[offs] & LONG_MASK) + carry;
8187 // out[offs--] = (int)product;
8188 // carry = product >>> 32;
8189 // }
8190 //
8191 push(tmp1);
8192 push(tmp2);
8193 push(tmp3);
8194 push(tmp4);
8195 push(tmp5);
8196
8197 Register op2 = tmp2;
8198 const Register sum = tmp3;
8199 const Register op1 = tmp4;
8200 const Register carry = tmp5;
8201
8202 if (UseBMI2Instructions) {
8203 op2 = rdxReg;
8204 movl(op2, k);
8205 }
8206 else {
8207 movl(op2, k);
8208 }
8209
8210 xorq(carry, carry);
8211
8212 //First loop
8213
8214 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8215 //The carry is in tmp5
8216 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8217
8218 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8219 decrementl(len);
8220 jccb(Assembler::negative, L_carry);
8221 decrementl(len);
8222 jccb(Assembler::negative, L_last_in);
8223
8224 movq(op1, Address(in, len, Address::times_4, 0));
8225 rorq(op1, 32);
8226
8227 subl(offs, 2);
8228 movq(sum, Address(out, offs, Address::times_4, 0));
8229 rorq(sum, 32);
8230
8231 if (UseBMI2Instructions) {
8232 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8233 }
8234 else {
8235 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8236 }
8237
8238 // Store back in big endian from little endian
8239 rorq(sum, 0x20);
8240 movq(Address(out, offs, Address::times_4, 0), sum);
8241
8242 testl(len, len);
8243 jccb(Assembler::zero, L_carry);
8244
8245 //Multiply the last in[] entry, if any
8246 bind(L_last_in);
8247 movl(op1, Address(in, 0));
8248 movl(sum, Address(out, offs, Address::times_4, -4));
8249
8250 movl(raxReg, k);
8251 mull(op1); //tmp4 * eax -> edx:eax
8252 addl(sum, carry);
8253 adcl(rdxReg, 0);
8254 addl(sum, raxReg);
8255 adcl(rdxReg, 0);
8256 movl(carry, rdxReg);
8257
8258 movl(Address(out, offs, Address::times_4, -4), sum);
8259
8260 bind(L_carry);
8261 //return tmp5/carry as carry in rax
8262 movl(rax, carry);
8263
8264 bind(L_done);
8265 pop(tmp5);
8266 pop(tmp4);
8267 pop(tmp3);
8268 pop(tmp2);
8269 pop(tmp1);
8270 }
8271 #endif
8272
8273 /**
8274 * Emits code to update CRC-32 with a byte value according to constants in table
8275 *
8276 * @param [in,out]crc Register containing the crc.
8277 * @param [in]val Register containing the byte to fold into the CRC.
8278 * @param [in]table Register containing the table of crc constants.
8279 *
8280 * uint32_t crc;
8281 * val = crc_table[(val ^ crc) & 0xFF];
8282 * crc = val ^ (crc >> 8);
8283 *
8284 */
8285 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8286 xorl(val, crc);
8287 andl(val, 0xFF);
8288 shrl(crc, 8); // unsigned shift
8289 xorl(crc, Address(table, val, Address::times_4, 0));
8290 }
8291
8292 /**
8293 * Fold 128-bit data chunk
8294 */
8295 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8296 if (UseAVX > 0) {
8297 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8298 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8299 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8300 pxor(xcrc, xtmp);
8301 } else {
8302 movdqa(xtmp, xcrc);
8303 pclmulhdq(xtmp, xK); // [123:64]
8304 pclmulldq(xcrc, xK); // [63:0]
8305 pxor(xcrc, xtmp);
8306 movdqu(xtmp, Address(buf, offset));
8307 pxor(xcrc, xtmp);
8308 }
8309 }
8310
8311 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8312 if (UseAVX > 0) {
8313 vpclmulhdq(xtmp, xK, xcrc);
8314 vpclmulldq(xcrc, xK, xcrc);
8315 pxor(xcrc, xbuf);
8316 pxor(xcrc, xtmp);
8317 } else {
8318 movdqa(xtmp, xcrc);
8319 pclmulhdq(xtmp, xK);
8320 pclmulldq(xcrc, xK);
8321 pxor(xcrc, xbuf);
8322 pxor(xcrc, xtmp);
8323 }
8324 }
8325
8326 /**
8327 * 8-bit folds to compute 32-bit CRC
8328 *
8329 * uint64_t xcrc;
8330 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8331 */
8332 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8333 movdl(tmp, xcrc);
8334 andl(tmp, 0xFF);
8335 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8336 psrldq(xcrc, 1); // unsigned shift one byte
8337 pxor(xcrc, xtmp);
8338 }
8339
8340 /**
8341 * uint32_t crc;
8342 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8343 */
8344 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8345 movl(tmp, crc);
8346 andl(tmp, 0xFF);
8347 shrl(crc, 8);
8348 xorl(crc, Address(table, tmp, Address::times_4, 0));
8349 }
8350
8351 /**
8352 * @param crc register containing existing CRC (32-bit)
8353 * @param buf register pointing to input byte buffer (byte*)
8354 * @param len register containing number of bytes
8355 * @param table register that will contain address of CRC table
8356 * @param tmp scratch register
8357 */
8358 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8359 assert_different_registers(crc, buf, len, table, tmp, rax);
8360
8361 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8362 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8363
8364 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8365 notl(crc); // ~crc
8366 cmpl(len, 16);
8367 jcc(Assembler::less, L_tail);
8368
8369 // Align buffer to 16 bytes
8370 movl(tmp, buf);
8371 andl(tmp, 0xF);
8372 jccb(Assembler::zero, L_aligned);
8373 subl(tmp, 16);
8374 addl(len, tmp);
8375
8376 align(4);
8377 BIND(L_align_loop);
8378 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8379 update_byte_crc32(crc, rax, table);
8380 increment(buf);
8381 incrementl(tmp);
8382 jccb(Assembler::less, L_align_loop);
8383
8384 BIND(L_aligned);
8385 movl(tmp, len); // save
8386 shrl(len, 4);
8387 jcc(Assembler::zero, L_tail_restore);
8388
8389 // Fold crc into first bytes of vector
8390 movdqa(xmm1, Address(buf, 0));
8391 movdl(rax, xmm1);
8392 xorl(crc, rax);
8393 pinsrd(xmm1, crc, 0);
8394 addptr(buf, 16);
8395 subl(len, 4); // len > 0
8396 jcc(Assembler::less, L_fold_tail);
8397
8398 movdqa(xmm2, Address(buf, 0));
8399 movdqa(xmm3, Address(buf, 16));
8400 movdqa(xmm4, Address(buf, 32));
8401 addptr(buf, 48);
8402 subl(len, 3);
8403 jcc(Assembler::lessEqual, L_fold_512b);
8404
8405 // Fold total 512 bits of polynomial on each iteration,
8406 // 128 bits per each of 4 parallel streams.
8407 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
8408
8409 align(32);
8410 BIND(L_fold_512b_loop);
8411 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8412 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8413 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8414 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8415 addptr(buf, 64);
8416 subl(len, 4);
8417 jcc(Assembler::greater, L_fold_512b_loop);
8418
8419 // Fold 512 bits to 128 bits.
8420 BIND(L_fold_512b);
8421 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8422 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8423 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8424 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8425
8426 // Fold the rest of 128 bits data chunks
8427 BIND(L_fold_tail);
8428 addl(len, 3);
8429 jccb(Assembler::lessEqual, L_fold_128b);
8430 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8431
8432 BIND(L_fold_tail_loop);
8433 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8434 addptr(buf, 16);
8435 decrementl(len);
8436 jccb(Assembler::greater, L_fold_tail_loop);
8437
8438 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8439 BIND(L_fold_128b);
8440 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
8441 if (UseAVX > 0) {
8442 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8443 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8444 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8445 } else {
8446 movdqa(xmm2, xmm0);
8447 pclmulqdq(xmm2, xmm1, 0x1);
8448 movdqa(xmm3, xmm0);
8449 pand(xmm3, xmm2);
8450 pclmulqdq(xmm0, xmm3, 0x1);
8451 }
8452 psrldq(xmm1, 8);
8453 psrldq(xmm2, 4);
8454 pxor(xmm0, xmm1);
8455 pxor(xmm0, xmm2);
8456
8457 // 8 8-bit folds to compute 32-bit CRC.
8458 for (int j = 0; j < 4; j++) {
8459 fold_8bit_crc32(xmm0, table, xmm1, rax);
8460 }
8461 movdl(crc, xmm0); // mov 32 bits to general register
8462 for (int j = 0; j < 4; j++) {
8463 fold_8bit_crc32(crc, table, rax);
8464 }
8465
8466 BIND(L_tail_restore);
8467 movl(len, tmp); // restore
8468 BIND(L_tail);
8469 andl(len, 0xf);
8470 jccb(Assembler::zero, L_exit);
8471
8472 // Fold the rest of bytes
8473 align(4);
8474 BIND(L_tail_loop);
8475 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8476 update_byte_crc32(crc, rax, table);
8477 increment(buf);
8478 decrementl(len);
8479 jccb(Assembler::greater, L_tail_loop);
8480
8481 BIND(L_exit);
8482 notl(crc); // ~c
8483 }
8484
8485 #undef BIND
8486 #undef BLOCK_COMMENT
8487
8488
8489 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
8490 switch (cond) {
8491 // Note some conditions are synonyms for others
8492 case Assembler::zero: return Assembler::notZero;
8493 case Assembler::notZero: return Assembler::zero;
8494 case Assembler::less: return Assembler::greaterEqual;
8495 case Assembler::lessEqual: return Assembler::greater;
8496 case Assembler::greater: return Assembler::lessEqual;
8497 case Assembler::greaterEqual: return Assembler::less;
8498 case Assembler::below: return Assembler::aboveEqual;
8499 case Assembler::belowEqual: return Assembler::above;
8500 case Assembler::above: return Assembler::belowEqual;
8501 case Assembler::aboveEqual: return Assembler::below;
8502 case Assembler::overflow: return Assembler::noOverflow;
8503 case Assembler::noOverflow: return Assembler::overflow;
8504 case Assembler::negative: return Assembler::positive;
8505 case Assembler::positive: return Assembler::negative;
8506 case Assembler::parity: return Assembler::noParity;
8507 case Assembler::noParity: return Assembler::parity;
8508 }
8509 ShouldNotReachHere(); return Assembler::overflow;
8510 }
8511
8512 SkipIfEqual::SkipIfEqual(
8513 MacroAssembler* masm, const bool* flag_addr, bool value) {
8514 _masm = masm;
8515 _masm->cmp8(ExternalAddress((address)flag_addr), value);
8516 _masm->jcc(Assembler::equal, _label);
8517 }
8518
8519 SkipIfEqual::~SkipIfEqual() {
8520 _masm->bind(_label);
8521 }