1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_InstructionPrinter.hpp"
27 #include "c1/c1_LIR.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_ValueStack.hpp"
30 #include "ci/ciInstance.hpp"
31 #include "runtime/sharedRuntime.hpp"
32
33 Register LIR_OprDesc::as_register() const {
34 return FrameMap::cpu_rnr2reg(cpu_regnr());
35 }
36
37 Register LIR_OprDesc::as_register_lo() const {
38 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
39 }
40
41 Register LIR_OprDesc::as_register_hi() const {
42 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
43 }
44
45 #if defined(X86)
46
47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
48 return FrameMap::nr2xmmreg(xmm_regnr());
49 }
50
51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
53 return FrameMap::nr2xmmreg(xmm_regnrLo());
54 }
55
56 #endif // X86
57
58 #if defined(SPARC) || defined(PPC)
59
60 FloatRegister LIR_OprDesc::as_float_reg() const {
61 return FrameMap::nr2floatreg(fpu_regnr());
62 }
63
64 FloatRegister LIR_OprDesc::as_double_reg() const {
65 return FrameMap::nr2floatreg(fpu_regnrHi());
66 }
67
68 #endif
69
70 #if defined(ARM) || defined (AARCH64)
71
72 FloatRegister LIR_OprDesc::as_float_reg() const {
73 return as_FloatRegister(fpu_regnr());
74 }
75
76 FloatRegister LIR_OprDesc::as_double_reg() const {
77 return as_FloatRegister(fpu_regnrLo());
78 }
79
80 #endif
81
82
83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
84
85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
86 ValueTag tag = type->tag();
87 switch (tag) {
88 case metaDataTag : {
89 ClassConstant* c = type->as_ClassConstant();
90 if (c != NULL && !c->value()->is_loaded()) {
91 return LIR_OprFact::metadataConst(NULL);
92 } else if (c != NULL) {
93 return LIR_OprFact::metadataConst(c->value()->constant_encoding());
94 } else {
95 MethodConstant* m = type->as_MethodConstant();
96 assert (m != NULL, "not a class or a method?");
97 return LIR_OprFact::metadataConst(m->value()->constant_encoding());
98 }
99 }
100 case objectTag : {
101 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
102 }
103 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
104 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
105 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
106 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
107 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
108 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
109 }
110 }
111
112
113 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
114 switch (type->tag()) {
115 case objectTag: return LIR_OprFact::oopConst(NULL);
116 case addressTag:return LIR_OprFact::addressConst(0);
117 case intTag: return LIR_OprFact::intConst(0);
118 case floatTag: return LIR_OprFact::floatConst(0.0);
119 case longTag: return LIR_OprFact::longConst(0);
120 case doubleTag: return LIR_OprFact::doubleConst(0.0);
121 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
122 }
123 return illegalOpr;
124 }
125
126
127
128 //---------------------------------------------------
129
130
131 LIR_Address::Scale LIR_Address::scale(BasicType type) {
132 int elem_size = type2aelembytes(type);
133 switch (elem_size) {
134 case 1: return LIR_Address::times_1;
135 case 2: return LIR_Address::times_2;
136 case 4: return LIR_Address::times_4;
137 case 8: return LIR_Address::times_8;
138 }
139 ShouldNotReachHere();
140 return LIR_Address::times_1;
141 }
142
143
144 #ifndef PRODUCT
145 void LIR_Address::verify0() const {
146 #if defined(SPARC) || defined(PPC)
147 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
148 assert(disp() == 0 || index()->is_illegal(), "can't have both");
149 #endif
150 #ifdef _LP64
151 assert(base()->is_cpu_register(), "wrong base operand");
152 #ifndef AARCH64
153 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
154 #else
155 assert(index()->is_illegal() || index()->is_double_cpu() || index()->is_single_cpu(), "wrong index operand");
156 #endif
157 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
158 "wrong type for addresses");
159 #else
160 assert(base()->is_single_cpu(), "wrong base operand");
161 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
162 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
163 "wrong type for addresses");
164 #endif
165 }
166 #endif
167
168
169 //---------------------------------------------------
170
171 char LIR_OprDesc::type_char(BasicType t) {
172 switch (t) {
173 case T_ARRAY:
174 t = T_OBJECT;
175 case T_BOOLEAN:
176 case T_CHAR:
177 case T_FLOAT:
178 case T_DOUBLE:
179 case T_BYTE:
180 case T_SHORT:
181 case T_INT:
182 case T_LONG:
183 case T_OBJECT:
184 case T_ADDRESS:
185 case T_VOID:
186 return ::type2char(t);
187 case T_METADATA:
188 return 'M';
189 case T_ILLEGAL:
190 return '?';
191
192 default:
193 ShouldNotReachHere();
194 return '?';
195 }
196 }
197
198 #ifndef PRODUCT
199 void LIR_OprDesc::validate_type() const {
200
201 #ifdef ASSERT
202 if (!is_pointer() && !is_illegal()) {
203 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
204 switch (as_BasicType(type_field())) {
205 case T_LONG:
206 assert((kindfield == cpu_register || kindfield == stack_value) &&
207 size_field() == double_size, "must match");
208 break;
209 case T_FLOAT:
210 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
211 assert((kindfield == fpu_register || kindfield == stack_value
212 ARM_ONLY(|| kindfield == cpu_register)
213 PPC_ONLY(|| kindfield == cpu_register) ) &&
214 size_field() == single_size, "must match");
215 break;
216 case T_DOUBLE:
217 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
218 assert((kindfield == fpu_register || kindfield == stack_value
219 ARM_ONLY(|| kindfield == cpu_register)
220 PPC_ONLY(|| kindfield == cpu_register) ) &&
221 size_field() == double_size, "must match");
222 break;
223 case T_BOOLEAN:
224 case T_CHAR:
225 case T_BYTE:
226 case T_SHORT:
227 case T_INT:
228 case T_ADDRESS:
229 case T_OBJECT:
230 case T_METADATA:
231 case T_ARRAY:
232 assert((kindfield == cpu_register || kindfield == stack_value) &&
233 size_field() == single_size, "must match");
234 break;
235
236 case T_ILLEGAL:
237 // XXX TKR also means unknown right now
238 // assert(is_illegal(), "must match");
239 break;
240
241 default:
242 ShouldNotReachHere();
243 }
244 }
245 #endif
246
247 }
248 #endif // PRODUCT
249
250
251 bool LIR_OprDesc::is_oop() const {
252 if (is_pointer()) {
253 return pointer()->is_oop_pointer();
254 } else {
255 OprType t= type_field();
256 assert(t != unknown_type, "not set");
257 return t == object_type;
258 }
259 }
260
261
262
263 void LIR_Op2::verify() const {
264 #ifdef ASSERT
265 switch (code()) {
266 case lir_cmove:
267 case lir_xchg:
268 break;
269
270 default:
271 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
272 "can't produce oops from arith");
273 }
274
275 if (TwoOperandLIRForm) {
276 switch (code()) {
277 case lir_add:
278 case lir_sub:
279 case lir_mul:
280 case lir_mul_strictfp:
281 case lir_div:
282 case lir_div_strictfp:
283 case lir_rem:
284 case lir_logic_and:
285 case lir_logic_or:
286 case lir_logic_xor:
287 case lir_shl:
288 case lir_shr:
289 assert(in_opr1() == result_opr(), "opr1 and result must match");
290 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
291 break;
292
293 // special handling for lir_ushr because of write barriers
294 case lir_ushr:
295 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
296 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
297 break;
298
299 }
300 }
301 #endif
302 }
303
304
305 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
306 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
307 , _cond(cond)
308 , _type(type)
309 , _label(block->label())
310 , _block(block)
311 , _ublock(NULL)
312 , _stub(NULL) {
313 }
314
315 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
316 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
317 , _cond(cond)
318 , _type(type)
319 , _label(stub->entry())
320 , _block(NULL)
321 , _ublock(NULL)
322 , _stub(stub) {
323 }
324
325 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
326 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
327 , _cond(cond)
328 , _type(type)
329 , _label(block->label())
330 , _block(block)
331 , _ublock(ublock)
332 , _stub(NULL)
333 {
334 }
335
336 void LIR_OpBranch::change_block(BlockBegin* b) {
337 assert(_block != NULL, "must have old block");
338 assert(_block->label() == label(), "must be equal");
339
340 _block = b;
341 _label = b->label();
342 }
343
344 void LIR_OpBranch::change_ublock(BlockBegin* b) {
345 assert(_ublock != NULL, "must have old block");
346 _ublock = b;
347 }
348
349 void LIR_OpBranch::negate_cond() {
350 switch (_cond) {
351 case lir_cond_equal: _cond = lir_cond_notEqual; break;
352 case lir_cond_notEqual: _cond = lir_cond_equal; break;
353 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
354 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
355 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
356 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
357 default: ShouldNotReachHere();
358 }
359 }
360
361
362 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
363 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
364 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
365 CodeStub* stub)
366
367 : LIR_Op(code, result, NULL)
368 , _object(object)
369 , _array(LIR_OprFact::illegalOpr)
370 , _klass(klass)
371 , _tmp1(tmp1)
372 , _tmp2(tmp2)
373 , _tmp3(tmp3)
374 , _fast_check(fast_check)
375 , _stub(stub)
376 , _info_for_patch(info_for_patch)
377 , _info_for_exception(info_for_exception)
378 , _profiled_method(NULL)
379 , _profiled_bci(-1)
380 , _should_profile(false)
381 {
382 if (code == lir_checkcast) {
383 assert(info_for_exception != NULL, "checkcast throws exceptions");
384 } else if (code == lir_instanceof) {
385 assert(info_for_exception == NULL, "instanceof throws no exceptions");
386 } else {
387 ShouldNotReachHere();
388 }
389 }
390
391
392
393 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
394 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
395 , _object(object)
396 , _array(array)
397 , _klass(NULL)
398 , _tmp1(tmp1)
399 , _tmp2(tmp2)
400 , _tmp3(tmp3)
401 , _fast_check(false)
402 , _stub(NULL)
403 , _info_for_patch(NULL)
404 , _info_for_exception(info_for_exception)
405 , _profiled_method(NULL)
406 , _profiled_bci(-1)
407 , _should_profile(false)
408 {
409 if (code == lir_store_check) {
410 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
411 assert(info_for_exception != NULL, "store_check throws exceptions");
412 } else {
413 ShouldNotReachHere();
414 }
415 }
416
417
418 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
419 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
420 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
421 , _tmp(tmp)
422 , _src(src)
423 , _src_pos(src_pos)
424 , _dst(dst)
425 , _dst_pos(dst_pos)
426 , _flags(flags)
427 , _expected_type(expected_type)
428 , _length(length) {
429 _stub = new ArrayCopyStub(this);
430 }
431
432 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
433 : LIR_Op(lir_updatecrc32, res, NULL)
434 , _crc(crc)
435 , _val(val) {
436 }
437
438 //-------------------verify--------------------------
439
440 void LIR_Op1::verify() const {
441 switch(code()) {
442 case lir_move:
443 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
444 break;
445 case lir_null_check:
446 assert(in_opr()->is_register(), "must be");
447 break;
448 case lir_return:
449 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
450 break;
451 }
452 }
453
454 void LIR_OpRTCall::verify() const {
455 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
456 }
457
458 //-------------------visits--------------------------
459
460 // complete rework of LIR instruction visitor.
461 // The virtual call for each instruction type is replaced by a big
462 // switch that adds the operands for each instruction
463
464 void LIR_OpVisitState::visit(LIR_Op* op) {
465 // copy information from the LIR_Op
466 reset();
467 set_op(op);
468
469 switch (op->code()) {
470
471 // LIR_Op0
472 case lir_word_align: // result and info always invalid
473 case lir_backwardbranch_target: // result and info always invalid
474 case lir_build_frame: // result and info always invalid
475 case lir_fpop_raw: // result and info always invalid
476 case lir_24bit_FPU: // result and info always invalid
477 case lir_reset_FPU: // result and info always invalid
478 case lir_breakpoint: // result and info always invalid
479 case lir_membar: // result and info always invalid
480 case lir_membar_acquire: // result and info always invalid
481 case lir_membar_release: // result and info always invalid
482 case lir_membar_loadload: // result and info always invalid
483 case lir_membar_storestore: // result and info always invalid
484 case lir_membar_loadstore: // result and info always invalid
485 case lir_membar_storeload: // result and info always invalid
486 {
487 assert(op->as_Op0() != NULL, "must be");
488 assert(op->_info == NULL, "info not used by this instruction");
489 assert(op->_result->is_illegal(), "not used");
490 break;
491 }
492
493 case lir_nop: // may have info, result always invalid
494 case lir_std_entry: // may have result, info always invalid
495 case lir_osr_entry: // may have result, info always invalid
496 case lir_get_thread: // may have result, info always invalid
497 {
498 assert(op->as_Op0() != NULL, "must be");
499 if (op->_info != NULL) do_info(op->_info);
500 if (op->_result->is_valid()) do_output(op->_result);
501 break;
502 }
503
504
505 // LIR_OpLabel
506 case lir_label: // result and info always invalid
507 {
508 assert(op->as_OpLabel() != NULL, "must be");
509 assert(op->_info == NULL, "info not used by this instruction");
510 assert(op->_result->is_illegal(), "not used");
511 break;
512 }
513
514
515 // LIR_Op1
516 case lir_fxch: // input always valid, result and info always invalid
517 case lir_fld: // input always valid, result and info always invalid
518 case lir_ffree: // input always valid, result and info always invalid
519 case lir_push: // input always valid, result and info always invalid
520 case lir_pop: // input always valid, result and info always invalid
521 case lir_leal: // input and result always valid, info always invalid
522 case lir_neg: // input and result always valid, info always invalid
523 case lir_monaddr: // input and result always valid, info always invalid
524 case lir_null_check: // input and info always valid, result always invalid
525 case lir_move: // input and result always valid, may have info
526 case lir_pack64: // input and result always valid
527 case lir_unpack64: // input and result always valid
528 {
529 assert(op->as_Op1() != NULL, "must be");
530 LIR_Op1* op1 = (LIR_Op1*)op;
531
532 if (op1->_info) do_info(op1->_info);
533 if (op1->_opr->is_valid()) do_input(op1->_opr);
534 if (op1->_result->is_valid()) do_output(op1->_result);
535
536 break;
537 }
538
539 case lir_return: // input always valid, result and info always invalid
540 {
541 assert(op->as_Op1Safepoint() != NULL, "must be");
542 LIR_Op1Safepoint* op_ret = (LIR_Op1Safepoint*)op;
543
544 if (op_ret->_info) do_info(op_ret->_info);
545 if (op_ret->_opr->is_valid()) do_input(op_ret->_opr);
546 if (op_ret->_result->is_valid()) do_output(op_ret->_result);
547
548 if (op_ret->tls_stub() != NULL) do_stub(op_ret->tls_stub());
549
550 break;
551 }
552
553 case lir_safepoint:
554 {
555 assert(op->as_Op1Safepoint() != NULL, "must be");
556 LIR_Op1Safepoint* op1 = (LIR_Op1Safepoint*)op;
557
558 assert(op1->_info != NULL, ""); do_info(op1->_info);
559 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
560 assert(op1->_result->is_illegal(), "safepoint does not produce value");
561
562 if (op1->tls_stub() != NULL) do_stub(op1->tls_stub());
563
564 break;
565 }
566
567 // LIR_OpConvert;
568 case lir_convert: // input and result always valid, info always invalid
569 {
570 assert(op->as_OpConvert() != NULL, "must be");
571 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
572
573 assert(opConvert->_info == NULL, "must be");
574 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
575 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
576 #ifdef PPC
577 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
578 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
579 #endif
580 do_stub(opConvert->_stub);
581
582 break;
583 }
584
585 // LIR_OpBranch;
586 case lir_branch: // may have info, input and result register always invalid
587 case lir_cond_float_branch: // may have info, input and result register always invalid
588 {
589 assert(op->as_OpBranch() != NULL, "must be");
590 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
591
592 if (opBranch->_info != NULL) do_info(opBranch->_info);
593 assert(opBranch->_result->is_illegal(), "not used");
594 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
595
596 break;
597 }
598
599
600 // LIR_OpAllocObj
601 case lir_alloc_object:
602 {
603 assert(op->as_OpAllocObj() != NULL, "must be");
604 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
605
606 if (opAllocObj->_info) do_info(opAllocObj->_info);
607 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
608 do_temp(opAllocObj->_opr);
609 }
610 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
611 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
612 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
613 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
614 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
615 do_stub(opAllocObj->_stub);
616 break;
617 }
618
619
620 // LIR_OpRoundFP;
621 case lir_roundfp: {
622 assert(op->as_OpRoundFP() != NULL, "must be");
623 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
624
625 assert(op->_info == NULL, "info not used by this instruction");
626 assert(opRoundFP->_tmp->is_illegal(), "not used");
627 do_input(opRoundFP->_opr);
628 do_output(opRoundFP->_result);
629
630 break;
631 }
632
633
634 // LIR_Op2
635 case lir_cmp:
636 case lir_cmp_l2i:
637 case lir_ucmp_fd2i:
638 case lir_cmp_fd2i:
639 case lir_add:
640 case lir_sub:
641 case lir_mul:
642 case lir_div:
643 case lir_rem:
644 case lir_sqrt:
645 case lir_abs:
646 case lir_logic_and:
647 case lir_logic_or:
648 case lir_logic_xor:
649 case lir_shl:
650 case lir_shr:
651 case lir_ushr:
652 case lir_xadd:
653 case lir_xchg:
654 case lir_assert:
655 {
656 assert(op->as_Op2() != NULL, "must be");
657 LIR_Op2* op2 = (LIR_Op2*)op;
658 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
659 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
660
661 if (op2->_info) do_info(op2->_info);
662 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
663 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
664 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
665 if (op2->_result->is_valid()) do_output(op2->_result);
666 if (op->code() == lir_xchg || op->code() == lir_xadd) {
667 // on ARM and PPC, return value is loaded first so could
668 // destroy inputs. On other platforms that implement those
669 // (x86, sparc), the extra constrainsts are harmless.
670 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
671 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
672 }
673
674 break;
675 }
676
677 // special handling for cmove: right input operand must not be equal
678 // to the result operand, otherwise the backend fails
679 case lir_cmove:
680 {
681 assert(op->as_Op2() != NULL, "must be");
682 LIR_Op2* op2 = (LIR_Op2*)op;
683
684 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
685 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
686 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
687
688 do_input(op2->_opr1);
689 do_input(op2->_opr2);
690 do_temp(op2->_opr2);
691 do_output(op2->_result);
692
693 break;
694 }
695
696 // vspecial handling for strict operations: register input operands
697 // as temp to guarantee that they do not overlap with other
698 // registers
699 case lir_mul_strictfp:
700 case lir_div_strictfp:
701 {
702 assert(op->as_Op2() != NULL, "must be");
703 LIR_Op2* op2 = (LIR_Op2*)op;
704
705 assert(op2->_info == NULL, "not used");
706 assert(op2->_opr1->is_valid(), "used");
707 assert(op2->_opr2->is_valid(), "used");
708 assert(op2->_result->is_valid(), "used");
709 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
710 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
711
712 do_input(op2->_opr1); do_temp(op2->_opr1);
713 do_input(op2->_opr2); do_temp(op2->_opr2);
714 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
715 do_output(op2->_result);
716
717 break;
718 }
719
720 case lir_throw: {
721 assert(op->as_Op2() != NULL, "must be");
722 LIR_Op2* op2 = (LIR_Op2*)op;
723
724 if (op2->_info) do_info(op2->_info);
725 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
726 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
727 assert(op2->_result->is_illegal(), "no result");
728 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
729 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
730
731 break;
732 }
733
734 case lir_unwind: {
735 assert(op->as_Op1() != NULL, "must be");
736 LIR_Op1* op1 = (LIR_Op1*)op;
737
738 assert(op1->_info == NULL, "no info");
739 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
740 assert(op1->_result->is_illegal(), "no result");
741
742 break;
743 }
744
745
746 case lir_tan:
747 case lir_sin:
748 case lir_cos:
749 case lir_log:
750 case lir_log10:
751 case lir_exp: {
752 assert(op->as_Op2() != NULL, "must be");
753 LIR_Op2* op2 = (LIR_Op2*)op;
754
755 // On x86 tan/sin/cos need two temporary fpu stack slots and
756 // log/log10 need one so handle opr2 and tmp as temp inputs.
757 // Register input operand as temp to guarantee that it doesn't
758 // overlap with the input.
759 assert(op2->_info == NULL, "not used");
760 assert(op2->_tmp5->is_illegal(), "not used");
761 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used");
762 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used");
763 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used");
764 assert(op2->_opr1->is_valid(), "used");
765 do_input(op2->_opr1); do_temp(op2->_opr1);
766
767 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
768 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
769 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2);
770 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3);
771 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4);
772 if (op2->_result->is_valid()) do_output(op2->_result);
773
774 break;
775 }
776
777 case lir_pow: {
778 assert(op->as_Op2() != NULL, "must be");
779 LIR_Op2* op2 = (LIR_Op2*)op;
780
781 // On x86 pow needs two temporary fpu stack slots: tmp1 and
782 // tmp2. Register input operands as temps to guarantee that it
783 // doesn't overlap with the temporary slots.
784 assert(op2->_info == NULL, "not used");
785 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used");
786 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid()
787 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used");
788 assert(op2->_result->is_valid(), "used");
789
790 do_input(op2->_opr1); do_temp(op2->_opr1);
791 do_input(op2->_opr2); do_temp(op2->_opr2);
792 do_temp(op2->_tmp1);
793 do_temp(op2->_tmp2);
794 do_temp(op2->_tmp3);
795 do_temp(op2->_tmp4);
796 do_temp(op2->_tmp5);
797 do_output(op2->_result);
798
799 break;
800 }
801
802 // LIR_Op3
803 case lir_idiv:
804 case lir_irem: {
805 assert(op->as_Op3() != NULL, "must be");
806 LIR_Op3* op3= (LIR_Op3*)op;
807
808 if (op3->_info) do_info(op3->_info);
809 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
810
811 // second operand is input and temp, so ensure that second operand
812 // and third operand get not the same register
813 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
814 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
815 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
816
817 if (op3->_result->is_valid()) do_output(op3->_result);
818
819 break;
820 }
821
822
823 // LIR_OpJavaCall
824 case lir_static_call:
825 case lir_optvirtual_call:
826 case lir_icvirtual_call:
827 case lir_virtual_call:
828 case lir_dynamic_call: {
829 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
830 assert(opJavaCall != NULL, "must be");
831
832 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
833
834 // only visit register parameters
835 int n = opJavaCall->_arguments->length();
836 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
837 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
838 do_input(*opJavaCall->_arguments->adr_at(i));
839 }
840 }
841
842 if (opJavaCall->_info) do_info(opJavaCall->_info);
843 if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr &&
844 opJavaCall->is_method_handle_invoke()) {
845 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
846 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
847 }
848 do_call();
849 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
850
851 break;
852 }
853
854
855 // LIR_OpRTCall
856 case lir_rtcall: {
857 assert(op->as_OpRTCall() != NULL, "must be");
858 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
859
860 // only visit register parameters
861 int n = opRTCall->_arguments->length();
862 for (int i = 0; i < n; i++) {
863 if (!opRTCall->_arguments->at(i)->is_pointer()) {
864 do_input(*opRTCall->_arguments->adr_at(i));
865 }
866 }
867 if (opRTCall->_info) do_info(opRTCall->_info);
868 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
869 do_call();
870 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
871
872 break;
873 }
874
875
876 // LIR_OpArrayCopy
877 case lir_arraycopy: {
878 assert(op->as_OpArrayCopy() != NULL, "must be");
879 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
880
881 assert(opArrayCopy->_result->is_illegal(), "unused");
882 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
883 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
884 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
885 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
886 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
887 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
888 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
889
890 // the implementation of arraycopy always has a call into the runtime
891 do_call();
892
893 break;
894 }
895
896
897 // LIR_OpUpdateCRC32
898 case lir_updatecrc32: {
899 assert(op->as_OpUpdateCRC32() != NULL, "must be");
900 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
901
902 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc);
903 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val);
904 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result);
905 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
906
907 break;
908 }
909
910
911 // LIR_OpLock
912 case lir_lock:
913 case lir_unlock: {
914 assert(op->as_OpLock() != NULL, "must be");
915 LIR_OpLock* opLock = (LIR_OpLock*)op;
916
917 if (opLock->_info) do_info(opLock->_info);
918
919 // TODO: check if these operands really have to be temp
920 // (or if input is sufficient). This may have influence on the oop map!
921 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
922 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
923 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
924
925 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
926 assert(opLock->_result->is_illegal(), "unused");
927
928 do_stub(opLock->_stub);
929
930 break;
931 }
932
933
934 // LIR_OpDelay
935 case lir_delay_slot: {
936 assert(op->as_OpDelay() != NULL, "must be");
937 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
938
939 visit(opDelay->delay_op());
940 break;
941 }
942
943 // LIR_OpTypeCheck
944 case lir_instanceof:
945 case lir_checkcast:
946 case lir_store_check: {
947 assert(op->as_OpTypeCheck() != NULL, "must be");
948 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
949
950 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
951 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
952 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
953 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
954 do_temp(opTypeCheck->_object);
955 }
956 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
957 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
958 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
959 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
960 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
961 do_stub(opTypeCheck->_stub);
962 break;
963 }
964
965 // LIR_OpCompareAndSwap
966 case lir_cas_long:
967 case lir_cas_obj:
968 case lir_cas_int: {
969 assert(op->as_OpCompareAndSwap() != NULL, "must be");
970 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
971
972 assert(opCompareAndSwap->_addr->is_valid(), "used");
973 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
974 assert(opCompareAndSwap->_new_value->is_valid(), "used");
975 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
976 do_input(opCompareAndSwap->_addr);
977 do_temp(opCompareAndSwap->_addr);
978 do_input(opCompareAndSwap->_cmp_value);
979 do_temp(opCompareAndSwap->_cmp_value);
980 do_input(opCompareAndSwap->_new_value);
981 do_temp(opCompareAndSwap->_new_value);
982 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
983 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
984 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
985
986 break;
987 }
988
989
990 // LIR_OpAllocArray;
991 case lir_alloc_array: {
992 assert(op->as_OpAllocArray() != NULL, "must be");
993 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
994
995 if (opAllocArray->_info) do_info(opAllocArray->_info);
996 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
997 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
998 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
999 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
1000 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
1001 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
1002 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
1003 do_stub(opAllocArray->_stub);
1004 break;
1005 }
1006
1007 // LIR_OpProfileCall:
1008 case lir_profile_call: {
1009 assert(op->as_OpProfileCall() != NULL, "must be");
1010 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
1011
1012 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
1013 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
1014 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
1015 break;
1016 }
1017
1018 // LIR_OpProfileType:
1019 case lir_profile_type: {
1020 assert(op->as_OpProfileType() != NULL, "must be");
1021 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
1022
1023 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
1024 do_input(opProfileType->_obj);
1025 do_temp(opProfileType->_tmp);
1026 break;
1027 }
1028 default:
1029 ShouldNotReachHere();
1030 }
1031 }
1032
1033
1034 void LIR_OpVisitState::do_stub(CodeStub* stub) {
1035 if (stub != NULL) {
1036 stub->visit(this);
1037 }
1038 }
1039
1040 XHandlers* LIR_OpVisitState::all_xhandler() {
1041 XHandlers* result = NULL;
1042
1043 int i;
1044 for (i = 0; i < info_count(); i++) {
1045 if (info_at(i)->exception_handlers() != NULL) {
1046 result = info_at(i)->exception_handlers();
1047 break;
1048 }
1049 }
1050
1051 #ifdef ASSERT
1052 for (i = 0; i < info_count(); i++) {
1053 assert(info_at(i)->exception_handlers() == NULL ||
1054 info_at(i)->exception_handlers() == result,
1055 "only one xhandler list allowed per LIR-operation");
1056 }
1057 #endif
1058
1059 if (result != NULL) {
1060 return result;
1061 } else {
1062 return new XHandlers();
1063 }
1064
1065 return result;
1066 }
1067
1068
1069 #ifdef ASSERT
1070 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1071 visit(op);
1072
1073 return opr_count(inputMode) == 0 &&
1074 opr_count(outputMode) == 0 &&
1075 opr_count(tempMode) == 0 &&
1076 info_count() == 0 &&
1077 !has_call() &&
1078 !has_slow_case();
1079 }
1080 #endif
1081
1082 //---------------------------------------------------
1083
1084
1085 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1086 masm->emit_call(this);
1087 }
1088
1089 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1090 masm->emit_rtcall(this);
1091 }
1092
1093 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1094 masm->emit_opLabel(this);
1095 }
1096
1097 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1098 masm->emit_arraycopy(this);
1099 masm->append_code_stub(stub());
1100 }
1101
1102 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1103 masm->emit_updatecrc32(this);
1104 }
1105
1106 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1107 masm->emit_op0(this);
1108 }
1109
1110 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1111 masm->emit_op1(this);
1112 }
1113
1114 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1115 masm->emit_alloc_obj(this);
1116 masm->append_code_stub(stub());
1117 }
1118
1119 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1120 masm->emit_opBranch(this);
1121 if (stub()) {
1122 masm->append_code_stub(stub());
1123 }
1124 }
1125
1126 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1127 masm->emit_opConvert(this);
1128 if (stub() != NULL) {
1129 masm->append_code_stub(stub());
1130 }
1131 }
1132
1133 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1134 masm->emit_op2(this);
1135 }
1136
1137 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1138 masm->emit_alloc_array(this);
1139 masm->append_code_stub(stub());
1140 }
1141
1142 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1143 masm->emit_opTypeCheck(this);
1144 if (stub()) {
1145 masm->append_code_stub(stub());
1146 }
1147 }
1148
1149 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1150 masm->emit_compare_and_swap(this);
1151 }
1152
1153 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1154 masm->emit_op3(this);
1155 }
1156
1157 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1158 masm->emit_lock(this);
1159 if (stub()) {
1160 masm->append_code_stub(stub());
1161 }
1162 }
1163
1164 #ifdef ASSERT
1165 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1166 masm->emit_assert(this);
1167 }
1168 #endif
1169
1170 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1171 masm->emit_delay(this);
1172 }
1173
1174 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1175 masm->emit_profile_call(this);
1176 }
1177
1178 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1179 masm->emit_profile_type(this);
1180 }
1181
1182 // LIR_List
1183 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1184 : _operations(8)
1185 , _compilation(compilation)
1186 #ifndef PRODUCT
1187 , _block(block)
1188 #endif
1189 #ifdef ASSERT
1190 , _file(NULL)
1191 , _line(0)
1192 #endif
1193 { }
1194
1195
1196 #ifdef ASSERT
1197 void LIR_List::set_file_and_line(const char * file, int line) {
1198 const char * f = strrchr(file, '/');
1199 if (f == NULL) f = strrchr(file, '\\');
1200 if (f == NULL) {
1201 f = file;
1202 } else {
1203 f++;
1204 }
1205 _file = f;
1206 _line = line;
1207 }
1208 #endif
1209
1210
1211 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1212 assert(this == buffer->lir_list(), "wrong lir list");
1213 const int n = _operations.length();
1214
1215 if (buffer->number_of_ops() > 0) {
1216 // increase size of instructions list
1217 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1218 // insert ops from buffer into instructions list
1219 int op_index = buffer->number_of_ops() - 1;
1220 int ip_index = buffer->number_of_insertion_points() - 1;
1221 int from_index = n - 1;
1222 int to_index = _operations.length() - 1;
1223 for (; ip_index >= 0; ip_index --) {
1224 int index = buffer->index_at(ip_index);
1225 // make room after insertion point
1226 while (index < from_index) {
1227 _operations.at_put(to_index --, _operations.at(from_index --));
1228 }
1229 // insert ops from buffer
1230 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1231 _operations.at_put(to_index --, buffer->op_at(op_index --));
1232 }
1233 }
1234 }
1235
1236 buffer->finish();
1237 }
1238
1239
1240 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1241 assert(reg->type() == T_OBJECT, "bad reg");
1242 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1243 }
1244
1245 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1246 assert(reg->type() == T_METADATA, "bad reg");
1247 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1248 }
1249
1250 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1251 append(new LIR_Op1(
1252 lir_move,
1253 LIR_OprFact::address(addr),
1254 src,
1255 addr->type(),
1256 patch_code,
1257 info));
1258 }
1259
1260
1261 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1262 append(new LIR_Op1(
1263 lir_move,
1264 LIR_OprFact::address(address),
1265 dst,
1266 address->type(),
1267 patch_code,
1268 info, lir_move_volatile));
1269 }
1270
1271 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1272 append(new LIR_Op1(
1273 lir_move,
1274 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1275 dst,
1276 type,
1277 patch_code,
1278 info, lir_move_volatile));
1279 }
1280
1281
1282 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1283 append(new LIR_Op1(
1284 lir_move,
1285 LIR_OprFact::intConst(v),
1286 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1287 type,
1288 patch_code,
1289 info));
1290 }
1291
1292
1293 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1294 append(new LIR_Op1(
1295 lir_move,
1296 LIR_OprFact::oopConst(o),
1297 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1298 type,
1299 patch_code,
1300 info));
1301 }
1302
1303
1304 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1305 append(new LIR_Op1(
1306 lir_move,
1307 src,
1308 LIR_OprFact::address(addr),
1309 addr->type(),
1310 patch_code,
1311 info));
1312 }
1313
1314
1315 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1316 append(new LIR_Op1(
1317 lir_move,
1318 src,
1319 LIR_OprFact::address(addr),
1320 addr->type(),
1321 patch_code,
1322 info,
1323 lir_move_volatile));
1324 }
1325
1326 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1327 append(new LIR_Op1(
1328 lir_move,
1329 src,
1330 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1331 type,
1332 patch_code,
1333 info, lir_move_volatile));
1334 }
1335
1336
1337 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1338 append(new LIR_Op3(
1339 lir_idiv,
1340 left,
1341 right,
1342 tmp,
1343 res,
1344 info));
1345 }
1346
1347
1348 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1349 append(new LIR_Op3(
1350 lir_idiv,
1351 left,
1352 LIR_OprFact::intConst(right),
1353 tmp,
1354 res,
1355 info));
1356 }
1357
1358
1359 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1360 append(new LIR_Op3(
1361 lir_irem,
1362 left,
1363 right,
1364 tmp,
1365 res,
1366 info));
1367 }
1368
1369
1370 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1371 append(new LIR_Op3(
1372 lir_irem,
1373 left,
1374 LIR_OprFact::intConst(right),
1375 tmp,
1376 res,
1377 info));
1378 }
1379
1380
1381 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1382 append(new LIR_Op2(
1383 lir_cmp,
1384 condition,
1385 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1386 LIR_OprFact::intConst(c),
1387 info));
1388 }
1389
1390
1391 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1392 append(new LIR_Op2(
1393 lir_cmp,
1394 condition,
1395 reg,
1396 LIR_OprFact::address(addr),
1397 info));
1398 }
1399
1400 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1401 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1402 append(new LIR_OpAllocObj(
1403 klass,
1404 dst,
1405 t1,
1406 t2,
1407 t3,
1408 t4,
1409 header_size,
1410 object_size,
1411 init_check,
1412 stub));
1413 }
1414
1415 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1416 append(new LIR_OpAllocArray(
1417 klass,
1418 len,
1419 dst,
1420 t1,
1421 t2,
1422 t3,
1423 t4,
1424 type,
1425 stub));
1426 }
1427
1428 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1429 append(new LIR_Op2(
1430 lir_shl,
1431 value,
1432 count,
1433 dst,
1434 tmp));
1435 }
1436
1437 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1438 append(new LIR_Op2(
1439 lir_shr,
1440 value,
1441 count,
1442 dst,
1443 tmp));
1444 }
1445
1446
1447 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1448 append(new LIR_Op2(
1449 lir_ushr,
1450 value,
1451 count,
1452 dst,
1453 tmp));
1454 }
1455
1456 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1457 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1458 left,
1459 right,
1460 dst));
1461 }
1462
1463 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1464 append(new LIR_OpLock(
1465 lir_lock,
1466 hdr,
1467 obj,
1468 lock,
1469 scratch,
1470 stub,
1471 info));
1472 }
1473
1474 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1475 append(new LIR_OpLock(
1476 lir_unlock,
1477 hdr,
1478 obj,
1479 lock,
1480 scratch,
1481 stub,
1482 NULL));
1483 }
1484
1485
1486 void check_LIR() {
1487 // cannot do the proper checking as PRODUCT and other modes return different results
1488 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1489 }
1490
1491
1492
1493 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1494 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1495 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1496 ciMethod* profiled_method, int profiled_bci) {
1497 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1498 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1499 if (profiled_method != NULL) {
1500 c->set_profiled_method(profiled_method);
1501 c->set_profiled_bci(profiled_bci);
1502 c->set_should_profile(true);
1503 }
1504 append(c);
1505 }
1506
1507 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1508 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1509 if (profiled_method != NULL) {
1510 c->set_profiled_method(profiled_method);
1511 c->set_profiled_bci(profiled_bci);
1512 c->set_should_profile(true);
1513 }
1514 append(c);
1515 }
1516
1517
1518 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1519 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1520 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1521 if (profiled_method != NULL) {
1522 c->set_profiled_method(profiled_method);
1523 c->set_profiled_bci(profiled_bci);
1524 c->set_should_profile(true);
1525 }
1526 append(c);
1527 }
1528
1529
1530 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1531 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1532 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1533 }
1534
1535 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1536 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1537 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1538 }
1539
1540 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1541 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1542 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1543 }
1544
1545 // LIR_Op1Safepoint
1546 LIR_Op1Safepoint::LIR_Op1Safepoint(LIR_Code code, LIR_Opr opr, CodeEmitInfo* info)
1547 : LIR_Op1(code, opr, info)
1548 , _tls_stub(NULL) {
1549 if (ThreadLocalSafepoints) {
1550 _tls_stub = new C1ThreadLocalSafepoint(code == lir_return);
1551 }
1552 }
1553
1554 #ifdef PRODUCT
1555
1556 void print_LIR(BlockList* blocks) {
1557 }
1558
1559 #else
1560 // LIR_OprDesc
1561 void LIR_OprDesc::print() const {
1562 print(tty);
1563 }
1564
1565 void LIR_OprDesc::print(outputStream* out) const {
1566 if (is_illegal()) {
1567 return;
1568 }
1569
1570 out->print("[");
1571 if (is_pointer()) {
1572 pointer()->print_value_on(out);
1573 } else if (is_single_stack()) {
1574 out->print("stack:%d", single_stack_ix());
1575 } else if (is_double_stack()) {
1576 out->print("dbl_stack:%d",double_stack_ix());
1577 } else if (is_virtual()) {
1578 out->print("R%d", vreg_number());
1579 } else if (is_single_cpu()) {
1580 out->print("%s", as_register()->name());
1581 } else if (is_double_cpu()) {
1582 out->print("%s", as_register_hi()->name());
1583 out->print("%s", as_register_lo()->name());
1584 #if defined(X86)
1585 } else if (is_single_xmm()) {
1586 out->print("%s", as_xmm_float_reg()->name());
1587 } else if (is_double_xmm()) {
1588 out->print("%s", as_xmm_double_reg()->name());
1589 } else if (is_single_fpu()) {
1590 out->print("fpu%d", fpu_regnr());
1591 } else if (is_double_fpu()) {
1592 out->print("fpu%d", fpu_regnrLo());
1593 #elif defined(AARCH64)
1594 } else if (is_single_fpu()) {
1595 out->print("fpu%d", fpu_regnr());
1596 } else if (is_double_fpu()) {
1597 out->print("fpu%d", fpu_regnrLo());
1598 #elif defined(ARM)
1599 } else if (is_single_fpu()) {
1600 out->print("s%d", fpu_regnr());
1601 } else if (is_double_fpu()) {
1602 out->print("d%d", fpu_regnrLo() >> 1);
1603 #else
1604 } else if (is_single_fpu()) {
1605 out->print("%s", as_float_reg()->name());
1606 } else if (is_double_fpu()) {
1607 out->print("%s", as_double_reg()->name());
1608 #endif
1609
1610 } else if (is_illegal()) {
1611 out->print("-");
1612 } else {
1613 out->print("Unknown Operand");
1614 }
1615 if (!is_illegal()) {
1616 out->print("|%c", type_char());
1617 }
1618 if (is_register() && is_last_use()) {
1619 out->print("(last_use)");
1620 }
1621 out->print("]");
1622 }
1623
1624
1625 // LIR_Address
1626 void LIR_Const::print_value_on(outputStream* out) const {
1627 switch (type()) {
1628 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1629 case T_INT: out->print("int:%d", as_jint()); break;
1630 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1631 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1632 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1633 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break;
1634 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break;
1635 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
1636 }
1637 }
1638
1639 // LIR_Address
1640 void LIR_Address::print_value_on(outputStream* out) const {
1641 out->print("Base:"); _base->print(out);
1642 if (!_index->is_illegal()) {
1643 out->print(" Index:"); _index->print(out);
1644 switch (scale()) {
1645 case times_1: break;
1646 case times_2: out->print(" * 2"); break;
1647 case times_4: out->print(" * 4"); break;
1648 case times_8: out->print(" * 8"); break;
1649 }
1650 }
1651 out->print(" Disp: " INTX_FORMAT, _disp);
1652 }
1653
1654 // debug output of block header without InstructionPrinter
1655 // (because phi functions are not necessary for LIR)
1656 static void print_block(BlockBegin* x) {
1657 // print block id
1658 BlockEnd* end = x->end();
1659 tty->print("B%d ", x->block_id());
1660
1661 // print flags
1662 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1663 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1664 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1665 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1666 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1667 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1668 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1669
1670 // print block bci range
1671 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1672
1673 // print predecessors and successors
1674 if (x->number_of_preds() > 0) {
1675 tty->print("preds: ");
1676 for (int i = 0; i < x->number_of_preds(); i ++) {
1677 tty->print("B%d ", x->pred_at(i)->block_id());
1678 }
1679 }
1680
1681 if (x->number_of_sux() > 0) {
1682 tty->print("sux: ");
1683 for (int i = 0; i < x->number_of_sux(); i ++) {
1684 tty->print("B%d ", x->sux_at(i)->block_id());
1685 }
1686 }
1687
1688 // print exception handlers
1689 if (x->number_of_exception_handlers() > 0) {
1690 tty->print("xhandler: ");
1691 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1692 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1693 }
1694 }
1695
1696 tty->cr();
1697 }
1698
1699 void print_LIR(BlockList* blocks) {
1700 tty->print_cr("LIR:");
1701 int i;
1702 for (i = 0; i < blocks->length(); i++) {
1703 BlockBegin* bb = blocks->at(i);
1704 print_block(bb);
1705 tty->print("__id_Instruction___________________________________________"); tty->cr();
1706 bb->lir()->print_instructions();
1707 }
1708 }
1709
1710 void LIR_List::print_instructions() {
1711 for (int i = 0; i < _operations.length(); i++) {
1712 _operations.at(i)->print(); tty->cr();
1713 }
1714 tty->cr();
1715 }
1716
1717 // LIR_Ops printing routines
1718 // LIR_Op
1719 void LIR_Op::print_on(outputStream* out) const {
1720 if (id() != -1 || PrintCFGToFile) {
1721 out->print("%4d ", id());
1722 } else {
1723 out->print(" ");
1724 }
1725 out->print("%s ", name());
1726 print_instr(out);
1727 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1728 #ifdef ASSERT
1729 if (Verbose && _file != NULL) {
1730 out->print(" (%s:%d)", _file, _line);
1731 }
1732 #endif
1733 }
1734
1735 const char * LIR_Op::name() const {
1736 const char* s = NULL;
1737 switch(code()) {
1738 // LIR_Op0
1739 case lir_membar: s = "membar"; break;
1740 case lir_membar_acquire: s = "membar_acquire"; break;
1741 case lir_membar_release: s = "membar_release"; break;
1742 case lir_membar_loadload: s = "membar_loadload"; break;
1743 case lir_membar_storestore: s = "membar_storestore"; break;
1744 case lir_membar_loadstore: s = "membar_loadstore"; break;
1745 case lir_membar_storeload: s = "membar_storeload"; break;
1746 case lir_word_align: s = "word_align"; break;
1747 case lir_label: s = "label"; break;
1748 case lir_nop: s = "nop"; break;
1749 case lir_backwardbranch_target: s = "backbranch"; break;
1750 case lir_std_entry: s = "std_entry"; break;
1751 case lir_osr_entry: s = "osr_entry"; break;
1752 case lir_build_frame: s = "build_frm"; break;
1753 case lir_fpop_raw: s = "fpop_raw"; break;
1754 case lir_24bit_FPU: s = "24bit_FPU"; break;
1755 case lir_reset_FPU: s = "reset_FPU"; break;
1756 case lir_breakpoint: s = "breakpoint"; break;
1757 case lir_get_thread: s = "get_thread"; break;
1758 // LIR_Op1
1759 case lir_fxch: s = "fxch"; break;
1760 case lir_fld: s = "fld"; break;
1761 case lir_ffree: s = "ffree"; break;
1762 case lir_push: s = "push"; break;
1763 case lir_pop: s = "pop"; break;
1764 case lir_null_check: s = "null_check"; break;
1765 case lir_return: s = "return"; break;
1766 case lir_safepoint: s = "safepoint"; break;
1767 case lir_neg: s = "neg"; break;
1768 case lir_leal: s = "leal"; break;
1769 case lir_branch: s = "branch"; break;
1770 case lir_cond_float_branch: s = "flt_cond_br"; break;
1771 case lir_move: s = "move"; break;
1772 case lir_roundfp: s = "roundfp"; break;
1773 case lir_rtcall: s = "rtcall"; break;
1774 case lir_throw: s = "throw"; break;
1775 case lir_unwind: s = "unwind"; break;
1776 case lir_convert: s = "convert"; break;
1777 case lir_alloc_object: s = "alloc_obj"; break;
1778 case lir_monaddr: s = "mon_addr"; break;
1779 case lir_pack64: s = "pack64"; break;
1780 case lir_unpack64: s = "unpack64"; break;
1781 // LIR_Op2
1782 case lir_cmp: s = "cmp"; break;
1783 case lir_cmp_l2i: s = "cmp_l2i"; break;
1784 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1785 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1786 case lir_cmove: s = "cmove"; break;
1787 case lir_add: s = "add"; break;
1788 case lir_sub: s = "sub"; break;
1789 case lir_mul: s = "mul"; break;
1790 case lir_mul_strictfp: s = "mul_strictfp"; break;
1791 case lir_div: s = "div"; break;
1792 case lir_div_strictfp: s = "div_strictfp"; break;
1793 case lir_rem: s = "rem"; break;
1794 case lir_abs: s = "abs"; break;
1795 case lir_sqrt: s = "sqrt"; break;
1796 case lir_sin: s = "sin"; break;
1797 case lir_cos: s = "cos"; break;
1798 case lir_tan: s = "tan"; break;
1799 case lir_log: s = "log"; break;
1800 case lir_log10: s = "log10"; break;
1801 case lir_exp: s = "exp"; break;
1802 case lir_pow: s = "pow"; break;
1803 case lir_logic_and: s = "logic_and"; break;
1804 case lir_logic_or: s = "logic_or"; break;
1805 case lir_logic_xor: s = "logic_xor"; break;
1806 case lir_shl: s = "shift_left"; break;
1807 case lir_shr: s = "shift_right"; break;
1808 case lir_ushr: s = "ushift_right"; break;
1809 case lir_alloc_array: s = "alloc_array"; break;
1810 case lir_xadd: s = "xadd"; break;
1811 case lir_xchg: s = "xchg"; break;
1812 // LIR_Op3
1813 case lir_idiv: s = "idiv"; break;
1814 case lir_irem: s = "irem"; break;
1815 // LIR_OpJavaCall
1816 case lir_static_call: s = "static"; break;
1817 case lir_optvirtual_call: s = "optvirtual"; break;
1818 case lir_icvirtual_call: s = "icvirtual"; break;
1819 case lir_virtual_call: s = "virtual"; break;
1820 case lir_dynamic_call: s = "dynamic"; break;
1821 // LIR_OpArrayCopy
1822 case lir_arraycopy: s = "arraycopy"; break;
1823 // LIR_OpUpdateCRC32
1824 case lir_updatecrc32: s = "updatecrc32"; break;
1825 // LIR_OpLock
1826 case lir_lock: s = "lock"; break;
1827 case lir_unlock: s = "unlock"; break;
1828 // LIR_OpDelay
1829 case lir_delay_slot: s = "delay"; break;
1830 // LIR_OpTypeCheck
1831 case lir_instanceof: s = "instanceof"; break;
1832 case lir_checkcast: s = "checkcast"; break;
1833 case lir_store_check: s = "store_check"; break;
1834 // LIR_OpCompareAndSwap
1835 case lir_cas_long: s = "cas_long"; break;
1836 case lir_cas_obj: s = "cas_obj"; break;
1837 case lir_cas_int: s = "cas_int"; break;
1838 // LIR_OpProfileCall
1839 case lir_profile_call: s = "profile_call"; break;
1840 // LIR_OpProfileType
1841 case lir_profile_type: s = "profile_type"; break;
1842 // LIR_OpAssert
1843 #ifdef ASSERT
1844 case lir_assert: s = "assert"; break;
1845 #endif
1846 case lir_none: ShouldNotReachHere();break;
1847 default: s = "illegal_op"; break;
1848 }
1849 return s;
1850 }
1851
1852 // LIR_OpJavaCall
1853 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1854 out->print("call: ");
1855 out->print("[addr: " INTPTR_FORMAT "]", p2i(address()));
1856 if (receiver()->is_valid()) {
1857 out->print(" [recv: "); receiver()->print(out); out->print("]");
1858 }
1859 if (result_opr()->is_valid()) {
1860 out->print(" [result: "); result_opr()->print(out); out->print("]");
1861 }
1862 }
1863
1864 // LIR_OpLabel
1865 void LIR_OpLabel::print_instr(outputStream* out) const {
1866 out->print("[label:" INTPTR_FORMAT "]", p2i(_label));
1867 }
1868
1869 // LIR_OpArrayCopy
1870 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1871 src()->print(out); out->print(" ");
1872 src_pos()->print(out); out->print(" ");
1873 dst()->print(out); out->print(" ");
1874 dst_pos()->print(out); out->print(" ");
1875 length()->print(out); out->print(" ");
1876 tmp()->print(out); out->print(" ");
1877 }
1878
1879 // LIR_OpUpdateCRC32
1880 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
1881 crc()->print(out); out->print(" ");
1882 val()->print(out); out->print(" ");
1883 result_opr()->print(out); out->print(" ");
1884 }
1885
1886 // LIR_OpCompareAndSwap
1887 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1888 addr()->print(out); out->print(" ");
1889 cmp_value()->print(out); out->print(" ");
1890 new_value()->print(out); out->print(" ");
1891 tmp1()->print(out); out->print(" ");
1892 tmp2()->print(out); out->print(" ");
1893
1894 }
1895
1896 // LIR_Op0
1897 void LIR_Op0::print_instr(outputStream* out) const {
1898 result_opr()->print(out);
1899 }
1900
1901 // LIR_Op1
1902 const char * LIR_Op1::name() const {
1903 if (code() == lir_move) {
1904 switch (move_kind()) {
1905 case lir_move_normal:
1906 return "move";
1907 case lir_move_unaligned:
1908 return "unaligned move";
1909 case lir_move_volatile:
1910 return "volatile_move";
1911 case lir_move_wide:
1912 return "wide_move";
1913 default:
1914 ShouldNotReachHere();
1915 return "illegal_op";
1916 }
1917 } else {
1918 return LIR_Op::name();
1919 }
1920 }
1921
1922
1923 void LIR_Op1::print_instr(outputStream* out) const {
1924 _opr->print(out); out->print(" ");
1925 result_opr()->print(out); out->print(" ");
1926 print_patch_code(out, patch_code());
1927 }
1928
1929
1930 // LIR_Op1
1931 void LIR_OpRTCall::print_instr(outputStream* out) const {
1932 intx a = (intx)addr();
1933 out->print("%s", Runtime1::name_for_address(addr()));
1934 out->print(" ");
1935 tmp()->print(out);
1936 }
1937
1938 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1939 switch(code) {
1940 case lir_patch_none: break;
1941 case lir_patch_low: out->print("[patch_low]"); break;
1942 case lir_patch_high: out->print("[patch_high]"); break;
1943 case lir_patch_normal: out->print("[patch_normal]"); break;
1944 default: ShouldNotReachHere();
1945 }
1946 }
1947
1948 // LIR_OpBranch
1949 void LIR_OpBranch::print_instr(outputStream* out) const {
1950 print_condition(out, cond()); out->print(" ");
1951 if (block() != NULL) {
1952 out->print("[B%d] ", block()->block_id());
1953 } else if (stub() != NULL) {
1954 out->print("[");
1955 stub()->print_name(out);
1956 out->print(": " INTPTR_FORMAT "]", p2i(stub()));
1957 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1958 } else {
1959 out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
1960 }
1961 if (ublock() != NULL) {
1962 out->print("unordered: [B%d] ", ublock()->block_id());
1963 }
1964 }
1965
1966 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1967 switch(cond) {
1968 case lir_cond_equal: out->print("[EQ]"); break;
1969 case lir_cond_notEqual: out->print("[NE]"); break;
1970 case lir_cond_less: out->print("[LT]"); break;
1971 case lir_cond_lessEqual: out->print("[LE]"); break;
1972 case lir_cond_greaterEqual: out->print("[GE]"); break;
1973 case lir_cond_greater: out->print("[GT]"); break;
1974 case lir_cond_belowEqual: out->print("[BE]"); break;
1975 case lir_cond_aboveEqual: out->print("[AE]"); break;
1976 case lir_cond_always: out->print("[AL]"); break;
1977 default: out->print("[%d]",cond); break;
1978 }
1979 }
1980
1981 // LIR_OpConvert
1982 void LIR_OpConvert::print_instr(outputStream* out) const {
1983 print_bytecode(out, bytecode());
1984 in_opr()->print(out); out->print(" ");
1985 result_opr()->print(out); out->print(" ");
1986 #ifdef PPC
1987 if(tmp1()->is_valid()) {
1988 tmp1()->print(out); out->print(" ");
1989 tmp2()->print(out); out->print(" ");
1990 }
1991 #endif
1992 }
1993
1994 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1995 switch(code) {
1996 case Bytecodes::_d2f: out->print("[d2f] "); break;
1997 case Bytecodes::_d2i: out->print("[d2i] "); break;
1998 case Bytecodes::_d2l: out->print("[d2l] "); break;
1999 case Bytecodes::_f2d: out->print("[f2d] "); break;
2000 case Bytecodes::_f2i: out->print("[f2i] "); break;
2001 case Bytecodes::_f2l: out->print("[f2l] "); break;
2002 case Bytecodes::_i2b: out->print("[i2b] "); break;
2003 case Bytecodes::_i2c: out->print("[i2c] "); break;
2004 case Bytecodes::_i2d: out->print("[i2d] "); break;
2005 case Bytecodes::_i2f: out->print("[i2f] "); break;
2006 case Bytecodes::_i2l: out->print("[i2l] "); break;
2007 case Bytecodes::_i2s: out->print("[i2s] "); break;
2008 case Bytecodes::_l2i: out->print("[l2i] "); break;
2009 case Bytecodes::_l2f: out->print("[l2f] "); break;
2010 case Bytecodes::_l2d: out->print("[l2d] "); break;
2011 default:
2012 out->print("[?%d]",code);
2013 break;
2014 }
2015 }
2016
2017 void LIR_OpAllocObj::print_instr(outputStream* out) const {
2018 klass()->print(out); out->print(" ");
2019 obj()->print(out); out->print(" ");
2020 tmp1()->print(out); out->print(" ");
2021 tmp2()->print(out); out->print(" ");
2022 tmp3()->print(out); out->print(" ");
2023 tmp4()->print(out); out->print(" ");
2024 out->print("[hdr:%d]", header_size()); out->print(" ");
2025 out->print("[obj:%d]", object_size()); out->print(" ");
2026 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2027 }
2028
2029 void LIR_OpRoundFP::print_instr(outputStream* out) const {
2030 _opr->print(out); out->print(" ");
2031 tmp()->print(out); out->print(" ");
2032 result_opr()->print(out); out->print(" ");
2033 }
2034
2035 // LIR_Op2
2036 void LIR_Op2::print_instr(outputStream* out) const {
2037 if (code() == lir_cmove) {
2038 print_condition(out, condition()); out->print(" ");
2039 }
2040 in_opr1()->print(out); out->print(" ");
2041 in_opr2()->print(out); out->print(" ");
2042 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2043 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2044 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2045 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
2046 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
2047 result_opr()->print(out);
2048 }
2049
2050 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2051 klass()->print(out); out->print(" ");
2052 len()->print(out); out->print(" ");
2053 obj()->print(out); out->print(" ");
2054 tmp1()->print(out); out->print(" ");
2055 tmp2()->print(out); out->print(" ");
2056 tmp3()->print(out); out->print(" ");
2057 tmp4()->print(out); out->print(" ");
2058 out->print("[type:0x%x]", type()); out->print(" ");
2059 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2060 }
2061
2062
2063 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
2064 object()->print(out); out->print(" ");
2065 if (code() == lir_store_check) {
2066 array()->print(out); out->print(" ");
2067 }
2068 if (code() != lir_store_check) {
2069 klass()->print_name_on(out); out->print(" ");
2070 if (fast_check()) out->print("fast_check ");
2071 }
2072 tmp1()->print(out); out->print(" ");
2073 tmp2()->print(out); out->print(" ");
2074 tmp3()->print(out); out->print(" ");
2075 result_opr()->print(out); out->print(" ");
2076 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2077 }
2078
2079
2080 // LIR_Op3
2081 void LIR_Op3::print_instr(outputStream* out) const {
2082 in_opr1()->print(out); out->print(" ");
2083 in_opr2()->print(out); out->print(" ");
2084 in_opr3()->print(out); out->print(" ");
2085 result_opr()->print(out);
2086 }
2087
2088
2089 void LIR_OpLock::print_instr(outputStream* out) const {
2090 hdr_opr()->print(out); out->print(" ");
2091 obj_opr()->print(out); out->print(" ");
2092 lock_opr()->print(out); out->print(" ");
2093 if (_scratch->is_valid()) {
2094 _scratch->print(out); out->print(" ");
2095 }
2096 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2097 }
2098
2099 #ifdef ASSERT
2100 void LIR_OpAssert::print_instr(outputStream* out) const {
2101 print_condition(out, condition()); out->print(" ");
2102 in_opr1()->print(out); out->print(" ");
2103 in_opr2()->print(out); out->print(", \"");
2104 out->print("%s", msg()); out->print("\"");
2105 }
2106 #endif
2107
2108
2109 void LIR_OpDelay::print_instr(outputStream* out) const {
2110 _op->print_on(out);
2111 }
2112
2113
2114 // LIR_OpProfileCall
2115 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2116 profiled_method()->name()->print_symbol_on(out);
2117 out->print(".");
2118 profiled_method()->holder()->name()->print_symbol_on(out);
2119 out->print(" @ %d ", profiled_bci());
2120 mdo()->print(out); out->print(" ");
2121 recv()->print(out); out->print(" ");
2122 tmp1()->print(out); out->print(" ");
2123 }
2124
2125 // LIR_OpProfileType
2126 void LIR_OpProfileType::print_instr(outputStream* out) const {
2127 out->print("exact = ");
2128 if (exact_klass() == NULL) {
2129 out->print("unknown");
2130 } else {
2131 exact_klass()->print_name_on(out);
2132 }
2133 out->print(" current = "); ciTypeEntries::print_ciklass(out, current_klass());
2134 out->print(" ");
2135 mdp()->print(out); out->print(" ");
2136 obj()->print(out); out->print(" ");
2137 tmp()->print(out); out->print(" ");
2138 }
2139
2140 #endif // PRODUCT
2141
2142 // Implementation of LIR_InsertionBuffer
2143
2144 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2145 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2146
2147 int i = number_of_insertion_points() - 1;
2148 if (i < 0 || index_at(i) < index) {
2149 append_new(index, 1);
2150 } else {
2151 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2152 assert(count_at(i) > 0, "check");
2153 set_count_at(i, count_at(i) + 1);
2154 }
2155 _ops.push(op);
2156
2157 DEBUG_ONLY(verify());
2158 }
2159
2160 #ifdef ASSERT
2161 void LIR_InsertionBuffer::verify() {
2162 int sum = 0;
2163 int prev_idx = -1;
2164
2165 for (int i = 0; i < number_of_insertion_points(); i++) {
2166 assert(prev_idx < index_at(i), "index must be ordered ascending");
2167 sum += count_at(i);
2168 }
2169 assert(sum == number_of_ops(), "wrong total sum");
2170 }
2171 #endif