1 /*
2 * Copyright (c) 2000, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/cardTableModRefBS.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "vmreg_x86.inline.hpp"
42
43
44 // These masks are used to provide 128-bit aligned bitmasks to the XMM
45 // instructions, to allow sign-masking or sign-bit flipping. They allow
46 // fast versions of NegF/NegD and AbsF/AbsD.
47
48 // Note: 'double' and 'long long' have 32-bits alignment on x86.
49 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
50 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
51 // of 128-bits operands for SSE instructions.
52 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
53 // Store the value to a 128-bits operand.
54 operand[0] = lo;
55 operand[1] = hi;
56 return operand;
57 }
58
59 // Buffer for 128-bits masks used by SSE instructions.
60 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
61
62 // Static initialization during VM startup.
63 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
64 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
65 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
66 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
67
68
69
70 NEEDS_CLEANUP // remove this definitions ?
71 const Register IC_Klass = rax; // where the IC klass is cached
72 const Register SYNC_header = rax; // synchronization header
73 const Register SHIFT_count = rcx; // where count for shift operations must be
74
75 #define __ _masm->
76
77
78 static void select_different_registers(Register preserve,
79 Register extra,
80 Register &tmp1,
81 Register &tmp2) {
82 if (tmp1 == preserve) {
83 assert_different_registers(tmp1, tmp2, extra);
84 tmp1 = extra;
85 } else if (tmp2 == preserve) {
86 assert_different_registers(tmp1, tmp2, extra);
87 tmp2 = extra;
88 }
89 assert_different_registers(preserve, tmp1, tmp2);
90 }
91
92
93
94 static void select_different_registers(Register preserve,
95 Register extra,
96 Register &tmp1,
97 Register &tmp2,
98 Register &tmp3) {
99 if (tmp1 == preserve) {
100 assert_different_registers(tmp1, tmp2, tmp3, extra);
101 tmp1 = extra;
102 } else if (tmp2 == preserve) {
103 assert_different_registers(tmp1, tmp2, tmp3, extra);
104 tmp2 = extra;
105 } else if (tmp3 == preserve) {
106 assert_different_registers(tmp1, tmp2, tmp3, extra);
107 tmp3 = extra;
108 }
109 assert_different_registers(preserve, tmp1, tmp2, tmp3);
110 }
111
112
113
114 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
115 if (opr->is_constant()) {
116 LIR_Const* constant = opr->as_constant_ptr();
117 switch (constant->type()) {
118 case T_INT: {
119 return true;
120 }
121
122 default:
123 return false;
124 }
125 }
126 return false;
127 }
128
129
130 LIR_Opr LIR_Assembler::receiverOpr() {
131 return FrameMap::receiver_opr;
132 }
133
134 LIR_Opr LIR_Assembler::osrBufferPointer() {
135 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
136 }
137
138 //--------------fpu register translations-----------------------
139
140
141 address LIR_Assembler::float_constant(float f) {
142 address const_addr = __ float_constant(f);
143 if (const_addr == NULL) {
144 bailout("const section overflow");
145 return __ code()->consts()->start();
146 } else {
147 return const_addr;
148 }
149 }
150
151
152 address LIR_Assembler::double_constant(double d) {
153 address const_addr = __ double_constant(d);
154 if (const_addr == NULL) {
155 bailout("const section overflow");
156 return __ code()->consts()->start();
157 } else {
158 return const_addr;
159 }
160 }
161
162
163 void LIR_Assembler::set_24bit_FPU() {
164 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
165 }
166
167 void LIR_Assembler::reset_FPU() {
168 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
169 }
170
171 void LIR_Assembler::fpop() {
172 __ fpop();
173 }
174
175 void LIR_Assembler::fxch(int i) {
176 __ fxch(i);
177 }
178
179 void LIR_Assembler::fld(int i) {
180 __ fld_s(i);
181 }
182
183 void LIR_Assembler::ffree(int i) {
184 __ ffree(i);
185 }
186
187 void LIR_Assembler::breakpoint() {
188 __ int3();
189 }
190
191 void LIR_Assembler::push(LIR_Opr opr) {
192 if (opr->is_single_cpu()) {
193 __ push_reg(opr->as_register());
194 } else if (opr->is_double_cpu()) {
195 NOT_LP64(__ push_reg(opr->as_register_hi()));
196 __ push_reg(opr->as_register_lo());
197 } else if (opr->is_stack()) {
198 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
199 } else if (opr->is_constant()) {
200 LIR_Const* const_opr = opr->as_constant_ptr();
201 if (const_opr->type() == T_OBJECT) {
202 __ push_oop(const_opr->as_jobject());
203 } else if (const_opr->type() == T_INT) {
204 __ push_jint(const_opr->as_jint());
205 } else {
206 ShouldNotReachHere();
207 }
208
209 } else {
210 ShouldNotReachHere();
211 }
212 }
213
214 void LIR_Assembler::pop(LIR_Opr opr) {
215 if (opr->is_single_cpu()) {
216 __ pop_reg(opr->as_register());
217 } else {
218 ShouldNotReachHere();
219 }
220 }
221
222 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
223 return addr->base()->is_illegal() && addr->index()->is_illegal();
224 }
225
226 //-------------------------------------------
227
228 Address LIR_Assembler::as_Address(LIR_Address* addr) {
229 return as_Address(addr, rscratch1);
230 }
231
232 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
233 if (addr->base()->is_illegal()) {
234 assert(addr->index()->is_illegal(), "must be illegal too");
235 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
236 if (! __ reachable(laddr)) {
237 __ movptr(tmp, laddr.addr());
238 Address res(tmp, 0);
239 return res;
240 } else {
241 return __ as_Address(laddr);
242 }
243 }
244
245 Register base = addr->base()->as_pointer_register();
246
247 if (addr->index()->is_illegal()) {
248 return Address( base, addr->disp());
249 } else if (addr->index()->is_cpu_register()) {
250 Register index = addr->index()->as_pointer_register();
251 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
252 } else if (addr->index()->is_constant()) {
253 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
254 assert(Assembler::is_simm32(addr_offset), "must be");
255
256 return Address(base, addr_offset);
257 } else {
258 Unimplemented();
259 return Address();
260 }
261 }
262
263
264 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
265 Address base = as_Address(addr);
266 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
267 }
268
269
270 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
271 return as_Address(addr);
272 }
273
274
275 void LIR_Assembler::osr_entry() {
276 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
277 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
278 ValueStack* entry_state = osr_entry->state();
279 int number_of_locks = entry_state->locks_size();
280
281 // we jump here if osr happens with the interpreter
282 // state set up to continue at the beginning of the
283 // loop that triggered osr - in particular, we have
284 // the following registers setup:
285 //
286 // rcx: osr buffer
287 //
288
289 // build frame
290 ciMethod* m = compilation()->method();
291 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
292
293 // OSR buffer is
294 //
295 // locals[nlocals-1..0]
296 // monitors[0..number_of_locks]
297 //
298 // locals is a direct copy of the interpreter frame so in the osr buffer
299 // so first slot in the local array is the last local from the interpreter
300 // and last slot is local[0] (receiver) from the interpreter
301 //
302 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
303 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
304 // in the interpreter frame (the method lock if a sync method)
305
306 // Initialize monitors in the compiled activation.
307 // rcx: pointer to osr buffer
308 //
309 // All other registers are dead at this point and the locals will be
310 // copied into place by code emitted in the IR.
311
312 Register OSR_buf = osrBufferPointer()->as_pointer_register();
313 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
314 int monitor_offset = BytesPerWord * method()->max_locals() +
315 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
316 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
317 // the OSR buffer using 2 word entries: first the lock and then
318 // the oop.
319 for (int i = 0; i < number_of_locks; i++) {
320 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
321 #ifdef ASSERT
322 // verify the interpreter's monitor has a non-null object
323 {
324 Label L;
325 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
326 __ jcc(Assembler::notZero, L);
327 __ stop("locked object is NULL");
328 __ bind(L);
329 }
330 #endif
331 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
332 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
333 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
334 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
335 }
336 }
337 }
338
339
340 // inline cache check; done before the frame is built.
341 int LIR_Assembler::check_icache() {
342 Register receiver = FrameMap::receiver_opr->as_register();
343 Register ic_klass = IC_Klass;
344 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
345 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
346 if (!do_post_padding) {
347 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
348 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
349 }
350 int offset = __ offset();
351 __ inline_cache_check(receiver, IC_Klass);
352 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
353 if (do_post_padding) {
354 // force alignment after the cache check.
355 // It's been verified to be aligned if !VerifyOops
356 __ align(CodeEntryAlignment);
357 }
358 return offset;
359 }
360
361
362 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
363 jobject o = NULL;
364 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
365 __ movoop(reg, o);
366 patching_epilog(patch, lir_patch_normal, reg, info);
367 }
368
369 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
370 Metadata* o = NULL;
371 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
372 __ mov_metadata(reg, o);
373 patching_epilog(patch, lir_patch_normal, reg, info);
374 }
375
376 // This specifies the rsp decrement needed to build the frame
377 int LIR_Assembler::initial_frame_size_in_bytes() const {
378 // if rounding, must let FrameMap know!
379
380 // The frame_map records size in slots (32bit word)
381
382 // subtract two words to account for return address and link
383 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
384 }
385
386
387 int LIR_Assembler::emit_exception_handler() {
388 // if the last instruction is a call (typically to do a throw which
389 // is coming at the end after block reordering) the return address
390 // must still point into the code area in order to avoid assertion
391 // failures when searching for the corresponding bci => add a nop
392 // (was bug 5/14/1999 - gri)
393 __ nop();
394
395 // generate code for exception handler
396 address handler_base = __ start_a_stub(exception_handler_size());
397 if (handler_base == NULL) {
398 // not enough space left for the handler
399 bailout("exception handler overflow");
400 return -1;
401 }
402
403 int offset = code_offset();
404
405 // the exception oop and pc are in rax, and rdx
406 // no other registers need to be preserved, so invalidate them
407 __ invalidate_registers(false, true, true, false, true, true);
408
409 // check that there is really an exception
410 __ verify_not_null_oop(rax);
411
412 // search an exception handler (rax: exception oop, rdx: throwing pc)
413 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
414 __ should_not_reach_here();
415 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
416 __ end_a_stub();
417
418 return offset;
419 }
420
421
422 // Emit the code to remove the frame from the stack in the exception
423 // unwind path.
424 int LIR_Assembler::emit_unwind_handler() {
425 #ifndef PRODUCT
426 if (CommentedAssembly) {
427 _masm->block_comment("Unwind handler");
428 }
429 #endif
430
431 int offset = code_offset();
432
433 // Fetch the exception from TLS and clear out exception related thread state
434 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
435 NOT_LP64(__ get_thread(rsi));
436 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
437 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
438 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
439
440 __ bind(_unwind_handler_entry);
441 __ verify_not_null_oop(rax);
442 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
443 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
444 }
445
446 // Preform needed unlocking
447 MonitorExitStub* stub = NULL;
448 if (method()->is_synchronized()) {
449 monitor_address(0, FrameMap::rax_opr);
450 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
451 __ unlock_object(rdi, rsi, rax, *stub->entry());
452 __ bind(*stub->continuation());
453 }
454
455 if (compilation()->env()->dtrace_method_probes()) {
456 #ifdef _LP64
457 __ mov(rdi, r15_thread);
458 __ mov_metadata(rsi, method()->constant_encoding());
459 #else
460 __ get_thread(rax);
461 __ movptr(Address(rsp, 0), rax);
462 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
463 #endif
464 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
465 }
466
467 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
468 __ mov(rax, rbx); // Restore the exception
469 }
470
471 // remove the activation and dispatch to the unwind handler
472 __ remove_frame(initial_frame_size_in_bytes());
473 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
474
475 // Emit the slow path assembly
476 if (stub != NULL) {
477 stub->emit_code(this);
478 }
479
480 return offset;
481 }
482
483
484 int LIR_Assembler::emit_deopt_handler() {
485 // if the last instruction is a call (typically to do a throw which
486 // is coming at the end after block reordering) the return address
487 // must still point into the code area in order to avoid assertion
488 // failures when searching for the corresponding bci => add a nop
489 // (was bug 5/14/1999 - gri)
490 __ nop();
491
492 // generate code for exception handler
493 address handler_base = __ start_a_stub(deopt_handler_size());
494 if (handler_base == NULL) {
495 // not enough space left for the handler
496 bailout("deopt handler overflow");
497 return -1;
498 }
499
500 int offset = code_offset();
501 InternalAddress here(__ pc());
502
503 __ pushptr(here.addr());
504 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
505 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
506 __ end_a_stub();
507
508 return offset;
509 }
510
511
512 void LIR_Assembler::return_op(LIR_Opr result) {
513 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
514 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
515 assert(result->fpu() == 0, "result must already be on TOS");
516 }
517
518 // Pop the stack before the safepoint code
519 __ remove_frame(initial_frame_size_in_bytes());
520
521 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
522 __ reserved_stack_check();
523 }
524
525 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
526
527 // Note: we do not need to round double result; float result has the right precision
528 // the poll sets the condition code, but no data registers
529 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
530
531 if (Assembler::is_polling_page_far()) {
532 __ lea(rscratch1, polling_page);
533 __ relocate(relocInfo::poll_return_type);
534 __ testl(rax, Address(rscratch1, 0));
535 } else {
536 __ testl(rax, polling_page);
537 }
538 __ ret(0);
539 }
540
541
542 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
543 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
544 guarantee(info != NULL, "Shouldn't be NULL");
545 int offset = __ offset();
546 if (Assembler::is_polling_page_far()) {
547 __ lea(rscratch1, polling_page);
548 offset = __ offset();
549 add_debug_info_for_branch(info);
550 __ relocate(relocInfo::poll_type);
551 __ testl(rax, Address(rscratch1, 0));
552 } else {
553 add_debug_info_for_branch(info);
554 __ testl(rax, polling_page);
555 }
556 return offset;
557 }
558
559
560 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
561 if (from_reg != to_reg) __ mov(to_reg, from_reg);
562 }
563
564 void LIR_Assembler::swap_reg(Register a, Register b) {
565 __ xchgptr(a, b);
566 }
567
568
569 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
570 assert(src->is_constant(), "should not call otherwise");
571 assert(dest->is_register(), "should not call otherwise");
572 LIR_Const* c = src->as_constant_ptr();
573
574 switch (c->type()) {
575 case T_INT: {
576 assert(patch_code == lir_patch_none, "no patching handled here");
577 __ movl(dest->as_register(), c->as_jint());
578 break;
579 }
580
581 case T_ADDRESS: {
582 assert(patch_code == lir_patch_none, "no patching handled here");
583 __ movptr(dest->as_register(), c->as_jint());
584 break;
585 }
586
587 case T_LONG: {
588 assert(patch_code == lir_patch_none, "no patching handled here");
589 #ifdef _LP64
590 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
591 #else
592 __ movptr(dest->as_register_lo(), c->as_jint_lo());
593 __ movptr(dest->as_register_hi(), c->as_jint_hi());
594 #endif // _LP64
595 break;
596 }
597
598 case T_OBJECT: {
599 if (patch_code != lir_patch_none) {
600 jobject2reg_with_patching(dest->as_register(), info);
601 } else {
602 __ movoop(dest->as_register(), c->as_jobject());
603 }
604 break;
605 }
606
607 case T_METADATA: {
608 if (patch_code != lir_patch_none) {
609 klass2reg_with_patching(dest->as_register(), info);
610 } else {
611 __ mov_metadata(dest->as_register(), c->as_metadata());
612 }
613 break;
614 }
615
616 case T_FLOAT: {
617 if (dest->is_single_xmm()) {
618 if (c->is_zero_float()) {
619 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
620 } else {
621 __ movflt(dest->as_xmm_float_reg(),
622 InternalAddress(float_constant(c->as_jfloat())));
623 }
624 } else {
625 assert(dest->is_single_fpu(), "must be");
626 assert(dest->fpu_regnr() == 0, "dest must be TOS");
627 if (c->is_zero_float()) {
628 __ fldz();
629 } else if (c->is_one_float()) {
630 __ fld1();
631 } else {
632 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
633 }
634 }
635 break;
636 }
637
638 case T_DOUBLE: {
639 if (dest->is_double_xmm()) {
640 if (c->is_zero_double()) {
641 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
642 } else {
643 __ movdbl(dest->as_xmm_double_reg(),
644 InternalAddress(double_constant(c->as_jdouble())));
645 }
646 } else {
647 assert(dest->is_double_fpu(), "must be");
648 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
649 if (c->is_zero_double()) {
650 __ fldz();
651 } else if (c->is_one_double()) {
652 __ fld1();
653 } else {
654 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
655 }
656 }
657 break;
658 }
659
660 default:
661 ShouldNotReachHere();
662 }
663 }
664
665 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
666 assert(src->is_constant(), "should not call otherwise");
667 assert(dest->is_stack(), "should not call otherwise");
668 LIR_Const* c = src->as_constant_ptr();
669
670 switch (c->type()) {
671 case T_INT: // fall through
672 case T_FLOAT:
673 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
674 break;
675
676 case T_ADDRESS:
677 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
678 break;
679
680 case T_OBJECT:
681 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
682 break;
683
684 case T_LONG: // fall through
685 case T_DOUBLE:
686 #ifdef _LP64
687 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
688 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
689 #else
690 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
691 lo_word_offset_in_bytes), c->as_jint_lo_bits());
692 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
693 hi_word_offset_in_bytes), c->as_jint_hi_bits());
694 #endif // _LP64
695 break;
696
697 default:
698 ShouldNotReachHere();
699 }
700 }
701
702 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
703 assert(src->is_constant(), "should not call otherwise");
704 assert(dest->is_address(), "should not call otherwise");
705 LIR_Const* c = src->as_constant_ptr();
706 LIR_Address* addr = dest->as_address_ptr();
707
708 int null_check_here = code_offset();
709 switch (type) {
710 case T_INT: // fall through
711 case T_FLOAT:
712 __ movl(as_Address(addr), c->as_jint_bits());
713 break;
714
715 case T_ADDRESS:
716 __ movptr(as_Address(addr), c->as_jint_bits());
717 break;
718
719 case T_OBJECT: // fall through
720 case T_ARRAY:
721 if (c->as_jobject() == NULL) {
722 if (UseCompressedOops && !wide) {
723 __ movl(as_Address(addr), (int32_t)NULL_WORD);
724 } else {
725 #ifdef _LP64
726 __ xorptr(rscratch1, rscratch1);
727 null_check_here = code_offset();
728 __ movptr(as_Address(addr), rscratch1);
729 #else
730 __ movptr(as_Address(addr), NULL_WORD);
731 #endif
732 }
733 } else {
734 if (is_literal_address(addr)) {
735 ShouldNotReachHere();
736 __ movoop(as_Address(addr, noreg), c->as_jobject());
737 } else {
738 #ifdef _LP64
739 __ movoop(rscratch1, c->as_jobject());
740 if (UseCompressedOops && !wide) {
741 __ encode_heap_oop(rscratch1);
742 null_check_here = code_offset();
743 __ movl(as_Address_lo(addr), rscratch1);
744 } else {
745 null_check_here = code_offset();
746 __ movptr(as_Address_lo(addr), rscratch1);
747 }
748 #else
749 __ movoop(as_Address(addr), c->as_jobject());
750 #endif
751 }
752 }
753 break;
754
755 case T_LONG: // fall through
756 case T_DOUBLE:
757 #ifdef _LP64
758 if (is_literal_address(addr)) {
759 ShouldNotReachHere();
760 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
761 } else {
762 __ movptr(r10, (intptr_t)c->as_jlong_bits());
763 null_check_here = code_offset();
764 __ movptr(as_Address_lo(addr), r10);
765 }
766 #else
767 // Always reachable in 32bit so this doesn't produce useless move literal
768 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
769 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
770 #endif // _LP64
771 break;
772
773 case T_BOOLEAN: // fall through
774 case T_BYTE:
775 __ movb(as_Address(addr), c->as_jint() & 0xFF);
776 break;
777
778 case T_CHAR: // fall through
779 case T_SHORT:
780 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
781 break;
782
783 default:
784 ShouldNotReachHere();
785 };
786
787 if (info != NULL) {
788 add_debug_info_for_null_check(null_check_here, info);
789 }
790 }
791
792
793 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
794 assert(src->is_register(), "should not call otherwise");
795 assert(dest->is_register(), "should not call otherwise");
796
797 // move between cpu-registers
798 if (dest->is_single_cpu()) {
799 #ifdef _LP64
800 if (src->type() == T_LONG) {
801 // Can do LONG -> OBJECT
802 move_regs(src->as_register_lo(), dest->as_register());
803 return;
804 }
805 #endif
806 assert(src->is_single_cpu(), "must match");
807 if (src->type() == T_OBJECT) {
808 __ verify_oop(src->as_register());
809 }
810 move_regs(src->as_register(), dest->as_register());
811
812 } else if (dest->is_double_cpu()) {
813 #ifdef _LP64
814 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
815 // Surprising to me but we can see move of a long to t_object
816 __ verify_oop(src->as_register());
817 move_regs(src->as_register(), dest->as_register_lo());
818 return;
819 }
820 #endif
821 assert(src->is_double_cpu(), "must match");
822 Register f_lo = src->as_register_lo();
823 Register f_hi = src->as_register_hi();
824 Register t_lo = dest->as_register_lo();
825 Register t_hi = dest->as_register_hi();
826 #ifdef _LP64
827 assert(f_hi == f_lo, "must be same");
828 assert(t_hi == t_lo, "must be same");
829 move_regs(f_lo, t_lo);
830 #else
831 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
832
833
834 if (f_lo == t_hi && f_hi == t_lo) {
835 swap_reg(f_lo, f_hi);
836 } else if (f_hi == t_lo) {
837 assert(f_lo != t_hi, "overwriting register");
838 move_regs(f_hi, t_hi);
839 move_regs(f_lo, t_lo);
840 } else {
841 assert(f_hi != t_lo, "overwriting register");
842 move_regs(f_lo, t_lo);
843 move_regs(f_hi, t_hi);
844 }
845 #endif // LP64
846
847 // special moves from fpu-register to xmm-register
848 // necessary for method results
849 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
850 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
851 __ fld_s(Address(rsp, 0));
852 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
853 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
854 __ fld_d(Address(rsp, 0));
855 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
856 __ fstp_s(Address(rsp, 0));
857 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
858 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
859 __ fstp_d(Address(rsp, 0));
860 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
861
862 // move between xmm-registers
863 } else if (dest->is_single_xmm()) {
864 assert(src->is_single_xmm(), "must match");
865 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
866 } else if (dest->is_double_xmm()) {
867 assert(src->is_double_xmm(), "must match");
868 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
869
870 // move between fpu-registers (no instruction necessary because of fpu-stack)
871 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
872 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
873 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
874 } else {
875 ShouldNotReachHere();
876 }
877 }
878
879 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
880 assert(src->is_register(), "should not call otherwise");
881 assert(dest->is_stack(), "should not call otherwise");
882
883 if (src->is_single_cpu()) {
884 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
885 if (type == T_OBJECT || type == T_ARRAY) {
886 __ verify_oop(src->as_register());
887 __ movptr (dst, src->as_register());
888 } else if (type == T_METADATA) {
889 __ movptr (dst, src->as_register());
890 } else {
891 __ movl (dst, src->as_register());
892 }
893
894 } else if (src->is_double_cpu()) {
895 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
896 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
897 __ movptr (dstLO, src->as_register_lo());
898 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
899
900 } else if (src->is_single_xmm()) {
901 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
902 __ movflt(dst_addr, src->as_xmm_float_reg());
903
904 } else if (src->is_double_xmm()) {
905 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
906 __ movdbl(dst_addr, src->as_xmm_double_reg());
907
908 } else if (src->is_single_fpu()) {
909 assert(src->fpu_regnr() == 0, "argument must be on TOS");
910 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
911 if (pop_fpu_stack) __ fstp_s (dst_addr);
912 else __ fst_s (dst_addr);
913
914 } else if (src->is_double_fpu()) {
915 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
916 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
917 if (pop_fpu_stack) __ fstp_d (dst_addr);
918 else __ fst_d (dst_addr);
919
920 } else {
921 ShouldNotReachHere();
922 }
923 }
924
925
926 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
927 LIR_Address* to_addr = dest->as_address_ptr();
928 PatchingStub* patch = NULL;
929 Register compressed_src = rscratch1;
930
931 if (type == T_ARRAY || type == T_OBJECT) {
932 __ verify_oop(src->as_register());
933 #ifdef _LP64
934 if (UseCompressedOops && !wide) {
935 __ movptr(compressed_src, src->as_register());
936 __ encode_heap_oop(compressed_src);
937 if (patch_code != lir_patch_none) {
938 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
939 }
940 }
941 #endif
942 }
943
944 if (patch_code != lir_patch_none) {
945 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
946 Address toa = as_Address(to_addr);
947 assert(toa.disp() != 0, "must have");
948 }
949
950 int null_check_here = code_offset();
951 switch (type) {
952 case T_FLOAT: {
953 if (src->is_single_xmm()) {
954 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
955 } else {
956 assert(src->is_single_fpu(), "must be");
957 assert(src->fpu_regnr() == 0, "argument must be on TOS");
958 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
959 else __ fst_s (as_Address(to_addr));
960 }
961 break;
962 }
963
964 case T_DOUBLE: {
965 if (src->is_double_xmm()) {
966 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
967 } else {
968 assert(src->is_double_fpu(), "must be");
969 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
970 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
971 else __ fst_d (as_Address(to_addr));
972 }
973 break;
974 }
975
976 case T_ARRAY: // fall through
977 case T_OBJECT: // fall through
978 if (UseCompressedOops && !wide) {
979 __ movl(as_Address(to_addr), compressed_src);
980 } else {
981 __ movptr(as_Address(to_addr), src->as_register());
982 }
983 break;
984 case T_METADATA:
985 // We get here to store a method pointer to the stack to pass to
986 // a dtrace runtime call. This can't work on 64 bit with
987 // compressed klass ptrs: T_METADATA can be a compressed klass
988 // ptr or a 64 bit method pointer.
989 LP64_ONLY(ShouldNotReachHere());
990 __ movptr(as_Address(to_addr), src->as_register());
991 break;
992 case T_ADDRESS:
993 __ movptr(as_Address(to_addr), src->as_register());
994 break;
995 case T_INT:
996 __ movl(as_Address(to_addr), src->as_register());
997 break;
998
999 case T_LONG: {
1000 Register from_lo = src->as_register_lo();
1001 Register from_hi = src->as_register_hi();
1002 #ifdef _LP64
1003 __ movptr(as_Address_lo(to_addr), from_lo);
1004 #else
1005 Register base = to_addr->base()->as_register();
1006 Register index = noreg;
1007 if (to_addr->index()->is_register()) {
1008 index = to_addr->index()->as_register();
1009 }
1010 if (base == from_lo || index == from_lo) {
1011 assert(base != from_hi, "can't be");
1012 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1013 __ movl(as_Address_hi(to_addr), from_hi);
1014 if (patch != NULL) {
1015 patching_epilog(patch, lir_patch_high, base, info);
1016 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1017 patch_code = lir_patch_low;
1018 }
1019 __ movl(as_Address_lo(to_addr), from_lo);
1020 } else {
1021 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1022 __ movl(as_Address_lo(to_addr), from_lo);
1023 if (patch != NULL) {
1024 patching_epilog(patch, lir_patch_low, base, info);
1025 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1026 patch_code = lir_patch_high;
1027 }
1028 __ movl(as_Address_hi(to_addr), from_hi);
1029 }
1030 #endif // _LP64
1031 break;
1032 }
1033
1034 case T_BYTE: // fall through
1035 case T_BOOLEAN: {
1036 Register src_reg = src->as_register();
1037 Address dst_addr = as_Address(to_addr);
1038 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1039 __ movb(dst_addr, src_reg);
1040 break;
1041 }
1042
1043 case T_CHAR: // fall through
1044 case T_SHORT:
1045 __ movw(as_Address(to_addr), src->as_register());
1046 break;
1047
1048 default:
1049 ShouldNotReachHere();
1050 }
1051 if (info != NULL) {
1052 add_debug_info_for_null_check(null_check_here, info);
1053 }
1054
1055 if (patch_code != lir_patch_none) {
1056 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1057 }
1058 }
1059
1060
1061 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1062 assert(src->is_stack(), "should not call otherwise");
1063 assert(dest->is_register(), "should not call otherwise");
1064
1065 if (dest->is_single_cpu()) {
1066 if (type == T_ARRAY || type == T_OBJECT) {
1067 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1068 __ verify_oop(dest->as_register());
1069 } else if (type == T_METADATA) {
1070 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1071 } else {
1072 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1073 }
1074
1075 } else if (dest->is_double_cpu()) {
1076 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1077 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1078 __ movptr(dest->as_register_lo(), src_addr_LO);
1079 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1080
1081 } else if (dest->is_single_xmm()) {
1082 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1083 __ movflt(dest->as_xmm_float_reg(), src_addr);
1084
1085 } else if (dest->is_double_xmm()) {
1086 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1087 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1088
1089 } else if (dest->is_single_fpu()) {
1090 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1091 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1092 __ fld_s(src_addr);
1093
1094 } else if (dest->is_double_fpu()) {
1095 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1096 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1097 __ fld_d(src_addr);
1098
1099 } else {
1100 ShouldNotReachHere();
1101 }
1102 }
1103
1104
1105 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1106 if (src->is_single_stack()) {
1107 if (type == T_OBJECT || type == T_ARRAY) {
1108 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1109 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1110 } else {
1111 #ifndef _LP64
1112 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1113 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1114 #else
1115 //no pushl on 64bits
1116 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1117 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1118 #endif
1119 }
1120
1121 } else if (src->is_double_stack()) {
1122 #ifdef _LP64
1123 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1124 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1125 #else
1126 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1127 // push and pop the part at src + wordSize, adding wordSize for the previous push
1128 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1129 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1130 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1131 #endif // _LP64
1132
1133 } else {
1134 ShouldNotReachHere();
1135 }
1136 }
1137
1138
1139 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1140 assert(src->is_address(), "should not call otherwise");
1141 assert(dest->is_register(), "should not call otherwise");
1142
1143 LIR_Address* addr = src->as_address_ptr();
1144 Address from_addr = as_Address(addr);
1145
1146 if (addr->base()->type() == T_OBJECT) {
1147 __ verify_oop(addr->base()->as_pointer_register());
1148 }
1149
1150 switch (type) {
1151 case T_BOOLEAN: // fall through
1152 case T_BYTE: // fall through
1153 case T_CHAR: // fall through
1154 case T_SHORT:
1155 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1156 // on pre P6 processors we may get partial register stalls
1157 // so blow away the value of to_rinfo before loading a
1158 // partial word into it. Do it here so that it precedes
1159 // the potential patch point below.
1160 __ xorptr(dest->as_register(), dest->as_register());
1161 }
1162 break;
1163 }
1164
1165 PatchingStub* patch = NULL;
1166 if (patch_code != lir_patch_none) {
1167 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1168 assert(from_addr.disp() != 0, "must have");
1169 }
1170 if (info != NULL) {
1171 add_debug_info_for_null_check_here(info);
1172 }
1173
1174 switch (type) {
1175 case T_FLOAT: {
1176 if (dest->is_single_xmm()) {
1177 __ movflt(dest->as_xmm_float_reg(), from_addr);
1178 } else {
1179 assert(dest->is_single_fpu(), "must be");
1180 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1181 __ fld_s(from_addr);
1182 }
1183 break;
1184 }
1185
1186 case T_DOUBLE: {
1187 if (dest->is_double_xmm()) {
1188 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1189 } else {
1190 assert(dest->is_double_fpu(), "must be");
1191 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1192 __ fld_d(from_addr);
1193 }
1194 break;
1195 }
1196
1197 case T_OBJECT: // fall through
1198 case T_ARRAY: // fall through
1199 if (UseCompressedOops && !wide) {
1200 __ movl(dest->as_register(), from_addr);
1201 } else {
1202 __ movptr(dest->as_register(), from_addr);
1203 }
1204 break;
1205
1206 case T_ADDRESS:
1207 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1208 __ movl(dest->as_register(), from_addr);
1209 } else {
1210 __ movptr(dest->as_register(), from_addr);
1211 }
1212 break;
1213 case T_INT:
1214 __ movl(dest->as_register(), from_addr);
1215 break;
1216
1217 case T_LONG: {
1218 Register to_lo = dest->as_register_lo();
1219 Register to_hi = dest->as_register_hi();
1220 #ifdef _LP64
1221 __ movptr(to_lo, as_Address_lo(addr));
1222 #else
1223 Register base = addr->base()->as_register();
1224 Register index = noreg;
1225 if (addr->index()->is_register()) {
1226 index = addr->index()->as_register();
1227 }
1228 if ((base == to_lo && index == to_hi) ||
1229 (base == to_hi && index == to_lo)) {
1230 // addresses with 2 registers are only formed as a result of
1231 // array access so this code will never have to deal with
1232 // patches or null checks.
1233 assert(info == NULL && patch == NULL, "must be");
1234 __ lea(to_hi, as_Address(addr));
1235 __ movl(to_lo, Address(to_hi, 0));
1236 __ movl(to_hi, Address(to_hi, BytesPerWord));
1237 } else if (base == to_lo || index == to_lo) {
1238 assert(base != to_hi, "can't be");
1239 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1240 __ movl(to_hi, as_Address_hi(addr));
1241 if (patch != NULL) {
1242 patching_epilog(patch, lir_patch_high, base, info);
1243 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1244 patch_code = lir_patch_low;
1245 }
1246 __ movl(to_lo, as_Address_lo(addr));
1247 } else {
1248 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1249 __ movl(to_lo, as_Address_lo(addr));
1250 if (patch != NULL) {
1251 patching_epilog(patch, lir_patch_low, base, info);
1252 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1253 patch_code = lir_patch_high;
1254 }
1255 __ movl(to_hi, as_Address_hi(addr));
1256 }
1257 #endif // _LP64
1258 break;
1259 }
1260
1261 case T_BOOLEAN: // fall through
1262 case T_BYTE: {
1263 Register dest_reg = dest->as_register();
1264 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1265 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1266 __ movsbl(dest_reg, from_addr);
1267 } else {
1268 __ movb(dest_reg, from_addr);
1269 __ shll(dest_reg, 24);
1270 __ sarl(dest_reg, 24);
1271 }
1272 break;
1273 }
1274
1275 case T_CHAR: {
1276 Register dest_reg = dest->as_register();
1277 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1278 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1279 __ movzwl(dest_reg, from_addr);
1280 } else {
1281 __ movw(dest_reg, from_addr);
1282 }
1283 break;
1284 }
1285
1286 case T_SHORT: {
1287 Register dest_reg = dest->as_register();
1288 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1289 __ movswl(dest_reg, from_addr);
1290 } else {
1291 __ movw(dest_reg, from_addr);
1292 __ shll(dest_reg, 16);
1293 __ sarl(dest_reg, 16);
1294 }
1295 break;
1296 }
1297
1298 default:
1299 ShouldNotReachHere();
1300 }
1301
1302 if (patch != NULL) {
1303 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1304 }
1305
1306 if (type == T_ARRAY || type == T_OBJECT) {
1307 #ifdef _LP64
1308 if (UseCompressedOops && !wide) {
1309 __ decode_heap_oop(dest->as_register());
1310 }
1311 #endif
1312 __ verify_oop(dest->as_register());
1313 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1314 #ifdef _LP64
1315 if (UseCompressedClassPointers) {
1316 __ decode_klass_not_null(dest->as_register());
1317 }
1318 #endif
1319 }
1320 }
1321
1322
1323 NEEDS_CLEANUP; // This could be static?
1324 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1325 int elem_size = type2aelembytes(type);
1326 switch (elem_size) {
1327 case 1: return Address::times_1;
1328 case 2: return Address::times_2;
1329 case 4: return Address::times_4;
1330 case 8: return Address::times_8;
1331 }
1332 ShouldNotReachHere();
1333 return Address::no_scale;
1334 }
1335
1336
1337 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1338 switch (op->code()) {
1339 case lir_idiv:
1340 case lir_irem:
1341 arithmetic_idiv(op->code(),
1342 op->in_opr1(),
1343 op->in_opr2(),
1344 op->in_opr3(),
1345 op->result_opr(),
1346 op->info());
1347 break;
1348 case lir_fmad:
1349 __ fmad(op->result_opr()->as_xmm_double_reg(),
1350 op->in_opr1()->as_xmm_double_reg(),
1351 op->in_opr2()->as_xmm_double_reg(),
1352 op->in_opr3()->as_xmm_double_reg());
1353 break;
1354 case lir_fmaf:
1355 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1356 op->in_opr1()->as_xmm_float_reg(),
1357 op->in_opr2()->as_xmm_float_reg(),
1358 op->in_opr3()->as_xmm_float_reg());
1359 break;
1360 default: ShouldNotReachHere(); break;
1361 }
1362 }
1363
1364 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1365 #ifdef ASSERT
1366 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1367 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1368 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1369 #endif
1370
1371 if (op->cond() == lir_cond_always) {
1372 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1373 __ jmp (*(op->label()));
1374 } else {
1375 Assembler::Condition acond = Assembler::zero;
1376 if (op->code() == lir_cond_float_branch) {
1377 assert(op->ublock() != NULL, "must have unordered successor");
1378 __ jcc(Assembler::parity, *(op->ublock()->label()));
1379 switch(op->cond()) {
1380 case lir_cond_equal: acond = Assembler::equal; break;
1381 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1382 case lir_cond_less: acond = Assembler::below; break;
1383 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1384 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1385 case lir_cond_greater: acond = Assembler::above; break;
1386 default: ShouldNotReachHere();
1387 }
1388 } else {
1389 switch (op->cond()) {
1390 case lir_cond_equal: acond = Assembler::equal; break;
1391 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1392 case lir_cond_less: acond = Assembler::less; break;
1393 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1394 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1395 case lir_cond_greater: acond = Assembler::greater; break;
1396 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1397 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1398 default: ShouldNotReachHere();
1399 }
1400 }
1401 __ jcc(acond,*(op->label()));
1402 }
1403 }
1404
1405 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1406 LIR_Opr src = op->in_opr();
1407 LIR_Opr dest = op->result_opr();
1408
1409 switch (op->bytecode()) {
1410 case Bytecodes::_i2l:
1411 #ifdef _LP64
1412 __ movl2ptr(dest->as_register_lo(), src->as_register());
1413 #else
1414 move_regs(src->as_register(), dest->as_register_lo());
1415 move_regs(src->as_register(), dest->as_register_hi());
1416 __ sarl(dest->as_register_hi(), 31);
1417 #endif // LP64
1418 break;
1419
1420 case Bytecodes::_l2i:
1421 #ifdef _LP64
1422 __ movl(dest->as_register(), src->as_register_lo());
1423 #else
1424 move_regs(src->as_register_lo(), dest->as_register());
1425 #endif
1426 break;
1427
1428 case Bytecodes::_i2b:
1429 move_regs(src->as_register(), dest->as_register());
1430 __ sign_extend_byte(dest->as_register());
1431 break;
1432
1433 case Bytecodes::_i2c:
1434 move_regs(src->as_register(), dest->as_register());
1435 __ andl(dest->as_register(), 0xFFFF);
1436 break;
1437
1438 case Bytecodes::_i2s:
1439 move_regs(src->as_register(), dest->as_register());
1440 __ sign_extend_short(dest->as_register());
1441 break;
1442
1443
1444 case Bytecodes::_f2d:
1445 case Bytecodes::_d2f:
1446 if (dest->is_single_xmm()) {
1447 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1448 } else if (dest->is_double_xmm()) {
1449 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1450 } else {
1451 assert(src->fpu() == dest->fpu(), "register must be equal");
1452 // do nothing (float result is rounded later through spilling)
1453 }
1454 break;
1455
1456 case Bytecodes::_i2f:
1457 case Bytecodes::_i2d:
1458 if (dest->is_single_xmm()) {
1459 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1460 } else if (dest->is_double_xmm()) {
1461 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1462 } else {
1463 assert(dest->fpu() == 0, "result must be on TOS");
1464 __ movl(Address(rsp, 0), src->as_register());
1465 __ fild_s(Address(rsp, 0));
1466 }
1467 break;
1468
1469 case Bytecodes::_f2i:
1470 case Bytecodes::_d2i:
1471 if (src->is_single_xmm()) {
1472 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1473 } else if (src->is_double_xmm()) {
1474 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1475 } else {
1476 assert(src->fpu() == 0, "input must be on TOS");
1477 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1478 __ fist_s(Address(rsp, 0));
1479 __ movl(dest->as_register(), Address(rsp, 0));
1480 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1481 }
1482
1483 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1484 assert(op->stub() != NULL, "stub required");
1485 __ cmpl(dest->as_register(), 0x80000000);
1486 __ jcc(Assembler::equal, *op->stub()->entry());
1487 __ bind(*op->stub()->continuation());
1488 break;
1489
1490 case Bytecodes::_l2f:
1491 case Bytecodes::_l2d:
1492 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1493 assert(dest->fpu() == 0, "result must be on TOS");
1494
1495 __ movptr(Address(rsp, 0), src->as_register_lo());
1496 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1497 __ fild_d(Address(rsp, 0));
1498 // float result is rounded later through spilling
1499 break;
1500
1501 case Bytecodes::_f2l:
1502 case Bytecodes::_d2l:
1503 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1504 assert(src->fpu() == 0, "input must be on TOS");
1505 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1506
1507 // instruction sequence too long to inline it here
1508 {
1509 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1510 }
1511 break;
1512
1513 default: ShouldNotReachHere();
1514 }
1515 }
1516
1517 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1518 if (op->init_check()) {
1519 __ cmpb(Address(op->klass()->as_register(),
1520 InstanceKlass::init_state_offset()),
1521 InstanceKlass::fully_initialized);
1522 add_debug_info_for_null_check_here(op->stub()->info());
1523 __ jcc(Assembler::notEqual, *op->stub()->entry());
1524 }
1525 __ allocate_object(op->obj()->as_register(),
1526 op->tmp1()->as_register(),
1527 op->tmp2()->as_register(),
1528 op->header_size(),
1529 op->object_size(),
1530 op->klass()->as_register(),
1531 *op->stub()->entry());
1532 __ bind(*op->stub()->continuation());
1533 }
1534
1535 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1536 Register len = op->len()->as_register();
1537 LP64_ONLY( __ movslq(len, len); )
1538
1539 if (UseSlowPath ||
1540 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1541 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1542 __ jmp(*op->stub()->entry());
1543 } else {
1544 Register tmp1 = op->tmp1()->as_register();
1545 Register tmp2 = op->tmp2()->as_register();
1546 Register tmp3 = op->tmp3()->as_register();
1547 if (len == tmp1) {
1548 tmp1 = tmp3;
1549 } else if (len == tmp2) {
1550 tmp2 = tmp3;
1551 } else if (len == tmp3) {
1552 // everything is ok
1553 } else {
1554 __ mov(tmp3, len);
1555 }
1556 __ allocate_array(op->obj()->as_register(),
1557 len,
1558 tmp1,
1559 tmp2,
1560 arrayOopDesc::header_size(op->type()),
1561 array_element_size(op->type()),
1562 op->klass()->as_register(),
1563 *op->stub()->entry());
1564 }
1565 __ bind(*op->stub()->continuation());
1566 }
1567
1568 void LIR_Assembler::type_profile_helper(Register mdo,
1569 ciMethodData *md, ciProfileData *data,
1570 Register recv, Label* update_done) {
1571 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1572 Label next_test;
1573 // See if the receiver is receiver[n].
1574 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1575 __ jccb(Assembler::notEqual, next_test);
1576 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1577 __ addptr(data_addr, DataLayout::counter_increment);
1578 __ jmp(*update_done);
1579 __ bind(next_test);
1580 }
1581
1582 // Didn't find receiver; find next empty slot and fill it in
1583 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1584 Label next_test;
1585 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1586 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1587 __ jccb(Assembler::notEqual, next_test);
1588 __ movptr(recv_addr, recv);
1589 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1590 __ jmp(*update_done);
1591 __ bind(next_test);
1592 }
1593 }
1594
1595 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1596 // we always need a stub for the failure case.
1597 CodeStub* stub = op->stub();
1598 Register obj = op->object()->as_register();
1599 Register k_RInfo = op->tmp1()->as_register();
1600 Register klass_RInfo = op->tmp2()->as_register();
1601 Register dst = op->result_opr()->as_register();
1602 ciKlass* k = op->klass();
1603 Register Rtmp1 = noreg;
1604
1605 // check if it needs to be profiled
1606 ciMethodData* md = NULL;
1607 ciProfileData* data = NULL;
1608
1609 if (op->should_profile()) {
1610 ciMethod* method = op->profiled_method();
1611 assert(method != NULL, "Should have method");
1612 int bci = op->profiled_bci();
1613 md = method->method_data_or_null();
1614 assert(md != NULL, "Sanity");
1615 data = md->bci_to_data(bci);
1616 assert(data != NULL, "need data for type check");
1617 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1618 }
1619 Label profile_cast_success, profile_cast_failure;
1620 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1621 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1622
1623 if (obj == k_RInfo) {
1624 k_RInfo = dst;
1625 } else if (obj == klass_RInfo) {
1626 klass_RInfo = dst;
1627 }
1628 if (k->is_loaded() && !UseCompressedClassPointers) {
1629 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1630 } else {
1631 Rtmp1 = op->tmp3()->as_register();
1632 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1633 }
1634
1635 assert_different_registers(obj, k_RInfo, klass_RInfo);
1636
1637 __ cmpptr(obj, (int32_t)NULL_WORD);
1638 if (op->should_profile()) {
1639 Label not_null;
1640 __ jccb(Assembler::notEqual, not_null);
1641 // Object is null; update MDO and exit
1642 Register mdo = klass_RInfo;
1643 __ mov_metadata(mdo, md->constant_encoding());
1644 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1645 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1646 __ orl(data_addr, header_bits);
1647 __ jmp(*obj_is_null);
1648 __ bind(not_null);
1649 } else {
1650 __ jcc(Assembler::equal, *obj_is_null);
1651 }
1652
1653 if (!k->is_loaded()) {
1654 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1655 } else {
1656 #ifdef _LP64
1657 __ mov_metadata(k_RInfo, k->constant_encoding());
1658 #endif // _LP64
1659 }
1660 __ verify_oop(obj);
1661
1662 if (op->fast_check()) {
1663 // get object class
1664 // not a safepoint as obj null check happens earlier
1665 #ifdef _LP64
1666 if (UseCompressedClassPointers) {
1667 __ load_klass(Rtmp1, obj);
1668 __ cmpptr(k_RInfo, Rtmp1);
1669 } else {
1670 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1671 }
1672 #else
1673 if (k->is_loaded()) {
1674 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1675 } else {
1676 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1677 }
1678 #endif
1679 __ jcc(Assembler::notEqual, *failure_target);
1680 // successful cast, fall through to profile or jump
1681 } else {
1682 // get object class
1683 // not a safepoint as obj null check happens earlier
1684 __ load_klass(klass_RInfo, obj);
1685 if (k->is_loaded()) {
1686 // See if we get an immediate positive hit
1687 #ifdef _LP64
1688 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1689 #else
1690 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1691 #endif // _LP64
1692 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1693 __ jcc(Assembler::notEqual, *failure_target);
1694 // successful cast, fall through to profile or jump
1695 } else {
1696 // See if we get an immediate positive hit
1697 __ jcc(Assembler::equal, *success_target);
1698 // check for self
1699 #ifdef _LP64
1700 __ cmpptr(klass_RInfo, k_RInfo);
1701 #else
1702 __ cmpklass(klass_RInfo, k->constant_encoding());
1703 #endif // _LP64
1704 __ jcc(Assembler::equal, *success_target);
1705
1706 __ push(klass_RInfo);
1707 #ifdef _LP64
1708 __ push(k_RInfo);
1709 #else
1710 __ pushklass(k->constant_encoding());
1711 #endif // _LP64
1712 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1713 __ pop(klass_RInfo);
1714 __ pop(klass_RInfo);
1715 // result is a boolean
1716 __ cmpl(klass_RInfo, 0);
1717 __ jcc(Assembler::equal, *failure_target);
1718 // successful cast, fall through to profile or jump
1719 }
1720 } else {
1721 // perform the fast part of the checking logic
1722 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1723 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1724 __ push(klass_RInfo);
1725 __ push(k_RInfo);
1726 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1727 __ pop(klass_RInfo);
1728 __ pop(k_RInfo);
1729 // result is a boolean
1730 __ cmpl(k_RInfo, 0);
1731 __ jcc(Assembler::equal, *failure_target);
1732 // successful cast, fall through to profile or jump
1733 }
1734 }
1735 if (op->should_profile()) {
1736 Register mdo = klass_RInfo, recv = k_RInfo;
1737 __ bind(profile_cast_success);
1738 __ mov_metadata(mdo, md->constant_encoding());
1739 __ load_klass(recv, obj);
1740 Label update_done;
1741 type_profile_helper(mdo, md, data, recv, success);
1742 __ jmp(*success);
1743
1744 __ bind(profile_cast_failure);
1745 __ mov_metadata(mdo, md->constant_encoding());
1746 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1747 __ subptr(counter_addr, DataLayout::counter_increment);
1748 __ jmp(*failure);
1749 }
1750 __ jmp(*success);
1751 }
1752
1753
1754 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1755 LIR_Code code = op->code();
1756 if (code == lir_store_check) {
1757 Register value = op->object()->as_register();
1758 Register array = op->array()->as_register();
1759 Register k_RInfo = op->tmp1()->as_register();
1760 Register klass_RInfo = op->tmp2()->as_register();
1761 Register Rtmp1 = op->tmp3()->as_register();
1762
1763 CodeStub* stub = op->stub();
1764
1765 // check if it needs to be profiled
1766 ciMethodData* md = NULL;
1767 ciProfileData* data = NULL;
1768
1769 if (op->should_profile()) {
1770 ciMethod* method = op->profiled_method();
1771 assert(method != NULL, "Should have method");
1772 int bci = op->profiled_bci();
1773 md = method->method_data_or_null();
1774 assert(md != NULL, "Sanity");
1775 data = md->bci_to_data(bci);
1776 assert(data != NULL, "need data for type check");
1777 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1778 }
1779 Label profile_cast_success, profile_cast_failure, done;
1780 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1781 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1782
1783 __ cmpptr(value, (int32_t)NULL_WORD);
1784 if (op->should_profile()) {
1785 Label not_null;
1786 __ jccb(Assembler::notEqual, not_null);
1787 // Object is null; update MDO and exit
1788 Register mdo = klass_RInfo;
1789 __ mov_metadata(mdo, md->constant_encoding());
1790 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1791 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1792 __ orl(data_addr, header_bits);
1793 __ jmp(done);
1794 __ bind(not_null);
1795 } else {
1796 __ jcc(Assembler::equal, done);
1797 }
1798
1799 add_debug_info_for_null_check_here(op->info_for_exception());
1800 __ load_klass(k_RInfo, array);
1801 __ load_klass(klass_RInfo, value);
1802
1803 // get instance klass (it's already uncompressed)
1804 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1805 // perform the fast part of the checking logic
1806 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1807 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1808 __ push(klass_RInfo);
1809 __ push(k_RInfo);
1810 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1811 __ pop(klass_RInfo);
1812 __ pop(k_RInfo);
1813 // result is a boolean
1814 __ cmpl(k_RInfo, 0);
1815 __ jcc(Assembler::equal, *failure_target);
1816 // fall through to the success case
1817
1818 if (op->should_profile()) {
1819 Register mdo = klass_RInfo, recv = k_RInfo;
1820 __ bind(profile_cast_success);
1821 __ mov_metadata(mdo, md->constant_encoding());
1822 __ load_klass(recv, value);
1823 Label update_done;
1824 type_profile_helper(mdo, md, data, recv, &done);
1825 __ jmpb(done);
1826
1827 __ bind(profile_cast_failure);
1828 __ mov_metadata(mdo, md->constant_encoding());
1829 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1830 __ subptr(counter_addr, DataLayout::counter_increment);
1831 __ jmp(*stub->entry());
1832 }
1833
1834 __ bind(done);
1835 } else
1836 if (code == lir_checkcast) {
1837 Register obj = op->object()->as_register();
1838 Register dst = op->result_opr()->as_register();
1839 Label success;
1840 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1841 __ bind(success);
1842 if (dst != obj) {
1843 __ mov(dst, obj);
1844 }
1845 } else
1846 if (code == lir_instanceof) {
1847 Register obj = op->object()->as_register();
1848 Register dst = op->result_opr()->as_register();
1849 Label success, failure, done;
1850 emit_typecheck_helper(op, &success, &failure, &failure);
1851 __ bind(failure);
1852 __ xorptr(dst, dst);
1853 __ jmpb(done);
1854 __ bind(success);
1855 __ movptr(dst, 1);
1856 __ bind(done);
1857 } else {
1858 ShouldNotReachHere();
1859 }
1860
1861 }
1862
1863
1864 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1865 LIR_Address* address = op->addr()->as_address_ptr();
1866 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1867 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1868 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1869 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1870 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1871 Register addr = address->base()->as_pointer_register();
1872 if (os::is_MP()) {
1873 __ lock();
1874 }
1875 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1876
1877 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1878 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1879 Register addr = address->base()->as_pointer_register();
1880 Register newval = op->new_value()->as_register();
1881 Register cmpval = op->cmp_value()->as_register();
1882 assert(cmpval == rax, "wrong register");
1883 assert(newval != NULL, "new val must be register");
1884 assert(cmpval != newval, "cmp and new values must be in different registers");
1885 assert(cmpval != addr, "cmp and addr must be in different registers");
1886 assert(newval != addr, "new value and addr must be in different registers");
1887
1888 if ( op->code() == lir_cas_obj) {
1889 #ifdef _LP64
1890 if (UseCompressedOops) {
1891 __ encode_heap_oop(cmpval);
1892 __ mov(rscratch1, newval);
1893 __ encode_heap_oop(rscratch1);
1894 if (os::is_MP()) {
1895 __ lock();
1896 }
1897 // cmpval (rax) is implicitly used by this instruction
1898 __ cmpxchgl(rscratch1, Address(addr, 0));
1899 } else
1900 #endif
1901 {
1902 if (os::is_MP()) {
1903 __ lock();
1904 }
1905 __ cmpxchgptr(newval, Address(addr, 0));
1906 }
1907 } else {
1908 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1909 if (os::is_MP()) {
1910 __ lock();
1911 }
1912 __ cmpxchgl(newval, Address(addr, 0));
1913 }
1914 #ifdef _LP64
1915 } else if (op->code() == lir_cas_long) {
1916 Register addr = address->base()->as_pointer_register();
1917 Register newval = op->new_value()->as_register_lo();
1918 Register cmpval = op->cmp_value()->as_register_lo();
1919 assert(cmpval == rax, "wrong register");
1920 assert(newval != NULL, "new val must be register");
1921 assert(cmpval != newval, "cmp and new values must be in different registers");
1922 assert(cmpval != addr, "cmp and addr must be in different registers");
1923 assert(newval != addr, "new value and addr must be in different registers");
1924 if (os::is_MP()) {
1925 __ lock();
1926 }
1927 __ cmpxchgq(newval, Address(addr, 0));
1928 #endif // _LP64
1929 } else {
1930 Unimplemented();
1931 }
1932 }
1933
1934 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1935 Assembler::Condition acond, ncond;
1936 switch (condition) {
1937 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1938 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1939 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1940 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1941 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1942 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1943 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1944 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1945 default: acond = Assembler::equal; ncond = Assembler::notEqual;
1946 ShouldNotReachHere();
1947 }
1948
1949 if (opr1->is_cpu_register()) {
1950 reg2reg(opr1, result);
1951 } else if (opr1->is_stack()) {
1952 stack2reg(opr1, result, result->type());
1953 } else if (opr1->is_constant()) {
1954 const2reg(opr1, result, lir_patch_none, NULL);
1955 } else {
1956 ShouldNotReachHere();
1957 }
1958
1959 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
1960 // optimized version that does not require a branch
1961 if (opr2->is_single_cpu()) {
1962 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1963 __ cmov(ncond, result->as_register(), opr2->as_register());
1964 } else if (opr2->is_double_cpu()) {
1965 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1966 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1967 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
1968 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
1969 } else if (opr2->is_single_stack()) {
1970 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
1971 } else if (opr2->is_double_stack()) {
1972 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
1973 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
1974 } else {
1975 ShouldNotReachHere();
1976 }
1977
1978 } else {
1979 Label skip;
1980 __ jcc (acond, skip);
1981 if (opr2->is_cpu_register()) {
1982 reg2reg(opr2, result);
1983 } else if (opr2->is_stack()) {
1984 stack2reg(opr2, result, result->type());
1985 } else if (opr2->is_constant()) {
1986 const2reg(opr2, result, lir_patch_none, NULL);
1987 } else {
1988 ShouldNotReachHere();
1989 }
1990 __ bind(skip);
1991 }
1992 }
1993
1994
1995 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1996 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1997
1998 if (left->is_single_cpu()) {
1999 assert(left == dest, "left and dest must be equal");
2000 Register lreg = left->as_register();
2001
2002 if (right->is_single_cpu()) {
2003 // cpu register - cpu register
2004 Register rreg = right->as_register();
2005 switch (code) {
2006 case lir_add: __ addl (lreg, rreg); break;
2007 case lir_sub: __ subl (lreg, rreg); break;
2008 case lir_mul: __ imull(lreg, rreg); break;
2009 default: ShouldNotReachHere();
2010 }
2011
2012 } else if (right->is_stack()) {
2013 // cpu register - stack
2014 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2015 switch (code) {
2016 case lir_add: __ addl(lreg, raddr); break;
2017 case lir_sub: __ subl(lreg, raddr); break;
2018 default: ShouldNotReachHere();
2019 }
2020
2021 } else if (right->is_constant()) {
2022 // cpu register - constant
2023 jint c = right->as_constant_ptr()->as_jint();
2024 switch (code) {
2025 case lir_add: {
2026 __ incrementl(lreg, c);
2027 break;
2028 }
2029 case lir_sub: {
2030 __ decrementl(lreg, c);
2031 break;
2032 }
2033 default: ShouldNotReachHere();
2034 }
2035
2036 } else {
2037 ShouldNotReachHere();
2038 }
2039
2040 } else if (left->is_double_cpu()) {
2041 assert(left == dest, "left and dest must be equal");
2042 Register lreg_lo = left->as_register_lo();
2043 Register lreg_hi = left->as_register_hi();
2044
2045 if (right->is_double_cpu()) {
2046 // cpu register - cpu register
2047 Register rreg_lo = right->as_register_lo();
2048 Register rreg_hi = right->as_register_hi();
2049 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2050 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2051 switch (code) {
2052 case lir_add:
2053 __ addptr(lreg_lo, rreg_lo);
2054 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2055 break;
2056 case lir_sub:
2057 __ subptr(lreg_lo, rreg_lo);
2058 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2059 break;
2060 case lir_mul:
2061 #ifdef _LP64
2062 __ imulq(lreg_lo, rreg_lo);
2063 #else
2064 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2065 __ imull(lreg_hi, rreg_lo);
2066 __ imull(rreg_hi, lreg_lo);
2067 __ addl (rreg_hi, lreg_hi);
2068 __ mull (rreg_lo);
2069 __ addl (lreg_hi, rreg_hi);
2070 #endif // _LP64
2071 break;
2072 default:
2073 ShouldNotReachHere();
2074 }
2075
2076 } else if (right->is_constant()) {
2077 // cpu register - constant
2078 #ifdef _LP64
2079 jlong c = right->as_constant_ptr()->as_jlong_bits();
2080 __ movptr(r10, (intptr_t) c);
2081 switch (code) {
2082 case lir_add:
2083 __ addptr(lreg_lo, r10);
2084 break;
2085 case lir_sub:
2086 __ subptr(lreg_lo, r10);
2087 break;
2088 default:
2089 ShouldNotReachHere();
2090 }
2091 #else
2092 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2093 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2094 switch (code) {
2095 case lir_add:
2096 __ addptr(lreg_lo, c_lo);
2097 __ adcl(lreg_hi, c_hi);
2098 break;
2099 case lir_sub:
2100 __ subptr(lreg_lo, c_lo);
2101 __ sbbl(lreg_hi, c_hi);
2102 break;
2103 default:
2104 ShouldNotReachHere();
2105 }
2106 #endif // _LP64
2107
2108 } else {
2109 ShouldNotReachHere();
2110 }
2111
2112 } else if (left->is_single_xmm()) {
2113 assert(left == dest, "left and dest must be equal");
2114 XMMRegister lreg = left->as_xmm_float_reg();
2115
2116 if (right->is_single_xmm()) {
2117 XMMRegister rreg = right->as_xmm_float_reg();
2118 switch (code) {
2119 case lir_add: __ addss(lreg, rreg); break;
2120 case lir_sub: __ subss(lreg, rreg); break;
2121 case lir_mul_strictfp: // fall through
2122 case lir_mul: __ mulss(lreg, rreg); break;
2123 case lir_div_strictfp: // fall through
2124 case lir_div: __ divss(lreg, rreg); break;
2125 default: ShouldNotReachHere();
2126 }
2127 } else {
2128 Address raddr;
2129 if (right->is_single_stack()) {
2130 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2131 } else if (right->is_constant()) {
2132 // hack for now
2133 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2134 } else {
2135 ShouldNotReachHere();
2136 }
2137 switch (code) {
2138 case lir_add: __ addss(lreg, raddr); break;
2139 case lir_sub: __ subss(lreg, raddr); break;
2140 case lir_mul_strictfp: // fall through
2141 case lir_mul: __ mulss(lreg, raddr); break;
2142 case lir_div_strictfp: // fall through
2143 case lir_div: __ divss(lreg, raddr); break;
2144 default: ShouldNotReachHere();
2145 }
2146 }
2147
2148 } else if (left->is_double_xmm()) {
2149 assert(left == dest, "left and dest must be equal");
2150
2151 XMMRegister lreg = left->as_xmm_double_reg();
2152 if (right->is_double_xmm()) {
2153 XMMRegister rreg = right->as_xmm_double_reg();
2154 switch (code) {
2155 case lir_add: __ addsd(lreg, rreg); break;
2156 case lir_sub: __ subsd(lreg, rreg); break;
2157 case lir_mul_strictfp: // fall through
2158 case lir_mul: __ mulsd(lreg, rreg); break;
2159 case lir_div_strictfp: // fall through
2160 case lir_div: __ divsd(lreg, rreg); break;
2161 default: ShouldNotReachHere();
2162 }
2163 } else {
2164 Address raddr;
2165 if (right->is_double_stack()) {
2166 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2167 } else if (right->is_constant()) {
2168 // hack for now
2169 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2170 } else {
2171 ShouldNotReachHere();
2172 }
2173 switch (code) {
2174 case lir_add: __ addsd(lreg, raddr); break;
2175 case lir_sub: __ subsd(lreg, raddr); break;
2176 case lir_mul_strictfp: // fall through
2177 case lir_mul: __ mulsd(lreg, raddr); break;
2178 case lir_div_strictfp: // fall through
2179 case lir_div: __ divsd(lreg, raddr); break;
2180 default: ShouldNotReachHere();
2181 }
2182 }
2183
2184 } else if (left->is_single_fpu()) {
2185 assert(dest->is_single_fpu(), "fpu stack allocation required");
2186
2187 if (right->is_single_fpu()) {
2188 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2189
2190 } else {
2191 assert(left->fpu_regnr() == 0, "left must be on TOS");
2192 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2193
2194 Address raddr;
2195 if (right->is_single_stack()) {
2196 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2197 } else if (right->is_constant()) {
2198 address const_addr = float_constant(right->as_jfloat());
2199 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2200 // hack for now
2201 raddr = __ as_Address(InternalAddress(const_addr));
2202 } else {
2203 ShouldNotReachHere();
2204 }
2205
2206 switch (code) {
2207 case lir_add: __ fadd_s(raddr); break;
2208 case lir_sub: __ fsub_s(raddr); break;
2209 case lir_mul_strictfp: // fall through
2210 case lir_mul: __ fmul_s(raddr); break;
2211 case lir_div_strictfp: // fall through
2212 case lir_div: __ fdiv_s(raddr); break;
2213 default: ShouldNotReachHere();
2214 }
2215 }
2216
2217 } else if (left->is_double_fpu()) {
2218 assert(dest->is_double_fpu(), "fpu stack allocation required");
2219
2220 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2221 // Double values require special handling for strictfp mul/div on x86
2222 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2223 __ fmulp(left->fpu_regnrLo() + 1);
2224 }
2225
2226 if (right->is_double_fpu()) {
2227 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2228
2229 } else {
2230 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2231 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2232
2233 Address raddr;
2234 if (right->is_double_stack()) {
2235 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2236 } else if (right->is_constant()) {
2237 // hack for now
2238 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2239 } else {
2240 ShouldNotReachHere();
2241 }
2242
2243 switch (code) {
2244 case lir_add: __ fadd_d(raddr); break;
2245 case lir_sub: __ fsub_d(raddr); break;
2246 case lir_mul_strictfp: // fall through
2247 case lir_mul: __ fmul_d(raddr); break;
2248 case lir_div_strictfp: // fall through
2249 case lir_div: __ fdiv_d(raddr); break;
2250 default: ShouldNotReachHere();
2251 }
2252 }
2253
2254 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2255 // Double values require special handling for strictfp mul/div on x86
2256 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2257 __ fmulp(dest->fpu_regnrLo() + 1);
2258 }
2259
2260 } else if (left->is_single_stack() || left->is_address()) {
2261 assert(left == dest, "left and dest must be equal");
2262
2263 Address laddr;
2264 if (left->is_single_stack()) {
2265 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2266 } else if (left->is_address()) {
2267 laddr = as_Address(left->as_address_ptr());
2268 } else {
2269 ShouldNotReachHere();
2270 }
2271
2272 if (right->is_single_cpu()) {
2273 Register rreg = right->as_register();
2274 switch (code) {
2275 case lir_add: __ addl(laddr, rreg); break;
2276 case lir_sub: __ subl(laddr, rreg); break;
2277 default: ShouldNotReachHere();
2278 }
2279 } else if (right->is_constant()) {
2280 jint c = right->as_constant_ptr()->as_jint();
2281 switch (code) {
2282 case lir_add: {
2283 __ incrementl(laddr, c);
2284 break;
2285 }
2286 case lir_sub: {
2287 __ decrementl(laddr, c);
2288 break;
2289 }
2290 default: ShouldNotReachHere();
2291 }
2292 } else {
2293 ShouldNotReachHere();
2294 }
2295
2296 } else {
2297 ShouldNotReachHere();
2298 }
2299 }
2300
2301 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2302 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2303 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2304 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2305
2306 bool left_is_tos = (left_index == 0);
2307 bool dest_is_tos = (dest_index == 0);
2308 int non_tos_index = (left_is_tos ? right_index : left_index);
2309
2310 switch (code) {
2311 case lir_add:
2312 if (pop_fpu_stack) __ faddp(non_tos_index);
2313 else if (dest_is_tos) __ fadd (non_tos_index);
2314 else __ fadda(non_tos_index);
2315 break;
2316
2317 case lir_sub:
2318 if (left_is_tos) {
2319 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2320 else if (dest_is_tos) __ fsub (non_tos_index);
2321 else __ fsubra(non_tos_index);
2322 } else {
2323 if (pop_fpu_stack) __ fsubp (non_tos_index);
2324 else if (dest_is_tos) __ fsubr (non_tos_index);
2325 else __ fsuba (non_tos_index);
2326 }
2327 break;
2328
2329 case lir_mul_strictfp: // fall through
2330 case lir_mul:
2331 if (pop_fpu_stack) __ fmulp(non_tos_index);
2332 else if (dest_is_tos) __ fmul (non_tos_index);
2333 else __ fmula(non_tos_index);
2334 break;
2335
2336 case lir_div_strictfp: // fall through
2337 case lir_div:
2338 if (left_is_tos) {
2339 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2340 else if (dest_is_tos) __ fdiv (non_tos_index);
2341 else __ fdivra(non_tos_index);
2342 } else {
2343 if (pop_fpu_stack) __ fdivp (non_tos_index);
2344 else if (dest_is_tos) __ fdivr (non_tos_index);
2345 else __ fdiva (non_tos_index);
2346 }
2347 break;
2348
2349 case lir_rem:
2350 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2351 __ fremr(noreg);
2352 break;
2353
2354 default:
2355 ShouldNotReachHere();
2356 }
2357 }
2358
2359
2360 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2361 if (value->is_double_xmm()) {
2362 switch(code) {
2363 case lir_abs :
2364 {
2365 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2366 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2367 }
2368 __ andpd(dest->as_xmm_double_reg(),
2369 ExternalAddress((address)double_signmask_pool));
2370 }
2371 break;
2372
2373 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2374 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2375 default : ShouldNotReachHere();
2376 }
2377
2378 } else if (value->is_double_fpu()) {
2379 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2380 switch(code) {
2381 case lir_abs : __ fabs() ; break;
2382 case lir_sqrt : __ fsqrt(); break;
2383 default : ShouldNotReachHere();
2384 }
2385 } else {
2386 Unimplemented();
2387 }
2388 }
2389
2390 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2391 // assert(left->destroys_register(), "check");
2392 if (left->is_single_cpu()) {
2393 Register reg = left->as_register();
2394 if (right->is_constant()) {
2395 int val = right->as_constant_ptr()->as_jint();
2396 switch (code) {
2397 case lir_logic_and: __ andl (reg, val); break;
2398 case lir_logic_or: __ orl (reg, val); break;
2399 case lir_logic_xor: __ xorl (reg, val); break;
2400 default: ShouldNotReachHere();
2401 }
2402 } else if (right->is_stack()) {
2403 // added support for stack operands
2404 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2405 switch (code) {
2406 case lir_logic_and: __ andl (reg, raddr); break;
2407 case lir_logic_or: __ orl (reg, raddr); break;
2408 case lir_logic_xor: __ xorl (reg, raddr); break;
2409 default: ShouldNotReachHere();
2410 }
2411 } else {
2412 Register rright = right->as_register();
2413 switch (code) {
2414 case lir_logic_and: __ andptr (reg, rright); break;
2415 case lir_logic_or : __ orptr (reg, rright); break;
2416 case lir_logic_xor: __ xorptr (reg, rright); break;
2417 default: ShouldNotReachHere();
2418 }
2419 }
2420 move_regs(reg, dst->as_register());
2421 } else {
2422 Register l_lo = left->as_register_lo();
2423 Register l_hi = left->as_register_hi();
2424 if (right->is_constant()) {
2425 #ifdef _LP64
2426 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2427 switch (code) {
2428 case lir_logic_and:
2429 __ andq(l_lo, rscratch1);
2430 break;
2431 case lir_logic_or:
2432 __ orq(l_lo, rscratch1);
2433 break;
2434 case lir_logic_xor:
2435 __ xorq(l_lo, rscratch1);
2436 break;
2437 default: ShouldNotReachHere();
2438 }
2439 #else
2440 int r_lo = right->as_constant_ptr()->as_jint_lo();
2441 int r_hi = right->as_constant_ptr()->as_jint_hi();
2442 switch (code) {
2443 case lir_logic_and:
2444 __ andl(l_lo, r_lo);
2445 __ andl(l_hi, r_hi);
2446 break;
2447 case lir_logic_or:
2448 __ orl(l_lo, r_lo);
2449 __ orl(l_hi, r_hi);
2450 break;
2451 case lir_logic_xor:
2452 __ xorl(l_lo, r_lo);
2453 __ xorl(l_hi, r_hi);
2454 break;
2455 default: ShouldNotReachHere();
2456 }
2457 #endif // _LP64
2458 } else {
2459 #ifdef _LP64
2460 Register r_lo;
2461 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2462 r_lo = right->as_register();
2463 } else {
2464 r_lo = right->as_register_lo();
2465 }
2466 #else
2467 Register r_lo = right->as_register_lo();
2468 Register r_hi = right->as_register_hi();
2469 assert(l_lo != r_hi, "overwriting registers");
2470 #endif
2471 switch (code) {
2472 case lir_logic_and:
2473 __ andptr(l_lo, r_lo);
2474 NOT_LP64(__ andptr(l_hi, r_hi);)
2475 break;
2476 case lir_logic_or:
2477 __ orptr(l_lo, r_lo);
2478 NOT_LP64(__ orptr(l_hi, r_hi);)
2479 break;
2480 case lir_logic_xor:
2481 __ xorptr(l_lo, r_lo);
2482 NOT_LP64(__ xorptr(l_hi, r_hi);)
2483 break;
2484 default: ShouldNotReachHere();
2485 }
2486 }
2487
2488 Register dst_lo = dst->as_register_lo();
2489 Register dst_hi = dst->as_register_hi();
2490
2491 #ifdef _LP64
2492 move_regs(l_lo, dst_lo);
2493 #else
2494 if (dst_lo == l_hi) {
2495 assert(dst_hi != l_lo, "overwriting registers");
2496 move_regs(l_hi, dst_hi);
2497 move_regs(l_lo, dst_lo);
2498 } else {
2499 assert(dst_lo != l_hi, "overwriting registers");
2500 move_regs(l_lo, dst_lo);
2501 move_regs(l_hi, dst_hi);
2502 }
2503 #endif // _LP64
2504 }
2505 }
2506
2507
2508 // we assume that rax, and rdx can be overwritten
2509 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2510
2511 assert(left->is_single_cpu(), "left must be register");
2512 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2513 assert(result->is_single_cpu(), "result must be register");
2514
2515 // assert(left->destroys_register(), "check");
2516 // assert(right->destroys_register(), "check");
2517
2518 Register lreg = left->as_register();
2519 Register dreg = result->as_register();
2520
2521 if (right->is_constant()) {
2522 int divisor = right->as_constant_ptr()->as_jint();
2523 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2524 if (code == lir_idiv) {
2525 assert(lreg == rax, "must be rax,");
2526 assert(temp->as_register() == rdx, "tmp register must be rdx");
2527 __ cdql(); // sign extend into rdx:rax
2528 if (divisor == 2) {
2529 __ subl(lreg, rdx);
2530 } else {
2531 __ andl(rdx, divisor - 1);
2532 __ addl(lreg, rdx);
2533 }
2534 __ sarl(lreg, log2_intptr(divisor));
2535 move_regs(lreg, dreg);
2536 } else if (code == lir_irem) {
2537 Label done;
2538 __ mov(dreg, lreg);
2539 __ andl(dreg, 0x80000000 | (divisor - 1));
2540 __ jcc(Assembler::positive, done);
2541 __ decrement(dreg);
2542 __ orl(dreg, ~(divisor - 1));
2543 __ increment(dreg);
2544 __ bind(done);
2545 } else {
2546 ShouldNotReachHere();
2547 }
2548 } else {
2549 Register rreg = right->as_register();
2550 assert(lreg == rax, "left register must be rax,");
2551 assert(rreg != rdx, "right register must not be rdx");
2552 assert(temp->as_register() == rdx, "tmp register must be rdx");
2553
2554 move_regs(lreg, rax);
2555
2556 int idivl_offset = __ corrected_idivl(rreg);
2557 add_debug_info_for_div0(idivl_offset, info);
2558 if (code == lir_irem) {
2559 move_regs(rdx, dreg); // result is in rdx
2560 } else {
2561 move_regs(rax, dreg);
2562 }
2563 }
2564 }
2565
2566
2567 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2568 if (opr1->is_single_cpu()) {
2569 Register reg1 = opr1->as_register();
2570 if (opr2->is_single_cpu()) {
2571 // cpu register - cpu register
2572 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2573 __ cmpptr(reg1, opr2->as_register());
2574 } else {
2575 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2576 __ cmpl(reg1, opr2->as_register());
2577 }
2578 } else if (opr2->is_stack()) {
2579 // cpu register - stack
2580 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2581 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2582 } else {
2583 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2584 }
2585 } else if (opr2->is_constant()) {
2586 // cpu register - constant
2587 LIR_Const* c = opr2->as_constant_ptr();
2588 if (c->type() == T_INT) {
2589 __ cmpl(reg1, c->as_jint());
2590 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2591 // In 64bit oops are single register
2592 jobject o = c->as_jobject();
2593 if (o == NULL) {
2594 __ cmpptr(reg1, (int32_t)NULL_WORD);
2595 } else {
2596 #ifdef _LP64
2597 __ movoop(rscratch1, o);
2598 __ cmpptr(reg1, rscratch1);
2599 #else
2600 __ cmpoop(reg1, c->as_jobject());
2601 #endif // _LP64
2602 }
2603 } else {
2604 fatal("unexpected type: %s", basictype_to_str(c->type()));
2605 }
2606 // cpu register - address
2607 } else if (opr2->is_address()) {
2608 if (op->info() != NULL) {
2609 add_debug_info_for_null_check_here(op->info());
2610 }
2611 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2612 } else {
2613 ShouldNotReachHere();
2614 }
2615
2616 } else if(opr1->is_double_cpu()) {
2617 Register xlo = opr1->as_register_lo();
2618 Register xhi = opr1->as_register_hi();
2619 if (opr2->is_double_cpu()) {
2620 #ifdef _LP64
2621 __ cmpptr(xlo, opr2->as_register_lo());
2622 #else
2623 // cpu register - cpu register
2624 Register ylo = opr2->as_register_lo();
2625 Register yhi = opr2->as_register_hi();
2626 __ subl(xlo, ylo);
2627 __ sbbl(xhi, yhi);
2628 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2629 __ orl(xhi, xlo);
2630 }
2631 #endif // _LP64
2632 } else if (opr2->is_constant()) {
2633 // cpu register - constant 0
2634 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2635 #ifdef _LP64
2636 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2637 #else
2638 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2639 __ orl(xhi, xlo);
2640 #endif // _LP64
2641 } else {
2642 ShouldNotReachHere();
2643 }
2644
2645 } else if (opr1->is_single_xmm()) {
2646 XMMRegister reg1 = opr1->as_xmm_float_reg();
2647 if (opr2->is_single_xmm()) {
2648 // xmm register - xmm register
2649 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2650 } else if (opr2->is_stack()) {
2651 // xmm register - stack
2652 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2653 } else if (opr2->is_constant()) {
2654 // xmm register - constant
2655 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2656 } else if (opr2->is_address()) {
2657 // xmm register - address
2658 if (op->info() != NULL) {
2659 add_debug_info_for_null_check_here(op->info());
2660 }
2661 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2662 } else {
2663 ShouldNotReachHere();
2664 }
2665
2666 } else if (opr1->is_double_xmm()) {
2667 XMMRegister reg1 = opr1->as_xmm_double_reg();
2668 if (opr2->is_double_xmm()) {
2669 // xmm register - xmm register
2670 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2671 } else if (opr2->is_stack()) {
2672 // xmm register - stack
2673 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2674 } else if (opr2->is_constant()) {
2675 // xmm register - constant
2676 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2677 } else if (opr2->is_address()) {
2678 // xmm register - address
2679 if (op->info() != NULL) {
2680 add_debug_info_for_null_check_here(op->info());
2681 }
2682 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2683 } else {
2684 ShouldNotReachHere();
2685 }
2686
2687 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2688 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2689 assert(opr2->is_fpu_register(), "both must be registers");
2690 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2691
2692 } else if (opr1->is_address() && opr2->is_constant()) {
2693 LIR_Const* c = opr2->as_constant_ptr();
2694 #ifdef _LP64
2695 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2696 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2697 __ movoop(rscratch1, c->as_jobject());
2698 }
2699 #endif // LP64
2700 if (op->info() != NULL) {
2701 add_debug_info_for_null_check_here(op->info());
2702 }
2703 // special case: address - constant
2704 LIR_Address* addr = opr1->as_address_ptr();
2705 if (c->type() == T_INT) {
2706 __ cmpl(as_Address(addr), c->as_jint());
2707 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2708 #ifdef _LP64
2709 // %%% Make this explode if addr isn't reachable until we figure out a
2710 // better strategy by giving noreg as the temp for as_Address
2711 __ cmpptr(rscratch1, as_Address(addr, noreg));
2712 #else
2713 __ cmpoop(as_Address(addr), c->as_jobject());
2714 #endif // _LP64
2715 } else {
2716 ShouldNotReachHere();
2717 }
2718
2719 } else {
2720 ShouldNotReachHere();
2721 }
2722 }
2723
2724 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2725 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2726 if (left->is_single_xmm()) {
2727 assert(right->is_single_xmm(), "must match");
2728 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2729 } else if (left->is_double_xmm()) {
2730 assert(right->is_double_xmm(), "must match");
2731 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2732
2733 } else {
2734 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2735 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2736
2737 assert(left->fpu() == 0, "left must be on TOS");
2738 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2739 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2740 }
2741 } else {
2742 assert(code == lir_cmp_l2i, "check");
2743 #ifdef _LP64
2744 Label done;
2745 Register dest = dst->as_register();
2746 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2747 __ movl(dest, -1);
2748 __ jccb(Assembler::less, done);
2749 __ set_byte_if_not_zero(dest);
2750 __ movzbl(dest, dest);
2751 __ bind(done);
2752 #else
2753 __ lcmp2int(left->as_register_hi(),
2754 left->as_register_lo(),
2755 right->as_register_hi(),
2756 right->as_register_lo());
2757 move_regs(left->as_register_hi(), dst->as_register());
2758 #endif // _LP64
2759 }
2760 }
2761
2762
2763 void LIR_Assembler::align_call(LIR_Code code) {
2764 if (os::is_MP()) {
2765 // make sure that the displacement word of the call ends up word aligned
2766 int offset = __ offset();
2767 switch (code) {
2768 case lir_static_call:
2769 case lir_optvirtual_call:
2770 case lir_dynamic_call:
2771 offset += NativeCall::displacement_offset;
2772 break;
2773 case lir_icvirtual_call:
2774 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2775 break;
2776 case lir_virtual_call: // currently, sparc-specific for niagara
2777 default: ShouldNotReachHere();
2778 }
2779 __ align(BytesPerWord, offset);
2780 }
2781 }
2782
2783
2784 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2785 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2786 "must be aligned");
2787 __ call(AddressLiteral(op->addr(), rtype));
2788 add_call_info(code_offset(), op->info());
2789 }
2790
2791
2792 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2793 __ ic_call(op->addr());
2794 add_call_info(code_offset(), op->info());
2795 assert(!os::is_MP() ||
2796 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2797 "must be aligned");
2798 }
2799
2800
2801 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2802 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2803 ShouldNotReachHere();
2804 }
2805
2806
2807 void LIR_Assembler::emit_static_call_stub() {
2808 address call_pc = __ pc();
2809 address stub = __ start_a_stub(call_stub_size());
2810 if (stub == NULL) {
2811 bailout("static call stub overflow");
2812 return;
2813 }
2814
2815 int start = __ offset();
2816 if (os::is_MP()) {
2817 // make sure that the displacement word of the call ends up word aligned
2818 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2819 }
2820 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */));
2821 __ mov_metadata(rbx, (Metadata*)NULL);
2822 // must be set to -1 at code generation time
2823 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2824 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2825 __ jump(RuntimeAddress(__ pc()));
2826
2827 if (UseAOT) {
2828 // Trampoline to aot code
2829 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */));
2830 #ifdef _LP64
2831 __ mov64(rax, CONST64(0)); // address is zapped till fixup time.
2832 #else
2833 __ movl(rax, 0xdeadffff); // address is zapped till fixup time.
2834 #endif
2835 __ jmp(rax);
2836 }
2837 assert(__ offset() - start <= call_stub_size(), "stub too big");
2838 __ end_a_stub();
2839 }
2840
2841
2842 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2843 assert(exceptionOop->as_register() == rax, "must match");
2844 assert(exceptionPC->as_register() == rdx, "must match");
2845
2846 // exception object is not added to oop map by LinearScan
2847 // (LinearScan assumes that no oops are in fixed registers)
2848 info->add_register_oop(exceptionOop);
2849 Runtime1::StubID unwind_id;
2850
2851 // get current pc information
2852 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2853 int pc_for_athrow_offset = __ offset();
2854 InternalAddress pc_for_athrow(__ pc());
2855 __ lea(exceptionPC->as_register(), pc_for_athrow);
2856 add_call_info(pc_for_athrow_offset, info); // for exception handler
2857
2858 __ verify_not_null_oop(rax);
2859 // search an exception handler (rax: exception oop, rdx: throwing pc)
2860 if (compilation()->has_fpu_code()) {
2861 unwind_id = Runtime1::handle_exception_id;
2862 } else {
2863 unwind_id = Runtime1::handle_exception_nofpu_id;
2864 }
2865 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2866
2867 // enough room for two byte trap
2868 __ nop();
2869 }
2870
2871
2872 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2873 assert(exceptionOop->as_register() == rax, "must match");
2874
2875 __ jmp(_unwind_handler_entry);
2876 }
2877
2878
2879 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2880
2881 // optimized version for linear scan:
2882 // * count must be already in ECX (guaranteed by LinearScan)
2883 // * left and dest must be equal
2884 // * tmp must be unused
2885 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2886 assert(left == dest, "left and dest must be equal");
2887 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2888
2889 if (left->is_single_cpu()) {
2890 Register value = left->as_register();
2891 assert(value != SHIFT_count, "left cannot be ECX");
2892
2893 switch (code) {
2894 case lir_shl: __ shll(value); break;
2895 case lir_shr: __ sarl(value); break;
2896 case lir_ushr: __ shrl(value); break;
2897 default: ShouldNotReachHere();
2898 }
2899 } else if (left->is_double_cpu()) {
2900 Register lo = left->as_register_lo();
2901 Register hi = left->as_register_hi();
2902 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2903 #ifdef _LP64
2904 switch (code) {
2905 case lir_shl: __ shlptr(lo); break;
2906 case lir_shr: __ sarptr(lo); break;
2907 case lir_ushr: __ shrptr(lo); break;
2908 default: ShouldNotReachHere();
2909 }
2910 #else
2911
2912 switch (code) {
2913 case lir_shl: __ lshl(hi, lo); break;
2914 case lir_shr: __ lshr(hi, lo, true); break;
2915 case lir_ushr: __ lshr(hi, lo, false); break;
2916 default: ShouldNotReachHere();
2917 }
2918 #endif // LP64
2919 } else {
2920 ShouldNotReachHere();
2921 }
2922 }
2923
2924
2925 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2926 if (dest->is_single_cpu()) {
2927 // first move left into dest so that left is not destroyed by the shift
2928 Register value = dest->as_register();
2929 count = count & 0x1F; // Java spec
2930
2931 move_regs(left->as_register(), value);
2932 switch (code) {
2933 case lir_shl: __ shll(value, count); break;
2934 case lir_shr: __ sarl(value, count); break;
2935 case lir_ushr: __ shrl(value, count); break;
2936 default: ShouldNotReachHere();
2937 }
2938 } else if (dest->is_double_cpu()) {
2939 #ifndef _LP64
2940 Unimplemented();
2941 #else
2942 // first move left into dest so that left is not destroyed by the shift
2943 Register value = dest->as_register_lo();
2944 count = count & 0x1F; // Java spec
2945
2946 move_regs(left->as_register_lo(), value);
2947 switch (code) {
2948 case lir_shl: __ shlptr(value, count); break;
2949 case lir_shr: __ sarptr(value, count); break;
2950 case lir_ushr: __ shrptr(value, count); break;
2951 default: ShouldNotReachHere();
2952 }
2953 #endif // _LP64
2954 } else {
2955 ShouldNotReachHere();
2956 }
2957 }
2958
2959
2960 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2961 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2962 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2963 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2964 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
2965 }
2966
2967
2968 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2969 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2970 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2971 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2972 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
2973 }
2974
2975
2976 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2977 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2978 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2979 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2980 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
2981 }
2982
2983
2984 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
2985 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2986 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2987 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2988 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
2989 }
2990
2991
2992 // This code replaces a call to arraycopy; no exception may
2993 // be thrown in this code, they must be thrown in the System.arraycopy
2994 // activation frame; we could save some checks if this would not be the case
2995 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2996 ciArrayKlass* default_type = op->expected_type();
2997 Register src = op->src()->as_register();
2998 Register dst = op->dst()->as_register();
2999 Register src_pos = op->src_pos()->as_register();
3000 Register dst_pos = op->dst_pos()->as_register();
3001 Register length = op->length()->as_register();
3002 Register tmp = op->tmp()->as_register();
3003
3004 CodeStub* stub = op->stub();
3005 int flags = op->flags();
3006 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3007 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3008
3009 // if we don't know anything, just go through the generic arraycopy
3010 if (default_type == NULL) {
3011 Label done;
3012 // save outgoing arguments on stack in case call to System.arraycopy is needed
3013 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3014 // for interpreter calling conventions. Now we have to do it in new style conventions.
3015 // For the moment until C1 gets the new register allocator I just force all the
3016 // args to the right place (except the register args) and then on the back side
3017 // reload the register args properly if we go slow path. Yuck
3018
3019 // These are proper for the calling convention
3020 store_parameter(length, 2);
3021 store_parameter(dst_pos, 1);
3022 store_parameter(dst, 0);
3023
3024 // these are just temporary placements until we need to reload
3025 store_parameter(src_pos, 3);
3026 store_parameter(src, 4);
3027 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3028
3029 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3030
3031 address copyfunc_addr = StubRoutines::generic_arraycopy();
3032
3033 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3034 #ifdef _LP64
3035 // The arguments are in java calling convention so we can trivially shift them to C
3036 // convention
3037 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3038 __ mov(c_rarg0, j_rarg0);
3039 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3040 __ mov(c_rarg1, j_rarg1);
3041 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3042 __ mov(c_rarg2, j_rarg2);
3043 assert_different_registers(c_rarg3, j_rarg4);
3044 __ mov(c_rarg3, j_rarg3);
3045 #ifdef _WIN64
3046 // Allocate abi space for args but be sure to keep stack aligned
3047 __ subptr(rsp, 6*wordSize);
3048 store_parameter(j_rarg4, 4);
3049 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3050 __ call(RuntimeAddress(C_entry));
3051 } else {
3052 #ifndef PRODUCT
3053 if (PrintC1Statistics) {
3054 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3055 }
3056 #endif
3057 __ call(RuntimeAddress(copyfunc_addr));
3058 }
3059 __ addptr(rsp, 6*wordSize);
3060 #else
3061 __ mov(c_rarg4, j_rarg4);
3062 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3063 __ call(RuntimeAddress(C_entry));
3064 } else {
3065 #ifndef PRODUCT
3066 if (PrintC1Statistics) {
3067 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3068 }
3069 #endif
3070 __ call(RuntimeAddress(copyfunc_addr));
3071 }
3072 #endif // _WIN64
3073 #else
3074 __ push(length);
3075 __ push(dst_pos);
3076 __ push(dst);
3077 __ push(src_pos);
3078 __ push(src);
3079
3080 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3081 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack
3082 } else {
3083 #ifndef PRODUCT
3084 if (PrintC1Statistics) {
3085 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3086 }
3087 #endif
3088 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3089 }
3090
3091 #endif // _LP64
3092
3093 __ cmpl(rax, 0);
3094 __ jcc(Assembler::equal, *stub->continuation());
3095
3096 if (copyfunc_addr != NULL) {
3097 __ mov(tmp, rax);
3098 __ xorl(tmp, -1);
3099 }
3100
3101 // Reload values from the stack so they are where the stub
3102 // expects them.
3103 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3104 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3105 __ movptr (length, Address(rsp, 2*BytesPerWord));
3106 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3107 __ movptr (src, Address(rsp, 4*BytesPerWord));
3108
3109 if (copyfunc_addr != NULL) {
3110 __ subl(length, tmp);
3111 __ addl(src_pos, tmp);
3112 __ addl(dst_pos, tmp);
3113 }
3114 __ jmp(*stub->entry());
3115
3116 __ bind(*stub->continuation());
3117 return;
3118 }
3119
3120 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3121
3122 int elem_size = type2aelembytes(basic_type);
3123 Address::ScaleFactor scale;
3124
3125 switch (elem_size) {
3126 case 1 :
3127 scale = Address::times_1;
3128 break;
3129 case 2 :
3130 scale = Address::times_2;
3131 break;
3132 case 4 :
3133 scale = Address::times_4;
3134 break;
3135 case 8 :
3136 scale = Address::times_8;
3137 break;
3138 default:
3139 scale = Address::no_scale;
3140 ShouldNotReachHere();
3141 }
3142
3143 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3144 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3145 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3146 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3147
3148 // length and pos's are all sign extended at this point on 64bit
3149
3150 // test for NULL
3151 if (flags & LIR_OpArrayCopy::src_null_check) {
3152 __ testptr(src, src);
3153 __ jcc(Assembler::zero, *stub->entry());
3154 }
3155 if (flags & LIR_OpArrayCopy::dst_null_check) {
3156 __ testptr(dst, dst);
3157 __ jcc(Assembler::zero, *stub->entry());
3158 }
3159
3160 // If the compiler was not able to prove that exact type of the source or the destination
3161 // of the arraycopy is an array type, check at runtime if the source or the destination is
3162 // an instance type.
3163 if (flags & LIR_OpArrayCopy::type_check) {
3164 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3165 __ load_klass(tmp, dst);
3166 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3167 __ jcc(Assembler::greaterEqual, *stub->entry());
3168 }
3169
3170 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3171 __ load_klass(tmp, src);
3172 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3173 __ jcc(Assembler::greaterEqual, *stub->entry());
3174 }
3175 }
3176
3177 // check if negative
3178 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3179 __ testl(src_pos, src_pos);
3180 __ jcc(Assembler::less, *stub->entry());
3181 }
3182 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3183 __ testl(dst_pos, dst_pos);
3184 __ jcc(Assembler::less, *stub->entry());
3185 }
3186
3187 if (flags & LIR_OpArrayCopy::src_range_check) {
3188 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3189 __ cmpl(tmp, src_length_addr);
3190 __ jcc(Assembler::above, *stub->entry());
3191 }
3192 if (flags & LIR_OpArrayCopy::dst_range_check) {
3193 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3194 __ cmpl(tmp, dst_length_addr);
3195 __ jcc(Assembler::above, *stub->entry());
3196 }
3197
3198 if (flags & LIR_OpArrayCopy::length_positive_check) {
3199 __ testl(length, length);
3200 __ jcc(Assembler::less, *stub->entry());
3201 }
3202
3203 #ifdef _LP64
3204 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3205 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3206 #endif
3207
3208 if (flags & LIR_OpArrayCopy::type_check) {
3209 // We don't know the array types are compatible
3210 if (basic_type != T_OBJECT) {
3211 // Simple test for basic type arrays
3212 if (UseCompressedClassPointers) {
3213 __ movl(tmp, src_klass_addr);
3214 __ cmpl(tmp, dst_klass_addr);
3215 } else {
3216 __ movptr(tmp, src_klass_addr);
3217 __ cmpptr(tmp, dst_klass_addr);
3218 }
3219 __ jcc(Assembler::notEqual, *stub->entry());
3220 } else {
3221 // For object arrays, if src is a sub class of dst then we can
3222 // safely do the copy.
3223 Label cont, slow;
3224
3225 __ push(src);
3226 __ push(dst);
3227
3228 __ load_klass(src, src);
3229 __ load_klass(dst, dst);
3230
3231 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3232
3233 __ push(src);
3234 __ push(dst);
3235 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3236 __ pop(dst);
3237 __ pop(src);
3238
3239 __ cmpl(src, 0);
3240 __ jcc(Assembler::notEqual, cont);
3241
3242 __ bind(slow);
3243 __ pop(dst);
3244 __ pop(src);
3245
3246 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3247 if (copyfunc_addr != NULL) { // use stub if available
3248 // src is not a sub class of dst so we have to do a
3249 // per-element check.
3250
3251 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3252 if ((flags & mask) != mask) {
3253 // Check that at least both of them object arrays.
3254 assert(flags & mask, "one of the two should be known to be an object array");
3255
3256 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3257 __ load_klass(tmp, src);
3258 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3259 __ load_klass(tmp, dst);
3260 }
3261 int lh_offset = in_bytes(Klass::layout_helper_offset());
3262 Address klass_lh_addr(tmp, lh_offset);
3263 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3264 __ cmpl(klass_lh_addr, objArray_lh);
3265 __ jcc(Assembler::notEqual, *stub->entry());
3266 }
3267
3268 // Spill because stubs can use any register they like and it's
3269 // easier to restore just those that we care about.
3270 store_parameter(dst, 0);
3271 store_parameter(dst_pos, 1);
3272 store_parameter(length, 2);
3273 store_parameter(src_pos, 3);
3274 store_parameter(src, 4);
3275
3276 #ifndef _LP64
3277 __ movptr(tmp, dst_klass_addr);
3278 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3279 __ push(tmp);
3280 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3281 __ push(tmp);
3282 __ push(length);
3283 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3284 __ push(tmp);
3285 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3286 __ push(tmp);
3287
3288 __ call_VM_leaf(copyfunc_addr, 5);
3289 #else
3290 __ movl2ptr(length, length); //higher 32bits must be null
3291
3292 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3293 assert_different_registers(c_rarg0, dst, dst_pos, length);
3294 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3295 assert_different_registers(c_rarg1, dst, length);
3296
3297 __ mov(c_rarg2, length);
3298 assert_different_registers(c_rarg2, dst);
3299
3300 #ifdef _WIN64
3301 // Allocate abi space for args but be sure to keep stack aligned
3302 __ subptr(rsp, 6*wordSize);
3303 __ load_klass(c_rarg3, dst);
3304 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3305 store_parameter(c_rarg3, 4);
3306 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3307 __ call(RuntimeAddress(copyfunc_addr));
3308 __ addptr(rsp, 6*wordSize);
3309 #else
3310 __ load_klass(c_rarg4, dst);
3311 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3312 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3313 __ call(RuntimeAddress(copyfunc_addr));
3314 #endif
3315
3316 #endif
3317
3318 #ifndef PRODUCT
3319 if (PrintC1Statistics) {
3320 Label failed;
3321 __ testl(rax, rax);
3322 __ jcc(Assembler::notZero, failed);
3323 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3324 __ bind(failed);
3325 }
3326 #endif
3327
3328 __ testl(rax, rax);
3329 __ jcc(Assembler::zero, *stub->continuation());
3330
3331 #ifndef PRODUCT
3332 if (PrintC1Statistics) {
3333 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3334 }
3335 #endif
3336
3337 __ mov(tmp, rax);
3338
3339 __ xorl(tmp, -1);
3340
3341 // Restore previously spilled arguments
3342 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3343 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3344 __ movptr (length, Address(rsp, 2*BytesPerWord));
3345 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3346 __ movptr (src, Address(rsp, 4*BytesPerWord));
3347
3348
3349 __ subl(length, tmp);
3350 __ addl(src_pos, tmp);
3351 __ addl(dst_pos, tmp);
3352 }
3353
3354 __ jmp(*stub->entry());
3355
3356 __ bind(cont);
3357 __ pop(dst);
3358 __ pop(src);
3359 }
3360 }
3361
3362 #ifdef ASSERT
3363 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3364 // Sanity check the known type with the incoming class. For the
3365 // primitive case the types must match exactly with src.klass and
3366 // dst.klass each exactly matching the default type. For the
3367 // object array case, if no type check is needed then either the
3368 // dst type is exactly the expected type and the src type is a
3369 // subtype which we can't check or src is the same array as dst
3370 // but not necessarily exactly of type default_type.
3371 Label known_ok, halt;
3372 __ mov_metadata(tmp, default_type->constant_encoding());
3373 #ifdef _LP64
3374 if (UseCompressedClassPointers) {
3375 __ encode_klass_not_null(tmp);
3376 }
3377 #endif
3378
3379 if (basic_type != T_OBJECT) {
3380
3381 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3382 else __ cmpptr(tmp, dst_klass_addr);
3383 __ jcc(Assembler::notEqual, halt);
3384 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3385 else __ cmpptr(tmp, src_klass_addr);
3386 __ jcc(Assembler::equal, known_ok);
3387 } else {
3388 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3389 else __ cmpptr(tmp, dst_klass_addr);
3390 __ jcc(Assembler::equal, known_ok);
3391 __ cmpptr(src, dst);
3392 __ jcc(Assembler::equal, known_ok);
3393 }
3394 __ bind(halt);
3395 __ stop("incorrect type information in arraycopy");
3396 __ bind(known_ok);
3397 }
3398 #endif
3399
3400 #ifndef PRODUCT
3401 if (PrintC1Statistics) {
3402 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3403 }
3404 #endif
3405
3406 #ifdef _LP64
3407 assert_different_registers(c_rarg0, dst, dst_pos, length);
3408 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3409 assert_different_registers(c_rarg1, length);
3410 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3411 __ mov(c_rarg2, length);
3412
3413 #else
3414 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3415 store_parameter(tmp, 0);
3416 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3417 store_parameter(tmp, 1);
3418 store_parameter(length, 2);
3419 #endif // _LP64
3420
3421 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3422 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3423 const char *name;
3424 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3425 __ call_VM_leaf(entry, 0);
3426
3427 __ bind(*stub->continuation());
3428 }
3429
3430 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3431 assert(op->crc()->is_single_cpu(), "crc must be register");
3432 assert(op->val()->is_single_cpu(), "byte value must be register");
3433 assert(op->result_opr()->is_single_cpu(), "result must be register");
3434 Register crc = op->crc()->as_register();
3435 Register val = op->val()->as_register();
3436 Register res = op->result_opr()->as_register();
3437
3438 assert_different_registers(val, crc, res);
3439
3440 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3441 __ notl(crc); // ~crc
3442 __ update_byte_crc32(crc, val, res);
3443 __ notl(crc); // ~crc
3444 __ mov(res, crc);
3445 }
3446
3447 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3448 Register obj = op->obj_opr()->as_register(); // may not be an oop
3449 Register hdr = op->hdr_opr()->as_register();
3450 Register lock = op->lock_opr()->as_register();
3451 if (!UseFastLocking) {
3452 __ jmp(*op->stub()->entry());
3453 } else if (op->code() == lir_lock) {
3454 Register scratch = noreg;
3455 if (UseBiasedLocking) {
3456 scratch = op->scratch_opr()->as_register();
3457 }
3458 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3459 // add debug info for NullPointerException only if one is possible
3460 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3461 if (op->info() != NULL) {
3462 add_debug_info_for_null_check(null_check_offset, op->info());
3463 }
3464 // done
3465 } else if (op->code() == lir_unlock) {
3466 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3467 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3468 } else {
3469 Unimplemented();
3470 }
3471 __ bind(*op->stub()->continuation());
3472 }
3473
3474
3475 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3476 ciMethod* method = op->profiled_method();
3477 int bci = op->profiled_bci();
3478 ciMethod* callee = op->profiled_callee();
3479
3480 // Update counter for all call types
3481 ciMethodData* md = method->method_data_or_null();
3482 assert(md != NULL, "Sanity");
3483 ciProfileData* data = md->bci_to_data(bci);
3484 assert(data->is_CounterData(), "need CounterData for calls");
3485 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3486 Register mdo = op->mdo()->as_register();
3487 __ mov_metadata(mdo, md->constant_encoding());
3488 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3489 Bytecodes::Code bc = method->java_code_at_bci(bci);
3490 const bool callee_is_static = callee->is_loaded() && callee->is_static();
3491 // Perform additional virtual call profiling for invokevirtual and
3492 // invokeinterface bytecodes
3493 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3494 !callee_is_static && // required for optimized MH invokes
3495 C1ProfileVirtualCalls) {
3496 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3497 Register recv = op->recv()->as_register();
3498 assert_different_registers(mdo, recv);
3499 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3500 ciKlass* known_klass = op->known_holder();
3501 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3502 // We know the type that will be seen at this call site; we can
3503 // statically update the MethodData* rather than needing to do
3504 // dynamic tests on the receiver type
3505
3506 // NOTE: we should probably put a lock around this search to
3507 // avoid collisions by concurrent compilations
3508 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3509 uint i;
3510 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3511 ciKlass* receiver = vc_data->receiver(i);
3512 if (known_klass->equals(receiver)) {
3513 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3514 __ addptr(data_addr, DataLayout::counter_increment);
3515 return;
3516 }
3517 }
3518
3519 // Receiver type not found in profile data; select an empty slot
3520
3521 // Note that this is less efficient than it should be because it
3522 // always does a write to the receiver part of the
3523 // VirtualCallData rather than just the first time
3524 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3525 ciKlass* receiver = vc_data->receiver(i);
3526 if (receiver == NULL) {
3527 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3528 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3529 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3530 __ addptr(data_addr, DataLayout::counter_increment);
3531 return;
3532 }
3533 }
3534 } else {
3535 __ load_klass(recv, recv);
3536 Label update_done;
3537 type_profile_helper(mdo, md, data, recv, &update_done);
3538 // Receiver did not match any saved receiver and there is no empty row for it.
3539 // Increment total counter to indicate polymorphic case.
3540 __ addptr(counter_addr, DataLayout::counter_increment);
3541
3542 __ bind(update_done);
3543 }
3544 } else {
3545 // Static call
3546 __ addptr(counter_addr, DataLayout::counter_increment);
3547 }
3548 }
3549
3550 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3551 Register obj = op->obj()->as_register();
3552 Register tmp = op->tmp()->as_pointer_register();
3553 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3554 ciKlass* exact_klass = op->exact_klass();
3555 intptr_t current_klass = op->current_klass();
3556 bool not_null = op->not_null();
3557 bool no_conflict = op->no_conflict();
3558
3559 Label update, next, none;
3560
3561 bool do_null = !not_null;
3562 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3563 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3564
3565 assert(do_null || do_update, "why are we here?");
3566 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3567
3568 __ verify_oop(obj);
3569
3570 if (tmp != obj) {
3571 __ mov(tmp, obj);
3572 }
3573 if (do_null) {
3574 __ testptr(tmp, tmp);
3575 __ jccb(Assembler::notZero, update);
3576 if (!TypeEntries::was_null_seen(current_klass)) {
3577 __ orptr(mdo_addr, TypeEntries::null_seen);
3578 }
3579 if (do_update) {
3580 #ifndef ASSERT
3581 __ jmpb(next);
3582 }
3583 #else
3584 __ jmp(next);
3585 }
3586 } else {
3587 __ testptr(tmp, tmp);
3588 __ jccb(Assembler::notZero, update);
3589 __ stop("unexpect null obj");
3590 #endif
3591 }
3592
3593 __ bind(update);
3594
3595 if (do_update) {
3596 #ifdef ASSERT
3597 if (exact_klass != NULL) {
3598 Label ok;
3599 __ load_klass(tmp, tmp);
3600 __ push(tmp);
3601 __ mov_metadata(tmp, exact_klass->constant_encoding());
3602 __ cmpptr(tmp, Address(rsp, 0));
3603 __ jccb(Assembler::equal, ok);
3604 __ stop("exact klass and actual klass differ");
3605 __ bind(ok);
3606 __ pop(tmp);
3607 }
3608 #endif
3609 if (!no_conflict) {
3610 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3611 if (exact_klass != NULL) {
3612 __ mov_metadata(tmp, exact_klass->constant_encoding());
3613 } else {
3614 __ load_klass(tmp, tmp);
3615 }
3616
3617 __ xorptr(tmp, mdo_addr);
3618 __ testptr(tmp, TypeEntries::type_klass_mask);
3619 // klass seen before, nothing to do. The unknown bit may have been
3620 // set already but no need to check.
3621 __ jccb(Assembler::zero, next);
3622
3623 __ testptr(tmp, TypeEntries::type_unknown);
3624 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3625
3626 if (TypeEntries::is_type_none(current_klass)) {
3627 __ cmpptr(mdo_addr, 0);
3628 __ jccb(Assembler::equal, none);
3629 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3630 __ jccb(Assembler::equal, none);
3631 // There is a chance that the checks above (re-reading profiling
3632 // data from memory) fail if another thread has just set the
3633 // profiling to this obj's klass
3634 __ xorptr(tmp, mdo_addr);
3635 __ testptr(tmp, TypeEntries::type_klass_mask);
3636 __ jccb(Assembler::zero, next);
3637 }
3638 } else {
3639 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3640 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3641
3642 __ movptr(tmp, mdo_addr);
3643 __ testptr(tmp, TypeEntries::type_unknown);
3644 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3645 }
3646
3647 // different than before. Cannot keep accurate profile.
3648 __ orptr(mdo_addr, TypeEntries::type_unknown);
3649
3650 if (TypeEntries::is_type_none(current_klass)) {
3651 __ jmpb(next);
3652
3653 __ bind(none);
3654 // first time here. Set profile type.
3655 __ movptr(mdo_addr, tmp);
3656 }
3657 } else {
3658 // There's a single possible klass at this profile point
3659 assert(exact_klass != NULL, "should be");
3660 if (TypeEntries::is_type_none(current_klass)) {
3661 __ mov_metadata(tmp, exact_klass->constant_encoding());
3662 __ xorptr(tmp, mdo_addr);
3663 __ testptr(tmp, TypeEntries::type_klass_mask);
3664 #ifdef ASSERT
3665 __ jcc(Assembler::zero, next);
3666
3667 {
3668 Label ok;
3669 __ push(tmp);
3670 __ cmpptr(mdo_addr, 0);
3671 __ jcc(Assembler::equal, ok);
3672 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3673 __ jcc(Assembler::equal, ok);
3674 // may have been set by another thread
3675 __ mov_metadata(tmp, exact_klass->constant_encoding());
3676 __ xorptr(tmp, mdo_addr);
3677 __ testptr(tmp, TypeEntries::type_mask);
3678 __ jcc(Assembler::zero, ok);
3679
3680 __ stop("unexpected profiling mismatch");
3681 __ bind(ok);
3682 __ pop(tmp);
3683 }
3684 #else
3685 __ jccb(Assembler::zero, next);
3686 #endif
3687 // first time here. Set profile type.
3688 __ movptr(mdo_addr, tmp);
3689 } else {
3690 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3691 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3692
3693 __ movptr(tmp, mdo_addr);
3694 __ testptr(tmp, TypeEntries::type_unknown);
3695 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3696
3697 __ orptr(mdo_addr, TypeEntries::type_unknown);
3698 }
3699 }
3700
3701 __ bind(next);
3702 }
3703 }
3704
3705 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3706 Unimplemented();
3707 }
3708
3709
3710 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3711 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3712 }
3713
3714
3715 void LIR_Assembler::align_backward_branch_target() {
3716 __ align(BytesPerWord);
3717 }
3718
3719
3720 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3721 if (left->is_single_cpu()) {
3722 __ negl(left->as_register());
3723 move_regs(left->as_register(), dest->as_register());
3724
3725 } else if (left->is_double_cpu()) {
3726 Register lo = left->as_register_lo();
3727 #ifdef _LP64
3728 Register dst = dest->as_register_lo();
3729 __ movptr(dst, lo);
3730 __ negptr(dst);
3731 #else
3732 Register hi = left->as_register_hi();
3733 __ lneg(hi, lo);
3734 if (dest->as_register_lo() == hi) {
3735 assert(dest->as_register_hi() != lo, "destroying register");
3736 move_regs(hi, dest->as_register_hi());
3737 move_regs(lo, dest->as_register_lo());
3738 } else {
3739 move_regs(lo, dest->as_register_lo());
3740 move_regs(hi, dest->as_register_hi());
3741 }
3742 #endif // _LP64
3743
3744 } else if (dest->is_single_xmm()) {
3745 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3746 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3747 }
3748 if (UseAVX > 0) {
3749 __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(),
3750 ExternalAddress((address)float_signflip_pool));
3751 } else {
3752 __ xorps(dest->as_xmm_float_reg(),
3753 ExternalAddress((address)float_signflip_pool));
3754 }
3755 } else if (dest->is_double_xmm()) {
3756 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3757 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3758 }
3759 if (UseAVX > 0) {
3760 __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(),
3761 ExternalAddress((address)double_signflip_pool));
3762 } else {
3763 __ xorpd(dest->as_xmm_double_reg(),
3764 ExternalAddress((address)double_signflip_pool));
3765 }
3766 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3767 assert(left->fpu() == 0, "arg must be on TOS");
3768 assert(dest->fpu() == 0, "dest must be TOS");
3769 __ fchs();
3770
3771 } else {
3772 ShouldNotReachHere();
3773 }
3774 }
3775
3776
3777 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3778 assert(addr->is_address() && dest->is_register(), "check");
3779 Register reg;
3780 reg = dest->as_pointer_register();
3781 __ lea(reg, as_Address(addr->as_address_ptr()));
3782 }
3783
3784
3785
3786 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3787 assert(!tmp->is_valid(), "don't need temporary");
3788 __ call(RuntimeAddress(dest));
3789 if (info != NULL) {
3790 add_call_info_here(info);
3791 }
3792 }
3793
3794
3795 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3796 assert(type == T_LONG, "only for volatile long fields");
3797
3798 if (info != NULL) {
3799 add_debug_info_for_null_check_here(info);
3800 }
3801
3802 if (src->is_double_xmm()) {
3803 if (dest->is_double_cpu()) {
3804 #ifdef _LP64
3805 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3806 #else
3807 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3808 __ psrlq(src->as_xmm_double_reg(), 32);
3809 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3810 #endif // _LP64
3811 } else if (dest->is_double_stack()) {
3812 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3813 } else if (dest->is_address()) {
3814 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3815 } else {
3816 ShouldNotReachHere();
3817 }
3818
3819 } else if (dest->is_double_xmm()) {
3820 if (src->is_double_stack()) {
3821 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3822 } else if (src->is_address()) {
3823 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3824 } else {
3825 ShouldNotReachHere();
3826 }
3827
3828 } else if (src->is_double_fpu()) {
3829 assert(src->fpu_regnrLo() == 0, "must be TOS");
3830 if (dest->is_double_stack()) {
3831 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3832 } else if (dest->is_address()) {
3833 __ fistp_d(as_Address(dest->as_address_ptr()));
3834 } else {
3835 ShouldNotReachHere();
3836 }
3837
3838 } else if (dest->is_double_fpu()) {
3839 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3840 if (src->is_double_stack()) {
3841 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3842 } else if (src->is_address()) {
3843 __ fild_d(as_Address(src->as_address_ptr()));
3844 } else {
3845 ShouldNotReachHere();
3846 }
3847 } else {
3848 ShouldNotReachHere();
3849 }
3850 }
3851
3852 #ifdef ASSERT
3853 // emit run-time assertion
3854 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3855 assert(op->code() == lir_assert, "must be");
3856
3857 if (op->in_opr1()->is_valid()) {
3858 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3859 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3860 } else {
3861 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3862 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3863 }
3864
3865 Label ok;
3866 if (op->condition() != lir_cond_always) {
3867 Assembler::Condition acond = Assembler::zero;
3868 switch (op->condition()) {
3869 case lir_cond_equal: acond = Assembler::equal; break;
3870 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3871 case lir_cond_less: acond = Assembler::less; break;
3872 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3873 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3874 case lir_cond_greater: acond = Assembler::greater; break;
3875 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3876 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3877 default: ShouldNotReachHere();
3878 }
3879 __ jcc(acond, ok);
3880 }
3881 if (op->halt()) {
3882 const char* str = __ code_string(op->msg());
3883 __ stop(str);
3884 } else {
3885 breakpoint();
3886 }
3887 __ bind(ok);
3888 }
3889 #endif
3890
3891 void LIR_Assembler::membar() {
3892 // QQQ sparc TSO uses this,
3893 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3894 }
3895
3896 void LIR_Assembler::membar_acquire() {
3897 // No x86 machines currently require load fences
3898 }
3899
3900 void LIR_Assembler::membar_release() {
3901 // No x86 machines currently require store fences
3902 }
3903
3904 void LIR_Assembler::membar_loadload() {
3905 // no-op
3906 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3907 }
3908
3909 void LIR_Assembler::membar_storestore() {
3910 // no-op
3911 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3912 }
3913
3914 void LIR_Assembler::membar_loadstore() {
3915 // no-op
3916 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3917 }
3918
3919 void LIR_Assembler::membar_storeload() {
3920 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3921 }
3922
3923 void LIR_Assembler::on_spin_wait() {
3924 __ pause ();
3925 }
3926
3927 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3928 assert(result_reg->is_register(), "check");
3929 #ifdef _LP64
3930 // __ get_thread(result_reg->as_register_lo());
3931 __ mov(result_reg->as_register(), r15_thread);
3932 #else
3933 __ get_thread(result_reg->as_register());
3934 #endif // _LP64
3935 }
3936
3937
3938 void LIR_Assembler::peephole(LIR_List*) {
3939 // do nothing for now
3940 }
3941
3942 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3943 assert(data == dest, "xchg/xadd uses only 2 operands");
3944
3945 if (data->type() == T_INT) {
3946 if (code == lir_xadd) {
3947 if (os::is_MP()) {
3948 __ lock();
3949 }
3950 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3951 } else {
3952 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
3953 }
3954 } else if (data->is_oop()) {
3955 assert (code == lir_xchg, "xadd for oops");
3956 Register obj = data->as_register();
3957 #ifdef _LP64
3958 if (UseCompressedOops) {
3959 __ encode_heap_oop(obj);
3960 __ xchgl(obj, as_Address(src->as_address_ptr()));
3961 __ decode_heap_oop(obj);
3962 } else {
3963 __ xchgptr(obj, as_Address(src->as_address_ptr()));
3964 }
3965 #else
3966 __ xchgl(obj, as_Address(src->as_address_ptr()));
3967 #endif
3968 } else if (data->type() == T_LONG) {
3969 #ifdef _LP64
3970 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
3971 if (code == lir_xadd) {
3972 if (os::is_MP()) {
3973 __ lock();
3974 }
3975 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
3976 } else {
3977 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
3978 }
3979 #else
3980 ShouldNotReachHere();
3981 #endif
3982 } else {
3983 ShouldNotReachHere();
3984 }
3985 }
3986
3987 #undef __