1845 } else
1846 if (code == lir_instanceof) {
1847 Register obj = op->object()->as_register();
1848 Register dst = op->result_opr()->as_register();
1849 Label success, failure, done;
1850 emit_typecheck_helper(op, &success, &failure, &failure);
1851 __ bind(failure);
1852 __ xorptr(dst, dst);
1853 __ jmpb(done);
1854 __ bind(success);
1855 __ movptr(dst, 1);
1856 __ bind(done);
1857 } else {
1858 ShouldNotReachHere();
1859 }
1860
1861 }
1862
1863
1864 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1865 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1866 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1867 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1868 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1869 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1870 Register addr = op->addr()->as_register();
1871 if (os::is_MP()) {
1872 __ lock();
1873 }
1874 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1875
1876 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1877 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1878 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1879 Register newval = op->new_value()->as_register();
1880 Register cmpval = op->cmp_value()->as_register();
1881 assert(cmpval == rax, "wrong register");
1882 assert(newval != NULL, "new val must be register");
1883 assert(cmpval != newval, "cmp and new values must be in different registers");
1884 assert(cmpval != addr, "cmp and addr must be in different registers");
1885 assert(newval != addr, "new value and addr must be in different registers");
1886
1887 if ( op->code() == lir_cas_obj) {
1888 #ifdef _LP64
1889 if (UseCompressedOops) {
1890 __ encode_heap_oop(cmpval);
1891 __ mov(rscratch1, newval);
1892 __ encode_heap_oop(rscratch1);
1893 if (os::is_MP()) {
1894 __ lock();
1895 }
1896 // cmpval (rax) is implicitly used by this instruction
1897 __ cmpxchgl(rscratch1, Address(addr, 0));
1898 } else
1899 #endif
1900 {
1901 if (os::is_MP()) {
1902 __ lock();
1903 }
1904 __ cmpxchgptr(newval, Address(addr, 0));
1905 }
1906 } else {
1907 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1908 if (os::is_MP()) {
1909 __ lock();
1910 }
1911 __ cmpxchgl(newval, Address(addr, 0));
1912 }
1913 #ifdef _LP64
1914 } else if (op->code() == lir_cas_long) {
1915 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1916 Register newval = op->new_value()->as_register_lo();
1917 Register cmpval = op->cmp_value()->as_register_lo();
1918 assert(cmpval == rax, "wrong register");
1919 assert(newval != NULL, "new val must be register");
1920 assert(cmpval != newval, "cmp and new values must be in different registers");
1921 assert(cmpval != addr, "cmp and addr must be in different registers");
1922 assert(newval != addr, "new value and addr must be in different registers");
1923 if (os::is_MP()) {
1924 __ lock();
1925 }
1926 __ cmpxchgq(newval, Address(addr, 0));
1927 #endif // _LP64
1928 } else {
1929 Unimplemented();
1930 }
1931 }
1932
1933 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1934 Assembler::Condition acond, ncond;
1935 switch (condition) {
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1845 } else
1846 if (code == lir_instanceof) {
1847 Register obj = op->object()->as_register();
1848 Register dst = op->result_opr()->as_register();
1849 Label success, failure, done;
1850 emit_typecheck_helper(op, &success, &failure, &failure);
1851 __ bind(failure);
1852 __ xorptr(dst, dst);
1853 __ jmpb(done);
1854 __ bind(success);
1855 __ movptr(dst, 1);
1856 __ bind(done);
1857 } else {
1858 ShouldNotReachHere();
1859 }
1860
1861 }
1862
1863
1864 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1865 LIR_Address* address = op->addr()->as_address_ptr();
1866 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1867 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1868 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1869 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1870 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1871 Register addr = address->base()->as_pointer_register();
1872 if (os::is_MP()) {
1873 __ lock();
1874 }
1875 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1876
1877 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1878 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1879 Register addr = address->base()->as_pointer_register();
1880 Register newval = op->new_value()->as_register();
1881 Register cmpval = op->cmp_value()->as_register();
1882 assert(cmpval == rax, "wrong register");
1883 assert(newval != NULL, "new val must be register");
1884 assert(cmpval != newval, "cmp and new values must be in different registers");
1885 assert(cmpval != addr, "cmp and addr must be in different registers");
1886 assert(newval != addr, "new value and addr must be in different registers");
1887
1888 if ( op->code() == lir_cas_obj) {
1889 #ifdef _LP64
1890 if (UseCompressedOops) {
1891 __ encode_heap_oop(cmpval);
1892 __ mov(rscratch1, newval);
1893 __ encode_heap_oop(rscratch1);
1894 if (os::is_MP()) {
1895 __ lock();
1896 }
1897 // cmpval (rax) is implicitly used by this instruction
1898 __ cmpxchgl(rscratch1, Address(addr, 0));
1899 } else
1900 #endif
1901 {
1902 if (os::is_MP()) {
1903 __ lock();
1904 }
1905 __ cmpxchgptr(newval, Address(addr, 0));
1906 }
1907 } else {
1908 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1909 if (os::is_MP()) {
1910 __ lock();
1911 }
1912 __ cmpxchgl(newval, Address(addr, 0));
1913 }
1914 #ifdef _LP64
1915 } else if (op->code() == lir_cas_long) {
1916 Register addr = address->base()->as_pointer_register();
1917 Register newval = op->new_value()->as_register_lo();
1918 Register cmpval = op->cmp_value()->as_register_lo();
1919 assert(cmpval == rax, "wrong register");
1920 assert(newval != NULL, "new val must be register");
1921 assert(cmpval != newval, "cmp and new values must be in different registers");
1922 assert(cmpval != addr, "cmp and addr must be in different registers");
1923 assert(newval != addr, "new value and addr must be in different registers");
1924 if (os::is_MP()) {
1925 __ lock();
1926 }
1927 __ cmpxchgq(newval, Address(addr, 0));
1928 #endif // _LP64
1929 } else {
1930 Unimplemented();
1931 }
1932 }
1933
1934 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1935 Assembler::Condition acond, ncond;
1936 switch (condition) {
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