1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
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23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 public:
42 // Support for VM calls
43 //
44 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
45 // may customize this version by overriding it for its purposes (e.g., to save/restore
46 // additional registers when doing a VM call).
47
48 virtual void call_VM_leaf_base(
49 address entry_point, // the entry point
50 int number_of_arguments // the number of arguments to pop after the call
51 );
52
53 protected:
54 // This is the base routine called by the different versions of call_VM. The interpreter
55 // may customize this version by overriding it for its purposes (e.g., to save/restore
56 // additional registers when doing a VM call).
57 //
58 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
59 // returns the register which contains the thread upon return. If a thread register has been
60 // specified, the return value will correspond to that register. If no last_java_sp is specified
61 // (noreg) than rsp will be used instead.
62 virtual void call_VM_base( // returns the register containing the thread upon return
63 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
64 Register java_thread, // the thread if computed before ; use noreg otherwise
65 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
66 address entry_point, // the entry point
67 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
68 bool check_exceptions // whether to check for pending exceptions after return
69 );
70
71 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
72
73 // helpers for FPU flag access
74 // tmp is a temporary register, if none is available use noreg
75 void save_rax (Register tmp);
76 void restore_rax(Register tmp);
77
78 public:
79 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
80
81 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
82 // The implementation is only non-empty for the InterpreterMacroAssembler,
83 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
84 virtual void check_and_handle_popframe(Register java_thread);
85 virtual void check_and_handle_earlyret(Register java_thread);
86
87 Address as_Address(AddressLiteral adr);
88 Address as_Address(ArrayAddress adr);
89
90 // Support for NULL-checks
91 //
92 // Generates code that causes a NULL OS exception if the content of reg is NULL.
93 // If the accessed location is M[reg + offset] and the offset is known, provide the
94 // offset. No explicit code generation is needed if the offset is within a certain
95 // range (0 <= offset <= page_size).
96
97 void null_check(Register reg, int offset = -1);
98 static bool needs_explicit_null_check(intptr_t offset);
99
100 // Required platform-specific helpers for Label::patch_instructions.
101 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
102 void pd_patch_instruction(address branch, address target) {
103 unsigned char op = branch[0];
104 assert(op == 0xE8 /* call */ ||
105 op == 0xE9 /* jmp */ ||
106 op == 0xEB /* short jmp */ ||
107 (op & 0xF0) == 0x70 /* short jcc */ ||
108 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
109 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
110 "Invalid opcode at patch point");
111
112 if (op == 0xEB || (op & 0xF0) == 0x70) {
113 // short offset operators (jmp and jcc)
114 char* disp = (char*) &branch[1];
115 int imm8 = target - (address) &disp[1];
116 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
117 *disp = imm8;
118 } else {
119 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
120 int imm32 = target - (address) &disp[1];
121 *disp = imm32;
122 }
123 }
124
125 // The following 4 methods return the offset of the appropriate move instruction
126
127 // Support for fast byte/short loading with zero extension (depending on particular CPU)
128 int load_unsigned_byte(Register dst, Address src);
129 int load_unsigned_short(Register dst, Address src);
130
131 // Support for fast byte/short loading with sign extension (depending on particular CPU)
132 int load_signed_byte(Register dst, Address src);
133 int load_signed_short(Register dst, Address src);
134
135 // Support for sign-extension (hi:lo = extend_sign(lo))
136 void extend_sign(Register hi, Register lo);
137
138 // Load and store values by size and signed-ness
139 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
140 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
141
142 // Support for inc/dec with optimal instruction selection depending on value
143
144 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
145 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
146
147 void decrementl(Address dst, int value = 1);
148 void decrementl(Register reg, int value = 1);
149
150 void decrementq(Register reg, int value = 1);
151 void decrementq(Address dst, int value = 1);
152
153 void incrementl(Address dst, int value = 1);
154 void incrementl(Register reg, int value = 1);
155
156 void incrementq(Register reg, int value = 1);
157 void incrementq(Address dst, int value = 1);
158
159 // special instructions for EVEX
160 void setvectmask(Register dst, Register src);
161 void restorevectmask();
162
163 // Support optimal SSE move instructions.
164 void movflt(XMMRegister dst, XMMRegister src) {
165 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
166 else { movss (dst, src); return; }
167 }
168 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
169 void movflt(XMMRegister dst, AddressLiteral src);
170 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
171
172 void movdbl(XMMRegister dst, XMMRegister src) {
173 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
174 else { movsd (dst, src); return; }
175 }
176
177 void movdbl(XMMRegister dst, AddressLiteral src);
178
179 void movdbl(XMMRegister dst, Address src) {
180 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
181 else { movlpd(dst, src); return; }
182 }
183 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
184
185 void incrementl(AddressLiteral dst);
186 void incrementl(ArrayAddress dst);
187
188 void incrementq(AddressLiteral dst);
189
190 // Alignment
191 void align(int modulus);
192 void align(int modulus, int target);
193
194 // A 5 byte nop that is safe for patching (see patch_verified_entry)
195 void fat_nop();
196
197 // Stack frame creation/removal
198 void enter();
199 void leave();
200
201 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
202 // The pointer will be loaded into the thread register.
203 void get_thread(Register thread);
204
205
206 // Support for VM calls
207 //
208 // It is imperative that all calls into the VM are handled via the call_VM macros.
209 // They make sure that the stack linkage is setup correctly. call_VM's correspond
210 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
211
212
213 void call_VM(Register oop_result,
214 address entry_point,
215 bool check_exceptions = true);
216 void call_VM(Register oop_result,
217 address entry_point,
218 Register arg_1,
219 bool check_exceptions = true);
220 void call_VM(Register oop_result,
221 address entry_point,
222 Register arg_1, Register arg_2,
223 bool check_exceptions = true);
224 void call_VM(Register oop_result,
225 address entry_point,
226 Register arg_1, Register arg_2, Register arg_3,
227 bool check_exceptions = true);
228
229 // Overloadings with last_Java_sp
230 void call_VM(Register oop_result,
231 Register last_java_sp,
232 address entry_point,
233 int number_of_arguments = 0,
234 bool check_exceptions = true);
235 void call_VM(Register oop_result,
236 Register last_java_sp,
237 address entry_point,
238 Register arg_1, bool
239 check_exceptions = true);
240 void call_VM(Register oop_result,
241 Register last_java_sp,
242 address entry_point,
243 Register arg_1, Register arg_2,
244 bool check_exceptions = true);
245 void call_VM(Register oop_result,
246 Register last_java_sp,
247 address entry_point,
248 Register arg_1, Register arg_2, Register arg_3,
249 bool check_exceptions = true);
250
251 void get_vm_result (Register oop_result, Register thread);
252 void get_vm_result_2(Register metadata_result, Register thread);
253
254 // These always tightly bind to MacroAssembler::call_VM_base
255 // bypassing the virtual implementation
256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
257 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
258 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
260 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
261
262 void call_VM_leaf0(address entry_point);
263 void call_VM_leaf(address entry_point,
264 int number_of_arguments = 0);
265 void call_VM_leaf(address entry_point,
266 Register arg_1);
267 void call_VM_leaf(address entry_point,
268 Register arg_1, Register arg_2);
269 void call_VM_leaf(address entry_point,
270 Register arg_1, Register arg_2, Register arg_3);
271
272 // These always tightly bind to MacroAssembler::call_VM_leaf_base
273 // bypassing the virtual implementation
274 void super_call_VM_leaf(address entry_point);
275 void super_call_VM_leaf(address entry_point, Register arg_1);
276 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
277 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
278 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
279
280 // last Java Frame (fills frame anchor)
281 void set_last_Java_frame(Register thread,
282 Register last_java_sp,
283 Register last_java_fp,
284 address last_java_pc);
285
286 // thread in the default location (r15_thread on 64bit)
287 void set_last_Java_frame(Register last_java_sp,
288 Register last_java_fp,
289 address last_java_pc);
290
291 void reset_last_Java_frame(Register thread, bool clear_fp);
292
293 // thread in the default location (r15_thread on 64bit)
294 void reset_last_Java_frame(bool clear_fp);
295
296 // jobjects
297 void resolve_jobject(Register value, Register thread, Register tmp);
298
299 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
300 void c2bool(Register x);
301
302 // C++ bool manipulation
303
304 void movbool(Register dst, Address src);
305 void movbool(Address dst, bool boolconst);
306 void movbool(Address dst, Register src);
307 void testbool(Register dst);
308
309 void load_mirror(Register mirror, Register method);
310
311 // oop manipulations
312 void load_klass(Register dst, Register src);
313 void store_klass(Register dst, Register src);
314
315 void load_heap_oop(Register dst, Address src);
316 void load_heap_oop_not_null(Register dst, Address src);
317 void store_heap_oop(Address dst, Register src);
318 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
319
320 // Used for storing NULL. All other oop constants should be
321 // stored using routines that take a jobject.
322 void store_heap_oop_null(Address dst);
323
324 void load_prototype_header(Register dst, Register src);
325
326 #ifdef _LP64
327 void store_klass_gap(Register dst, Register src);
328
329 // This dummy is to prevent a call to store_heap_oop from
330 // converting a zero (like NULL) into a Register by giving
331 // the compiler two choices it can't resolve
332
333 void store_heap_oop(Address dst, void* dummy);
334
335 void encode_heap_oop(Register r);
336 void decode_heap_oop(Register r);
337 void encode_heap_oop_not_null(Register r);
338 void decode_heap_oop_not_null(Register r);
339 void encode_heap_oop_not_null(Register dst, Register src);
340 void decode_heap_oop_not_null(Register dst, Register src);
341
342 void set_narrow_oop(Register dst, jobject obj);
343 void set_narrow_oop(Address dst, jobject obj);
344 void cmp_narrow_oop(Register dst, jobject obj);
345 void cmp_narrow_oop(Address dst, jobject obj);
346
347 void encode_klass_not_null(Register r);
348 void decode_klass_not_null(Register r);
349 void encode_klass_not_null(Register dst, Register src);
350 void decode_klass_not_null(Register dst, Register src);
351 void set_narrow_klass(Register dst, Klass* k);
352 void set_narrow_klass(Address dst, Klass* k);
353 void cmp_narrow_klass(Register dst, Klass* k);
354 void cmp_narrow_klass(Address dst, Klass* k);
355
356 // Returns the byte size of the instructions generated by decode_klass_not_null()
357 // when compressed klass pointers are being used.
358 static int instr_size_for_decode_klass_not_null();
359
360 // if heap base register is used - reinit it with the correct value
361 void reinit_heapbase();
362
363 DEBUG_ONLY(void verify_heapbase(const char* msg);)
364
365 #endif // _LP64
366
367 // Int division/remainder for Java
368 // (as idivl, but checks for special case as described in JVM spec.)
369 // returns idivl instruction offset for implicit exception handling
370 int corrected_idivl(Register reg);
371
372 // Long division/remainder for Java
373 // (as idivq, but checks for special case as described in JVM spec.)
374 // returns idivq instruction offset for implicit exception handling
375 int corrected_idivq(Register reg);
376
377 void int3();
378
379 // Long operation macros for a 32bit cpu
380 // Long negation for Java
381 void lneg(Register hi, Register lo);
382
383 // Long multiplication for Java
384 // (destroys contents of eax, ebx, ecx and edx)
385 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
386
387 // Long shifts for Java
388 // (semantics as described in JVM spec.)
389 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
390 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
391
392 // Long compare for Java
393 // (semantics as described in JVM spec.)
394 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
395
396
397 // misc
398
399 // Sign extension
400 void sign_extend_short(Register reg);
401 void sign_extend_byte(Register reg);
402
403 // Division by power of 2, rounding towards 0
404 void division_with_shift(Register reg, int shift_value);
405
406 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
407 //
408 // CF (corresponds to C0) if x < y
409 // PF (corresponds to C2) if unordered
410 // ZF (corresponds to C3) if x = y
411 //
412 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
413 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
414 void fcmp(Register tmp);
415 // Variant of the above which allows y to be further down the stack
416 // and which only pops x and y if specified. If pop_right is
417 // specified then pop_left must also be specified.
418 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
419
420 // Floating-point comparison for Java
421 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
422 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
423 // (semantics as described in JVM spec.)
424 void fcmp2int(Register dst, bool unordered_is_less);
425 // Variant of the above which allows y to be further down the stack
426 // and which only pops x and y if specified. If pop_right is
427 // specified then pop_left must also be specified.
428 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
429
430 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
431 // tmp is a temporary register, if none is available use noreg
432 void fremr(Register tmp);
433
434 // dst = c = a * b + c
435 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
436 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
437
438
439 // same as fcmp2int, but using SSE2
440 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
441 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
442
443 // branch to L if FPU flag C2 is set/not set
444 // tmp is a temporary register, if none is available use noreg
445 void jC2 (Register tmp, Label& L);
446 void jnC2(Register tmp, Label& L);
447
448 // Pop ST (ffree & fincstp combined)
449 void fpop();
450
451 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
452 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
453 void load_float(Address src);
454
455 // Store float value to 'address'. If UseSSE >= 1, the value is stored
456 // from register xmm0. Otherwise, the value is stored from the FPU stack.
457 void store_float(Address dst);
458
459 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
460 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
461 void load_double(Address src);
462
463 // Store double value to 'address'. If UseSSE >= 2, the value is stored
464 // from register xmm0. Otherwise, the value is stored from the FPU stack.
465 void store_double(Address dst);
466
467 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
468 void push_fTOS();
469
470 // pops double TOS element from CPU stack and pushes on FPU stack
471 void pop_fTOS();
472
473 void empty_FPU_stack();
474
475 void push_IU_state();
476 void pop_IU_state();
477
478 void push_FPU_state();
479 void pop_FPU_state();
480
481 void push_CPU_state();
482 void pop_CPU_state();
483
484 // Round up to a power of two
485 void round_to(Register reg, int modulus);
486
487 // Callee saved registers handling
488 void push_callee_saved_registers();
489 void pop_callee_saved_registers();
490
491 // allocation
492 void eden_allocate(
493 Register obj, // result: pointer to object after successful allocation
494 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
495 int con_size_in_bytes, // object size in bytes if known at compile time
496 Register t1, // temp register
497 Label& slow_case // continuation point if fast allocation fails
498 );
499 void tlab_allocate(
500 Register obj, // result: pointer to object after successful allocation
501 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
502 int con_size_in_bytes, // object size in bytes if known at compile time
503 Register t1, // temp register
504 Register t2, // temp register
505 Label& slow_case // continuation point if fast allocation fails
506 );
507 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
508 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
509
510 void incr_allocated_bytes(Register thread,
511 Register var_size_in_bytes, int con_size_in_bytes,
512 Register t1 = noreg);
513
514 // interface method calling
515 void lookup_interface_method(Register recv_klass,
516 Register intf_klass,
517 RegisterOrConstant itable_index,
518 Register method_result,
519 Register scan_temp,
520 Label& no_such_interface);
521
522 // virtual method calling
523 void lookup_virtual_method(Register recv_klass,
524 RegisterOrConstant vtable_index,
525 Register method_result);
526
527 // Test sub_klass against super_klass, with fast and slow paths.
528
529 // The fast path produces a tri-state answer: yes / no / maybe-slow.
530 // One of the three labels can be NULL, meaning take the fall-through.
531 // If super_check_offset is -1, the value is loaded up from super_klass.
532 // No registers are killed, except temp_reg.
533 void check_klass_subtype_fast_path(Register sub_klass,
534 Register super_klass,
535 Register temp_reg,
536 Label* L_success,
537 Label* L_failure,
538 Label* L_slow_path,
539 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
540
541 // The rest of the type check; must be wired to a corresponding fast path.
542 // It does not repeat the fast path logic, so don't use it standalone.
543 // The temp_reg and temp2_reg can be noreg, if no temps are available.
544 // Updates the sub's secondary super cache as necessary.
545 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
546 void check_klass_subtype_slow_path(Register sub_klass,
547 Register super_klass,
548 Register temp_reg,
549 Register temp2_reg,
550 Label* L_success,
551 Label* L_failure,
552 bool set_cond_codes = false);
553
554 // Simplified, combined version, good for typical uses.
555 // Falls through on failure.
556 void check_klass_subtype(Register sub_klass,
557 Register super_klass,
558 Register temp_reg,
559 Label& L_success);
560
561 // method handles (JSR 292)
562 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
563
564 //----
565 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
566
567 // Debugging
568
569 // only if +VerifyOops
570 // TODO: Make these macros with file and line like sparc version!
571 void verify_oop(Register reg, const char* s = "broken oop");
572 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
573
574 // TODO: verify method and klass metadata (compare against vptr?)
575 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
576 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
577
578 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
579 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
580
581 // only if +VerifyFPU
582 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
583
584 // Verify or restore cpu control state after JNI call
585 void restore_cpu_control_state_after_jni();
586
587 // prints msg, dumps registers and stops execution
588 void stop(const char* msg);
589
590 // prints msg and continues
591 void warn(const char* msg);
592
593 // dumps registers and other state
594 void print_state();
595
596 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
597 static void debug64(char* msg, int64_t pc, int64_t regs[]);
598 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
599 static void print_state64(int64_t pc, int64_t regs[]);
600
601 void os_breakpoint();
602
603 void untested() { stop("untested"); }
604
605 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
606
607 void should_not_reach_here() { stop("should not reach here"); }
608
609 void print_CPU_state();
610
611 // Stack overflow checking
612 void bang_stack_with_offset(int offset) {
613 // stack grows down, caller passes positive offset
614 assert(offset > 0, "must bang with negative offset");
615 movl(Address(rsp, (-offset)), rax);
616 }
617
618 // Writes to stack successive pages until offset reached to check for
619 // stack overflow + shadow pages. Also, clobbers tmp
620 void bang_stack_size(Register size, Register tmp);
621
622 // Check for reserved stack access in method being exited (for JIT)
623 void reserved_stack_check();
624
625 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
626 Register tmp,
627 int offset);
628
629 // Support for serializing memory accesses between threads
630 void serialize_memory(Register thread, Register tmp);
631
632 void verify_tlab();
633
634 // Biased locking support
635 // lock_reg and obj_reg must be loaded up with the appropriate values.
636 // swap_reg must be rax, and is killed.
637 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
638 // be killed; if not supplied, push/pop will be used internally to
639 // allocate a temporary (inefficient, avoid if possible).
640 // Optional slow case is for implementations (interpreter and C1) which branch to
641 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
642 // Returns offset of first potentially-faulting instruction for null
643 // check info (currently consumed only by C1). If
644 // swap_reg_contains_mark is true then returns -1 as it is assumed
645 // the calling code has already passed any potential faults.
646 int biased_locking_enter(Register lock_reg, Register obj_reg,
647 Register swap_reg, Register tmp_reg,
648 bool swap_reg_contains_mark,
649 Label& done, Label* slow_case = NULL,
650 BiasedLockingCounters* counters = NULL);
651 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
652 #ifdef COMPILER2
653 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
654 // See full desription in macroAssembler_x86.cpp.
655 void fast_lock(Register obj, Register box, Register tmp,
656 Register scr, Register cx1, Register cx2,
657 BiasedLockingCounters* counters,
658 RTMLockingCounters* rtm_counters,
659 RTMLockingCounters* stack_rtm_counters,
660 Metadata* method_data,
661 bool use_rtm, bool profile_rtm);
662 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
663 #if INCLUDE_RTM_OPT
664 void rtm_counters_update(Register abort_status, Register rtm_counters);
665 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
666 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
667 RTMLockingCounters* rtm_counters,
668 Metadata* method_data);
669 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
670 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
671 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
672 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
673 void rtm_stack_locking(Register obj, Register tmp, Register scr,
674 Register retry_on_abort_count,
675 RTMLockingCounters* stack_rtm_counters,
676 Metadata* method_data, bool profile_rtm,
677 Label& DONE_LABEL, Label& IsInflated);
678 void rtm_inflated_locking(Register obj, Register box, Register tmp,
679 Register scr, Register retry_on_busy_count,
680 Register retry_on_abort_count,
681 RTMLockingCounters* rtm_counters,
682 Metadata* method_data, bool profile_rtm,
683 Label& DONE_LABEL);
684 #endif
685 #endif
686
687 Condition negate_condition(Condition cond);
688
689 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
690 // operands. In general the names are modified to avoid hiding the instruction in Assembler
691 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
692 // here in MacroAssembler. The major exception to this rule is call
693
694 // Arithmetics
695
696
697 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
698 void addptr(Address dst, Register src);
699
700 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
701 void addptr(Register dst, int32_t src);
702 void addptr(Register dst, Register src);
703 void addptr(Register dst, RegisterOrConstant src) {
704 if (src.is_constant()) addptr(dst, (int) src.as_constant());
705 else addptr(dst, src.as_register());
706 }
707
708 void andptr(Register dst, int32_t src);
709 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
710
711 void cmp8(AddressLiteral src1, int imm);
712
713 // renamed to drag out the casting of address to int32_t/intptr_t
714 void cmp32(Register src1, int32_t imm);
715
716 void cmp32(AddressLiteral src1, int32_t imm);
717 // compare reg - mem, or reg - &mem
718 void cmp32(Register src1, AddressLiteral src2);
719
720 void cmp32(Register src1, Address src2);
721
722 #ifndef _LP64
723 void cmpklass(Address dst, Metadata* obj);
724 void cmpklass(Register dst, Metadata* obj);
725 void cmpoop(Address dst, jobject obj);
726 void cmpoop(Register dst, jobject obj);
727 #endif // _LP64
728
729 // NOTE src2 must be the lval. This is NOT an mem-mem compare
730 void cmpptr(Address src1, AddressLiteral src2);
731
732 void cmpptr(Register src1, AddressLiteral src2);
733
734 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
735 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
736 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
737
738 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
739 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
740
741 // cmp64 to avoild hiding cmpq
742 void cmp64(Register src1, AddressLiteral src);
743
744 void cmpxchgptr(Register reg, Address adr);
745
746 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
747
748
749 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
750 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
751
752
753 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
754
755 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
756
757 void shlptr(Register dst, int32_t shift);
758 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
759
760 void shrptr(Register dst, int32_t shift);
761 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
762
763 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
764 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
765
766 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
767
768 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
769 void subptr(Register dst, int32_t src);
770 // Force generation of a 4 byte immediate value even if it fits into 8bit
771 void subptr_imm32(Register dst, int32_t src);
772 void subptr(Register dst, Register src);
773 void subptr(Register dst, RegisterOrConstant src) {
774 if (src.is_constant()) subptr(dst, (int) src.as_constant());
775 else subptr(dst, src.as_register());
776 }
777
778 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
779 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
780
781 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
782 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
783
784 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
785
786
787
788 // Helper functions for statistics gathering.
789 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
790 void cond_inc32(Condition cond, AddressLiteral counter_addr);
791 // Unconditional atomic increment.
792 void atomic_incl(Address counter_addr);
793 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
794 #ifdef _LP64
795 void atomic_incq(Address counter_addr);
796 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
797 #endif
798 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
799 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
800
801 void lea(Register dst, AddressLiteral adr);
802 void lea(Address dst, AddressLiteral adr);
803 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
804
805 void leal32(Register dst, Address src) { leal(dst, src); }
806
807 // Import other testl() methods from the parent class or else
808 // they will be hidden by the following overriding declaration.
809 using Assembler::testl;
810 void testl(Register dst, AddressLiteral src);
811
812 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
813 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
814 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
815 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
816
817 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
818 void testptr(Register src1, Register src2);
819
820 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
821 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
822
823 // Calls
824
825 void call(Label& L, relocInfo::relocType rtype);
826 void call(Register entry);
827
828 // NOTE: this call transfers to the effective address of entry NOT
829 // the address contained by entry. This is because this is more natural
830 // for jumps/calls.
831 void call(AddressLiteral entry);
832
833 // Emit the CompiledIC call idiom
834 void ic_call(address entry, jint method_index = 0);
835
836 // Jumps
837
838 // NOTE: these jumps tranfer to the effective address of dst NOT
839 // the address contained by dst. This is because this is more natural
840 // for jumps/calls.
841 void jump(AddressLiteral dst);
842 void jump_cc(Condition cc, AddressLiteral dst);
843
844 // 32bit can do a case table jump in one instruction but we no longer allow the base
845 // to be installed in the Address class. This jump will tranfers to the address
846 // contained in the location described by entry (not the address of entry)
847 void jump(ArrayAddress entry);
848
849 // Floating
850
851 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
852 void andpd(XMMRegister dst, AddressLiteral src);
853 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
854
855 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
856 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
857 void andps(XMMRegister dst, AddressLiteral src);
858
859 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
860 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
861 void comiss(XMMRegister dst, AddressLiteral src);
862
863 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
864 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
865 void comisd(XMMRegister dst, AddressLiteral src);
866
867 void fadd_s(Address src) { Assembler::fadd_s(src); }
868 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
869
870 void fldcw(Address src) { Assembler::fldcw(src); }
871 void fldcw(AddressLiteral src);
872
873 void fld_s(int index) { Assembler::fld_s(index); }
874 void fld_s(Address src) { Assembler::fld_s(src); }
875 void fld_s(AddressLiteral src);
876
877 void fld_d(Address src) { Assembler::fld_d(src); }
878 void fld_d(AddressLiteral src);
879
880 void fld_x(Address src) { Assembler::fld_x(src); }
881 void fld_x(AddressLiteral src);
882
883 void fmul_s(Address src) { Assembler::fmul_s(src); }
884 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
885
886 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
887 void ldmxcsr(AddressLiteral src);
888
889 #ifdef _LP64
890 private:
891 void sha256_AVX2_one_round_compute(
892 Register reg_old_h,
893 Register reg_a,
894 Register reg_b,
895 Register reg_c,
896 Register reg_d,
897 Register reg_e,
898 Register reg_f,
899 Register reg_g,
900 Register reg_h,
901 int iter);
902 void sha256_AVX2_four_rounds_compute_first(int start);
903 void sha256_AVX2_four_rounds_compute_last(int start);
904 void sha256_AVX2_one_round_and_sched(
905 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
906 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
907 XMMRegister xmm_2, /* ymm6 */
908 XMMRegister xmm_3, /* ymm7 */
909 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
910 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
911 Register reg_c, /* edi */
912 Register reg_d, /* esi */
913 Register reg_e, /* r8d */
914 Register reg_f, /* r9d */
915 Register reg_g, /* r10d */
916 Register reg_h, /* r11d */
917 int iter);
918
919 void addm(int disp, Register r1, Register r2);
920
921 public:
922 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
923 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
924 Register buf, Register state, Register ofs, Register limit, Register rsp,
925 bool multi_block, XMMRegister shuf_mask);
926 #endif
927
928 #ifdef _LP64
929 private:
930 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
931 Register e, Register f, Register g, Register h, int iteration);
932
933 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
934 Register a, Register b, Register c, Register d, Register e, Register f,
935 Register g, Register h, int iteration);
936
937 void addmq(int disp, Register r1, Register r2);
938 public:
939 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
940 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
941 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
942 XMMRegister shuf_mask);
943 #endif
944
945 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
946 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
947 Register buf, Register state, Register ofs, Register limit, Register rsp,
948 bool multi_block);
949
950 #ifdef _LP64
951 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
952 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
953 Register buf, Register state, Register ofs, Register limit, Register rsp,
954 bool multi_block, XMMRegister shuf_mask);
955 #else
956 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
957 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
958 Register buf, Register state, Register ofs, Register limit, Register rsp,
959 bool multi_block);
960 #endif
961
962 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
963 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
964 Register rax, Register rcx, Register rdx, Register tmp);
965
966 #ifdef _LP64
967 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
968 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
969 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
970
971 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
972 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
973 Register rax, Register rcx, Register rdx, Register r11);
974
975 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
976 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
977 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
978
979 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
980 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
981 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
982 Register tmp3, Register tmp4);
983
984 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
985 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
986 Register rax, Register rcx, Register rdx, Register tmp1,
987 Register tmp2, Register tmp3, Register tmp4);
988 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
989 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
990 Register rax, Register rcx, Register rdx, Register tmp1,
991 Register tmp2, Register tmp3, Register tmp4);
992 #else
993 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
994 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
995 Register rax, Register rcx, Register rdx, Register tmp1);
996
997 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
998 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
999 Register rax, Register rcx, Register rdx, Register tmp);
1000
1001 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1002 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1003 Register rdx, Register tmp);
1004
1005 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1006 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1007 Register rax, Register rbx, Register rdx);
1008
1009 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1010 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1011 Register rax, Register rcx, Register rdx, Register tmp);
1012
1013 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1014 Register edx, Register ebx, Register esi, Register edi,
1015 Register ebp, Register esp);
1016
1017 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1018 Register esi, Register edi, Register ebp, Register esp);
1019
1020 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1021 Register edx, Register ebx, Register esi, Register edi,
1022 Register ebp, Register esp);
1023
1024 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1025 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1026 Register rax, Register rcx, Register rdx, Register tmp);
1027 #endif
1028
1029 void increase_precision();
1030 void restore_precision();
1031
1032 private:
1033
1034 // these are private because users should be doing movflt/movdbl
1035
1036 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1037 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1038 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1039 void movss(XMMRegister dst, AddressLiteral src);
1040
1041 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1042 void movlpd(XMMRegister dst, AddressLiteral src);
1043
1044 public:
1045
1046 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1047 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1048 void addsd(XMMRegister dst, AddressLiteral src);
1049
1050 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1051 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1052 void addss(XMMRegister dst, AddressLiteral src);
1053
1054 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1055 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1056 void addpd(XMMRegister dst, AddressLiteral src);
1057
1058 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1059 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1060 void divsd(XMMRegister dst, AddressLiteral src);
1061
1062 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1063 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1064 void divss(XMMRegister dst, AddressLiteral src);
1065
1066 // Move Unaligned Double Quadword
1067 void movdqu(Address dst, XMMRegister src);
1068 void movdqu(XMMRegister dst, Address src);
1069 void movdqu(XMMRegister dst, XMMRegister src);
1070 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1071 // AVX Unaligned forms
1072 void vmovdqu(Address dst, XMMRegister src);
1073 void vmovdqu(XMMRegister dst, Address src);
1074 void vmovdqu(XMMRegister dst, XMMRegister src);
1075 void vmovdqu(XMMRegister dst, AddressLiteral src);
1076
1077 // Move Aligned Double Quadword
1078 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1079 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1080 void movdqa(XMMRegister dst, AddressLiteral src);
1081
1082 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1083 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1084 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1085 void movsd(XMMRegister dst, AddressLiteral src);
1086
1087 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1088 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1089 void mulpd(XMMRegister dst, AddressLiteral src);
1090
1091 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1092 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1093 void mulsd(XMMRegister dst, AddressLiteral src);
1094
1095 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1096 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1097 void mulss(XMMRegister dst, AddressLiteral src);
1098
1099 // Carry-Less Multiplication Quadword
1100 void pclmulldq(XMMRegister dst, XMMRegister src) {
1101 // 0x00 - multiply lower 64 bits [0:63]
1102 Assembler::pclmulqdq(dst, src, 0x00);
1103 }
1104 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1105 // 0x11 - multiply upper 64 bits [64:127]
1106 Assembler::pclmulqdq(dst, src, 0x11);
1107 }
1108
1109 void pcmpeqb(XMMRegister dst, XMMRegister src);
1110 void pcmpeqw(XMMRegister dst, XMMRegister src);
1111
1112 void pcmpestri(XMMRegister dst, Address src, int imm8);
1113 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1114
1115 void pmovzxbw(XMMRegister dst, XMMRegister src);
1116 void pmovzxbw(XMMRegister dst, Address src);
1117
1118 void pmovmskb(Register dst, XMMRegister src);
1119
1120 void ptest(XMMRegister dst, XMMRegister src);
1121
1122 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1123 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1124 void sqrtsd(XMMRegister dst, AddressLiteral src);
1125
1126 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1127 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1128 void sqrtss(XMMRegister dst, AddressLiteral src);
1129
1130 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1131 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1132 void subsd(XMMRegister dst, AddressLiteral src);
1133
1134 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1135 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1136 void subss(XMMRegister dst, AddressLiteral src);
1137
1138 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1139 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1140 void ucomiss(XMMRegister dst, AddressLiteral src);
1141
1142 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1143 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1144 void ucomisd(XMMRegister dst, AddressLiteral src);
1145
1146 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1147 void xorpd(XMMRegister dst, XMMRegister src);
1148 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1149 void xorpd(XMMRegister dst, AddressLiteral src);
1150
1151 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1152 void xorps(XMMRegister dst, XMMRegister src);
1153 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1154 void xorps(XMMRegister dst, AddressLiteral src);
1155
1156 // Shuffle Bytes
1157 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1158 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1159 void pshufb(XMMRegister dst, AddressLiteral src);
1160 // AVX 3-operands instructions
1161
1162 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1163 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1164 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1165
1166 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1167 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1168 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1169
1170 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1171 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1172
1173 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1174 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1175
1176 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1177 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1178
1179 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1180 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1181 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1182
1183 void vpbroadcastw(XMMRegister dst, XMMRegister src);
1184
1185 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1186 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1187
1188 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1189 void vpmovmskb(Register dst, XMMRegister src);
1190
1191 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1192 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1193
1194 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1195 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1196
1197 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1198 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1199
1200 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1201 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1202
1203 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1204 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1205
1206 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1207 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1208
1209 void vptest(XMMRegister dst, XMMRegister src);
1210
1211 void punpcklbw(XMMRegister dst, XMMRegister src);
1212 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1213
1214 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1215 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1216
1217 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1218 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1219 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1220
1221 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1222 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1223 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1224
1225 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1226 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1227 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1228
1229 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1230 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1231 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1232
1233 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1234 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1235 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1236
1237 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1238 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1239 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1240
1241 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1242 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1243 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1244
1245 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1246 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1247 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1248
1249 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1250 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1251
1252 // AVX Vector instructions
1253
1254 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1255 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1256 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1257
1258 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1259 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1260 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1261
1262 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1263 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1264 Assembler::vpxor(dst, nds, src, vector_len);
1265 else
1266 Assembler::vxorpd(dst, nds, src, vector_len);
1267 }
1268 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1269 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1270 Assembler::vpxor(dst, nds, src, vector_len);
1271 else
1272 Assembler::vxorpd(dst, nds, src, vector_len);
1273 }
1274
1275 // Simple version for AVX2 256bit vectors
1276 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1277 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1278
1279 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1280 if (UseAVX > 2) {
1281 Assembler::vinserti32x4(dst, dst, src, imm8);
1282 } else if (UseAVX > 1) {
1283 // vinserti128 is available only in AVX2
1284 Assembler::vinserti128(dst, nds, src, imm8);
1285 } else {
1286 Assembler::vinsertf128(dst, nds, src, imm8);
1287 }
1288 }
1289
1290 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1291 if (UseAVX > 2) {
1292 Assembler::vinserti32x4(dst, dst, src, imm8);
1293 } else if (UseAVX > 1) {
1294 // vinserti128 is available only in AVX2
1295 Assembler::vinserti128(dst, nds, src, imm8);
1296 } else {
1297 Assembler::vinsertf128(dst, nds, src, imm8);
1298 }
1299 }
1300
1301 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1302 if (UseAVX > 2) {
1303 Assembler::vextracti32x4(dst, src, imm8);
1304 } else if (UseAVX > 1) {
1305 // vextracti128 is available only in AVX2
1306 Assembler::vextracti128(dst, src, imm8);
1307 } else {
1308 Assembler::vextractf128(dst, src, imm8);
1309 }
1310 }
1311
1312 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1313 if (UseAVX > 2) {
1314 Assembler::vextracti32x4(dst, src, imm8);
1315 } else if (UseAVX > 1) {
1316 // vextracti128 is available only in AVX2
1317 Assembler::vextracti128(dst, src, imm8);
1318 } else {
1319 Assembler::vextractf128(dst, src, imm8);
1320 }
1321 }
1322
1323 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1324 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1325 vinserti128(dst, dst, src, 1);
1326 }
1327 void vinserti128_high(XMMRegister dst, Address src) {
1328 vinserti128(dst, dst, src, 1);
1329 }
1330 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1331 vextracti128(dst, src, 1);
1332 }
1333 void vextracti128_high(Address dst, XMMRegister src) {
1334 vextracti128(dst, src, 1);
1335 }
1336
1337 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1338 if (UseAVX > 2) {
1339 Assembler::vinsertf32x4(dst, dst, src, 1);
1340 } else {
1341 Assembler::vinsertf128(dst, dst, src, 1);
1342 }
1343 }
1344
1345 void vinsertf128_high(XMMRegister dst, Address src) {
1346 if (UseAVX > 2) {
1347 Assembler::vinsertf32x4(dst, dst, src, 1);
1348 } else {
1349 Assembler::vinsertf128(dst, dst, src, 1);
1350 }
1351 }
1352
1353 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1354 if (UseAVX > 2) {
1355 Assembler::vextractf32x4(dst, src, 1);
1356 } else {
1357 Assembler::vextractf128(dst, src, 1);
1358 }
1359 }
1360
1361 void vextractf128_high(Address dst, XMMRegister src) {
1362 if (UseAVX > 2) {
1363 Assembler::vextractf32x4(dst, src, 1);
1364 } else {
1365 Assembler::vextractf128(dst, src, 1);
1366 }
1367 }
1368
1369 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1370 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1371 Assembler::vinserti64x4(dst, dst, src, 1);
1372 }
1373 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1374 Assembler::vinsertf64x4(dst, dst, src, 1);
1375 }
1376 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1377 Assembler::vextracti64x4(dst, src, 1);
1378 }
1379 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1380 Assembler::vextractf64x4(dst, src, 1);
1381 }
1382 void vextractf64x4_high(Address dst, XMMRegister src) {
1383 Assembler::vextractf64x4(dst, src, 1);
1384 }
1385 void vinsertf64x4_high(XMMRegister dst, Address src) {
1386 Assembler::vinsertf64x4(dst, dst, src, 1);
1387 }
1388
1389 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1390 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1391 vinserti128(dst, dst, src, 0);
1392 }
1393 void vinserti128_low(XMMRegister dst, Address src) {
1394 vinserti128(dst, dst, src, 0);
1395 }
1396 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1397 vextracti128(dst, src, 0);
1398 }
1399 void vextracti128_low(Address dst, XMMRegister src) {
1400 vextracti128(dst, src, 0);
1401 }
1402
1403 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1404 if (UseAVX > 2) {
1405 Assembler::vinsertf32x4(dst, dst, src, 0);
1406 } else {
1407 Assembler::vinsertf128(dst, dst, src, 0);
1408 }
1409 }
1410
1411 void vinsertf128_low(XMMRegister dst, Address src) {
1412 if (UseAVX > 2) {
1413 Assembler::vinsertf32x4(dst, dst, src, 0);
1414 } else {
1415 Assembler::vinsertf128(dst, dst, src, 0);
1416 }
1417 }
1418
1419 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1420 if (UseAVX > 2) {
1421 Assembler::vextractf32x4(dst, src, 0);
1422 } else {
1423 Assembler::vextractf128(dst, src, 0);
1424 }
1425 }
1426
1427 void vextractf128_low(Address dst, XMMRegister src) {
1428 if (UseAVX > 2) {
1429 Assembler::vextractf32x4(dst, src, 0);
1430 } else {
1431 Assembler::vextractf128(dst, src, 0);
1432 }
1433 }
1434
1435 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1436 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1437 Assembler::vinserti64x4(dst, dst, src, 0);
1438 }
1439 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1440 Assembler::vinsertf64x4(dst, dst, src, 0);
1441 }
1442 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1443 Assembler::vextracti64x4(dst, src, 0);
1444 }
1445 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1446 Assembler::vextractf64x4(dst, src, 0);
1447 }
1448 void vextractf64x4_low(Address dst, XMMRegister src) {
1449 Assembler::vextractf64x4(dst, src, 0);
1450 }
1451 void vinsertf64x4_low(XMMRegister dst, Address src) {
1452 Assembler::vinsertf64x4(dst, dst, src, 0);
1453 }
1454
1455 // Carry-Less Multiplication Quadword
1456 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1457 // 0x00 - multiply lower 64 bits [0:63]
1458 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1459 }
1460 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1461 // 0x11 - multiply upper 64 bits [64:127]
1462 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1463 }
1464
1465 // Data
1466
1467 void cmov32( Condition cc, Register dst, Address src);
1468 void cmov32( Condition cc, Register dst, Register src);
1469
1470 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1471
1472 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1473 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1474
1475 void movoop(Register dst, jobject obj);
1476 void movoop(Address dst, jobject obj);
1477
1478 void mov_metadata(Register dst, Metadata* obj);
1479 void mov_metadata(Address dst, Metadata* obj);
1480
1481 void movptr(ArrayAddress dst, Register src);
1482 // can this do an lea?
1483 void movptr(Register dst, ArrayAddress src);
1484
1485 void movptr(Register dst, Address src);
1486
1487 #ifdef _LP64
1488 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1489 #else
1490 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1491 #endif
1492
1493 void movptr(Register dst, intptr_t src);
1494 void movptr(Register dst, Register src);
1495 void movptr(Address dst, intptr_t src);
1496
1497 void movptr(Address dst, Register src);
1498
1499 void movptr(Register dst, RegisterOrConstant src) {
1500 if (src.is_constant()) movptr(dst, src.as_constant());
1501 else movptr(dst, src.as_register());
1502 }
1503
1504 #ifdef _LP64
1505 // Generally the next two are only used for moving NULL
1506 // Although there are situations in initializing the mark word where
1507 // they could be used. They are dangerous.
1508
1509 // They only exist on LP64 so that int32_t and intptr_t are not the same
1510 // and we have ambiguous declarations.
1511
1512 void movptr(Address dst, int32_t imm32);
1513 void movptr(Register dst, int32_t imm32);
1514 #endif // _LP64
1515
1516 // to avoid hiding movl
1517 void mov32(AddressLiteral dst, Register src);
1518 void mov32(Register dst, AddressLiteral src);
1519
1520 // to avoid hiding movb
1521 void movbyte(ArrayAddress dst, int src);
1522
1523 // Import other mov() methods from the parent class or else
1524 // they will be hidden by the following overriding declaration.
1525 using Assembler::movdl;
1526 using Assembler::movq;
1527 void movdl(XMMRegister dst, AddressLiteral src);
1528 void movq(XMMRegister dst, AddressLiteral src);
1529
1530 // Can push value or effective address
1531 void pushptr(AddressLiteral src);
1532
1533 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1534 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1535
1536 void pushoop(jobject obj);
1537 void pushklass(Metadata* obj);
1538
1539 // sign extend as need a l to ptr sized element
1540 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1541 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1542
1543 // C2 compiled method's prolog code.
1544 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1545
1546 // clear memory of size 'cnt' qwords, starting at 'base';
1547 // if 'is_large' is set, do not try to produce short loop
1548 void clear_mem(Register base, Register cnt, Register rtmp, bool is_large);
1549
1550 #ifdef COMPILER2
1551 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1552 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1553
1554 // IndexOf strings.
1555 // Small strings are loaded through stack if they cross page boundary.
1556 void string_indexof(Register str1, Register str2,
1557 Register cnt1, Register cnt2,
1558 int int_cnt2, Register result,
1559 XMMRegister vec, Register tmp,
1560 int ae);
1561
1562 // IndexOf for constant substrings with size >= 8 elements
1563 // which don't need to be loaded through stack.
1564 void string_indexofC8(Register str1, Register str2,
1565 Register cnt1, Register cnt2,
1566 int int_cnt2, Register result,
1567 XMMRegister vec, Register tmp,
1568 int ae);
1569
1570 // Smallest code: we don't need to load through stack,
1571 // check string tail.
1572
1573 // helper function for string_compare
1574 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1575 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1576 Address::ScaleFactor scale2, Register index, int ae);
1577 // Compare strings.
1578 void string_compare(Register str1, Register str2,
1579 Register cnt1, Register cnt2, Register result,
1580 XMMRegister vec1, int ae);
1581
1582 // Search for Non-ASCII character (Negative byte value) in a byte array,
1583 // return true if it has any and false otherwise.
1584 void has_negatives(Register ary1, Register len,
1585 Register result, Register tmp1,
1586 XMMRegister vec1, XMMRegister vec2);
1587
1588 // Compare char[] or byte[] arrays.
1589 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1590 Register limit, Register result, Register chr,
1591 XMMRegister vec1, XMMRegister vec2, bool is_char);
1592
1593 #endif
1594
1595 // Fill primitive arrays
1596 void generate_fill(BasicType t, bool aligned,
1597 Register to, Register value, Register count,
1598 Register rtmp, XMMRegister xtmp);
1599
1600 void encode_iso_array(Register src, Register dst, Register len,
1601 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1602 XMMRegister tmp4, Register tmp5, Register result);
1603
1604 #ifdef _LP64
1605 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1606 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1607 Register y, Register y_idx, Register z,
1608 Register carry, Register product,
1609 Register idx, Register kdx);
1610 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1611 Register yz_idx, Register idx,
1612 Register carry, Register product, int offset);
1613 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1614 Register carry, Register carry2,
1615 Register idx, Register jdx,
1616 Register yz_idx1, Register yz_idx2,
1617 Register tmp, Register tmp3, Register tmp4);
1618 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1619 Register yz_idx, Register idx, Register jdx,
1620 Register carry, Register product,
1621 Register carry2);
1622 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1623 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1624 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1625 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1626 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1627 Register tmp2);
1628 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1629 Register rdxReg, Register raxReg);
1630 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1631 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1632 Register tmp3, Register tmp4);
1633 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1634 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1635
1636 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1637 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1638 Register raxReg);
1639 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1640 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1641 Register raxReg);
1642 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1643 Register result, Register tmp1, Register tmp2,
1644 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1645 #endif
1646
1647 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1648 void update_byte_crc32(Register crc, Register val, Register table);
1649 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1650 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1651 // Note on a naming convention:
1652 // Prefix w = register only used on a Westmere+ architecture
1653 // Prefix n = register only used on a Nehalem architecture
1654 #ifdef _LP64
1655 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1656 Register tmp1, Register tmp2, Register tmp3);
1657 #else
1658 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1659 Register tmp1, Register tmp2, Register tmp3,
1660 XMMRegister xtmp1, XMMRegister xtmp2);
1661 #endif
1662 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1663 Register in_out,
1664 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1665 XMMRegister w_xtmp2,
1666 Register tmp1,
1667 Register n_tmp2, Register n_tmp3);
1668 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1669 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1670 Register tmp1, Register tmp2,
1671 Register n_tmp3);
1672 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1673 Register in_out1, Register in_out2, Register in_out3,
1674 Register tmp1, Register tmp2, Register tmp3,
1675 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1676 Register tmp4, Register tmp5,
1677 Register n_tmp6);
1678 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1679 Register tmp1, Register tmp2, Register tmp3,
1680 Register tmp4, Register tmp5, Register tmp6,
1681 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1682 bool is_pclmulqdq_supported);
1683 // Fold 128-bit data chunk
1684 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1685 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1686 // Fold 8-bit data
1687 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1688 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1689
1690 // Compress char[] array to byte[].
1691 void char_array_compress(Register src, Register dst, Register len,
1692 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1693 XMMRegister tmp4, Register tmp5, Register result);
1694
1695 // Inflate byte[] array to char[].
1696 void byte_array_inflate(Register src, Register dst, Register len,
1697 XMMRegister tmp1, Register tmp2);
1698
1699 };
1700
1701 /**
1702 * class SkipIfEqual:
1703 *
1704 * Instantiating this class will result in assembly code being output that will
1705 * jump around any code emitted between the creation of the instance and it's
1706 * automatic destruction at the end of a scope block, depending on the value of
1707 * the flag passed to the constructor, which will be checked at run-time.
1708 */
1709 class SkipIfEqual {
1710 private:
1711 MacroAssembler* _masm;
1712 Label _label;
1713
1714 public:
1715 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1716 ~SkipIfEqual();
1717 };
1718
1719 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP