src/cpu/aarch64/vm/templateTable_aarch64.cpp

rev 13098 : 8182161: aarch64: combine andr+cbnz into tbnz when possible
Summary: Combine andr+cbnz into tbnz when possible to save one instruction
Reviewed-by: aph

@@ -244,12 +244,11 @@
       // additional, required work.
       assert(byte_no == f1_byte || byte_no == f2_byte, "byte_no out of range");
       assert(load_bc_into_bc_reg, "we use bc_reg as temp");
       __ get_cache_and_index_and_bytecode_at_bcp(temp_reg, bc_reg, temp_reg, byte_no, 1);
       __ movw(bc_reg, bc);
-      __ cmpw(temp_reg, (unsigned) 0);
-      __ br(Assembler::EQ, L_patch_done);  // don't patch
+      __ cbzw(temp_reg, L_patch_done);  // don't patch
     }
     break;
   default:
     assert(byte_no == -1, "sanity");
     // the pair bytecodes have already done the load.