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src/cpu/aarch64/vm/aarch64.ad

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rev 11914 : 8221658: aarch64: add necessary predicate for ubfx patterns
Reviewed-by: aph


3876   predicate(n->get_long() == 65535L);
3877   match(ConL);
3878 
3879   op_cost(0);
3880   format %{ %}
3881   interface(CONST_INTER);
3882 %}
3883 
3884 operand immL_4294967295()
3885 %{
3886   predicate(n->get_long() == 4294967295L);
3887   match(ConL);
3888 
3889   op_cost(0);
3890   format %{ %}
3891   interface(CONST_INTER);
3892 %}
3893 
3894 operand immL_bitmask()
3895 %{
3896   predicate(((n->get_long() & 0xc000000000000000l) == 0)

3897             && is_power_of_2(n->get_long() + 1));
3898   match(ConL);
3899 
3900   op_cost(0);
3901   format %{ %}
3902   interface(CONST_INTER);
3903 %}
3904 
3905 operand immI_bitmask()
3906 %{
3907   predicate(((n->get_int() & 0xc0000000) == 0)

3908             && is_power_of_2(n->get_int() + 1));
3909   match(ConI);
3910 
3911   op_cost(0);
3912   format %{ %}
3913   interface(CONST_INTER);
3914 %}
3915 
3916 // Scale values for scaled offset addressing modes (up to long but not quad)
3917 operand immIScale()
3918 %{
3919   predicate(0 <= n->get_int() && (n->get_int() <= 3));
3920   match(ConI);
3921 
3922   op_cost(0);
3923   format %{ %}
3924   interface(CONST_INTER);
3925 %}
3926 
3927 // 26 bit signed offset -- for pc-relative branches


10888             && (unsigned int)n->in(1)->in(2)->get_int() <= 31);
10889 
10890   ins_cost(INSN_COST * 2);
10891   format %{ "ubfmw  $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %}
10892   ins_encode %{
10893     int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;
10894     int s = 31 - lshift;
10895     int r = (rshift - lshift) & 31;
10896     __ ubfmw(as_Register($dst$$reg),
10897             as_Register($src$$reg),
10898             r, s);
10899   %}
10900 
10901   ins_pipe(ialu_reg_shift);
10902 %}
10903 // Bitfield extract with shift & mask
10904 
10905 instruct ubfxwI(iRegINoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
10906 %{
10907   match(Set dst (AndI (URShiftI src rshift) mask));


10908 
10909   ins_cost(INSN_COST);
10910   format %{ "ubfxw $dst, $src, $mask" %}
10911   ins_encode %{
10912     int rshift = $rshift$$constant;
10913     long mask = $mask$$constant;
10914     int width = exact_log2(mask+1);
10915     __ ubfxw(as_Register($dst$$reg),
10916             as_Register($src$$reg), rshift, width);
10917   %}
10918   ins_pipe(ialu_reg_shift);
10919 %}
10920 instruct ubfxL(iRegLNoSp dst, iRegL src, immI rshift, immL_bitmask mask)
10921 %{
10922   match(Set dst (AndL (URShiftL src rshift) mask));


10923 
10924   ins_cost(INSN_COST);
10925   format %{ "ubfx $dst, $src, $mask" %}
10926   ins_encode %{
10927     int rshift = $rshift$$constant;
10928     long mask = $mask$$constant;
10929     int width = exact_log2(mask+1);
10930     __ ubfx(as_Register($dst$$reg),
10931             as_Register($src$$reg), rshift, width);
10932   %}
10933   ins_pipe(ialu_reg_shift);
10934 %}
10935 
10936 // We can use ubfx when extending an And with a mask when we know mask
10937 // is positive.  We know that because immI_bitmask guarantees it.
10938 instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
10939 %{
10940   match(Set dst (ConvI2L (AndI (URShiftI src rshift) mask)));


10941 
10942   ins_cost(INSN_COST * 2);
10943   format %{ "ubfx $dst, $src, $mask" %}
10944   ins_encode %{
10945     int rshift = $rshift$$constant;
10946     long mask = $mask$$constant;
10947     int width = exact_log2(mask+1);
10948     __ ubfx(as_Register($dst$$reg),
10949             as_Register($src$$reg), rshift, width);
10950   %}
10951   ins_pipe(ialu_reg_shift);
10952 %}
10953 
10954 // Rotations
10955 
10956 instruct extrOrL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
10957 %{
10958   match(Set dst (OrL (LShiftL src1 lshift) (URShiftL src2 rshift)));
10959   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 63));
10960 
10961   ins_cost(INSN_COST);
10962   format %{ "extr $dst, $src1, $src2, #$rshift" %}
10963 
10964   ins_encode %{
10965     __ extr(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),




3876   predicate(n->get_long() == 65535L);
3877   match(ConL);
3878 
3879   op_cost(0);
3880   format %{ %}
3881   interface(CONST_INTER);
3882 %}
3883 
3884 operand immL_4294967295()
3885 %{
3886   predicate(n->get_long() == 4294967295L);
3887   match(ConL);
3888 
3889   op_cost(0);
3890   format %{ %}
3891   interface(CONST_INTER);
3892 %}
3893 
3894 operand immL_bitmask()
3895 %{
3896   predicate((n->get_long() != 0)
3897             && ((n->get_long() & 0xc000000000000000l) == 0)
3898             && is_power_of_2(n->get_long() + 1));
3899   match(ConL);
3900 
3901   op_cost(0);
3902   format %{ %}
3903   interface(CONST_INTER);
3904 %}
3905 
3906 operand immI_bitmask()
3907 %{
3908   predicate((n->get_int() != 0)
3909             && ((n->get_int() & 0xc0000000) == 0)
3910             && is_power_of_2(n->get_int() + 1));
3911   match(ConI);
3912 
3913   op_cost(0);
3914   format %{ %}
3915   interface(CONST_INTER);
3916 %}
3917 
3918 // Scale values for scaled offset addressing modes (up to long but not quad)
3919 operand immIScale()
3920 %{
3921   predicate(0 <= n->get_int() && (n->get_int() <= 3));
3922   match(ConI);
3923 
3924   op_cost(0);
3925   format %{ %}
3926   interface(CONST_INTER);
3927 %}
3928 
3929 // 26 bit signed offset -- for pc-relative branches


10890             && (unsigned int)n->in(1)->in(2)->get_int() <= 31);
10891 
10892   ins_cost(INSN_COST * 2);
10893   format %{ "ubfmw  $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %}
10894   ins_encode %{
10895     int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;
10896     int s = 31 - lshift;
10897     int r = (rshift - lshift) & 31;
10898     __ ubfmw(as_Register($dst$$reg),
10899             as_Register($src$$reg),
10900             r, s);
10901   %}
10902 
10903   ins_pipe(ialu_reg_shift);
10904 %}
10905 // Bitfield extract with shift & mask
10906 
10907 instruct ubfxwI(iRegINoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
10908 %{
10909   match(Set dst (AndI (URShiftI src rshift) mask));
10910   // Make sure we are not going to exceed what ubfxw can do.
10911   predicate((exact_log2(n->in(2)->get_int() + 1) + (n->in(1)->in(2)->get_int() & 31)) <= (31 + 1));
10912 
10913   ins_cost(INSN_COST);
10914   format %{ "ubfxw $dst, $src, $mask" %}
10915   ins_encode %{
10916     int rshift = $rshift$$constant & 31;
10917     long mask = $mask$$constant;
10918     int width = exact_log2(mask+1);
10919     __ ubfxw(as_Register($dst$$reg),
10920             as_Register($src$$reg), rshift, width);
10921   %}
10922   ins_pipe(ialu_reg_shift);
10923 %}
10924 instruct ubfxL(iRegLNoSp dst, iRegL src, immI rshift, immL_bitmask mask)
10925 %{
10926   match(Set dst (AndL (URShiftL src rshift) mask));
10927   // Make sure we are not going to exceed what ubfx can do.
10928   predicate((exact_log2_long(n->in(2)->get_long() + 1) + (n->in(1)->in(2)->get_int() & 63)) <= (63 + 1));
10929 
10930   ins_cost(INSN_COST);
10931   format %{ "ubfx $dst, $src, $mask" %}
10932   ins_encode %{
10933     int rshift = $rshift$$constant & 63;
10934     long mask = $mask$$constant;
10935     int width = exact_log2_long(mask+1);
10936     __ ubfx(as_Register($dst$$reg),
10937             as_Register($src$$reg), rshift, width);
10938   %}
10939   ins_pipe(ialu_reg_shift);
10940 %}
10941 
10942 // We can use ubfx when extending an And with a mask when we know mask
10943 // is positive.  We know that because immI_bitmask guarantees it.
10944 instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
10945 %{
10946   match(Set dst (ConvI2L (AndI (URShiftI src rshift) mask)));
10947   // Make sure we are not going to exceed what ubfxw can do.
10948   predicate((exact_log2(n->in(1)->in(2)->get_int() + 1) + (n->in(1)->in(1)->in(2)->get_int() & 31)) <= (31 + 1));
10949 
10950   ins_cost(INSN_COST * 2);
10951   format %{ "ubfx $dst, $src, $mask" %}
10952   ins_encode %{
10953     int rshift = $rshift$$constant & 31;
10954     long mask = $mask$$constant;
10955     int width = exact_log2(mask+1);
10956     __ ubfx(as_Register($dst$$reg),
10957             as_Register($src$$reg), rshift, width);
10958   %}
10959   ins_pipe(ialu_reg_shift);
10960 %}
10961 
10962 // Rotations
10963 
10964 instruct extrOrL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
10965 %{
10966   match(Set dst (OrL (LShiftL src1 lshift) (URShiftL src2 rshift)));
10967   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 63));
10968 
10969   ins_cost(INSN_COST);
10970   format %{ "extr $dst, $src1, $src2, #$rshift" %}
10971 
10972   ins_encode %{
10973     __ extr(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),


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