2385 f(0b11001110011, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2386 }
2387
2388 INSN(sha512h, 0b100000);
2389 INSN(sha512h2, 0b100001);
2390 INSN(sha512su1, 0b100010);
2391
2392 #undef INSN
2393
2394 #define INSN(NAME, opc) \
2395 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2396 starti; \
2397 assert(T == T2D, "arrangement must be T2D"); \
2398 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2399 }
2400
2401 INSN(sha512su0, 0b1100111011000000100000);
2402
2403 #undef INSN
2404
2405 #define INSN(NAME, opc) \
2406 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2407 starti; \
2408 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2409 }
2410
2411 INSN(aese, 0b0100111000101000010010);
2412 INSN(aesd, 0b0100111000101000010110);
2413 INSN(aesmc, 0b0100111000101000011010);
2414 INSN(aesimc, 0b0100111000101000011110);
2415
2416 #undef INSN
2417
2418 #define INSN(NAME, op1, op2) \
2419 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index = 0) { \
2420 starti; \
2421 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2422 assert(index >= 0 && ((T == T2D && index <= 1) || (T != T2D && index <= 3)), "invalid index"); \
2423 f(0, 31), f((int)T & 1, 30), f(op1, 29); f(0b011111, 28, 23); \
2424 f(T == T2D ? 1 : 0, 22), f(T == T2D ? 0 : index & 1, 21), rf(Vm, 16); \
|
2385 f(0b11001110011, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2386 }
2387
2388 INSN(sha512h, 0b100000);
2389 INSN(sha512h2, 0b100001);
2390 INSN(sha512su1, 0b100010);
2391
2392 #undef INSN
2393
2394 #define INSN(NAME, opc) \
2395 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2396 starti; \
2397 assert(T == T2D, "arrangement must be T2D"); \
2398 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2399 }
2400
2401 INSN(sha512su0, 0b1100111011000000100000);
2402
2403 #undef INSN
2404
2405 #define INSN(NAME, opc) \
2406 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, FloatRegister Va) { \
2407 starti; \
2408 assert(T == T16B, "arrangement must be T16B"); \
2409 f(0b11001110, 31, 24), f(opc, 23, 21), rf(Vm, 16), f(0b0, 15, 15), rf(Va, 10), rf(Vn, 5), rf(Vd, 0); \
2410 }
2411
2412 INSN(eor3, 0b000);
2413 INSN(bcax, 0b001);
2414
2415 #undef INSN
2416
2417 #define INSN(NAME, opc) \
2418 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, unsigned imm) { \
2419 starti; \
2420 assert(T == T2D, "arrangement must be T2D"); \
2421 f(0b11001110, 31, 24), f(opc, 23, 21), rf(Vm, 16), f(imm, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2422 }
2423
2424 INSN(xar, 0b100);
2425
2426 #undef INSN
2427
2428 #define INSN(NAME, opc) \
2429 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2430 starti; \
2431 assert(T == T2D, "arrangement must be T2D"); \
2432 f(0b11001110, 31, 24), f(opc, 23, 21), rf(Vm, 16), f(0b100011, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2433 }
2434
2435 INSN(rax1, 0b011);
2436
2437 #undef INSN
2438
2439 #define INSN(NAME, opc) \
2440 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2441 starti; \
2442 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2443 }
2444
2445 INSN(aese, 0b0100111000101000010010);
2446 INSN(aesd, 0b0100111000101000010110);
2447 INSN(aesmc, 0b0100111000101000011010);
2448 INSN(aesimc, 0b0100111000101000011110);
2449
2450 #undef INSN
2451
2452 #define INSN(NAME, op1, op2) \
2453 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index = 0) { \
2454 starti; \
2455 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2456 assert(index >= 0 && ((T == T2D && index <= 1) || (T != T2D && index <= 3)), "invalid index"); \
2457 f(0, 31), f((int)T & 1, 30), f(op1, 29); f(0b011111, 28, 23); \
2458 f(T == T2D ? 1 : 0, 22), f(T == T2D ? 0 : index & 1, 21), rf(Vm, 16); \
|