1 /* 2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef SHARE_VM_OPTO_MATCHER_HPP 26 #define SHARE_VM_OPTO_MATCHER_HPP 27 28 #include "libadt/vectset.hpp" 29 #include "memory/resourceArea.hpp" 30 #include "opto/node.hpp" 31 #include "opto/phaseX.hpp" 32 #include "opto/regmask.hpp" 33 34 class Compile; 35 class Node; 36 class MachNode; 37 class MachTypeNode; 38 class MachOper; 39 40 //---------------------------Matcher------------------------------------------- 41 class Matcher : public PhaseTransform { 42 friend class VMStructs; 43 // Private arena of State objects 44 ResourceArea _states_arena; 45 46 VectorSet _visited; // Visit bits 47 48 // Used to control the Label pass 49 VectorSet _shared; // Shared Ideal Node 50 VectorSet _dontcare; // Nothing the matcher cares about 51 52 // Private methods which perform the actual matching and reduction 53 // Walks the label tree, generating machine nodes 54 MachNode *ReduceInst( State *s, int rule, Node *&mem); 55 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach); 56 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds); 57 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach ); 58 59 // If this node already matched using "rule", return the MachNode for it. 60 MachNode* find_shared_node(Node* n, uint rule); 61 62 // Convert a dense opcode number to an expanded rule number 63 const int *_reduceOp; 64 const int *_leftOp; 65 const int *_rightOp; 66 67 // Map dense opcode number to info on when rule is swallowed constant. 68 const bool *_swallowed; 69 70 // Map dense rule number to determine if this is an instruction chain rule 71 const uint _begin_inst_chain_rule; 72 const uint _end_inst_chain_rule; 73 74 // We want to clone constants and possible CmpI-variants. 75 // If we do not clone CmpI, then we can have many instances of 76 // condition codes alive at once. This is OK on some chips and 77 // bad on others. Hence the machine-dependent table lookup. 78 const char *_must_clone; 79 80 // Find shared Nodes, or Nodes that otherwise are Matcher roots 81 void find_shared( Node *n ); 82 #ifdef X86 83 bool is_bmi_pattern(Node *n, Node *m); 84 #endif 85 86 // Debug and profile information for nodes in old space: 87 GrowableArray<Node_Notes*>* _old_node_note_array; 88 89 // Node labeling iterator for instruction selection 90 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem ); 91 92 Node *transform( Node *dummy ); 93 94 Node_List _projection_list; // For Machine nodes killing many values 95 96 Node_Array _shared_nodes; 97 98 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots 99 debug_only(Node_Array _new2old_map;) // Maps machine nodes back to ideal 100 101 // Accessors for the inherited field PhaseTransform::_nodes: 102 void grow_new_node_array(uint idx_limit) { 103 _nodes.map(idx_limit-1, NULL); 104 } 105 bool has_new_node(const Node* n) const { 106 return _nodes.at(n->_idx) != NULL; 107 } 108 Node* new_node(const Node* n) const { 109 assert(has_new_node(n), "set before get"); 110 return _nodes.at(n->_idx); 111 } 112 void set_new_node(const Node* n, Node *nn) { 113 assert(!has_new_node(n), "set only once"); 114 _nodes.map(n->_idx, nn); 115 } 116 117 #ifdef ASSERT 118 // Make sure only new nodes are reachable from this node 119 void verify_new_nodes_only(Node* root); 120 121 Node* _mem_node; // Ideal memory node consumed by mach node 122 #endif 123 124 // Mach node for ConP #NULL 125 MachNode* _mach_null; 126 127 public: 128 int LabelRootDepth; 129 // Convert ideal machine register to a register mask for spill-loads 130 static const RegMask *idealreg2regmask[]; 131 RegMask *idealreg2spillmask [_last_machine_leaf]; 132 RegMask *idealreg2debugmask [_last_machine_leaf]; 133 RegMask *idealreg2mhdebugmask[_last_machine_leaf]; 134 void init_spill_mask( Node *ret ); 135 // Convert machine register number to register mask 136 static uint mreg2regmask_max; 137 static RegMask mreg2regmask[]; 138 static RegMask STACK_ONLY_mask; 139 140 MachNode* mach_null() const { return _mach_null; } 141 142 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; } 143 void set_shared( Node *n ) { _shared.set(n->_idx); } 144 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; } 145 void set_visited( Node *n ) { _visited.set(n->_idx); } 146 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; } 147 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); } 148 149 // Mode bit to tell DFA and expand rules whether we are running after 150 // (or during) register selection. Usually, the matcher runs before, 151 // but it will also get called to generate post-allocation spill code. 152 // In this situation, it is a deadly error to attempt to allocate more 153 // temporary registers. 154 bool _allocation_started; 155 156 // Machine register names 157 static const char *regName[]; 158 // Machine register encodings 159 static const unsigned char _regEncode[]; 160 // Machine Node names 161 const char **_ruleName; 162 // Rules that are cheaper to rematerialize than to spill 163 static const uint _begin_rematerialize; 164 static const uint _end_rematerialize; 165 166 // An array of chars, from 0 to _last_Mach_Reg. 167 // No Save = 'N' (for register windows) 168 // Save on Entry = 'E' 169 // Save on Call = 'C' 170 // Always Save = 'A' (same as SOE + SOC) 171 const char *_register_save_policy; 172 const char *_c_reg_save_policy; 173 // Convert a machine register to a machine register type, so-as to 174 // properly match spill code. 175 const int *_register_save_type; 176 // Maps from machine register to boolean; true if machine register can 177 // be holding a call argument in some signature. 178 static bool can_be_java_arg( int reg ); 179 // Maps from machine register to boolean; true if machine register holds 180 // a spillable argument. 181 static bool is_spillable_arg( int reg ); 182 183 // List of IfFalse or IfTrue Nodes that indicate a taken null test. 184 // List is valid in the post-matching space. 185 Node_List _null_check_tests; 186 void collect_null_checks( Node *proj, Node *orig_proj ); 187 void validate_null_checks( ); 188 189 Matcher(); 190 191 // Get a projection node at position pos 192 Node* get_projection(uint pos) { 193 return _projection_list[pos]; 194 } 195 196 // Push a projection node onto the projection list 197 void push_projection(Node* node) { 198 _projection_list.push(node); 199 } 200 201 Node* pop_projection() { 202 return _projection_list.pop(); 203 } 204 205 // Number of nodes in the projection list 206 uint number_of_projections() const { 207 return _projection_list.size(); 208 } 209 210 // Select instructions for entire method 211 void match(); 212 213 // Helper for match 214 OptoReg::Name warp_incoming_stk_arg( VMReg reg ); 215 216 // Transform, then walk. Does implicit DCE while walking. 217 // Name changed from "transform" to avoid it being virtual. 218 Node *xform( Node *old_space_node, int Nodes ); 219 220 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce. 221 MachNode *match_tree( const Node *n ); 222 MachNode *match_sfpt( SafePointNode *sfpt ); 223 // Helper for match_sfpt 224 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ); 225 226 // Initialize first stack mask and related masks. 227 void init_first_stack_mask(); 228 229 // If we should save-on-entry this register 230 bool is_save_on_entry( int reg ); 231 232 // Fixup the save-on-entry registers 233 void Fixup_Save_On_Entry( ); 234 235 // --- Frame handling --- 236 237 // Register number of the stack slot corresponding to the incoming SP. 238 // Per the Big Picture in the AD file, it is: 239 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2. 240 OptoReg::Name _old_SP; 241 242 // Register number of the stack slot corresponding to the highest incoming 243 // argument on the stack. Per the Big Picture in the AD file, it is: 244 // _old_SP + out_preserve_stack_slots + incoming argument size. 245 OptoReg::Name _in_arg_limit; 246 247 // Register number of the stack slot corresponding to the new SP. 248 // Per the Big Picture in the AD file, it is: 249 // _in_arg_limit + pad0 250 OptoReg::Name _new_SP; 251 252 // Register number of the stack slot corresponding to the highest outgoing 253 // argument on the stack. Per the Big Picture in the AD file, it is: 254 // _new_SP + max outgoing arguments of all calls 255 OptoReg::Name _out_arg_limit; 256 257 OptoRegPair *_parm_regs; // Array of machine registers per argument 258 RegMask *_calling_convention_mask; // Array of RegMasks per argument 259 260 // Does matcher have a match rule for this ideal node? 261 static const bool has_match_rule(int opcode); 262 static const bool _hasMatchRule[_last_opcode]; 263 264 // Does matcher have a match rule for this ideal node and is the 265 // predicate (if there is one) true? 266 // NOTE: If this function is used more commonly in the future, ADLC 267 // should generate this one. 268 static const bool match_rule_supported(int opcode); 269 270 // Used to determine if we have fast l2f conversion 271 // USII has it, USIII doesn't 272 static const bool convL2FSupported(void); 273 274 // Vector width in bytes 275 static const int vector_width_in_bytes(BasicType bt); 276 277 // Limits on vector size (number of elements). 278 static const int max_vector_size(const BasicType bt); 279 static const int min_vector_size(const BasicType bt); 280 static const bool vector_size_supported(const BasicType bt, int size) { 281 return (Matcher::max_vector_size(bt) >= size && 282 Matcher::min_vector_size(bt) <= size); 283 } 284 285 // Vector ideal reg 286 static const int vector_ideal_reg(int len); 287 static const int vector_shift_count_ideal_reg(int len); 288 289 // CPU supports misaligned vectors store/load. 290 static const bool misaligned_vectors_ok(); 291 292 // Should original key array reference be passed to AES stubs 293 static const bool pass_original_key_for_aes(); 294 295 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.) 296 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI). 297 // Depends on the details of 64-bit constant generation on the CPU. 298 static const bool isSimpleConstant64(jlong con); 299 300 // These calls are all generated by the ADLC 301 302 // TRUE - grows up, FALSE - grows down (Intel) 303 virtual bool stack_direction() const; 304 305 // Java-Java calling convention 306 // (what you use when Java calls Java) 307 308 // Alignment of stack in bytes, standard Intel word alignment is 4. 309 // Sparc probably wants at least double-word (8). 310 static uint stack_alignment_in_bytes(); 311 // Alignment of stack, measured in stack slots. 312 // The size of stack slots is defined by VMRegImpl::stack_slot_size. 313 static uint stack_alignment_in_slots() { 314 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size); 315 } 316 317 // Array mapping arguments to registers. Argument 0 is usually the 'this' 318 // pointer. Registers can include stack-slots and regular registers. 319 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing ); 320 321 // Convert a sig into a calling convention register layout 322 // and find interesting things about it. 323 static OptoReg::Name find_receiver( bool is_outgoing ); 324 // Return address register. On Intel it is a stack-slot. On PowerPC 325 // it is the Link register. On Sparc it is r31? 326 virtual OptoReg::Name return_addr() const; 327 RegMask _return_addr_mask; 328 // Return value register. On Intel it is EAX. On Sparc i0/o0. 329 static OptoRegPair return_value(int ideal_reg, bool is_outgoing); 330 static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing); 331 RegMask _return_value_mask; 332 // Inline Cache Register 333 static OptoReg::Name inline_cache_reg(); 334 static int inline_cache_reg_encode(); 335 336 // Register for DIVI projection of divmodI 337 static RegMask divI_proj_mask(); 338 // Register for MODI projection of divmodI 339 static RegMask modI_proj_mask(); 340 341 // Register for DIVL projection of divmodL 342 static RegMask divL_proj_mask(); 343 // Register for MODL projection of divmodL 344 static RegMask modL_proj_mask(); 345 346 // Use hardware DIV instruction when it is faster than 347 // a code which use multiply for division by constant. 348 static bool use_asm_for_ldiv_by_con( jlong divisor ); 349 350 static const RegMask method_handle_invoke_SP_save_mask(); 351 352 // Java-Interpreter calling convention 353 // (what you use when calling between compiled-Java and Interpreted-Java 354 355 // Number of callee-save + always-save registers 356 // Ignores frame pointer and "special" registers 357 static int number_of_saved_registers(); 358 359 // The Method-klass-holder may be passed in the inline_cache_reg 360 // and then expanded into the inline_cache_reg and a method_oop register 361 362 static OptoReg::Name interpreter_method_oop_reg(); 363 static int interpreter_method_oop_reg_encode(); 364 365 static OptoReg::Name compiler_method_oop_reg(); 366 static const RegMask &compiler_method_oop_reg_mask(); 367 static int compiler_method_oop_reg_encode(); 368 369 // Interpreter's Frame Pointer Register 370 static OptoReg::Name interpreter_frame_pointer_reg(); 371 372 // Java-Native calling convention 373 // (what you use when intercalling between Java and C++ code) 374 375 // Array mapping arguments to registers. Argument 0 is usually the 'this' 376 // pointer. Registers can include stack-slots and regular registers. 377 static void c_calling_convention( BasicType*, VMRegPair *, uint ); 378 // Frame pointer. The frame pointer is kept at the base of the stack 379 // and so is probably the stack pointer for most machines. On Intel 380 // it is ESP. On the PowerPC it is R1. On Sparc it is SP. 381 OptoReg::Name c_frame_pointer() const; 382 static RegMask c_frame_ptr_mask; 383 384 // !!!!! Special stuff for building ScopeDescs 385 virtual int regnum_to_fpu_offset(int regnum); 386 387 // Is this branch offset small enough to be addressed by a short branch? 388 bool is_short_branch_offset(int rule, int br_size, int offset); 389 390 // Optional scaling for the parameter to the ClearArray/CopyArray node. 391 static const bool init_array_count_is_in_bytes; 392 393 // Threshold small size (in bytes) for a ClearArray/CopyArray node. 394 // Anything this size or smaller may get converted to discrete scalar stores. 395 static const int init_array_short_size; 396 397 // Some hardware needs 2 CMOV's for longs. 398 static const int long_cmove_cost(); 399 400 // Some hardware have expensive CMOV for float and double. 401 static const int float_cmove_cost(); 402 403 // Should the Matcher clone shifts on addressing modes, expecting them to 404 // be subsumed into complex addressing expressions or compute them into 405 // registers? True for Intel but false for most RISCs 406 static const bool clone_shift_expressions; 407 408 static bool narrow_oop_use_complex_address(); 409 static bool narrow_klass_use_complex_address(); 410 411 // Generate implicit null check for narrow oops if it can fold 412 // into address expression (x64). 413 // 414 // [R12 + narrow_oop_reg<<3 + offset] // fold into address expression 415 // NullCheck narrow_oop_reg 416 // 417 // When narrow oops can't fold into address expression (Sparc) and 418 // base is not null use decode_not_null and normal implicit null check. 419 // Note, decode_not_null node can be used here since it is referenced 420 // only on non null path but it requires special handling, see 421 // collect_null_checks(): 422 // 423 // decode_not_null narrow_oop_reg, oop_reg // 'shift' and 'add base' 424 // [oop_reg + offset] 425 // NullCheck oop_reg 426 // 427 // With Zero base and when narrow oops can not fold into address 428 // expression use normal implicit null check since only shift 429 // is needed to decode narrow oop. 430 // 431 // decode narrow_oop_reg, oop_reg // only 'shift' 432 // [oop_reg + offset] 433 // NullCheck oop_reg 434 // 435 inline static bool gen_narrow_oop_implicit_null_checks() { 436 return Universe::narrow_oop_use_implicit_null_checks() && 437 (narrow_oop_use_complex_address() || 438 Universe::narrow_oop_base() != NULL); 439 } 440 441 // Is it better to copy float constants, or load them directly from memory? 442 // Intel can load a float constant from a direct address, requiring no 443 // extra registers. Most RISCs will have to materialize an address into a 444 // register first, so they may as well materialize the constant immediately. 445 static const bool rematerialize_float_constants; 446 447 // If CPU can load and store mis-aligned doubles directly then no fixup is 448 // needed. Else we split the double into 2 integer pieces and move it 449 // piece-by-piece. Only happens when passing doubles into C code or when 450 // calling i2c adapters as the Java calling convention forces doubles to be 451 // aligned. 452 static const bool misaligned_doubles_ok; 453 454 // Does the CPU require postalloc expand (see block.cpp for description of 455 // postalloc expand)? 456 static const bool require_postalloc_expand; 457 458 // Perform a platform dependent implicit null fixup. This is needed 459 // on windows95 to take care of some unusual register constraints. 460 void pd_implicit_null_fixup(MachNode *load, uint idx); 461 462 // Advertise here if the CPU requires explicit rounding operations 463 // to implement the UseStrictFP mode. 464 static const bool strict_fp_requires_explicit_rounding; 465 466 // Are floats conerted to double when stored to stack during deoptimization? 467 static bool float_in_double(); 468 // Do ints take an entire long register or just half? 469 static const bool int_in_long; 470 471 // Do the processor's shift instructions only use the low 5/6 bits 472 // of the count for 32/64 bit ints? If not we need to do the masking 473 // ourselves. 474 static const bool need_masked_shift_count; 475 476 // This routine is run whenever a graph fails to match. 477 // If it returns, the compiler should bailout to interpreter without error. 478 // In non-product mode, SoftMatchFailure is false to detect non-canonical 479 // graphs. Print a message and exit. 480 static void soft_match_failure() { 481 if( SoftMatchFailure ) return; 482 else { fatal("SoftMatchFailure is not allowed except in product"); } 483 } 484 485 // Check for a following volatile memory barrier without an 486 // intervening load and thus we don't need a barrier here. We 487 // retain the Node to act as a compiler ordering barrier. 488 static bool post_store_load_barrier(const Node* mb); 489 490 // Does n lead to an uncommon trap that can cause deoptimization? 491 static bool branches_to_uncommon_trap(const Node *n); 492 493 #ifdef ASSERT 494 void dump_old2new_map(); // machine-independent to machine-dependent 495 496 Node* find_old_node(Node* new_node) { 497 return _new2old_map[new_node->_idx]; 498 } 499 #endif 500 }; 501 502 #endif // SHARE_VM_OPTO_MATCHER_HPP