1 /* 2 * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2016 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_S390_VM_ASSEMBLER_S390_HPP 27 #define CPU_S390_VM_ASSEMBLER_S390_HPP 28 29 #undef LUCY_DBG 30 31 #define NearLabel Label 32 33 // Immediate is an abstraction to represent the various immediate 34 // operands which exist on z/Architecture. Neither this class nor 35 // instances hereof have an own state. It consists of methods only. 36 class Immediate VALUE_OBJ_CLASS_SPEC { 37 38 public: 39 static bool is_simm(int64_t x, unsigned int nbits) { 40 // nbits < 2 --> false 41 // nbits >= 64 --> true 42 assert(2 <= nbits && nbits < 64, "Don't call, use statically known result."); 43 const int64_t min = -(1L << (nbits-1)); 44 const int64_t maxplus1 = (1L << (nbits-1)); 45 return min <= x && x < maxplus1; 46 } 47 static bool is_simm32(int64_t x) { 48 return is_simm(x, 32); 49 } 50 static bool is_simm20(int64_t x) { 51 return is_simm(x, 20); 52 } 53 static bool is_simm16(int64_t x) { 54 return is_simm(x, 16); 55 } 56 static bool is_simm8(int64_t x) { 57 return is_simm(x, 8); 58 } 59 60 // Test if x is within signed immediate range for nbits. 61 static bool is_uimm(int64_t x, unsigned int nbits) { 62 // nbits == 0 --> false 63 // nbits >= 64 --> true 64 assert(1 <= nbits && nbits < 64, "don't call, use statically known result"); 65 const uint64_t xu = (unsigned long)x; 66 const uint64_t maxplus1 = 1UL << nbits; 67 return xu < maxplus1; // Unsigned comparison. Negative inputs appear to be very large. 68 } 69 static bool is_uimm32(int64_t x) { 70 return is_uimm(x, 32); 71 } 72 static bool is_uimm16(int64_t x) { 73 return is_uimm(x, 16); 74 } 75 static bool is_uimm12(int64_t x) { 76 return is_uimm(x, 12); 77 } 78 static bool is_uimm8(int64_t x) { 79 return is_uimm(x, 8); 80 } 81 }; 82 83 // Displacement is an abstraction to represent the various 84 // displacements which exist with addresses on z/ArchiTecture. 85 // Neither this class nor instances hereof have an own state. It 86 // consists of methods only. 87 class Displacement VALUE_OBJ_CLASS_SPEC { 88 89 public: // These tests are used outside the (Macro)Assembler world, e.g. in ad-file. 90 91 static bool is_longDisp(int64_t x) { // Fits in a 20-bit displacement field. 92 return Immediate::is_simm20(x); 93 } 94 static bool is_shortDisp(int64_t x) { // Fits in a 12-bit displacement field. 95 return Immediate::is_uimm12(x); 96 } 97 static bool is_validDisp(int64_t x) { // Is a valid displacement, regardless of length constraints. 98 return is_longDisp(x); 99 } 100 }; 101 102 // RelAddr is an abstraction to represent relative addresses in the 103 // form they are used on z/Architecture for instructions which access 104 // their operand with pc-relative addresses. Neither this class nor 105 // instances hereof have an own state. It consists of methods only. 106 class RelAddr VALUE_OBJ_CLASS_SPEC { 107 108 private: // No public use at all. Solely for (Macro)Assembler. 109 110 static bool is_in_range_of_RelAddr(address target, address pc, bool shortForm) { 111 // Guard against illegal branch targets, e.g. -1. Occurrences in 112 // CompiledStaticCall and ad-file. Do not assert (it's a test 113 // function!). Just return false in case of illegal operands. 114 if ((((uint64_t)target) & 0x0001L) != 0) return false; 115 if ((((uint64_t)pc) & 0x0001L) != 0) return false; 116 117 if (shortForm) { 118 return Immediate::is_simm((int64_t)(target-pc), 17); // Relative short addresses can reach +/- 2**16 bytes. 119 } else { 120 return Immediate::is_simm((int64_t)(target-pc), 33); // Relative long addresses can reach +/- 2**32 bytes. 121 } 122 } 123 124 static bool is_in_range_of_RelAddr16(address target, address pc) { 125 return is_in_range_of_RelAddr(target, pc, true); 126 } 127 static bool is_in_range_of_RelAddr16(ptrdiff_t distance) { 128 return is_in_range_of_RelAddr((address)distance, 0, true); 129 } 130 131 static bool is_in_range_of_RelAddr32(address target, address pc) { 132 return is_in_range_of_RelAddr(target, pc, false); 133 } 134 static bool is_in_range_of_RelAddr32(ptrdiff_t distance) { 135 return is_in_range_of_RelAddr((address)distance, 0, false); 136 } 137 138 static int pcrel_off(address target, address pc, bool shortForm) { 139 assert(((uint64_t)target & 0x0001L) == 0, "target of a relative address must be aligned"); 140 assert(((uint64_t)pc & 0x0001L) == 0, "origin of a relative address must be aligned"); 141 142 if ((target == NULL) || (target == pc)) { 143 return 0; // Yet unknown branch destination. 144 } else { 145 guarantee(is_in_range_of_RelAddr(target, pc, shortForm), "target not within reach"); 146 return (int)((target - pc)>>1); 147 } 148 } 149 150 static int pcrel_off16(address target, address pc) { 151 return pcrel_off(target, pc, true); 152 } 153 static int pcrel_off16(ptrdiff_t distance) { 154 return pcrel_off((address)distance, 0, true); 155 } 156 157 static int pcrel_off32(address target, address pc) { 158 return pcrel_off(target, pc, false); 159 } 160 static int pcrel_off32(ptrdiff_t distance) { 161 return pcrel_off((address)distance, 0, false); 162 } 163 164 static ptrdiff_t inv_pcrel_off16(int offset) { 165 return ((ptrdiff_t)offset)<<1; 166 } 167 168 static ptrdiff_t inv_pcrel_off32(int offset) { 169 return ((ptrdiff_t)offset)<<1; 170 } 171 172 friend class Assembler; 173 friend class MacroAssembler; 174 friend class NativeGeneralJump; 175 }; 176 177 // Address is an abstraction used to represent a memory location 178 // as passed to Z assembler instructions. 179 // 180 // Note: A register location is represented via a Register, not 181 // via an address for efficiency & simplicity reasons. 182 class Address VALUE_OBJ_CLASS_SPEC { 183 private: 184 Register _base; // Base register. 185 Register _index; // Index register 186 intptr_t _disp; // Constant displacement. 187 188 public: 189 Address() : 190 _base(noreg), 191 _index(noreg), 192 _disp(0) {} 193 194 Address(Register base, Register index, intptr_t disp = 0) : 195 _base(base), 196 _index(index), 197 _disp(disp) {} 198 199 Address(Register base, intptr_t disp = 0) : 200 _base(base), 201 _index(noreg), 202 _disp(disp) {} 203 204 Address(Register base, RegisterOrConstant roc, intptr_t disp = 0) : 205 _base(base), 206 _index(noreg), 207 _disp(disp) { 208 if (roc.is_constant()) _disp += roc.as_constant(); else _index = roc.as_register(); 209 } 210 211 #ifdef ASSERT 212 // ByteSize is only a class when ASSERT is defined, otherwise it's an int. 213 Address(Register base, ByteSize disp) : 214 _base(base), 215 _index(noreg), 216 _disp(in_bytes(disp)) {} 217 218 Address(Register base, Register index, ByteSize disp) : 219 _base(base), 220 _index(index), 221 _disp(in_bytes(disp)) {} 222 #endif 223 224 // Aborts if disp is a register and base and index are set already. 225 Address plus_disp(RegisterOrConstant disp) const { 226 Address a = (*this); 227 a._disp += disp.constant_or_zero(); 228 if (disp.is_register()) { 229 if (a._index == noreg) { 230 a._index = disp.as_register(); 231 } else { 232 guarantee(_base == noreg, "can not encode"); a._base = disp.as_register(); 233 } 234 } 235 return a; 236 } 237 238 // A call to this is generated by adlc for replacement variable $xxx$$Address. 239 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); 240 241 bool is_same_address(Address a) const { 242 return _base == a._base && _index == a._index && _disp == a._disp; 243 } 244 245 // testers 246 bool has_base() const { return _base != noreg; } 247 bool has_index() const { return _index != noreg; } 248 bool has_disp() const { return true; } // There is no "invalid" value. 249 250 bool is_disp12() const { return Immediate::is_uimm12(disp()); } 251 bool is_disp20() const { return Immediate::is_simm20(disp()); } 252 bool is_RSform() { return has_base() && !has_index() && is_disp12(); } 253 bool is_RSYform() { return has_base() && !has_index() && is_disp20(); } 254 bool is_RXform() { return has_base() && has_index() && is_disp12(); } 255 bool is_RXEform() { return has_base() && has_index() && is_disp12(); } 256 bool is_RXYform() { return has_base() && has_index() && is_disp20(); } 257 258 bool uses(Register r) { return _base == r || _index == r; }; 259 260 // accessors 261 Register base() const { return _base; } 262 Register baseOrR0() const { assert(_base != Z_R0, ""); return _base == noreg ? Z_R0 : _base; } 263 Register index() const { return _index; } 264 Register indexOrR0() const { assert(_index != Z_R0, ""); return _index == noreg ? Z_R0 : _index; } 265 intptr_t disp() const { return _disp; } 266 // Specific version for short displacement instructions. 267 int disp12() const { 268 assert(is_disp12(), "displacement out of range for uimm12"); 269 return _disp; 270 } 271 // Specific version for long displacement instructions. 272 int disp20() const { 273 assert(is_disp20(), "displacement out of range for simm20"); 274 return _disp; 275 } 276 intptr_t value() const { return _disp; } 277 278 friend class Assembler; 279 }; 280 281 class AddressLiteral VALUE_OBJ_CLASS_SPEC { 282 private: 283 address _address; 284 RelocationHolder _rspec; 285 286 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { 287 switch (rtype) { 288 case relocInfo::external_word_type: 289 return external_word_Relocation::spec(addr); 290 case relocInfo::internal_word_type: 291 return internal_word_Relocation::spec(addr); 292 case relocInfo::opt_virtual_call_type: 293 return opt_virtual_call_Relocation::spec(); 294 case relocInfo::static_call_type: 295 return static_call_Relocation::spec(); 296 case relocInfo::runtime_call_w_cp_type: 297 return runtime_call_w_cp_Relocation::spec(); 298 case relocInfo::none: 299 return RelocationHolder(); 300 default: 301 ShouldNotReachHere(); 302 return RelocationHolder(); 303 } 304 } 305 306 protected: 307 // creation 308 AddressLiteral() : _address(NULL), _rspec(NULL) {} 309 310 public: 311 AddressLiteral(address addr, RelocationHolder const& rspec) 312 : _address(addr), 313 _rspec(rspec) {} 314 315 // Some constructors to avoid casting at the call site. 316 AddressLiteral(jobject obj, RelocationHolder const& rspec) 317 : _address((address) obj), 318 _rspec(rspec) {} 319 320 AddressLiteral(intptr_t value, RelocationHolder const& rspec) 321 : _address((address) value), 322 _rspec(rspec) {} 323 324 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none) 325 : _address((address) addr), 326 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 327 328 // Some constructors to avoid casting at the call site. 329 AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none) 330 : _address((address) addr), 331 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 332 333 AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none) 334 : _address((address) addr), 335 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 336 337 AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none) 338 : _address((address) addr), 339 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 340 341 AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none) 342 : _address((address) addr), 343 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 344 345 AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none) 346 : _address((address) addr), 347 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 348 349 AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none) 350 : _address((address) addr), 351 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 352 353 AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none) 354 : _address((address) addr), 355 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 356 357 AddressLiteral(oop addr, relocInfo::relocType rtype = relocInfo::none) 358 : _address((address) addr), 359 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 360 361 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none) 362 : _address((address) addr), 363 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 364 365 AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none) 366 : _address((address) addr), 367 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 368 369 AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none) 370 : _address((address) addr), 371 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 372 373 intptr_t value() const { return (intptr_t) _address; } 374 375 const relocInfo::relocType rtype() const { return _rspec.type(); } 376 const RelocationHolder& rspec() const { return _rspec; } 377 378 RelocationHolder rspec(int offset) const { 379 return offset == 0 ? _rspec : _rspec.plus(offset); 380 } 381 }; 382 383 // Convenience classes 384 class ExternalAddress: public AddressLiteral { 385 private: 386 static relocInfo::relocType reloc_for_target(address target) { 387 // Sometimes ExternalAddress is used for values which aren't 388 // exactly addresses, like the card table base. 389 // External_word_type can't be used for values in the first page 390 // so just skip the reloc in that case. 391 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; 392 } 393 394 public: 395 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target( target)) {} 396 ExternalAddress(oop* target) : AddressLiteral(target, reloc_for_target((address) target)) {} 397 }; 398 399 // Argument is an abstraction used to represent an outgoing actual 400 // argument or an incoming formal parameter, whether it resides in 401 // memory or in a register, in a manner consistent with the 402 // z/Architecture Application Binary Interface, or ABI. This is often 403 // referred to as the native or C calling convention. 404 class Argument VALUE_OBJ_CLASS_SPEC { 405 private: 406 int _number; 407 bool _is_in; 408 409 public: 410 enum { 411 // Only 5 registers may contain integer parameters. 412 n_register_parameters = 5, 413 // Can have up to 4 floating registers. 414 n_float_register_parameters = 4 415 }; 416 417 // creation 418 Argument(int number, bool is_in) : _number(number), _is_in(is_in) {} 419 Argument(int number) : _number(number) {} 420 421 int number() const { return _number; } 422 423 Argument successor() const { return Argument(number() + 1); } 424 425 // Locating register-based arguments: 426 bool is_register() const { return _number < n_register_parameters; } 427 428 // Locating Floating Point register-based arguments: 429 bool is_float_register() const { return _number < n_float_register_parameters; } 430 431 FloatRegister as_float_register() const { 432 assert(is_float_register(), "must be a register argument"); 433 return as_FloatRegister((number() *2) + 1); 434 } 435 436 FloatRegister as_double_register() const { 437 assert(is_float_register(), "must be a register argument"); 438 return as_FloatRegister((number() *2)); 439 } 440 441 Register as_register() const { 442 assert(is_register(), "must be a register argument"); 443 return as_Register(number() + Z_ARG1->encoding()); 444 } 445 446 // debugging 447 const char* name() const; 448 449 friend class Assembler; 450 }; 451 452 453 // The z/Architecture Assembler: Pure assembler doing NO optimizations 454 // on the instruction level; i.e., what you write is what you get. The 455 // Assembler is generating code into a CodeBuffer. 456 class Assembler : public AbstractAssembler { 457 protected: 458 459 friend class AbstractAssembler; 460 friend class AddressLiteral; 461 462 // Code patchers need various routines like inv_wdisp(). 463 friend class NativeInstruction; 464 #ifndef COMPILER2 465 friend class NativeGeneralJump; 466 #endif 467 friend class Relocation; 468 469 public: 470 471 // Addressing 472 473 // address calculation 474 #define LA_ZOPC (unsigned int)(0x41 << 24) 475 #define LAY_ZOPC (unsigned long)(0xe3L << 40 | 0x71L) 476 #define LARL_ZOPC (unsigned long)(0xc0L << 40 | 0x00L << 32) 477 478 479 // Data Transfer 480 481 // register to register transfer 482 #define LR_ZOPC (unsigned int)(24 << 8) 483 #define LBR_ZOPC (unsigned int)(0xb926 << 16) 484 #define LHR_ZOPC (unsigned int)(0xb927 << 16) 485 #define LGBR_ZOPC (unsigned int)(0xb906 << 16) 486 #define LGHR_ZOPC (unsigned int)(0xb907 << 16) 487 #define LGFR_ZOPC (unsigned int)(0xb914 << 16) 488 #define LGR_ZOPC (unsigned int)(0xb904 << 16) 489 490 #define LLHR_ZOPC (unsigned int)(0xb995 << 16) 491 #define LLGCR_ZOPC (unsigned int)(0xb984 << 16) 492 #define LLGHR_ZOPC (unsigned int)(0xb985 << 16) 493 #define LLGTR_ZOPC (unsigned int)(185 << 24 | 23 << 16) 494 #define LLGFR_ZOPC (unsigned int)(185 << 24 | 22 << 16) 495 496 #define LTR_ZOPC (unsigned int)(18 << 8) 497 #define LTGFR_ZOPC (unsigned int)(185 << 24 | 18 << 16) 498 #define LTGR_ZOPC (unsigned int)(185 << 24 | 2 << 16) 499 500 #define LER_ZOPC (unsigned int)(56 << 8) 501 #define LEDBR_ZOPC (unsigned int)(179 << 24 | 68 << 16) 502 #define LEXBR_ZOPC (unsigned int)(179 << 24 | 70 << 16) 503 #define LDEBR_ZOPC (unsigned int)(179 << 24 | 4 << 16) 504 #define LDR_ZOPC (unsigned int)(40 << 8) 505 #define LDXBR_ZOPC (unsigned int)(179 << 24 | 69 << 16) 506 #define LXEBR_ZOPC (unsigned int)(179 << 24 | 6 << 16) 507 #define LXDBR_ZOPC (unsigned int)(179 << 24 | 5 << 16) 508 #define LXR_ZOPC (unsigned int)(179 << 24 | 101 << 16) 509 #define LTEBR_ZOPC (unsigned int)(179 << 24 | 2 << 16) 510 #define LTDBR_ZOPC (unsigned int)(179 << 24 | 18 << 16) 511 #define LTXBR_ZOPC (unsigned int)(179 << 24 | 66 << 16) 512 513 #define LRVR_ZOPC (unsigned int)(0xb91f << 16) 514 #define LRVGR_ZOPC (unsigned int)(0xb90f << 16) 515 516 #define LDGR_ZOPC (unsigned int)(0xb3c1 << 16) // z10 517 #define LGDR_ZOPC (unsigned int)(0xb3cd << 16) // z10 518 519 #define LOCR_ZOPC (unsigned int)(0xb9f2 << 16) // z196 520 #define LOCGR_ZOPC (unsigned int)(0xb9e2 << 16) // z196 521 522 // immediate to register transfer 523 #define IIHH_ZOPC (unsigned int)(165 << 24) 524 #define IIHL_ZOPC (unsigned int)(165 << 24 | 1 << 16) 525 #define IILH_ZOPC (unsigned int)(165 << 24 | 2 << 16) 526 #define IILL_ZOPC (unsigned int)(165 << 24 | 3 << 16) 527 #define IIHF_ZOPC (unsigned long)(0xc0L << 40 | 8L << 32) 528 #define IILF_ZOPC (unsigned long)(0xc0L << 40 | 9L << 32) 529 #define LLIHH_ZOPC (unsigned int)(165 << 24 | 12 << 16) 530 #define LLIHL_ZOPC (unsigned int)(165 << 24 | 13 << 16) 531 #define LLILH_ZOPC (unsigned int)(165 << 24 | 14 << 16) 532 #define LLILL_ZOPC (unsigned int)(165 << 24 | 15 << 16) 533 #define LLIHF_ZOPC (unsigned long)(0xc0L << 40 | 14L << 32) 534 #define LLILF_ZOPC (unsigned long)(0xc0L << 40 | 15L << 32) 535 #define LHI_ZOPC (unsigned int)(167 << 24 | 8 << 16) 536 #define LGHI_ZOPC (unsigned int)(167 << 24 | 9 << 16) 537 #define LGFI_ZOPC (unsigned long)(0xc0L << 40 | 1L << 32) 538 539 #define LZER_ZOPC (unsigned int)(0xb374 << 16) 540 #define LZDR_ZOPC (unsigned int)(0xb375 << 16) 541 542 // LOAD: memory to register transfer 543 #define LB_ZOPC (unsigned long)(227L << 40 | 118L) 544 #define LH_ZOPC (unsigned int)(72 << 24) 545 #define LHY_ZOPC (unsigned long)(227L << 40 | 120L) 546 #define L_ZOPC (unsigned int)(88 << 24) 547 #define LY_ZOPC (unsigned long)(227L << 40 | 88L) 548 #define LT_ZOPC (unsigned long)(0xe3L << 40 | 0x12L) 549 #define LGB_ZOPC (unsigned long)(227L << 40 | 119L) 550 #define LGH_ZOPC (unsigned long)(227L << 40 | 21L) 551 #define LGF_ZOPC (unsigned long)(227L << 40 | 20L) 552 #define LG_ZOPC (unsigned long)(227L << 40 | 4L) 553 #define LTG_ZOPC (unsigned long)(0xe3L << 40 | 0x02L) 554 #define LTGF_ZOPC (unsigned long)(0xe3L << 40 | 0x32L) 555 556 #define LLC_ZOPC (unsigned long)(0xe3L << 40 | 0x94L) 557 #define LLH_ZOPC (unsigned long)(0xe3L << 40 | 0x95L) 558 #define LLGT_ZOPC (unsigned long)(227L << 40 | 23L) 559 #define LLGC_ZOPC (unsigned long)(227L << 40 | 144L) 560 #define LLGH_ZOPC (unsigned long)(227L << 40 | 145L) 561 #define LLGF_ZOPC (unsigned long)(227L << 40 | 22L) 562 563 #define IC_ZOPC (unsigned int)(0x43 << 24) 564 #define ICY_ZOPC (unsigned long)(0xe3L << 40 | 0x73L) 565 #define ICM_ZOPC (unsigned int)(0xbf << 24) 566 #define ICMY_ZOPC (unsigned long)(0xebL << 40 | 0x81L) 567 #define ICMH_ZOPC (unsigned long)(0xebL << 40 | 0x80L) 568 569 #define LRVH_ZOPC (unsigned long)(0xe3L << 40 | 0x1fL) 570 #define LRV_ZOPC (unsigned long)(0xe3L << 40 | 0x1eL) 571 #define LRVG_ZOPC (unsigned long)(0xe3L << 40 | 0x0fL) 572 573 574 // LOAD relative: memory to register transfer 575 #define LHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x05L << 32) // z10 576 #define LRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0dL << 32) // z10 577 #define LGHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x04L << 32) // z10 578 #define LGFRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0cL << 32) // z10 579 #define LGRL_ZOPC (unsigned long)(0xc4L << 40 | 0x08L << 32) // z10 580 581 #define LLHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x02L << 32) // z10 582 #define LLGHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x06L << 32) // z10 583 #define LLGFRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0eL << 32) // z10 584 585 #define LOC_ZOPC (unsigned long)(0xebL << 40 | 0xf2L) // z196 586 #define LOCG_ZOPC (unsigned long)(0xebL << 40 | 0xe2L) // z196 587 588 #define LMG_ZOPC (unsigned long)(235L << 40 | 4L) 589 590 #define LE_ZOPC (unsigned int)(0x78 << 24) 591 #define LEY_ZOPC (unsigned long)(237L << 40 | 100L) 592 #define LDEB_ZOPC (unsigned long)(237L << 40 | 4) 593 #define LD_ZOPC (unsigned int)(0x68 << 24) 594 #define LDY_ZOPC (unsigned long)(237L << 40 | 101L) 595 #define LXEB_ZOPC (unsigned long)(237L << 40 | 6) 596 #define LXDB_ZOPC (unsigned long)(237L << 40 | 5) 597 598 // STORE: register to memory transfer 599 #define STC_ZOPC (unsigned int)(0x42 << 24) 600 #define STCY_ZOPC (unsigned long)(227L << 40 | 114L) 601 #define STH_ZOPC (unsigned int)(64 << 24) 602 #define STHY_ZOPC (unsigned long)(227L << 40 | 112L) 603 #define ST_ZOPC (unsigned int)(80 << 24) 604 #define STY_ZOPC (unsigned long)(227L << 40 | 80L) 605 #define STG_ZOPC (unsigned long)(227L << 40 | 36L) 606 607 #define STCM_ZOPC (unsigned long)(0xbeL << 24) 608 #define STCMY_ZOPC (unsigned long)(0xebL << 40 | 0x2dL) 609 #define STCMH_ZOPC (unsigned long)(0xebL << 40 | 0x2cL) 610 611 // STORE relative: memory to register transfer 612 #define STHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x07L << 32) // z10 613 #define STRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0fL << 32) // z10 614 #define STGRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0bL << 32) // z10 615 616 #define STOC_ZOPC (unsigned long)(0xebL << 40 | 0xf3L) // z196 617 #define STOCG_ZOPC (unsigned long)(0xebL << 40 | 0xe3L) // z196 618 619 #define STMG_ZOPC (unsigned long)(235L << 40 | 36L) 620 621 #define STE_ZOPC (unsigned int)(0x70 << 24) 622 #define STEY_ZOPC (unsigned long)(237L << 40 | 102L) 623 #define STD_ZOPC (unsigned int)(0x60 << 24) 624 #define STDY_ZOPC (unsigned long)(237L << 40 | 103L) 625 626 // MOVE: immediate to memory transfer 627 #define MVHHI_ZOPC (unsigned long)(0xe5L << 40 | 0x44L << 32) // z10 628 #define MVHI_ZOPC (unsigned long)(0xe5L << 40 | 0x4cL << 32) // z10 629 #define MVGHI_ZOPC (unsigned long)(0xe5L << 40 | 0x48L << 32) // z10 630 631 632 // ALU operations 633 634 // Load Positive 635 #define LPR_ZOPC (unsigned int)(16 << 8) 636 #define LPGFR_ZOPC (unsigned int)(185 << 24 | 16 << 16) 637 #define LPGR_ZOPC (unsigned int)(185 << 24) 638 #define LPEBR_ZOPC (unsigned int)(179 << 24) 639 #define LPDBR_ZOPC (unsigned int)(179 << 24 | 16 << 16) 640 #define LPXBR_ZOPC (unsigned int)(179 << 24 | 64 << 16) 641 642 // Load Negative 643 #define LNR_ZOPC (unsigned int)(17 << 8) 644 #define LNGFR_ZOPC (unsigned int)(185 << 24 | 17 << 16) 645 #define LNGR_ZOPC (unsigned int)(185 << 24 | 1 << 16) 646 #define LNEBR_ZOPC (unsigned int)(179 << 24 | 1 << 16) 647 #define LNDBR_ZOPC (unsigned int)(179 << 24 | 17 << 16) 648 #define LNXBR_ZOPC (unsigned int)(179 << 24 | 65 << 16) 649 650 // Load Complement 651 #define LCR_ZOPC (unsigned int)(19 << 8) 652 #define LCGFR_ZOPC (unsigned int)(185 << 24 | 19 << 16) 653 #define LCGR_ZOPC (unsigned int)(185 << 24 | 3 << 16) 654 #define LCEBR_ZOPC (unsigned int)(179 << 24 | 3 << 16) 655 #define LCDBR_ZOPC (unsigned int)(179 << 24 | 19 << 16) 656 #define LCXBR_ZOPC (unsigned int)(179 << 24 | 67 << 16) 657 658 // Add 659 // RR, signed 660 #define AR_ZOPC (unsigned int)(26 << 8) 661 #define AGFR_ZOPC (unsigned int)(0xb9 << 24 | 0x18 << 16) 662 #define AGR_ZOPC (unsigned int)(0xb9 << 24 | 0x08 << 16) 663 // RRF, signed 664 #define ARK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f8 << 16) 665 #define AGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e8 << 16) 666 // RI, signed 667 #define AHI_ZOPC (unsigned int)(167 << 24 | 10 << 16) 668 #define AFI_ZOPC (unsigned long)(0xc2L << 40 | 9L << 32) 669 #define AGHI_ZOPC (unsigned int)(167 << 24 | 11 << 16) 670 #define AGFI_ZOPC (unsigned long)(0xc2L << 40 | 8L << 32) 671 // RIE, signed 672 #define AHIK_ZOPC (unsigned long)(0xecL << 40 | 0x00d8L) 673 #define AGHIK_ZOPC (unsigned long)(0xecL << 40 | 0x00d9L) 674 #define AIH_ZOPC (unsigned long)(0xccL << 40 | 0x08L << 32) 675 // RM, signed 676 #define AHY_ZOPC (unsigned long)(227L << 40 | 122L) 677 #define A_ZOPC (unsigned int)(90 << 24) 678 #define AY_ZOPC (unsigned long)(227L << 40 | 90L) 679 #define AGF_ZOPC (unsigned long)(227L << 40 | 24L) 680 #define AG_ZOPC (unsigned long)(227L << 40 | 8L) 681 // In-memory arithmetic (add signed, add logical with signed immediate). 682 // MI, signed 683 #define ASI_ZOPC (unsigned long)(0xebL << 40 | 0x6aL) 684 #define AGSI_ZOPC (unsigned long)(0xebL << 40 | 0x7aL) 685 686 // RR, Logical 687 #define ALR_ZOPC (unsigned int)(30 << 8) 688 #define ALGFR_ZOPC (unsigned int)(185 << 24 | 26 << 16) 689 #define ALGR_ZOPC (unsigned int)(185 << 24 | 10 << 16) 690 #define ALCGR_ZOPC (unsigned int)(185 << 24 | 136 << 16) 691 // RRF, Logical 692 #define ALRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00fa << 16) 693 #define ALGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00ea << 16) 694 // RI, Logical 695 #define ALFI_ZOPC (unsigned long)(0xc2L << 40 | 0x0bL << 32) 696 #define ALGFI_ZOPC (unsigned long)(0xc2L << 40 | 0x0aL << 32) 697 // RIE, Logical 698 #define ALHSIK_ZOPC (unsigned long)(0xecL << 40 | 0x00daL) 699 #define ALGHSIK_ZOPC (unsigned long)(0xecL << 40 | 0x00dbL) 700 // RM, Logical 701 #define AL_ZOPC (unsigned int)(0x5e << 24) 702 #define ALY_ZOPC (unsigned long)(227L << 40 | 94L) 703 #define ALGF_ZOPC (unsigned long)(227L << 40 | 26L) 704 #define ALG_ZOPC (unsigned long)(227L << 40 | 10L) 705 // In-memory arithmetic (add signed, add logical with signed immediate). 706 // MI, Logical 707 #define ALSI_ZOPC (unsigned long)(0xebL << 40 | 0x6eL) 708 #define ALGSI_ZOPC (unsigned long)(0xebL << 40 | 0x7eL) 709 710 // RR, BFP 711 #define AEBR_ZOPC (unsigned int)(179 << 24 | 10 << 16) 712 #define ADBR_ZOPC (unsigned int)(179 << 24 | 26 << 16) 713 #define AXBR_ZOPC (unsigned int)(179 << 24 | 74 << 16) 714 // RM, BFP 715 #define AEB_ZOPC (unsigned long)(237L << 40 | 10) 716 #define ADB_ZOPC (unsigned long)(237L << 40 | 26) 717 718 // Subtract 719 // RR, signed 720 #define SR_ZOPC (unsigned int)(27 << 8) 721 #define SGFR_ZOPC (unsigned int)(185 << 24 | 25 << 16) 722 #define SGR_ZOPC (unsigned int)(185 << 24 | 9 << 16) 723 // RRF, signed 724 #define SRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f9 << 16) 725 #define SGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e9 << 16) 726 // RM, signed 727 #define SH_ZOPC (unsigned int)(0x4b << 24) 728 #define SHY_ZOPC (unsigned long)(227L << 40 | 123L) 729 #define S_ZOPC (unsigned int)(0x5B << 24) 730 #define SY_ZOPC (unsigned long)(227L << 40 | 91L) 731 #define SGF_ZOPC (unsigned long)(227L << 40 | 25) 732 #define SG_ZOPC (unsigned long)(227L << 40 | 9) 733 // RR, Logical 734 #define SLR_ZOPC (unsigned int)(31 << 8) 735 #define SLGFR_ZOPC (unsigned int)(185 << 24 | 27 << 16) 736 #define SLGR_ZOPC (unsigned int)(185 << 24 | 11 << 16) 737 // RIL, Logical 738 #define SLFI_ZOPC (unsigned long)(0xc2L << 40 | 0x05L << 32) 739 #define SLGFI_ZOPC (unsigned long)(0xc2L << 40 | 0x04L << 32) 740 // RRF, Logical 741 #define SLRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00fb << 16) 742 #define SLGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00eb << 16) 743 // RM, Logical 744 #define SLY_ZOPC (unsigned long)(227L << 40 | 95L) 745 #define SLGF_ZOPC (unsigned long)(227L << 40 | 27L) 746 #define SLG_ZOPC (unsigned long)(227L << 40 | 11L) 747 748 // RR, BFP 749 #define SEBR_ZOPC (unsigned int)(179 << 24 | 11 << 16) 750 #define SDBR_ZOPC (unsigned int)(179 << 24 | 27 << 16) 751 #define SXBR_ZOPC (unsigned int)(179 << 24 | 75 << 16) 752 // RM, BFP 753 #define SEB_ZOPC (unsigned long)(237L << 40 | 11) 754 #define SDB_ZOPC (unsigned long)(237L << 40 | 27) 755 756 // Multiply 757 // RR, signed 758 #define MR_ZOPC (unsigned int)(28 << 8) 759 #define MSR_ZOPC (unsigned int)(178 << 24 | 82 << 16) 760 #define MSGFR_ZOPC (unsigned int)(185 << 24 | 28 << 16) 761 #define MSGR_ZOPC (unsigned int)(185 << 24 | 12 << 16) 762 // RI, signed 763 #define MHI_ZOPC (unsigned int)(167 << 24 | 12 << 16) 764 #define MGHI_ZOPC (unsigned int)(167 << 24 | 13 << 16) 765 #define MSFI_ZOPC (unsigned long)(0xc2L << 40 | 0x01L << 32) // z10 766 #define MSGFI_ZOPC (unsigned long)(0xc2L << 40 | 0x00L << 32) // z10 767 // RM, signed 768 #define M_ZOPC (unsigned int)(92 << 24) 769 #define MS_ZOPC (unsigned int)(0x71 << 24) 770 #define MHY_ZOPC (unsigned long)(0xe3L<< 40 | 0x7cL) 771 #define MSY_ZOPC (unsigned long)(227L << 40 | 81L) 772 #define MSGF_ZOPC (unsigned long)(227L << 40 | 28L) 773 #define MSG_ZOPC (unsigned long)(227L << 40 | 12L) 774 // RR, unsigned 775 #define MLR_ZOPC (unsigned int)(185 << 24 | 150 << 16) 776 #define MLGR_ZOPC (unsigned int)(185 << 24 | 134 << 16) 777 // RM, unsigned 778 #define ML_ZOPC (unsigned long)(227L << 40 | 150L) 779 #define MLG_ZOPC (unsigned long)(227L << 40 | 134L) 780 781 // RR, BFP 782 #define MEEBR_ZOPC (unsigned int)(179 << 24 | 23 << 16) 783 #define MDEBR_ZOPC (unsigned int)(179 << 24 | 12 << 16) 784 #define MDBR_ZOPC (unsigned int)(179 << 24 | 28 << 16) 785 #define MXDBR_ZOPC (unsigned int)(179 << 24 | 7 << 16) 786 #define MXBR_ZOPC (unsigned int)(179 << 24 | 76 << 16) 787 // RM, BFP 788 #define MEEB_ZOPC (unsigned long)(237L << 40 | 23) 789 #define MDEB_ZOPC (unsigned long)(237L << 40 | 12) 790 #define MDB_ZOPC (unsigned long)(237L << 40 | 28) 791 #define MXDB_ZOPC (unsigned long)(237L << 40 | 7) 792 793 // Divide 794 // RR, signed 795 #define DSGFR_ZOPC (unsigned int)(0xb91d << 16) 796 #define DSGR_ZOPC (unsigned int)(0xb90d << 16) 797 // RM, signed 798 #define D_ZOPC (unsigned int)(93 << 24) 799 #define DSGF_ZOPC (unsigned long)(227L << 40 | 29L) 800 #define DSG_ZOPC (unsigned long)(227L << 40 | 13L) 801 // RR, unsigned 802 #define DLR_ZOPC (unsigned int)(185 << 24 | 151 << 16) 803 #define DLGR_ZOPC (unsigned int)(185 << 24 | 135 << 16) 804 // RM, unsigned 805 #define DL_ZOPC (unsigned long)(227L << 40 | 151L) 806 #define DLG_ZOPC (unsigned long)(227L << 40 | 135L) 807 808 // RR, BFP 809 #define DEBR_ZOPC (unsigned int)(179 << 24 | 13 << 16) 810 #define DDBR_ZOPC (unsigned int)(179 << 24 | 29 << 16) 811 #define DXBR_ZOPC (unsigned int)(179 << 24 | 77 << 16) 812 // RM, BFP 813 #define DEB_ZOPC (unsigned long)(237L << 40 | 13) 814 #define DDB_ZOPC (unsigned long)(237L << 40 | 29) 815 816 // Square Root 817 // RR, BFP 818 #define SQEBR_ZOPC (unsigned int)(0xb314 << 16) 819 #define SQDBR_ZOPC (unsigned int)(0xb315 << 16) 820 #define SQXBR_ZOPC (unsigned int)(0xb316 << 16) 821 // RM, BFP 822 #define SQEB_ZOPC (unsigned long)(237L << 40 | 20) 823 #define SQDB_ZOPC (unsigned long)(237L << 40 | 21) 824 825 // Compare and Test 826 // RR, signed 827 #define CR_ZOPC (unsigned int)(25 << 8) 828 #define CGFR_ZOPC (unsigned int)(185 << 24 | 48 << 16) 829 #define CGR_ZOPC (unsigned int)(185 << 24 | 32 << 16) 830 // RI, signed 831 #define CHI_ZOPC (unsigned int)(167 << 24 | 14 << 16) 832 #define CFI_ZOPC (unsigned long)(0xc2L << 40 | 0xdL << 32) 833 #define CGHI_ZOPC (unsigned int)(167 << 24 | 15 << 16) 834 #define CGFI_ZOPC (unsigned long)(0xc2L << 40 | 0xcL << 32) 835 // RM, signed 836 #define CH_ZOPC (unsigned int)(0x49 << 24) 837 #define CHY_ZOPC (unsigned long)(227L << 40 | 121L) 838 #define C_ZOPC (unsigned int)(0x59 << 24) 839 #define CY_ZOPC (unsigned long)(227L << 40 | 89L) 840 #define CGF_ZOPC (unsigned long)(227L << 40 | 48L) 841 #define CG_ZOPC (unsigned long)(227L << 40 | 32L) 842 // RR, unsigned 843 #define CLR_ZOPC (unsigned int)(21 << 8) 844 #define CLGFR_ZOPC (unsigned int)(185 << 24 | 49 << 16) 845 #define CLGR_ZOPC (unsigned int)(185 << 24 | 33 << 16) 846 // RIL, unsigned 847 #define CLFI_ZOPC (unsigned long)(0xc2L << 40 | 0xfL << 32) 848 #define CLGFI_ZOPC (unsigned long)(0xc2L << 40 | 0xeL << 32) 849 // RM, unsigned 850 #define CL_ZOPC (unsigned int)(0x55 << 24) 851 #define CLY_ZOPC (unsigned long)(227L << 40 | 85L) 852 #define CLGF_ZOPC (unsigned long)(227L << 40 | 49L) 853 #define CLG_ZOPC (unsigned long)(227L << 40 | 33L) 854 // RI, unsigned 855 #define TMHH_ZOPC (unsigned int)(167 << 24 | 2 << 16) 856 #define TMHL_ZOPC (unsigned int)(167 << 24 | 3 << 16) 857 #define TMLH_ZOPC (unsigned int)(167 << 24) 858 #define TMLL_ZOPC (unsigned int)(167 << 24 | 1 << 16) 859 860 // RR, BFP 861 #define CEBR_ZOPC (unsigned int)(179 << 24 | 9 << 16) 862 #define CDBR_ZOPC (unsigned int)(179 << 24 | 25 << 16) 863 #define CXBR_ZOPC (unsigned int)(179 << 24 | 73 << 16) 864 // RM, BFP 865 #define CEB_ZOPC (unsigned long)(237L << 40 | 9) 866 #define CDB_ZOPC (unsigned long)(237L << 40 | 25) 867 868 // Shift 869 // arithmetic 870 #define SLA_ZOPC (unsigned int)(139 << 24) 871 #define SLAG_ZOPC (unsigned long)(235L << 40 | 11L) 872 #define SRA_ZOPC (unsigned int)(138 << 24) 873 #define SRAG_ZOPC (unsigned long)(235L << 40 | 10L) 874 // logical 875 #define SLL_ZOPC (unsigned int)(137 << 24) 876 #define SLLG_ZOPC (unsigned long)(235L << 40 | 13L) 877 #define SRL_ZOPC (unsigned int)(136 << 24) 878 #define SRLG_ZOPC (unsigned long)(235L << 40 | 12L) 879 880 // Rotate, then AND/XOR/OR/insert 881 // rotate 882 #define RLL_ZOPC (unsigned long)(0xebL << 40 | 0x1dL) // z10 883 #define RLLG_ZOPC (unsigned long)(0xebL << 40 | 0x1cL) // z10 884 // rotate and {AND|XOR|OR|INS} 885 #define RNSBG_ZOPC (unsigned long)(0xecL << 40 | 0x54L) // z196 886 #define RXSBG_ZOPC (unsigned long)(0xecL << 40 | 0x57L) // z196 887 #define ROSBG_ZOPC (unsigned long)(0xecL << 40 | 0x56L) // z196 888 #define RISBG_ZOPC (unsigned long)(0xecL << 40 | 0x55L) // z196 889 890 // AND 891 // RR, signed 892 #define NR_ZOPC (unsigned int)(20 << 8) 893 #define NGR_ZOPC (unsigned int)(185 << 24 | 128 << 16) 894 // RRF, signed 895 #define NRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f4 << 16) 896 #define NGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e4 << 16) 897 // RI, signed 898 #define NIHH_ZOPC (unsigned int)(165 << 24 | 4 << 16) 899 #define NIHL_ZOPC (unsigned int)(165 << 24 | 5 << 16) 900 #define NILH_ZOPC (unsigned int)(165 << 24 | 6 << 16) 901 #define NILL_ZOPC (unsigned int)(165 << 24 | 7 << 16) 902 #define NIHF_ZOPC (unsigned long)(0xc0L << 40 | 10L << 32) 903 #define NILF_ZOPC (unsigned long)(0xc0L << 40 | 11L << 32) 904 // RM, signed 905 #define N_ZOPC (unsigned int)(0x54 << 24) 906 #define NY_ZOPC (unsigned long)(227L << 40 | 84L) 907 #define NG_ZOPC (unsigned long)(227L << 40 | 128L) 908 909 // OR 910 // RR, signed 911 #define OR_ZOPC (unsigned int)(22 << 8) 912 #define OGR_ZOPC (unsigned int)(185 << 24 | 129 << 16) 913 // RRF, signed 914 #define ORK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f6 << 16) 915 #define OGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e6 << 16) 916 // RI, signed 917 #define OIHH_ZOPC (unsigned int)(165 << 24 | 8 << 16) 918 #define OIHL_ZOPC (unsigned int)(165 << 24 | 9 << 16) 919 #define OILH_ZOPC (unsigned int)(165 << 24 | 10 << 16) 920 #define OILL_ZOPC (unsigned int)(165 << 24 | 11 << 16) 921 #define OIHF_ZOPC (unsigned long)(0xc0L << 40 | 12L << 32) 922 #define OILF_ZOPC (unsigned long)(0xc0L << 40 | 13L << 32) 923 // RM, signed 924 #define O_ZOPC (unsigned int)(0x56 << 24) 925 #define OY_ZOPC (unsigned long)(227L << 40 | 86L) 926 #define OG_ZOPC (unsigned long)(227L << 40 | 129L) 927 928 // XOR 929 // RR, signed 930 #define XR_ZOPC (unsigned int)(23 << 8) 931 #define XGR_ZOPC (unsigned int)(185 << 24 | 130 << 16) 932 // RRF, signed 933 #define XRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f7 << 16) 934 #define XGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e7 << 16) 935 // RI, signed 936 #define XIHF_ZOPC (unsigned long)(0xc0L << 40 | 6L << 32) 937 #define XILF_ZOPC (unsigned long)(0xc0L << 40 | 7L << 32) 938 // RM, signed 939 #define X_ZOPC (unsigned int)(0x57 << 24) 940 #define XY_ZOPC (unsigned long)(227L << 40 | 87L) 941 #define XG_ZOPC (unsigned long)(227L << 40 | 130L) 942 943 944 // Data Conversion 945 946 // INT to BFP 947 #define CEFBR_ZOPC (unsigned int)(179 << 24 | 148 << 16) 948 #define CDFBR_ZOPC (unsigned int)(179 << 24 | 149 << 16) 949 #define CXFBR_ZOPC (unsigned int)(179 << 24 | 150 << 16) 950 #define CEGBR_ZOPC (unsigned int)(179 << 24 | 164 << 16) 951 #define CDGBR_ZOPC (unsigned int)(179 << 24 | 165 << 16) 952 #define CXGBR_ZOPC (unsigned int)(179 << 24 | 166 << 16) 953 // BFP to INT 954 #define CFEBR_ZOPC (unsigned int)(179 << 24 | 152 << 16) 955 #define CFDBR_ZOPC (unsigned int)(179 << 24 | 153 << 16) 956 #define CFXBR_ZOPC (unsigned int)(179 << 24 | 154 << 16) 957 #define CGEBR_ZOPC (unsigned int)(179 << 24 | 168 << 16) 958 #define CGDBR_ZOPC (unsigned int)(179 << 24 | 169 << 16) 959 #define CGXBR_ZOPC (unsigned int)(179 << 24 | 170 << 16) 960 // INT to DEC 961 #define CVD_ZOPC (unsigned int)(0x4e << 24) 962 #define CVDY_ZOPC (unsigned long)(0xe3L << 40 | 0x26L) 963 #define CVDG_ZOPC (unsigned long)(0xe3L << 40 | 0x2eL) 964 965 966 // BFP Control 967 968 #define SRNM_ZOPC (unsigned int)(178 << 24 | 153 << 16) 969 #define EFPC_ZOPC (unsigned int)(179 << 24 | 140 << 16) 970 #define SFPC_ZOPC (unsigned int)(179 << 24 | 132 << 16) 971 #define STFPC_ZOPC (unsigned int)(178 << 24 | 156 << 16) 972 #define LFPC_ZOPC (unsigned int)(178 << 24 | 157 << 16) 973 974 975 // Branch Instructions 976 977 // Register 978 #define BCR_ZOPC (unsigned int)(7 << 8) 979 #define BALR_ZOPC (unsigned int)(5 << 8) 980 #define BASR_ZOPC (unsigned int)(13 << 8) 981 #define BCTGR_ZOPC (unsigned long)(0xb946 << 16) 982 // Absolute 983 #define BC_ZOPC (unsigned int)(71 << 24) 984 #define BAL_ZOPC (unsigned int)(69 << 24) 985 #define BAS_ZOPC (unsigned int)(77 << 24) 986 #define BXH_ZOPC (unsigned int)(134 << 24) 987 #define BXHG_ZOPC (unsigned long)(235L << 40 | 68) 988 // Relative 989 #define BRC_ZOPC (unsigned int)(167 << 24 | 4 << 16) 990 #define BRCL_ZOPC (unsigned long)(192L << 40 | 4L << 32) 991 #define BRAS_ZOPC (unsigned int)(167 << 24 | 5 << 16) 992 #define BRASL_ZOPC (unsigned long)(192L << 40 | 5L << 32) 993 #define BRCT_ZOPC (unsigned int)(167 << 24 | 6 << 16) 994 #define BRCTG_ZOPC (unsigned int)(167 << 24 | 7 << 16) 995 #define BRXH_ZOPC (unsigned int)(132 << 24) 996 #define BRXHG_ZOPC (unsigned long)(236L << 40 | 68) 997 #define BRXLE_ZOPC (unsigned int)(133 << 24) 998 #define BRXLG_ZOPC (unsigned long)(236L << 40 | 69) 999 1000 1001 // Compare and Branch Instructions 1002 1003 // signed comp reg/reg, branch Absolute 1004 #define CRB_ZOPC (unsigned long)(0xecL << 40 | 0xf6L) // z10 1005 #define CGRB_ZOPC (unsigned long)(0xecL << 40 | 0xe4L) // z10 1006 // signed comp reg/reg, branch Relative 1007 #define CRJ_ZOPC (unsigned long)(0xecL << 40 | 0x76L) // z10 1008 #define CGRJ_ZOPC (unsigned long)(0xecL << 40 | 0x64L) // z10 1009 // signed comp reg/imm, branch absolute 1010 #define CIB_ZOPC (unsigned long)(0xecL << 40 | 0xfeL) // z10 1011 #define CGIB_ZOPC (unsigned long)(0xecL << 40 | 0xfcL) // z10 1012 // signed comp reg/imm, branch relative 1013 #define CIJ_ZOPC (unsigned long)(0xecL << 40 | 0x7eL) // z10 1014 #define CGIJ_ZOPC (unsigned long)(0xecL << 40 | 0x7cL) // z10 1015 1016 // unsigned comp reg/reg, branch Absolute 1017 #define CLRB_ZOPC (unsigned long)(0xecL << 40 | 0xf7L) // z10 1018 #define CLGRB_ZOPC (unsigned long)(0xecL << 40 | 0xe5L) // z10 1019 // unsigned comp reg/reg, branch Relative 1020 #define CLRJ_ZOPC (unsigned long)(0xecL << 40 | 0x77L) // z10 1021 #define CLGRJ_ZOPC (unsigned long)(0xecL << 40 | 0x65L) // z10 1022 // unsigned comp reg/imm, branch absolute 1023 #define CLIB_ZOPC (unsigned long)(0xecL << 40 | 0xffL) // z10 1024 #define CLGIB_ZOPC (unsigned long)(0xecL << 40 | 0xfdL) // z10 1025 // unsigned comp reg/imm, branch relative 1026 #define CLIJ_ZOPC (unsigned long)(0xecL << 40 | 0x7fL) // z10 1027 #define CLGIJ_ZOPC (unsigned long)(0xecL << 40 | 0x7dL) // z10 1028 1029 // comp reg/reg, trap 1030 #define CRT_ZOPC (unsigned int)(0xb972 << 16) // z10 1031 #define CGRT_ZOPC (unsigned int)(0xb960 << 16) // z10 1032 #define CLRT_ZOPC (unsigned int)(0xb973 << 16) // z10 1033 #define CLGRT_ZOPC (unsigned int)(0xb961 << 16) // z10 1034 // comp reg/imm, trap 1035 #define CIT_ZOPC (unsigned long)(0xecL << 40 | 0x72L) // z10 1036 #define CGIT_ZOPC (unsigned long)(0xecL << 40 | 0x70L) // z10 1037 #define CLFIT_ZOPC (unsigned long)(0xecL << 40 | 0x73L) // z10 1038 #define CLGIT_ZOPC (unsigned long)(0xecL << 40 | 0x71L) // z10 1039 1040 1041 // Direct Memory Operations 1042 1043 // Compare 1044 #define CLI_ZOPC (unsigned int)(0x95 << 24) 1045 #define CLIY_ZOPC (unsigned long)(0xebL << 40 | 0x55L) 1046 #define CLC_ZOPC (unsigned long)(0xd5L << 40) 1047 #define CLCL_ZOPC (unsigned int)(0x0f << 8) 1048 #define CLCLE_ZOPC (unsigned int)(0xa9 << 24) 1049 #define CLCLU_ZOPC (unsigned long)(0xebL << 40 | 0x8fL) 1050 1051 // Move 1052 #define MVI_ZOPC (unsigned int)(0x92 << 24) 1053 #define MVIY_ZOPC (unsigned long)(0xebL << 40 | 0x52L) 1054 #define MVC_ZOPC (unsigned long)(0xd2L << 40) 1055 #define MVCL_ZOPC (unsigned int)(0x0e << 8) 1056 #define MVCLE_ZOPC (unsigned int)(0xa8 << 24) 1057 1058 // Test 1059 #define TM_ZOPC (unsigned int)(0x91 << 24) 1060 #define TMY_ZOPC (unsigned long)(0xebL << 40 | 0x51L) 1061 1062 // AND 1063 #define NI_ZOPC (unsigned int)(0x94 << 24) 1064 #define NIY_ZOPC (unsigned long)(0xebL << 40 | 0x54L) 1065 #define NC_ZOPC (unsigned long)(0xd4L << 40) 1066 1067 // OR 1068 #define OI_ZOPC (unsigned int)(0x96 << 24) 1069 #define OIY_ZOPC (unsigned long)(0xebL << 40 | 0x56L) 1070 #define OC_ZOPC (unsigned long)(0xd6L << 40) 1071 1072 // XOR 1073 #define XI_ZOPC (unsigned int)(0x97 << 24) 1074 #define XIY_ZOPC (unsigned long)(0xebL << 40 | 0x57L) 1075 #define XC_ZOPC (unsigned long)(0xd7L << 40) 1076 1077 // Search String 1078 #define SRST_ZOPC (unsigned int)(178 << 24 | 94 << 16) 1079 #define SRSTU_ZOPC (unsigned int)(185 << 24 | 190 << 16) 1080 1081 // Translate characters 1082 #define TROO_ZOPC (unsigned int)(0xb9 << 24 | 0x93 << 16) 1083 #define TROT_ZOPC (unsigned int)(0xb9 << 24 | 0x92 << 16) 1084 #define TRTO_ZOPC (unsigned int)(0xb9 << 24 | 0x91 << 16) 1085 #define TRTT_ZOPC (unsigned int)(0xb9 << 24 | 0x90 << 16) 1086 1087 1088 // Miscellaneous Operations 1089 1090 // Execute 1091 #define EX_ZOPC (unsigned int)(68L << 24) 1092 #define EXRL_ZOPC (unsigned long)(0xc6L << 40 | 0x00L << 32) // z10 1093 1094 // Compare and Swap 1095 #define CS_ZOPC (unsigned int)(0xba << 24) 1096 #define CSY_ZOPC (unsigned long)(0xebL << 40 | 0x14L) 1097 #define CSG_ZOPC (unsigned long)(0xebL << 40 | 0x30L) 1098 1099 // Interlocked-Update 1100 #define LAA_ZOPC (unsigned long)(0xebL << 40 | 0xf8L) // z196 1101 #define LAAG_ZOPC (unsigned long)(0xebL << 40 | 0xe8L) // z196 1102 #define LAAL_ZOPC (unsigned long)(0xebL << 40 | 0xfaL) // z196 1103 #define LAALG_ZOPC (unsigned long)(0xebL << 40 | 0xeaL) // z196 1104 #define LAN_ZOPC (unsigned long)(0xebL << 40 | 0xf4L) // z196 1105 #define LANG_ZOPC (unsigned long)(0xebL << 40 | 0xe4L) // z196 1106 #define LAX_ZOPC (unsigned long)(0xebL << 40 | 0xf7L) // z196 1107 #define LAXG_ZOPC (unsigned long)(0xebL << 40 | 0xe7L) // z196 1108 #define LAO_ZOPC (unsigned long)(0xebL << 40 | 0xf6L) // z196 1109 #define LAOG_ZOPC (unsigned long)(0xebL << 40 | 0xe6L) // z196 1110 1111 // System Functions 1112 #define STCK_ZOPC (unsigned int)(0xb2 << 24 | 0x05 << 16) 1113 #define STCKF_ZOPC (unsigned int)(0xb2 << 24 | 0x7c << 16) 1114 #define STFLE_ZOPC (unsigned int)(0xb2 << 24 | 0xb0 << 16) 1115 #define ECTG_ZOPC (unsigned long)(0xc8L <<40 | 0x01L << 32) // z10 1116 #define ECAG_ZOPC (unsigned long)(0xebL <<40 | 0x4cL) // z10 1117 1118 // Execution Prediction 1119 #define PFD_ZOPC (unsigned long)(0xe3L <<40 | 0x36L) // z10 1120 #define PFDRL_ZOPC (unsigned long)(0xc6L <<40 | 0x02L << 32) // z10 1121 #define BPP_ZOPC (unsigned long)(0xc7L <<40) // branch prediction preload -- EC12 1122 #define BPRP_ZOPC (unsigned long)(0xc5L <<40) // branch prediction preload -- EC12 1123 1124 // Transaction Control 1125 #define TBEGIN_ZOPC (unsigned long)(0xe560L << 32) // tx begin -- EC12 1126 #define TBEGINC_ZOPC (unsigned long)(0xe561L << 32) // tx begin (constrained) -- EC12 1127 #define TEND_ZOPC (unsigned int)(0xb2f8 << 16) // tx end -- EC12 1128 #define TABORT_ZOPC (unsigned int)(0xb2fc << 16) // tx abort -- EC12 1129 #define ETND_ZOPC (unsigned int)(0xb2ec << 16) // tx nesting depth -- EC12 1130 #define PPA_ZOPC (unsigned int)(0xb2e8 << 16) // tx processor assist -- EC12 1131 1132 // Crypto and Checksum 1133 #define CKSM_ZOPC (unsigned int)(0xb2 << 24 | 0x41 << 16) // checksum. This is NOT CRC32 1134 #define KM_ZOPC (unsigned int)(0xb9 << 24 | 0x2e << 16) // cipher 1135 #define KMC_ZOPC (unsigned int)(0xb9 << 24 | 0x2f << 16) // cipher 1136 #define KIMD_ZOPC (unsigned int)(0xb9 << 24 | 0x3e << 16) // SHA (msg digest) 1137 #define KLMD_ZOPC (unsigned int)(0xb9 << 24 | 0x3f << 16) // SHA (msg digest) 1138 #define KMAC_ZOPC (unsigned int)(0xb9 << 24 | 0x1e << 16) // Message Authentication Code 1139 1140 // Various 1141 #define TCEB_ZOPC (unsigned long)(237L << 40 | 16) 1142 #define TCDB_ZOPC (unsigned long)(237L << 40 | 17) 1143 #define TAM_ZOPC (unsigned long)(267) 1144 1145 #define FLOGR_ZOPC (unsigned int)(0xb9 << 24 | 0x83 << 16) 1146 #define POPCNT_ZOPC (unsigned int)(0xb9e1 << 16) 1147 #define AHHHR_ZOPC (unsigned int)(0xb9c8 << 16) 1148 #define AHHLR_ZOPC (unsigned int)(0xb9d8 << 16) 1149 1150 1151 // OpCode field masks 1152 1153 #define RI_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1154 #define RRE_MASK (unsigned int)(0xff << 24 | 0xff << 16) 1155 #define RSI_MASK (unsigned int)(0xff << 24) 1156 #define RIE_MASK (unsigned long)(0xffL << 40 | 0xffL) 1157 #define RIL_MASK (unsigned long)(0xffL << 40 | 0x0fL << 32) 1158 1159 #define BASR_MASK (unsigned int)(0xff << 8) 1160 #define BCR_MASK (unsigned int)(0xff << 8) 1161 #define BRC_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1162 #define LGHI_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1163 #define LLI_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1164 #define II_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1165 #define LLIF_MASK (unsigned long)(0xffL << 40 | 0x0fL << 32) 1166 #define IIF_MASK (unsigned long)(0xffL << 40 | 0x0fL << 32) 1167 #define BRASL_MASK (unsigned long)(0xffL << 40 | 0x0fL << 32) 1168 #define TM_MASK (unsigned int)(0xff << 24) 1169 #define TMY_MASK (unsigned long)(0xffL << 40 | 0xffL) 1170 #define LB_MASK (unsigned long)(0xffL << 40 | 0xffL) 1171 #define LH_MASK (unsigned int)(0xff << 24) 1172 #define L_MASK (unsigned int)(0xff << 24) 1173 #define LY_MASK (unsigned long)(0xffL << 40 | 0xffL) 1174 #define LG_MASK (unsigned long)(0xffL << 40 | 0xffL) 1175 #define LLGH_MASK (unsigned long)(0xffL << 40 | 0xffL) 1176 #define LLGF_MASK (unsigned long)(0xffL << 40 | 0xffL) 1177 #define SLAG_MASK (unsigned long)(0xffL << 40 | 0xffL) 1178 #define LARL_MASK (unsigned long)(0xff0fL << 32) 1179 #define LGRL_MASK (unsigned long)(0xff0fL << 32) 1180 #define LE_MASK (unsigned int)(0xff << 24) 1181 #define LD_MASK (unsigned int)(0xff << 24) 1182 #define ST_MASK (unsigned int)(0xff << 24) 1183 #define STC_MASK (unsigned int)(0xff << 24) 1184 #define STG_MASK (unsigned long)(0xffL << 40 | 0xffL) 1185 #define STH_MASK (unsigned int)(0xff << 24) 1186 #define STE_MASK (unsigned int)(0xff << 24) 1187 #define STD_MASK (unsigned int)(0xff << 24) 1188 #define CMPBRANCH_MASK (unsigned long)(0xffL << 40 | 0xffL) 1189 #define REL_LONG_MASK (unsigned long)(0xff0fL << 32) 1190 1191 public: 1192 // Condition code masks. Details: 1193 // - Mask bit#3 must be zero for all compare and branch/trap instructions to ensure 1194 // future compatibility. 1195 // - For all arithmetic instructions which set the condition code, mask bit#3 1196 // indicates overflow ("unordered" in float operations). 1197 // - "unordered" float comparison results have to be treated as low. 1198 // - When overflow/unordered is detected, none of the branch conditions is true, 1199 // except for bcondOverflow/bcondNotOrdered and bcondAlways. 1200 // - For INT comparisons, the inverse condition can be calculated as (14-cond). 1201 // - For FLOAT comparisons, the inverse condition can be calculated as (15-cond). 1202 enum branch_condition { 1203 bcondNever = 0, 1204 bcondAlways = 15, 1205 1206 // Specific names. Make use of lightweight sync. 1207 // Full and lightweight sync operation. 1208 bcondFullSync = 15, 1209 bcondLightSync = 14, 1210 bcondNop = 0, 1211 1212 // arithmetic compare instructions 1213 // arithmetic load and test, insert instructions 1214 // Mask bit#3 must be zero for future compatibility. 1215 bcondEqual = 8, 1216 bcondNotEqual = 6, 1217 bcondLow = 4, 1218 bcondNotLow = 10, 1219 bcondHigh = 2, 1220 bcondNotHigh = 12, 1221 // arithmetic calculation instructions 1222 // Mask bit#3 indicates overflow if detected by instr. 1223 // Mask bit#3 = 0 (overflow is not handled by compiler). 1224 bcondOverflow = 1, 1225 bcondNotOverflow = 14, 1226 bcondZero = bcondEqual, 1227 bcondNotZero = bcondNotEqual, 1228 bcondNegative = bcondLow, 1229 bcondNotNegative = bcondNotLow, 1230 bcondPositive = bcondHigh, 1231 bcondNotPositive = bcondNotHigh, 1232 bcondNotOrdered = 1, // float comparisons 1233 bcondOrdered = 14, // float comparisons 1234 bcondLowOrNotOrdered = bcondLow|bcondNotOrdered, // float comparisons 1235 bcondHighOrNotOrdered = bcondHigh|bcondNotOrdered, // float comparisons 1236 // unsigned arithmetic calculation instructions 1237 // Mask bit#0 is not used by these instructions. 1238 // There is no indication of overflow for these instr. 1239 bcondLogZero = 2, 1240 bcondLogNotZero = 5, 1241 bcondLogNotZero_Borrow = 4, 1242 bcondLogNotZero_NoBorrow = 1, 1243 // string search instructions 1244 bcondFound = 4, 1245 bcondNotFound = 2, 1246 bcondInterrupted = 1, 1247 // bit test instructions 1248 bcondAllZero = 8, 1249 bcondMixed = 6, 1250 bcondAllOne = 1, 1251 bcondNotAllZero = 7 // for tmll 1252 }; 1253 1254 enum Condition { 1255 // z/Architecture 1256 negative = 0, 1257 less = 0, 1258 positive = 1, 1259 greater = 1, 1260 zero = 2, 1261 equal = 2, 1262 summary_overflow = 3, 1263 }; 1264 1265 // Rounding mode for float-2-int conversions. 1266 enum RoundingMode { 1267 current_mode = 0, // Mode taken from FPC register. 1268 biased_to_nearest = 1, 1269 to_nearest = 4, 1270 to_zero = 5, 1271 to_plus_infinity = 6, 1272 to_minus_infinity = 7 1273 }; 1274 1275 // Inverse condition code, i.e. determine "15 - cc" for a given condition code cc. 1276 static branch_condition inverse_condition(branch_condition cc); 1277 static branch_condition inverse_float_condition(branch_condition cc); 1278 1279 1280 //----------------------------------------------- 1281 // instruction property getter methods 1282 //----------------------------------------------- 1283 1284 // Calculate length of instruction. 1285 static int instr_len(unsigned char *instr); 1286 1287 // Longest instructions are 6 bytes on z/Architecture. 1288 static int instr_maxlen() { return 6; } 1289 1290 // Average instruction is 4 bytes on z/Architecture (just a guess). 1291 static int instr_avglen() { return 4; } 1292 1293 // Shortest instructions are 2 bytes on z/Architecture. 1294 static int instr_minlen() { return 2; } 1295 1296 // Move instruction at pc right-justified into passed long int. 1297 // Return instr len in bytes as function result. 1298 static unsigned int get_instruction(unsigned char *pc, unsigned long *instr); 1299 1300 // Move instruction in passed (long int) into storage at pc. 1301 // This code is _NOT_ MT-safe!! 1302 static void set_instruction(unsigned char *pc, unsigned long instr, unsigned int len) { 1303 memcpy(pc, ((unsigned char *)&instr)+sizeof(unsigned long)-len, len); 1304 } 1305 1306 1307 //------------------------------------------ 1308 // instruction field test methods 1309 //------------------------------------------ 1310 1311 // Only used once in s390.ad to implement Matcher::is_short_branch_offset(). 1312 static bool is_within_range_of_RelAddr16(address target, address origin) { 1313 return RelAddr::is_in_range_of_RelAddr16(target, origin); 1314 } 1315 1316 1317 //---------------------------------- 1318 // some diagnostic output 1319 //---------------------------------- 1320 1321 static void print_dbg_msg(outputStream* out, unsigned long inst, const char* msg, int ilen) PRODUCT_RETURN; 1322 static void dump_code_range(outputStream* out, address pc, const unsigned int range, const char* msg = " ") PRODUCT_RETURN; 1323 1324 protected: 1325 1326 //------------------------------------------------------- 1327 // instruction field helper methods (internal) 1328 //------------------------------------------------------- 1329 1330 // Return a mask of 1s between hi_bit and lo_bit (inclusive). 1331 static long fmask(unsigned int hi_bit, unsigned int lo_bit) { 1332 assert(hi_bit >= lo_bit && hi_bit < 48, "bad bits"); 1333 return ((1L<<(hi_bit-lo_bit+1)) - 1) << lo_bit; 1334 } 1335 1336 // extract u_field 1337 // unsigned value 1338 static long inv_u_field(long x, int hi_bit, int lo_bit) { 1339 return (x & fmask(hi_bit, lo_bit)) >> lo_bit; 1340 } 1341 1342 // extract s_field 1343 // Signed value, may need sign extension. 1344 static long inv_s_field(long x, int hi_bit, int lo_bit) { 1345 x = inv_u_field(x, hi_bit, lo_bit); 1346 // Highest extracted bit set -> sign extension. 1347 return (x >= (1L<<(hi_bit-lo_bit)) ? x | ((-1L)<<(hi_bit-lo_bit)) : x); 1348 } 1349 1350 // Extract primary opcode from instruction. 1351 static int z_inv_op(int x) { return inv_u_field(x, 31, 24); } 1352 static int z_inv_op(long x) { return inv_u_field(x, 47, 40); } 1353 1354 static int inv_reg( long x, int s, int len) { return inv_u_field(x, (len-s)-1, (len-s)-4); } // Regs are encoded in 4 bits. 1355 static int inv_mask(long x, int s, int len) { return inv_u_field(x, (len-s)-1, (len-s)-8); } // Mask is 8 bits long. 1356 static int inv_simm16_48(long x) { return (inv_s_field(x, 31, 16)); } // 6-byte instructions only 1357 static int inv_simm16(long x) { return (inv_s_field(x, 15, 0)); } // 4-byte instructions only 1358 static int inv_simm20(long x) { return (inv_u_field(x, 27, 16) | // 6-byte instructions only 1359 inv_s_field(x, 15, 8)<<12); } 1360 static int inv_simm32(long x) { return (inv_s_field(x, 31, 0)); } // 6-byte instructions only 1361 static int inv_uimm12(long x) { return (inv_u_field(x, 11, 0)); } // 4-byte instructions only 1362 1363 // Encode u_field from long value. 1364 static long u_field(long x, int hi_bit, int lo_bit) { 1365 long r = x << lo_bit; 1366 assert((r & ~fmask(hi_bit, lo_bit)) == 0, "value out of range"); 1367 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); 1368 return r; 1369 } 1370 1371 public: 1372 1373 //-------------------------------------------------- 1374 // instruction field construction methods 1375 //-------------------------------------------------- 1376 1377 // Compute relative address (32 bit) for branch. 1378 // Only used once in nativeInst_s390.cpp. 1379 static intptr_t z_pcrel_off(address dest, address pc) { 1380 return RelAddr::pcrel_off32(dest, pc); 1381 } 1382 1383 // Extract 20-bit signed displacement. 1384 // Only used in disassembler_s390.cpp for temp enhancements. 1385 static int inv_simm20_xx(address iLoc) { 1386 unsigned long instr = 0; 1387 unsigned long iLen = get_instruction(iLoc, &instr); 1388 return inv_simm20(instr); 1389 } 1390 1391 // unsigned immediate, in low bits, nbits long 1392 static long uimm(long x, int nbits) { 1393 assert(Immediate::is_uimm(x, nbits), "unsigned constant out of range"); 1394 return x & fmask(nbits - 1, 0); 1395 } 1396 1397 // Cast '1' to long to avoid sign extension if nbits = 32. 1398 // signed immediate, in low bits, nbits long 1399 static long simm(long x, int nbits) { 1400 assert(Immediate::is_simm(x, nbits), "value out of range"); 1401 return x & fmask(nbits - 1, 0); 1402 } 1403 1404 static long imm(int64_t x, int nbits) { 1405 // Assert that x can be represented with nbits bits ignoring the sign bits, 1406 // i.e. the more higher bits should all be 0 or 1. 1407 assert((x >> nbits) == 0 || (x >> nbits) == -1, "value out of range"); 1408 return x & fmask(nbits-1, 0); 1409 } 1410 1411 // A 20-bit displacement is only in instructions of the 1412 // RSY, RXY, or SIY format. In these instructions, the D 1413 // field consists of a DL (low) field in bit positions 20-31 1414 // and of a DH (high) field in bit positions 32-39. The 1415 // value of the displacement is formed by appending the 1416 // contents of the DH field to the left of the contents of 1417 // the DL field. 1418 static long simm20(int64_t ui20) { 1419 assert(Immediate::is_simm(ui20, 20), "value out of range"); 1420 return ( ((ui20 & 0xfffL) << (48-32)) | // DL 1421 (((ui20 >> 12) & 0xffL) << (48-40))); // DH 1422 } 1423 1424 static long reg(Register r, int s, int len) { return u_field(r->encoding(), (len-s)-1, (len-s)-4); } 1425 static long reg(int r, int s, int len) { return u_field(r, (len-s)-1, (len-s)-4); } 1426 static long regt(Register r, int s, int len) { return reg(r, s, len); } 1427 static long regz(Register r, int s, int len) { assert(r != Z_R0, "cannot use register R0 in memory access"); return reg(r, s, len); } 1428 1429 static long uimm4( int64_t ui4, int s, int len) { return uimm(ui4, 4) << (len-s-4); } 1430 static long uimm6( int64_t ui6, int s, int len) { return uimm(ui6, 6) << (len-s-6); } 1431 static long uimm8( int64_t ui8, int s, int len) { return uimm(ui8, 8) << (len-s-8); } 1432 static long uimm12(int64_t ui12, int s, int len) { return uimm(ui12, 12) << (len-s-12); } 1433 static long uimm16(int64_t ui16, int s, int len) { return uimm(ui16, 16) << (len-s-16); } 1434 static long uimm32(int64_t ui32, int s, int len) { return uimm((unsigned)ui32, 32) << (len-s-32); } // prevent sign extension 1435 1436 static long simm8( int64_t si8, int s, int len) { return simm(si8, 8) << (len-s-8); } 1437 static long simm12(int64_t si12, int s, int len) { return simm(si12, 12) << (len-s-12); } 1438 static long simm16(int64_t si16, int s, int len) { return simm(si16, 16) << (len-s-16); } 1439 static long simm24(int64_t si24, int s, int len) { return simm(si24, 24) << (len-s-24); } 1440 static long simm32(int64_t si32, int s, int len) { return simm(si32, 32) << (len-s-32); } 1441 1442 static long imm8( int64_t i8, int s, int len) { return imm(i8, 8) << (len-s-8); } 1443 static long imm12(int64_t i12, int s, int len) { return imm(i12, 12) << (len-s-12); } 1444 static long imm16(int64_t i16, int s, int len) { return imm(i16, 16) << (len-s-16); } 1445 static long imm24(int64_t i24, int s, int len) { return imm(i24, 24) << (len-s-24); } 1446 static long imm32(int64_t i32, int s, int len) { return imm(i32, 32) << (len-s-32); } 1447 1448 static long fregt(FloatRegister r, int s, int len) { return freg(r,s,len); } 1449 static long freg( FloatRegister r, int s, int len) { return u_field(r->encoding(), (len-s)-1, (len-s)-4); } 1450 1451 // Rounding mode for float-2-int conversions. 1452 static long rounding_mode(RoundingMode m, int s, int len) { 1453 assert(m != 2 && m != 3, "invalid mode"); 1454 return uimm(m, 4) << (len-s-4); 1455 } 1456 1457 //-------------------------------------------- 1458 // instruction field getter methods 1459 //-------------------------------------------- 1460 1461 static int get_imm32(address a, int instruction_number) { 1462 int imm; 1463 int *p =((int *)(a + 2 + 6 * instruction_number)); 1464 imm = *p; 1465 return imm; 1466 } 1467 1468 static short get_imm16(address a, int instruction_number) { 1469 short imm; 1470 short *p =((short *)a) + 2 * instruction_number + 1; 1471 imm = *p; 1472 return imm; 1473 } 1474 1475 1476 //-------------------------------------------- 1477 // instruction field setter methods 1478 //-------------------------------------------- 1479 1480 static void set_imm32(address a, int64_t s) { 1481 assert(Immediate::is_simm32(s) || Immediate::is_uimm32(s), "to big"); 1482 int* p = (int *) (a + 2); 1483 *p = s; 1484 } 1485 1486 static void set_imm16(int* instr, int64_t s) { 1487 assert(Immediate::is_simm16(s) || Immediate::is_uimm16(s), "to big"); 1488 short* p = ((short *)instr) + 1; 1489 *p = s; 1490 } 1491 1492 public: 1493 1494 static unsigned int align(unsigned int x, unsigned int a) { return ((x + (a - 1)) & ~(a - 1)); } 1495 static bool is_aligned(unsigned int x, unsigned int a) { return (0 == x % a); } 1496 1497 inline void emit_16(int x); 1498 inline void emit_32(int x); 1499 inline void emit_48(long x); 1500 1501 // Compare and control flow instructions 1502 // ===================================== 1503 1504 // See also commodity routines compare64_and_branch(), compare32_and_branch(). 1505 1506 // compare instructions 1507 // compare register 1508 inline void z_cr( Register r1, Register r2); // compare (r1, r2) ; int32 1509 inline void z_cgr( Register r1, Register r2); // compare (r1, r2) ; int64 1510 inline void z_cgfr(Register r1, Register r2); // compare (r1, r2) ; int64 <--> int32 1511 // compare immediate 1512 inline void z_chi( Register r1, int64_t i2); // compare (r1, i2_imm16) ; int32 1513 inline void z_cfi( Register r1, int64_t i2); // compare (r1, i2_imm32) ; int32 1514 inline void z_cghi(Register r1, int64_t i2); // compare (r1, i2_imm16) ; int64 1515 inline void z_cgfi(Register r1, int64_t i2); // compare (r1, i2_imm32) ; int64 1516 // compare memory 1517 inline void z_ch( Register r1, const Address &a); // compare (r1, *(a)) ; int32 <--> int16 1518 inline void z_ch( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_uimm12+x2+b2)) ; int32 <--> int16 1519 inline void z_c( Register r1, const Address &a); // compare (r1, *(a)) ; int32 1520 inline void z_c( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_uimm12+x2+b2)) ; int32 1521 inline void z_cy( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_uimm20+x2+b2)) ; int32 1522 inline void z_cy( Register r1, int64_t d2, Register b2); // compare (r1, *(d2_uimm20+x2+b2)) ; int32 1523 inline void z_cy( Register r1, const Address& a); // compare (r1, *(a)) ; int32 1524 //inline void z_cgf(Register r1,const Address &a); // compare (r1, *(a)) ; int64 <--> int32 1525 //inline void z_cgf(Register r1,int64_t d2, Register x2, Register b2);// compare (r1, *(d2_uimm12+x2+b2)) ; int64 <--> int32 1526 inline void z_cg( Register r1, const Address &a); // compare (r1, *(a)) ; int64 1527 inline void z_cg( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm20+x2+b2)) ; int64 1528 1529 // compare logical instructions 1530 // compare register 1531 inline void z_clr( Register r1, Register r2); // compare (r1, r2) ; uint32 1532 inline void z_clgr( Register r1, Register r2); // compare (r1, r2) ; uint64 1533 // compare immediate 1534 inline void z_clfi( Register r1, int64_t i2); // compare (r1, i2_uimm32) ; uint32 1535 inline void z_clgfi(Register r1, int64_t i2); // compare (r1, i2_uimm32) ; uint64 1536 inline void z_cl( Register r1, const Address &a); // compare (r1, *(a) ; uint32 1537 inline void z_cl( Register r1, int64_t d2, Register x2, Register b2);// compare (r1, *(d2_uimm12+x2+b2) ; uint32 1538 inline void z_cly( Register r1, int64_t d2, Register x2, Register b2);// compare (r1, *(d2_uimm20+x2+b2)) ; uint32 1539 inline void z_cly( Register r1, int64_t d2, Register b2); // compare (r1, *(d2_uimm20+x2+b2)) ; uint32 1540 inline void z_cly( Register r1, const Address& a); // compare (r1, *(a)) ; uint32 1541 inline void z_clg( Register r1, const Address &a); // compare (r1, *(a) ; uint64 1542 inline void z_clg( Register r1, int64_t d2, Register x2, Register b2);// compare (r1, *(d2_imm20+x2+b2) ; uint64 1543 1544 // test under mask 1545 inline void z_tmll(Register r1, int64_t i2); // test under mask, see docu 1546 inline void z_tmlh(Register r1, int64_t i2); // test under mask, see docu 1547 inline void z_tmhl(Register r1, int64_t i2); // test under mask, see docu 1548 inline void z_tmhh(Register r1, int64_t i2); // test under mask, see docu 1549 1550 // branch instructions 1551 inline void z_bc( branch_condition m1, int64_t d2, Register x2, Register b2);// branch m1 ? pc = (d2_uimm12+x2+b2) 1552 inline void z_bcr( branch_condition m1, Register r2); // branch (m1 && r2!=R0) ? pc = r2 1553 inline void z_brc( branch_condition i1, int64_t i2); // branch i1 ? pc = pc + i2_imm16 1554 inline void z_brc( branch_condition i1, address a); // branch i1 ? pc = a 1555 inline void z_brc( branch_condition i1, Label& L); // branch i1 ? pc = Label 1556 //inline void z_brcl(branch_condition i1, int64_t i2); // branch i1 ? pc = pc + i2_imm32 1557 inline void z_brcl(branch_condition i1, address a); // branch i1 ? pc = a 1558 inline void z_brcl(branch_condition i1, Label& L); // branch i1 ? pc = Label 1559 inline void z_bctgr(Register r1, Register r2); // branch on count r1 -= 1; (r1!=0) ? pc = r2 ; r1 is int64 1560 1561 // branch unconditional / always 1562 inline void z_br(Register r2); // branch to r2, nop if r2 == Z_R0 1563 1564 1565 // See also commodity routines compare64_and_branch(), compare32_and_branch(). 1566 // signed comparison and branch 1567 inline void z_crb( Register r1, Register r2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 r2) ? goto b4+d4 ; int32 -- z10 1568 inline void z_cgrb(Register r1, Register r2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 r2) ? goto b4+d4 ; int64 -- z10 1569 inline void z_crj( Register r1, Register r2, branch_condition m3, Label& L); // (r1 m3 r2) ? goto L ; int32 -- z10 1570 inline void z_crj( Register r1, Register r2, branch_condition m3, address a4); // (r1 m3 r2) ? goto (pc+a4<<1) ; int32 -- z10 1571 inline void z_cgrj(Register r1, Register r2, branch_condition m3, Label& L); // (r1 m3 r2) ? goto L ; int64 -- z10 1572 inline void z_cgrj(Register r1, Register r2, branch_condition m3, address a4); // (r1 m3 r2) ? goto (pc+a4<<1) ; int64 -- z10 1573 inline void z_cib( Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 i2_imm8) ? goto b4+d4 ; int32 -- z10 1574 inline void z_cgib(Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 i2_imm8) ? goto b4+d4 ; int64 -- z10 1575 inline void z_cij( Register r1, int64_t i2, branch_condition m3, Label& L); // (r1 m3 i2_imm8) ? goto L ; int32 -- z10 1576 inline void z_cij( Register r1, int64_t i2, branch_condition m3, address a4); // (r1 m3 i2_imm8) ? goto (pc+a4<<1) ; int32 -- z10 1577 inline void z_cgij(Register r1, int64_t i2, branch_condition m3, Label& L); // (r1 m3 i2_imm8) ? goto L ; int64 -- z10 1578 inline void z_cgij(Register r1, int64_t i2, branch_condition m3, address a4); // (r1 m3 i2_imm8) ? goto (pc+a4<<1) ; int64 -- z10 1579 // unsigned comparison and branch 1580 inline void z_clrb( Register r1, Register r2, branch_condition m3, int64_t d4, Register b4);// (r1 m3 r2) ? goto b4+d4 ; uint32 -- z10 1581 inline void z_clgrb(Register r1, Register r2, branch_condition m3, int64_t d4, Register b4);// (r1 m3 r2) ? goto b4+d4 ; uint64 -- z10 1582 inline void z_clrj( Register r1, Register r2, branch_condition m3, Label& L); // (r1 m3 r2) ? goto L ; uint32 -- z10 1583 inline void z_clrj( Register r1, Register r2, branch_condition m3, address a4); // (r1 m3 r2) ? goto (pc+a4<<1) ; uint32 -- z10 1584 inline void z_clgrj(Register r1, Register r2, branch_condition m3, Label& L); // (r1 m3 r2) ? goto L ; uint64 -- z10 1585 inline void z_clgrj(Register r1, Register r2, branch_condition m3, address a4); // (r1 m3 r2) ? goto (pc+a4<<1) ; uint64 -- z10 1586 inline void z_clib( Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 i2_uimm8) ? goto b4+d4 ; uint32 -- z10 1587 inline void z_clgib(Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 i2_uimm8) ? goto b4+d4 ; uint64 -- z10 1588 inline void z_clij( Register r1, int64_t i2, branch_condition m3, Label& L); // (r1 m3 i2_uimm8) ? goto L ; uint32 -- z10 1589 inline void z_clij( Register r1, int64_t i2, branch_condition m3, address a4); // (r1 m3 i2_uimm8) ? goto (pc+a4<<1) ; uint32 -- z10 1590 inline void z_clgij(Register r1, int64_t i2, branch_condition m3, Label& L); // (r1 m3 i2_uimm8) ? goto L ; uint64 -- z10 1591 inline void z_clgij(Register r1, int64_t i2, branch_condition m3, address a4); // (r1 m3 i2_uimm8) ? goto (pc+a4<<1) ; uint64 -- z10 1592 1593 // Compare and trap instructions. 1594 // signed comparison 1595 inline void z_crt(Register r1, Register r2, int64_t m3); // (r1 m3 r2) ? trap ; int32 -- z10 1596 inline void z_cgrt(Register r1, Register r2, int64_t m3); // (r1 m3 r2) ? trap ; int64 -- z10 1597 inline void z_cit(Register r1, int64_t i2, int64_t m3); // (r1 m3 i2_imm16) ? trap ; int32 -- z10 1598 inline void z_cgit(Register r1, int64_t i2, int64_t m3); // (r1 m3 i2_imm16) ? trap ; int64 -- z10 1599 // unsigned comparison 1600 inline void z_clrt(Register r1, Register r2, int64_t m3); // (r1 m3 r2) ? trap ; uint32 -- z10 1601 inline void z_clgrt(Register r1, Register r2, int64_t m3); // (r1 m3 r2) ? trap ; uint64 -- z10 1602 inline void z_clfit(Register r1, int64_t i2, int64_t m3); // (r1 m3 i2_uimm16) ? trap ; uint32 -- z10 1603 inline void z_clgit(Register r1, int64_t i2, int64_t m3); // (r1 m3 i2_uimm16) ? trap ; uint64 -- z10 1604 1605 inline void z_illtrap(); 1606 inline void z_illtrap(int id); 1607 inline void z_illtrap_eyecatcher(unsigned short xpattern, unsigned short pattern); 1608 1609 1610 // load address, add for addresses 1611 // =============================== 1612 1613 // The versions without suffix z assert that the base reg is != Z_R0. 1614 // Z_R0 is interpreted as constant '0'. The variants with Address operand 1615 // check this automatically, so no two versions are needed. 1616 inline void z_layz(Register r1, int64_t d2, Register x2, Register b2); // Special version. Allows Z_R0 as base reg. 1617 inline void z_lay(Register r1, const Address &a); // r1 = a 1618 inline void z_lay(Register r1, int64_t d2, Register x2, Register b2); // r1 = d2_imm20+x2+b2 1619 inline void z_laz(Register r1, int64_t d2, Register x2, Register b2); // Special version. Allows Z_R0 as base reg. 1620 inline void z_la(Register r1, const Address &a); // r1 = a ; unsigned immediate! 1621 inline void z_la(Register r1, int64_t d2, Register x2, Register b2); // r1 = d2_uimm12+x2+b2 ; unsigned immediate! 1622 inline void z_larl(Register r1, int64_t i2); // r1 = pc + i2_imm32<<1; 1623 inline void z_larl(Register r1, address a2); // r1 = pc + i2_imm32<<1; 1624 1625 // Load instructions for integers 1626 // ============================== 1627 1628 // Address as base + index + offset 1629 inline void z_lb( Register r1, const Address &a); // load r1 = *(a) ; int32 <- int8 1630 inline void z_lb( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int32 <- int8 1631 inline void z_lh( Register r1, const Address &a); // load r1 = *(a) ; int32 <- int16 1632 inline void z_lh( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2); int32 <- int16 1633 inline void z_lhy(Register r1, const Address &a); // load r1 = *(a) ; int32 <- int16 1634 inline void z_lhy(Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int32 <- int16 1635 inline void z_l( Register r1, const Address& a); // load r1 = *(a) ; int32 1636 inline void z_l( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2); int32 1637 inline void z_ly( Register r1, const Address& a); // load r1 = *(a) ; int32 1638 inline void z_ly( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int32 1639 1640 inline void z_lgb(Register r1, const Address &a); // load r1 = *(a) ; int64 <- int8 1641 inline void z_lgb(Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int64 <- int8 1642 inline void z_lgh(Register r1, const Address &a); // load r1 = *(a) ; int64 <- int16 1643 inline void z_lgh(Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm12+x2+b2) ; int64 <- int16 1644 inline void z_lgf(Register r1, const Address &a); // load r1 = *(a) ; int64 <- int32 1645 inline void z_lgf(Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int64 <- int32 1646 inline void z_lg( Register r1, const Address& a); // load r1 = *(a) ; int64 <- int64 1647 inline void z_lg( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int64 <- int64 1648 1649 // load and test 1650 inline void z_lt( Register r1, const Address &a); // load and test r1 = *(a) ; int32 1651 inline void z_lt( Register r1, int64_t d2, Register x2, Register b2);// load and test r1 = *(d2_imm20+x2+b2) ; int32 1652 inline void z_ltg( Register r1, const Address &a); // load and test r1 = *(a) ; int64 1653 inline void z_ltg( Register r1, int64_t d2, Register x2, Register b2);// load and test r1 = *(d2_imm20+x2+b2) ; int64 1654 inline void z_ltgf(Register r1, const Address &a); // load and test r1 = *(a) ; int64 <- int32 1655 inline void z_ltgf(Register r1, int64_t d2, Register x2, Register b2);// load and test r1 = *(d2_imm20+x2+b2) ; int64 <- int32 1656 1657 // load unsigned integer - zero extended 1658 inline void z_llc( Register r1, const Address& a); // load r1 = *(a) ; uint32 <- uint8 1659 inline void z_llc( Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint32 <- uint8 1660 inline void z_llh( Register r1, const Address& a); // load r1 = *(a) ; uint32 <- uint16 1661 inline void z_llh( Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint32 <- uint16 1662 inline void z_llgc(Register r1, const Address& a); // load r1 = *(a) ; uint64 <- uint8 1663 inline void z_llgc(Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint64 <- uint8 1664 inline void z_llgc( Register r1, int64_t d2, Register b2); // load r1 = *(d2_imm20+b2) ; uint64 <- uint8 1665 inline void z_llgh(Register r1, const Address& a); // load r1 = *(a) ; uint64 <- uint16 1666 inline void z_llgh(Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint64 <- uint16 1667 inline void z_llgf(Register r1, const Address& a); // load r1 = *(a) ; uint64 <- uint32 1668 inline void z_llgf(Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint64 <- uint32 1669 1670 // pc relative addressing 1671 inline void z_lhrl( Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int32 <- int16 -- z10 1672 inline void z_lrl( Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int32 -- z10 1673 inline void z_lghrl(Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int64 <- int16 -- z10 1674 inline void z_lgfrl(Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int64 <- int32 -- z10 1675 inline void z_lgrl( Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int64 -- z10 1676 1677 inline void z_llhrl( Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; uint32 <- uint16 -- z10 1678 inline void z_llghrl(Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; uint64 <- uint16 -- z10 1679 inline void z_llgfrl(Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; uint64 <- uint32 -- z10 1680 1681 // Store instructions for integers 1682 // =============================== 1683 1684 // Address as base + index + offset 1685 inline void z_stc( Register r1, const Address &d); // store *(a) = r1 ; int8 1686 inline void z_stc( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; int8 1687 inline void z_stcy(Register r1, const Address &d); // store *(a) = r1 ; int8 1688 inline void z_stcy(Register r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; int8 1689 inline void z_sth( Register r1, const Address &d); // store *(a) = r1 ; int16 1690 inline void z_sth( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; int16 1691 inline void z_sthy(Register r1, const Address &d); // store *(a) = r1 ; int16 1692 inline void z_sthy(Register r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; int16 1693 inline void z_st( Register r1, const Address &d); // store *(a) = r1 ; int32 1694 inline void z_st( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; int32 1695 inline void z_sty( Register r1, const Address &d); // store *(a) = r1 ; int32 1696 inline void z_sty( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; int32 1697 inline void z_stg( Register r1, const Address &d); // store *(a) = r1 ; int64 1698 inline void z_stg( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; int64 1699 1700 inline void z_stcm( Register r1, int64_t m3, int64_t d2, Register b2); // store character under mask 1701 inline void z_stcmy(Register r1, int64_t m3, int64_t d2, Register b2); // store character under mask 1702 inline void z_stcmh(Register r1, int64_t m3, int64_t d2, Register b2); // store character under mask 1703 1704 // pc relative addressing 1705 inline void z_sthrl(Register r1, int64_t i2); // store *(pc + i2_imm32<<1) = r1 ; int16 -- z10 1706 inline void z_strl( Register r1, int64_t i2); // store *(pc + i2_imm32<<1) = r1 ; int32 -- z10 1707 inline void z_stgrl(Register r1, int64_t i2); // store *(pc + i2_imm32<<1) = r1 ; int64 -- z10 1708 1709 1710 // Load and store immediates 1711 // ========================= 1712 1713 // load immediate 1714 inline void z_lhi( Register r1, int64_t i2); // r1 = i2_imm16 ; int32 <- int16 1715 inline void z_lghi(Register r1, int64_t i2); // r1 = i2_imm16 ; int64 <- int16 1716 inline void z_lgfi(Register r1, int64_t i2); // r1 = i2_imm32 ; int64 <- int32 1717 1718 inline void z_llihf(Register r1, int64_t i2); // r1 = i2_imm32 ; uint64 <- (uint32<<32) 1719 inline void z_llilf(Register r1, int64_t i2); // r1 = i2_imm32 ; uint64 <- uint32 1720 inline void z_llihh(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- (uint16<<48) 1721 inline void z_llihl(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- (uint16<<32) 1722 inline void z_llilh(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- (uint16<<16) 1723 inline void z_llill(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- uint16 1724 1725 // insert immediate 1726 inline void z_ic( Register r1, int64_t d2, Register x2, Register b2); // insert character 1727 inline void z_icy( Register r1, int64_t d2, Register x2, Register b2); // insert character 1728 inline void z_icm( Register r1, int64_t m3, int64_t d2, Register b2); // insert character under mask 1729 inline void z_icmy(Register r1, int64_t m3, int64_t d2, Register b2); // insert character under mask 1730 inline void z_icmh(Register r1, int64_t m3, int64_t d2, Register b2); // insert character under mask 1731 1732 inline void z_iihh(Register r1, int64_t i2); // insert immediate r1[ 0-15] = i2_imm16 1733 inline void z_iihl(Register r1, int64_t i2); // insert immediate r1[16-31] = i2_imm16 1734 inline void z_iilh(Register r1, int64_t i2); // insert immediate r1[32-47] = i2_imm16 1735 inline void z_iill(Register r1, int64_t i2); // insert immediate r1[48-63] = i2_imm16 1736 inline void z_iihf(Register r1, int64_t i2); // insert immediate r1[32-63] = i2_imm32 1737 inline void z_iilf(Register r1, int64_t i2); // insert immediate r1[ 0-31] = i2_imm32 1738 1739 // store immediate 1740 inline void z_mvhhi(const Address &d, int64_t i2); // store *(d) = i2_imm16 ; int16 1741 inline void z_mvhhi(int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm16 ; int16 1742 inline void z_mvhi( const Address &d, int64_t i2); // store *(d) = i2_imm16 ; int32 1743 inline void z_mvhi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm16 ; int32 1744 inline void z_mvghi(const Address &d, int64_t i2); // store *(d) = i2_imm16 ; int64 1745 inline void z_mvghi(int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm16 ; int64 1746 1747 // Move and Convert instructions 1748 // ============================= 1749 1750 // move, sign extend 1751 inline void z_lbr(Register r1, Register r2); // move r1 = r2 ; int32 <- int8 1752 inline void z_lhr( Register r1, Register r2); // move r1 = r2 ; int32 <- int16 1753 inline void z_lr(Register r1, Register r2); // move r1 = r2 ; int32, no sign extension 1754 inline void z_lgbr(Register r1, Register r2); // move r1 = r2 ; int64 <- int8 1755 inline void z_lghr(Register r1, Register r2); // move r1 = r2 ; int64 <- int16 1756 inline void z_lgfr(Register r1, Register r2); // move r1 = r2 ; int64 <- int32 1757 inline void z_lgr(Register r1, Register r2); // move r1 = r2 ; int64 1758 // move, zero extend 1759 inline void z_llhr( Register r1, Register r2); // move r1 = r2 ; uint32 <- uint16 1760 inline void z_llgcr(Register r1, Register r2); // move r1 = r2 ; uint64 <- uint8 1761 inline void z_llghr(Register r1, Register r2); // move r1 = r2 ; uint64 <- uint16 1762 inline void z_llgfr(Register r1, Register r2); // move r1 = r2 ; uint64 <- uint32 1763 1764 // move and test register 1765 inline void z_ltr(Register r1, Register r2); // load/move and test r1 = r2; int32 1766 inline void z_ltgr(Register r1, Register r2); // load/move and test r1 = r2; int64 1767 inline void z_ltgfr(Register r1, Register r2); // load/move and test r1 = r2; int64 <-- int32 1768 1769 // move and byte-reverse 1770 inline void z_lrvr( Register r1, Register r2); // move and reverse byte order r1 = r2; int32 1771 inline void z_lrvgr(Register r1, Register r2); // move and reverse byte order r1 = r2; int64 1772 1773 1774 // Arithmetic instructions (Integer only) 1775 // ====================================== 1776 // For float arithmetic instructions scroll further down 1777 // Add logical differs in the condition codes set! 1778 1779 // add registers 1780 inline void z_ar( Register r1, Register r2); // add r1 = r1 + r2 ; int32 1781 inline void z_agr( Register r1, Register r2); // add r1 = r1 + r2 ; int64 1782 inline void z_agfr( Register r1, Register r2); // add r1 = r1 + r2 ; int64 <- int32 1783 inline void z_ark( Register r1, Register r2, Register r3); // add r1 = r2 + r3 ; int32 1784 inline void z_agrk( Register r1, Register r2, Register r3); // add r1 = r2 + r3 ; int64 1785 1786 inline void z_alr( Register r1, Register r2); // add logical r1 = r1 + r2 ; int32 1787 inline void z_algr( Register r1, Register r2); // add logical r1 = r1 + r2 ; int64 1788 inline void z_algfr(Register r1, Register r2); // add logical r1 = r1 + r2 ; int64 <- int32 1789 inline void z_alrk( Register r1, Register r2, Register r3); // add logical r1 = r2 + r3 ; int32 1790 inline void z_algrk(Register r1, Register r2, Register r3); // add logical r1 = r2 + r3 ; int64 1791 inline void z_alcgr(Register r1, Register r2); // add logical with carry r1 = r1 + r2 + c ; int64 1792 1793 // add immediate 1794 inline void z_ahi( Register r1, int64_t i2); // add r1 = r1 + i2_imm16 ; int32 1795 inline void z_afi( Register r1, int64_t i2); // add r1 = r1 + i2_imm32 ; int32 1796 inline void z_alfi( Register r1, int64_t i2); // add r1 = r1 + i2_imm32 ; int32 1797 inline void z_aghi( Register r1, int64_t i2); // add logical r1 = r1 + i2_imm16 ; int64 1798 inline void z_agfi( Register r1, int64_t i2); // add r1 = r1 + i2_imm32 ; int64 1799 inline void z_algfi(Register r1, int64_t i2); // add logical r1 = r1 + i2_imm32 ; int64 1800 inline void z_ahik( Register r1, Register r3, int64_t i2); // add r1 = r3 + i2_imm16 ; int32 1801 inline void z_aghik(Register r1, Register r3, int64_t i2); // add r1 = r3 + i2_imm16 ; int64 1802 inline void z_aih( Register r1, int64_t i2); // add r1 = r1 + i2_imm32 ; int32 (HiWord) 1803 1804 // add memory 1805 inline void z_a( Register r1, int64_t d2, Register x2, Register b2); // add r1 = r1 + *(d2_uimm12+s2+b2) ; int32 1806 inline void z_ay( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+s2+b2) ; int32 1807 inline void z_ag( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+s2+b2) ; int64 1808 inline void z_agf( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+x2+b2) ; int64 <- int32 1809 inline void z_al( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_uimm12+x2+b2) ; int32 1810 inline void z_aly( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+x2+b2) ; int32 1811 inline void z_alg( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+x2+b2) ; int64 1812 inline void z_algf(Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+x2+b2) ; int64 <- int32 1813 inline void z_a( Register r1, const Address& a); // add r1 = r1 + *(a) ; int32 1814 inline void z_ay( Register r1, const Address& a); // add r1 = r1 + *(a) ; int32 1815 inline void z_al( Register r1, const Address& a); // add r1 = r1 + *(a) ; int32 1816 inline void z_aly( Register r1, const Address& a); // add r1 = r1 + *(a) ; int32 1817 inline void z_ag( Register r1, const Address& a); // add r1 = r1 + *(a) ; int64 1818 inline void z_agf( Register r1, const Address& a); // add r1 = r1 + *(a) ; int64 <- int32 1819 inline void z_alg( Register r1, const Address& a); // add r1 = r1 + *(a) ; int64 1820 inline void z_algf(Register r1, const Address& a); // add r1 = r1 + *(a) ; int64 <- int32 1821 1822 1823 inline void z_alhsik( Register r1, Register r3, int64_t i2); // add logical r1 = r3 + i2_imm16 ; int32 1824 inline void z_alghsik(Register r1, Register r3, int64_t i2); // add logical r1 = r3 + i2_imm16 ; int64 1825 1826 inline void z_asi( int64_t d1, Register b1, int64_t i2); // add *(d1_imm20+b1) += i2_imm8 ; int32 -- z10 1827 inline void z_agsi( int64_t d1, Register b1, int64_t i2); // add *(d1_imm20+b1) += i2_imm8 ; int64 -- z10 1828 inline void z_alsi( int64_t d1, Register b1, int64_t i2); // add logical *(d1_imm20+b1) += i2_imm8 ; uint32 -- z10 1829 inline void z_algsi(int64_t d1, Register b1, int64_t i2); // add logical *(d1_imm20+b1) += i2_imm8 ; uint64 -- z10 1830 inline void z_asi( const Address& d, int64_t i2); // add *(d) += i2_imm8 ; int32 -- z10 1831 inline void z_agsi( const Address& d, int64_t i2); // add *(d) += i2_imm8 ; int64 -- z10 1832 inline void z_alsi( const Address& d, int64_t i2); // add logical *(d) += i2_imm8 ; uint32 -- z10 1833 inline void z_algsi(const Address& d, int64_t i2); // add logical *(d) += i2_imm8 ; uint64 -- z10 1834 1835 // negate 1836 inline void z_lcr( Register r1, Register r2 = noreg); // neg r1 = -r2 ; int32 1837 inline void z_lcgr( Register r1, Register r2 = noreg); // neg r1 = -r2 ; int64 1838 inline void z_lcgfr(Register r1, Register r2); // neg r1 = -r2 ; int64 <- int32 1839 inline void z_lnr( Register r1, Register r2 = noreg); // neg r1 = -|r2| ; int32 1840 inline void z_lngr( Register r1, Register r2 = noreg); // neg r1 = -|r2| ; int64 1841 inline void z_lngfr(Register r1, Register r2); // neg r1 = -|r2| ; int64 <- int32 1842 1843 // subtract intstructions 1844 // sub registers 1845 inline void z_sr( Register r1, Register r2); // sub r1 = r1 - r2 ; int32 1846 inline void z_sgr( Register r1, Register r2); // sub r1 = r1 - r2 ; int64 1847 inline void z_sgfr( Register r1, Register r2); // sub r1 = r1 - r2 ; int64 <- int32 1848 inline void z_srk( Register r1, Register r2, Register r3); // sub r1 = r2 - r3 ; int32 1849 inline void z_sgrk( Register r1, Register r2, Register r3); // sub r1 = r2 - r3 ; int64 1850 1851 inline void z_slr( Register r1, Register r2); // sub logical r1 = r1 - r2 ; int32 1852 inline void z_slgr( Register r1, Register r2); // sub logical r1 = r1 - r2 ; int64 1853 inline void z_slgfr(Register r1, Register r2); // sub logical r1 = r1 - r2 ; int64 <- int32 1854 inline void z_slrk( Register r1, Register r2, Register r3); // sub logical r1 = r2 - r3 ; int32 1855 inline void z_slgrk(Register r1, Register r2, Register r3); // sub logical r1 = r2 - r3 ; int64 1856 inline void z_slfi( Register r1, int64_t i2); // sub logical r1 = r1 - i2_uimm32 ; int32 1857 inline void z_slgfi(Register r1, int64_t i2); // add logical r1 = r1 - i2_uimm32 ; int64 1858 1859 // sub memory 1860 inline void z_s( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int32 1861 inline void z_sy( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 + *(d2_imm20+s2+b2) ; int32 1862 inline void z_sg( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int64 1863 inline void z_sgf( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int64 - int32 1864 inline void z_slg( Register r1, int64_t d2, Register x2, Register b2); // sub logical r1 = r1 - *(d2_imm20+x2+b2) ; uint64 1865 inline void z_slgf(Register r1, int64_t d2, Register x2, Register b2); // sub logical r1 = r1 - *(d2_imm20+x2+b2) ; uint64 - uint32 1866 inline void z_s( Register r1, const Address& a); // sub r1 = r1 - *(a) ; int32 1867 inline void z_sy( Register r1, const Address& a); // sub r1 = r1 - *(a) ; int32 1868 inline void z_sg( Register r1, const Address& a); // sub r1 = r1 - *(a) ; int64 1869 inline void z_sgf( Register r1, const Address& a); // sub r1 = r1 - *(a) ; int64 - int32 1870 inline void z_slg( Register r1, const Address& a); // sub r1 = r1 - *(a) ; uint64 1871 inline void z_slgf(Register r1, const Address& a); // sub r1 = r1 - *(a) ; uint64 - uint32 1872 1873 inline void z_sh( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int32 - int16 1874 inline void z_shy( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm20+x2+b2) ; int32 - int16 1875 inline void z_sh( Register r1, const Address &a); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int32 - int16 1876 inline void z_shy( Register r1, const Address &a); // sub r1 = r1 - *(d2_imm20+x2+b2) ; int32 - int16 1877 1878 // Multiplication instructions 1879 // mul registers 1880 inline void z_msr( Register r1, Register r2); // mul r1 = r1 * r2 ; int32 1881 inline void z_msgr( Register r1, Register r2); // mul r1 = r1 * r2 ; int64 1882 inline void z_msgfr(Register r1, Register r2); // mul r1 = r1 * r2 ; int64 <- int32 1883 inline void z_mlr( Register r1, Register r2); // mul r1 = r1 * r2 ; int32 unsigned 1884 inline void z_mlgr( Register r1, Register r2); // mul r1 = r1 * r2 ; int64 unsigned 1885 // mul register - memory 1886 inline void z_mhy( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 1887 inline void z_msy( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 1888 inline void z_msg( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 1889 inline void z_msgf(Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 1890 inline void z_ml( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 1891 inline void z_mlg( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 1892 inline void z_mhy( Register r1, const Address& a); // mul r1 = r1 * *(a) 1893 inline void z_msy( Register r1, const Address& a); // mul r1 = r1 * *(a) 1894 inline void z_msg( Register r1, const Address& a); // mul r1 = r1 * *(a) 1895 inline void z_msgf(Register r1, const Address& a); // mul r1 = r1 * *(a) 1896 inline void z_ml( Register r1, const Address& a); // mul r1 = r1 * *(a) 1897 inline void z_mlg( Register r1, const Address& a); // mul r1 = r1 * *(a) 1898 1899 inline void z_msfi( Register r1, int64_t i2); // mult r1 = r1 * i2_imm32; int32 -- z10 1900 inline void z_msgfi(Register r1, int64_t i2); // mult r1 = r1 * i2_imm32; int64 -- z10 1901 inline void z_mhi( Register r1, int64_t i2); // mult r1 = r1 * i2_imm16; int32 1902 inline void z_mghi( Register r1, int64_t i2); // mult r1 = r1 * i2_imm16; int64 1903 1904 // Division instructions 1905 inline void z_dsgr( Register r1, Register r2); // div r1 = r1 / r2 ; int64/int32 needs reg pair! 1906 inline void z_dsgfr(Register r1, Register r2); // div r1 = r1 / r2 ; int64/int32 needs reg pair! 1907 1908 1909 // Logic instructions 1910 // =================== 1911 1912 // and 1913 inline void z_n( Register r1, int64_t d2, Register x2, Register b2); 1914 inline void z_ny( Register r1, int64_t d2, Register x2, Register b2); 1915 inline void z_ng( Register r1, int64_t d2, Register x2, Register b2); 1916 inline void z_n( Register r1, const Address& a); 1917 inline void z_ny( Register r1, const Address& a); 1918 inline void z_ng( Register r1, const Address& a); 1919 1920 inline void z_nr( Register r1, Register r2); // and r1 = r1 & r2 ; int32 1921 inline void z_ngr( Register r1, Register r2); // and r1 = r1 & r2 ; int64 1922 inline void z_nrk( Register r1, Register r2, Register r3); // and r1 = r2 & r3 ; int32 1923 inline void z_ngrk(Register r1, Register r2, Register r3); // and r1 = r2 & r3 ; int64 1924 1925 inline void z_nihh(Register r1, int64_t i2); // and r1 = r1 & i2_imm16 ; and only for bits 0-15 1926 inline void z_nihl(Register r1, int64_t i2); // and r1 = r1 & i2_imm16 ; and only for bits 16-31 1927 inline void z_nilh(Register r1, int64_t i2); // and r1 = r1 & i2_imm16 ; and only for bits 32-47 1928 inline void z_nill(Register r1, int64_t i2); // and r1 = r1 & i2_imm16 ; and only for bits 48-63 1929 inline void z_nihf(Register r1, int64_t i2); // and r1 = r1 & i2_imm32 ; and only for bits 0-31 1930 inline void z_nilf(Register r1, int64_t i2); // and r1 = r1 & i2_imm32 ; and only for bits 32-63 see also MacroAssembler::nilf. 1931 1932 // or 1933 inline void z_o( Register r1, int64_t d2, Register x2, Register b2); 1934 inline void z_oy( Register r1, int64_t d2, Register x2, Register b2); 1935 inline void z_og( Register r1, int64_t d2, Register x2, Register b2); 1936 inline void z_o( Register r1, const Address& a); 1937 inline void z_oy( Register r1, const Address& a); 1938 inline void z_og( Register r1, const Address& a); 1939 1940 inline void z_or( Register r1, Register r2); // or r1 = r1 | r2; int32 1941 inline void z_ogr( Register r1, Register r2); // or r1 = r1 | r2; int64 1942 inline void z_ork( Register r1, Register r2, Register r3); // or r1 = r2 | r3 ; int32 1943 inline void z_ogrk(Register r1, Register r2, Register r3); // or r1 = r2 | r3 ; int64 1944 1945 inline void z_oihh(Register r1, int64_t i2); // or r1 = r1 | i2_imm16 ; or only for bits 0-15 1946 inline void z_oihl(Register r1, int64_t i2); // or r1 = r1 | i2_imm16 ; or only for bits 16-31 1947 inline void z_oilh(Register r1, int64_t i2); // or r1 = r1 | i2_imm16 ; or only for bits 32-47 1948 inline void z_oill(Register r1, int64_t i2); // or r1 = r1 | i2_imm16 ; or only for bits 48-63 1949 inline void z_oihf(Register r1, int64_t i2); // or r1 = r1 | i2_imm32 ; or only for bits 0-31 1950 inline void z_oilf(Register r1, int64_t i2); // or r1 = r1 | i2_imm32 ; or only for bits 32-63 1951 1952 // xor 1953 inline void z_x( Register r1, int64_t d2, Register x2, Register b2); 1954 inline void z_xy( Register r1, int64_t d2, Register x2, Register b2); 1955 inline void z_xg( Register r1, int64_t d2, Register x2, Register b2); 1956 inline void z_x( Register r1, const Address& a); 1957 inline void z_xy( Register r1, const Address& a); 1958 inline void z_xg( Register r1, const Address& a); 1959 1960 inline void z_xr( Register r1, Register r2); // xor r1 = r1 ^ r2 ; int32 1961 inline void z_xgr( Register r1, Register r2); // xor r1 = r1 ^ r2 ; int64 1962 inline void z_xrk( Register r1, Register r2, Register r3); // xor r1 = r2 ^ r3 ; int32 1963 inline void z_xgrk(Register r1, Register r2, Register r3); // xor r1 = r2 ^ r3 ; int64 1964 1965 inline void z_xihf(Register r1, int64_t i2); // xor r1 = r1 ^ i2_imm32 ; or only for bits 0-31 1966 inline void z_xilf(Register r1, int64_t i2); // xor r1 = r1 ^ i2_imm32 ; or only for bits 32-63 1967 1968 // shift 1969 inline void z_sla( Register r1, int64_t d2, Register b2=Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, only 31 bits shifted, sign preserved! 1970 inline void z_slag(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, only 63 bits shifted, sign preserved! 1971 inline void z_sra( Register r1, int64_t d2, Register b2=Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, sign extended 1972 inline void z_srag(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, sign extended 1973 inline void z_sll( Register r1, int64_t d2, Register b2=Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, zeros added 1974 inline void z_sllg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, zeros added 1975 inline void z_srl( Register r1, int64_t d2, Register b2=Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, zero extended 1976 inline void z_srlg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, zero extended 1977 1978 // rotate 1979 inline void z_rll( Register r1, Register r3, int64_t d2, Register b2=Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int32 -- z10 1980 inline void z_rllg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int64 -- z10 1981 1982 // rotate the AND/XOR/OR/insert 1983 inline void z_rnsbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then AND selected bits -- z196 1984 inline void z_rxsbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then XOR selected bits -- z196 1985 inline void z_rosbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then OR selected bits -- z196 1986 inline void z_risbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool zero_rest = false); // rotate then INS selected bits -- z196 1987 1988 1989 // memory-immediate instructions (8-bit immediate) 1990 // =============================================== 1991 1992 inline void z_cli( int64_t d1, Register b1, int64_t i2); // compare *(d1_imm12+b1) ^= i2_imm8 ; int8 1993 inline void z_mvi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm8 ; int8 1994 inline void z_tm( int64_t d1, Register b1, int64_t i2); // test *(d1_imm12+b1) against mask i2_imm8 ; int8 1995 inline void z_ni( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) &= i2_imm8 ; int8 1996 inline void z_oi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) |= i2_imm8 ; int8 1997 inline void z_xi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) ^= i2_imm8 ; int8 1998 inline void z_cliy(int64_t d1, Register b1, int64_t i2); // compare *(d1_imm12+b1) ^= i2_imm8 ; int8 1999 inline void z_mviy(int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm8 ; int8 2000 inline void z_tmy( int64_t d1, Register b1, int64_t i2); // test *(d1_imm12+b1) against mask i2_imm8 ; int8 2001 inline void z_niy( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) &= i2_imm8 ; int8 2002 inline void z_oiy( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) |= i2_imm8 ; int8 2003 inline void z_xiy( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) ^= i2_imm8 ; int8 2004 inline void z_cli( const Address& a, int64_t imm8); // compare *(a) ^= imm8 ; int8 2005 inline void z_mvi( const Address& a, int64_t imm8); // store *(a) = imm8 ; int8 2006 inline void z_tm( const Address& a, int64_t imm8); // test *(a) against mask imm8 ; int8 2007 inline void z_ni( const Address& a, int64_t imm8); // store *(a) &= imm8 ; int8 2008 inline void z_oi( const Address& a, int64_t imm8); // store *(a) |= imm8 ; int8 2009 inline void z_xi( const Address& a, int64_t imm8); // store *(a) ^= imm8 ; int8 2010 inline void z_cliy(const Address& a, int64_t imm8); // compare *(a) ^= imm8 ; int8 2011 inline void z_mviy(const Address& a, int64_t imm8); // store *(a) = imm8 ; int8 2012 inline void z_tmy( const Address& a, int64_t imm8); // test *(a) against mask imm8 ; int8 2013 inline void z_niy( const Address& a, int64_t imm8); // store *(a) &= imm8 ; int8 2014 inline void z_oiy( const Address& a, int64_t imm8); // store *(a) |= imm8 ; int8 2015 inline void z_xiy( const Address& a, int64_t imm8); // store *(a) ^= imm8 ; int8 2016 2017 2018 //------------------------------ 2019 // Interlocked-Update 2020 //------------------------------ 2021 inline void z_laa( Register r1, Register r3, int64_t d2, Register b2); // load and add int32, signed -- z196 2022 inline void z_laag( Register r1, Register r3, int64_t d2, Register b2); // load and add int64, signed -- z196 2023 inline void z_laal( Register r1, Register r3, int64_t d2, Register b2); // load and add int32, unsigned -- z196 2024 inline void z_laalg(Register r1, Register r3, int64_t d2, Register b2); // load and add int64, unsigned -- z196 2025 inline void z_lan( Register r1, Register r3, int64_t d2, Register b2); // load and and int32 -- z196 2026 inline void z_lang( Register r1, Register r3, int64_t d2, Register b2); // load and and int64 -- z196 2027 inline void z_lax( Register r1, Register r3, int64_t d2, Register b2); // load and xor int32 -- z196 2028 inline void z_laxg( Register r1, Register r3, int64_t d2, Register b2); // load and xor int64 -- z196 2029 inline void z_lao( Register r1, Register r3, int64_t d2, Register b2); // load and or int32 -- z196 2030 inline void z_laog( Register r1, Register r3, int64_t d2, Register b2); // load and or int64 -- z196 2031 2032 inline void z_laa( Register r1, Register r3, const Address& a); // load and add int32, signed -- z196 2033 inline void z_laag( Register r1, Register r3, const Address& a); // load and add int64, signed -- z196 2034 inline void z_laal( Register r1, Register r3, const Address& a); // load and add int32, unsigned -- z196 2035 inline void z_laalg(Register r1, Register r3, const Address& a); // load and add int64, unsigned -- z196 2036 inline void z_lan( Register r1, Register r3, const Address& a); // load and and int32 -- z196 2037 inline void z_lang( Register r1, Register r3, const Address& a); // load and and int64 -- z196 2038 inline void z_lax( Register r1, Register r3, const Address& a); // load and xor int32 -- z196 2039 inline void z_laxg( Register r1, Register r3, const Address& a); // load and xor int64 -- z196 2040 inline void z_lao( Register r1, Register r3, const Address& a); // load and or int32 -- z196 2041 inline void z_laog( Register r1, Register r3, const Address& a); // load and or int64 -- z196 2042 2043 //-------------------------------- 2044 // Execution Prediction 2045 //-------------------------------- 2046 inline void z_pfd( int64_t m1, int64_t d2, Register x2, Register b2); // prefetch 2047 inline void z_pfd( int64_t m1, Address a); 2048 inline void z_pfdrl(int64_t m1, int64_t i2); // prefetch 2049 inline void z_bpp( int64_t m1, int64_t i2, int64_t d3, Register b3); // branch prediction -- EC12 2050 inline void z_bprp( int64_t m1, int64_t i2, int64_t i3); // branch prediction -- EC12 2051 2052 //------------------------------- 2053 // Transaction Control 2054 //------------------------------- 2055 inline void z_tbegin(int64_t d1, Register b1, int64_t i2); // begin transaction -- EC12 2056 inline void z_tbeginc(int64_t d1, Register b1, int64_t i2); // begin transaction (constrained) -- EC12 2057 inline void z_tend(); // end transaction -- EC12 2058 inline void z_tabort(int64_t d2, Register b2); // abort transaction -- EC12 2059 inline void z_etnd(Register r1); // extract tx nesting depth -- EC12 2060 inline void z_ppa(Register r1, Register r2, int64_t m3); // perform processor assist -- EC12 2061 2062 //--------------------------------- 2063 // Conditional Execution 2064 //--------------------------------- 2065 inline void z_locr( Register r1, Register r2, branch_condition cc); // if (cc) load r1 = r2 ; int32 -- z196 2066 inline void z_locgr(Register r1, Register r2, branch_condition cc); // if (cc) load r1 = r2 ; int64 -- z196 2067 inline void z_loc( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) load r1 = *(d2_simm20+b2) ; int32 -- z196 2068 inline void z_locg( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) load r1 = *(d2_simm20+b2) ; int64 -- z196 2069 inline void z_loc( Register r1, const Address& a, branch_condition cc); // if (cc) load r1 = *(a) ; int32 -- z196 2070 inline void z_locg( Register r1, const Address& a, branch_condition cc); // if (cc) load r1 = *(a) ; int64 -- z196 2071 inline void z_stoc( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) store *(d2_simm20+b2) = r1 ; int32 -- z196 2072 inline void z_stocg(Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) store *(d2_simm20+b2) = r1 ; int64 -- z196 2073 2074 2075 // Complex CISC instructions 2076 // ========================== 2077 2078 inline void z_cksm(Register r1, Register r2); // checksum. This is NOT CRC32 2079 inline void z_km( Register r1, Register r2); // cipher message 2080 inline void z_kmc( Register r1, Register r2); // cipher message with chaining 2081 inline void z_kimd(Register r1, Register r2); // msg digest (SHA) 2082 inline void z_klmd(Register r1, Register r2); // msg digest (SHA) 2083 inline void z_kmac(Register r1, Register r2); // msg authentication code 2084 2085 inline void z_ex(Register r1, int64_t d2, Register x2, Register b2);// execute 2086 inline void z_exrl(Register r1, int64_t i2); // execute relative long -- z10 2087 inline void z_exrl(Register r1, address a2); // execute relative long -- z10 2088 2089 inline void z_ectg(int64_t d1, Register b1, int64_t d2, Register b2, Register r3); // extract cpu time 2090 inline void z_ecag(Register r1, Register r3, int64_t d2, Register b2); // extract CPU attribute 2091 2092 inline void z_srst(Register r1, Register r2); // search string 2093 inline void z_srstu(Register r1, Register r2); // search string unicode 2094 2095 inline void z_mvc(const Address& d, const Address& s, int64_t l); // move l bytes 2096 inline void z_mvc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2); // move l+1 bytes 2097 inline void z_mvcle(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // move region of memory 2098 2099 inline void z_stfle(int64_t d2, Register b2); // store facility list extended 2100 2101 inline void z_nc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// and *(d1+b1) = *(d1+l+b1) & *(d2+b2) ; d1, d2: uimm12, ands l+1 bytes 2102 inline void z_oc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// or *(d1+b1) = *(d1+l+b1) | *(d2+b2) ; d1, d2: uimm12, ors l+1 bytes 2103 inline void z_xc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// xor *(d1+b1) = *(d1+l+b1) ^ *(d2+b2) ; d1, d2: uimm12, xors l+1 bytes 2104 inline void z_nc(Address dst, int64_t len, Address src2); // and *dst = *dst & *src2, ands len bytes in memory 2105 inline void z_oc(Address dst, int64_t len, Address src2); // or *dst = *dst | *src2, ors len bytes in memory 2106 inline void z_xc(Address dst, int64_t len, Address src2); // xor *dst = *dst ^ *src2, xors len bytes in memory 2107 2108 // compare instructions 2109 inline void z_clc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2); // compare (*(d1_uimm12+b1), *(d1_uimm12+b1)) ; compare l bytes 2110 inline void z_clcle(Register r1, Register r3, int64_t d2, Register b2); // compare logical long extended, see docu 2111 inline void z_clclu(Register r1, Register r3, int64_t d2, Register b2); // compare logical long unicode, see docu 2112 2113 // Translate characters 2114 inline void z_troo(Register r1, Register r2, int64_t m3); 2115 inline void z_trot(Register r1, Register r2, int64_t m3); 2116 inline void z_trto(Register r1, Register r2, int64_t m3); 2117 inline void z_trtt(Register r1, Register r2, int64_t m3); 2118 2119 2120 // Floatingpoint instructions 2121 // ========================== 2122 2123 // compare instructions 2124 inline void z_cebr(FloatRegister r1, FloatRegister r2); // compare (r1, r2) ; float 2125 inline void z_ceb(FloatRegister r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm12+x2+b2)) ; float 2126 inline void z_ceb(FloatRegister r1, const Address &a); // compare (r1, *(d2_imm12+x2+b2)) ; float 2127 inline void z_cdbr(FloatRegister r1, FloatRegister r2); // compare (r1, r2) ; double 2128 inline void z_cdb(FloatRegister r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm12+x2+b2)) ; double 2129 inline void z_cdb(FloatRegister r1, const Address &a); // compare (r1, *(d2_imm12+x2+b2)) ; double 2130 2131 // load instructions 2132 inline void z_le( FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2) ; float 2133 inline void z_ley(FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; float 2134 inline void z_ld( FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2) ; double 2135 inline void z_ldy(FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; double 2136 inline void z_le( FloatRegister r1, const Address &a); // load r1 = *(a) ; float 2137 inline void z_ley(FloatRegister r1, const Address &a); // load r1 = *(a) ; float 2138 inline void z_ld( FloatRegister r1, const Address &a); // load r1 = *(a) ; double 2139 inline void z_ldy(FloatRegister r1, const Address &a); // load r1 = *(a) ; double 2140 2141 // store instructions 2142 inline void z_ste( FloatRegister r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; float 2143 inline void z_stey(FloatRegister r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; float 2144 inline void z_std( FloatRegister r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; double 2145 inline void z_stdy(FloatRegister r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; double 2146 inline void z_ste( FloatRegister r1, const Address &a); // store *(a) = r1 ; float 2147 inline void z_stey(FloatRegister r1, const Address &a); // store *(a) = r1 ; float 2148 inline void z_std( FloatRegister r1, const Address &a); // store *(a) = r1 ; double 2149 inline void z_stdy(FloatRegister r1, const Address &a); // store *(a) = r1 ; double 2150 2151 // load and store immediates 2152 inline void z_lzer(FloatRegister r1); // r1 = 0 ; single 2153 inline void z_lzdr(FloatRegister r1); // r1 = 0 ; double 2154 2155 // Move and Convert instructions 2156 inline void z_ler(FloatRegister r1, FloatRegister r2); // move r1 = r2 ; float 2157 inline void z_ldr(FloatRegister r1, FloatRegister r2); // move r1 = r2 ; double 2158 inline void z_ledbr(FloatRegister r1, FloatRegister r2); // conv / round r1 = r2 ; float <- double 2159 inline void z_ldebr(FloatRegister r1, FloatRegister r2); // conv r1 = r2 ; double <- float 2160 2161 // move between integer and float registers 2162 inline void z_cefbr( FloatRegister r1, Register r2); // r1 = r2; float <-- int32 2163 inline void z_cdfbr( FloatRegister r1, Register r2); // r1 = r2; double <-- int32 2164 inline void z_cegbr( FloatRegister r1, Register r2); // r1 = r2; float <-- int64 2165 inline void z_cdgbr( FloatRegister r1, Register r2); // r1 = r2; double <-- int64 2166 2167 // rounding mode for float-2-int conversions 2168 inline void z_cfebr(Register r1, FloatRegister r2, RoundingMode m); // conv r1 = r2 ; int32 <-- float 2169 inline void z_cfdbr(Register r1, FloatRegister r2, RoundingMode m); // conv r1 = r2 ; int32 <-- double 2170 inline void z_cgebr(Register r1, FloatRegister r2, RoundingMode m); // conv r1 = r2 ; int64 <-- float 2171 inline void z_cgdbr(Register r1, FloatRegister r2, RoundingMode m); // conv r1 = r2 ; int64 <-- double 2172 2173 inline void z_ldgr(FloatRegister r1, Register r2); // fr1 = r2 ; what kind of conversion? -- z10 2174 inline void z_lgdr(Register r1, FloatRegister r2); // r1 = fr2 ; what kind of conversion? -- z10 2175 2176 2177 // ADD 2178 inline void z_aebr(FloatRegister f1, FloatRegister f2); // f1 = f1 + f2 ; float 2179 inline void z_adbr(FloatRegister f1, FloatRegister f2); // f1 = f1 + f2 ; double 2180 inline void z_aeb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 + *(d2+x2+b2) ; float 2181 inline void z_adb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 + *(d2+x2+b2) ; double 2182 inline void z_aeb( FloatRegister f1, const Address& a); // f1 = f1 + *(a) ; float 2183 inline void z_adb( FloatRegister f1, const Address& a); // f1 = f1 + *(a) ; double 2184 2185 // SUB 2186 inline void z_sebr(FloatRegister f1, FloatRegister f2); // f1 = f1 - f2 ; float 2187 inline void z_sdbr(FloatRegister f1, FloatRegister f2); // f1 = f1 - f2 ; double 2188 inline void z_seb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 - *(d2+x2+b2) ; float 2189 inline void z_sdb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 - *(d2+x2+b2) ; double 2190 inline void z_seb( FloatRegister f1, const Address& a); // f1 = f1 - *(a) ; float 2191 inline void z_sdb( FloatRegister f1, const Address& a); // f1 = f1 - *(a) ; double 2192 // negate 2193 inline void z_lcebr(FloatRegister r1, FloatRegister r2); // neg r1 = -r2 ; float 2194 inline void z_lcdbr(FloatRegister r1, FloatRegister r2); // neg r1 = -r2 ; double 2195 2196 // Absolute value, monadic if fr2 == noreg. 2197 inline void z_lpdbr( FloatRegister fr1, FloatRegister fr2 = fnoreg); // fr1 = |fr2| 2198 2199 2200 // MUL 2201 inline void z_meebr(FloatRegister f1, FloatRegister f2); // f1 = f1 * f2 ; float 2202 inline void z_mdbr( FloatRegister f1, FloatRegister f2); // f1 = f1 * f2 ; double 2203 inline void z_meeb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 * *(d2+x2+b2) ; float 2204 inline void z_mdb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 * *(d2+x2+b2) ; double 2205 inline void z_meeb( FloatRegister f1, const Address& a); 2206 inline void z_mdb( FloatRegister f1, const Address& a); 2207 2208 // DIV 2209 inline void z_debr( FloatRegister f1, FloatRegister f2); // f1 = f1 / f2 ; float 2210 inline void z_ddbr( FloatRegister f1, FloatRegister f2); // f1 = f1 / f2 ; double 2211 inline void z_deb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 / *(d2+x2+b2) ; float 2212 inline void z_ddb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 / *(d2+x2+b2) ; double 2213 inline void z_deb( FloatRegister f1, const Address& a); // f1 = f1 / *(a) ; float 2214 inline void z_ddb( FloatRegister f1, const Address& a); // f1 = f1 / *(a) ; double 2215 2216 // square root 2217 inline void z_sqdbr(FloatRegister fr1, FloatRegister fr2); // fr1 = sqrt(fr2) ; double 2218 inline void z_sqdb( FloatRegister fr1, int64_t d2, Register x2, Register b2); // fr1 = srqt( *(d2+x2+b2) 2219 inline void z_sqdb( FloatRegister fr1, int64_t d2, Register b2); // fr1 = srqt( *(d2+b2) 2220 2221 // Nop instruction 2222 // =============== 2223 2224 // branch never (nop) 2225 inline void z_nop(); 2226 2227 // =============================================================================================== 2228 2229 // Simplified emitters: 2230 // ==================== 2231 2232 2233 // Some memory instructions without index register (just convenience). 2234 inline void z_layz(Register r1, int64_t d2, Register b2 = Z_R0); 2235 inline void z_lay(Register r1, int64_t d2, Register b2); 2236 inline void z_laz(Register r1, int64_t d2, Register b2); 2237 inline void z_la(Register r1, int64_t d2, Register b2); 2238 inline void z_l(Register r1, int64_t d2, Register b2); 2239 inline void z_ly(Register r1, int64_t d2, Register b2); 2240 inline void z_lg(Register r1, int64_t d2, Register b2); 2241 inline void z_st(Register r1, int64_t d2, Register b2); 2242 inline void z_sty(Register r1, int64_t d2, Register b2); 2243 inline void z_stg(Register r1, int64_t d2, Register b2); 2244 inline void z_lgf(Register r1, int64_t d2, Register b2); 2245 inline void z_lgh(Register r1, int64_t d2, Register b2); 2246 inline void z_llgh(Register r1, int64_t d2, Register b2); 2247 inline void z_llgf(Register r1, int64_t d2, Register b2); 2248 inline void z_lgb(Register r1, int64_t d2, Register b2); 2249 inline void z_cl( Register r1, int64_t d2, Register b2); 2250 inline void z_c(Register r1, int64_t d2, Register b2); 2251 inline void z_cg(Register r1, int64_t d2, Register b2); 2252 inline void z_sh(Register r1, int64_t d2, Register b2); 2253 inline void z_shy(Register r1, int64_t d2, Register b2); 2254 inline void z_ste(FloatRegister r1, int64_t d2, Register b2); 2255 inline void z_std(FloatRegister r1, int64_t d2, Register b2); 2256 inline void z_stdy(FloatRegister r1, int64_t d2, Register b2); 2257 inline void z_stey(FloatRegister r1, int64_t d2, Register b2); 2258 inline void z_ld(FloatRegister r1, int64_t d2, Register b2); 2259 inline void z_ldy(FloatRegister r1, int64_t d2, Register b2); 2260 inline void z_le(FloatRegister r1, int64_t d2, Register b2); 2261 inline void z_ley(FloatRegister r1, int64_t d2, Register b2); 2262 2263 inline void z_agf(Register r1, int64_t d2, Register b2); 2264 2265 inline void z_exrl(Register r1, Label& L); 2266 inline void z_larl(Register r1, Label& L); 2267 inline void z_bru( Label& L); 2268 inline void z_brul(Label& L); 2269 inline void z_brul(address a); 2270 inline void z_brh( Label& L); 2271 inline void z_brl( Label& L); 2272 inline void z_bre( Label& L); 2273 inline void z_brnh(Label& L); 2274 inline void z_brnl(Label& L); 2275 inline void z_brne(Label& L); 2276 inline void z_brz( Label& L); 2277 inline void z_brnz(Label& L); 2278 inline void z_brnaz(Label& L); 2279 inline void z_braz(Label& L); 2280 inline void z_brnp(Label& L); 2281 2282 inline void z_btrue( Label& L); 2283 inline void z_bfalse(Label& L); 2284 2285 inline void z_brno( Label& L); 2286 2287 2288 inline void z_basr(Register r1, Register r2); 2289 inline void z_brasl(Register r1, address a); 2290 inline void z_brct(Register r1, address a); 2291 inline void z_brct(Register r1, Label& L); 2292 2293 inline void z_brxh(Register r1, Register r3, address a); 2294 inline void z_brxh(Register r1, Register r3, Label& L); 2295 2296 inline void z_brxle(Register r1, Register r3, address a); 2297 inline void z_brxle(Register r1, Register r3, Label& L); 2298 2299 inline void z_brxhg(Register r1, Register r3, address a); 2300 inline void z_brxhg(Register r1, Register r3, Label& L); 2301 2302 inline void z_brxlg(Register r1, Register r3, address a); 2303 inline void z_brxlg(Register r1, Register r3, Label& L); 2304 2305 // Ppopulation count intrinsics. 2306 inline void z_flogr(Register r1, Register r2); // find leftmost one 2307 inline void z_popcnt(Register r1, Register r2); // population count 2308 inline void z_ahhhr(Register r1, Register r2, Register r3); // ADD halfword high high 2309 inline void z_ahhlr(Register r1, Register r2, Register r3); // ADD halfword high low 2310 2311 inline void z_tam(); 2312 inline void z_stck(int64_t d2, Register b2); 2313 inline void z_stckf(int64_t d2, Register b2); 2314 inline void z_stmg(Register r1, Register r3, int64_t d2, Register b2); 2315 inline void z_lmg(Register r1, Register r3, int64_t d2, Register b2); 2316 2317 inline void z_cs( Register r1, Register r3, int64_t d2, Register b2); 2318 inline void z_csy(Register r1, Register r3, int64_t d2, Register b2); 2319 inline void z_csg(Register r1, Register r3, int64_t d2, Register b2); 2320 inline void z_cs( Register r1, Register r3, const Address& a); 2321 inline void z_csy(Register r1, Register r3, const Address& a); 2322 inline void z_csg(Register r1, Register r3, const Address& a); 2323 2324 inline void z_cvd(Register r1, int64_t d2, Register x2, Register b2); 2325 inline void z_cvdg(Register r1, int64_t d2, Register x2, Register b2); 2326 inline void z_cvd(Register r1, int64_t d2, Register b2); 2327 inline void z_cvdg(Register r1, int64_t d2, Register b2); 2328 2329 // Instruction queries: 2330 // instruction properties and recognize emitted instructions 2331 // =========================================================== 2332 2333 static int nop_size() { return 2; } 2334 2335 static int z_brul_size() { return 6; } 2336 2337 static bool is_z_basr(short x) { 2338 return (BASR_ZOPC == (x & BASR_MASK)); 2339 } 2340 static bool is_z_algr(long x) { 2341 return (ALGR_ZOPC == (x & RRE_MASK)); 2342 } 2343 static bool is_z_lb(long x) { 2344 return (LB_ZOPC == (x & LB_MASK)); 2345 } 2346 static bool is_z_lh(int x) { 2347 return (LH_ZOPC == (x & LH_MASK)); 2348 } 2349 static bool is_z_l(int x) { 2350 return (L_ZOPC == (x & L_MASK)); 2351 } 2352 static bool is_z_lgr(long x) { 2353 return (LGR_ZOPC == (x & RRE_MASK)); 2354 } 2355 static bool is_z_ly(long x) { 2356 return (LY_ZOPC == (x & LY_MASK)); 2357 } 2358 static bool is_z_lg(long x) { 2359 return (LG_ZOPC == (x & LG_MASK)); 2360 } 2361 static bool is_z_llgh(long x) { 2362 return (LLGH_ZOPC == (x & LLGH_MASK)); 2363 } 2364 static bool is_z_llgf(long x) { 2365 return (LLGF_ZOPC == (x & LLGF_MASK)); 2366 } 2367 static bool is_z_le(int x) { 2368 return (LE_ZOPC == (x & LE_MASK)); 2369 } 2370 static bool is_z_ld(int x) { 2371 return (LD_ZOPC == (x & LD_MASK)); 2372 } 2373 static bool is_z_st(int x) { 2374 return (ST_ZOPC == (x & ST_MASK)); 2375 } 2376 static bool is_z_stc(int x) { 2377 return (STC_ZOPC == (x & STC_MASK)); 2378 } 2379 static bool is_z_stg(long x) { 2380 return (STG_ZOPC == (x & STG_MASK)); 2381 } 2382 static bool is_z_sth(int x) { 2383 return (STH_ZOPC == (x & STH_MASK)); 2384 } 2385 static bool is_z_ste(int x) { 2386 return (STE_ZOPC == (x & STE_MASK)); 2387 } 2388 static bool is_z_std(int x) { 2389 return (STD_ZOPC == (x & STD_MASK)); 2390 } 2391 static bool is_z_slag(long x) { 2392 return (SLAG_ZOPC == (x & SLAG_MASK)); 2393 } 2394 static bool is_z_tmy(long x) { 2395 return (TMY_ZOPC == (x & TMY_MASK)); 2396 } 2397 static bool is_z_tm(long x) { 2398 return ((unsigned int)TM_ZOPC == (x & (unsigned int)TM_MASK)); 2399 } 2400 static bool is_z_bcr(long x) { 2401 return (BCR_ZOPC == (x & BCR_MASK)); 2402 } 2403 static bool is_z_nop(long x) { 2404 return is_z_bcr(x) && ((x & 0x00ff) == 0); 2405 } 2406 static bool is_z_nop(address x) { 2407 return is_z_nop(* (short *) x); 2408 } 2409 static bool is_z_br(long x) { 2410 return is_z_bcr(x) && ((x & 0x00f0) == 0x00f0); 2411 } 2412 static bool is_z_brc(long x, int cond) { 2413 return ((unsigned int)BRC_ZOPC == (x & BRC_MASK)) && ((cond<<20) == (x & 0x00f00000U)); 2414 } 2415 // Make use of lightweight sync. 2416 static bool is_z_sync_full(long x) { 2417 return is_z_bcr(x) && (((x & 0x00f0)>>4)==bcondFullSync) && ((x & 0x000f)==0x0000); 2418 } 2419 static bool is_z_sync_light(long x) { 2420 return is_z_bcr(x) && (((x & 0x00f0)>>4)==bcondLightSync) && ((x & 0x000f)==0x0000); 2421 } 2422 static bool is_z_sync(long x) { 2423 return is_z_sync_full(x) || is_z_sync_light(x); 2424 } 2425 2426 static bool is_z_brasl(long x) { 2427 return (BRASL_ZOPC == (x & BRASL_MASK)); 2428 } 2429 static bool is_z_brasl(address a) { 2430 long x = (*((long *)a))>>16; 2431 return is_z_brasl(x); 2432 } 2433 static bool is_z_larl(long x) { 2434 return (LARL_ZOPC == (x & LARL_MASK)); 2435 } 2436 static bool is_z_lgrl(long x) { 2437 return (LGRL_ZOPC == (x & LGRL_MASK)); 2438 } 2439 static bool is_z_lgrl(address a) { 2440 long x = (*((long *)a))>>16; 2441 return is_z_lgrl(x); 2442 } 2443 2444 static bool is_z_lghi(unsigned long x) { 2445 return (unsigned int)LGHI_ZOPC == (x & (unsigned int)LGHI_MASK); 2446 } 2447 2448 static bool is_z_llill(unsigned long x) { 2449 return (unsigned int)LLILL_ZOPC == (x & (unsigned int)LLI_MASK); 2450 } 2451 static bool is_z_llilh(unsigned long x) { 2452 return (unsigned int)LLILH_ZOPC == (x & (unsigned int)LLI_MASK); 2453 } 2454 static bool is_z_llihl(unsigned long x) { 2455 return (unsigned int)LLIHL_ZOPC == (x & (unsigned int)LLI_MASK); 2456 } 2457 static bool is_z_llihh(unsigned long x) { 2458 return (unsigned int)LLIHH_ZOPC == (x & (unsigned int)LLI_MASK); 2459 } 2460 static bool is_z_llilf(unsigned long x) { 2461 return LLILF_ZOPC == (x & LLIF_MASK); 2462 } 2463 static bool is_z_llihf(unsigned long x) { 2464 return LLIHF_ZOPC == (x & LLIF_MASK); 2465 } 2466 2467 static bool is_z_iill(unsigned long x) { 2468 return (unsigned int)IILL_ZOPC == (x & (unsigned int)II_MASK); 2469 } 2470 static bool is_z_iilh(unsigned long x) { 2471 return (unsigned int)IILH_ZOPC == (x & (unsigned int)II_MASK); 2472 } 2473 static bool is_z_iihl(unsigned long x) { 2474 return (unsigned int)IIHL_ZOPC == (x & (unsigned int)II_MASK); 2475 } 2476 static bool is_z_iihh(unsigned long x) { 2477 return (unsigned int)IIHH_ZOPC == (x & (unsigned int)II_MASK); 2478 } 2479 static bool is_z_iilf(unsigned long x) { 2480 return IILF_ZOPC == (x & IIF_MASK); 2481 } 2482 static bool is_z_iihf(unsigned long x) { 2483 return IIHF_ZOPC == (x & IIF_MASK); 2484 } 2485 2486 static inline bool is_equal(unsigned long inst, unsigned long idef); 2487 static inline bool is_equal(unsigned long inst, unsigned long idef, unsigned long imask); 2488 static inline bool is_equal(address iloc, unsigned long idef); 2489 static inline bool is_equal(address iloc, unsigned long idef, unsigned long imask); 2490 2491 static inline bool is_sigtrap_range_check(address pc); 2492 static inline bool is_sigtrap_zero_check(address pc); 2493 2494 //----------------- 2495 // memory barriers 2496 //----------------- 2497 // machine barrier instructions: 2498 // 2499 // - z_sync Two-way memory barrier, aka fence. 2500 // Only load-after-store-order is not guaranteed in the 2501 // z/Architecture memory model, i.e. only 'fence' is needed. 2502 // 2503 // semantic barrier instructions: 2504 // (as defined in orderAccess.hpp) 2505 // 2506 // - z_release orders Store|Store, empty implementation 2507 // Load|Store 2508 // - z_acquire orders Load|Store, empty implementation 2509 // Load|Load 2510 // - z_fence orders Store|Store, implemented as z_sync. 2511 // Load|Store, 2512 // Load|Load, 2513 // Store|Load 2514 // 2515 // For this implementation to be correct, we need H/W fixes on (very) old H/W: 2516 // For z990, it is Driver-55: MCL232 in the J13484 (i390/ML) Stream. 2517 // For z9, it is Driver-67: MCL065 in the G40963 (i390/ML) Stream. 2518 // These drivers are a prereq. Otherwise, memory synchronization will not work. 2519 2520 inline void z_sync(); 2521 inline void z_release(); 2522 inline void z_acquire(); 2523 inline void z_fence(); 2524 2525 // Creation 2526 Assembler(CodeBuffer* code) : AbstractAssembler(code) { } 2527 2528 }; 2529 2530 #endif // CPU_S390_VM_ASSEMBLER_S390_HPP