1 //
2 // Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2016 SAP SE. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24
25 // z/Architecture Architecture Description File
26
27 // Major contributions by AS, JL, LS.
28
29 //
30 // Following information is derived from private mail communication
31 // (Oct. 2011).
32 //
33 // General branch target alignment considerations
34 //
35 // z/Architecture does not imply a general branch target alignment requirement.
36 // There are side effects and side considerations, though, which may
37 // provide some performance benefit. These are:
38 // - Align branch target on octoword (32-byte) boundary
39 // On more recent models (from z9 on), I-fetch is done on a Octoword
40 // (32 bytes at a time) basis. To avoid I-fetching unnecessary
41 // instructions, branch targets should be 32-byte aligend. If this
42 // exact alingment cannot be achieved, having the branch target in
43 // the first doubleword still provides some benefit.
44 // - Avoid branch targets at the end of cache lines (> 64 bytes distance).
45 // Sequential instruction prefetching after the branch target starts
46 // immediately after having fetched the octoword containing the
47 // branch target. When I-fetching crosses a cache line, there may be
48 // a small stall. The worst case: the branch target (at the end of
49 // a cache line) is a L1 I-cache miss and the next line as well.
50 // Then, the entire target line must be filled first (to contine at the
51 // branch target). Only then can the next sequential line be filled.
52 // - Avoid multiple poorly predicted branches in a row.
53 //
54
55 //----------REGISTER DEFINITION BLOCK------------------------------------------
56 // This information is used by the matcher and the register allocator to
57 // describe individual registers and classes of registers within the target
58 // architecture.
59
60 register %{
61
62 //----------Architecture Description Register Definitions----------------------
63 // General Registers
64 // "reg_def" name (register save type, C convention save type,
65 // ideal register type, encoding);
66 //
67 // Register Save Types:
68 //
69 // NS = No-Save: The register allocator assumes that these registers
70 // can be used without saving upon entry to the method, &
71 // that they do not need to be saved at call sites.
72 //
73 // SOC = Save-On-Call: The register allocator assumes that these registers
74 // can be used without saving upon entry to the method,
75 // but that they must be saved at call sites.
76 //
77 // SOE = Save-On-Entry: The register allocator assumes that these registers
78 // must be saved before using them upon entry to the
79 // method, but they do not need to be saved at call sites.
80 //
81 // AS = Always-Save: The register allocator assumes that these registers
82 // must be saved before using them upon entry to the
83 // method, & that they must be saved at call sites.
84 //
85 // Ideal Register Type is used to determine how to save & restore a
86 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
87 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
88 //
89 // The encoding number is the actual bit-pattern placed into the opcodes.
90
91 // z/Architecture register definitions, based on the z/Architecture Principles
92 // of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement,
93 // 5th Edition, March 2001.
94 //
95 // For each 64-bit register we must define two registers: the register
96 // itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half',
97 // e.g. Z_R3_H, which is needed by the allocator, but is not used
98 // for stores, loads, etc.
99
100 // Integer/Long Registers
101 // ----------------------------
102
103 // z/Architecture has 16 64-bit integer registers.
104
105 // types: v = volatile, nv = non-volatile, s = system
106 reg_def Z_R0 (SOC, SOC, Op_RegI, 0, Z_R0->as_VMReg()); // v scratch1
107 reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next());
108 reg_def Z_R1 (SOC, SOC, Op_RegI, 1, Z_R1->as_VMReg()); // v scratch2
109 reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next());
110 reg_def Z_R2 (SOC, SOC, Op_RegI, 2, Z_R2->as_VMReg()); // v iarg1 & iret
111 reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next());
112 reg_def Z_R3 (SOC, SOC, Op_RegI, 3, Z_R3->as_VMReg()); // v iarg2
113 reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next());
114 reg_def Z_R4 (SOC, SOC, Op_RegI, 4, Z_R4->as_VMReg()); // v iarg3
115 reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next());
116 reg_def Z_R5 (SOC, SOC, Op_RegI, 5, Z_R5->as_VMReg()); // v iarg4
117 reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next());
118 reg_def Z_R6 (SOC, SOE, Op_RegI, 6, Z_R6->as_VMReg()); // v iarg5
119 reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next());
120 reg_def Z_R7 (SOC, SOE, Op_RegI, 7, Z_R7->as_VMReg());
121 reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next());
122 reg_def Z_R8 (SOC, SOE, Op_RegI, 8, Z_R8->as_VMReg());
123 reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next());
124 reg_def Z_R9 (SOC, SOE, Op_RegI, 9, Z_R9->as_VMReg());
125 reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next());
126 reg_def Z_R10 (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg());
127 reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next());
128 reg_def Z_R11 (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg());
129 reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next());
130 reg_def Z_R12 (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg());
131 reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next());
132 reg_def Z_R13 (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg());
133 reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next());
134 reg_def Z_R14 (NS, NS, Op_RegI, 14, Z_R14->as_VMReg()); // s return_pc
135 reg_def Z_R14_H(NS, NS, Op_RegI, 99, Z_R14->as_VMReg()->next());
136 reg_def Z_R15 (NS, NS, Op_RegI, 15, Z_R15->as_VMReg()); // s SP
137 reg_def Z_R15_H(NS, NS, Op_RegI, 99, Z_R15->as_VMReg()->next());
138
139 // Float/Double Registers
140
141 // The rules of ADL require that double registers be defined in pairs.
142 // Each pair must be two 32-bit values, but not necessarily a pair of
143 // single float registers. In each pair, ADLC-assigned register numbers
144 // must be adjacent, with the lower number even. Finally, when the
145 // CPU stores such a register pair to memory, the word associated with
146 // the lower ADLC-assigned number must be stored to the lower address.
147
148 // z/Architecture has 16 64-bit floating-point registers. Each can store a single
149 // or double precision floating-point value.
150
151 // types: v = volatile, nv = non-volatile, s = system
152 reg_def Z_F0 (SOC, SOC, Op_RegF, 0, Z_F0->as_VMReg()); // v farg1 & fret
153 reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next());
154 reg_def Z_F1 (SOC, SOC, Op_RegF, 1, Z_F1->as_VMReg());
155 reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next());
156 reg_def Z_F2 (SOC, SOC, Op_RegF, 2, Z_F2->as_VMReg()); // v farg2
157 reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next());
158 reg_def Z_F3 (SOC, SOC, Op_RegF, 3, Z_F3->as_VMReg());
159 reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next());
160 reg_def Z_F4 (SOC, SOC, Op_RegF, 4, Z_F4->as_VMReg()); // v farg3
161 reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next());
162 reg_def Z_F5 (SOC, SOC, Op_RegF, 5, Z_F5->as_VMReg());
163 reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next());
164 reg_def Z_F6 (SOC, SOC, Op_RegF, 6, Z_F6->as_VMReg());
165 reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next());
166 reg_def Z_F7 (SOC, SOC, Op_RegF, 7, Z_F7->as_VMReg());
167 reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next());
168 reg_def Z_F8 (SOC, SOE, Op_RegF, 8, Z_F8->as_VMReg());
169 reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next());
170 reg_def Z_F9 (SOC, SOE, Op_RegF, 9, Z_F9->as_VMReg());
171 reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next());
172 reg_def Z_F10 (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg());
173 reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next());
174 reg_def Z_F11 (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg());
175 reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next());
176 reg_def Z_F12 (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg());
177 reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next());
178 reg_def Z_F13 (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg());
179 reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next());
180 reg_def Z_F14 (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg());
181 reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next());
182 reg_def Z_F15 (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg());
183 reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next());
184
185
186 // Special Registers
187
188 // Condition Codes Flag Registers
189
190 // z/Architecture has the PSW (program status word) that contains
191 // (among other information) the condition code. We treat this
192 // part of the PSW as a condition register CR. It consists of 4
193 // bits. Floating point instructions influence the same condition register CR.
194
195 reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg()); // volatile
196
197
198 // Specify priority of register selection within phases of register
199 // allocation. Highest priority is first. A useful heuristic is to
200 // give registers a low priority when they are required by machine
201 // instructions, and choose no-save registers before save-on-call, and
202 // save-on-call before save-on-entry. Registers which participate in
203 // fix calling sequences should come last. Registers which are used
204 // as pairs must fall on an even boundary.
205
206 // It's worth about 1% on SPEC geomean to get this right.
207
208 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
209 // in adGlobals_s390.hpp which defines the <register>_num values, e.g.
210 // Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not)
211 // the same as Z_R3->encoding()! Furthermore, we cannot make any
212 // assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num.
213 // Additionally, the function
214 // static enum RC rc_class(OptoReg::Name reg)
215 // maps a given <register>_num value to its chunk type (except for flags)
216 // and its current implementation relies on chunk0 and chunk1 having a
217 // size of 64 each.
218
219 alloc_class chunk0(
220 // chunk0 contains *all* 32 integer registers halves.
221
222 // potential SOE regs
223 Z_R13,Z_R13_H,
224 Z_R12,Z_R12_H,
225 Z_R11,Z_R11_H,
226 Z_R10,Z_R10_H,
227
228 Z_R9,Z_R9_H,
229 Z_R8,Z_R8_H,
230 Z_R7,Z_R7_H,
231
232 Z_R1,Z_R1_H,
233 Z_R0,Z_R0_H,
234
235 // argument registers
236 Z_R6,Z_R6_H,
237 Z_R5,Z_R5_H,
238 Z_R4,Z_R4_H,
239 Z_R3,Z_R3_H,
240 Z_R2,Z_R2_H,
241
242 // special registers
243 Z_R14,Z_R14_H,
244 Z_R15,Z_R15_H
245 );
246
247 alloc_class chunk1(
248 // Chunk1 contains *all* 64 floating-point registers halves.
249
250 Z_F15,Z_F15_H,
251 Z_F14,Z_F14_H,
252 Z_F13,Z_F13_H,
253 Z_F12,Z_F12_H,
254 Z_F11,Z_F11_H,
255 Z_F10,Z_F10_H,
256 Z_F9,Z_F9_H,
257 Z_F8,Z_F8_H,
258 // scratch register
259 Z_F7,Z_F7_H,
260 Z_F5,Z_F5_H,
261 Z_F3,Z_F3_H,
262 Z_F1,Z_F1_H,
263 // argument registers
264 Z_F6,Z_F6_H,
265 Z_F4,Z_F4_H,
266 Z_F2,Z_F2_H,
267 Z_F0,Z_F0_H
268 );
269
270 alloc_class chunk2(
271 Z_CR
272 );
273
274
275 //-------Architecture Description Register Classes-----------------------
276
277 // Several register classes are automatically defined based upon
278 // information in this architecture description.
279
280 // 1) reg_class inline_cache_reg (as defined in frame section)
281 // 2) reg_class compiler_method_oop_reg (as defined in frame section)
282 // 2) reg_class interpreter_method_oop_reg (as defined in frame section)
283 // 3) reg_class stack_slots(/* one chunk of stack-based "registers" */)
284
285 // Integer Register Classes
286 reg_class z_int_reg(
287 /*Z_R0*/ // R0
288 /*Z_R1*/
289 Z_R2,
290 Z_R3,
291 Z_R4,
292 Z_R5,
293 Z_R6,
294 Z_R7,
295 /*Z_R8,*/ // Z_thread
296 Z_R9,
297 Z_R10,
298 Z_R11,
299 Z_R12,
300 Z_R13
301 /*Z_R14*/ // return_pc
302 /*Z_R15*/ // SP
303 );
304
305 reg_class z_no_odd_int_reg(
306 /*Z_R0*/ // R0
307 /*Z_R1*/
308 Z_R2,
309 Z_R3,
310 Z_R4,
311 /*Z_R5,*/ // odd part of fix register pair
312 Z_R6,
313 Z_R7,
314 /*Z_R8,*/ // Z_thread
315 Z_R9,
316 Z_R10,
317 Z_R11,
318 Z_R12,
319 Z_R13
320 /*Z_R14*/ // return_pc
321 /*Z_R15*/ // SP
322 );
323
324 reg_class z_no_arg_int_reg(
325 /*Z_R0*/ // R0
326 /*Z_R1*/ // scratch
327 /*Z_R2*/
328 /*Z_R3*/
329 /*Z_R4*/
330 /*Z_R5*/
331 /*Z_R6*/
332 Z_R7,
333 /*Z_R8*/ // Z_thread
334 Z_R9,
335 Z_R10,
336 Z_R11,
337 Z_R12,
338 Z_R13
339 /*Z_R14*/ // return_pc
340 /*Z_R15*/ // SP
341 );
342
343 reg_class z_rarg1_int_reg(Z_R2);
344 reg_class z_rarg2_int_reg(Z_R3);
345 reg_class z_rarg3_int_reg(Z_R4);
346 reg_class z_rarg4_int_reg(Z_R5);
347 reg_class z_rarg5_int_reg(Z_R6);
348
349 // Pointer Register Classes
350
351 // 64-bit build means 64-bit pointers means hi/lo pairs.
352
353 reg_class z_rarg5_ptrN_reg(Z_R6);
354
355 reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2);
356 reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3);
357 reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4);
358 reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5);
359 reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6);
360 reg_class z_thread_ptr_reg(Z_R8_H,Z_R8);
361
362 reg_class z_ptr_reg(
363 /*Z_R0_H,Z_R0*/ // R0
364 /*Z_R1_H,Z_R1*/
365 Z_R2_H,Z_R2,
366 Z_R3_H,Z_R3,
367 Z_R4_H,Z_R4,
368 Z_R5_H,Z_R5,
369 Z_R6_H,Z_R6,
370 Z_R7_H,Z_R7,
371 /*Z_R8_H,Z_R8,*/ // Z_thread
372 Z_R9_H,Z_R9,
373 Z_R10_H,Z_R10,
374 Z_R11_H,Z_R11,
375 Z_R12_H,Z_R12,
376 Z_R13_H,Z_R13
377 /*Z_R14_H,Z_R14*/ // return_pc
378 /*Z_R15_H,Z_R15*/ // SP
379 );
380
381 reg_class z_lock_ptr_reg(
382 /*Z_R0_H,Z_R0*/ // R0
383 /*Z_R1_H,Z_R1*/
384 Z_R2_H,Z_R2,
385 Z_R3_H,Z_R3,
386 Z_R4_H,Z_R4,
387 /*Z_R5_H,Z_R5,*/
388 /*Z_R6_H,Z_R6,*/
389 Z_R7_H,Z_R7,
390 /*Z_R8_H,Z_R8,*/ // Z_thread
391 Z_R9_H,Z_R9,
392 Z_R10_H,Z_R10,
393 Z_R11_H,Z_R11,
394 Z_R12_H,Z_R12,
395 Z_R13_H,Z_R13
396 /*Z_R14_H,Z_R14*/ // return_pc
397 /*Z_R15_H,Z_R15*/ // SP
398 );
399
400 reg_class z_no_arg_ptr_reg(
401 /*Z_R0_H,Z_R0*/ // R0
402 /*Z_R1_H,Z_R1*/ // scratch
403 /*Z_R2_H,Z_R2*/
404 /*Z_R3_H,Z_R3*/
405 /*Z_R4_H,Z_R4*/
406 /*Z_R5_H,Z_R5*/
407 /*Z_R6_H,Z_R6*/
408 Z_R7_H, Z_R7,
409 /*Z_R8_H,Z_R8*/ // Z_thread
410 Z_R9_H,Z_R9,
411 Z_R10_H,Z_R10,
412 Z_R11_H,Z_R11,
413 Z_R12_H,Z_R12,
414 Z_R13_H,Z_R13
415 /*Z_R14_H,Z_R14*/ // return_pc
416 /*Z_R15_H,Z_R15*/ // SP
417 );
418
419 // Special class for storeP instructions, which can store SP or RPC to
420 // TLS. (Note: Do not generalize this to "any_reg". If you add
421 // another register, such as FP, to this mask, the allocator may try
422 // to put a temp in it.)
423 // Register class for memory access base registers,
424 // This class is a superset of z_ptr_reg including Z_thread.
425 reg_class z_memory_ptr_reg(
426 /*Z_R0_H,Z_R0*/ // R0
427 /*Z_R1_H,Z_R1*/
428 Z_R2_H,Z_R2,
429 Z_R3_H,Z_R3,
430 Z_R4_H,Z_R4,
431 Z_R5_H,Z_R5,
432 Z_R6_H,Z_R6,
433 Z_R7_H,Z_R7,
434 Z_R8_H,Z_R8, // Z_thread
435 Z_R9_H,Z_R9,
436 Z_R10_H,Z_R10,
437 Z_R11_H,Z_R11,
438 Z_R12_H,Z_R12,
439 Z_R13_H,Z_R13
440 /*Z_R14_H,Z_R14*/ // return_pc
441 /*Z_R15_H,Z_R15*/ // SP
442 );
443
444 // Other special pointer regs.
445 reg_class z_r1_regP(Z_R1_H,Z_R1);
446 reg_class z_r9_regP(Z_R9_H,Z_R9);
447
448
449 // Long Register Classes
450
451 reg_class z_rarg1_long_reg(Z_R2_H,Z_R2);
452 reg_class z_rarg2_long_reg(Z_R3_H,Z_R3);
453 reg_class z_rarg3_long_reg(Z_R4_H,Z_R4);
454 reg_class z_rarg4_long_reg(Z_R5_H,Z_R5);
455 reg_class z_rarg5_long_reg(Z_R6_H,Z_R6);
456
457 // Longs in 1 register. Aligned adjacent hi/lo pairs.
458 reg_class z_long_reg(
459 /*Z_R0_H,Z_R0*/ // R0
460 /*Z_R1_H,Z_R1*/
461 Z_R2_H,Z_R2,
462 Z_R3_H,Z_R3,
463 Z_R4_H,Z_R4,
464 Z_R5_H,Z_R5,
465 Z_R6_H,Z_R6,
466 Z_R7_H,Z_R7,
467 /*Z_R8_H,Z_R8,*/ // Z_thread
468 Z_R9_H,Z_R9,
469 Z_R10_H,Z_R10,
470 Z_R11_H,Z_R11,
471 Z_R12_H,Z_R12,
472 Z_R13_H,Z_R13
473 /*Z_R14_H,Z_R14,*/ // return_pc
474 /*Z_R15_H,Z_R15*/ // SP
475 );
476
477
478 // Special Class for Condition Code Flags Register
479
480 reg_class z_condition_reg(
481 Z_CR
482 );
483
484 // Scratch register for late profiling. Callee saved.
485 reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2);
486
487
488 // Float Register Classes
489
490 reg_class z_flt_reg(
491 Z_F0,
492 /*Z_F1,*/ // scratch
493 Z_F2,
494 Z_F3,
495 Z_F4,
496 Z_F5,
497 Z_F6,
498 Z_F7,
499 Z_F8,
500 Z_F9,
501 Z_F10,
502 Z_F11,
503 Z_F12,
504 Z_F13,
505 Z_F14,
506 Z_F15
507 );
508 reg_class z_rscratch1_flt_reg(Z_F1);
509
510 // Double precision float registers have virtual `high halves' that
511 // are needed by the allocator.
512 reg_class z_dbl_reg(
513 Z_F0,Z_F0_H,
514 /*Z_F1,Z_F1_H,*/ // scratch
515 Z_F2,Z_F2_H,
516 Z_F3,Z_F3_H,
517 Z_F4,Z_F4_H,
518 Z_F5,Z_F5_H,
519 Z_F6,Z_F6_H,
520 Z_F7,Z_F7_H,
521 Z_F8,Z_F8_H,
522 Z_F9,Z_F9_H,
523 Z_F10,Z_F10_H,
524 Z_F11,Z_F11_H,
525 Z_F12,Z_F12_H,
526 Z_F13,Z_F13_H,
527 Z_F14,Z_F14_H,
528 Z_F15,Z_F15_H
529 );
530 reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H);
531
532 %}
533
534 //----------DEFINITION BLOCK---------------------------------------------------
535 // Define 'name --> value' mappings to inform the ADLC of an integer valued name.
536 // Current support includes integer values in the range [0, 0x7FFFFFFF].
537 // Format:
538 // int_def <name> (<int_value>, <expression>);
539 // Generated Code in ad_<arch>.hpp
540 // #define <name> (<expression>)
541 // // value == <int_value>
542 // Generated code in ad_<arch>.cpp adlc_verification()
543 // assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>");
544 //
545 definitions %{
546 // The default cost (of an ALU instruction).
547 int_def DEFAULT_COST ( 100, 100);
548 int_def DEFAULT_COST_LOW ( 80, 80);
549 int_def DEFAULT_COST_HIGH ( 120, 120);
550 int_def HUGE_COST (1000000, 1000000);
551
552 // Put an advantage on REG_MEM vs. MEM+REG_REG operations.
553 int_def ALU_REG_COST ( 100, DEFAULT_COST);
554 int_def ALU_MEMORY_COST ( 150, 150);
555
556 // Memory refs are twice as expensive as run-of-the-mill.
557 int_def MEMORY_REF_COST_HI ( 220, 2 * DEFAULT_COST+20);
558 int_def MEMORY_REF_COST ( 200, 2 * DEFAULT_COST);
559 int_def MEMORY_REF_COST_LO ( 180, 2 * DEFAULT_COST-20);
560
561 // Branches are even more expensive.
562 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
563 int_def CALL_COST ( 300, DEFAULT_COST * 3);
564 %}
565
566 source %{
567
568 #ifdef PRODUCT
569 #define BLOCK_COMMENT(str)
570 #define BIND(label) __ bind(label)
571 #else
572 #define BLOCK_COMMENT(str) __ block_comment(str)
573 #define BIND(label) __ bind(label); BLOCK_COMMENT(#label ":")
574 #endif
575
576 #define __ _masm.
577
578 #define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ? 4 : 6
579 #define Z_DISP3_SIZE 6
580
581 // Tertiary op of a LoadP or StoreP encoding.
582 #define REGP_OP true
583
584 // Given a register encoding, produce an Integer Register object.
585 static Register reg_to_register_object(int register_encoding);
586
587 // ****************************************************************************
588
589 // REQUIRED FUNCTIONALITY
590
591 // !!!!! Special hack to get all type of calls to specify the byte offset
592 // from the start of the call to the point where the return address
593 // will point.
594
595 int MachCallStaticJavaNode::ret_addr_offset() {
596 if (_method) {
597 return 8;
598 } else {
599 return MacroAssembler::call_far_patchable_ret_addr_offset();
600 }
601 }
602
603 int MachCallDynamicJavaNode::ret_addr_offset() {
604 // Consider size of receiver type profiling (C2 tiers).
605 int profile_receiver_type_size = 0;
606
607 int vtable_index = this->_vtable_index;
608 if (vtable_index == -4) {
609 return 14 + profile_receiver_type_size;
610 } else {
611 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
612 return 36 + profile_receiver_type_size;
613 }
614 }
615
616 int MachCallRuntimeNode::ret_addr_offset() {
617 return 12 + MacroAssembler::call_far_patchable_ret_addr_offset();
618 }
619
620 // Compute padding required for nodes which need alignment
621 //
622 // The addresses of the call instructions needs to be 4-byte aligned to
623 // ensure that they don't span a cache line so that they are atomically patchable.
624 // The actual calls get emitted at different offsets within the node emitters.
625 // ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted.
626
627 int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
628 return (0 - current_offset) & 2;
629 }
630
631 int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
632 return (6 - current_offset) & 2;
633 }
634
635 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
636 return (12 - current_offset) & 2;
637 }
638
639 int CallLeafDirectNode::compute_padding(int current_offset) const {
640 return (12 - current_offset) & 2;
641 }
642
643 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
644 return (12 - current_offset) & 2;
645 }
646
647 // Indicate if the safepoint node needs the polling page as an input.
648 // Since z/Architecture does not have absolute addressing, it does.
649 bool SafePointNode::needs_polling_address_input() {
650 return true;
651 }
652
653 void emit_nop(CodeBuffer &cbuf) {
654 MacroAssembler _masm(&cbuf);
655 __ z_nop();
656 }
657
658 // Emit an interrupt that is caught by the debugger (for debugging compiler).
659 void emit_break(CodeBuffer &cbuf) {
660 MacroAssembler _masm(&cbuf);
661 __ z_illtrap();
662 }
663
664 #if !defined(PRODUCT)
665 void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const {
666 os->print("TA");
667 }
668 #endif
669
670 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
671 emit_break(cbuf);
672 }
673
674 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
675 return MachNode::size(ra_);
676 }
677
678 static inline void z_emit16(CodeBuffer &cbuf, long value) {
679 // 32bit instructions may become sign extended.
680 assert(value >= 0, "unintended sign extension (int->long)");
681 assert(value < (1L << 16), "instruction too large");
682 *((unsigned short*)(cbuf.insts_end())) = (unsigned short)value;
683 cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned short));
684 }
685
686 static inline void z_emit32(CodeBuffer &cbuf, long value) {
687 // 32bit instructions may become sign extended.
688 assert(value < (1L << 32), "instruction too large");
689 *((unsigned int*)(cbuf.insts_end())) = (unsigned int)value;
690 cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned int));
691 }
692
693 static inline void z_emit48(CodeBuffer &cbuf, long value) {
694 // 32bit instructions may become sign extended.
695 assert(value >= 0, "unintended sign extension (int->long)");
696 assert(value < (1L << 48), "instruction too large");
697 value = value<<16;
698 memcpy(cbuf.insts_end(), (unsigned char*)&value, 6);
699 cbuf.set_insts_end(cbuf.insts_end() + 6);
700 }
701
702 static inline unsigned int z_emit_inst(CodeBuffer &cbuf, long value) {
703 if (value < 0) {
704 // There obviously has been an unintended sign extension (int->long). Revert it.
705 value = (long)((unsigned long)((unsigned int)value));
706 }
707
708 if (value < (1L << 16)) { // 2-byte instruction
709 z_emit16(cbuf, value);
710 return 2;
711 }
712
713 if (value < (1L << 32)) { // 4-byte instruction, might be unaligned store
714 z_emit32(cbuf, value);
715 return 4;
716 }
717
718 // 6-byte instruction, probably unaligned store.
719 z_emit48(cbuf, value);
720 return 6;
721 }
722
723 // Check effective address (at runtime) for required alignment.
724 static inline void z_assert_aligned(CodeBuffer &cbuf, int disp, Register index, Register base, int alignment) {
725 MacroAssembler _masm(&cbuf);
726
727 __ z_lay(Z_R0, disp, index, base);
728 __ z_nill(Z_R0, alignment-1);
729 __ z_brc(Assembler::bcondEqual, +3);
730 __ z_illtrap();
731 }
732
733 int emit_call_reloc(MacroAssembler &_masm, intptr_t entry_point, relocInfo::relocType rtype,
734 PhaseRegAlloc* ra_, bool is_native_call = false) {
735 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
736 address old_mark = __ inst_mark();
737 unsigned int start_off = __ offset();
738
739 if (is_native_call) {
740 ShouldNotReachHere();
741 }
742
743 if (rtype == relocInfo::runtime_call_w_cp_type) {
744 assert((__ offset() & 2) == 0, "misaligned emit_call_reloc");
745 address call_addr = __ call_c_opt((address)entry_point);
746 if (call_addr == NULL) {
747 Compile::current()->env()->record_out_of_memory_failure();
748 return -1;
749 }
750 } else {
751 assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type ||
752 rtype == relocInfo::static_call_type, "unexpected rtype");
753 __ relocate(rtype);
754 // BRASL must be prepended with a nop to identify it in the instruction stream.
755 __ z_nop();
756 __ z_brasl(Z_R14, (address)entry_point);
757 }
758
759 unsigned int ret_off = __ offset();
760
761 return (ret_off - start_off);
762 }
763
764 static int emit_call_reloc(MacroAssembler &_masm, intptr_t entry_point, RelocationHolder const& rspec) {
765 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
766 address old_mark = __ inst_mark();
767 unsigned int start_off = __ offset();
768
769 relocInfo::relocType rtype = rspec.type();
770 assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type,
771 "unexpected rtype");
772
773 __ relocate(rspec);
774 __ z_nop();
775 __ z_brasl(Z_R14, (address)entry_point);
776
777 unsigned int ret_off = __ offset();
778
779 return (ret_off - start_off);
780 }
781
782 //=============================================================================
783
784 const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask;
785 int Compile::ConstantTable::calculate_table_base_offset() const {
786 return 0; // absolute addressing, no offset
787 }
788
789 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
790 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
791 ShouldNotReachHere();
792 }
793
794 // Even with PC-relative TOC addressing, we still need this node.
795 // Float loads/stores do not support PC-relative addresses.
796 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
797 MacroAssembler _masm(&cbuf);
798 Register Rtoc = as_Register(ra_->get_encode(this));
799 __ load_toc(Rtoc);
800 }
801
802 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
803 // PCrelative TOC access.
804 return 6; // sizeof(LARL)
805 }
806
807 #if !defined(PRODUCT)
808 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
809 Register r = as_Register(ra_->get_encode(this));
810 st->print("LARL %s,&constant_pool # MachConstantBaseNode", r->name());
811 }
812 #endif
813
814 //=============================================================================
815
816 #if !defined(PRODUCT)
817 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
818 Compile* C = ra_->C;
819 st->print_cr("--- MachPrologNode ---");
820 st->print("\t");
821 for (int i = 0; i < OptoPrologueNops; i++) {
822 st->print_cr("NOP"); st->print("\t");
823 }
824
825 if (VerifyThread) {
826 st->print_cr("Verify_Thread");
827 st->print("\t");
828 }
829
830 long framesize = C->frame_size_in_bytes();
831 int bangsize = C->bang_size_in_bytes();
832
833 // Calls to C2R adapters often do not accept exceptional returns.
834 // We require that their callers must bang for them. But be
835 // careful, because some VM calls (such as call site linkage) can
836 // use several kilobytes of stack. But the stack safety zone should
837 // account for that. See bugs 4446381, 4468289, 4497237.
838 if (C->need_stack_bang(bangsize) && UseStackBanging) {
839 st->print_cr("# stack bang"); st->print("\t");
840 }
841 st->print_cr("push_frame %d", (int)-framesize);
842 st->print("\t");
843 }
844 #endif
845
846 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
847 Compile* C = ra_->C;
848 MacroAssembler _masm(&cbuf);
849
850 __ verify_thread();
851
852 size_t framesize = C->frame_size_in_bytes();
853 size_t bangsize = C->bang_size_in_bytes();
854
855 assert(framesize % wordSize == 0, "must preserve wordSize alignment");
856
857 // Calls to C2R adapters often do not accept exceptional returns.
858 // We require that their callers must bang for them. But be
859 // careful, because some VM calls (such as call site linkage) can
860 // use several kilobytes of stack. But the stack safety zone should
861 // account for that. See bugs 4446381, 4468289, 4497237.
862 if (C->need_stack_bang(bangsize) && UseStackBanging) {
863 __ generate_stack_overflow_check(bangsize);
864 }
865
866 assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!");
867 __ save_return_pc();
868
869 // The z/Architecture abi is already accounted for in `framesize' via the
870 // 'out_preserve_stack_slots' declaration.
871 __ push_frame((unsigned int)framesize/*includes JIT ABI*/);
872
873 if (C->has_mach_constant_base_node()) {
874 // NOTE: We set the table base offset here because users might be
875 // emitted before MachConstantBaseNode.
876 Compile::ConstantTable& constant_table = C->constant_table();
877 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
878 }
879 }
880
881 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
882 // Variable size. Determine dynamically.
883 return MachNode::size(ra_);
884 }
885
886 int MachPrologNode::reloc() const {
887 // Return number of relocatable values contained in this instruction.
888 return 1; // One reloc entry for load_const(toc).
889 }
890
891 //=============================================================================
892
893 #if !defined(PRODUCT)
894 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
895 os->print_cr("epilog");
896 os->print("\t");
897 if (do_polling() && ra_->C->is_method_compilation()) {
898 os->print_cr("load_from_polling_page Z_R1_scratch");
899 os->print("\t");
900 }
901 }
902 #endif
903
904 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
905 MacroAssembler _masm(&cbuf);
906 Compile* C = ra_->C;
907 __ verify_thread();
908
909 // If this does safepoint polling, then do it here.
910 bool need_polling = do_polling() && C->is_method_compilation();
911
912 // Pop frame, restore return_pc, and all stuff needed by interpreter.
913 // Pop frame by add instead of load (a penny saved is a penny got :-).
914 int frame_size_in_bytes = Assembler::align((C->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes);
915 int retPC_offset = frame_size_in_bytes + _z_abi16(return_pc);
916 if (Displacement::is_validDisp(retPC_offset)) {
917 __ z_lg(Z_R14, retPC_offset, Z_SP);
918 __ add2reg(Z_SP, frame_size_in_bytes);
919 } else {
920 __ add2reg(Z_SP, frame_size_in_bytes);
921 __ restore_return_pc();
922 }
923
924 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
925 __ reserved_stack_check(Z_R14);
926 }
927
928 // Touch the polling page.
929 // Part 1: get the page's address.
930 if (need_polling) {
931 AddressLiteral pp(os::get_polling_page());
932 __ load_const_optimized(Z_R1_scratch, pp);
933 }
934
935 // Touch the polling page,
936 // part 2: touch the page now.
937 if (need_polling) {
938 // We need to mark the code position where the load from the safepoint
939 // polling page was emitted as relocInfo::poll_return_type here.
940 __ relocate(relocInfo::poll_return_type);
941 __ load_from_polling_page(Z_R1_scratch);
942 }
943 }
944
945 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
946 // variable size. determine dynamically.
947 return MachNode::size(ra_);
948 }
949
950 int MachEpilogNode::reloc() const {
951 // Return number of relocatable values contained in this instruction.
952 return 1; // One for load_from_polling_page.
953 }
954
955 const Pipeline * MachEpilogNode::pipeline() const {
956 return MachNode::pipeline_class();
957 }
958
959 int MachEpilogNode::safepoint_offset() const {
960 assert(do_polling(), "no return for this epilog node");
961 return 0;
962 }
963
964 //=============================================================================
965
966 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack.
967 enum RC { rc_bad, rc_int, rc_float, rc_stack };
968
969 static enum RC rc_class(OptoReg::Name reg) {
970 // Return the register class for the given register. The given register
971 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
972 // enumeration in adGlobals_s390.hpp.
973
974 if (reg == OptoReg::Bad) {
975 return rc_bad;
976 }
977
978 // We have 32 integer register halves, starting at index 0.
979 if (reg < 32) {
980 return rc_int;
981 }
982
983 // We have 32 floating-point register halves, starting at index 32.
984 if (reg < 32+32) {
985 return rc_float;
986 }
987
988 // Between float regs & stack are the flags regs.
989 assert(reg >= OptoReg::stack0(), "blow up if spilling flags");
990 return rc_stack;
991 }
992
993 // Returns size as obtained from z_emit_instr.
994 static unsigned int z_ld_st_helper(CodeBuffer *cbuf, const char *op_str, unsigned long opcode,
995 int reg, int offset, bool do_print, outputStream *os) {
996
997 if (cbuf) {
998 if (opcode > (1L<<32)) {
999 return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 48) |
1000 Assembler::simm20(offset) | Assembler::reg(Z_R0, 12, 48) | Assembler::regz(Z_SP, 16, 48));
1001 } else {
1002 return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 32) |
1003 Assembler::uimm12(offset, 20, 32) | Assembler::reg(Z_R0, 12, 32) | Assembler::regz(Z_SP, 16, 32));
1004 }
1005 }
1006
1007 #if !defined(PRODUCT)
1008 if (do_print) {
1009 os->print("%s %s,#%d[,SP]\t # MachCopy spill code",op_str, Matcher::regName[reg], offset);
1010 }
1011 #endif
1012 return (opcode > (1L << 32)) ? 6 : 4;
1013 }
1014
1015 static unsigned int z_mvc_helper(CodeBuffer *cbuf, int len, int dst_off, int src_off, bool do_print, outputStream *os) {
1016 if (cbuf) {
1017 MacroAssembler _masm(cbuf);
1018 __ z_mvc(dst_off, len-1, Z_SP, src_off, Z_SP);
1019 }
1020
1021 #if !defined(PRODUCT)
1022 else if (do_print) {
1023 os->print("MVC %d(%d,SP),%d(SP)\t # MachCopy spill code",dst_off, len, src_off);
1024 }
1025 #endif
1026
1027 return 6;
1028 }
1029
1030 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *os) const {
1031 // Get registers to move.
1032 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1033 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1034 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1035 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1036
1037 enum RC src_hi_rc = rc_class(src_hi);
1038 enum RC src_lo_rc = rc_class(src_lo);
1039 enum RC dst_hi_rc = rc_class(dst_hi);
1040 enum RC dst_lo_rc = rc_class(dst_lo);
1041
1042 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1043 bool is64 = (src_hi_rc != rc_bad);
1044 assert(!is64 ||
1045 ((src_lo&1) == 0 && src_lo+1 == src_hi && (dst_lo&1) == 0 && dst_lo+1 == dst_hi),
1046 "expected aligned-adjacent pairs");
1047
1048 // Generate spill code!
1049
1050 if (src_lo == dst_lo && src_hi == dst_hi) {
1051 return 0; // Self copy, no move.
1052 }
1053
1054 int src_offset = ra_->reg2offset(src_lo);
1055 int dst_offset = ra_->reg2offset(dst_lo);
1056 bool print = !do_size;
1057 bool src12 = Immediate::is_uimm12(src_offset);
1058 bool dst12 = Immediate::is_uimm12(dst_offset);
1059
1060 const char *mnemo = NULL;
1061 unsigned long opc = 0;
1062
1063 // Memory->Memory Spill. Use Z_R0 to hold the value.
1064 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1065
1066 assert(!is64 || (src_hi_rc==rc_stack && dst_hi_rc==rc_stack),
1067 "expected same type of move for high parts");
1068
1069 if (src12 && dst12) {
1070 return z_mvc_helper(cbuf, is64 ? 8 : 4, dst_offset, src_offset, print, os);
1071 }
1072
1073 int r0 = Z_R0_num;
1074 if (is64) {
1075 return z_ld_st_helper(cbuf, "LG ", LG_ZOPC, r0, src_offset, print, os) +
1076 z_ld_st_helper(cbuf, "STG ", STG_ZOPC, r0, dst_offset, print, os);
1077 }
1078
1079 return z_ld_st_helper(cbuf, "LY ", LY_ZOPC, r0, src_offset, print, os) +
1080 z_ld_st_helper(cbuf, "STY ", STY_ZOPC, r0, dst_offset, print, os);
1081 }
1082
1083 // Check for float->int copy. Requires a trip through memory.
1084 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1085 Unimplemented(); // Unsafe, do not remove!
1086 }
1087
1088 // Check for integer reg-reg copy.
1089 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1090 if (cbuf) {
1091 MacroAssembler _masm(cbuf);
1092 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1093 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1094 __ z_lgr(Rdst, Rsrc);
1095 return 4;
1096 }
1097 #if !defined(PRODUCT)
1098 // else
1099 if (print) {
1100 os->print("LGR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1101 }
1102 #endif
1103 return 4;
1104 }
1105
1106 // Check for integer store.
1107 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1108 assert(!is64 || (src_hi_rc==rc_int && dst_hi_rc==rc_stack),
1109 "expected same type of move for high parts");
1110
1111 if (is64) {
1112 return z_ld_st_helper(cbuf, "STG ", STG_ZOPC, src_lo, dst_offset, print, os);
1113 }
1114
1115 // else
1116 mnemo = dst12 ? "ST " : "STY ";
1117 opc = dst12 ? ST_ZOPC : STY_ZOPC;
1118
1119 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
1120 }
1121
1122 // Check for integer load
1123 // Always load cOops zero-extended. That doesn't hurt int loads.
1124 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1125
1126 assert(!is64 || (dst_hi_rc==rc_int && src_hi_rc==rc_stack),
1127 "expected same type of move for high parts");
1128
1129 mnemo = is64 ? "LG " : "LLGF";
1130 opc = is64 ? LG_ZOPC : LLGF_ZOPC;
1131
1132 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
1133 }
1134
1135 // Check for float reg-reg copy.
1136 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1137 if (cbuf) {
1138 MacroAssembler _masm(cbuf);
1139 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1140 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1141 __ z_ldr(Rdst, Rsrc);
1142 return 2;
1143 }
1144 #if !defined(PRODUCT)
1145 // else
1146 if (print) {
1147 os->print("LDR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1148 }
1149 #endif
1150 return 2;
1151 }
1152
1153 // Check for float store.
1154 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1155 assert(!is64 || (src_hi_rc==rc_float && dst_hi_rc==rc_stack),
1156 "expected same type of move for high parts");
1157
1158 if (is64) {
1159 mnemo = dst12 ? "STD " : "STDY ";
1160 opc = dst12 ? STD_ZOPC : STDY_ZOPC;
1161 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
1162 }
1163 // else
1164
1165 mnemo = dst12 ? "STE " : "STEY ";
1166 opc = dst12 ? STE_ZOPC : STEY_ZOPC;
1167 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
1168 }
1169
1170 // Check for float load.
1171 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1172 assert(!is64 || (dst_hi_rc==rc_float && src_hi_rc==rc_stack),
1173 "expected same type of move for high parts");
1174
1175 if (is64) {
1176 mnemo = src12 ? "LD " : "LDY ";
1177 opc = src12 ? LD_ZOPC : LDY_ZOPC;
1178 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
1179 }
1180 // else
1181
1182 mnemo = src12 ? "LE " : "LEY ";
1183 opc = src12 ? LE_ZOPC : LEY_ZOPC;
1184 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
1185 }
1186
1187 // --------------------------------------------------------------------
1188 // Check for hi bits still needing moving. Only happens for misaligned
1189 // arguments to native calls.
1190 if (src_hi == dst_hi) {
1191 return 0; // Self copy, no move.
1192 }
1193
1194 assert(is64 && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1195 Unimplemented(); // Unsafe, do not remove!
1196
1197 return 0; // never reached, but make the compiler shut up!
1198 }
1199
1200 #if !defined(PRODUCT)
1201 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1202 if (ra_ && ra_->node_regs_max_index() > 0) {
1203 implementation(NULL, ra_, false, os);
1204 } else {
1205 if (req() == 2 && in(1)) {
1206 os->print("N%d = N%d\n", _idx, in(1)->_idx);
1207 } else {
1208 const char *c = "(";
1209 os->print("N%d = ", _idx);
1210 for (uint i = 1; i < req(); ++i) {
1211 os->print("%sN%d", c, in(i)->_idx);
1212 c = ", ";
1213 }
1214 os->print(")");
1215 }
1216 }
1217 }
1218 #endif
1219
1220 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1221 implementation(&cbuf, ra_, false, NULL);
1222 }
1223
1224 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1225 return implementation(NULL, ra_, true, NULL);
1226 }
1227
1228 //=============================================================================
1229
1230 #if !defined(PRODUCT)
1231 void MachNopNode::format(PhaseRegAlloc *, outputStream *os) const {
1232 os->print("NOP # pad for alignment (%d nops, %d bytes)", _count, _count*MacroAssembler::nop_size());
1233 }
1234 #endif
1235
1236 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ra_) const {
1237 MacroAssembler _masm(&cbuf);
1238
1239 int rem_space = 0;
1240 if (!(ra_->C->in_scratch_emit_size())) {
1241 rem_space = cbuf.insts()->remaining();
1242 if (rem_space <= _count*2 + 8) {
1243 tty->print("NopNode: _count = %3.3d, remaining space before = %d", _count, rem_space);
1244 }
1245 }
1246
1247 for (int i = 0; i < _count; i++) {
1248 __ z_nop();
1249 }
1250
1251 if (!(ra_->C->in_scratch_emit_size())) {
1252 if (rem_space <= _count*2 + 8) {
1253 int rem_space2 = cbuf.insts()->remaining();
1254 tty->print_cr(", after = %d", rem_space2);
1255 }
1256 }
1257 }
1258
1259 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1260 return 2 * _count;
1261 }
1262
1263 #if !defined(PRODUCT)
1264 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1265 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1266 if (ra_ && ra_->node_regs_max_index() > 0) {
1267 int reg = ra_->get_reg_first(this);
1268 os->print("ADDHI %s, SP, %d\t//box node", Matcher::regName[reg], offset);
1269 } else {
1270 os->print("ADDHI N%d = SP + %d\t// box node", _idx, offset);
1271 }
1272 }
1273 #endif
1274
1275 // Take care of the size function, if you make changes here!
1276 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1277 MacroAssembler _masm(&cbuf);
1278
1279 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1280 int reg = ra_->get_encode(this);
1281 __ z_lay(as_Register(reg), offset, Z_SP);
1282 }
1283
1284 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1285 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1286 return 6;
1287 }
1288
1289 %} // end source section
1290
1291 //----------SOURCE BLOCK-------------------------------------------------------
1292 // This is a block of C++ code which provides values, functions, and
1293 // definitions necessary in the rest of the architecture description
1294
1295 source_hpp %{
1296
1297 // Header information of the source block.
1298 // Method declarations/definitions which are used outside
1299 // the ad-scope can conveniently be defined here.
1300 //
1301 // To keep related declarations/definitions/uses close together,
1302 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
1303
1304 //--------------------------------------------------------------
1305 // Used for optimization in Compile::Shorten_branches
1306 //--------------------------------------------------------------
1307
1308 class CallStubImpl {
1309 public:
1310
1311 // call trampolines
1312 // Size of call trampoline stub. For add'l comments, see size_java_to_interp().
1313 static uint size_call_trampoline() {
1314 return 0; // no call trampolines on this platform
1315 }
1316
1317 // call trampolines
1318 // Number of relocations needed by a call trampoline stub.
1319 static uint reloc_call_trampoline() {
1320 return 0; // No call trampolines on this platform.
1321 }
1322 };
1323
1324 %} // end source_hpp section
1325
1326 source %{
1327
1328 #if !defined(PRODUCT)
1329 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1330 os->print_cr("---- MachUEPNode ----");
1331 os->print_cr("\tTA");
1332 os->print_cr("\tload_const Z_R1, SharedRuntime::get_ic_miss_stub()");
1333 os->print_cr("\tBR(Z_R1)");
1334 os->print_cr("\tTA # pad with illtraps");
1335 os->print_cr("\t...");
1336 os->print_cr("\tTA");
1337 os->print_cr("\tLTGR Z_R2, Z_R2");
1338 os->print_cr("\tBRU ic_miss");
1339 }
1340 #endif
1341
1342 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1343 MacroAssembler _masm(&cbuf);
1344 const int ic_miss_offset = 2;
1345
1346 // Inline_cache contains a klass.
1347 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
1348 // ARG1 is the receiver oop.
1349 Register R2_receiver = Z_ARG1;
1350 int klass_offset = oopDesc::klass_offset_in_bytes();
1351 AddressLiteral icmiss(SharedRuntime::get_ic_miss_stub());
1352 Register R1_ic_miss_stub_addr = Z_R1_scratch;
1353
1354 // Null check of receiver.
1355 // This is the null check of the receiver that actually should be
1356 // done in the caller. It's here because in case of implicit null
1357 // checks we get it for free.
1358 assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()),
1359 "second word in oop should not require explicit null check.");
1360 if (!ImplicitNullChecks) {
1361 Label valid;
1362 if (VM_Version::has_CompareBranch()) {
1363 __ z_cgij(R2_receiver, 0, Assembler::bcondNotEqual, valid);
1364 } else {
1365 __ z_ltgr(R2_receiver, R2_receiver);
1366 __ z_bre(valid);
1367 }
1368 // The ic_miss_stub will handle the null pointer exception.
1369 __ load_const_optimized(R1_ic_miss_stub_addr, icmiss);
1370 __ z_br(R1_ic_miss_stub_addr);
1371 __ bind(valid);
1372 }
1373
1374 // Check whether this method is the proper implementation for the class of
1375 // the receiver (ic miss check).
1376 {
1377 Label valid;
1378 // Compare cached class against klass from receiver.
1379 // This also does an implicit null check!
1380 __ compare_klass_ptr(ic_klass, klass_offset, R2_receiver, false);
1381 __ z_bre(valid);
1382 // The inline cache points to the wrong method. Call the
1383 // ic_miss_stub to find the proper method.
1384 __ load_const_optimized(R1_ic_miss_stub_addr, icmiss);
1385 __ z_br(R1_ic_miss_stub_addr);
1386 __ bind(valid);
1387 }
1388
1389 }
1390
1391 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1392 // Determine size dynamically.
1393 return MachNode::size(ra_);
1394 }
1395
1396 //=============================================================================
1397
1398 %} // interrupt source section
1399
1400 source_hpp %{ // Header information of the source block.
1401
1402 class HandlerImpl {
1403 public:
1404
1405 static int emit_exception_handler(CodeBuffer &cbuf);
1406 static int emit_deopt_handler(CodeBuffer& cbuf);
1407
1408 static uint size_exception_handler() {
1409 return NativeJump::max_instruction_size();
1410 }
1411
1412 static uint size_deopt_handler() {
1413 return NativeCall::max_instruction_size();
1414 }
1415 };
1416
1417 %} // end source_hpp section
1418
1419 source %{
1420
1421 // This exception handler code snippet is placed after the method's
1422 // code. It is the return point if an exception occurred. it jumps to
1423 // the exception blob.
1424 //
1425 // If the method gets deoptimized, the method and this code snippet
1426 // get patched.
1427 //
1428 // 1) Trampoline code gets patched into the end of this exception
1429 // handler. the trampoline code jumps to the deoptimization blob.
1430 //
1431 // 2) The return address in the method's code will get patched such
1432 // that it jumps to the trampoline.
1433 //
1434 // 3) The handler will get patched such that it does not jump to the
1435 // exception blob, but to an entry in the deoptimization blob being
1436 // aware of the exception.
1437 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
1438 Register temp_reg = Z_R1;
1439 MacroAssembler _masm(&cbuf);
1440
1441 address base = __ start_a_stub(size_exception_handler());
1442 if (base == NULL) {
1443 return 0; // CodeBuffer::expand failed
1444 }
1445
1446 int offset = __ offset();
1447 // Use unconditional pc-relative jump with 32-bit range here.
1448 __ load_const_optimized(temp_reg, (address)OptoRuntime::exception_blob()->content_begin());
1449 __ z_br(temp_reg);
1450
1451 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1452
1453 __ end_a_stub();
1454
1455 return offset;
1456 }
1457
1458 // Emit deopt handler code.
1459 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1460 MacroAssembler _masm(&cbuf);
1461 address base = __ start_a_stub(size_deopt_handler());
1462
1463 if (base == NULL) {
1464 return 0; // CodeBuffer::expand failed
1465 }
1466
1467 int offset = __ offset();
1468
1469 // Size_deopt_handler() must be exact on zarch, so for simplicity
1470 // we do not use load_const_opt here.
1471 __ load_const(Z_R1, SharedRuntime::deopt_blob()->unpack());
1472 __ call(Z_R1);
1473 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
1474
1475 __ end_a_stub();
1476 return offset;
1477 }
1478
1479 //=============================================================================
1480
1481
1482 // Given a register encoding, produce an Integer Register object.
1483 static Register reg_to_register_object(int register_encoding) {
1484 assert(Z_R12->encoding() == Z_R12_enc, "wrong coding");
1485 return as_Register(register_encoding);
1486 }
1487
1488 const bool Matcher::match_rule_supported(int opcode) {
1489 if (!has_match_rule(opcode)) return false;
1490
1491 switch (opcode) {
1492 case Op_CountLeadingZerosI:
1493 case Op_CountLeadingZerosL:
1494 case Op_CountTrailingZerosI:
1495 case Op_CountTrailingZerosL:
1496 // Implementation requires FLOGR instruction, which is available since z9.
1497 return true;
1498
1499 case Op_ReverseBytesI:
1500 case Op_ReverseBytesL:
1501 return UseByteReverseInstruction;
1502
1503 // PopCount supported by H/W from z/Architecture G5 (z196) on.
1504 case Op_PopCountI:
1505 case Op_PopCountL:
1506 return UsePopCountInstruction && VM_Version::has_PopCount();
1507
1508 case Op_StrComp:
1509 return SpecialStringCompareTo;
1510 case Op_StrEquals:
1511 return SpecialStringEquals;
1512 case Op_StrIndexOf:
1513 case Op_StrIndexOfChar:
1514 return SpecialStringIndexOf;
1515
1516 case Op_GetAndAddI:
1517 case Op_GetAndAddL:
1518 return true;
1519 // return VM_Version::has_AtomicMemWithImmALUOps();
1520 case Op_GetAndSetI:
1521 case Op_GetAndSetL:
1522 case Op_GetAndSetP:
1523 case Op_GetAndSetN:
1524 return true; // General CAS implementation, always available.
1525
1526 default:
1527 return true; // Per default match rules are supported.
1528 // BUT: make sure match rule is not disabled by a false predicate!
1529 }
1530
1531 return true; // Per default match rules are supported.
1532 // BUT: make sure match rule is not disabled by a false predicate!
1533 }
1534
1535 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1536 // TODO
1537 // Identify extra cases that we might want to provide match rules for
1538 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen.
1539 bool ret_value = match_rule_supported(opcode);
1540 // Add rules here.
1541
1542 return ret_value; // Per default match rules are supported.
1543 }
1544
1545 int Matcher::regnum_to_fpu_offset(int regnum) {
1546 ShouldNotReachHere();
1547 return regnum - 32; // The FP registers are in the second chunk.
1548 }
1549
1550 const bool Matcher::has_predicated_vectors(void) {
1551 return false;
1552 }
1553
1554 const int Matcher::float_pressure(int default_pressure_threshold) {
1555 return default_pressure_threshold;
1556 }
1557
1558 const bool Matcher::convL2FSupported(void) {
1559 return true; // False means that conversion is done by runtime call.
1560 }
1561
1562 //----------SUPERWORD HELPERS----------------------------------------
1563
1564 // Vector width in bytes.
1565 const int Matcher::vector_width_in_bytes(BasicType bt) {
1566 assert(MaxVectorSize == 8, "");
1567 return 8;
1568 }
1569
1570 // Vector ideal reg.
1571 const int Matcher::vector_ideal_reg(int size) {
1572 assert(MaxVectorSize == 8 && size == 8, "");
1573 return Op_RegL;
1574 }
1575
1576 // Limits on vector size (number of elements) loaded into vector.
1577 const int Matcher::max_vector_size(const BasicType bt) {
1578 assert(is_java_primitive(bt), "only primitive type vectors");
1579 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1580 }
1581
1582 const int Matcher::min_vector_size(const BasicType bt) {
1583 return max_vector_size(bt); // Same as max.
1584 }
1585
1586 const int Matcher::vector_shift_count_ideal_reg(int size) {
1587 fatal("vector shift is not supported");
1588 return Node::NotAMachineReg;
1589 }
1590
1591 // z/Architecture does support misaligned store/load at minimal extra cost.
1592 const bool Matcher::misaligned_vectors_ok() {
1593 return true;
1594 }
1595
1596 // Not yet ported to z/Architecture.
1597 const bool Matcher::pass_original_key_for_aes() {
1598 return false;
1599 }
1600
1601 // RETURNS: whether this branch offset is short enough that a short
1602 // branch can be used.
1603 //
1604 // If the platform does not provide any short branch variants, then
1605 // this method should return `false' for offset 0.
1606 //
1607 // `Compile::Fill_buffer' will decide on basis of this information
1608 // whether to do the pass `Compile::Shorten_branches' at all.
1609 //
1610 // And `Compile::Shorten_branches' will decide on basis of this
1611 // information whether to replace particular branch sites by short
1612 // ones.
1613 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1614 // On zarch short branches use a 16 bit signed immediate that
1615 // is the pc-relative offset in halfword (= 2 bytes) units.
1616 return Assembler::is_within_range_of_RelAddr16((address)((long)offset), (address)0);
1617 }
1618
1619 const bool Matcher::isSimpleConstant64(jlong value) {
1620 // Probably always true, even if a temp register is required.
1621 return true;
1622 }
1623
1624 // Should correspond to setting above
1625 const bool Matcher::init_array_count_is_in_bytes = false;
1626
1627 // Suppress CMOVL. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet.
1628 const int Matcher::long_cmove_cost() { return ConditionalMoveLimit; }
1629
1630 // Suppress CMOVF. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet.
1631 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1632
1633 // Does the CPU require postalloc expand (see block.cpp for description of postalloc expand)?
1634 const bool Matcher::require_postalloc_expand = false;
1635
1636 // Do we need to mask the count passed to shift instructions or does
1637 // the cpu only look at the lower 5/6 bits anyway?
1638 // 32bit shifts mask in emitter, 64bit shifts need no mask.
1639 // Constant shift counts are handled in Ideal phase.
1640 const bool Matcher::need_masked_shift_count = false;
1641
1642 // Set this as clone_shift_expressions.
1643 bool Matcher::narrow_oop_use_complex_address() {
1644 if (Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0) return true;
1645 return false;
1646 }
1647
1648 bool Matcher::narrow_klass_use_complex_address() {
1649 NOT_LP64(ShouldNotCallThis());
1650 assert(UseCompressedClassPointers, "only for compressed klass code");
1651 // TODO HS25: z port if (MatchDecodeNodes) return true;
1652 return false;
1653 }
1654
1655 bool Matcher::const_oop_prefer_decode() {
1656 // Prefer ConN+DecodeN over ConP in simple compressed oops mode.
1657 return Universe::narrow_oop_base() == NULL;
1658 }
1659
1660 bool Matcher::const_klass_prefer_decode() {
1661 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1662 return Universe::narrow_klass_base() == NULL;
1663 }
1664
1665 // Is it better to copy float constants, or load them directly from memory?
1666 // Most RISCs will have to materialize an address into a
1667 // register first, so they would do better to copy the constant from stack.
1668 const bool Matcher::rematerialize_float_constants = false;
1669
1670 // If CPU can load and store mis-aligned doubles directly then no fixup is
1671 // needed. Else we split the double into 2 integer pieces and move it
1672 // piece-by-piece. Only happens when passing doubles into C code as the
1673 // Java calling convention forces doubles to be aligned.
1674 const bool Matcher::misaligned_doubles_ok = true;
1675
1676 // Advertise here if the CPU requires explicit rounding operations
1677 // to implement the UseStrictFP mode.
1678 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1679
1680 // Do floats take an entire double register or just half?
1681 //
1682 // A float in resides in a zarch double register. When storing it by
1683 // z_std, it cannot be restored in C-code by reloading it as a double
1684 // and casting it into a float afterwards.
1685 bool Matcher::float_in_double() { return false; }
1686
1687 // Do ints take an entire long register or just half?
1688 // The relevant question is how the int is callee-saved:
1689 // the whole long is written but de-opt'ing will have to extract
1690 // the relevant 32 bits.
1691 const bool Matcher::int_in_long = true;
1692
1693 // Constants for c2c and c calling conventions.
1694
1695 const MachRegisterNumbers z_iarg_reg[5] = {
1696 Z_R2_num, Z_R3_num, Z_R4_num, Z_R5_num, Z_R6_num
1697 };
1698
1699 const MachRegisterNumbers z_farg_reg[4] = {
1700 Z_F0_num, Z_F2_num, Z_F4_num, Z_F6_num
1701 };
1702
1703 const int z_num_iarg_registers = sizeof(z_iarg_reg) / sizeof(z_iarg_reg[0]);
1704
1705 const int z_num_farg_registers = sizeof(z_farg_reg) / sizeof(z_farg_reg[0]);
1706
1707 // Return whether or not this register is ever used as an argument. This
1708 // function is used on startup to build the trampoline stubs in generateOptoStub.
1709 // Registers not mentioned will be killed by the VM call in the trampoline, and
1710 // arguments in those registers not be available to the callee.
1711 bool Matcher::can_be_java_arg(int reg) {
1712 // We return true for all registers contained in z_iarg_reg[] and
1713 // z_farg_reg[] and their virtual halves.
1714 // We must include the virtual halves in order to get STDs and LDs
1715 // instead of STWs and LWs in the trampoline stubs.
1716
1717 if (reg == Z_R2_num || reg == Z_R2_H_num ||
1718 reg == Z_R3_num || reg == Z_R3_H_num ||
1719 reg == Z_R4_num || reg == Z_R4_H_num ||
1720 reg == Z_R5_num || reg == Z_R5_H_num ||
1721 reg == Z_R6_num || reg == Z_R6_H_num) {
1722 return true;
1723 }
1724
1725 if (reg == Z_F0_num || reg == Z_F0_H_num ||
1726 reg == Z_F2_num || reg == Z_F2_H_num ||
1727 reg == Z_F4_num || reg == Z_F4_H_num ||
1728 reg == Z_F6_num || reg == Z_F6_H_num) {
1729 return true;
1730 }
1731
1732 return false;
1733 }
1734
1735 bool Matcher::is_spillable_arg(int reg) {
1736 return can_be_java_arg(reg);
1737 }
1738
1739 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
1740 return false;
1741 }
1742
1743 // Register for DIVI projection of divmodI
1744 RegMask Matcher::divI_proj_mask() {
1745 return _Z_RARG4_INT_REG_mask;
1746 }
1747
1748 // Register for MODI projection of divmodI
1749 RegMask Matcher::modI_proj_mask() {
1750 return _Z_RARG3_INT_REG_mask;
1751 }
1752
1753 // Register for DIVL projection of divmodL
1754 RegMask Matcher::divL_proj_mask() {
1755 return _Z_RARG4_LONG_REG_mask;
1756 }
1757
1758 // Register for MODL projection of divmodL
1759 RegMask Matcher::modL_proj_mask() {
1760 return _Z_RARG3_LONG_REG_mask;
1761 }
1762
1763 // Copied from sparc.
1764 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1765 return RegMask();
1766 }
1767
1768 const bool Matcher::convi2l_type_required = true;
1769
1770 // Should the Matcher clone shifts on addressing modes, expecting them
1771 // to be subsumed into complex addressing expressions or compute them
1772 // into registers?
1773 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
1774 return clone_base_plus_offset_address(m, mstack, address_visited);
1775 }
1776
1777 void Compile::reshape_address(AddPNode* addp) {
1778 }
1779
1780 %} // source
1781
1782 //----------ENCODING BLOCK-----------------------------------------------------
1783 // This block specifies the encoding classes used by the compiler to output
1784 // byte streams. Encoding classes are parameterized macros used by
1785 // Machine Instruction Nodes in order to generate the bit encoding of the
1786 // instruction. Operands specify their base encoding interface with the
1787 // interface keyword. There are currently supported four interfaces,
1788 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1789 // operand to generate a function which returns its register number when
1790 // queried. CONST_INTER causes an operand to generate a function which
1791 // returns the value of the constant when queried. MEMORY_INTER causes an
1792 // operand to generate four functions which return the Base Register, the
1793 // Index Register, the Scale Value, and the Offset Value of the operand when
1794 // queried. COND_INTER causes an operand to generate six functions which
1795 // return the encoding code (ie - encoding bits for the instruction)
1796 // associated with each basic boolean condition for a conditional instruction.
1797 //
1798 // Instructions specify two basic values for encoding. Again, a function
1799 // is available to check if the constant displacement is an oop. They use the
1800 // ins_encode keyword to specify their encoding classes (which must be
1801 // a sequence of enc_class names, and their parameters, specified in
1802 // the encoding block), and they use the
1803 // opcode keyword to specify, in order, their primary, secondary, and
1804 // tertiary opcode. Only the opcode sections which a particular instruction
1805 // needs for encoding need to be specified.
1806 encode %{
1807 enc_class enc_unimplemented %{
1808 MacroAssembler _masm(&cbuf);
1809 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
1810 %}
1811
1812 enc_class enc_untested %{
1813 #ifdef ASSERT
1814 MacroAssembler _masm(&cbuf);
1815 __ untested("Untested mach node encoding in AD file.");
1816 #endif
1817 %}
1818
1819 enc_class z_rrform(iRegI dst, iRegI src) %{
1820 assert((($primary >> 14) & 0x03) == 0, "Instruction format error");
1821 assert( ($primary >> 16) == 0, "Instruction format error");
1822 z_emit16(cbuf, $primary |
1823 Assembler::reg($dst$$reg,8,16) |
1824 Assembler::reg($src$$reg,12,16));
1825 %}
1826
1827 enc_class z_rreform(iRegI dst1, iRegI src2) %{
1828 assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
1829 z_emit32(cbuf, $primary |
1830 Assembler::reg($dst1$$reg,24,32) |
1831 Assembler::reg($src2$$reg,28,32));
1832 %}
1833
1834 enc_class z_rrfform(iRegI dst1, iRegI src2, iRegI src3) %{
1835 assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
1836 z_emit32(cbuf, $primary |
1837 Assembler::reg($dst1$$reg,24,32) |
1838 Assembler::reg($src2$$reg,28,32) |
1839 Assembler::reg($src3$$reg,16,32));
1840 %}
1841
1842 enc_class z_riform_signed(iRegI dst, immI16 src) %{
1843 assert((($primary>>30) & 0x03) == 2, "Instruction format error");
1844 z_emit32(cbuf, $primary |
1845 Assembler::reg($dst$$reg,8,32) |
1846 Assembler::simm16($src$$constant,16,32));
1847 %}
1848
1849 enc_class z_riform_unsigned(iRegI dst, uimmI16 src) %{
1850 assert((($primary>>30) & 0x03) == 2, "Instruction format error");
1851 z_emit32(cbuf, $primary |
1852 Assembler::reg($dst$$reg,8,32) |
1853 Assembler::uimm16($src$$constant,16,32));
1854 %}
1855
1856 enc_class z_rieform_d(iRegI dst1, iRegI src3, immI src2) %{
1857 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
1858 z_emit48(cbuf, $primary |
1859 Assembler::reg($dst1$$reg,8,48) |
1860 Assembler::reg($src3$$reg,12,48) |
1861 Assembler::simm16($src2$$constant,16,48));
1862 %}
1863
1864 enc_class z_rilform_signed(iRegI dst, immL32 src) %{
1865 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
1866 z_emit48(cbuf, $primary |
1867 Assembler::reg($dst$$reg,8,48) |
1868 Assembler::simm32($src$$constant,16,48));
1869 %}
1870
1871 enc_class z_rilform_unsigned(iRegI dst, uimmL32 src) %{
1872 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
1873 z_emit48(cbuf, $primary |
1874 Assembler::reg($dst$$reg,8,48) |
1875 Assembler::uimm32($src$$constant,16,48));
1876 %}
1877
1878 enc_class z_rsyform_const(iRegI dst, iRegI src1, immI src2) %{
1879 z_emit48(cbuf, $primary |
1880 Assembler::reg($dst$$reg,8,48) |
1881 Assembler::reg($src1$$reg,12,48) |
1882 Assembler::simm20($src2$$constant));
1883 %}
1884
1885 enc_class z_rsyform_reg_reg(iRegI dst, iRegI src, iRegI shft) %{
1886 z_emit48(cbuf, $primary |
1887 Assembler::reg($dst$$reg,8,48) |
1888 Assembler::reg($src$$reg,12,48) |
1889 Assembler::reg($shft$$reg,16,48) |
1890 Assembler::simm20(0));
1891 %}
1892
1893 enc_class z_rxform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
1894 assert((($primary>>30) & 0x03) == 1, "Instruction format error");
1895 z_emit32(cbuf, $primary |
1896 Assembler::reg($dst$$reg,8,32) |
1897 Assembler::reg($src1$$reg,12,32) |
1898 Assembler::reg($src2$$reg,16,32) |
1899 Assembler::uimm12($con$$constant,20,32));
1900 %}
1901
1902 enc_class z_rxform_imm_reg(iRegL dst, immL con, iRegL src) %{
1903 assert((($primary>>30) & 0x03) == 1, "Instruction format error");
1904 z_emit32(cbuf, $primary |
1905 Assembler::reg($dst$$reg,8,32) |
1906 Assembler::reg($src$$reg,16,32) |
1907 Assembler::uimm12($con$$constant,20,32));
1908 %}
1909
1910 enc_class z_rxyform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
1911 z_emit48(cbuf, $primary |
1912 Assembler::reg($dst$$reg,8,48) |
1913 Assembler::reg($src1$$reg,12,48) |
1914 Assembler::reg($src2$$reg,16,48) |
1915 Assembler::simm20($con$$constant));
1916 %}
1917
1918 enc_class z_rxyform_imm_reg(iRegL dst, immL con, iRegL src) %{
1919 z_emit48(cbuf, $primary |
1920 Assembler::reg($dst$$reg,8,48) |
1921 Assembler::reg($src$$reg,16,48) |
1922 Assembler::simm20($con$$constant));
1923 %}
1924
1925 // Direct memory arithmetic.
1926 enc_class z_siyform(memoryRSY mem, immI8 src) %{
1927 int disp = $mem$$disp;
1928 Register base = reg_to_register_object($mem$$base);
1929 int con = $src$$constant;
1930
1931 assert(VM_Version::has_MemWithImmALUOps(), "unsupported CPU");
1932 z_emit_inst(cbuf, $primary |
1933 Assembler::regz(base,16,48) |
1934 Assembler::simm20(disp) |
1935 Assembler::simm8(con,8,48));
1936 %}
1937
1938 enc_class z_silform(memoryRS mem, immI16 src) %{
1939 z_emit_inst(cbuf, $primary |
1940 Assembler::regz(reg_to_register_object($mem$$base),16,48) |
1941 Assembler::uimm12($mem$$disp,20,48) |
1942 Assembler::simm16($src$$constant,32,48));
1943 %}
1944
1945 // Encoder for FP ALU reg/mem instructions (support only short displacements).
1946 enc_class z_form_rt_memFP(RegF dst, memoryRX mem) %{
1947 Register Ridx = $mem$$index$$Register;
1948 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
1949 if ($primary > (1L << 32)) {
1950 z_emit_inst(cbuf, $primary |
1951 Assembler::reg($dst$$reg, 8, 48) |
1952 Assembler::uimm12($mem$$disp, 20, 48) |
1953 Assembler::reg(Ridx, 12, 48) |
1954 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
1955 } else {
1956 z_emit_inst(cbuf, $primary |
1957 Assembler::reg($dst$$reg, 8, 32) |
1958 Assembler::uimm12($mem$$disp, 20, 32) |
1959 Assembler::reg(Ridx, 12, 32) |
1960 Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
1961 }
1962 %}
1963
1964 enc_class z_form_rt_mem(iRegI dst, memory mem) %{
1965 Register Ridx = $mem$$index$$Register;
1966 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
1967 if ($primary > (1L<<32)) {
1968 z_emit_inst(cbuf, $primary |
1969 Assembler::reg($dst$$reg, 8, 48) |
1970 Assembler::simm20($mem$$disp) |
1971 Assembler::reg(Ridx, 12, 48) |
1972 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
1973 } else {
1974 z_emit_inst(cbuf, $primary |
1975 Assembler::reg($dst$$reg, 8, 32) |
1976 Assembler::uimm12($mem$$disp, 20, 32) |
1977 Assembler::reg(Ridx, 12, 32) |
1978 Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
1979 }
1980 %}
1981
1982 enc_class z_form_rt_mem_opt(iRegI dst, memory mem) %{
1983 int isize = $secondary > 1L << 32 ? 48 : 32;
1984 Register Ridx = $mem$$index$$Register;
1985 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
1986
1987 if (Displacement::is_shortDisp((long)$mem$$disp)) {
1988 z_emit_inst(cbuf, $secondary |
1989 Assembler::reg($dst$$reg, 8, isize) |
1990 Assembler::uimm12($mem$$disp, 20, isize) |
1991 Assembler::reg(Ridx, 12, isize) |
1992 Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
1993 } else if (Displacement::is_validDisp((long)$mem$$disp)) {
1994 z_emit_inst(cbuf, $primary |
1995 Assembler::reg($dst$$reg, 8, 48) |
1996 Assembler::simm20($mem$$disp) |
1997 Assembler::reg(Ridx, 12, 48) |
1998 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
1999 } else {
2000 MacroAssembler _masm(&cbuf);
2001 __ load_const_optimized(Z_R1_scratch, $mem$$disp);
2002 if (Ridx != Z_R0) { __ z_agr(Z_R1_scratch, Ridx); }
2003 z_emit_inst(cbuf, $secondary |
2004 Assembler::reg($dst$$reg, 8, isize) |
2005 Assembler::uimm12(0, 20, isize) |
2006 Assembler::reg(Z_R1_scratch, 12, isize) |
2007 Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
2008 }
2009 %}
2010
2011 enc_class z_enc_brul(Label lbl) %{
2012 MacroAssembler _masm(&cbuf);
2013 Label* p = $lbl$$label;
2014
2015 // 'p' is `NULL' when this encoding class is used only to
2016 // determine the size of the encoded instruction.
2017 // Use a bound dummy label in that case.
2018 Label d;
2019 __ bind(d);
2020 Label& l = (NULL == p) ? d : *(p);
2021 __ z_brul(l);
2022 %}
2023
2024 enc_class z_enc_bru(Label lbl) %{
2025 MacroAssembler _masm(&cbuf);
2026 Label* p = $lbl$$label;
2027
2028 // 'p' is `NULL' when this encoding class is used only to
2029 // determine the size of the encoded instruction.
2030 // Use a bound dummy label in that case.
2031 Label d;
2032 __ bind(d);
2033 Label& l = (NULL == p) ? d : *(p);
2034 __ z_bru(l);
2035 %}
2036
2037 enc_class z_enc_branch_con_far(cmpOp cmp, Label lbl) %{
2038 MacroAssembler _masm(&cbuf);
2039 Label* p = $lbl$$label;
2040
2041 // 'p' is `NULL' when this encoding class is used only to
2042 // determine the size of the encoded instruction.
2043 // Use a bound dummy label in that case.
2044 Label d;
2045 __ bind(d);
2046 Label& l = (NULL == p) ? d : *(p);
2047 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2048 %}
2049
2050 enc_class z_enc_branch_con_short(cmpOp cmp, Label lbl) %{
2051 MacroAssembler _masm(&cbuf);
2052 Label* p = $lbl$$label;
2053
2054 // 'p' is `NULL' when this encoding class is used only to
2055 // determine the size of the encoded instruction.
2056 // Use a bound dummy label in that case.
2057 Label d;
2058 __ bind(d);
2059 Label& l = (NULL == p) ? d : *(p);
2060 __ z_brc((Assembler::branch_condition)$cmp$$cmpcode, l);
2061 %}
2062
2063 enc_class z_enc_cmpb_regreg(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2064 MacroAssembler _masm(&cbuf);
2065 Label* p = $lbl$$label;
2066
2067 // 'p' is `NULL' when this encoding class is used only to
2068 // determine the size of the encoded instruction.
2069 // Use a bound dummy label in that case.
2070 Label d;
2071 __ bind(d);
2072 Label& l = (NULL == p) ? d : *(p);
2073 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2074 unsigned long instr = $primary;
2075 if (instr == CRJ_ZOPC) {
2076 __ z_crj($src1$$Register, $src2$$Register, cc, l);
2077 } else if (instr == CLRJ_ZOPC) {
2078 __ z_clrj($src1$$Register, $src2$$Register, cc, l);
2079 } else if (instr == CGRJ_ZOPC) {
2080 __ z_cgrj($src1$$Register, $src2$$Register, cc, l);
2081 } else {
2082 guarantee(instr == CLGRJ_ZOPC, "opcode not implemented");
2083 __ z_clgrj($src1$$Register, $src2$$Register, cc, l);
2084 }
2085 %}
2086
2087 enc_class z_enc_cmpb_regregFar(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2088 MacroAssembler _masm(&cbuf);
2089 Label* p = $lbl$$label;
2090
2091 // 'p' is `NULL' when this encoding class is used only to
2092 // determine the size of the encoded instruction.
2093 // Use a bound dummy label in that case.
2094 Label d;
2095 __ bind(d);
2096 Label& l = (NULL == p) ? d : *(p);
2097
2098 unsigned long instr = $primary;
2099 if (instr == CR_ZOPC) {
2100 __ z_cr($src1$$Register, $src2$$Register);
2101 } else if (instr == CLR_ZOPC) {
2102 __ z_clr($src1$$Register, $src2$$Register);
2103 } else if (instr == CGR_ZOPC) {
2104 __ z_cgr($src1$$Register, $src2$$Register);
2105 } else {
2106 guarantee(instr == CLGR_ZOPC, "opcode not implemented");
2107 __ z_clgr($src1$$Register, $src2$$Register);
2108 }
2109
2110 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2111 %}
2112
2113 enc_class z_enc_cmpb_regimm(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2114 MacroAssembler _masm(&cbuf);
2115 Label* p = $lbl$$label;
2116
2117 // 'p' is `NULL' when this encoding class is used only to
2118 // determine the size of the encoded instruction.
2119 // Use a bound dummy label in that case.
2120 Label d;
2121 __ bind(d);
2122 Label& l = (NULL == p) ? d : *(p);
2123
2124 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2125 unsigned long instr = $primary;
2126 if (instr == CIJ_ZOPC) {
2127 __ z_cij($src1$$Register, $src2$$constant, cc, l);
2128 } else if (instr == CLIJ_ZOPC) {
2129 __ z_clij($src1$$Register, $src2$$constant, cc, l);
2130 } else if (instr == CGIJ_ZOPC) {
2131 __ z_cgij($src1$$Register, $src2$$constant, cc, l);
2132 } else {
2133 guarantee(instr == CLGIJ_ZOPC, "opcode not implemented");
2134 __ z_clgij($src1$$Register, $src2$$constant, cc, l);
2135 }
2136 %}
2137
2138 enc_class z_enc_cmpb_regimmFar(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2139 MacroAssembler _masm(&cbuf);
2140 Label* p = $lbl$$label;
2141
2142 // 'p' is `NULL' when this encoding class is used only to
2143 // determine the size of the encoded instruction.
2144 // Use a bound dummy label in that case.
2145 Label d;
2146 __ bind(d);
2147 Label& l = (NULL == p) ? d : *(p);
2148
2149 unsigned long instr = $primary;
2150 if (instr == CHI_ZOPC) {
2151 __ z_chi($src1$$Register, $src2$$constant);
2152 } else if (instr == CLFI_ZOPC) {
2153 __ z_clfi($src1$$Register, $src2$$constant);
2154 } else if (instr == CGHI_ZOPC) {
2155 __ z_cghi($src1$$Register, $src2$$constant);
2156 } else {
2157 guarantee(instr == CLGFI_ZOPC, "opcode not implemented");
2158 __ z_clgfi($src1$$Register, $src2$$constant);
2159 }
2160
2161 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2162 %}
2163
2164 // Call from Java to runtime.
2165 enc_class z_enc_java_to_runtime_call(method meth) %{
2166 MacroAssembler _masm(&cbuf);
2167
2168 // Save return pc before call to the place where we need it, since
2169 // callee doesn't.
2170 unsigned int start_off = __ offset();
2171 // Compute size of "larl + stg + call_c_opt".
2172 const int size_of_code = 6 + 6 + MacroAssembler::call_far_patchable_size();
2173 __ get_PC(Z_R14, size_of_code);
2174 __ save_return_pc();
2175 assert(__ offset() - start_off == 12, "bad prelude len: %d", __ offset() - start_off);
2176
2177 assert((__ offset() & 2) == 0, "misaligned z_enc_java_to_runtime_call");
2178 address call_addr = __ call_c_opt((address)$meth$$method);
2179 if (call_addr == NULL) {
2180 Compile::current()->env()->record_out_of_memory_failure();
2181 return;
2182 }
2183
2184 #ifdef ASSERT
2185 // Plausibility check for size_of_code assumptions.
2186 unsigned int actual_ret_off = __ offset();
2187 assert(start_off + size_of_code == actual_ret_off, "wrong return_pc");
2188 #endif
2189 %}
2190
2191 enc_class z_enc_java_static_call(method meth) %{
2192 // Call to fixup routine. Fixup routine uses ScopeDesc info to determine
2193 // whom we intended to call.
2194 MacroAssembler _masm(&cbuf);
2195 int ret_offset = 0;
2196
2197 if (!_method) {
2198 ret_offset = emit_call_reloc(_masm, $meth$$method,
2199 relocInfo::runtime_call_w_cp_type, ra_);
2200 } else {
2201 int method_index = resolved_method_index(cbuf);
2202 if (_optimized_virtual) {
2203 ret_offset = emit_call_reloc(_masm, $meth$$method,
2204 opt_virtual_call_Relocation::spec(method_index));
2205 } else {
2206 ret_offset = emit_call_reloc(_masm, $meth$$method,
2207 static_call_Relocation::spec(method_index));
2208 }
2209 }
2210 assert(__ inst_mark() != NULL, "emit_call_reloc must set_inst_mark()");
2211
2212 if (_method) { // Emit stub for static call.
2213 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2214 if (stub == NULL) {
2215 ciEnv::current()->record_failure("CodeCache is full");
2216 return;
2217 }
2218 }
2219 %}
2220
2221 // Java dynamic call
2222 enc_class z_enc_java_dynamic_call(method meth) %{
2223 MacroAssembler _masm(&cbuf);
2224 unsigned int start_off = __ offset();
2225
2226 int vtable_index = this->_vtable_index;
2227 if (vtable_index == -4) {
2228 Register ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2229 address virtual_call_oop_addr = NULL;
2230
2231 AddressLiteral empty_ic((address) Universe::non_oop_word());
2232 virtual_call_oop_addr = __ pc();
2233 bool success = __ load_const_from_toc(ic_reg, empty_ic);
2234 if (!success) {
2235 Compile::current()->env()->record_out_of_memory_failure();
2236 return;
2237 }
2238
2239 // Call to fixup routine. Fixup routine uses ScopeDesc info
2240 // to determine who we intended to call.
2241 int method_index = resolved_method_index(cbuf);
2242 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
2243 unsigned int ret_off = __ offset();
2244 assert(__ offset() - start_off == 6, "bad prelude len: %d", __ offset() - start_off);
2245 ret_off += emit_call_reloc(_masm, $meth$$method, relocInfo::none, ra_);
2246 assert(_method, "lazy_constant may be wrong when _method==null");
2247 } else {
2248 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2249 // Go through the vtable. Get receiver klass. Receiver already
2250 // checked for non-null. If we'll go thru a C2I adapter, the
2251 // interpreter expects method in Z_method.
2252 // Use Z_method to temporarily hold the klass oop. Z_R1_scratch is destroyed
2253 // by load_heap_oop_not_null.
2254 __ load_klass(Z_method, Z_R2);
2255
2256 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes();
2257 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
2258
2259 if (Displacement::is_validDisp(v_off) ) {
2260 // Can use load instruction with large offset.
2261 __ z_lg(Z_method, Address(Z_method /*class oop*/, v_off /*method offset*/));
2262 } else {
2263 // Worse case, must load offset into register.
2264 __ load_const(Z_R1_scratch, v_off);
2265 __ z_lg(Z_method, Address(Z_method /*class oop*/, Z_R1_scratch /*method offset*/));
2266 }
2267 // NOTE: for vtable dispatches, the vtable entry will never be
2268 // null. However it may very well end up in handle_wrong_method
2269 // if the method is abstract for the particular class.
2270 __ z_lg(Z_R1_scratch, Address(Z_method, Method::from_compiled_offset()));
2271 // Call target. Either compiled code or C2I adapter.
2272 __ z_basr(Z_R14, Z_R1_scratch);
2273 unsigned int ret_off = __ offset();
2274 }
2275 %}
2276
2277 enc_class z_enc_cmov_reg(cmpOp cmp, iRegI dst, iRegI src) %{
2278 MacroAssembler _masm(&cbuf);
2279 Register Rdst = reg_to_register_object($dst$$reg);
2280 Register Rsrc = reg_to_register_object($src$$reg);
2281
2282 // Don't emit code if operands are identical (same register).
2283 if (Rsrc != Rdst) {
2284 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2285
2286 if (VM_Version::has_LoadStoreConditional()) {
2287 __ z_locgr(Rdst, Rsrc, cc);
2288 } else {
2289 // Branch if not (cmp cr).
2290 Label done;
2291 __ z_brc(Assembler::inverse_condition(cc), done);
2292 __ z_lgr(Rdst, Rsrc); // Used for int and long+ptr.
2293 __ bind(done);
2294 }
2295 }
2296 %}
2297
2298 enc_class z_enc_cmov_imm(cmpOp cmp, iRegI dst, immI16 src) %{
2299 MacroAssembler _masm(&cbuf);
2300 Register Rdst = reg_to_register_object($dst$$reg);
2301 int Csrc = $src$$constant;
2302 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2303 Label done;
2304 // Branch if not (cmp cr).
2305 __ z_brc(Assembler::inverse_condition(cc), done);
2306 if (Csrc == 0) {
2307 // Don't set CC.
2308 __ clear_reg(Rdst, true, false); // Use for int, long & ptr.
2309 } else {
2310 __ z_lghi(Rdst, Csrc); // Use for int, long & ptr.
2311 }
2312 __ bind(done);
2313 %}
2314
2315 enc_class z_enc_cctobool(iRegI res) %{
2316 MacroAssembler _masm(&cbuf);
2317 Register Rres = reg_to_register_object($res$$reg);
2318
2319 if (VM_Version::has_LoadStoreConditional()) {
2320 __ load_const_optimized(Z_R0_scratch, 0L); // false (failed)
2321 __ load_const_optimized(Rres, 1L); // true (succeed)
2322 __ z_locgr(Rres, Z_R0_scratch, Assembler::bcondNotEqual);
2323 } else {
2324 Label done;
2325 __ load_const_optimized(Rres, 0L); // false (failed)
2326 __ z_brne(done); // Assume true to be the common case.
2327 __ load_const_optimized(Rres, 1L); // true (succeed)
2328 __ bind(done);
2329 }
2330 %}
2331
2332 enc_class z_enc_casI(iRegI compare_value, iRegI exchange_value, iRegP addr_ptr) %{
2333 MacroAssembler _masm(&cbuf);
2334 Register Rcomp = reg_to_register_object($compare_value$$reg);
2335 Register Rnew = reg_to_register_object($exchange_value$$reg);
2336 Register Raddr = reg_to_register_object($addr_ptr$$reg);
2337
2338 __ z_cs(Rcomp, Rnew, 0, Raddr);
2339 %}
2340
2341 enc_class z_enc_casL(iRegL compare_value, iRegL exchange_value, iRegP addr_ptr) %{
2342 MacroAssembler _masm(&cbuf);
2343 Register Rcomp = reg_to_register_object($compare_value$$reg);
2344 Register Rnew = reg_to_register_object($exchange_value$$reg);
2345 Register Raddr = reg_to_register_object($addr_ptr$$reg);
2346
2347 __ z_csg(Rcomp, Rnew, 0, Raddr);
2348 %}
2349
2350 enc_class z_enc_SwapI(memoryRSY mem, iRegI dst, iRegI tmp) %{
2351 MacroAssembler _masm(&cbuf);
2352 Register Rdst = reg_to_register_object($dst$$reg);
2353 Register Rtmp = reg_to_register_object($tmp$$reg);
2354 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2355 Label retry;
2356
2357 // Iterate until swap succeeds.
2358 __ z_llgf(Rtmp, $mem$$Address); // current contents
2359 __ bind(retry);
2360 // Calculate incremented value.
2361 __ z_csy(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2362 __ z_brne(retry); // Yikes, concurrent update, need to retry.
2363 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value.
2364 %}
2365
2366 enc_class z_enc_SwapL(memoryRSY mem, iRegL dst, iRegL tmp) %{
2367 MacroAssembler _masm(&cbuf);
2368 Register Rdst = reg_to_register_object($dst$$reg);
2369 Register Rtmp = reg_to_register_object($tmp$$reg);
2370 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2371 Label retry;
2372
2373 // Iterate until swap succeeds.
2374 __ z_lg(Rtmp, $mem$$Address); // current contents
2375 __ bind(retry);
2376 // Calculate incremented value.
2377 __ z_csg(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2378 __ z_brne(retry); // Yikes, concurrent update, need to retry.
2379 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value.
2380 %}
2381
2382 %} // encode
2383
2384 source %{
2385
2386 // Check whether outs are all Stores. If so, we can omit clearing the upper
2387 // 32 bits after encoding.
2388 static bool all_outs_are_Stores(const Node *n) {
2389 for (DUIterator_Fast imax, k = n->fast_outs(imax); k < imax; k++) {
2390 Node *out = n->fast_out(k);
2391 if (!out->is_Mach() || out->as_Mach()->ideal_Opcode() != Op_StoreN) {
2392 // Most other outs are SpillCopy, but there are various other.
2393 // jvm98 has arond 9% Encodes where we return false.
2394 return false;
2395 }
2396 }
2397 return true;
2398 }
2399
2400 %} // source
2401
2402
2403 //----------FRAME--------------------------------------------------------------
2404 // Definition of frame structure and management information.
2405
2406 frame %{
2407 // What direction does stack grow in (assumed to be same for native & Java).
2408 stack_direction(TOWARDS_LOW);
2409
2410 // These two registers define part of the calling convention between
2411 // compiled code and the interpreter.
2412
2413 // Inline Cache Register
2414 inline_cache_reg(Z_R9); // Z_inline_cache
2415
2416 // Argument pointer for I2C adapters
2417 //
2418 // Tos is loaded in run_compiled_code to Z_ARG5=Z_R6.
2419 // interpreter_arg_ptr_reg(Z_R6);
2420
2421 // Temporary in compiled entry-points
2422 // compiler_method_oop_reg(Z_R1);//Z_R1_scratch
2423
2424 // Method Oop Register when calling interpreter
2425 interpreter_method_oop_reg(Z_R9);//Z_method
2426
2427 // Optional: name the operand used by cisc-spilling to access
2428 // [stack_pointer + offset].
2429 cisc_spilling_operand_name(indOffset12);
2430
2431 // Number of stack slots consumed by a Monitor enter.
2432 sync_stack_slots(frame::jit_monitor_size_in_4_byte_units);
2433
2434 // Compiled code's Frame Pointer
2435 //
2436 // z/Architecture stack pointer
2437 frame_pointer(Z_R15); // Z_SP
2438
2439 // Interpreter stores its frame pointer in a register which is
2440 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
2441 // interpreted java to compiled java.
2442 //
2443 // Z_state holds pointer to caller's cInterpreter.
2444 interpreter_frame_pointer(Z_R7); // Z_state
2445
2446 // Use alignment_in_bytes instead of log_2_of_alignment_in_bits.
2447 stack_alignment(frame::alignment_in_bytes);
2448
2449 in_preserve_stack_slots(frame::jit_in_preserve_size_in_4_byte_units);
2450
2451 // A `slot' is assumed 4 bytes here!
2452 // out_preserve_stack_slots(frame::jit_out_preserve_size_in_4_byte_units);
2453
2454 // Number of outgoing stack slots killed above the
2455 // out_preserve_stack_slots for calls to C. Supports the var-args
2456 // backing area for register parms.
2457 varargs_C_out_slots_killed(((frame::z_abi_160_size - frame::z_jit_out_preserve_size) / VMRegImpl::stack_slot_size));
2458
2459 // The after-PROLOG location of the return address. Location of
2460 // return address specifies a type (REG or STACK) and a number
2461 // representing the register number (i.e. - use a register name) or
2462 // stack slot.
2463 return_addr(REG Z_R14);
2464
2465 // This is the body of the function
2466 //
2467 // void Matcher::calling_convention(OptoRegPair* sig /* array of ideal regs */,
2468 // uint length /* length of array */,
2469 // bool is_outgoing)
2470 //
2471 // The `sig' array is to be updated. Sig[j] represents the location
2472 // of the j-th argument, either a register or a stack slot.
2473
2474 // Body of function which returns an integer array locating
2475 // arguments either in registers or in stack slots. Passed an array
2476 // of ideal registers called "sig" and a "length" count. Stack-slot
2477 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2478 // arguments for a CALLEE. Incoming stack arguments are
2479 // automatically biased by the preserve_stack_slots field above.
2480 calling_convention %{
2481 // No difference between ingoing/outgoing just pass false.
2482 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2483 %}
2484
2485 // Body of function which returns an integer array locating
2486 // arguments either in registers or in stack slots. Passed an array
2487 // of ideal registers called "sig" and a "length" count. Stack-slot
2488 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2489 // arguments for a CALLEE. Incoming stack arguments are
2490 // automatically biased by the preserve_stack_slots field above.
2491 c_calling_convention %{
2492 // This is obviously always outgoing.
2493 // C argument must be in register AND stack slot.
2494 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2495 %}
2496
2497 // Location of native (C/C++) and interpreter return values. This
2498 // is specified to be the same as Java. In the 32-bit VM, long
2499 // values are actually returned from native calls in O0:O1 and
2500 // returned to the interpreter in I0:I1. The copying to and from
2501 // the register pairs is done by the appropriate call and epilog
2502 // opcodes. This simplifies the register allocator.
2503 //
2504 // Use register pair for c return value.
2505 c_return_value %{
2506 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
2507 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
2508 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
2509 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
2510 %}
2511
2512 // Use register pair for return value.
2513 // Location of compiled Java return values. Same as C
2514 return_value %{
2515 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
2516 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
2517 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
2518 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
2519 %}
2520 %}
2521
2522
2523 //----------ATTRIBUTES---------------------------------------------------------
2524
2525 //----------Operand Attributes-------------------------------------------------
2526 op_attrib op_cost(1); // Required cost attribute
2527
2528 //----------Instruction Attributes---------------------------------------------
2529
2530 // Cost attribute. required.
2531 ins_attrib ins_cost(DEFAULT_COST);
2532
2533 // Is this instruction a non-matching short branch variant of some
2534 // long branch? Not required.
2535 ins_attrib ins_short_branch(0);
2536
2537 // Indicates this is a trap based check node and final control-flow fixup
2538 // must generate a proper fall through.
2539 ins_attrib ins_is_TrapBasedCheckNode(true);
2540
2541 // Attribute of instruction to tell how many constants the instruction will generate.
2542 // (optional attribute). Default: 0.
2543 ins_attrib ins_num_consts(0);
2544
2545 // Required alignment attribute (must be a power of 2)
2546 // specifies the alignment that some part of the instruction (not
2547 // necessarily the start) requires. If > 1, a compute_padding()
2548 // function must be provided for the instruction.
2549 //
2550 // WARNING: Don't use size(FIXED_SIZE) or size(VARIABLE_SIZE) in
2551 // instructions which depend on the proper alignment, because the
2552 // desired alignment isn't guaranteed for the call to "emit()" during
2553 // the size computation.
2554 ins_attrib ins_alignment(1);
2555
2556 // Enforce/prohibit rematerializations.
2557 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
2558 // then rematerialization of that instruction is prohibited and the
2559 // instruction's value will be spilled if necessary.
2560 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
2561 // then rematerialization is enforced and the instruction's value will
2562 // never get spilled. a copy of the instruction will be inserted if
2563 // necessary.
2564 // Note: this may result in rematerializations in front of every use.
2565 // (optional attribute)
2566 ins_attrib ins_cannot_rematerialize(false);
2567 ins_attrib ins_should_rematerialize(false);
2568
2569 //----------OPERANDS-----------------------------------------------------------
2570 // Operand definitions must precede instruction definitions for correct
2571 // parsing in the ADLC because operands constitute user defined types
2572 // which are used in instruction definitions.
2573
2574 //----------Simple Operands----------------------------------------------------
2575 // Immediate Operands
2576 // Please note:
2577 // Formats are generated automatically for constants and base registers.
2578
2579 //----------------------------------------------
2580 // SIGNED (shorter than INT) immediate operands
2581 //----------------------------------------------
2582
2583 // Byte Immediate: constant 'int -1'
2584 operand immB_minus1() %{
2585 // sign-ext constant zero-ext constant
2586 predicate((n->get_int() == -1) || ((n->get_int()&0x000000ff) == 0x000000ff));
2587 match(ConI);
2588 op_cost(1);
2589 format %{ %}
2590 interface(CONST_INTER);
2591 %}
2592
2593 // Byte Immediate: constant, but not 'int 0' nor 'int -1'.
2594 operand immB_n0m1() %{
2595 // sign-ext constant zero-ext constant
2596 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x000000ff) != 0x000000ff);
2597 match(ConI);
2598 op_cost(1);
2599 format %{ %}
2600 interface(CONST_INTER);
2601 %}
2602
2603 // Short Immediate: constant 'int -1'
2604 operand immS_minus1() %{
2605 // sign-ext constant zero-ext constant
2606 predicate((n->get_int() == -1) || ((n->get_int()&0x0000ffff) == 0x0000ffff));
2607 match(ConI);
2608 op_cost(1);
2609 format %{ %}
2610 interface(CONST_INTER);
2611 %}
2612
2613 // Short Immediate: constant, but not 'int 0' nor 'int -1'.
2614 operand immS_n0m1() %{
2615 // sign-ext constant zero-ext constant
2616 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x0000ffff) != 0x0000ffff);
2617 match(ConI);
2618 op_cost(1);
2619 format %{ %}
2620 interface(CONST_INTER);
2621 %}
2622
2623 //-----------------------------------------
2624 // SIGNED INT immediate operands
2625 //-----------------------------------------
2626
2627 // Integer Immediate: 32-bit
2628 operand immI() %{
2629 match(ConI);
2630 op_cost(1);
2631 format %{ %}
2632 interface(CONST_INTER);
2633 %}
2634
2635 // Int Immediate: 20-bit
2636 operand immI20() %{
2637 predicate(Immediate::is_simm20(n->get_int()));
2638 match(ConI);
2639 op_cost(1);
2640 format %{ %}
2641 interface(CONST_INTER);
2642 %}
2643
2644 // Integer Immediate: 16-bit
2645 operand immI16() %{
2646 predicate(Immediate::is_simm16(n->get_int()));
2647 match(ConI);
2648 op_cost(1);
2649 format %{ %}
2650 interface(CONST_INTER);
2651 %}
2652
2653 // Integer Immediate: 8-bit
2654 operand immI8() %{
2655 predicate(Immediate::is_simm8(n->get_int()));
2656 match(ConI);
2657 op_cost(1);
2658 format %{ %}
2659 interface(CONST_INTER);
2660 %}
2661
2662 // Integer Immediate: constant 'int 0'
2663 operand immI_0() %{
2664 predicate(n->get_int() == 0);
2665 match(ConI);
2666 op_cost(1);
2667 format %{ %}
2668 interface(CONST_INTER);
2669 %}
2670
2671 // Integer Immediate: constant 'int -1'
2672 operand immI_minus1() %{
2673 predicate(n->get_int() == -1);
2674 match(ConI);
2675 op_cost(1);
2676 format %{ %}
2677 interface(CONST_INTER);
2678 %}
2679
2680 // Integer Immediate: constant, but not 'int 0' nor 'int -1'.
2681 operand immI_n0m1() %{
2682 predicate(n->get_int() != 0 && n->get_int() != -1);
2683 match(ConI);
2684 op_cost(1);
2685 format %{ %}
2686 interface(CONST_INTER);
2687 %}
2688
2689 //-------------------------------------------
2690 // UNSIGNED INT immediate operands
2691 //-------------------------------------------
2692
2693 // Unsigned Integer Immediate: 32-bit
2694 operand uimmI() %{
2695 match(ConI);
2696 op_cost(1);
2697 format %{ %}
2698 interface(CONST_INTER);
2699 %}
2700
2701 // Unsigned Integer Immediate: 16-bit
2702 operand uimmI16() %{
2703 predicate(Immediate::is_uimm16(n->get_int()));
2704 match(ConI);
2705 op_cost(1);
2706 format %{ %}
2707 interface(CONST_INTER);
2708 %}
2709
2710 // Unsigned Integer Immediate: 12-bit
2711 operand uimmI12() %{
2712 predicate(Immediate::is_uimm12(n->get_int()));
2713 match(ConI);
2714 op_cost(1);
2715 format %{ %}
2716 interface(CONST_INTER);
2717 %}
2718
2719 // Unsigned Integer Immediate: 12-bit
2720 operand uimmI8() %{
2721 predicate(Immediate::is_uimm8(n->get_int()));
2722 match(ConI);
2723 op_cost(1);
2724 format %{ %}
2725 interface(CONST_INTER);
2726 %}
2727
2728 // Integer Immediate: 6-bit
2729 operand uimmI6() %{
2730 predicate(Immediate::is_uimm(n->get_int(), 6));
2731 match(ConI);
2732 op_cost(1);
2733 format %{ %}
2734 interface(CONST_INTER);
2735 %}
2736
2737 // Integer Immediate: 5-bit
2738 operand uimmI5() %{
2739 predicate(Immediate::is_uimm(n->get_int(), 5));
2740 match(ConI);
2741 op_cost(1);
2742 format %{ %}
2743 interface(CONST_INTER);
2744 %}
2745
2746 // Length for SS instructions, given in DWs,
2747 // possible range [1..512], i.e. [8..4096] Bytes
2748 // used range [1..256], i.e. [8..2048] Bytes
2749 // operand type int
2750 // Unsigned Integer Immediate: 9-bit
2751 operand SSlenDW() %{
2752 predicate(Immediate::is_uimm8(n->get_long()-1));
2753 match(ConL);
2754 op_cost(1);
2755 format %{ %}
2756 interface(CONST_INTER);
2757 %}
2758
2759 //------------------------------------------
2760 // (UN)SIGNED INT specific values
2761 //------------------------------------------
2762
2763 // Integer Immediate: the value 1
2764 operand immI_1() %{
2765 predicate(n->get_int() == 1);
2766 match(ConI);
2767 op_cost(1);
2768 format %{ %}
2769 interface(CONST_INTER);
2770 %}
2771
2772 // Integer Immediate: the value 16.
2773 operand immI_16() %{
2774 predicate(n->get_int() == 16);
2775 match(ConI);
2776 op_cost(1);
2777 format %{ %}
2778 interface(CONST_INTER);
2779 %}
2780
2781 // Integer Immediate: the value 24.
2782 operand immI_24() %{
2783 predicate(n->get_int() == 24);
2784 match(ConI);
2785 op_cost(1);
2786 format %{ %}
2787 interface(CONST_INTER);
2788 %}
2789
2790 // Integer Immediate: the value 255
2791 operand immI_255() %{
2792 predicate(n->get_int() == 255);
2793 match(ConI);
2794 op_cost(1);
2795 format %{ %}
2796 interface(CONST_INTER);
2797 %}
2798
2799 // Integer Immediate: the values 32-63
2800 operand immI_32_63() %{
2801 predicate(n->get_int() >= 32 && n->get_int() <= 63);
2802 match(ConI);
2803 op_cost(1);
2804 format %{ %}
2805 interface(CONST_INTER);
2806 %}
2807
2808 // Unsigned Integer Immediate: LL-part, extended by 1s.
2809 operand uimmI_LL1() %{
2810 predicate((n->get_int() & 0xFFFF0000) == 0xFFFF0000);
2811 match(ConI);
2812 op_cost(1);
2813 format %{ %}
2814 interface(CONST_INTER);
2815 %}
2816
2817 // Unsigned Integer Immediate: LH-part, extended by 1s.
2818 operand uimmI_LH1() %{
2819 predicate((n->get_int() & 0xFFFF) == 0xFFFF);
2820 match(ConI);
2821 op_cost(1);
2822 format %{ %}
2823 interface(CONST_INTER);
2824 %}
2825
2826 //------------------------------------------
2827 // SIGNED LONG immediate operands
2828 //------------------------------------------
2829
2830 operand immL() %{
2831 match(ConL);
2832 op_cost(1);
2833 format %{ %}
2834 interface(CONST_INTER);
2835 %}
2836
2837 // Long Immediate: 32-bit
2838 operand immL32() %{
2839 predicate(Immediate::is_simm32(n->get_long()));
2840 match(ConL);
2841 op_cost(1);
2842 format %{ %}
2843 interface(CONST_INTER);
2844 %}
2845
2846 // Long Immediate: 20-bit
2847 operand immL20() %{
2848 predicate(Immediate::is_simm20(n->get_long()));
2849 match(ConL);
2850 op_cost(1);
2851 format %{ %}
2852 interface(CONST_INTER);
2853 %}
2854
2855 // Long Immediate: 16-bit
2856 operand immL16() %{
2857 predicate(Immediate::is_simm16(n->get_long()));
2858 match(ConL);
2859 op_cost(1);
2860 format %{ %}
2861 interface(CONST_INTER);
2862 %}
2863
2864 // Long Immediate: 8-bit
2865 operand immL8() %{
2866 predicate(Immediate::is_simm8(n->get_long()));
2867 match(ConL);
2868 op_cost(1);
2869 format %{ %}
2870 interface(CONST_INTER);
2871 %}
2872
2873 //--------------------------------------------
2874 // UNSIGNED LONG immediate operands
2875 //--------------------------------------------
2876
2877 operand uimmL32() %{
2878 predicate(Immediate::is_uimm32(n->get_long()));
2879 match(ConL);
2880 op_cost(1);
2881 format %{ %}
2882 interface(CONST_INTER);
2883 %}
2884
2885 // Unsigned Long Immediate: 16-bit
2886 operand uimmL16() %{
2887 predicate(Immediate::is_uimm16(n->get_long()));
2888 match(ConL);
2889 op_cost(1);
2890 format %{ %}
2891 interface(CONST_INTER);
2892 %}
2893
2894 // Unsigned Long Immediate: 12-bit
2895 operand uimmL12() %{
2896 predicate(Immediate::is_uimm12(n->get_long()));
2897 match(ConL);
2898 op_cost(1);
2899 format %{ %}
2900 interface(CONST_INTER);
2901 %}
2902
2903 // Unsigned Long Immediate: 8-bit
2904 operand uimmL8() %{
2905 predicate(Immediate::is_uimm8(n->get_long()));
2906 match(ConL);
2907 op_cost(1);
2908 format %{ %}
2909 interface(CONST_INTER);
2910 %}
2911
2912 //-------------------------------------------
2913 // (UN)SIGNED LONG specific values
2914 //-------------------------------------------
2915
2916 // Long Immediate: the value FF
2917 operand immL_FF() %{
2918 predicate(n->get_long() == 0xFFL);
2919 match(ConL);
2920 op_cost(1);
2921 format %{ %}
2922 interface(CONST_INTER);
2923 %}
2924
2925 // Long Immediate: the value FFFF
2926 operand immL_FFFF() %{
2927 predicate(n->get_long() == 0xFFFFL);
2928 match(ConL);
2929 op_cost(1);
2930 format %{ %}
2931 interface(CONST_INTER);
2932 %}
2933
2934 // Long Immediate: the value FFFFFFFF
2935 operand immL_FFFFFFFF() %{
2936 predicate(n->get_long() == 0xFFFFFFFFL);
2937 match(ConL);
2938 op_cost(1);
2939 format %{ %}
2940 interface(CONST_INTER);
2941 %}
2942
2943 operand immL_0() %{
2944 predicate(n->get_long() == 0L);
2945 match(ConL);
2946 op_cost(1);
2947 format %{ %}
2948 interface(CONST_INTER);
2949 %}
2950
2951 // Unsigned Long Immediate: LL-part, extended by 1s.
2952 operand uimmL_LL1() %{
2953 predicate((n->get_long() & 0xFFFFFFFFFFFF0000L) == 0xFFFFFFFFFFFF0000L);
2954 match(ConL);
2955 op_cost(1);
2956 format %{ %}
2957 interface(CONST_INTER);
2958 %}
2959
2960 // Unsigned Long Immediate: LH-part, extended by 1s.
2961 operand uimmL_LH1() %{
2962 predicate((n->get_long() & 0xFFFFFFFF0000FFFFL) == 0xFFFFFFFF0000FFFFL);
2963 match(ConL);
2964 op_cost(1);
2965 format %{ %}
2966 interface(CONST_INTER);
2967 %}
2968
2969 // Unsigned Long Immediate: HL-part, extended by 1s.
2970 operand uimmL_HL1() %{
2971 predicate((n->get_long() & 0xFFFF0000FFFFFFFFL) == 0xFFFF0000FFFFFFFFL);
2972 match(ConL);
2973 op_cost(1);
2974 format %{ %}
2975 interface(CONST_INTER);
2976 %}
2977
2978 // Unsigned Long Immediate: HH-part, extended by 1s.
2979 operand uimmL_HH1() %{
2980 predicate((n->get_long() & 0xFFFFFFFFFFFFL) == 0xFFFFFFFFFFFFL);
2981 match(ConL);
2982 op_cost(1);
2983 format %{ %}
2984 interface(CONST_INTER);
2985 %}
2986
2987 // Long Immediate: low 32-bit mask
2988 operand immL_32bits() %{
2989 predicate(n->get_long() == 0xFFFFFFFFL);
2990 match(ConL);
2991 op_cost(1);
2992 format %{ %}
2993 interface(CONST_INTER);
2994 %}
2995
2996 //--------------------------------------
2997 // POINTER immediate operands
2998 //--------------------------------------
2999
3000 // Pointer Immediate: 64-bit
3001 operand immP() %{
3002 match(ConP);
3003 op_cost(1);
3004 format %{ %}
3005 interface(CONST_INTER);
3006 %}
3007
3008 // Pointer Immediate: 32-bit
3009 operand immP32() %{
3010 predicate(Immediate::is_uimm32(n->get_ptr()));
3011 match(ConP);
3012 op_cost(1);
3013 format %{ %}
3014 interface(CONST_INTER);
3015 %}
3016
3017 // Pointer Immediate: 16-bit
3018 operand immP16() %{
3019 predicate(Immediate::is_uimm16(n->get_ptr()));
3020 match(ConP);
3021 op_cost(1);
3022 format %{ %}
3023 interface(CONST_INTER);
3024 %}
3025
3026 // Pointer Immediate: 8-bit
3027 operand immP8() %{
3028 predicate(Immediate::is_uimm8(n->get_ptr()));
3029 match(ConP);
3030 op_cost(1);
3031 format %{ %}
3032 interface(CONST_INTER);
3033 %}
3034
3035 //-----------------------------------
3036 // POINTER specific values
3037 //-----------------------------------
3038
3039 // Pointer Immediate: NULL
3040 operand immP0() %{
3041 predicate(n->get_ptr() == 0);
3042 match(ConP);
3043 op_cost(1);
3044 format %{ %}
3045 interface(CONST_INTER);
3046 %}
3047
3048 //---------------------------------------------
3049 // NARROW POINTER immediate operands
3050 //---------------------------------------------
3051
3052 // Narrow Pointer Immediate
3053 operand immN() %{
3054 match(ConN);
3055 op_cost(1);
3056 format %{ %}
3057 interface(CONST_INTER);
3058 %}
3059
3060 operand immNKlass() %{
3061 match(ConNKlass);
3062 op_cost(1);
3063 format %{ %}
3064 interface(CONST_INTER);
3065 %}
3066
3067 // Narrow Pointer Immediate
3068 operand immN8() %{
3069 predicate(Immediate::is_uimm8(n->get_narrowcon()));
3070 match(ConN);
3071 op_cost(1);
3072 format %{ %}
3073 interface(CONST_INTER);
3074 %}
3075
3076 // Narrow NULL Pointer Immediate
3077 operand immN0() %{
3078 predicate(n->get_narrowcon() == 0);
3079 match(ConN);
3080 op_cost(1);
3081 format %{ %}
3082 interface(CONST_INTER);
3083 %}
3084
3085 // FLOAT and DOUBLE immediate operands
3086
3087 // Double Immediate
3088 operand immD() %{
3089 match(ConD);
3090 op_cost(1);
3091 format %{ %}
3092 interface(CONST_INTER);
3093 %}
3094
3095 // Double Immediate: +-0
3096 operand immDpm0() %{
3097 predicate(n->getd() == 0);
3098 match(ConD);
3099 op_cost(1);
3100 format %{ %}
3101 interface(CONST_INTER);
3102 %}
3103
3104 // Double Immediate: +0
3105 operand immDp0() %{
3106 predicate(jlong_cast(n->getd()) == 0);
3107 match(ConD);
3108 op_cost(1);
3109 format %{ %}
3110 interface(CONST_INTER);
3111 %}
3112
3113 // Float Immediate
3114 operand immF() %{
3115 match(ConF);
3116 op_cost(1);
3117 format %{ %}
3118 interface(CONST_INTER);
3119 %}
3120
3121 // Float Immediate: +-0
3122 operand immFpm0() %{
3123 predicate(n->getf() == 0);
3124 match(ConF);
3125 op_cost(1);
3126 format %{ %}
3127 interface(CONST_INTER);
3128 %}
3129
3130 // Float Immediate: +0
3131 operand immFp0() %{
3132 predicate(jint_cast(n->getf()) == 0);
3133 match(ConF);
3134 op_cost(1);
3135 format %{ %}
3136 interface(CONST_INTER);
3137 %}
3138
3139 // End of Immediate Operands
3140
3141 // Integer Register Operands
3142 // Integer Register
3143 operand iRegI() %{
3144 constraint(ALLOC_IN_RC(z_int_reg));
3145 match(RegI);
3146 match(noArg_iRegI);
3147 match(rarg1RegI);
3148 match(rarg2RegI);
3149 match(rarg3RegI);
3150 match(rarg4RegI);
3151 match(rarg5RegI);
3152 match(noOdd_iRegI);
3153 match(revenRegI);
3154 match(roddRegI);
3155 format %{ %}
3156 interface(REG_INTER);
3157 %}
3158
3159 operand noArg_iRegI() %{
3160 constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3161 match(RegI);
3162 format %{ %}
3163 interface(REG_INTER);
3164 %}
3165
3166 // Revenregi and roddRegI constitute and even-odd-pair.
3167 operand revenRegI() %{
3168 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3169 match(iRegI);
3170 format %{ %}
3171 interface(REG_INTER);
3172 %}
3173
3174 // Revenregi and roddRegI constitute and even-odd-pair.
3175 operand roddRegI() %{
3176 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3177 match(iRegI);
3178 format %{ %}
3179 interface(REG_INTER);
3180 %}
3181
3182 operand rarg1RegI() %{
3183 constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3184 match(iRegI);
3185 format %{ %}
3186 interface(REG_INTER);
3187 %}
3188
3189 operand rarg2RegI() %{
3190 constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3191 match(iRegI);
3192 format %{ %}
3193 interface(REG_INTER);
3194 %}
3195
3196 operand rarg3RegI() %{
3197 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3198 match(iRegI);
3199 format %{ %}
3200 interface(REG_INTER);
3201 %}
3202
3203 operand rarg4RegI() %{
3204 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3205 match(iRegI);
3206 format %{ %}
3207 interface(REG_INTER);
3208 %}
3209
3210 operand rarg5RegI() %{
3211 constraint(ALLOC_IN_RC(z_rarg5_int_reg));
3212 match(iRegI);
3213 format %{ %}
3214 interface(REG_INTER);
3215 %}
3216
3217 operand noOdd_iRegI() %{
3218 constraint(ALLOC_IN_RC(z_no_odd_int_reg));
3219 match(RegI);
3220 match(revenRegI);
3221 format %{ %}
3222 interface(REG_INTER);
3223 %}
3224
3225 // Pointer Register
3226 operand iRegP() %{
3227 constraint(ALLOC_IN_RC(z_ptr_reg));
3228 match(RegP);
3229 match(noArg_iRegP);
3230 match(rarg1RegP);
3231 match(rarg2RegP);
3232 match(rarg3RegP);
3233 match(rarg4RegP);
3234 match(rarg5RegP);
3235 match(revenRegP);
3236 match(roddRegP);
3237 format %{ %}
3238 interface(REG_INTER);
3239 %}
3240
3241 // thread operand
3242 operand threadRegP() %{
3243 constraint(ALLOC_IN_RC(z_thread_ptr_reg));
3244 match(RegP);
3245 format %{ "Z_THREAD" %}
3246 interface(REG_INTER);
3247 %}
3248
3249 operand noArg_iRegP() %{
3250 constraint(ALLOC_IN_RC(z_no_arg_ptr_reg));
3251 match(iRegP);
3252 format %{ %}
3253 interface(REG_INTER);
3254 %}
3255
3256 operand rarg1RegP() %{
3257 constraint(ALLOC_IN_RC(z_rarg1_ptr_reg));
3258 match(iRegP);
3259 format %{ %}
3260 interface(REG_INTER);
3261 %}
3262
3263 operand rarg2RegP() %{
3264 constraint(ALLOC_IN_RC(z_rarg2_ptr_reg));
3265 match(iRegP);
3266 format %{ %}
3267 interface(REG_INTER);
3268 %}
3269
3270 operand rarg3RegP() %{
3271 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3272 match(iRegP);
3273 format %{ %}
3274 interface(REG_INTER);
3275 %}
3276
3277 operand rarg4RegP() %{
3278 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3279 match(iRegP);
3280 format %{ %}
3281 interface(REG_INTER);
3282 %}
3283
3284 operand rarg5RegP() %{
3285 constraint(ALLOC_IN_RC(z_rarg5_ptr_reg));
3286 match(iRegP);
3287 format %{ %}
3288 interface(REG_INTER);
3289 %}
3290
3291 operand memoryRegP() %{
3292 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3293 match(RegP);
3294 match(iRegP);
3295 match(threadRegP);
3296 format %{ %}
3297 interface(REG_INTER);
3298 %}
3299
3300 // Revenregp and roddRegP constitute and even-odd-pair.
3301 operand revenRegP() %{
3302 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3303 match(iRegP);
3304 format %{ %}
3305 interface(REG_INTER);
3306 %}
3307
3308 // Revenregl and roddRegL constitute and even-odd-pair.
3309 operand roddRegP() %{
3310 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3311 match(iRegP);
3312 format %{ %}
3313 interface(REG_INTER);
3314 %}
3315
3316 operand lock_ptr_RegP() %{
3317 constraint(ALLOC_IN_RC(z_lock_ptr_reg));
3318 match(RegP);
3319 format %{ %}
3320 interface(REG_INTER);
3321 %}
3322
3323 operand rscratch2RegP() %{
3324 constraint(ALLOC_IN_RC(z_rscratch2_bits64_reg));
3325 match(RegP);
3326 format %{ %}
3327 interface(REG_INTER);
3328 %}
3329
3330 operand iRegN() %{
3331 constraint(ALLOC_IN_RC(z_int_reg));
3332 match(RegN);
3333 match(noArg_iRegN);
3334 match(rarg1RegN);
3335 match(rarg2RegN);
3336 match(rarg3RegN);
3337 match(rarg4RegN);
3338 match(rarg5RegN);
3339 format %{ %}
3340 interface(REG_INTER);
3341 %}
3342
3343 operand noArg_iRegN() %{
3344 constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3345 match(iRegN);
3346 format %{ %}
3347 interface(REG_INTER);
3348 %}
3349
3350 operand rarg1RegN() %{
3351 constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3352 match(iRegN);
3353 format %{ %}
3354 interface(REG_INTER);
3355 %}
3356
3357 operand rarg2RegN() %{
3358 constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3359 match(iRegN);
3360 format %{ %}
3361 interface(REG_INTER);
3362 %}
3363
3364 operand rarg3RegN() %{
3365 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3366 match(iRegN);
3367 format %{ %}
3368 interface(REG_INTER);
3369 %}
3370
3371 operand rarg4RegN() %{
3372 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3373 match(iRegN);
3374 format %{ %}
3375 interface(REG_INTER);
3376 %}
3377
3378 operand rarg5RegN() %{
3379 constraint(ALLOC_IN_RC(z_rarg5_ptrN_reg));
3380 match(iRegN);
3381 format %{ %}
3382 interface(REG_INTER);
3383 %}
3384
3385 // Long Register
3386 operand iRegL() %{
3387 constraint(ALLOC_IN_RC(z_long_reg));
3388 match(RegL);
3389 match(revenRegL);
3390 match(roddRegL);
3391 match(rarg1RegL);
3392 match(rarg5RegL);
3393 format %{ %}
3394 interface(REG_INTER);
3395 %}
3396
3397 // Revenregl and roddRegL constitute and even-odd-pair.
3398 operand revenRegL() %{
3399 constraint(ALLOC_IN_RC(z_rarg3_long_reg));
3400 match(iRegL);
3401 format %{ %}
3402 interface(REG_INTER);
3403 %}
3404
3405 // Revenregl and roddRegL constitute and even-odd-pair.
3406 operand roddRegL() %{
3407 constraint(ALLOC_IN_RC(z_rarg4_long_reg));
3408 match(iRegL);
3409 format %{ %}
3410 interface(REG_INTER);
3411 %}
3412
3413 operand rarg1RegL() %{
3414 constraint(ALLOC_IN_RC(z_rarg1_long_reg));
3415 match(iRegL);
3416 format %{ %}
3417 interface(REG_INTER);
3418 %}
3419
3420 operand rarg5RegL() %{
3421 constraint(ALLOC_IN_RC(z_rarg5_long_reg));
3422 match(iRegL);
3423 format %{ %}
3424 interface(REG_INTER);
3425 %}
3426
3427 // Condition Code Flag Registers
3428 operand flagsReg() %{
3429 constraint(ALLOC_IN_RC(z_condition_reg));
3430 match(RegFlags);
3431 format %{ "CR" %}
3432 interface(REG_INTER);
3433 %}
3434
3435 // Condition Code Flag Registers for rules with result tuples
3436 operand TD_flagsReg() %{
3437 constraint(ALLOC_IN_RC(z_condition_reg));
3438 match(RegFlags);
3439 format %{ "CR" %}
3440 interface(REG_TUPLE_DEST_INTER);
3441 %}
3442
3443 operand regD() %{
3444 constraint(ALLOC_IN_RC(z_dbl_reg));
3445 match(RegD);
3446 format %{ %}
3447 interface(REG_INTER);
3448 %}
3449
3450 operand rscratchRegD() %{
3451 constraint(ALLOC_IN_RC(z_rscratch1_dbl_reg));
3452 match(RegD);
3453 format %{ %}
3454 interface(REG_INTER);
3455 %}
3456
3457 operand regF() %{
3458 constraint(ALLOC_IN_RC(z_flt_reg));
3459 match(RegF);
3460 format %{ %}
3461 interface(REG_INTER);
3462 %}
3463
3464 operand rscratchRegF() %{
3465 constraint(ALLOC_IN_RC(z_rscratch1_flt_reg));
3466 match(RegF);
3467 format %{ %}
3468 interface(REG_INTER);
3469 %}
3470
3471 // Special Registers
3472
3473 // Method Register
3474 operand inline_cache_regP(iRegP reg) %{
3475 constraint(ALLOC_IN_RC(z_r9_regP)); // inline_cache_reg
3476 match(reg);
3477 format %{ %}
3478 interface(REG_INTER);
3479 %}
3480
3481 operand compiler_method_oop_regP(iRegP reg) %{
3482 constraint(ALLOC_IN_RC(z_r1_RegP)); // compiler_method_oop_reg
3483 match(reg);
3484 format %{ %}
3485 interface(REG_INTER);
3486 %}
3487
3488 operand interpreter_method_oop_regP(iRegP reg) %{
3489 constraint(ALLOC_IN_RC(z_r9_regP)); // interpreter_method_oop_reg
3490 match(reg);
3491 format %{ %}
3492 interface(REG_INTER);
3493 %}
3494
3495 // Operands to remove register moves in unscaled mode.
3496 // Match read/write registers with an EncodeP node if neither shift nor add are required.
3497 operand iRegP2N(iRegP reg) %{
3498 predicate(Universe::narrow_oop_shift() == 0 && _leaf->as_EncodeP()->in(0) == NULL);
3499 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3500 match(EncodeP reg);
3501 format %{ "$reg" %}
3502 interface(REG_INTER)
3503 %}
3504
3505 operand iRegN2P(iRegN reg) %{
3506 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0 &&
3507 _leaf->as_DecodeN()->in(0) == NULL);
3508 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3509 match(DecodeN reg);
3510 format %{ "$reg" %}
3511 interface(REG_INTER)
3512 %}
3513
3514
3515 //----------Complex Operands---------------------------------------------------
3516
3517 // Indirect Memory Reference
3518 operand indirect(memoryRegP base) %{
3519 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3520 match(base);
3521 op_cost(1);
3522 format %{ "#0[,$base]" %}
3523 interface(MEMORY_INTER) %{
3524 base($base);
3525 index(0xffffFFFF); // noreg
3526 scale(0x0);
3527 disp(0x0);
3528 %}
3529 %}
3530
3531 // Indirect with Offset (long)
3532 operand indOffset20(memoryRegP base, immL20 offset) %{
3533 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3534 match(AddP base offset);
3535 op_cost(1);
3536 format %{ "$offset[,$base]" %}
3537 interface(MEMORY_INTER) %{
3538 base($base);
3539 index(0xffffFFFF); // noreg
3540 scale(0x0);
3541 disp($offset);
3542 %}
3543 %}
3544
3545 operand indOffset20Narrow(iRegN base, immL20 offset) %{
3546 predicate(Matcher::narrow_oop_use_complex_address());
3547 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3548 match(AddP (DecodeN base) offset);
3549 op_cost(1);
3550 format %{ "$offset[,$base]" %}
3551 interface(MEMORY_INTER) %{
3552 base($base);
3553 index(0xffffFFFF); // noreg
3554 scale(0x0);
3555 disp($offset);
3556 %}
3557 %}
3558
3559 // Indirect with Offset (short)
3560 operand indOffset12(memoryRegP base, uimmL12 offset) %{
3561 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3562 match(AddP base offset);
3563 op_cost(1);
3564 format %{ "$offset[[,$base]]" %}
3565 interface(MEMORY_INTER) %{
3566 base($base);
3567 index(0xffffFFFF); // noreg
3568 scale(0x0);
3569 disp($offset);
3570 %}
3571 %}
3572
3573 operand indOffset12Narrow(iRegN base, uimmL12 offset) %{
3574 predicate(Matcher::narrow_oop_use_complex_address());
3575 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3576 match(AddP (DecodeN base) offset);
3577 op_cost(1);
3578 format %{ "$offset[[,$base]]" %}
3579 interface(MEMORY_INTER) %{
3580 base($base);
3581 index(0xffffFFFF); // noreg
3582 scale(0x0);
3583 disp($offset);
3584 %}
3585 %}
3586
3587 // Indirect with Register Index
3588 operand indIndex(memoryRegP base, iRegL index) %{
3589 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3590 match(AddP base index);
3591 op_cost(1);
3592 format %{ "#0[($index,$base)]" %}
3593 interface(MEMORY_INTER) %{
3594 base($base);
3595 index($index);
3596 scale(0x0);
3597 disp(0x0);
3598 %}
3599 %}
3600
3601 // Indirect with Offset (long) and index
3602 operand indOffset20index(memoryRegP base, immL20 offset, iRegL index) %{
3603 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3604 match(AddP (AddP base index) offset);
3605 op_cost(1);
3606 format %{ "$offset[($index,$base)]" %}
3607 interface(MEMORY_INTER) %{
3608 base($base);
3609 index($index);
3610 scale(0x0);
3611 disp($offset);
3612 %}
3613 %}
3614
3615 operand indOffset20indexNarrow(iRegN base, immL20 offset, iRegL index) %{
3616 predicate(Matcher::narrow_oop_use_complex_address());
3617 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3618 match(AddP (AddP (DecodeN base) index) offset);
3619 op_cost(1);
3620 format %{ "$offset[($index,$base)]" %}
3621 interface(MEMORY_INTER) %{
3622 base($base);
3623 index($index);
3624 scale(0x0);
3625 disp($offset);
3626 %}
3627 %}
3628
3629 // Indirect with Offset (short) and index
3630 operand indOffset12index(memoryRegP base, uimmL12 offset, iRegL index) %{
3631 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3632 match(AddP (AddP base index) offset);
3633 op_cost(1);
3634 format %{ "$offset[[($index,$base)]]" %}
3635 interface(MEMORY_INTER) %{
3636 base($base);
3637 index($index);
3638 scale(0x0);
3639 disp($offset);
3640 %}
3641 %}
3642
3643 operand indOffset12indexNarrow(iRegN base, uimmL12 offset, iRegL index) %{
3644 predicate(Matcher::narrow_oop_use_complex_address());
3645 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3646 match(AddP (AddP (DecodeN base) index) offset);
3647 op_cost(1);
3648 format %{ "$offset[[($index,$base)]]" %}
3649 interface(MEMORY_INTER) %{
3650 base($base);
3651 index($index);
3652 scale(0x0);
3653 disp($offset);
3654 %}
3655 %}
3656
3657 //----------Special Memory Operands--------------------------------------------
3658
3659 // Stack Slot Operand
3660 // This operand is used for loading and storing temporary values on
3661 // the stack where a match requires a value to flow through memory.
3662 operand stackSlotI(sRegI reg) %{
3663 constraint(ALLOC_IN_RC(stack_slots));
3664 op_cost(1);
3665 format %{ "[$reg(stackSlotI)]" %}
3666 interface(MEMORY_INTER) %{
3667 base(0xf); // Z_SP
3668 index(0xffffFFFF); // noreg
3669 scale(0x0);
3670 disp($reg); // stack offset
3671 %}
3672 %}
3673
3674 operand stackSlotP(sRegP reg) %{
3675 constraint(ALLOC_IN_RC(stack_slots));
3676 op_cost(1);
3677 format %{ "[$reg(stackSlotP)]" %}
3678 interface(MEMORY_INTER) %{
3679 base(0xf); // Z_SP
3680 index(0xffffFFFF); // noreg
3681 scale(0x0);
3682 disp($reg); // Stack Offset
3683 %}
3684 %}
3685
3686 operand stackSlotF(sRegF reg) %{
3687 constraint(ALLOC_IN_RC(stack_slots));
3688 op_cost(1);
3689 format %{ "[$reg(stackSlotF)]" %}
3690 interface(MEMORY_INTER) %{
3691 base(0xf); // Z_SP
3692 index(0xffffFFFF); // noreg
3693 scale(0x0);
3694 disp($reg); // Stack Offset
3695 %}
3696 %}
3697
3698 operand stackSlotD(sRegD reg) %{
3699 constraint(ALLOC_IN_RC(stack_slots));
3700 op_cost(1);
3701 //match(RegD);
3702 format %{ "[$reg(stackSlotD)]" %}
3703 interface(MEMORY_INTER) %{
3704 base(0xf); // Z_SP
3705 index(0xffffFFFF); // noreg
3706 scale(0x0);
3707 disp($reg); // Stack Offset
3708 %}
3709 %}
3710
3711 operand stackSlotL(sRegL reg) %{
3712 constraint(ALLOC_IN_RC(stack_slots));
3713 op_cost(1); //match(RegL);
3714 format %{ "[$reg(stackSlotL)]" %}
3715 interface(MEMORY_INTER) %{
3716 base(0xf); // Z_SP
3717 index(0xffffFFFF); // noreg
3718 scale(0x0);
3719 disp($reg); // Stack Offset
3720 %}
3721 %}
3722
3723 // Operands for expressing Control Flow
3724 // NOTE: Label is a predefined operand which should not be redefined in
3725 // the AD file. It is generically handled within the ADLC.
3726
3727 //----------Conditional Branch Operands----------------------------------------
3728 // Comparison Op - This is the operation of the comparison, and is limited to
3729 // the following set of codes:
3730 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3731 //
3732 // Other attributes of the comparison, such as unsignedness, are specified
3733 // by the comparison instruction that sets a condition code flags register.
3734 // That result is represented by a flags operand whose subtype is appropriate
3735 // to the unsignedness (etc.) of the comparison.
3736 //
3737 // Later, the instruction which matches both the Comparison Op (a Bool) and
3738 // the flags (produced by the Cmp) specifies the coding of the comparison op
3739 // by matching a specific subtype of Bool operand below.
3740
3741 // INT cmpOps for CompareAndBranch and CompareAndTrap instructions should not
3742 // have mask bit #3 set.
3743 operand cmpOpT() %{
3744 match(Bool);
3745 format %{ "" %}
3746 interface(COND_INTER) %{
3747 equal(0x8); // Assembler::bcondEqual
3748 not_equal(0x6); // Assembler::bcondNotEqual
3749 less(0x4); // Assembler::bcondLow
3750 greater_equal(0xa); // Assembler::bcondNotLow
3751 less_equal(0xc); // Assembler::bcondNotHigh
3752 greater(0x2); // Assembler::bcondHigh
3753 overflow(0x1); // Assembler::bcondOverflow
3754 no_overflow(0xe); // Assembler::bcondNotOverflow
3755 %}
3756 %}
3757
3758 // When used for floating point comparisons: unordered is treated as less.
3759 operand cmpOpF() %{
3760 match(Bool);
3761 format %{ "" %}
3762 interface(COND_INTER) %{
3763 equal(0x8);
3764 not_equal(0x7); // Includes 'unordered'.
3765 less(0x5); // Includes 'unordered'.
3766 greater_equal(0xa);
3767 less_equal(0xd); // Includes 'unordered'.
3768 greater(0x2);
3769 overflow(0x0); // Not meaningful on z/Architecture.
3770 no_overflow(0x0); // leave unchanged (zero) therefore
3771 %}
3772 %}
3773
3774 // "Regular" cmpOp for int comparisons, includes bit #3 (overflow).
3775 operand cmpOp() %{
3776 match(Bool);
3777 format %{ "" %}
3778 interface(COND_INTER) %{
3779 equal(0x8);
3780 not_equal(0x7); // Includes 'unordered'.
3781 less(0x5); // Includes 'unordered'.
3782 greater_equal(0xa);
3783 less_equal(0xd); // Includes 'unordered'.
3784 greater(0x2);
3785 overflow(0x1); // Assembler::bcondOverflow
3786 no_overflow(0xe); // Assembler::bcondNotOverflow
3787 %}
3788 %}
3789
3790 //----------OPERAND CLASSES----------------------------------------------------
3791 // Operand Classes are groups of operands that are used to simplify
3792 // instruction definitions by not requiring the AD writer to specify
3793 // seperate instructions for every form of operand when the
3794 // instruction accepts multiple operand types with the same basic
3795 // encoding and format. The classic case of this is memory operands.
3796 // Indirect is not included since its use is limited to Compare & Swap
3797
3798 // Most general memory operand, allows base, index, and long displacement.
3799 opclass memory(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3800 opclass memoryRXY(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3801
3802 // General memory operand, allows base, index, and short displacement.
3803 opclass memoryRX(indirect, indIndex, indOffset12, indOffset12Narrow, indOffset12index, indOffset12indexNarrow);
3804
3805 // Memory operand, allows only base and long displacement.
3806 opclass memoryRSY(indirect, indOffset20, indOffset20Narrow);
3807
3808 // Memory operand, allows only base and short displacement.
3809 opclass memoryRS(indirect, indOffset12, indOffset12Narrow);
3810
3811 // Operand classes to match encode and decode.
3812 opclass iRegN_P2N(iRegN);
3813 opclass iRegP_N2P(iRegP);
3814
3815
3816 //----------PIPELINE-----------------------------------------------------------
3817 pipeline %{
3818
3819 //----------ATTRIBUTES---------------------------------------------------------
3820 attributes %{
3821 // z/Architecture instructions are of length 2, 4, or 6 bytes.
3822 variable_size_instructions;
3823 instruction_unit_size = 2;
3824
3825 // Meaningless on z/Architecture.
3826 max_instructions_per_bundle = 1;
3827
3828 // The z/Architecture processor fetches 64 bytes...
3829 instruction_fetch_unit_size = 64;
3830
3831 // ...in one line.
3832 instruction_fetch_units = 1
3833 %}
3834
3835 //----------RESOURCES----------------------------------------------------------
3836 // Resources are the functional units available to the machine.
3837 resources(
3838 Z_BR, // branch unit
3839 Z_CR, // condition unit
3840 Z_FX1, // integer arithmetic unit 1
3841 Z_FX2, // integer arithmetic unit 2
3842 Z_LDST1, // load/store unit 1
3843 Z_LDST2, // load/store unit 2
3844 Z_FP1, // float arithmetic unit 1
3845 Z_FP2, // float arithmetic unit 2
3846 Z_LDST = Z_LDST1 | Z_LDST2,
3847 Z_FX = Z_FX1 | Z_FX2,
3848 Z_FP = Z_FP1 | Z_FP2
3849 );
3850
3851 //----------PIPELINE DESCRIPTION-----------------------------------------------
3852 // Pipeline Description specifies the stages in the machine's pipeline.
3853 pipe_desc(
3854 // TODO: adapt
3855 Z_IF, // instruction fetch
3856 Z_IC,
3857 Z_D0, // decode
3858 Z_D1, // decode
3859 Z_D2, // decode
3860 Z_D3, // decode
3861 Z_Xfer1,
3862 Z_GD, // group definition
3863 Z_MP, // map
3864 Z_ISS, // issue
3865 Z_RF, // resource fetch
3866 Z_EX1, // execute (all units)
3867 Z_EX2, // execute (FP, LDST)
3868 Z_EX3, // execute (FP, LDST)
3869 Z_EX4, // execute (FP)
3870 Z_EX5, // execute (FP)
3871 Z_EX6, // execute (FP)
3872 Z_WB, // write back
3873 Z_Xfer2,
3874 Z_CP
3875 );
3876
3877 //----------PIPELINE CLASSES---------------------------------------------------
3878 // Pipeline Classes describe the stages in which input and output are
3879 // referenced by the hardware pipeline.
3880
3881 // Providing the `ins_pipe' declarations in the instruction
3882 // specifications seems to be of little use. So we use
3883 // `pipe_class_dummy' for all our instructions at present.
3884 pipe_class pipe_class_dummy() %{
3885 single_instruction;
3886 fixed_latency(4);
3887 %}
3888
3889 // SIGTRAP based implicit range checks in compiled code.
3890 // Currently, no pipe classes are used on z/Architecture.
3891 pipe_class pipe_class_trap() %{
3892 single_instruction;
3893 %}
3894
3895 pipe_class pipe_class_fx_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
3896 single_instruction;
3897 dst : Z_EX1(write);
3898 src1 : Z_RF(read);
3899 src2 : Z_RF(read);
3900 Z_FX : Z_RF;
3901 %}
3902
3903 pipe_class pipe_class_ldst(iRegP dst, memory mem) %{
3904 single_instruction;
3905 mem : Z_RF(read);
3906 dst : Z_WB(write);
3907 Z_LDST : Z_RF;
3908 %}
3909
3910 define %{
3911 MachNop = pipe_class_dummy;
3912 %}
3913
3914 %}
3915
3916 //----------INSTRUCTIONS-------------------------------------------------------
3917
3918 //---------- Chain stack slots between similar types --------
3919
3920 // Load integer from stack slot.
3921 instruct stkI_to_regI(iRegI dst, stackSlotI src) %{
3922 match(Set dst src);
3923 ins_cost(MEMORY_REF_COST);
3924 // TODO: s390 port size(FIXED_SIZE);
3925 format %{ "L $dst,$src\t # stk reload int" %}
3926 opcode(L_ZOPC);
3927 ins_encode(z_form_rt_mem(dst, src));
3928 ins_pipe(pipe_class_dummy);
3929 %}
3930
3931 // Store integer to stack slot.
3932 instruct regI_to_stkI(stackSlotI dst, iRegI src) %{
3933 match(Set dst src);
3934 ins_cost(MEMORY_REF_COST);
3935 // TODO: s390 port size(FIXED_SIZE);
3936 format %{ "ST $src,$dst\t # stk spill int" %}
3937 opcode(ST_ZOPC);
3938 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
3939 ins_pipe(pipe_class_dummy);
3940 %}
3941
3942 // Load long from stack slot.
3943 instruct stkL_to_regL(iRegL dst, stackSlotL src) %{
3944 match(Set dst src);
3945 ins_cost(MEMORY_REF_COST);
3946 // TODO: s390 port size(FIXED_SIZE);
3947 format %{ "LG $dst,$src\t # stk reload long" %}
3948 opcode(LG_ZOPC);
3949 ins_encode(z_form_rt_mem(dst, src));
3950 ins_pipe(pipe_class_dummy);
3951 %}
3952
3953 // Store long to stack slot.
3954 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
3955 match(Set dst src);
3956 ins_cost(MEMORY_REF_COST);
3957 size(6);
3958 format %{ "STG $src,$dst\t # stk spill long" %}
3959 opcode(STG_ZOPC);
3960 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
3961 ins_pipe(pipe_class_dummy);
3962 %}
3963
3964 // Load pointer from stack slot, 64-bit encoding.
3965 instruct stkP_to_regP(iRegP dst, stackSlotP src) %{
3966 match(Set dst src);
3967 ins_cost(MEMORY_REF_COST);
3968 // TODO: s390 port size(FIXED_SIZE);
3969 format %{ "LG $dst,$src\t # stk reload ptr" %}
3970 opcode(LG_ZOPC);
3971 ins_encode(z_form_rt_mem(dst, src));
3972 ins_pipe(pipe_class_dummy);
3973 %}
3974
3975 // Store pointer to stack slot.
3976 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
3977 match(Set dst src);
3978 ins_cost(MEMORY_REF_COST);
3979 // TODO: s390 port size(FIXED_SIZE);
3980 format %{ "STG $src,$dst\t # stk spill ptr" %}
3981 opcode(STG_ZOPC);
3982 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
3983 ins_pipe(pipe_class_dummy);
3984 %}
3985
3986 // Float types
3987
3988 // Load float value from stack slot.
3989 instruct stkF_to_regF(regF dst, stackSlotF src) %{
3990 match(Set dst src);
3991 ins_cost(MEMORY_REF_COST);
3992 size(4);
3993 format %{ "LE(Y) $dst,$src\t # stk reload float" %}
3994 opcode(LE_ZOPC);
3995 ins_encode(z_form_rt_mem(dst, src));
3996 ins_pipe(pipe_class_dummy);
3997 %}
3998
3999 // Store float value to stack slot.
4000 instruct regF_to_stkF(stackSlotF dst, regF src) %{
4001 match(Set dst src);
4002 ins_cost(MEMORY_REF_COST);
4003 size(4);
4004 format %{ "STE(Y) $src,$dst\t # stk spill float" %}
4005 opcode(STE_ZOPC);
4006 ins_encode(z_form_rt_mem(src, dst));
4007 ins_pipe(pipe_class_dummy);
4008 %}
4009
4010 // Load double value from stack slot.
4011 instruct stkD_to_regD(regD dst, stackSlotD src) %{
4012 match(Set dst src);
4013 ins_cost(MEMORY_REF_COST);
4014 // TODO: s390 port size(FIXED_SIZE);
4015 format %{ "LD(Y) $dst,$src\t # stk reload double" %}
4016 opcode(LD_ZOPC);
4017 ins_encode(z_form_rt_mem(dst, src));
4018 ins_pipe(pipe_class_dummy);
4019 %}
4020
4021 // Store double value to stack slot.
4022 instruct regD_to_stkD(stackSlotD dst, regD src) %{
4023 match(Set dst src);
4024 ins_cost(MEMORY_REF_COST);
4025 size(4);
4026 format %{ "STD(Y) $src,$dst\t # stk spill double" %}
4027 opcode(STD_ZOPC);
4028 ins_encode(z_form_rt_mem(src, dst));
4029 ins_pipe(pipe_class_dummy);
4030 %}
4031
4032 //----------Load/Store/Move Instructions---------------------------------------
4033
4034 //----------Load Instructions--------------------------------------------------
4035
4036 //------------------
4037 // MEMORY
4038 //------------------
4039
4040 // BYTE
4041 // Load Byte (8bit signed)
4042 instruct loadB(iRegI dst, memory mem) %{
4043 match(Set dst (LoadB mem));
4044 ins_cost(MEMORY_REF_COST);
4045 size(Z_DISP3_SIZE);
4046 format %{ "LB $dst, $mem\t # sign-extend byte to int" %}
4047 opcode(LB_ZOPC, LB_ZOPC);
4048 ins_encode(z_form_rt_mem_opt(dst, mem));
4049 ins_pipe(pipe_class_dummy);
4050 %}
4051
4052 // Load Byte (8bit signed)
4053 instruct loadB2L(iRegL dst, memory mem) %{
4054 match(Set dst (ConvI2L (LoadB mem)));
4055 ins_cost(MEMORY_REF_COST);
4056 size(Z_DISP3_SIZE);
4057 format %{ "LGB $dst, $mem\t # sign-extend byte to long" %}
4058 opcode(LGB_ZOPC, LGB_ZOPC);
4059 ins_encode(z_form_rt_mem_opt(dst, mem));
4060 ins_pipe(pipe_class_dummy);
4061 %}
4062
4063 // Load Unsigned Byte (8bit UNsigned) into an int reg.
4064 instruct loadUB(iRegI dst, memory mem) %{
4065 match(Set dst (LoadUB mem));
4066 ins_cost(MEMORY_REF_COST);
4067 size(Z_DISP3_SIZE);
4068 format %{ "LLGC $dst,$mem\t # zero-extend byte to int" %}
4069 opcode(LLGC_ZOPC, LLGC_ZOPC);
4070 ins_encode(z_form_rt_mem_opt(dst, mem));
4071 ins_pipe(pipe_class_dummy);
4072 %}
4073
4074 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
4075 instruct loadUB2L(iRegL dst, memory mem) %{
4076 match(Set dst (ConvI2L (LoadUB mem)));
4077 ins_cost(MEMORY_REF_COST);
4078 size(Z_DISP3_SIZE);
4079 format %{ "LLGC $dst,$mem\t # zero-extend byte to long" %}
4080 opcode(LLGC_ZOPC, LLGC_ZOPC);
4081 ins_encode(z_form_rt_mem_opt(dst, mem));
4082 ins_pipe(pipe_class_dummy);
4083 %}
4084
4085 // CHAR/SHORT
4086
4087 // Load Short (16bit signed)
4088 instruct loadS(iRegI dst, memory mem) %{
4089 match(Set dst (LoadS mem));
4090 ins_cost(MEMORY_REF_COST);
4091 size(Z_DISP_SIZE);
4092 format %{ "LH(Y) $dst,$mem\t # sign-extend short to int" %}
4093 opcode(LHY_ZOPC, LH_ZOPC);
4094 ins_encode(z_form_rt_mem_opt(dst, mem));
4095 ins_pipe(pipe_class_dummy);
4096 %}
4097
4098 // Load Short (16bit signed)
4099 instruct loadS2L(iRegL dst, memory mem) %{
4100 match(Set dst (ConvI2L (LoadS mem)));
4101 ins_cost(MEMORY_REF_COST);
4102 size(Z_DISP3_SIZE);
4103 format %{ "LGH $dst,$mem\t # sign-extend short to long" %}
4104 opcode(LGH_ZOPC, LGH_ZOPC);
4105 ins_encode(z_form_rt_mem_opt(dst, mem));
4106 ins_pipe(pipe_class_dummy);
4107 %}
4108
4109 // Load Char (16bit Unsigned)
4110 instruct loadUS(iRegI dst, memory mem) %{
4111 match(Set dst (LoadUS mem));
4112 ins_cost(MEMORY_REF_COST);
4113 size(Z_DISP3_SIZE);
4114 format %{ "LLGH $dst,$mem\t # zero-extend short to int" %}
4115 opcode(LLGH_ZOPC, LLGH_ZOPC);
4116 ins_encode(z_form_rt_mem_opt(dst, mem));
4117 ins_pipe(pipe_class_dummy);
4118 %}
4119
4120 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
4121 instruct loadUS2L(iRegL dst, memory mem) %{
4122 match(Set dst (ConvI2L (LoadUS mem)));
4123 ins_cost(MEMORY_REF_COST);
4124 size(Z_DISP3_SIZE);
4125 format %{ "LLGH $dst,$mem\t # zero-extend short to long" %}
4126 opcode(LLGH_ZOPC, LLGH_ZOPC);
4127 ins_encode(z_form_rt_mem_opt(dst, mem));
4128 ins_pipe(pipe_class_dummy);
4129 %}
4130
4131 // INT
4132
4133 // Load Integer
4134 instruct loadI(iRegI dst, memory mem) %{
4135 match(Set dst (LoadI mem));
4136 ins_cost(MEMORY_REF_COST);
4137 size(Z_DISP_SIZE);
4138 format %{ "L(Y) $dst,$mem\t #" %}
4139 opcode(LY_ZOPC, L_ZOPC);
4140 ins_encode(z_form_rt_mem_opt(dst, mem));
4141 ins_pipe(pipe_class_dummy);
4142 %}
4143
4144 // Load and convert to long.
4145 instruct loadI2L(iRegL dst, memory mem) %{
4146 match(Set dst (ConvI2L (LoadI mem)));
4147 ins_cost(MEMORY_REF_COST);
4148 size(Z_DISP3_SIZE);
4149 format %{ "LGF $dst,$mem\t #" %}
4150 opcode(LGF_ZOPC, LGF_ZOPC);
4151 ins_encode(z_form_rt_mem_opt(dst, mem));
4152 ins_pipe(pipe_class_dummy);
4153 %}
4154
4155 // Load Unsigned Integer into a Long Register
4156 instruct loadUI2L(iRegL dst, memory mem, immL_FFFFFFFF mask) %{
4157 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4158 ins_cost(MEMORY_REF_COST);
4159 size(Z_DISP3_SIZE);
4160 format %{ "LLGF $dst,$mem\t # zero-extend int to long" %}
4161 opcode(LLGF_ZOPC, LLGF_ZOPC);
4162 ins_encode(z_form_rt_mem_opt(dst, mem));
4163 ins_pipe(pipe_class_dummy);
4164 %}
4165
4166 // range = array length (=jint)
4167 // Load Range
4168 instruct loadRange(iRegI dst, memory mem) %{
4169 match(Set dst (LoadRange mem));
4170 ins_cost(MEMORY_REF_COST);
4171 size(Z_DISP_SIZE);
4172 format %{ "L(Y) $dst,$mem\t # range" %}
4173 opcode(LY_ZOPC, L_ZOPC);
4174 ins_encode(z_form_rt_mem_opt(dst, mem));
4175 ins_pipe(pipe_class_dummy);
4176 %}
4177
4178 // LONG
4179
4180 // Load Long - aligned
4181 instruct loadL(iRegL dst, memory mem) %{
4182 match(Set dst (LoadL mem));
4183 ins_cost(MEMORY_REF_COST);
4184 size(Z_DISP3_SIZE);
4185 format %{ "LG $dst,$mem\t # long" %}
4186 opcode(LG_ZOPC, LG_ZOPC);
4187 ins_encode(z_form_rt_mem_opt(dst, mem));
4188 ins_pipe(pipe_class_dummy);
4189 %}
4190
4191 // Load Long - UNaligned
4192 instruct loadL_unaligned(iRegL dst, memory mem) %{
4193 match(Set dst (LoadL_unaligned mem));
4194 ins_cost(MEMORY_REF_COST);
4195 size(Z_DISP3_SIZE);
4196 format %{ "LG $dst,$mem\t # unaligned long" %}
4197 opcode(LG_ZOPC, LG_ZOPC);
4198 ins_encode(z_form_rt_mem_opt(dst, mem));
4199 ins_pipe(pipe_class_dummy);
4200 %}
4201
4202
4203 // PTR
4204
4205 // Load Pointer
4206 instruct loadP(iRegP dst, memory mem) %{
4207 match(Set dst (LoadP mem));
4208 ins_cost(MEMORY_REF_COST);
4209 size(Z_DISP3_SIZE);
4210 format %{ "LG $dst,$mem\t # ptr" %}
4211 opcode(LG_ZOPC, LG_ZOPC);
4212 ins_encode(z_form_rt_mem_opt(dst, mem));
4213 ins_pipe(pipe_class_dummy);
4214 %}
4215
4216 // LoadP + CastP2L
4217 instruct castP2X_loadP(iRegL dst, memory mem) %{
4218 match(Set dst (CastP2X (LoadP mem)));
4219 ins_cost(MEMORY_REF_COST);
4220 size(Z_DISP3_SIZE);
4221 format %{ "LG $dst,$mem\t # ptr + p2x" %}
4222 opcode(LG_ZOPC, LG_ZOPC);
4223 ins_encode(z_form_rt_mem_opt(dst, mem));
4224 ins_pipe(pipe_class_dummy);
4225 %}
4226
4227 // Load Klass Pointer
4228 instruct loadKlass(iRegP dst, memory mem) %{
4229 match(Set dst (LoadKlass mem));
4230 ins_cost(MEMORY_REF_COST);
4231 size(Z_DISP3_SIZE);
4232 format %{ "LG $dst,$mem\t # klass ptr" %}
4233 opcode(LG_ZOPC, LG_ZOPC);
4234 ins_encode(z_form_rt_mem_opt(dst, mem));
4235 ins_pipe(pipe_class_dummy);
4236 %}
4237
4238 instruct loadTOC(iRegL dst) %{
4239 effect(DEF dst);
4240 ins_cost(DEFAULT_COST);
4241 // TODO: s390 port size(FIXED_SIZE);
4242 // TODO: check why this attribute causes many unnecessary rematerializations.
4243 //
4244 // The graphs I saw just had high register pressure. Further the
4245 // register TOC is loaded to is overwritten by the constant short
4246 // after. Here something as round robin register allocation might
4247 // help. But rematerializing seems not to hurt, jack even seems to
4248 // improve slightly.
4249 //
4250 // Without this flag we get spill-split recycle sanity check
4251 // failures in
4252 // spec.benchmarks._228_jack.NfaState::GenerateCode. This happens in
4253 // a block with three loadConP_dynTOC nodes and a tlsLoadP. The
4254 // tlsLoadP has a huge amount of outs and forces the TOC down to the
4255 // stack. Later tlsLoadP is rematerialized, leaving the register
4256 // allocator with TOC on the stack and a badly placed reload.
4257 ins_should_rematerialize(true);
4258 format %{ "LARL $dst, &constant_pool\t; load dynTOC" %}
4259 ins_encode %{ __ load_toc($dst$$Register); %}
4260 ins_pipe(pipe_class_dummy);
4261 %}
4262
4263 // FLOAT
4264
4265 // Load Float
4266 instruct loadF(regF dst, memory mem) %{
4267 match(Set dst (LoadF mem));
4268 ins_cost(MEMORY_REF_COST);
4269 size(Z_DISP_SIZE);
4270 format %{ "LE(Y) $dst,$mem" %}
4271 opcode(LEY_ZOPC, LE_ZOPC);
4272 ins_encode(z_form_rt_mem_opt(dst, mem));
4273 ins_pipe(pipe_class_dummy);
4274 %}
4275
4276 // DOUBLE
4277
4278 // Load Double
4279 instruct loadD(regD dst, memory mem) %{
4280 match(Set dst (LoadD mem));
4281 ins_cost(MEMORY_REF_COST);
4282 size(Z_DISP_SIZE);
4283 format %{ "LD(Y) $dst,$mem" %}
4284 opcode(LDY_ZOPC, LD_ZOPC);
4285 ins_encode(z_form_rt_mem_opt(dst, mem));
4286 ins_pipe(pipe_class_dummy);
4287 %}
4288
4289 // Load Double - UNaligned
4290 instruct loadD_unaligned(regD dst, memory mem) %{
4291 match(Set dst (LoadD_unaligned mem));
4292 ins_cost(MEMORY_REF_COST);
4293 size(Z_DISP_SIZE);
4294 format %{ "LD(Y) $dst,$mem" %}
4295 opcode(LDY_ZOPC, LD_ZOPC);
4296 ins_encode(z_form_rt_mem_opt(dst, mem));
4297 ins_pipe(pipe_class_dummy);
4298 %}
4299
4300
4301 //----------------------
4302 // IMMEDIATES
4303 //----------------------
4304
4305 instruct loadConI(iRegI dst, immI src) %{
4306 match(Set dst src);
4307 ins_cost(DEFAULT_COST);
4308 size(6);
4309 format %{ "LGFI $dst,$src\t # (int)" %}
4310 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4311 ins_pipe(pipe_class_dummy);
4312 %}
4313
4314 instruct loadConI16(iRegI dst, immI16 src) %{
4315 match(Set dst src);
4316 ins_cost(DEFAULT_COST_LOW);
4317 size(4);
4318 format %{ "LGHI $dst,$src\t # (int)" %}
4319 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4320 ins_pipe(pipe_class_dummy);
4321 %}
4322
4323 instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{
4324 match(Set dst src);
4325 effect(KILL cr);
4326 ins_cost(DEFAULT_COST_LOW);
4327 size(4);
4328 format %{ "loadConI $dst,$src\t # (int) XGR because ZERO is loaded" %}
4329 opcode(XGR_ZOPC);
4330 ins_encode(z_rreform(dst, dst));
4331 ins_pipe(pipe_class_dummy);
4332 %}
4333
4334 instruct loadConUI16(iRegI dst, uimmI16 src) %{
4335 match(Set dst src);
4336 // TODO: s390 port size(FIXED_SIZE);
4337 format %{ "LLILL $dst,$src" %}
4338 opcode(LLILL_ZOPC);
4339 ins_encode(z_riform_unsigned(dst, src) );
4340 ins_pipe(pipe_class_dummy);
4341 %}
4342
4343 // Load long constant from TOC with pcrelative address.
4344 instruct loadConL_pcrelTOC(iRegL dst, immL src) %{
4345 match(Set dst src);
4346 ins_cost(MEMORY_REF_COST_LO);
4347 size(6);
4348 format %{ "LGRL $dst,[pcrelTOC]\t # load long $src from table" %}
4349 ins_encode %{
4350 address long_address = __ long_constant($src$$constant);
4351 if (long_address == NULL) {
4352 Compile::current()->env()->record_out_of_memory_failure();
4353 return;
4354 }
4355 __ load_long_pcrelative($dst$$Register, long_address);
4356 %}
4357 ins_pipe(pipe_class_dummy);
4358 %}
4359
4360 instruct loadConL32(iRegL dst, immL32 src) %{
4361 match(Set dst src);
4362 ins_cost(DEFAULT_COST);
4363 size(6);
4364 format %{ "LGFI $dst,$src\t # (long)" %}
4365 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4366 ins_pipe(pipe_class_dummy);
4367 %}
4368
4369 instruct loadConL16(iRegL dst, immL16 src) %{
4370 match(Set dst src);
4371 ins_cost(DEFAULT_COST_LOW);
4372 size(4);
4373 format %{ "LGHI $dst,$src\t # (long)" %}
4374 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4375 ins_pipe(pipe_class_dummy);
4376 %}
4377
4378 instruct loadConL_0(iRegL dst, immL_0 src, flagsReg cr) %{
4379 match(Set dst src);
4380 effect(KILL cr);
4381 ins_cost(DEFAULT_COST_LOW);
4382 format %{ "LoadConL $dst,$src\t # (long) XGR because ZERO is loaded" %}
4383 opcode(XGR_ZOPC);
4384 ins_encode(z_rreform(dst, dst));
4385 ins_pipe(pipe_class_dummy);
4386 %}
4387
4388 // Load ptr constant from TOC with pc relative address.
4389 // Special handling for oop constants required.
4390 instruct loadConP_pcrelTOC(iRegP dst, immP src) %{
4391 match(Set dst src);
4392 ins_cost(MEMORY_REF_COST_LO);
4393 size(6);
4394 format %{ "LGRL $dst,[pcrelTOC]\t # load ptr $src from table" %}
4395 ins_encode %{
4396 relocInfo::relocType constant_reloc = $src->constant_reloc();
4397 if (constant_reloc == relocInfo::oop_type) {
4398 AddressLiteral a = __ allocate_oop_address((jobject)$src$$constant);
4399 bool success = __ load_oop_from_toc($dst$$Register, a);
4400 if (!success) {
4401 Compile::current()->env()->record_out_of_memory_failure();
4402 return;
4403 }
4404 } else if (constant_reloc == relocInfo::metadata_type) {
4405 AddressLiteral a = __ constant_metadata_address((Metadata *)$src$$constant);
4406 address const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
4407 if (const_toc_addr == NULL) {
4408 Compile::current()->env()->record_out_of_memory_failure();
4409 return;
4410 }
4411 __ load_long_pcrelative($dst$$Register, const_toc_addr);
4412 } else { // Non-oop pointers, e.g. card mark base, heap top.
4413 address long_address = __ long_constant((jlong)$src$$constant);
4414 if (long_address == NULL) {
4415 Compile::current()->env()->record_out_of_memory_failure();
4416 return;
4417 }
4418 __ load_long_pcrelative($dst$$Register, long_address);
4419 }
4420 %}
4421 ins_pipe(pipe_class_dummy);
4422 %}
4423
4424 // We don't use immP16 to avoid problems with oops.
4425 instruct loadConP0(iRegP dst, immP0 src, flagsReg cr) %{
4426 match(Set dst src);
4427 effect(KILL cr);
4428 size(4);
4429 format %{ "XGR $dst,$dst\t # NULL ptr" %}
4430 opcode(XGR_ZOPC);
4431 ins_encode(z_rreform(dst, dst));
4432 ins_pipe(pipe_class_dummy);
4433 %}
4434
4435 //----------Load Float Constant Instructions-------------------------------------------------
4436
4437 // We may not specify this instruction via an `expand' rule. If we do,
4438 // code selection will forget that this instruction needs a floating
4439 // point constant inserted into the code buffer. So `Shorten_branches'
4440 // will fail.
4441 instruct loadConF_dynTOC(regF dst, immF src, flagsReg cr) %{
4442 match(Set dst src);
4443 effect(KILL cr);
4444 ins_cost(MEMORY_REF_COST);
4445 size(6);
4446 // If this instruction rematerializes, it prolongs the live range
4447 // of the toc node, causing illegal graphs.
4448 ins_cannot_rematerialize(true);
4449 format %{ "LE(Y) $dst,$constantoffset[,$constanttablebase]\t # load FLOAT $src from table" %}
4450 ins_encode %{
4451 __ load_float_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4452 %}
4453 ins_pipe(pipe_class_dummy);
4454 %}
4455
4456 // E may not specify this instruction via an `expand' rule. If we do,
4457 // code selection will forget that this instruction needs a floating
4458 // point constant inserted into the code buffer. So `Shorten_branches'
4459 // will fail.
4460 instruct loadConD_dynTOC(regD dst, immD src, flagsReg cr) %{
4461 match(Set dst src);
4462 effect(KILL cr);
4463 ins_cost(MEMORY_REF_COST);
4464 size(6);
4465 // If this instruction rematerializes, it prolongs the live range
4466 // of the toc node, causing illegal graphs.
4467 ins_cannot_rematerialize(true);
4468 format %{ "LD(Y) $dst,$constantoffset[,$constanttablebase]\t # load DOUBLE $src from table" %}
4469 ins_encode %{
4470 __ load_double_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4471 %}
4472 ins_pipe(pipe_class_dummy);
4473 %}
4474
4475 // Special case: Load Const 0.0F
4476
4477 // There's a special instr to clear a FP register.
4478 instruct loadConF0(regF dst, immFp0 src) %{
4479 match(Set dst src);
4480 ins_cost(DEFAULT_COST_LOW);
4481 size(4);
4482 format %{ "LZER $dst,$src\t # clear to zero" %}
4483 opcode(LZER_ZOPC);
4484 ins_encode(z_rreform(dst, Z_F0));
4485 ins_pipe(pipe_class_dummy);
4486 %}
4487
4488 // There's a special instr to clear a FP register.
4489 instruct loadConD0(regD dst, immDp0 src) %{
4490 match(Set dst src);
4491 ins_cost(DEFAULT_COST_LOW);
4492 size(4);
4493 format %{ "LZDR $dst,$src\t # clear to zero" %}
4494 opcode(LZDR_ZOPC);
4495 ins_encode(z_rreform(dst, Z_F0));
4496 ins_pipe(pipe_class_dummy);
4497 %}
4498
4499
4500 //----------Store Instructions-------------------------------------------------
4501
4502 // BYTE
4503
4504 // Store Byte
4505 instruct storeB(memory mem, iRegI src) %{
4506 match(Set mem (StoreB mem src));
4507 ins_cost(MEMORY_REF_COST);
4508 size(Z_DISP_SIZE);
4509 format %{ "STC(Y) $src,$mem\t # byte" %}
4510 opcode(STCY_ZOPC, STC_ZOPC);
4511 ins_encode(z_form_rt_mem_opt(src, mem));
4512 ins_pipe(pipe_class_dummy);
4513 %}
4514
4515 instruct storeCM(memory mem, immI_0 src) %{
4516 match(Set mem (StoreCM mem src));
4517 ins_cost(MEMORY_REF_COST);
4518 // TODO: s390 port size(VARIABLE_SIZE);
4519 format %{ "STC(Y) $src,$mem\t # CMS card-mark byte (must be 0!)" %}
4520 ins_encode %{
4521 guarantee($mem$$index$$Register != Z_R0, "content will not be used.");
4522 if ($mem$$index$$Register != noreg) {
4523 // Can't use clear_mem --> load const zero and store character.
4524 __ load_const_optimized(Z_R0_scratch, (long)0);
4525 if (Immediate::is_uimm12($mem$$disp)) {
4526 __ z_stc(Z_R0_scratch, $mem$$Address);
4527 } else {
4528 __ z_stcy(Z_R0_scratch, $mem$$Address);
4529 }
4530 } else {
4531 __ clear_mem(Address($mem$$Address), 1);
4532 }
4533 %}
4534 ins_pipe(pipe_class_dummy);
4535 %}
4536
4537 // CHAR/SHORT
4538
4539 // Store Char/Short
4540 instruct storeC(memory mem, iRegI src) %{
4541 match(Set mem (StoreC mem src));
4542 ins_cost(MEMORY_REF_COST);
4543 size(Z_DISP_SIZE);
4544 format %{ "STH(Y) $src,$mem\t # short" %}
4545 opcode(STHY_ZOPC, STH_ZOPC);
4546 ins_encode(z_form_rt_mem_opt(src, mem));
4547 ins_pipe(pipe_class_dummy);
4548 %}
4549
4550 // INT
4551
4552 // Store Integer
4553 instruct storeI(memory mem, iRegI src) %{
4554 match(Set mem (StoreI mem src));
4555 ins_cost(MEMORY_REF_COST);
4556 size(Z_DISP_SIZE);
4557 format %{ "ST(Y) $src,$mem\t # int" %}
4558 opcode(STY_ZOPC, ST_ZOPC);
4559 ins_encode(z_form_rt_mem_opt(src, mem));
4560 ins_pipe(pipe_class_dummy);
4561 %}
4562
4563 // LONG
4564
4565 // Store Long
4566 instruct storeL(memory mem, iRegL src) %{
4567 match(Set mem (StoreL mem src));
4568 ins_cost(MEMORY_REF_COST);
4569 size(Z_DISP3_SIZE);
4570 format %{ "STG $src,$mem\t # long" %}
4571 opcode(STG_ZOPC, STG_ZOPC);
4572 ins_encode(z_form_rt_mem_opt(src, mem));
4573 ins_pipe(pipe_class_dummy);
4574 %}
4575
4576 // PTR
4577
4578 // Store Pointer
4579 instruct storeP(memory dst, memoryRegP src) %{
4580 match(Set dst (StoreP dst src));
4581 ins_cost(MEMORY_REF_COST);
4582 size(Z_DISP3_SIZE);
4583 format %{ "STG $src,$dst\t # ptr" %}
4584 opcode(STG_ZOPC, STG_ZOPC);
4585 ins_encode(z_form_rt_mem_opt(src, dst));
4586 ins_pipe(pipe_class_dummy);
4587 %}
4588
4589 // FLOAT
4590
4591 // Store Float
4592 instruct storeF(memory mem, regF src) %{
4593 match(Set mem (StoreF mem src));
4594 ins_cost(MEMORY_REF_COST);
4595 size(Z_DISP_SIZE);
4596 format %{ "STE(Y) $src,$mem\t # float" %}
4597 opcode(STEY_ZOPC, STE_ZOPC);
4598 ins_encode(z_form_rt_mem_opt(src, mem));
4599 ins_pipe(pipe_class_dummy);
4600 %}
4601
4602 // DOUBLE
4603
4604 // Store Double
4605 instruct storeD(memory mem, regD src) %{
4606 match(Set mem (StoreD mem src));
4607 ins_cost(MEMORY_REF_COST);
4608 size(Z_DISP_SIZE);
4609 format %{ "STD(Y) $src,$mem\t # double" %}
4610 opcode(STDY_ZOPC, STD_ZOPC);
4611 ins_encode(z_form_rt_mem_opt(src, mem));
4612 ins_pipe(pipe_class_dummy);
4613 %}
4614
4615 // Prefetch instructions. Must be safe to execute with invalid address (cannot fault).
4616
4617 // Should support match rule for PrefetchAllocation.
4618 // Still needed after 8068977 for PrefetchAllocate.
4619 instruct prefetchAlloc(memory mem) %{
4620 match(PrefetchAllocation mem);
4621 predicate(VM_Version::has_Prefetch());
4622 ins_cost(DEFAULT_COST);
4623 format %{ "PREFETCH 2, $mem\t # Prefetch allocation, z10 only" %}
4624 ins_encode %{ __ z_pfd(0x02, $mem$$Address); %}
4625 ins_pipe(pipe_class_dummy);
4626 %}
4627
4628 //----------Memory init instructions------------------------------------------
4629
4630 // Move Immediate to 1-byte memory.
4631 instruct memInitB(memoryRSY mem, immI8 src) %{
4632 match(Set mem (StoreB mem src));
4633 ins_cost(MEMORY_REF_COST);
4634 // TODO: s390 port size(VARIABLE_SIZE);
4635 format %{ "MVI $mem,$src\t # direct mem init 1" %}
4636 ins_encode %{
4637 if (Immediate::is_uimm12((long)$mem$$disp)) {
4638 __ z_mvi($mem$$Address, $src$$constant);
4639 } else {
4640 __ z_mviy($mem$$Address, $src$$constant);
4641 }
4642 %}
4643 ins_pipe(pipe_class_dummy);
4644 %}
4645
4646 // Move Immediate to 2-byte memory.
4647 instruct memInitC(memoryRS mem, immI16 src) %{
4648 match(Set mem (StoreC mem src));
4649 ins_cost(MEMORY_REF_COST);
4650 size(6);
4651 format %{ "MVHHI $mem,$src\t # direct mem init 2" %}
4652 opcode(MVHHI_ZOPC);
4653 ins_encode(z_silform(mem, src));
4654 ins_pipe(pipe_class_dummy);
4655 %}
4656
4657 // Move Immediate to 4-byte memory.
4658 instruct memInitI(memoryRS mem, immI16 src) %{
4659 match(Set mem (StoreI mem src));
4660 ins_cost(MEMORY_REF_COST);
4661 size(6);
4662 format %{ "MVHI $mem,$src\t # direct mem init 4" %}
4663 opcode(MVHI_ZOPC);
4664 ins_encode(z_silform(mem, src));
4665 ins_pipe(pipe_class_dummy);
4666 %}
4667
4668
4669 // Move Immediate to 8-byte memory.
4670 instruct memInitL(memoryRS mem, immL16 src) %{
4671 match(Set mem (StoreL mem src));
4672 ins_cost(MEMORY_REF_COST);
4673 size(6);
4674 format %{ "MVGHI $mem,$src\t # direct mem init 8" %}
4675 opcode(MVGHI_ZOPC);
4676 ins_encode(z_silform(mem, src));
4677 ins_pipe(pipe_class_dummy);
4678 %}
4679
4680 // Move Immediate to 8-byte memory.
4681 instruct memInitP(memoryRS mem, immP16 src) %{
4682 match(Set mem (StoreP mem src));
4683 ins_cost(MEMORY_REF_COST);
4684 size(6);
4685 format %{ "MVGHI $mem,$src\t # direct mem init 8" %}
4686 opcode(MVGHI_ZOPC);
4687 ins_encode(z_silform(mem, src));
4688 ins_pipe(pipe_class_dummy);
4689 %}
4690
4691
4692 //----------Instructions for compressed pointers (cOop and NKlass)-------------
4693
4694 // See cOop encoding classes for elaborate comment.
4695
4696 // Moved here because it is needed in expand rules for encode.
4697 // Long negation.
4698 instruct negL_reg_reg(iRegL dst, immL_0 zero, iRegL src, flagsReg cr) %{
4699 match(Set dst (SubL zero src));
4700 effect(KILL cr);
4701 size(4);
4702 format %{ "NEG $dst, $src\t # long" %}
4703 ins_encode %{ __ z_lcgr($dst$$Register, $src$$Register); %}
4704 ins_pipe(pipe_class_dummy);
4705 %}
4706
4707 // Load Compressed Pointer
4708
4709 // Load narrow oop
4710 instruct loadN(iRegN dst, memory mem) %{
4711 match(Set dst (LoadN mem));
4712 ins_cost(MEMORY_REF_COST);
4713 size(Z_DISP3_SIZE);
4714 format %{ "LoadN $dst,$mem\t# (cOop)" %}
4715 opcode(LLGF_ZOPC, LLGF_ZOPC);
4716 ins_encode(z_form_rt_mem_opt(dst, mem));
4717 ins_pipe(pipe_class_dummy);
4718 %}
4719
4720 // Load narrow Klass Pointer
4721 instruct loadNKlass(iRegN dst, memory mem) %{
4722 match(Set dst (LoadNKlass mem));
4723 ins_cost(MEMORY_REF_COST);
4724 size(Z_DISP3_SIZE);
4725 format %{ "LoadNKlass $dst,$mem\t# (klass cOop)" %}
4726 opcode(LLGF_ZOPC, LLGF_ZOPC);
4727 ins_encode(z_form_rt_mem_opt(dst, mem));
4728 ins_pipe(pipe_class_dummy);
4729 %}
4730
4731 // Load constant Compressed Pointer
4732
4733 instruct loadConN(iRegN dst, immN src) %{
4734 match(Set dst src);
4735 ins_cost(DEFAULT_COST);
4736 size(6);
4737 format %{ "loadConN $dst,$src\t # (cOop)" %}
4738 ins_encode %{
4739 AddressLiteral cOop = __ constant_oop_address((jobject)$src$$constant);
4740 __ relocate(cOop.rspec(), 1);
4741 __ load_narrow_oop($dst$$Register, (narrowOop)cOop.value());
4742 %}
4743 ins_pipe(pipe_class_dummy);
4744 %}
4745
4746 instruct loadConN0(iRegN dst, immN0 src, flagsReg cr) %{
4747 match(Set dst src);
4748 effect(KILL cr);
4749 ins_cost(DEFAULT_COST_LOW);
4750 size(4);
4751 format %{ "loadConN $dst,$src\t # (cOop) XGR because ZERO is loaded" %}
4752 opcode(XGR_ZOPC);
4753 ins_encode(z_rreform(dst, dst));
4754 ins_pipe(pipe_class_dummy);
4755 %}
4756
4757 instruct loadConNKlass(iRegN dst, immNKlass src) %{
4758 match(Set dst src);
4759 ins_cost(DEFAULT_COST);
4760 size(6);
4761 format %{ "loadConNKlass $dst,$src\t # (cKlass)" %}
4762 ins_encode %{
4763 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4764 __ relocate(NKlass.rspec(), 1);
4765 __ load_narrow_klass($dst$$Register, (Klass*)NKlass.value());
4766 %}
4767 ins_pipe(pipe_class_dummy);
4768 %}
4769
4770 // Load and Decode Compressed Pointer
4771 // optimized variants for Unscaled cOops
4772
4773 instruct decodeLoadN(iRegP dst, memory mem) %{
4774 match(Set dst (DecodeN (LoadN mem)));
4775 predicate(false && (Universe::narrow_oop_base()==NULL)&&(Universe::narrow_oop_shift()==0));
4776 ins_cost(MEMORY_REF_COST);
4777 size(Z_DISP3_SIZE);
4778 format %{ "DecodeLoadN $dst,$mem\t# (cOop Load+Decode)" %}
4779 opcode(LLGF_ZOPC, LLGF_ZOPC);
4780 ins_encode(z_form_rt_mem_opt(dst, mem));
4781 ins_pipe(pipe_class_dummy);
4782 %}
4783
4784 instruct decodeLoadNKlass(iRegP dst, memory mem) %{
4785 match(Set dst (DecodeNKlass (LoadNKlass mem)));
4786 predicate(false && (Universe::narrow_klass_base()==NULL)&&(Universe::narrow_klass_shift()==0));
4787 ins_cost(MEMORY_REF_COST);
4788 size(Z_DISP3_SIZE);
4789 format %{ "DecodeLoadNKlass $dst,$mem\t# (load/decode NKlass)" %}
4790 opcode(LLGF_ZOPC, LLGF_ZOPC);
4791 ins_encode(z_form_rt_mem_opt(dst, mem));
4792 ins_pipe(pipe_class_dummy);
4793 %}
4794
4795 instruct decodeLoadConNKlass(iRegP dst, immNKlass src) %{
4796 match(Set dst (DecodeNKlass src));
4797 ins_cost(3 * DEFAULT_COST);
4798 size(12);
4799 format %{ "DecodeLoadConNKlass $dst,$src\t # decode(cKlass)" %}
4800 ins_encode %{
4801 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4802 __ relocate(NKlass.rspec(), 1);
4803 __ load_const($dst$$Register, (Klass*)NKlass.value());
4804 %}
4805 ins_pipe(pipe_class_dummy);
4806 %}
4807
4808 // Decode Compressed Pointer
4809
4810 // General decoder
4811 instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{
4812 match(Set dst (DecodeN src));
4813 effect(KILL cr);
4814 predicate(Universe::narrow_oop_base() == NULL || !ExpandLoadingBaseDecode);
4815 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
4816 // TODO: s390 port size(VARIABLE_SIZE);
4817 format %{ "decodeN $dst,$src\t# (decode cOop)" %}
4818 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true); %}
4819 ins_pipe(pipe_class_dummy);
4820 %}
4821
4822 // General Klass decoder
4823 instruct decodeKlass(iRegP dst, iRegN src, flagsReg cr) %{
4824 match(Set dst (DecodeNKlass src));
4825 effect(KILL cr);
4826 ins_cost(3 * DEFAULT_COST);
4827 format %{ "decode_klass $dst,$src" %}
4828 ins_encode %{ __ decode_klass_not_null($dst$$Register, $src$$Register); %}
4829 ins_pipe(pipe_class_dummy);
4830 %}
4831
4832 // General decoder
4833 instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{
4834 match(Set dst (DecodeN src));
4835 effect(KILL cr);
4836 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
4837 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
4838 (Universe::narrow_oop_base()== NULL || !ExpandLoadingBaseDecode_NN));
4839 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4840 // TODO: s390 port size(VARIABLE_SIZE);
4841 format %{ "decodeN $dst,$src\t# (decode cOop NN)" %}
4842 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %}
4843 ins_pipe(pipe_class_dummy);
4844 %}
4845
4846 instruct loadBase(iRegL dst, immL baseImm) %{
4847 effect(DEF dst, USE baseImm);
4848 predicate(false);
4849 format %{ "llihl $dst=$baseImm \t// load heap base" %}
4850 ins_encode %{ __ get_oop_base($dst$$Register, $baseImm$$constant); %}
4851 ins_pipe(pipe_class_dummy);
4852 %}
4853
4854 // Decoder for heapbased mode peeling off loading the base.
4855 instruct decodeN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
4856 match(Set dst (DecodeN src base));
4857 // Note: Effect TEMP dst was used with the intention to get
4858 // different regs for dst and base, but this has caused ADLC to
4859 // generate wrong code. Oop_decoder generates additional lgr when
4860 // dst==base.
4861 effect(KILL cr);
4862 predicate(false);
4863 // TODO: s390 port size(VARIABLE_SIZE);
4864 format %{ "decodeN $dst = ($src == 0) ? NULL : ($src << 3) + $base + pow2_offset\t# (decode cOop)" %}
4865 ins_encode %{
4866 __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register,
4867 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)Universe::narrow_oop_base()));
4868 %}
4869 ins_pipe(pipe_class_dummy);
4870 %}
4871
4872 // Decoder for heapbased mode peeling off loading the base.
4873 instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
4874 match(Set dst (DecodeN src base));
4875 effect(KILL cr);
4876 predicate(false);
4877 // TODO: s390 port size(VARIABLE_SIZE);
4878 format %{ "decodeN $dst = ($src << 3) + $base + pow2_offset\t# (decode cOop)" %}
4879 ins_encode %{
4880 __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register,
4881 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)Universe::narrow_oop_base()));
4882 %}
4883 ins_pipe(pipe_class_dummy);
4884 %}
4885
4886 // Decoder for heapbased mode peeling off loading the base.
4887 instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
4888 match(Set dst (DecodeN src));
4889 predicate(Universe::narrow_oop_base() != NULL && ExpandLoadingBaseDecode);
4890 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
4891 // TODO: s390 port size(VARIABLE_SIZE);
4892 expand %{
4893 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %}
4894 iRegL base;
4895 loadBase(base, baseImm);
4896 decodeN_base(dst, src, base, cr);
4897 %}
4898 %}
4899
4900 // Decoder for heapbased mode peeling off loading the base.
4901 instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
4902 match(Set dst (DecodeN src));
4903 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
4904 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
4905 Universe::narrow_oop_base() != NULL && ExpandLoadingBaseDecode_NN);
4906 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4907 // TODO: s390 port size(VARIABLE_SIZE);
4908 expand %{
4909 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %}
4910 iRegL base;
4911 loadBase(base, baseImm);
4912 decodeN_NN_base(dst, src, base, cr);
4913 %}
4914 %}
4915
4916 // Encode Compressed Pointer
4917
4918 // General encoder
4919 instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{
4920 match(Set dst (EncodeP src));
4921 effect(KILL cr);
4922 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
4923 (Universe::narrow_oop_base() == 0 ||
4924 Universe::narrow_oop_base_disjoint() ||
4925 !ExpandLoadingBaseEncode));
4926 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
4927 // TODO: s390 port size(VARIABLE_SIZE);
4928 format %{ "encodeP $dst,$src\t# (encode cOop)" %}
4929 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
4930 ins_pipe(pipe_class_dummy);
4931 %}
4932
4933 // General class encoder
4934 instruct encodeKlass(iRegN dst, iRegP src, flagsReg cr) %{
4935 match(Set dst (EncodePKlass src));
4936 effect(KILL cr);
4937 format %{ "encode_klass $dst,$src" %}
4938 ins_encode %{ __ encode_klass_not_null($dst$$Register, $src$$Register); %}
4939 ins_pipe(pipe_class_dummy);
4940 %}
4941
4942 instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{
4943 match(Set dst (EncodeP src));
4944 effect(KILL cr);
4945 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
4946 (Universe::narrow_oop_base() == 0 ||
4947 Universe::narrow_oop_base_disjoint() ||
4948 !ExpandLoadingBaseEncode_NN));
4949 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
4950 // TODO: s390 port size(VARIABLE_SIZE);
4951 format %{ "encodeP $dst,$src\t# (encode cOop)" %}
4952 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
4953 ins_pipe(pipe_class_dummy);
4954 %}
4955
4956 // Encoder for heapbased mode peeling off loading the base.
4957 instruct encodeP_base(iRegN dst, iRegP src, iRegL base) %{
4958 match(Set dst (EncodeP src (Binary base dst)));
4959 effect(TEMP_DEF dst);
4960 predicate(false);
4961 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4962 // TODO: s390 port size(VARIABLE_SIZE);
4963 format %{ "encodeP $dst = ($src>>3) +$base + pow2_offset\t# (encode cOop)" %}
4964 ins_encode %{
4965 jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset
4966 (((uint64_t)(intptr_t)Universe::narrow_oop_base()) >> Universe::narrow_oop_shift());
4967 __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset);
4968 %}
4969 ins_pipe(pipe_class_dummy);
4970 %}
4971
4972 // Encoder for heapbased mode peeling off loading the base.
4973 instruct encodeP_NN_base(iRegN dst, iRegP src, iRegL base, immL pow2_offset) %{
4974 match(Set dst (EncodeP src base));
4975 effect(USE pow2_offset);
4976 predicate(false);
4977 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4978 // TODO: s390 port size(VARIABLE_SIZE);
4979 format %{ "encodeP $dst = ($src>>3) +$base + $pow2_offset\t# (encode cOop)" %}
4980 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %}
4981 ins_pipe(pipe_class_dummy);
4982 %}
4983
4984 // Encoder for heapbased mode peeling off loading the base.
4985 instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{
4986 match(Set dst (EncodeP src));
4987 effect(KILL cr);
4988 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
4989 (Universe::narrow_oop_base_overlaps() && ExpandLoadingBaseEncode));
4990 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
4991 // TODO: s390 port size(VARIABLE_SIZE);
4992 expand %{
4993 immL baseImm %{ ((jlong)(intptr_t)Universe::narrow_oop_base()) >> Universe::narrow_oop_shift() %}
4994 immL_0 zero %{ (0) %}
4995 flagsReg ccr;
4996 iRegL base;
4997 iRegL negBase;
4998 loadBase(base, baseImm);
4999 negL_reg_reg(negBase, zero, base, ccr);
5000 encodeP_base(dst, src, negBase);
5001 %}
5002 %}
5003
5004 // Encoder for heapbased mode peeling off loading the base.
5005 instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{
5006 match(Set dst (EncodeP src));
5007 effect(KILL cr);
5008 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
5009 (Universe::narrow_oop_base_overlaps() && ExpandLoadingBaseEncode_NN));
5010 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5011 // TODO: s390 port size(VARIABLE_SIZE);
5012 expand %{
5013 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %}
5014 immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)Universe::narrow_oop_base())) %}
5015 immL_0 zero %{ 0 %}
5016 flagsReg ccr;
5017 iRegL base;
5018 iRegL negBase;
5019 loadBase(base, baseImm);
5020 negL_reg_reg(negBase, zero, base, ccr);
5021 encodeP_NN_base(dst, src, negBase, pow2_offset);
5022 %}
5023 %}
5024
5025 // Store Compressed Pointer
5026
5027 // Store Compressed Pointer
5028 instruct storeN(memory mem, iRegN_P2N src) %{
5029 match(Set mem (StoreN mem src));
5030 ins_cost(MEMORY_REF_COST);
5031 size(Z_DISP_SIZE);
5032 format %{ "ST $src,$mem\t# (cOop)" %}
5033 opcode(STY_ZOPC, ST_ZOPC);
5034 ins_encode(z_form_rt_mem_opt(src, mem));
5035 ins_pipe(pipe_class_dummy);
5036 %}
5037
5038 // Store Compressed Klass pointer
5039 instruct storeNKlass(memory mem, iRegN src) %{
5040 match(Set mem (StoreNKlass mem src));
5041 ins_cost(MEMORY_REF_COST);
5042 size(Z_DISP_SIZE);
5043 format %{ "ST $src,$mem\t# (cKlass)" %}
5044 opcode(STY_ZOPC, ST_ZOPC);
5045 ins_encode(z_form_rt_mem_opt(src, mem));
5046 ins_pipe(pipe_class_dummy);
5047 %}
5048
5049 // Compare Compressed Pointers
5050
5051 instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{
5052 match(Set cr (CmpN src1 src2));
5053 ins_cost(DEFAULT_COST);
5054 size(2);
5055 format %{ "CLR $src1,$src2\t# (cOop)" %}
5056 opcode(CLR_ZOPC);
5057 ins_encode(z_rrform(src1, src2));
5058 ins_pipe(pipe_class_dummy);
5059 %}
5060
5061 instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{
5062 match(Set cr (CmpN src1 src2));
5063 ins_cost(DEFAULT_COST);
5064 size(6);
5065 format %{ "CLFI $src1,$src2\t# (cOop) compare immediate narrow" %}
5066 ins_encode %{
5067 AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant);
5068 __ relocate(cOop.rspec(), 1);
5069 __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value());
5070 %}
5071 ins_pipe(pipe_class_dummy);
5072 %}
5073
5074 instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{
5075 match(Set cr (CmpN src1 src2));
5076 ins_cost(DEFAULT_COST);
5077 size(6);
5078 format %{ "CLFI $src1,$src2\t# (NKlass) compare immediate narrow" %}
5079 ins_encode %{
5080 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant);
5081 __ relocate(NKlass.rspec(), 1);
5082 __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value());
5083 %}
5084 ins_pipe(pipe_class_dummy);
5085 %}
5086
5087 instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{
5088 match(Set cr (CmpN src1 src2));
5089 ins_cost(DEFAULT_COST);
5090 size(2);
5091 format %{ "LTR $src1,$src2\t# (cOop) LTR because comparing against zero" %}
5092 opcode(LTR_ZOPC);
5093 ins_encode(z_rrform(src1, src1));
5094 ins_pipe(pipe_class_dummy);
5095 %}
5096
5097
5098 //----------MemBar Instructions-----------------------------------------------
5099
5100 // Memory barrier flavors
5101
5102 instruct membar_acquire() %{
5103 match(MemBarAcquire);
5104 match(LoadFence);
5105 ins_cost(4*MEMORY_REF_COST);
5106 size(0);
5107 format %{ "MEMBAR-acquire" %}
5108 ins_encode %{ __ z_acquire(); %}
5109 ins_pipe(pipe_class_dummy);
5110 %}
5111
5112 instruct membar_acquire_lock() %{
5113 match(MemBarAcquireLock);
5114 ins_cost(0);
5115 size(0);
5116 format %{ "MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
5117 ins_encode(/*empty*/);
5118 ins_pipe(pipe_class_dummy);
5119 %}
5120
5121 instruct membar_release() %{
5122 match(MemBarRelease);
5123 match(StoreFence);
5124 ins_cost(4 * MEMORY_REF_COST);
5125 size(0);
5126 format %{ "MEMBAR-release" %}
5127 ins_encode %{ __ z_release(); %}
5128 ins_pipe(pipe_class_dummy);
5129 %}
5130
5131 instruct membar_release_lock() %{
5132 match(MemBarReleaseLock);
5133 ins_cost(0);
5134 size(0);
5135 format %{ "MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
5136 ins_encode(/*empty*/);
5137 ins_pipe(pipe_class_dummy);
5138 %}
5139
5140 instruct membar_volatile() %{
5141 match(MemBarVolatile);
5142 ins_cost(4 * MEMORY_REF_COST);
5143 size(2);
5144 format %{ "MEMBAR-volatile" %}
5145 ins_encode %{ __ z_fence(); %}
5146 ins_pipe(pipe_class_dummy);
5147 %}
5148
5149 instruct unnecessary_membar_volatile() %{
5150 match(MemBarVolatile);
5151 predicate(Matcher::post_store_load_barrier(n));
5152 ins_cost(0);
5153 size(0);
5154 format %{ "# MEMBAR-volatile (empty)" %}
5155 ins_encode(/*empty*/);
5156 ins_pipe(pipe_class_dummy);
5157 %}
5158
5159 instruct membar_CPUOrder() %{
5160 match(MemBarCPUOrder);
5161 ins_cost(0);
5162 // TODO: s390 port size(FIXED_SIZE);
5163 format %{ "MEMBAR-CPUOrder (empty)" %}
5164 ins_encode(/*empty*/);
5165 ins_pipe(pipe_class_dummy);
5166 %}
5167
5168 instruct membar_storestore() %{
5169 match(MemBarStoreStore);
5170 ins_cost(0);
5171 size(0);
5172 format %{ "MEMBAR-storestore (empty)" %}
5173 ins_encode();
5174 ins_pipe(pipe_class_dummy);
5175 %}
5176
5177
5178 //----------Register Move Instructions-----------------------------------------
5179 instruct roundDouble_nop(regD dst) %{
5180 match(Set dst (RoundDouble dst));
5181 ins_cost(0);
5182 // TODO: s390 port size(FIXED_SIZE);
5183 // z/Architecture results are already "rounded" (i.e., normal-format IEEE).
5184 ins_encode();
5185 ins_pipe(pipe_class_dummy);
5186 %}
5187
5188 instruct roundFloat_nop(regF dst) %{
5189 match(Set dst (RoundFloat dst));
5190 ins_cost(0);
5191 // TODO: s390 port size(FIXED_SIZE);
5192 // z/Architecture results are already "rounded" (i.e., normal-format IEEE).
5193 ins_encode();
5194 ins_pipe(pipe_class_dummy);
5195 %}
5196
5197 // Cast Long to Pointer for unsafe natives.
5198 instruct castX2P(iRegP dst, iRegL src) %{
5199 match(Set dst (CastX2P src));
5200 // TODO: s390 port size(VARIABLE_SIZE);
5201 format %{ "LGR $dst,$src\t # CastX2P" %}
5202 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5203 ins_pipe(pipe_class_dummy);
5204 %}
5205
5206 // Cast Pointer to Long for unsafe natives.
5207 instruct castP2X(iRegL dst, iRegP_N2P src) %{
5208 match(Set dst (CastP2X src));
5209 // TODO: s390 port size(VARIABLE_SIZE);
5210 format %{ "LGR $dst,$src\t # CastP2X" %}
5211 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5212 ins_pipe(pipe_class_dummy);
5213 %}
5214
5215 instruct stfSSD(stackSlotD stkSlot, regD src) %{
5216 // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5217 match(Set stkSlot src); // chain rule
5218 ins_cost(MEMORY_REF_COST);
5219 // TODO: s390 port size(FIXED_SIZE);
5220 format %{ " STD $src,$stkSlot\t # stk" %}
5221 opcode(STD_ZOPC);
5222 ins_encode(z_form_rt_mem(src, stkSlot));
5223 ins_pipe(pipe_class_dummy);
5224 %}
5225
5226 instruct stfSSF(stackSlotF stkSlot, regF src) %{
5227 // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5228 match(Set stkSlot src); // chain rule
5229 ins_cost(MEMORY_REF_COST);
5230 // TODO: s390 port size(FIXED_SIZE);
5231 format %{ "STE $src,$stkSlot\t # stk" %}
5232 opcode(STE_ZOPC);
5233 ins_encode(z_form_rt_mem(src, stkSlot));
5234 ins_pipe(pipe_class_dummy);
5235 %}
5236
5237 //----------Conditional Move---------------------------------------------------
5238
5239 instruct cmovN_reg(cmpOp cmp, flagsReg cr, iRegN dst, iRegN_P2N src) %{
5240 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5241 ins_cost(DEFAULT_COST + BRANCH_COST);
5242 // TODO: s390 port size(VARIABLE_SIZE);
5243 format %{ "CMoveN,$cmp $dst,$src" %}
5244 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5245 ins_pipe(pipe_class_dummy);
5246 %}
5247
5248 instruct cmovN_imm(cmpOp cmp, flagsReg cr, iRegN dst, immN0 src) %{
5249 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5250 ins_cost(DEFAULT_COST + BRANCH_COST);
5251 // TODO: s390 port size(VARIABLE_SIZE);
5252 format %{ "CMoveN,$cmp $dst,$src" %}
5253 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5254 ins_pipe(pipe_class_dummy);
5255 %}
5256
5257 instruct cmovI_reg(cmpOp cmp, flagsReg cr, iRegI dst, iRegI src) %{
5258 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5259 ins_cost(DEFAULT_COST + BRANCH_COST);
5260 // TODO: s390 port size(VARIABLE_SIZE);
5261 format %{ "CMoveI,$cmp $dst,$src" %}
5262 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5263 ins_pipe(pipe_class_dummy);
5264 %}
5265
5266 instruct cmovI_imm(cmpOp cmp, flagsReg cr, iRegI dst, immI16 src) %{
5267 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5268 ins_cost(DEFAULT_COST + BRANCH_COST);
5269 // TODO: s390 port size(VARIABLE_SIZE);
5270 format %{ "CMoveI,$cmp $dst,$src" %}
5271 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5272 ins_pipe(pipe_class_dummy);
5273 %}
5274
5275 instruct cmovP_reg(cmpOp cmp, flagsReg cr, iRegP dst, iRegP_N2P src) %{
5276 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5277 ins_cost(DEFAULT_COST + BRANCH_COST);
5278 // TODO: s390 port size(VARIABLE_SIZE);
5279 format %{ "CMoveP,$cmp $dst,$src" %}
5280 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5281 ins_pipe(pipe_class_dummy);
5282 %}
5283
5284 instruct cmovP_imm(cmpOp cmp, flagsReg cr, iRegP dst, immP0 src) %{
5285 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5286 ins_cost(DEFAULT_COST + BRANCH_COST);
5287 // TODO: s390 port size(VARIABLE_SIZE);
5288 format %{ "CMoveP,$cmp $dst,$src" %}
5289 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5290 ins_pipe(pipe_class_dummy);
5291 %}
5292
5293 instruct cmovF_reg(cmpOpF cmp, flagsReg cr, regF dst, regF src) %{
5294 match(Set dst (CMoveF (Binary cmp cr) (Binary dst src)));
5295 ins_cost(DEFAULT_COST + BRANCH_COST);
5296 // TODO: s390 port size(VARIABLE_SIZE);
5297 format %{ "CMoveF,$cmp $dst,$src" %}
5298 ins_encode %{
5299 // Don't emit code if operands are identical (same register).
5300 if ($dst$$FloatRegister != $src$$FloatRegister) {
5301 Label done;
5302 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5303 __ z_ler($dst$$FloatRegister, $src$$FloatRegister);
5304 __ bind(done);
5305 }
5306 %}
5307 ins_pipe(pipe_class_dummy);
5308 %}
5309
5310 instruct cmovD_reg(cmpOpF cmp, flagsReg cr, regD dst, regD src) %{
5311 match(Set dst (CMoveD (Binary cmp cr) (Binary dst src)));
5312 ins_cost(DEFAULT_COST + BRANCH_COST);
5313 // TODO: s390 port size(VARIABLE_SIZE);
5314 format %{ "CMoveD,$cmp $dst,$src" %}
5315 ins_encode %{
5316 // Don't emit code if operands are identical (same register).
5317 if ($dst$$FloatRegister != $src$$FloatRegister) {
5318 Label done;
5319 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5320 __ z_ldr($dst$$FloatRegister, $src$$FloatRegister);
5321 __ bind(done);
5322 }
5323 %}
5324 ins_pipe(pipe_class_dummy);
5325 %}
5326
5327 instruct cmovL_reg(cmpOp cmp, flagsReg cr, iRegL dst, iRegL src) %{
5328 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5329 ins_cost(DEFAULT_COST + BRANCH_COST);
5330 // TODO: s390 port size(VARIABLE_SIZE);
5331 format %{ "CMoveL,$cmp $dst,$src" %}
5332 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5333 ins_pipe(pipe_class_dummy);
5334 %}
5335
5336 instruct cmovL_imm(cmpOp cmp, flagsReg cr, iRegL dst, immL16 src) %{
5337 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5338 ins_cost(DEFAULT_COST + BRANCH_COST);
5339 // TODO: s390 port size(VARIABLE_SIZE);
5340 format %{ "CMoveL,$cmp $dst,$src" %}
5341 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5342 ins_pipe(pipe_class_dummy);
5343 %}
5344
5345 //----------OS and Locking Instructions----------------------------------------
5346
5347 // This name is KNOWN by the ADLC and cannot be changed.
5348 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
5349 // for this guy.
5350 instruct tlsLoadP(threadRegP dst) %{
5351 match(Set dst (ThreadLocal));
5352 ins_cost(0);
5353 size(0);
5354 ins_should_rematerialize(true);
5355 format %{ "# $dst=ThreadLocal" %}
5356 ins_encode(/* empty */);
5357 ins_pipe(pipe_class_dummy);
5358 %}
5359
5360 instruct checkCastPP(iRegP dst) %{
5361 match(Set dst (CheckCastPP dst));
5362 size(0);
5363 format %{ "# checkcastPP of $dst" %}
5364 ins_encode(/*empty*/);
5365 ins_pipe(pipe_class_dummy);
5366 %}
5367
5368 instruct castPP(iRegP dst) %{
5369 match(Set dst (CastPP dst));
5370 size(0);
5371 format %{ "# castPP of $dst" %}
5372 ins_encode(/*empty*/);
5373 ins_pipe(pipe_class_dummy);
5374 %}
5375
5376 instruct castII(iRegI dst) %{
5377 match(Set dst (CastII dst));
5378 size(0);
5379 format %{ "# castII of $dst" %}
5380 ins_encode(/*empty*/);
5381 ins_pipe(pipe_class_dummy);
5382 %}
5383
5384
5385 //----------Conditional_store--------------------------------------------------
5386 // Conditional-store of the updated heap-top.
5387 // Used during allocation of the shared heap.
5388 // Sets flags (EQ) on success.
5389
5390 // Implement LoadPLocked. Must be ordered against changes of the memory location
5391 // by storePConditional.
5392 // Don't know whether this is ever used.
5393 instruct loadPLocked(iRegP dst, memory mem) %{
5394 match(Set dst (LoadPLocked mem));
5395 ins_cost(MEMORY_REF_COST);
5396 size(Z_DISP3_SIZE);
5397 format %{ "LG $dst,$mem\t # LoadPLocked" %}
5398 opcode(LG_ZOPC, LG_ZOPC);
5399 ins_encode(z_form_rt_mem_opt(dst, mem));
5400 ins_pipe(pipe_class_dummy);
5401 %}
5402
5403 // As compareAndSwapP, but return flag register instead of boolean value in
5404 // int register.
5405 // This instruction is matched if UseTLAB is off. Needed to pass
5406 // option tests. Mem_ptr must be a memory operand, else this node
5407 // does not get Flag_needs_anti_dependence_check set by adlc. If this
5408 // is not set this node can be rematerialized which leads to errors.
5409 instruct storePConditional(indirect mem_ptr, rarg5RegP oldval, iRegP_N2P newval, flagsReg cr) %{
5410 match(Set cr (StorePConditional mem_ptr (Binary oldval newval)));
5411 effect(KILL oldval);
5412 // TODO: s390 port size(FIXED_SIZE);
5413 format %{ "storePConditional $oldval,$newval,$mem_ptr" %}
5414 ins_encode(z_enc_casL(oldval, newval, mem_ptr));
5415 ins_pipe(pipe_class_dummy);
5416 %}
5417
5418 // As compareAndSwapL, but return flag register instead of boolean value in
5419 // int register.
5420 // Used by sun/misc/AtomicLongCSImpl.java. Mem_ptr must be a memory
5421 // operand, else this node does not get
5422 // Flag_needs_anti_dependence_check set by adlc. If this is not set
5423 // this node can be rematerialized which leads to errors.
5424 instruct storeLConditional(indirect mem_ptr, rarg5RegL oldval, iRegL newval, flagsReg cr) %{
5425 match(Set cr (StoreLConditional mem_ptr (Binary oldval newval)));
5426 effect(KILL oldval);
5427 // TODO: s390 port size(FIXED_SIZE);
5428 format %{ "storePConditional $oldval,$newval,$mem_ptr" %}
5429 ins_encode(z_enc_casL(oldval, newval, mem_ptr));
5430 ins_pipe(pipe_class_dummy);
5431 %}
5432
5433 // No flag versions for CompareAndSwap{P,I,L,N} because matcher can't match them.
5434
5435 instruct compareAndSwapI_bool(iRegP mem_ptr, rarg5RegI oldval, iRegI newval, iRegI res, flagsReg cr) %{
5436 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
5437 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5438 size(16);
5439 format %{ "$res = CompareAndSwapI $oldval,$newval,$mem_ptr" %}
5440 ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5441 z_enc_cctobool(res));
5442 ins_pipe(pipe_class_dummy);
5443 %}
5444
5445 instruct compareAndSwapL_bool(iRegP mem_ptr, rarg5RegL oldval, iRegL newval, iRegI res, flagsReg cr) %{
5446 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
5447 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5448 size(18);
5449 format %{ "$res = CompareAndSwapL $oldval,$newval,$mem_ptr" %}
5450 ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5451 z_enc_cctobool(res));
5452 ins_pipe(pipe_class_dummy);
5453 %}
5454
5455 instruct compareAndSwapP_bool(iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, iRegI res, flagsReg cr) %{
5456 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
5457 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5458 size(18);
5459 format %{ "$res = CompareAndSwapP $oldval,$newval,$mem_ptr" %}
5460 ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5461 z_enc_cctobool(res));
5462 ins_pipe(pipe_class_dummy);
5463 %}
5464
5465 instruct compareAndSwapN_bool(iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, iRegI res, flagsReg cr) %{
5466 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
5467 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5468 size(16);
5469 format %{ "$res = CompareAndSwapN $oldval,$newval,$mem_ptr" %}
5470 ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5471 z_enc_cctobool(res));
5472 ins_pipe(pipe_class_dummy);
5473 %}
5474
5475 //----------Atomic operations on memory (GetAndSet*, GetAndAdd*)---------------
5476
5477 // Exploit: direct memory arithmetic
5478 // Prereqs: - instructions available
5479 // - instructions guarantee atomicity
5480 // - immediate operand to be added
5481 // - immediate operand is small enough (8-bit signed).
5482 // - result of instruction is not used
5483 instruct addI_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immI8 src, flagsReg cr) %{
5484 match(Set dummy (GetAndAddI mem src));
5485 effect(KILL cr);
5486 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5487 ins_cost(MEMORY_REF_COST);
5488 size(6);
5489 format %{ "ASI [$mem],$src\t # GetAndAddI (atomic)" %}
5490 opcode(ASI_ZOPC);
5491 ins_encode(z_siyform(mem, src));
5492 ins_pipe(pipe_class_dummy);
5493 %}
5494
5495 // Fallback: direct memory arithmetic not available
5496 // Disadvantages: - CS-Loop required, very expensive.
5497 // - more code generated (26 to xx bytes vs. 6 bytes)
5498 instruct addI_mem_imm16_atomic(memoryRSY mem, iRegI dst, immI16 src, iRegI tmp, flagsReg cr) %{
5499 match(Set dst (GetAndAddI mem src));
5500 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5501 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5502 format %{ "BEGIN ATOMIC {\n\t"
5503 " LGF $dst,[$mem]\n\t"
5504 " AHIK $tmp,$dst,$src\n\t"
5505 " CSY $dst,$tmp,$mem\n\t"
5506 " retry if failed\n\t"
5507 "} END ATOMIC"
5508 %}
5509 ins_encode %{
5510 Register Rdst = $dst$$Register;
5511 Register Rtmp = $tmp$$Register;
5512 int Isrc = $src$$constant;
5513 Label retry;
5514
5515 // Iterate until update with incremented value succeeds.
5516 __ z_lgf(Rdst, $mem$$Address); // current contents
5517 __ bind(retry);
5518 // Calculate incremented value.
5519 if (VM_Version::has_DistinctOpnds()) {
5520 __ z_ahik(Rtmp, Rdst, Isrc);
5521 } else {
5522 __ z_lr(Rtmp, Rdst);
5523 __ z_ahi(Rtmp, Isrc);
5524 }
5525 // Swap into memory location.
5526 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5527 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5528 %}
5529 ins_pipe(pipe_class_dummy);
5530 %}
5531
5532 instruct addI_mem_imm32_atomic(memoryRSY mem, iRegI dst, immI src, iRegI tmp, flagsReg cr) %{
5533 match(Set dst (GetAndAddI mem src));
5534 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5535 ins_cost(MEMORY_REF_COST+200*DEFAULT_COST);
5536 format %{ "BEGIN ATOMIC {\n\t"
5537 " LGF $dst,[$mem]\n\t"
5538 " LGR $tmp,$dst\n\t"
5539 " AFI $tmp,$src\n\t"
5540 " CSY $dst,$tmp,$mem\n\t"
5541 " retry if failed\n\t"
5542 "} END ATOMIC"
5543 %}
5544 ins_encode %{
5545 Register Rdst = $dst$$Register;
5546 Register Rtmp = $tmp$$Register;
5547 int Isrc = $src$$constant;
5548 Label retry;
5549
5550 // Iterate until update with incremented value succeeds.
5551 __ z_lgf(Rdst, $mem$$Address); // current contents
5552 __ bind(retry);
5553 // Calculate incremented value.
5554 __ z_lr(Rtmp, Rdst);
5555 __ z_afi(Rtmp, Isrc);
5556 // Swap into memory location.
5557 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5558 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5559 %}
5560 ins_pipe(pipe_class_dummy);
5561 %}
5562
5563 instruct addI_mem_reg_atomic(memoryRSY mem, iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
5564 match(Set dst (GetAndAddI mem src));
5565 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5566 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5567 format %{ "BEGIN ATOMIC {\n\t"
5568 " LGF $dst,[$mem]\n\t"
5569 " ARK $tmp,$dst,$src\n\t"
5570 " CSY $dst,$tmp,$mem\n\t"
5571 " retry if failed\n\t"
5572 "} END ATOMIC"
5573 %}
5574 ins_encode %{
5575 Register Rsrc = $src$$Register;
5576 Register Rdst = $dst$$Register;
5577 Register Rtmp = $tmp$$Register;
5578 Label retry;
5579
5580 // Iterate until update with incremented value succeeds.
5581 __ z_lgf(Rdst, $mem$$Address); // current contents
5582 __ bind(retry);
5583 // Calculate incremented value.
5584 if (VM_Version::has_DistinctOpnds()) {
5585 __ z_ark(Rtmp, Rdst, Rsrc);
5586 } else {
5587 __ z_lr(Rtmp, Rdst);
5588 __ z_ar(Rtmp, Rsrc);
5589 }
5590 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5591 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5592 %}
5593 ins_pipe(pipe_class_dummy);
5594 %}
5595
5596
5597 // Exploit: direct memory arithmetic
5598 // Prereqs: - instructions available
5599 // - instructions guarantee atomicity
5600 // - immediate operand to be added
5601 // - immediate operand is small enough (8-bit signed).
5602 // - result of instruction is not used
5603 instruct addL_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immL8 src, flagsReg cr) %{
5604 match(Set dummy (GetAndAddL mem src));
5605 effect(KILL cr);
5606 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5607 ins_cost(MEMORY_REF_COST);
5608 size(6);
5609 format %{ "AGSI [$mem],$src\t # GetAndAddL (atomic)" %}
5610 opcode(AGSI_ZOPC);
5611 ins_encode(z_siyform(mem, src));
5612 ins_pipe(pipe_class_dummy);
5613 %}
5614
5615 // Fallback: direct memory arithmetic not available
5616 // Disadvantages: - CS-Loop required, very expensive.
5617 // - more code generated (26 to xx bytes vs. 6 bytes)
5618 instruct addL_mem_imm16_atomic(memoryRSY mem, iRegL dst, immL16 src, iRegL tmp, flagsReg cr) %{
5619 match(Set dst (GetAndAddL mem src));
5620 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5621 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5622 format %{ "BEGIN ATOMIC {\n\t"
5623 " LG $dst,[$mem]\n\t"
5624 " AGHIK $tmp,$dst,$src\n\t"
5625 " CSG $dst,$tmp,$mem\n\t"
5626 " retry if failed\n\t"
5627 "} END ATOMIC"
5628 %}
5629 ins_encode %{
5630 Register Rdst = $dst$$Register;
5631 Register Rtmp = $tmp$$Register;
5632 int Isrc = $src$$constant;
5633 Label retry;
5634
5635 // Iterate until update with incremented value succeeds.
5636 __ z_lg(Rdst, $mem$$Address); // current contents
5637 __ bind(retry);
5638 // Calculate incremented value.
5639 if (VM_Version::has_DistinctOpnds()) {
5640 __ z_aghik(Rtmp, Rdst, Isrc);
5641 } else {
5642 __ z_lgr(Rtmp, Rdst);
5643 __ z_aghi(Rtmp, Isrc);
5644 }
5645 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5646 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5647 %}
5648 ins_pipe(pipe_class_dummy);
5649 %}
5650
5651 instruct addL_mem_imm32_atomic(memoryRSY mem, iRegL dst, immL32 src, iRegL tmp, flagsReg cr) %{
5652 match(Set dst (GetAndAddL mem src));
5653 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5654 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5655 format %{ "BEGIN ATOMIC {\n\t"
5656 " LG $dst,[$mem]\n\t"
5657 " LGR $tmp,$dst\n\t"
5658 " AGFI $tmp,$src\n\t"
5659 " CSG $dst,$tmp,$mem\n\t"
5660 " retry if failed\n\t"
5661 "} END ATOMIC"
5662 %}
5663 ins_encode %{
5664 Register Rdst = $dst$$Register;
5665 Register Rtmp = $tmp$$Register;
5666 int Isrc = $src$$constant;
5667 Label retry;
5668
5669 // Iterate until update with incremented value succeeds.
5670 __ z_lg(Rdst, $mem$$Address); // current contents
5671 __ bind(retry);
5672 // Calculate incremented value.
5673 __ z_lgr(Rtmp, Rdst);
5674 __ z_agfi(Rtmp, Isrc);
5675 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5676 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5677 %}
5678 ins_pipe(pipe_class_dummy);
5679 %}
5680
5681 instruct addL_mem_reg_atomic(memoryRSY mem, iRegL dst, iRegL src, iRegL tmp, flagsReg cr) %{
5682 match(Set dst (GetAndAddL mem src));
5683 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5684 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5685 format %{ "BEGIN ATOMIC {\n\t"
5686 " LG $dst,[$mem]\n\t"
5687 " AGRK $tmp,$dst,$src\n\t"
5688 " CSG $dst,$tmp,$mem\n\t"
5689 " retry if failed\n\t"
5690 "} END ATOMIC"
5691 %}
5692 ins_encode %{
5693 Register Rsrc = $src$$Register;
5694 Register Rdst = $dst$$Register;
5695 Register Rtmp = $tmp$$Register;
5696 Label retry;
5697
5698 // Iterate until update with incremented value succeeds.
5699 __ z_lg(Rdst, $mem$$Address); // current contents
5700 __ bind(retry);
5701 // Calculate incremented value.
5702 if (VM_Version::has_DistinctOpnds()) {
5703 __ z_agrk(Rtmp, Rdst, Rsrc);
5704 } else {
5705 __ z_lgr(Rtmp, Rdst);
5706 __ z_agr(Rtmp, Rsrc);
5707 }
5708 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5709 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5710 %}
5711 ins_pipe(pipe_class_dummy);
5712 %}
5713
5714 // Increment value in memory, save old value in dst.
5715 instruct addI_mem_reg_atomic_z196(memoryRSY mem, iRegI dst, iRegI src) %{
5716 match(Set dst (GetAndAddI mem src));
5717 predicate(VM_Version::has_LoadAndALUAtomicV1());
5718 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5719 size(6);
5720 format %{ "LAA $dst,$src,[$mem]" %}
5721 ins_encode %{ __ z_laa($dst$$Register, $src$$Register, $mem$$Address); %}
5722 ins_pipe(pipe_class_dummy);
5723 %}
5724
5725 // Increment value in memory, save old value in dst.
5726 instruct addL_mem_reg_atomic_z196(memoryRSY mem, iRegL dst, iRegL src) %{
5727 match(Set dst (GetAndAddL mem src));
5728 predicate(VM_Version::has_LoadAndALUAtomicV1());
5729 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5730 size(6);
5731 format %{ "LAAG $dst,$src,[$mem]" %}
5732 ins_encode %{ __ z_laag($dst$$Register, $src$$Register, $mem$$Address); %}
5733 ins_pipe(pipe_class_dummy);
5734 %}
5735
5736
5737 instruct xchgI_reg_mem(memoryRSY mem, iRegI dst, iRegI tmp, flagsReg cr) %{
5738 match(Set dst (GetAndSetI mem dst));
5739 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5740 format %{ "XCHGI $dst,[$mem]\t # EXCHANGE (int, atomic), temp $tmp" %}
5741 ins_encode(z_enc_SwapI(mem, dst, tmp));
5742 ins_pipe(pipe_class_dummy);
5743 %}
5744
5745 instruct xchgL_reg_mem(memoryRSY mem, iRegL dst, iRegL tmp, flagsReg cr) %{
5746 match(Set dst (GetAndSetL mem dst));
5747 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5748 format %{ "XCHGL $dst,[$mem]\t # EXCHANGE (long, atomic), temp $tmp" %}
5749 ins_encode(z_enc_SwapL(mem, dst, tmp));
5750 ins_pipe(pipe_class_dummy);
5751 %}
5752
5753 instruct xchgN_reg_mem(memoryRSY mem, iRegN dst, iRegI tmp, flagsReg cr) %{
5754 match(Set dst (GetAndSetN mem dst));
5755 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5756 format %{ "XCHGN $dst,[$mem]\t # EXCHANGE (coop, atomic), temp $tmp" %}
5757 ins_encode(z_enc_SwapI(mem, dst, tmp));
5758 ins_pipe(pipe_class_dummy);
5759 %}
5760
5761 instruct xchgP_reg_mem(memoryRSY mem, iRegP dst, iRegL tmp, flagsReg cr) %{
5762 match(Set dst (GetAndSetP mem dst));
5763 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5764 format %{ "XCHGP $dst,[$mem]\t # EXCHANGE (oop, atomic), temp $tmp" %}
5765 ins_encode(z_enc_SwapL(mem, dst, tmp));
5766 ins_pipe(pipe_class_dummy);
5767 %}
5768
5769
5770 //----------Arithmetic Instructions--------------------------------------------
5771
5772 // The rules are sorted by right operand type and operand length. Please keep
5773 // it that way.
5774 // Left operand type is always reg. Left operand len is I, L, P
5775 // Right operand type is reg, imm, mem. Right operand len is S, I, L, P
5776 // Special instruction formats, e.g. multi-operand, are inserted at the end.
5777
5778 // ADD
5779
5780 // REG = REG + REG
5781
5782 // Register Addition
5783 instruct addI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
5784 match(Set dst (AddI dst src));
5785 effect(KILL cr);
5786 // TODO: s390 port size(FIXED_SIZE);
5787 format %{ "AR $dst,$src\t # int CISC ALU" %}
5788 opcode(AR_ZOPC);
5789 ins_encode(z_rrform(dst, src));
5790 ins_pipe(pipe_class_dummy);
5791 %}
5792
5793 // Avoid use of LA(Y) for general ALU operation.
5794 instruct addI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
5795 match(Set dst (AddI src1 src2));
5796 effect(KILL cr);
5797 predicate(VM_Version::has_DistinctOpnds());
5798 ins_cost(DEFAULT_COST);
5799 size(4);
5800 format %{ "ARK $dst,$src1,$src2\t # int RISC ALU" %}
5801 opcode(ARK_ZOPC);
5802 ins_encode(z_rrfform(dst, src1, src2));
5803 ins_pipe(pipe_class_dummy);
5804 %}
5805
5806 // REG = REG + IMM
5807
5808 // Avoid use of LA(Y) for general ALU operation.
5809 // Immediate Addition
5810 instruct addI_reg_imm16_CISC(iRegI dst, immI16 con, flagsReg cr) %{
5811 match(Set dst (AddI dst con));
5812 effect(KILL cr);
5813 ins_cost(DEFAULT_COST);
5814 // TODO: s390 port size(FIXED_SIZE);
5815 format %{ "AHI $dst,$con\t # int CISC ALU" %}
5816 opcode(AHI_ZOPC);
5817 ins_encode(z_riform_signed(dst, con));
5818 ins_pipe(pipe_class_dummy);
5819 %}
5820
5821 // Avoid use of LA(Y) for general ALU operation.
5822 // Immediate Addition
5823 instruct addI_reg_imm16_RISC(iRegI dst, iRegI src, immI16 con, flagsReg cr) %{
5824 match(Set dst (AddI src con));
5825 effect(KILL cr);
5826 predicate( VM_Version::has_DistinctOpnds());
5827 ins_cost(DEFAULT_COST);
5828 // TODO: s390 port size(FIXED_SIZE);
5829 format %{ "AHIK $dst,$src,$con\t # int RISC ALU" %}
5830 opcode(AHIK_ZOPC);
5831 ins_encode(z_rieform_d(dst, src, con));
5832 ins_pipe(pipe_class_dummy);
5833 %}
5834
5835 // Immediate Addition
5836 instruct addI_reg_imm32(iRegI dst, immI src, flagsReg cr) %{
5837 match(Set dst (AddI dst src));
5838 effect(KILL cr);
5839 ins_cost(DEFAULT_COST_HIGH);
5840 size(6);
5841 format %{ "AFI $dst,$src" %}
5842 opcode(AFI_ZOPC);
5843 ins_encode(z_rilform_signed(dst, src));
5844 ins_pipe(pipe_class_dummy);
5845 %}
5846
5847 // Immediate Addition
5848 instruct addI_reg_imm12(iRegI dst, iRegI src, uimmI12 con) %{
5849 match(Set dst (AddI src con));
5850 predicate(PreferLAoverADD);
5851 ins_cost(DEFAULT_COST_LOW);
5852 size(4);
5853 format %{ "LA $dst,$con(,$src)\t # int d12(,b)" %}
5854 opcode(LA_ZOPC);
5855 ins_encode(z_rxform_imm_reg(dst, con, src));
5856 ins_pipe(pipe_class_dummy);
5857 %}
5858
5859 // Immediate Addition
5860 instruct addI_reg_imm20(iRegI dst, iRegI src, immI20 con) %{
5861 match(Set dst (AddI src con));
5862 predicate(PreferLAoverADD);
5863 ins_cost(DEFAULT_COST);
5864 size(6);
5865 format %{ "LAY $dst,$con(,$src)\t # int d20(,b)" %}
5866 opcode(LAY_ZOPC);
5867 ins_encode(z_rxyform_imm_reg(dst, con, src));
5868 ins_pipe(pipe_class_dummy);
5869 %}
5870
5871 instruct addI_reg_reg_imm12(iRegI dst, iRegI src1, iRegI src2, uimmI12 con) %{
5872 match(Set dst (AddI (AddI src1 src2) con));
5873 predicate( PreferLAoverADD);
5874 ins_cost(DEFAULT_COST_LOW);
5875 size(4);
5876 format %{ "LA $dst,$con($src1,$src2)\t # int d12(x,b)" %}
5877 opcode(LA_ZOPC);
5878 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
5879 ins_pipe(pipe_class_dummy);
5880 %}
5881
5882 instruct addI_reg_reg_imm20(iRegI dst, iRegI src1, iRegI src2, immI20 con) %{
5883 match(Set dst (AddI (AddI src1 src2) con));
5884 predicate(PreferLAoverADD);
5885 ins_cost(DEFAULT_COST);
5886 size(6);
5887 format %{ "LAY $dst,$con($src1,$src2)\t # int d20(x,b)" %}
5888 opcode(LAY_ZOPC);
5889 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
5890 ins_pipe(pipe_class_dummy);
5891 %}
5892
5893 // REG = REG + MEM
5894
5895 instruct addI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
5896 match(Set dst (AddI dst (LoadI src)));
5897 effect(KILL cr);
5898 ins_cost(MEMORY_REF_COST);
5899 // TODO: s390 port size(VARIABLE_SIZE);
5900 format %{ "A(Y) $dst, $src\t # int" %}
5901 opcode(AY_ZOPC, A_ZOPC);
5902 ins_encode(z_form_rt_mem_opt(dst, src));
5903 ins_pipe(pipe_class_dummy);
5904 %}
5905
5906 // MEM = MEM + IMM
5907
5908 // Add Immediate to 4-byte memory operand and result
5909 instruct addI_mem_imm(memoryRSY mem, immI8 src, flagsReg cr) %{
5910 match(Set mem (StoreI mem (AddI (LoadI mem) src)));
5911 effect(KILL cr);
5912 predicate(VM_Version::has_MemWithImmALUOps());
5913 ins_cost(MEMORY_REF_COST);
5914 size(6);
5915 format %{ "ASI $mem,$src\t # direct mem add 4" %}
5916 opcode(ASI_ZOPC);
5917 ins_encode(z_siyform(mem, src));
5918 ins_pipe(pipe_class_dummy);
5919 %}
5920
5921
5922 //
5923
5924 // REG = REG + REG
5925
5926 instruct addL_reg_regI(iRegL dst, iRegI src, flagsReg cr) %{
5927 match(Set dst (AddL dst (ConvI2L src)));
5928 effect(KILL cr);
5929 size(4);
5930 format %{ "AGFR $dst,$src\t # long<-int CISC ALU" %}
5931 opcode(AGFR_ZOPC);
5932 ins_encode(z_rreform(dst, src));
5933 ins_pipe(pipe_class_dummy);
5934 %}
5935
5936 instruct addL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
5937 match(Set dst (AddL dst src));
5938 effect(KILL cr);
5939 // TODO: s390 port size(FIXED_SIZE);
5940 format %{ "AGR $dst, $src\t # long CISC ALU" %}
5941 opcode(AGR_ZOPC);
5942 ins_encode(z_rreform(dst, src));
5943 ins_pipe(pipe_class_dummy);
5944 %}
5945
5946 // Avoid use of LA(Y) for general ALU operation.
5947 instruct addL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
5948 match(Set dst (AddL src1 src2));
5949 effect(KILL cr);
5950 predicate(VM_Version::has_DistinctOpnds());
5951 ins_cost(DEFAULT_COST);
5952 size(4);
5953 format %{ "AGRK $dst,$src1,$src2\t # long RISC ALU" %}
5954 opcode(AGRK_ZOPC);
5955 ins_encode(z_rrfform(dst, src1, src2));
5956 ins_pipe(pipe_class_dummy);
5957 %}
5958
5959 // REG = REG + IMM
5960
5961 instruct addL_reg_imm12(iRegL dst, iRegL src, uimmL12 con) %{
5962 match(Set dst (AddL src con));
5963 predicate( PreferLAoverADD);
5964 ins_cost(DEFAULT_COST_LOW);
5965 size(4);
5966 format %{ "LA $dst,$con(,$src)\t # long d12(,b)" %}
5967 opcode(LA_ZOPC);
5968 ins_encode(z_rxform_imm_reg(dst, con, src));
5969 ins_pipe(pipe_class_dummy);
5970 %}
5971
5972 instruct addL_reg_imm20(iRegL dst, iRegL src, immL20 con) %{
5973 match(Set dst (AddL src con));
5974 predicate(PreferLAoverADD);
5975 ins_cost(DEFAULT_COST);
5976 size(6);
5977 format %{ "LAY $dst,$con(,$src)\t # long d20(,b)" %}
5978 opcode(LAY_ZOPC);
5979 ins_encode(z_rxyform_imm_reg(dst, con, src));
5980 ins_pipe(pipe_class_dummy);
5981 %}
5982
5983 instruct addL_reg_imm32(iRegL dst, immL32 con, flagsReg cr) %{
5984 match(Set dst (AddL dst con));
5985 effect(KILL cr);
5986 ins_cost(DEFAULT_COST_HIGH);
5987 size(6);
5988 format %{ "AGFI $dst,$con\t # long CISC ALU" %}
5989 opcode(AGFI_ZOPC);
5990 ins_encode(z_rilform_signed(dst, con));
5991 ins_pipe(pipe_class_dummy);
5992 %}
5993
5994 // Avoid use of LA(Y) for general ALU operation.
5995 instruct addL_reg_imm16_CISC(iRegL dst, immL16 con, flagsReg cr) %{
5996 match(Set dst (AddL dst con));
5997 effect(KILL cr);
5998 ins_cost(DEFAULT_COST);
5999 // TODO: s390 port size(FIXED_SIZE);
6000 format %{ "AGHI $dst,$con\t # long CISC ALU" %}
6001 opcode(AGHI_ZOPC);
6002 ins_encode(z_riform_signed(dst, con));
6003 ins_pipe(pipe_class_dummy);
6004 %}
6005
6006 // Avoid use of LA(Y) for general ALU operation.
6007 instruct addL_reg_imm16_RISC(iRegL dst, iRegL src, immL16 con, flagsReg cr) %{
6008 match(Set dst (AddL src con));
6009 effect(KILL cr);
6010 predicate( VM_Version::has_DistinctOpnds());
6011 ins_cost(DEFAULT_COST);
6012 size(6);
6013 format %{ "AGHIK $dst,$src,$con\t # long RISC ALU" %}
6014 opcode(AGHIK_ZOPC);
6015 ins_encode(z_rieform_d(dst, src, con));
6016 ins_pipe(pipe_class_dummy);
6017 %}
6018
6019 // REG = REG + MEM
6020
6021 instruct addL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6022 match(Set dst (AddL dst (ConvI2L (LoadI src))));
6023 effect(KILL cr);
6024 ins_cost(MEMORY_REF_COST);
6025 size(Z_DISP3_SIZE);
6026 format %{ "AGF $dst, $src\t # long/int" %}
6027 opcode(AGF_ZOPC, AGF_ZOPC);
6028 ins_encode(z_form_rt_mem_opt(dst, src));
6029 ins_pipe(pipe_class_dummy);
6030 %}
6031
6032 instruct addL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6033 match(Set dst (AddL dst (LoadL src)));
6034 effect(KILL cr);
6035 ins_cost(MEMORY_REF_COST);
6036 size(Z_DISP3_SIZE);
6037 format %{ "AG $dst, $src\t # long" %}
6038 opcode(AG_ZOPC, AG_ZOPC);
6039 ins_encode(z_form_rt_mem_opt(dst, src));
6040 ins_pipe(pipe_class_dummy);
6041 %}
6042
6043 instruct addL_reg_reg_imm12(iRegL dst, iRegL src1, iRegL src2, uimmL12 con) %{
6044 match(Set dst (AddL (AddL src1 src2) con));
6045 predicate( PreferLAoverADD);
6046 ins_cost(DEFAULT_COST_LOW);
6047 size(4);
6048 format %{ "LA $dst,$con($src1,$src2)\t # long d12(x,b)" %}
6049 opcode(LA_ZOPC);
6050 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6051 ins_pipe(pipe_class_dummy);
6052 %}
6053
6054 instruct addL_reg_reg_imm20(iRegL dst, iRegL src1, iRegL src2, immL20 con) %{
6055 match(Set dst (AddL (AddL src1 src2) con));
6056 predicate(PreferLAoverADD);
6057 ins_cost(DEFAULT_COST);
6058 size(6);
6059 format %{ "LAY $dst,$con($src1,$src2)\t # long d20(x,b)" %}
6060 opcode(LAY_ZOPC);
6061 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6062 ins_pipe(pipe_class_dummy);
6063 %}
6064
6065 // MEM = MEM + IMM
6066
6067 // Add Immediate to 8-byte memory operand and result.
6068 instruct addL_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6069 match(Set mem (StoreL mem (AddL (LoadL mem) src)));
6070 effect(KILL cr);
6071 predicate(VM_Version::has_MemWithImmALUOps());
6072 ins_cost(MEMORY_REF_COST);
6073 size(6);
6074 format %{ "AGSI $mem,$src\t # direct mem add 8" %}
6075 opcode(AGSI_ZOPC);
6076 ins_encode(z_siyform(mem, src));
6077 ins_pipe(pipe_class_dummy);
6078 %}
6079
6080
6081 // REG = REG + REG
6082
6083 // Ptr Addition
6084 instruct addP_reg_reg_LA(iRegP dst, iRegP_N2P src1, iRegL src2) %{
6085 match(Set dst (AddP src1 src2));
6086 predicate( PreferLAoverADD);
6087 ins_cost(DEFAULT_COST);
6088 size(4);
6089 format %{ "LA $dst,#0($src1,$src2)\t # ptr 0(x,b)" %}
6090 opcode(LA_ZOPC);
6091 ins_encode(z_rxform_imm_reg_reg(dst, 0x0, src1, src2));
6092 ins_pipe(pipe_class_dummy);
6093 %}
6094
6095 // Ptr Addition
6096 // Avoid use of LA(Y) for general ALU operation.
6097 instruct addP_reg_reg_CISC(iRegP dst, iRegL src, flagsReg cr) %{
6098 match(Set dst (AddP dst src));
6099 effect(KILL cr);
6100 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6101 ins_cost(DEFAULT_COST);
6102 // TODO: s390 port size(FIXED_SIZE);
6103 format %{ "ALGR $dst,$src\t # ptr CICS ALU" %}
6104 opcode(ALGR_ZOPC);
6105 ins_encode(z_rreform(dst, src));
6106 ins_pipe(pipe_class_dummy);
6107 %}
6108
6109 // Ptr Addition
6110 // Avoid use of LA(Y) for general ALU operation.
6111 instruct addP_reg_reg_RISC(iRegP dst, iRegP_N2P src1, iRegL src2, flagsReg cr) %{
6112 match(Set dst (AddP src1 src2));
6113 effect(KILL cr);
6114 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6115 ins_cost(DEFAULT_COST);
6116 // TODO: s390 port size(FIXED_SIZE);
6117 format %{ "ALGRK $dst,$src1,$src2\t # ptr RISC ALU" %}
6118 opcode(ALGRK_ZOPC);
6119 ins_encode(z_rrfform(dst, src1, src2));
6120 ins_pipe(pipe_class_dummy);
6121 %}
6122
6123 // REG = REG + IMM
6124
6125 instruct addP_reg_imm12(iRegP dst, iRegP_N2P src, uimmL12 con) %{
6126 match(Set dst (AddP src con));
6127 predicate( PreferLAoverADD);
6128 ins_cost(DEFAULT_COST_LOW);
6129 size(4);
6130 format %{ "LA $dst,$con(,$src)\t # ptr d12(,b)" %}
6131 opcode(LA_ZOPC);
6132 ins_encode(z_rxform_imm_reg(dst, con, src));
6133 ins_pipe(pipe_class_dummy);
6134 %}
6135
6136 // Avoid use of LA(Y) for general ALU operation.
6137 instruct addP_reg_imm16_CISC(iRegP dst, immL16 src, flagsReg cr) %{
6138 match(Set dst (AddP dst src));
6139 effect(KILL cr);
6140 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6141 ins_cost(DEFAULT_COST);
6142 // TODO: s390 port size(FIXED_SIZE);
6143 format %{ "AGHI $dst,$src\t # ptr CISC ALU" %}
6144 opcode(AGHI_ZOPC);
6145 ins_encode(z_riform_signed(dst, src));
6146 ins_pipe(pipe_class_dummy);
6147 %}
6148
6149 // Avoid use of LA(Y) for general ALU operation.
6150 instruct addP_reg_imm16_RISC(iRegP dst, iRegP_N2P src, immL16 con, flagsReg cr) %{
6151 match(Set dst (AddP src con));
6152 effect(KILL cr);
6153 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6154 ins_cost(DEFAULT_COST);
6155 // TODO: s390 port size(FIXED_SIZE);
6156 format %{ "ALGHSIK $dst,$src,$con\t # ptr RISC ALU" %}
6157 opcode(ALGHSIK_ZOPC);
6158 ins_encode(z_rieform_d(dst, src, con));
6159 ins_pipe(pipe_class_dummy);
6160 %}
6161
6162 instruct addP_reg_imm20(iRegP dst, memoryRegP src, immL20 con) %{
6163 match(Set dst (AddP src con));
6164 predicate(PreferLAoverADD);
6165 ins_cost(DEFAULT_COST);
6166 size(6);
6167 format %{ "LAY $dst,$con(,$src)\t # ptr d20(,b)" %}
6168 opcode(LAY_ZOPC);
6169 ins_encode(z_rxyform_imm_reg(dst, con, src));
6170 ins_pipe(pipe_class_dummy);
6171 %}
6172
6173 // Pointer Immediate Addition
6174 instruct addP_reg_imm32(iRegP dst, immL32 src, flagsReg cr) %{
6175 match(Set dst (AddP dst src));
6176 effect(KILL cr);
6177 ins_cost(DEFAULT_COST_HIGH);
6178 // TODO: s390 port size(FIXED_SIZE);
6179 format %{ "AGFI $dst,$src\t # ptr" %}
6180 opcode(AGFI_ZOPC);
6181 ins_encode(z_rilform_signed(dst, src));
6182 ins_pipe(pipe_class_dummy);
6183 %}
6184
6185 // REG = REG1 + REG2 + IMM
6186
6187 instruct addP_reg_reg_imm12(iRegP dst, memoryRegP src1, iRegL src2, uimmL12 con) %{
6188 match(Set dst (AddP (AddP src1 src2) con));
6189 predicate( PreferLAoverADD);
6190 ins_cost(DEFAULT_COST_LOW);
6191 size(4);
6192 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6193 opcode(LA_ZOPC);
6194 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6195 ins_pipe(pipe_class_dummy);
6196 %}
6197
6198 instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{
6199 match(Set dst (AddP (AddP src1 src2) con));
6200 predicate( PreferLAoverADD && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
6201 ins_cost(DEFAULT_COST_LOW);
6202 size(4);
6203 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6204 opcode(LA_ZOPC);
6205 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6206 ins_pipe(pipe_class_dummy);
6207 %}
6208
6209 instruct addP_reg_reg_imm20(iRegP dst, memoryRegP src1, iRegL src2, immL20 con) %{
6210 match(Set dst (AddP (AddP src1 src2) con));
6211 predicate(PreferLAoverADD);
6212 ins_cost(DEFAULT_COST);
6213 // TODO: s390 port size(FIXED_SIZE);
6214 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6215 opcode(LAY_ZOPC);
6216 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6217 ins_pipe(pipe_class_dummy);
6218 %}
6219
6220 instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{
6221 match(Set dst (AddP (AddP src1 src2) con));
6222 predicate( PreferLAoverADD && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
6223 ins_cost(DEFAULT_COST);
6224 // TODO: s390 port size(FIXED_SIZE);
6225 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6226 opcode(LAY_ZOPC);
6227 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6228 ins_pipe(pipe_class_dummy);
6229 %}
6230
6231 // MEM = MEM + IMM
6232
6233 // Add Immediate to 8-byte memory operand and result
6234 instruct addP_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6235 match(Set mem (StoreP mem (AddP (LoadP mem) src)));
6236 effect(KILL cr);
6237 predicate(VM_Version::has_MemWithImmALUOps());
6238 ins_cost(MEMORY_REF_COST);
6239 size(6);
6240 format %{ "AGSI $mem,$src\t # direct mem add 8 (ptr)" %}
6241 opcode(AGSI_ZOPC);
6242 ins_encode(z_siyform(mem, src));
6243 ins_pipe(pipe_class_dummy);
6244 %}
6245
6246 // SUB
6247
6248 // Register Subtraction
6249 instruct subI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
6250 match(Set dst (SubI dst src));
6251 effect(KILL cr);
6252 // TODO: s390 port size(FIXED_SIZE);
6253 format %{ "SR $dst,$src\t # int CISC ALU" %}
6254 opcode(SR_ZOPC);
6255 ins_encode(z_rrform(dst, src));
6256 ins_pipe(pipe_class_dummy);
6257 %}
6258
6259 instruct subI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
6260 match(Set dst (SubI src1 src2));
6261 effect(KILL cr);
6262 predicate(VM_Version::has_DistinctOpnds());
6263 ins_cost(DEFAULT_COST);
6264 size(4);
6265 format %{ "SRK $dst,$src1,$src2\t # int RISC ALU" %}
6266 opcode(SRK_ZOPC);
6267 ins_encode(z_rrfform(dst, src1, src2));
6268 ins_pipe(pipe_class_dummy);
6269 %}
6270
6271 instruct subI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
6272 match(Set dst (SubI dst (LoadI src)));
6273 effect(KILL cr);
6274 ins_cost(MEMORY_REF_COST);
6275 // TODO: s390 port size(VARIABLE_SIZE);
6276 format %{ "S(Y) $dst, $src\t # int" %}
6277 opcode(SY_ZOPC, S_ZOPC);
6278 ins_encode(z_form_rt_mem_opt(dst, src));
6279 ins_pipe(pipe_class_dummy);
6280 %}
6281
6282 instruct subI_zero_reg(iRegI dst, immI_0 zero, iRegI src, flagsReg cr) %{
6283 match(Set dst (SubI zero src));
6284 effect(KILL cr);
6285 size(2);
6286 format %{ "NEG $dst, $src" %}
6287 ins_encode %{ __ z_lcr($dst$$Register, $src$$Register); %}
6288 ins_pipe(pipe_class_dummy);
6289 %}
6290
6291 //
6292
6293 // Long subtraction
6294 instruct subL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
6295 match(Set dst (SubL dst src));
6296 effect(KILL cr);
6297 // TODO: s390 port size(FIXED_SIZE);
6298 format %{ "SGR $dst,$src\t # int CISC ALU" %}
6299 opcode(SGR_ZOPC);
6300 ins_encode(z_rreform(dst, src));
6301 ins_pipe(pipe_class_dummy);
6302 %}
6303
6304 // Avoid use of LA(Y) for general ALU operation.
6305 instruct subL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
6306 match(Set dst (SubL src1 src2));
6307 effect(KILL cr);
6308 predicate(VM_Version::has_DistinctOpnds());
6309 ins_cost(DEFAULT_COST);
6310 size(4);
6311 format %{ "SGRK $dst,$src1,$src2\t # int RISC ALU" %}
6312 opcode(SGRK_ZOPC);
6313 ins_encode(z_rrfform(dst, src1, src2));
6314 ins_pipe(pipe_class_dummy);
6315 %}
6316
6317 instruct subL_reg_regI_CISC(iRegL dst, iRegI src, flagsReg cr) %{
6318 match(Set dst (SubL dst (ConvI2L src)));
6319 effect(KILL cr);
6320 size(4);
6321 format %{ "SGFR $dst, $src\t # int CISC ALU" %}
6322 opcode(SGFR_ZOPC);
6323 ins_encode(z_rreform(dst, src));
6324 ins_pipe(pipe_class_dummy);
6325 %}
6326
6327 instruct subL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6328 match(Set dst (SubL dst (ConvI2L (LoadI src))));
6329 effect(KILL cr);
6330 ins_cost(MEMORY_REF_COST);
6331 size(Z_DISP3_SIZE);
6332 format %{ "SGF $dst, $src\t # long/int" %}
6333 opcode(SGF_ZOPC, SGF_ZOPC);
6334 ins_encode(z_form_rt_mem_opt(dst, src));
6335 ins_pipe(pipe_class_dummy);
6336 %}
6337
6338 instruct subL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6339 match(Set dst (SubL dst (LoadL src)));
6340 effect(KILL cr);
6341 ins_cost(MEMORY_REF_COST);
6342 size(Z_DISP3_SIZE);
6343 format %{ "SG $dst, $src\t # long" %}
6344 opcode(SG_ZOPC, SG_ZOPC);
6345 ins_encode(z_form_rt_mem_opt(dst, src));
6346 ins_pipe(pipe_class_dummy);
6347 %}
6348
6349 // Moved declaration of negL_reg_reg before encode nodes, where it is used.
6350
6351 // MUL
6352
6353 // Register Multiplication
6354 instruct mulI_reg_reg(iRegI dst, iRegI src) %{
6355 match(Set dst (MulI dst src));
6356 ins_cost(DEFAULT_COST);
6357 size(4);
6358 format %{ "MSR $dst, $src" %}
6359 opcode(MSR_ZOPC);
6360 ins_encode(z_rreform(dst, src));
6361 ins_pipe(pipe_class_dummy);
6362 %}
6363
6364 // Immediate Multiplication
6365 instruct mulI_reg_imm16(iRegI dst, immI16 con) %{
6366 match(Set dst (MulI dst con));
6367 ins_cost(DEFAULT_COST);
6368 // TODO: s390 port size(FIXED_SIZE);
6369 format %{ "MHI $dst,$con" %}
6370 opcode(MHI_ZOPC);
6371 ins_encode(z_riform_signed(dst,con));
6372 ins_pipe(pipe_class_dummy);
6373 %}
6374
6375 // Immediate (32bit) Multiplication
6376 instruct mulI_reg_imm32(iRegI dst, immI con) %{
6377 match(Set dst (MulI dst con));
6378 ins_cost(DEFAULT_COST);
6379 size(6);
6380 format %{ "MSFI $dst,$con" %}
6381 opcode(MSFI_ZOPC);
6382 ins_encode(z_rilform_signed(dst,con));
6383 ins_pipe(pipe_class_dummy);
6384 %}
6385
6386 instruct mulI_Reg_mem(iRegI dst, memory src)%{
6387 match(Set dst (MulI dst (LoadI src)));
6388 ins_cost(MEMORY_REF_COST);
6389 // TODO: s390 port size(VARIABLE_SIZE);
6390 format %{ "MS(Y) $dst, $src\t # int" %}
6391 opcode(MSY_ZOPC, MS_ZOPC);
6392 ins_encode(z_form_rt_mem_opt(dst, src));
6393 ins_pipe(pipe_class_dummy);
6394 %}
6395
6396 //
6397
6398 instruct mulL_reg_regI(iRegL dst, iRegI src) %{
6399 match(Set dst (MulL dst (ConvI2L src)));
6400 ins_cost(DEFAULT_COST);
6401 // TODO: s390 port size(FIXED_SIZE);
6402 format %{ "MSGFR $dst $src\t # long/int" %}
6403 opcode(MSGFR_ZOPC);
6404 ins_encode(z_rreform(dst, src));
6405 ins_pipe(pipe_class_dummy);
6406 %}
6407
6408 instruct mulL_reg_reg(iRegL dst, iRegL src) %{
6409 match(Set dst (MulL dst src));
6410 ins_cost(DEFAULT_COST);
6411 size(4);
6412 format %{ "MSGR $dst $src\t # long" %}
6413 opcode(MSGR_ZOPC);
6414 ins_encode(z_rreform(dst, src));
6415 ins_pipe(pipe_class_dummy);
6416 %}
6417
6418 // Immediate Multiplication
6419 instruct mulL_reg_imm16(iRegL dst, immL16 src) %{
6420 match(Set dst (MulL dst src));
6421 ins_cost(DEFAULT_COST);
6422 // TODO: s390 port size(FIXED_SIZE);
6423 format %{ "MGHI $dst,$src\t # long" %}
6424 opcode(MGHI_ZOPC);
6425 ins_encode(z_riform_signed(dst, src));
6426 ins_pipe(pipe_class_dummy);
6427 %}
6428
6429 // Immediate (32bit) Multiplication
6430 instruct mulL_reg_imm32(iRegL dst, immL32 con) %{
6431 match(Set dst (MulL dst con));
6432 ins_cost(DEFAULT_COST);
6433 size(6);
6434 format %{ "MSGFI $dst,$con" %}
6435 opcode(MSGFI_ZOPC);
6436 ins_encode(z_rilform_signed(dst,con));
6437 ins_pipe(pipe_class_dummy);
6438 %}
6439
6440 instruct mulL_Reg_memI(iRegL dst, memory src)%{
6441 match(Set dst (MulL dst (ConvI2L (LoadI src))));
6442 ins_cost(MEMORY_REF_COST);
6443 size(Z_DISP3_SIZE);
6444 format %{ "MSGF $dst, $src\t # long" %}
6445 opcode(MSGF_ZOPC, MSGF_ZOPC);
6446 ins_encode(z_form_rt_mem_opt(dst, src));
6447 ins_pipe(pipe_class_dummy);
6448 %}
6449
6450 instruct mulL_Reg_mem(iRegL dst, memory src)%{
6451 match(Set dst (MulL dst (LoadL src)));
6452 ins_cost(MEMORY_REF_COST);
6453 size(Z_DISP3_SIZE);
6454 format %{ "MSG $dst, $src\t # long" %}
6455 opcode(MSG_ZOPC, MSG_ZOPC);
6456 ins_encode(z_form_rt_mem_opt(dst, src));
6457 ins_pipe(pipe_class_dummy);
6458 %}
6459
6460 // DIV
6461
6462 // Integer DIVMOD with Register, both quotient and mod results
6463 instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{
6464 match(DivModI dst1src1 src2);
6465 effect(KILL cr);
6466 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6467 size(VM_Version::has_CompareBranch() ? 24 : 26);
6468 format %{ "DIVMODI ($dst1src1, $dst2) $src2" %}
6469 ins_encode %{
6470 Register d1s1 = $dst1src1$$Register;
6471 Register d2 = $dst2$$Register;
6472 Register s2 = $src2$$Register;
6473
6474 assert_different_registers(d1s1, s2);
6475
6476 Label do_div, done_div;
6477 if (VM_Version::has_CompareBranch()) {
6478 __ z_cij(s2, -1, Assembler::bcondNotEqual, do_div);
6479 } else {
6480 __ z_chi(s2, -1);
6481 __ z_brne(do_div);
6482 }
6483 __ z_lcr(d1s1, d1s1);
6484 __ clear_reg(d2, false, false);
6485 __ z_bru(done_div);
6486 __ bind(do_div);
6487 __ z_lgfr(d1s1, d1s1);
6488 __ z_dsgfr(d2, s2);
6489 __ bind(done_div);
6490 %}
6491 ins_pipe(pipe_class_dummy);
6492 %}
6493
6494
6495 // Register Division
6496 instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{
6497 match(Set dst (DivI src1 src2));
6498 effect(KILL tmp, KILL cr);
6499 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6500 size(VM_Version::has_CompareBranch() ? 20 : 22);
6501 format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %}
6502 ins_encode %{
6503 Register a = $src1$$Register;
6504 Register b = $src2$$Register;
6505 Register t = $dst$$Register;
6506
6507 assert_different_registers(t, b);
6508
6509 Label do_div, done_div;
6510 if (VM_Version::has_CompareBranch()) {
6511 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6512 } else {
6513 __ z_chi(b, -1);
6514 __ z_brne(do_div);
6515 }
6516 __ z_lcr(t, a);
6517 __ z_bru(done_div);
6518 __ bind(do_div);
6519 __ z_lgfr(t, a);
6520 __ z_dsgfr(t->predecessor()/* t is odd part of a register pair. */, b);
6521 __ bind(done_div);
6522 %}
6523 ins_pipe(pipe_class_dummy);
6524 %}
6525
6526 // Immediate Division
6527 instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, flagsReg cr) %{
6528 match(Set dst (DivI src1 src2));
6529 effect(KILL tmp, KILL cr); // R0 is killed, too.
6530 ins_cost(2 * DEFAULT_COST);
6531 // TODO: s390 port size(VARIABLE_SIZE);
6532 format %{ "DIV_const $dst,$src1,$src2" %}
6533 ins_encode %{
6534 // No sign extension of Rdividend needed here.
6535 if ($src2$$constant != -1) {
6536 __ z_lghi(Z_R0_scratch, $src2$$constant);
6537 __ z_lgfr($dst$$Register, $src1$$Register);
6538 __ z_dsgfr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6539 } else {
6540 __ z_lcr($dst$$Register, $src1$$Register);
6541 }
6542 %}
6543 ins_pipe(pipe_class_dummy);
6544 %}
6545
6546 // Long DIVMOD with Register, both quotient and mod results
6547 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{
6548 match(DivModL dst1src1 src2);
6549 effect(KILL cr);
6550 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6551 size(VM_Version::has_CompareBranch() ? 22 : 24);
6552 format %{ "DIVMODL ($dst1src1, $dst2) $src2" %}
6553 ins_encode %{
6554 Register d1s1 = $dst1src1$$Register;
6555 Register d2 = $dst2$$Register;
6556 Register s2 = $src2$$Register;
6557
6558 Label do_div, done_div;
6559 if (VM_Version::has_CompareBranch()) {
6560 __ z_cgij(s2, -1, Assembler::bcondNotEqual, do_div);
6561 } else {
6562 __ z_cghi(s2, -1);
6563 __ z_brne(do_div);
6564 }
6565 __ z_lcgr(d1s1, d1s1);
6566 // indicate unused result
6567 (void) __ clear_reg(d2, true, false);
6568 __ z_bru(done_div);
6569 __ bind(do_div);
6570 __ z_dsgr(d2, s2);
6571 __ bind(done_div);
6572 %}
6573 ins_pipe(pipe_class_dummy);
6574 %}
6575
6576 // Register Long Division
6577 instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{
6578 match(Set dst (DivL dst src));
6579 effect(KILL tmp, KILL cr);
6580 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6581 size(VM_Version::has_CompareBranch() ? 18 : 20);
6582 format %{ "DIVG_checked $dst, $src\t # long, treats special case 0x80../-1" %}
6583 ins_encode %{
6584 Register b = $src$$Register;
6585 Register t = $dst$$Register;
6586
6587 Label done_div;
6588 __ z_lcgr(t, t); // Does no harm. divisor is in other register.
6589 if (VM_Version::has_CompareBranch()) {
6590 __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6591 } else {
6592 __ z_cghi(b, -1);
6593 __ z_bre(done_div);
6594 }
6595 __ z_lcgr(t, t); // Restore sign.
6596 __ z_dsgr(t->predecessor()/* t is odd part of a register pair. */, b);
6597 __ bind(done_div);
6598 %}
6599 ins_pipe(pipe_class_dummy);
6600 %}
6601
6602 // Immediate Long Division
6603 instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{
6604 match(Set dst (DivL src1 src2));
6605 effect(KILL tmp, KILL cr); // R0 is killed, too.
6606 ins_cost(2 * DEFAULT_COST);
6607 // TODO: s390 port size(VARIABLE_SIZE);
6608 format %{ "DIVG_const $dst,$src1,$src2\t # long" %}
6609 ins_encode %{
6610 if ($src2$$constant != -1) {
6611 __ z_lghi(Z_R0_scratch, $src2$$constant);
6612 __ lgr_if_needed($dst$$Register, $src1$$Register);
6613 __ z_dsgr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6614 } else {
6615 __ z_lcgr($dst$$Register, $src1$$Register);
6616 }
6617 %}
6618 ins_pipe(pipe_class_dummy);
6619 %}
6620
6621 // REM
6622
6623 // Integer Remainder
6624 // Register Remainder
6625 instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp, flagsReg cr) %{
6626 match(Set dst (ModI src1 src2));
6627 effect(KILL tmp, KILL cr);
6628 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6629 // TODO: s390 port size(VARIABLE_SIZE);
6630 format %{ "MOD_checked $dst,$src1,$src2" %}
6631 ins_encode %{
6632 Register a = $src1$$Register;
6633 Register b = $src2$$Register;
6634 Register t = $dst$$Register;
6635 assert_different_registers(t->successor(), b);
6636
6637 Label do_div, done_div;
6638
6639 if ((t->encoding() != b->encoding()) && (t->encoding() != a->encoding())) {
6640 (void) __ clear_reg(t, true, false); // Does no harm. Operands are in other regs.
6641 if (VM_Version::has_CompareBranch()) {
6642 __ z_cij(b, -1, Assembler::bcondEqual, done_div);
6643 } else {
6644 __ z_chi(b, -1);
6645 __ z_bre(done_div);
6646 }
6647 __ z_lgfr(t->successor(), a);
6648 __ z_dsgfr(t/* t is even part of a register pair. */, b);
6649 } else {
6650 if (VM_Version::has_CompareBranch()) {
6651 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6652 } else {
6653 __ z_chi(b, -1);
6654 __ z_brne(do_div);
6655 }
6656 __ clear_reg(t, true, false);
6657 __ z_bru(done_div);
6658 __ bind(do_div);
6659 __ z_lgfr(t->successor(), a);
6660 __ z_dsgfr(t/* t is even part of a register pair. */, b);
6661 }
6662 __ bind(done_div);
6663 %}
6664 ins_pipe(pipe_class_dummy);
6665 %}
6666
6667 // Immediate Remainder
6668 instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{
6669 match(Set dst (ModI src1 src2));
6670 effect(KILL tmp, KILL cr); // R0 is killed, too.
6671 ins_cost(3 * DEFAULT_COST);
6672 // TODO: s390 port size(VARIABLE_SIZE);
6673 format %{ "MOD_const $dst,src1,$src2" %}
6674 ins_encode %{
6675 assert_different_registers($dst$$Register, $src1$$Register);
6676 assert_different_registers($dst$$Register->successor(), $src1$$Register);
6677 int divisor = $src2$$constant;
6678
6679 if (divisor != -1) {
6680 __ z_lghi(Z_R0_scratch, divisor);
6681 __ z_lgfr($dst$$Register->successor(), $src1$$Register);
6682 __ z_dsgfr($dst$$Register/* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
6683 } else {
6684 __ clear_reg($dst$$Register, true, false);
6685 }
6686 %}
6687 ins_pipe(pipe_class_dummy);
6688 %}
6689
6690 // Register Long Remainder
6691 instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{
6692 match(Set dst (ModL src1 src2));
6693 effect(KILL src1, KILL cr); // R0 is killed, too.
6694 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6695 // TODO: s390 port size(VARIABLE_SIZE);
6696 format %{ "MODG_checked $dst,$src1,$src2" %}
6697 ins_encode %{
6698 Register a = $src1$$Register;
6699 Register b = $src2$$Register;
6700 Register t = $dst$$Register;
6701 assert(t->successor() == a, "(t,a) is an even-odd pair" );
6702
6703 Label do_div, done_div;
6704 if (t->encoding() != b->encoding()) {
6705 (void) __ clear_reg(t, true, false); // Does no harm. Dividend is in successor.
6706 if (VM_Version::has_CompareBranch()) {
6707 __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6708 } else {
6709 __ z_cghi(b, -1);
6710 __ z_bre(done_div);
6711 }
6712 __ z_dsgr(t, b);
6713 } else {
6714 if (VM_Version::has_CompareBranch()) {
6715 __ z_cgij(b, -1, Assembler::bcondNotEqual, do_div);
6716 } else {
6717 __ z_cghi(b, -1);
6718 __ z_brne(do_div);
6719 }
6720 __ clear_reg(t, true, false);
6721 __ z_bru(done_div);
6722 __ bind(do_div);
6723 __ z_dsgr(t, b);
6724 }
6725 __ bind(done_div);
6726 %}
6727 ins_pipe(pipe_class_dummy);
6728 %}
6729
6730 // Register Long Remainder
6731 instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{
6732 match(Set dst (ModL src1 src2));
6733 effect(KILL tmp, KILL cr); // R0 is killed, too.
6734 ins_cost(3 * DEFAULT_COST);
6735 // TODO: s390 port size(VARIABLE_SIZE);
6736 format %{ "MODG_const $dst,src1,$src2\t # long" %}
6737 ins_encode %{
6738 int divisor = $src2$$constant;
6739 if (divisor != -1) {
6740 __ z_lghi(Z_R0_scratch, divisor);
6741 __ z_lgr($dst$$Register->successor(), $src1$$Register);
6742 __ z_dsgr($dst$$Register /* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
6743 } else {
6744 __ clear_reg($dst$$Register, true, false);
6745 }
6746 %}
6747 ins_pipe(pipe_class_dummy);
6748 %}
6749
6750 // SHIFT
6751
6752 // Shift left logical
6753
6754 // Register Shift Left variable
6755 instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{
6756 match(Set dst (LShiftI src nbits));
6757 effect(KILL cr); // R1 is killed, too.
6758 ins_cost(3 * DEFAULT_COST);
6759 size(14);
6760 format %{ "SLL $dst,$src,[$nbits] & 31\t# use RISC-like SLLG also for int" %}
6761 ins_encode %{
6762 __ z_lgr(Z_R1_scratch, $nbits$$Register);
6763 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6764 __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch);
6765 %}
6766 ins_pipe(pipe_class_dummy);
6767 %}
6768
6769 // Register Shift Left Immediate
6770 // Constant shift count is masked in ideal graph already.
6771 instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{
6772 match(Set dst (LShiftI src nbits));
6773 size(6);
6774 format %{ "SLL $dst,$src,$nbits\t# use RISC-like SLLG also for int" %}
6775 ins_encode %{
6776 int Nbit = $nbits$$constant;
6777 __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6778 %}
6779 ins_pipe(pipe_class_dummy);
6780 %}
6781
6782 // Register Shift Left Immediate by 1bit
6783 instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{
6784 match(Set dst (LShiftI src nbits));
6785 predicate(PreferLAoverADD);
6786 ins_cost(DEFAULT_COST_LOW);
6787 size(4);
6788 format %{ "LA $dst,#0($src,$src)\t # SLL by 1 (int)" %}
6789 ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %}
6790 ins_pipe(pipe_class_dummy);
6791 %}
6792
6793 // Register Shift Left Long
6794 instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{
6795 match(Set dst (LShiftL src1 nbits));
6796 size(6);
6797 format %{ "SLLG $dst,$src1,[$nbits]" %}
6798 opcode(SLLG_ZOPC);
6799 ins_encode(z_rsyform_reg_reg(dst, src1, nbits));
6800 ins_pipe(pipe_class_dummy);
6801 %}
6802
6803 // Register Shift Left Long Immediate
6804 instruct sllL_reg_imm(iRegL dst, iRegL src1, immI nbits) %{
6805 match(Set dst (LShiftL src1 nbits));
6806 size(6);
6807 format %{ "SLLG $dst,$src1,$nbits" %}
6808 opcode(SLLG_ZOPC);
6809 ins_encode(z_rsyform_const(dst, src1, nbits));
6810 ins_pipe(pipe_class_dummy);
6811 %}
6812
6813 // Register Shift Left Long Immediate by 1bit
6814 instruct sllL_reg_imm_1(iRegL dst, iRegL src1, immI_1 nbits) %{
6815 match(Set dst (LShiftL src1 nbits));
6816 predicate(PreferLAoverADD);
6817 ins_cost(DEFAULT_COST_LOW);
6818 size(4);
6819 format %{ "LA $dst,#0($src1,$src1)\t # SLLG by 1 (long)" %}
6820 ins_encode %{ __ z_la($dst$$Register, 0, $src1$$Register, $src1$$Register); %}
6821 ins_pipe(pipe_class_dummy);
6822 %}
6823
6824 // Shift right arithmetic
6825
6826 // Register Arithmetic Shift Right
6827 instruct sraI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
6828 match(Set dst (RShiftI dst src));
6829 effect(KILL cr); // R1 is killed, too.
6830 ins_cost(3 * DEFAULT_COST);
6831 size(12);
6832 format %{ "SRA $dst,[$src] & 31" %}
6833 ins_encode %{
6834 __ z_lgr(Z_R1_scratch, $src$$Register);
6835 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6836 __ z_sra($dst$$Register, 0, Z_R1_scratch);
6837 %}
6838 ins_pipe(pipe_class_dummy);
6839 %}
6840
6841 // Register Arithmetic Shift Right Immediate
6842 // Constant shift count is masked in ideal graph already.
6843 instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{
6844 match(Set dst (RShiftI dst src));
6845 effect(KILL cr);
6846 size(4);
6847 format %{ "SRA $dst,$src" %}
6848 ins_encode %{
6849 int Nbit = $src$$constant;
6850 __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6851 %}
6852 ins_pipe(pipe_class_dummy);
6853 %}
6854
6855 // Register Arithmetic Shift Right Long
6856 instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{
6857 match(Set dst (RShiftL src1 src2));
6858 effect(KILL cr);
6859 size(6);
6860 format %{ "SRAG $dst,$src1,[$src2]" %}
6861 opcode(SRAG_ZOPC);
6862 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
6863 ins_pipe(pipe_class_dummy);
6864 %}
6865
6866 // Register Arithmetic Shift Right Long Immediate
6867 instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{
6868 match(Set dst (RShiftL src1 src2));
6869 effect(KILL cr);
6870 size(6);
6871 format %{ "SRAG $dst,$src1,$src2" %}
6872 opcode(SRAG_ZOPC);
6873 ins_encode(z_rsyform_const(dst, src1, src2));
6874 ins_pipe(pipe_class_dummy);
6875 %}
6876
6877 // Shift right logical
6878
6879 // Register Shift Right
6880 instruct srlI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
6881 match(Set dst (URShiftI dst src));
6882 effect(KILL cr); // R1 is killed, too.
6883 ins_cost(3 * DEFAULT_COST);
6884 size(12);
6885 format %{ "SRL $dst,[$src] & 31" %}
6886 ins_encode %{
6887 __ z_lgr(Z_R1_scratch, $src$$Register);
6888 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6889 __ z_srl($dst$$Register, 0, Z_R1_scratch);
6890 %}
6891 ins_pipe(pipe_class_dummy);
6892 %}
6893
6894 // Register Shift Right Immediate
6895 // Constant shift count is masked in ideal graph already.
6896 instruct srlI_reg_imm(iRegI dst, immI src) %{
6897 match(Set dst (URShiftI dst src));
6898 size(4);
6899 format %{ "SRL $dst,$src" %}
6900 ins_encode %{
6901 int Nbit = $src$$constant;
6902 __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6903 %}
6904 ins_pipe(pipe_class_dummy);
6905 %}
6906
6907 // Register Shift Right Long
6908 instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
6909 match(Set dst (URShiftL src1 src2));
6910 size(6);
6911 format %{ "SRLG $dst,$src1,[$src2]" %}
6912 opcode(SRLG_ZOPC);
6913 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
6914 ins_pipe(pipe_class_dummy);
6915 %}
6916
6917 // Register Shift Right Long Immediate
6918 instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{
6919 match(Set dst (URShiftL src1 src2));
6920 size(6);
6921 format %{ "SRLG $dst,$src1,$src2" %}
6922 opcode(SRLG_ZOPC);
6923 ins_encode(z_rsyform_const(dst, src1, src2));
6924 ins_pipe(pipe_class_dummy);
6925 %}
6926
6927 // Register Shift Right Immediate with a CastP2X
6928 instruct srlP_reg_imm(iRegL dst, iRegP_N2P src1, immI src2) %{
6929 match(Set dst (URShiftL (CastP2X src1) src2));
6930 size(6);
6931 format %{ "SRLG $dst,$src1,$src2\t # Cast ptr $src1 to long and shift" %}
6932 opcode(SRLG_ZOPC);
6933 ins_encode(z_rsyform_const(dst, src1, src2));
6934 ins_pipe(pipe_class_dummy);
6935 %}
6936
6937 //----------Rotate Instructions------------------------------------------------
6938
6939 // Rotate left 32bit.
6940 instruct rotlI_reg_immI8(iRegI dst, iRegI src, immI8 lshift, immI8 rshift) %{
6941 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
6942 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
6943 size(6);
6944 format %{ "RLL $dst,$src,$lshift\t # ROTL32" %}
6945 opcode(RLL_ZOPC);
6946 ins_encode(z_rsyform_const(dst, src, lshift));
6947 ins_pipe(pipe_class_dummy);
6948 %}
6949
6950 // Rotate left 64bit.
6951 instruct rotlL_reg_immI8(iRegL dst, iRegL src, immI8 lshift, immI8 rshift) %{
6952 match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift)));
6953 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
6954 size(6);
6955 format %{ "RLLG $dst,$src,$lshift\t # ROTL64" %}
6956 opcode(RLLG_ZOPC);
6957 ins_encode(z_rsyform_const(dst, src, lshift));
6958 ins_pipe(pipe_class_dummy);
6959 %}
6960
6961 // Rotate right 32bit.
6962 instruct rotrI_reg_immI8(iRegI dst, iRegI src, immI8 rshift, immI8 lshift) %{
6963 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
6964 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
6965 // TODO: s390 port size(FIXED_SIZE);
6966 format %{ "RLL $dst,$src,$rshift\t # ROTR32" %}
6967 opcode(RLL_ZOPC);
6968 ins_encode(z_rsyform_const(dst, src, rshift));
6969 ins_pipe(pipe_class_dummy);
6970 %}
6971
6972 // Rotate right 64bit.
6973 instruct rotrL_reg_immI8(iRegL dst, iRegL src, immI8 rshift, immI8 lshift) %{
6974 match(Set dst (OrL (URShiftL src rshift) (LShiftL src lshift)));
6975 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
6976 // TODO: s390 port size(FIXED_SIZE);
6977 format %{ "RLLG $dst,$src,$rshift\t # ROTR64" %}
6978 opcode(RLLG_ZOPC);
6979 ins_encode(z_rsyform_const(dst, src, rshift));
6980 ins_pipe(pipe_class_dummy);
6981 %}
6982
6983
6984 //----------Overflow Math Instructions-----------------------------------------
6985
6986 instruct overflowAddI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
6987 match(Set cr (OverflowAddI op1 op2));
6988 effect(DEF cr, USE op1, USE op2);
6989 // TODO: s390 port size(FIXED_SIZE);
6990 format %{ "AR $op1,$op2\t # overflow check int" %}
6991 ins_encode %{
6992 __ z_lr(Z_R0_scratch, $op1$$Register);
6993 __ z_ar(Z_R0_scratch, $op2$$Register);
6994 %}
6995 ins_pipe(pipe_class_dummy);
6996 %}
6997
6998 instruct overflowAddI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
6999 match(Set cr (OverflowAddI op1 op2));
7000 effect(DEF cr, USE op1, USE op2);
7001 // TODO: s390 port size(VARIABLE_SIZE);
7002 format %{ "AR $op1,$op2\t # overflow check int" %}
7003 ins_encode %{
7004 __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7005 __ z_ar(Z_R0_scratch, $op1$$Register);
7006 %}
7007 ins_pipe(pipe_class_dummy);
7008 %}
7009
7010 instruct overflowAddL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7011 match(Set cr (OverflowAddL op1 op2));
7012 effect(DEF cr, USE op1, USE op2);
7013 // TODO: s390 port size(FIXED_SIZE);
7014 format %{ "AGR $op1,$op2\t # overflow check long" %}
7015 ins_encode %{
7016 __ z_lgr(Z_R0_scratch, $op1$$Register);
7017 __ z_agr(Z_R0_scratch, $op2$$Register);
7018 %}
7019 ins_pipe(pipe_class_dummy);
7020 %}
7021
7022 instruct overflowAddL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7023 match(Set cr (OverflowAddL op1 op2));
7024 effect(DEF cr, USE op1, USE op2);
7025 // TODO: s390 port size(VARIABLE_SIZE);
7026 format %{ "AGR $op1,$op2\t # overflow check long" %}
7027 ins_encode %{
7028 __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7029 __ z_agr(Z_R0_scratch, $op1$$Register);
7030 %}
7031 ins_pipe(pipe_class_dummy);
7032 %}
7033
7034 instruct overflowSubI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
7035 match(Set cr (OverflowSubI op1 op2));
7036 effect(DEF cr, USE op1, USE op2);
7037 // TODO: s390 port size(FIXED_SIZE);
7038 format %{ "SR $op1,$op2\t # overflow check int" %}
7039 ins_encode %{
7040 __ z_lr(Z_R0_scratch, $op1$$Register);
7041 __ z_sr(Z_R0_scratch, $op2$$Register);
7042 %}
7043 ins_pipe(pipe_class_dummy);
7044 %}
7045
7046 instruct overflowSubI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
7047 match(Set cr (OverflowSubI op1 op2));
7048 effect(DEF cr, USE op1, USE op2);
7049 // TODO: s390 port size(VARIABLE_SIZE);
7050 format %{ "SR $op1,$op2\t # overflow check int" %}
7051 ins_encode %{
7052 __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7053 __ z_lr(Z_R0_scratch, $op1$$Register);
7054 __ z_sr(Z_R0_scratch, Z_R1_scratch);
7055 %}
7056 ins_pipe(pipe_class_dummy);
7057 %}
7058
7059 instruct overflowSubL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7060 match(Set cr (OverflowSubL op1 op2));
7061 effect(DEF cr, USE op1, USE op2);
7062 // TODO: s390 port size(FIXED_SIZE);
7063 format %{ "SGR $op1,$op2\t # overflow check long" %}
7064 ins_encode %{
7065 __ z_lgr(Z_R0_scratch, $op1$$Register);
7066 __ z_sgr(Z_R0_scratch, $op2$$Register);
7067 %}
7068 ins_pipe(pipe_class_dummy);
7069 %}
7070
7071 instruct overflowSubL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7072 match(Set cr (OverflowSubL op1 op2));
7073 effect(DEF cr, USE op1, USE op2);
7074 // TODO: s390 port size(VARIABLE_SIZE);
7075 format %{ "SGR $op1,$op2\t # overflow check long" %}
7076 ins_encode %{
7077 __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7078 __ z_lgr(Z_R0_scratch, $op1$$Register);
7079 __ z_sgr(Z_R0_scratch, Z_R1_scratch);
7080 %}
7081 ins_pipe(pipe_class_dummy);
7082 %}
7083
7084 instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{
7085 match(Set cr (OverflowSubI zero op2));
7086 effect(DEF cr, USE op2);
7087 format %{ "NEG $op2\t# overflow check int" %}
7088 ins_encode %{
7089 __ clear_reg(Z_R0_scratch, false, false);
7090 __ z_sr(Z_R0_scratch, $op2$$Register);
7091 %}
7092 ins_pipe(pipe_class_dummy);
7093 %}
7094
7095 instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{
7096 match(Set cr (OverflowSubL zero op2));
7097 effect(DEF cr, USE op2);
7098 format %{ "NEGG $op2\t# overflow check long" %}
7099 ins_encode %{
7100 __ clear_reg(Z_R0_scratch, true, false);
7101 __ z_sgr(Z_R0_scratch, $op2$$Register);
7102 %}
7103 ins_pipe(pipe_class_dummy);
7104 %}
7105
7106 // No intrinsics for multiplication, since there is no easy way
7107 // to check for overflow.
7108
7109
7110 //----------Floating Point Arithmetic Instructions-----------------------------
7111
7112 // ADD
7113
7114 // Add float single precision
7115 instruct addF_reg_reg(regF dst, regF src, flagsReg cr) %{
7116 match(Set dst (AddF dst src));
7117 effect(KILL cr);
7118 ins_cost(ALU_REG_COST);
7119 size(4);
7120 format %{ "AEBR $dst,$src" %}
7121 opcode(AEBR_ZOPC);
7122 ins_encode(z_rreform(dst, src));
7123 ins_pipe(pipe_class_dummy);
7124 %}
7125
7126 instruct addF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7127 match(Set dst (AddF dst (LoadF src)));
7128 effect(KILL cr);
7129 ins_cost(ALU_MEMORY_COST);
7130 size(6);
7131 format %{ "AEB $dst,$src\t # floatMemory" %}
7132 opcode(AEB_ZOPC);
7133 ins_encode(z_form_rt_memFP(dst, src));
7134 ins_pipe(pipe_class_dummy);
7135 %}
7136
7137 // Add float double precision
7138 instruct addD_reg_reg(regD dst, regD src, flagsReg cr) %{
7139 match(Set dst (AddD dst src));
7140 effect(KILL cr);
7141 ins_cost(ALU_REG_COST);
7142 size(4);
7143 format %{ "ADBR $dst,$src" %}
7144 opcode(ADBR_ZOPC);
7145 ins_encode(z_rreform(dst, src));
7146 ins_pipe(pipe_class_dummy);
7147 %}
7148
7149 instruct addD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7150 match(Set dst (AddD dst (LoadD src)));
7151 effect(KILL cr);
7152 ins_cost(ALU_MEMORY_COST);
7153 size(6);
7154 format %{ "ADB $dst,$src\t # doubleMemory" %}
7155 opcode(ADB_ZOPC);
7156 ins_encode(z_form_rt_memFP(dst, src));
7157 ins_pipe(pipe_class_dummy);
7158 %}
7159
7160 // SUB
7161
7162 // Sub float single precision
7163 instruct subF_reg_reg(regF dst, regF src, flagsReg cr) %{
7164 match(Set dst (SubF dst src));
7165 effect(KILL cr);
7166 ins_cost(ALU_REG_COST);
7167 size(4);
7168 format %{ "SEBR $dst,$src" %}
7169 opcode(SEBR_ZOPC);
7170 ins_encode(z_rreform(dst, src));
7171 ins_pipe(pipe_class_dummy);
7172 %}
7173
7174 instruct subF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7175 match(Set dst (SubF dst (LoadF src)));
7176 effect(KILL cr);
7177 ins_cost(ALU_MEMORY_COST);
7178 size(6);
7179 format %{ "SEB $dst,$src\t # floatMemory" %}
7180 opcode(SEB_ZOPC);
7181 ins_encode(z_form_rt_memFP(dst, src));
7182 ins_pipe(pipe_class_dummy);
7183 %}
7184
7185 // Sub float double precision
7186 instruct subD_reg_reg(regD dst, regD src, flagsReg cr) %{
7187 match(Set dst (SubD dst src));
7188 effect(KILL cr);
7189 ins_cost(ALU_REG_COST);
7190 size(4);
7191 format %{ "SDBR $dst,$src" %}
7192 opcode(SDBR_ZOPC);
7193 ins_encode(z_rreform(dst, src));
7194 ins_pipe(pipe_class_dummy);
7195 %}
7196
7197 instruct subD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7198 match(Set dst (SubD dst (LoadD src)));
7199 effect(KILL cr);
7200 ins_cost(ALU_MEMORY_COST);
7201 size(6);
7202 format %{ "SDB $dst,$src\t # doubleMemory" %}
7203 opcode(SDB_ZOPC);
7204 ins_encode(z_form_rt_memFP(dst, src));
7205 ins_pipe(pipe_class_dummy);
7206 %}
7207
7208 // MUL
7209
7210 // Mul float single precision
7211 instruct mulF_reg_reg(regF dst, regF src) %{
7212 match(Set dst (MulF dst src));
7213 // CC unchanged by MUL.
7214 ins_cost(ALU_REG_COST);
7215 size(4);
7216 format %{ "MEEBR $dst,$src" %}
7217 opcode(MEEBR_ZOPC);
7218 ins_encode(z_rreform(dst, src));
7219 ins_pipe(pipe_class_dummy);
7220 %}
7221
7222 instruct mulF_reg_mem(regF dst, memoryRX src)%{
7223 match(Set dst (MulF dst (LoadF src)));
7224 // CC unchanged by MUL.
7225 ins_cost(ALU_MEMORY_COST);
7226 size(6);
7227 format %{ "MEEB $dst,$src\t # floatMemory" %}
7228 opcode(MEEB_ZOPC);
7229 ins_encode(z_form_rt_memFP(dst, src));
7230 ins_pipe(pipe_class_dummy);
7231 %}
7232
7233 // Mul float double precision
7234 instruct mulD_reg_reg(regD dst, regD src) %{
7235 match(Set dst (MulD dst src));
7236 // CC unchanged by MUL.
7237 ins_cost(ALU_REG_COST);
7238 size(4);
7239 format %{ "MDBR $dst,$src" %}
7240 opcode(MDBR_ZOPC);
7241 ins_encode(z_rreform(dst, src));
7242 ins_pipe(pipe_class_dummy);
7243 %}
7244
7245 instruct mulD_reg_mem(regD dst, memoryRX src)%{
7246 match(Set dst (MulD dst (LoadD src)));
7247 // CC unchanged by MUL.
7248 ins_cost(ALU_MEMORY_COST);
7249 size(6);
7250 format %{ "MDB $dst,$src\t # doubleMemory" %}
7251 opcode(MDB_ZOPC);
7252 ins_encode(z_form_rt_memFP(dst, src));
7253 ins_pipe(pipe_class_dummy);
7254 %}
7255
7256 // Multiply-Accumulate
7257 // src1 * src2 + dst
7258 instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{
7259 match(Set dst (FmaF dst (Binary src1 src2)));
7260 // CC unchanged by MUL-ADD.
7261 ins_cost(ALU_REG_COST);
7262 size(4);
7263 format %{ "MAEBR $dst, $src1, $src2" %}
7264 ins_encode %{
7265 __ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7266 %}
7267 ins_pipe(pipe_class_dummy);
7268 %}
7269
7270 // src1 * src2 + dst
7271 instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{
7272 match(Set dst (FmaD dst (Binary src1 src2)));
7273 // CC unchanged by MUL-ADD.
7274 ins_cost(ALU_REG_COST);
7275 size(4);
7276 format %{ "MADBR $dst, $src1, $src2" %}
7277 ins_encode %{
7278 __ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7279 %}
7280 ins_pipe(pipe_class_dummy);
7281 %}
7282
7283 // src1 * src2 - dst
7284 instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{
7285 match(Set dst (FmaF (NegF dst) (Binary src1 src2)));
7286 // CC unchanged by MUL-SUB.
7287 ins_cost(ALU_REG_COST);
7288 size(4);
7289 format %{ "MSEBR $dst, $src1, $src2" %}
7290 ins_encode %{
7291 __ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7292 %}
7293 ins_pipe(pipe_class_dummy);
7294 %}
7295
7296 // src1 * src2 - dst
7297 instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{
7298 match(Set dst (FmaD (NegD dst) (Binary src1 src2)));
7299 // CC unchanged by MUL-SUB.
7300 ins_cost(ALU_REG_COST);
7301 size(4);
7302 format %{ "MSDBR $dst, $src1, $src2" %}
7303 ins_encode %{
7304 __ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7305 %}
7306 ins_pipe(pipe_class_dummy);
7307 %}
7308
7309 // src1 * src2 + dst
7310 instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7311 match(Set dst (FmaF dst (Binary src1 (LoadF src2))));
7312 // CC unchanged by MUL-ADD.
7313 ins_cost(ALU_MEMORY_COST);
7314 size(6);
7315 format %{ "MAEB $dst, $src1, $src2" %}
7316 ins_encode %{
7317 __ z_maeb($dst$$FloatRegister, $src1$$FloatRegister,
7318 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7319 %}
7320 ins_pipe(pipe_class_dummy);
7321 %}
7322
7323 // src1 * src2 + dst
7324 instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7325 match(Set dst (FmaD dst (Binary src1 (LoadD src2))));
7326 // CC unchanged by MUL-ADD.
7327 ins_cost(ALU_MEMORY_COST);
7328 size(6);
7329 format %{ "MADB $dst, $src1, $src2" %}
7330 ins_encode %{
7331 __ z_madb($dst$$FloatRegister, $src1$$FloatRegister,
7332 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7333 %}
7334 ins_pipe(pipe_class_dummy);
7335 %}
7336
7337 // src1 * src2 - dst
7338 instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7339 match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2))));
7340 // CC unchanged by MUL-SUB.
7341 ins_cost(ALU_MEMORY_COST);
7342 size(6);
7343 format %{ "MSEB $dst, $src1, $src2" %}
7344 ins_encode %{
7345 __ z_mseb($dst$$FloatRegister, $src1$$FloatRegister,
7346 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7347 %}
7348 ins_pipe(pipe_class_dummy);
7349 %}
7350
7351 // src1 * src2 - dst
7352 instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7353 match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2))));
7354 // CC unchanged by MUL-SUB.
7355 ins_cost(ALU_MEMORY_COST);
7356 size(6);
7357 format %{ "MSDB $dst, $src1, $src2" %}
7358 ins_encode %{
7359 __ z_msdb($dst$$FloatRegister, $src1$$FloatRegister,
7360 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7361 %}
7362 ins_pipe(pipe_class_dummy);
7363 %}
7364
7365 // src1 * src2 + dst
7366 instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7367 match(Set dst (FmaF dst (Binary (LoadF src1) src2)));
7368 // CC unchanged by MUL-ADD.
7369 ins_cost(ALU_MEMORY_COST);
7370 size(6);
7371 format %{ "MAEB $dst, $src1, $src2" %}
7372 ins_encode %{
7373 __ z_maeb($dst$$FloatRegister, $src2$$FloatRegister,
7374 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7375 %}
7376 ins_pipe(pipe_class_dummy);
7377 %}
7378
7379 // src1 * src2 + dst
7380 instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7381 match(Set dst (FmaD dst (Binary (LoadD src1) src2)));
7382 // CC unchanged by MUL-ADD.
7383 ins_cost(ALU_MEMORY_COST);
7384 size(6);
7385 format %{ "MADB $dst, $src1, $src2" %}
7386 ins_encode %{
7387 __ z_madb($dst$$FloatRegister, $src2$$FloatRegister,
7388 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7389 %}
7390 ins_pipe(pipe_class_dummy);
7391 %}
7392
7393 // src1 * src2 - dst
7394 instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7395 match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2)));
7396 // CC unchanged by MUL-SUB.
7397 ins_cost(ALU_MEMORY_COST);
7398 size(6);
7399 format %{ "MSEB $dst, $src1, $src2" %}
7400 ins_encode %{
7401 __ z_mseb($dst$$FloatRegister, $src2$$FloatRegister,
7402 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7403 %}
7404 ins_pipe(pipe_class_dummy);
7405 %}
7406
7407 // src1 * src2 - dst
7408 instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7409 match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2)));
7410 // CC unchanged by MUL-SUB.
7411 ins_cost(ALU_MEMORY_COST);
7412 size(6);
7413 format %{ "MSDB $dst, $src1, $src2" %}
7414 ins_encode %{
7415 __ z_msdb($dst$$FloatRegister, $src2$$FloatRegister,
7416 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7417 %}
7418 ins_pipe(pipe_class_dummy);
7419 %}
7420
7421 // DIV
7422
7423 // Div float single precision
7424 instruct divF_reg_reg(regF dst, regF src) %{
7425 match(Set dst (DivF dst src));
7426 // CC unchanged by DIV.
7427 ins_cost(ALU_REG_COST);
7428 size(4);
7429 format %{ "DEBR $dst,$src" %}
7430 opcode(DEBR_ZOPC);
7431 ins_encode(z_rreform(dst, src));
7432 ins_pipe(pipe_class_dummy);
7433 %}
7434
7435 instruct divF_reg_mem(regF dst, memoryRX src)%{
7436 match(Set dst (DivF dst (LoadF src)));
7437 // CC unchanged by DIV.
7438 ins_cost(ALU_MEMORY_COST);
7439 size(6);
7440 format %{ "DEB $dst,$src\t # floatMemory" %}
7441 opcode(DEB_ZOPC);
7442 ins_encode(z_form_rt_memFP(dst, src));
7443 ins_pipe(pipe_class_dummy);
7444 %}
7445
7446 // Div float double precision
7447 instruct divD_reg_reg(regD dst, regD src) %{
7448 match(Set dst (DivD dst src));
7449 // CC unchanged by DIV.
7450 ins_cost(ALU_REG_COST);
7451 size(4);
7452 format %{ "DDBR $dst,$src" %}
7453 opcode(DDBR_ZOPC);
7454 ins_encode(z_rreform(dst, src));
7455 ins_pipe(pipe_class_dummy);
7456 %}
7457
7458 instruct divD_reg_mem(regD dst, memoryRX src)%{
7459 match(Set dst (DivD dst (LoadD src)));
7460 // CC unchanged by DIV.
7461 ins_cost(ALU_MEMORY_COST);
7462 size(6);
7463 format %{ "DDB $dst,$src\t # doubleMemory" %}
7464 opcode(DDB_ZOPC);
7465 ins_encode(z_form_rt_memFP(dst, src));
7466 ins_pipe(pipe_class_dummy);
7467 %}
7468
7469 // ABS
7470
7471 // Absolute float single precision
7472 instruct absF_reg(regF dst, regF src, flagsReg cr) %{
7473 match(Set dst (AbsF src));
7474 effect(KILL cr);
7475 size(4);
7476 format %{ "LPEBR $dst,$src\t float" %}
7477 opcode(LPEBR_ZOPC);
7478 ins_encode(z_rreform(dst, src));
7479 ins_pipe(pipe_class_dummy);
7480 %}
7481
7482 // Absolute float double precision
7483 instruct absD_reg(regD dst, regD src, flagsReg cr) %{
7484 match(Set dst (AbsD src));
7485 effect(KILL cr);
7486 size(4);
7487 format %{ "LPDBR $dst,$src\t double" %}
7488 opcode(LPDBR_ZOPC);
7489 ins_encode(z_rreform(dst, src));
7490 ins_pipe(pipe_class_dummy);
7491 %}
7492
7493 // NEG(ABS)
7494
7495 // Negative absolute float single precision
7496 instruct nabsF_reg(regF dst, regF src, flagsReg cr) %{
7497 match(Set dst (NegF (AbsF src)));
7498 effect(KILL cr);
7499 size(4);
7500 format %{ "LNEBR $dst,$src\t float" %}
7501 opcode(LNEBR_ZOPC);
7502 ins_encode(z_rreform(dst, src));
7503 ins_pipe(pipe_class_dummy);
7504 %}
7505
7506 // Negative absolute float double precision
7507 instruct nabsD_reg(regD dst, regD src, flagsReg cr) %{
7508 match(Set dst (NegD (AbsD src)));
7509 effect(KILL cr);
7510 size(4);
7511 format %{ "LNDBR $dst,$src\t double" %}
7512 opcode(LNDBR_ZOPC);
7513 ins_encode(z_rreform(dst, src));
7514 ins_pipe(pipe_class_dummy);
7515 %}
7516
7517 // NEG
7518
7519 instruct negF_reg(regF dst, regF src, flagsReg cr) %{
7520 match(Set dst (NegF src));
7521 effect(KILL cr);
7522 size(4);
7523 format %{ "NegF $dst,$src\t float" %}
7524 ins_encode %{ __ z_lcebr($dst$$FloatRegister, $src$$FloatRegister); %}
7525 ins_pipe(pipe_class_dummy);
7526 %}
7527
7528 instruct negD_reg(regD dst, regD src, flagsReg cr) %{
7529 match(Set dst (NegD src));
7530 effect(KILL cr);
7531 size(4);
7532 format %{ "NegD $dst,$src\t double" %}
7533 ins_encode %{ __ z_lcdbr($dst$$FloatRegister, $src$$FloatRegister); %}
7534 ins_pipe(pipe_class_dummy);
7535 %}
7536
7537 // SQRT
7538
7539 // Sqrt float precision
7540 instruct sqrtF_reg(regF dst, regF src) %{
7541 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7542 // CC remains unchanged.
7543 ins_cost(ALU_REG_COST);
7544 size(4);
7545 format %{ "SQEBR $dst,$src" %}
7546 opcode(SQEBR_ZOPC);
7547 ins_encode(z_rreform(dst, src));
7548 ins_pipe(pipe_class_dummy);
7549 %}
7550
7551 // Sqrt double precision
7552 instruct sqrtD_reg(regD dst, regD src) %{
7553 match(Set dst (SqrtD src));
7554 // CC remains unchanged.
7555 ins_cost(ALU_REG_COST);
7556 size(4);
7557 format %{ "SQDBR $dst,$src" %}
7558 opcode(SQDBR_ZOPC);
7559 ins_encode(z_rreform(dst, src));
7560 ins_pipe(pipe_class_dummy);
7561 %}
7562
7563 instruct sqrtF_mem(regF dst, memoryRX src) %{
7564 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7565 // CC remains unchanged.
7566 ins_cost(ALU_MEMORY_COST);
7567 size(6);
7568 format %{ "SQEB $dst,$src\t # floatMemory" %}
7569 opcode(SQEB_ZOPC);
7570 ins_encode(z_form_rt_memFP(dst, src));
7571 ins_pipe(pipe_class_dummy);
7572 %}
7573
7574 instruct sqrtD_mem(regD dst, memoryRX src) %{
7575 match(Set dst (SqrtD src));
7576 // CC remains unchanged.
7577 ins_cost(ALU_MEMORY_COST);
7578 // TODO: s390 port size(FIXED_SIZE);
7579 format %{ "SQDB $dst,$src\t # doubleMemory" %}
7580 opcode(SQDB_ZOPC);
7581 ins_encode(z_form_rt_memFP(dst, src));
7582 ins_pipe(pipe_class_dummy);
7583 %}
7584
7585 //----------Logical Instructions-----------------------------------------------
7586
7587 // Register And
7588 instruct andI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7589 match(Set dst (AndI dst src));
7590 effect(KILL cr);
7591 ins_cost(DEFAULT_COST_LOW);
7592 size(2);
7593 format %{ "NR $dst,$src\t # int" %}
7594 opcode(NR_ZOPC);
7595 ins_encode(z_rrform(dst, src));
7596 ins_pipe(pipe_class_dummy);
7597 %}
7598
7599 instruct andI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7600 match(Set dst (AndI dst (LoadI src)));
7601 effect(KILL cr);
7602 ins_cost(MEMORY_REF_COST);
7603 // TODO: s390 port size(VARIABLE_SIZE);
7604 format %{ "N(Y) $dst, $src\t # int" %}
7605 opcode(NY_ZOPC, N_ZOPC);
7606 ins_encode(z_form_rt_mem_opt(dst, src));
7607 ins_pipe(pipe_class_dummy);
7608 %}
7609
7610 // Immediate And
7611 instruct andI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
7612 match(Set dst (AndI dst src));
7613 effect(KILL cr);
7614 ins_cost(DEFAULT_COST_HIGH);
7615 size(6);
7616 format %{ "NILF $dst,$src" %}
7617 opcode(NILF_ZOPC);
7618 ins_encode(z_rilform_unsigned(dst, src));
7619 ins_pipe(pipe_class_dummy);
7620 %}
7621
7622 instruct andI_reg_uimmI_LH1(iRegI dst, uimmI_LH1 src, flagsReg cr) %{
7623 match(Set dst (AndI dst src));
7624 effect(KILL cr);
7625 ins_cost(DEFAULT_COST);
7626 size(4);
7627 format %{ "NILH $dst,$src" %}
7628 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7629 ins_pipe(pipe_class_dummy);
7630 %}
7631
7632 instruct andI_reg_uimmI_LL1(iRegI dst, uimmI_LL1 src, flagsReg cr) %{
7633 match(Set dst (AndI dst src));
7634 effect(KILL cr);
7635 ins_cost(DEFAULT_COST);
7636 size(4);
7637 format %{ "NILL $dst,$src" %}
7638 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7639 ins_pipe(pipe_class_dummy);
7640 %}
7641
7642 // Register And Long
7643 instruct andL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7644 match(Set dst (AndL dst src));
7645 effect(KILL cr);
7646 ins_cost(DEFAULT_COST);
7647 size(4);
7648 format %{ "NGR $dst,$src\t # long" %}
7649 opcode(NGR_ZOPC);
7650 ins_encode(z_rreform(dst, src));
7651 ins_pipe(pipe_class_dummy);
7652 %}
7653
7654 instruct andL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7655 match(Set dst (AndL dst (LoadL src)));
7656 effect(KILL cr);
7657 ins_cost(MEMORY_REF_COST);
7658 size(Z_DISP3_SIZE);
7659 format %{ "NG $dst, $src\t # long" %}
7660 opcode(NG_ZOPC, NG_ZOPC);
7661 ins_encode(z_form_rt_mem_opt(dst, src));
7662 ins_pipe(pipe_class_dummy);
7663 %}
7664
7665 instruct andL_reg_uimmL_LL1(iRegL dst, uimmL_LL1 src, flagsReg cr) %{
7666 match(Set dst (AndL dst src));
7667 effect(KILL cr);
7668 ins_cost(DEFAULT_COST);
7669 size(4);
7670 format %{ "NILL $dst,$src\t # long" %}
7671 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7672 ins_pipe(pipe_class_dummy);
7673 %}
7674
7675 instruct andL_reg_uimmL_LH1(iRegL dst, uimmL_LH1 src, flagsReg cr) %{
7676 match(Set dst (AndL dst src));
7677 effect(KILL cr);
7678 ins_cost(DEFAULT_COST);
7679 size(4);
7680 format %{ "NILH $dst,$src\t # long" %}
7681 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7682 ins_pipe(pipe_class_dummy);
7683 %}
7684
7685 instruct andL_reg_uimmL_HL1(iRegL dst, uimmL_HL1 src, flagsReg cr) %{
7686 match(Set dst (AndL dst src));
7687 effect(KILL cr);
7688 ins_cost(DEFAULT_COST);
7689 size(4);
7690 format %{ "NIHL $dst,$src\t # long" %}
7691 ins_encode %{ __ z_nihl($dst$$Register, ($src$$constant >> 32) & 0xFFFF); %}
7692 ins_pipe(pipe_class_dummy);
7693 %}
7694
7695 instruct andL_reg_uimmL_HH1(iRegL dst, uimmL_HH1 src, flagsReg cr) %{
7696 match(Set dst (AndL dst src));
7697 effect(KILL cr);
7698 ins_cost(DEFAULT_COST);
7699 size(4);
7700 format %{ "NIHH $dst,$src\t # long" %}
7701 ins_encode %{ __ z_nihh($dst$$Register, ($src$$constant >> 48) & 0xFFFF); %}
7702 ins_pipe(pipe_class_dummy);
7703 %}
7704
7705 // OR
7706
7707 // Or Instructions
7708 // Register Or
7709 instruct orI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7710 match(Set dst (OrI dst src));
7711 effect(KILL cr);
7712 size(2);
7713 format %{ "OR $dst,$src" %}
7714 opcode(OR_ZOPC);
7715 ins_encode(z_rrform(dst, src));
7716 ins_pipe(pipe_class_dummy);
7717 %}
7718
7719 instruct orI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7720 match(Set dst (OrI dst (LoadI src)));
7721 effect(KILL cr);
7722 ins_cost(MEMORY_REF_COST);
7723 // TODO: s390 port size(VARIABLE_SIZE);
7724 format %{ "O(Y) $dst, $src\t # int" %}
7725 opcode(OY_ZOPC, O_ZOPC);
7726 ins_encode(z_form_rt_mem_opt(dst, src));
7727 ins_pipe(pipe_class_dummy);
7728 %}
7729
7730 // Immediate Or
7731 instruct orI_reg_uimm16(iRegI dst, uimmI16 con, flagsReg cr) %{
7732 match(Set dst (OrI dst con));
7733 effect(KILL cr);
7734 size(4);
7735 format %{ "OILL $dst,$con" %}
7736 opcode(OILL_ZOPC);
7737 ins_encode(z_riform_unsigned(dst,con));
7738 ins_pipe(pipe_class_dummy);
7739 %}
7740
7741 instruct orI_reg_uimm32(iRegI dst, uimmI con, flagsReg cr) %{
7742 match(Set dst (OrI dst con));
7743 effect(KILL cr);
7744 ins_cost(DEFAULT_COST_HIGH);
7745 size(6);
7746 format %{ "OILF $dst,$con" %}
7747 opcode(OILF_ZOPC);
7748 ins_encode(z_rilform_unsigned(dst,con));
7749 ins_pipe(pipe_class_dummy);
7750 %}
7751
7752 // Register Or Long
7753 instruct orL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7754 match(Set dst (OrL dst src));
7755 effect(KILL cr);
7756 ins_cost(DEFAULT_COST);
7757 size(4);
7758 format %{ "OGR $dst,$src\t # long" %}
7759 opcode(OGR_ZOPC);
7760 ins_encode(z_rreform(dst, src));
7761 ins_pipe(pipe_class_dummy);
7762 %}
7763
7764 instruct orL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7765 match(Set dst (OrL dst (LoadL src)));
7766 effect(KILL cr);
7767 ins_cost(MEMORY_REF_COST);
7768 size(Z_DISP3_SIZE);
7769 format %{ "OG $dst, $src\t # long" %}
7770 opcode(OG_ZOPC, OG_ZOPC);
7771 ins_encode(z_form_rt_mem_opt(dst, src));
7772 ins_pipe(pipe_class_dummy);
7773 %}
7774
7775 // Immediate Or long
7776 instruct orL_reg_uimm16(iRegL dst, uimmL16 con, flagsReg cr) %{
7777 match(Set dst (OrL dst con));
7778 effect(KILL cr);
7779 ins_cost(DEFAULT_COST);
7780 size(4);
7781 format %{ "OILL $dst,$con\t # long" %}
7782 opcode(OILL_ZOPC);
7783 ins_encode(z_riform_unsigned(dst,con));
7784 ins_pipe(pipe_class_dummy);
7785 %}
7786
7787 instruct orL_reg_uimm32(iRegI dst, uimmL32 con, flagsReg cr) %{
7788 match(Set dst (OrI dst con));
7789 effect(KILL cr);
7790 ins_cost(DEFAULT_COST_HIGH);
7791 // TODO: s390 port size(FIXED_SIZE);
7792 format %{ "OILF $dst,$con\t # long" %}
7793 opcode(OILF_ZOPC);
7794 ins_encode(z_rilform_unsigned(dst,con));
7795 ins_pipe(pipe_class_dummy);
7796 %}
7797
7798 // XOR
7799
7800 // Register Xor
7801 instruct xorI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7802 match(Set dst (XorI dst src));
7803 effect(KILL cr);
7804 size(2);
7805 format %{ "XR $dst,$src" %}
7806 opcode(XR_ZOPC);
7807 ins_encode(z_rrform(dst, src));
7808 ins_pipe(pipe_class_dummy);
7809 %}
7810
7811 instruct xorI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7812 match(Set dst (XorI dst (LoadI src)));
7813 effect(KILL cr);
7814 ins_cost(MEMORY_REF_COST);
7815 // TODO: s390 port size(VARIABLE_SIZE);
7816 format %{ "X(Y) $dst, $src\t # int" %}
7817 opcode(XY_ZOPC, X_ZOPC);
7818 ins_encode(z_form_rt_mem_opt(dst, src));
7819 ins_pipe(pipe_class_dummy);
7820 %}
7821
7822 // Immediate Xor
7823 instruct xorI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
7824 match(Set dst (XorI dst src));
7825 effect(KILL cr);
7826 ins_cost(DEFAULT_COST_HIGH);
7827 size(6);
7828 format %{ "XILF $dst,$src" %}
7829 opcode(XILF_ZOPC);
7830 ins_encode(z_rilform_unsigned(dst, src));
7831 ins_pipe(pipe_class_dummy);
7832 %}
7833
7834 // Register Xor Long
7835 instruct xorL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7836 match(Set dst (XorL dst src));
7837 effect(KILL cr);
7838 ins_cost(DEFAULT_COST);
7839 size(4);
7840 format %{ "XGR $dst,$src\t # long" %}
7841 opcode(XGR_ZOPC);
7842 ins_encode(z_rreform(dst, src));
7843 ins_pipe(pipe_class_dummy);
7844 %}
7845
7846 instruct xorL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7847 match(Set dst (XorL dst (LoadL src)));
7848 effect(KILL cr);
7849 ins_cost(MEMORY_REF_COST);
7850 size(Z_DISP3_SIZE);
7851 format %{ "XG $dst, $src\t # long" %}
7852 opcode(XG_ZOPC, XG_ZOPC);
7853 ins_encode(z_form_rt_mem_opt(dst, src));
7854 ins_pipe(pipe_class_dummy);
7855 %}
7856
7857 // Immediate Xor Long
7858 instruct xorL_reg_uimm32(iRegL dst, uimmL32 con, flagsReg cr) %{
7859 match(Set dst (XorL dst con));
7860 effect(KILL cr);
7861 ins_cost(DEFAULT_COST_HIGH);
7862 size(6);
7863 format %{ "XILF $dst,$con\t # long" %}
7864 opcode(XILF_ZOPC);
7865 ins_encode(z_rilform_unsigned(dst,con));
7866 ins_pipe(pipe_class_dummy);
7867 %}
7868
7869 //----------Convert to Boolean-------------------------------------------------
7870
7871 // Convert integer to boolean.
7872 instruct convI2B(iRegI dst, iRegI src, flagsReg cr) %{
7873 match(Set dst (Conv2B src));
7874 effect(KILL cr);
7875 ins_cost(3 * DEFAULT_COST);
7876 size(6);
7877 format %{ "convI2B $dst,$src" %}
7878 ins_encode %{
7879 __ z_lnr($dst$$Register, $src$$Register); // Rdst := -|Rsrc|, i.e. Rdst == 0 <=> Rsrc == 0
7880 __ z_srl($dst$$Register, 31); // Rdst := sign(Rdest)
7881 %}
7882 ins_pipe(pipe_class_dummy);
7883 %}
7884
7885 instruct convP2B(iRegI dst, iRegP_N2P src, flagsReg cr) %{
7886 match(Set dst (Conv2B src));
7887 effect(KILL cr);
7888 ins_cost(3 * DEFAULT_COST);
7889 size(10);
7890 format %{ "convP2B $dst,$src" %}
7891 ins_encode %{
7892 __ z_lngr($dst$$Register, $src$$Register); // Rdst := -|Rsrc| i.e. Rdst == 0 <=> Rsrc == 0
7893 __ z_srlg($dst$$Register, $dst$$Register, 63); // Rdst := sign(Rdest)
7894 %}
7895 ins_pipe(pipe_class_dummy);
7896 %}
7897
7898 instruct cmpLTMask_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7899 match(Set dst (CmpLTMask dst src));
7900 effect(KILL cr);
7901 ins_cost(2 * DEFAULT_COST);
7902 size(18);
7903 format %{ "Set $dst CmpLTMask $dst,$src" %}
7904 ins_encode %{
7905 // Avoid signed 32 bit overflow: Do sign extend and sub 64 bit.
7906 __ z_lgfr(Z_R0_scratch, $src$$Register);
7907 __ z_lgfr($dst$$Register, $dst$$Register);
7908 __ z_sgr($dst$$Register, Z_R0_scratch);
7909 __ z_srag($dst$$Register, $dst$$Register, 63);
7910 %}
7911 ins_pipe(pipe_class_dummy);
7912 %}
7913
7914 instruct cmpLTMask_reg_zero(iRegI dst, immI_0 zero, flagsReg cr) %{
7915 match(Set dst (CmpLTMask dst zero));
7916 effect(KILL cr);
7917 ins_cost(DEFAULT_COST);
7918 size(4);
7919 format %{ "Set $dst CmpLTMask $dst,$zero" %}
7920 ins_encode %{ __ z_sra($dst$$Register, 31); %}
7921 ins_pipe(pipe_class_dummy);
7922 %}
7923
7924
7925 //----------Arithmetic Conversion Instructions---------------------------------
7926 // The conversions operations are all Alpha sorted. Please keep it that way!
7927
7928 instruct convD2F_reg(regF dst, regD src) %{
7929 match(Set dst (ConvD2F src));
7930 // CC remains unchanged.
7931 size(4);
7932 format %{ "LEDBR $dst,$src" %}
7933 opcode(LEDBR_ZOPC);
7934 ins_encode(z_rreform(dst, src));
7935 ins_pipe(pipe_class_dummy);
7936 %}
7937
7938 instruct convF2I_reg(iRegI dst, regF src, flagsReg cr) %{
7939 match(Set dst (ConvF2I src));
7940 effect(KILL cr);
7941 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
7942 size(16);
7943 format %{ "convF2I $dst,$src" %}
7944 ins_encode %{
7945 Label done;
7946 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0.
7947 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round.
7948 __ z_brno(done); // Result is zero if unordered argument.
7949 __ z_cfebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
7950 __ bind(done);
7951 %}
7952 ins_pipe(pipe_class_dummy);
7953 %}
7954
7955 instruct convD2I_reg(iRegI dst, regD src, flagsReg cr) %{
7956 match(Set dst (ConvD2I src));
7957 effect(KILL cr);
7958 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
7959 size(16);
7960 format %{ "convD2I $dst,$src" %}
7961 ins_encode %{
7962 Label done;
7963 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0.
7964 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round.
7965 __ z_brno(done); // Result is zero if unordered argument.
7966 __ z_cfdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
7967 __ bind(done);
7968 %}
7969 ins_pipe(pipe_class_dummy);
7970 %}
7971
7972 instruct convF2L_reg(iRegL dst, regF src, flagsReg cr) %{
7973 match(Set dst (ConvF2L src));
7974 effect(KILL cr);
7975 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
7976 size(16);
7977 format %{ "convF2L $dst,$src" %}
7978 ins_encode %{
7979 Label done;
7980 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0.
7981 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round.
7982 __ z_brno(done); // Result is zero if unordered argument.
7983 __ z_cgebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
7984 __ bind(done);
7985 %}
7986 ins_pipe(pipe_class_dummy);
7987 %}
7988
7989 instruct convD2L_reg(iRegL dst, regD src, flagsReg cr) %{
7990 match(Set dst (ConvD2L src));
7991 effect(KILL cr);
7992 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
7993 size(16);
7994 format %{ "convD2L $dst,$src" %}
7995 ins_encode %{
7996 Label done;
7997 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0.
7998 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round.
7999 __ z_brno(done); // Result is zero if unordered argument.
8000 __ z_cgdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8001 __ bind(done);
8002 %}
8003 ins_pipe(pipe_class_dummy);
8004 %}
8005
8006 instruct convF2D_reg(regD dst, regF src) %{
8007 match(Set dst (ConvF2D src));
8008 // CC remains unchanged.
8009 size(4);
8010 format %{ "LDEBR $dst,$src" %}
8011 opcode(LDEBR_ZOPC);
8012 ins_encode(z_rreform(dst, src));
8013 ins_pipe(pipe_class_dummy);
8014 %}
8015
8016 instruct convF2D_mem(regD dst, memoryRX src) %{
8017 match(Set dst (ConvF2D src));
8018 // CC remains unchanged.
8019 size(6);
8020 format %{ "LDEB $dst,$src" %}
8021 opcode(LDEB_ZOPC);
8022 ins_encode(z_form_rt_memFP(dst, src));
8023 ins_pipe(pipe_class_dummy);
8024 %}
8025
8026 instruct convI2D_reg(regD dst, iRegI src) %{
8027 match(Set dst (ConvI2D src));
8028 // CC remains unchanged.
8029 ins_cost(DEFAULT_COST);
8030 size(4);
8031 format %{ "CDFBR $dst,$src" %}
8032 opcode(CDFBR_ZOPC);
8033 ins_encode(z_rreform(dst, src));
8034 ins_pipe(pipe_class_dummy);
8035 %}
8036
8037 // Optimization that saves up to two memory operations for each conversion.
8038 instruct convI2F_ireg(regF dst, iRegI src) %{
8039 match(Set dst (ConvI2F src));
8040 // CC remains unchanged.
8041 ins_cost(DEFAULT_COST);
8042 size(4);
8043 format %{ "CEFBR $dst,$src\t # convert int to float" %}
8044 opcode(CEFBR_ZOPC);
8045 ins_encode(z_rreform(dst, src));
8046 ins_pipe(pipe_class_dummy);
8047 %}
8048
8049 instruct convI2L_reg(iRegL dst, iRegI src) %{
8050 match(Set dst (ConvI2L src));
8051 size(4);
8052 format %{ "LGFR $dst,$src\t # int->long" %}
8053 opcode(LGFR_ZOPC);
8054 ins_encode(z_rreform(dst, src));
8055 ins_pipe(pipe_class_dummy);
8056 %}
8057
8058 // Zero-extend convert int to long.
8059 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask) %{
8060 match(Set dst (AndL (ConvI2L src) mask));
8061 size(4);
8062 format %{ "LLGFR $dst, $src \t # zero-extend int to long" %}
8063 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8064 ins_pipe(pipe_class_dummy);
8065 %}
8066
8067 // Zero-extend convert int to long.
8068 instruct convI2L_mem_zex(iRegL dst, memory src, immL_32bits mask) %{
8069 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
8070 // Uses load_const_optmized, so size can vary.
8071 // TODO: s390 port size(VARIABLE_SIZE);
8072 format %{ "LLGF $dst, $src \t # zero-extend int to long" %}
8073 opcode(LLGF_ZOPC, LLGF_ZOPC);
8074 ins_encode(z_form_rt_mem_opt(dst, src));
8075 ins_pipe(pipe_class_dummy);
8076 %}
8077
8078 // Zero-extend long
8079 instruct zeroExtend_long(iRegL dst, iRegL src, immL_32bits mask) %{
8080 match(Set dst (AndL src mask));
8081 size(4);
8082 format %{ "LLGFR $dst, $src \t # zero-extend long to long" %}
8083 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8084 ins_pipe(pipe_class_dummy);
8085 %}
8086
8087 instruct rShiftI16_lShiftI16_reg(iRegI dst, iRegI src, immI_16 amount) %{
8088 match(Set dst (RShiftI (LShiftI src amount) amount));
8089 size(4);
8090 format %{ "LHR $dst,$src\t short->int" %}
8091 opcode(LHR_ZOPC);
8092 ins_encode(z_rreform(dst, src));
8093 ins_pipe(pipe_class_dummy);
8094 %}
8095
8096 instruct rShiftI24_lShiftI24_reg(iRegI dst, iRegI src, immI_24 amount) %{
8097 match(Set dst (RShiftI (LShiftI src amount) amount));
8098 size(4);
8099 format %{ "LBR $dst,$src\t byte->int" %}
8100 opcode(LBR_ZOPC);
8101 ins_encode(z_rreform(dst, src));
8102 ins_pipe(pipe_class_dummy);
8103 %}
8104
8105 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8106 match(Set dst (MoveF2I src));
8107 ins_cost(MEMORY_REF_COST);
8108 size(4);
8109 format %{ "L $dst,$src\t # MoveF2I" %}
8110 opcode(L_ZOPC);
8111 ins_encode(z_form_rt_mem(dst, src));
8112 ins_pipe(pipe_class_dummy);
8113 %}
8114
8115 // javax.imageio.stream.ImageInputStreamImpl.toFloats([B[FII)
8116 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8117 match(Set dst (MoveI2F src));
8118 ins_cost(MEMORY_REF_COST);
8119 // TODO: s390 port size(FIXED_SIZE);
8120 format %{ "LE $dst,$src\t # MoveI2F" %}
8121 opcode(LE_ZOPC);
8122 ins_encode(z_form_rt_mem(dst, src));
8123 ins_pipe(pipe_class_dummy);
8124 %}
8125
8126 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8127 match(Set dst (MoveD2L src));
8128 ins_cost(MEMORY_REF_COST);
8129 size(6);
8130 format %{ "LG $src,$dst\t # MoveD2L" %}
8131 opcode(LG_ZOPC);
8132 ins_encode(z_form_rt_mem(dst, src));
8133 ins_pipe(pipe_class_dummy);
8134 %}
8135
8136 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8137 match(Set dst (MoveL2D src));
8138 ins_cost(MEMORY_REF_COST);
8139 size(4);
8140 format %{ "LD $dst,$src\t # MoveL2D" %}
8141 opcode(LD_ZOPC);
8142 ins_encode(z_form_rt_mem(dst, src));
8143 ins_pipe(pipe_class_dummy);
8144 %}
8145
8146 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8147 match(Set dst (MoveI2F src));
8148 ins_cost(MEMORY_REF_COST);
8149 size(4);
8150 format %{ "ST $src,$dst\t # MoveI2F" %}
8151 opcode(ST_ZOPC);
8152 ins_encode(z_form_rt_mem(src, dst));
8153 ins_pipe(pipe_class_dummy);
8154 %}
8155
8156 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8157 match(Set dst (MoveD2L src));
8158 effect(DEF dst, USE src);
8159 ins_cost(MEMORY_REF_COST);
8160 size(4);
8161 format %{ "STD $src,$dst\t # MoveD2L" %}
8162 opcode(STD_ZOPC);
8163 ins_encode(z_form_rt_mem(src,dst));
8164 ins_pipe(pipe_class_dummy);
8165 %}
8166
8167 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8168 match(Set dst (MoveL2D src));
8169 ins_cost(MEMORY_REF_COST);
8170 size(6);
8171 format %{ "STG $src,$dst\t # MoveL2D" %}
8172 opcode(STG_ZOPC);
8173 ins_encode(z_form_rt_mem(src,dst));
8174 ins_pipe(pipe_class_dummy);
8175 %}
8176
8177 instruct convL2F_reg(regF dst, iRegL src) %{
8178 match(Set dst (ConvL2F src));
8179 // CC remains unchanged.
8180 ins_cost(DEFAULT_COST);
8181 size(4);
8182 format %{ "CEGBR $dst,$src" %}
8183 opcode(CEGBR_ZOPC);
8184 ins_encode(z_rreform(dst, src));
8185 ins_pipe(pipe_class_dummy);
8186 %}
8187
8188 instruct convL2D_reg(regD dst, iRegL src) %{
8189 match(Set dst (ConvL2D src));
8190 // CC remains unchanged.
8191 ins_cost(DEFAULT_COST);
8192 size(4);
8193 format %{ "CDGBR $dst,$src" %}
8194 opcode(CDGBR_ZOPC);
8195 ins_encode(z_rreform(dst, src));
8196 ins_pipe(pipe_class_dummy);
8197 %}
8198
8199 instruct convL2I_reg(iRegI dst, iRegL src) %{
8200 match(Set dst (ConvL2I src));
8201 // TODO: s390 port size(VARIABLE_SIZE);
8202 format %{ "LR $dst,$src\t # long->int (if needed)" %}
8203 ins_encode %{ __ lr_if_needed($dst$$Register, $src$$Register); %}
8204 ins_pipe(pipe_class_dummy);
8205 %}
8206
8207 // Register Shift Right Immediate
8208 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt, flagsReg cr) %{
8209 match(Set dst (ConvL2I (RShiftL src cnt)));
8210 effect(KILL cr);
8211 size(6);
8212 format %{ "SRAG $dst,$src,$cnt" %}
8213 opcode(SRAG_ZOPC);
8214 ins_encode(z_rsyform_const(dst, src, cnt));
8215 ins_pipe(pipe_class_dummy);
8216 %}
8217
8218 //----------TRAP based zero checks and range checks----------------------------
8219
8220 // SIGTRAP based implicit range checks in compiled code.
8221 // A range check in the ideal world has one of the following shapes:
8222 // - (If le (CmpU length index)), (IfTrue throw exception)
8223 // - (If lt (CmpU index length)), (IfFalse throw exception)
8224 //
8225 // Match range check 'If le (CmpU length index)'
8226 instruct rangeCheck_iReg_uimmI16(cmpOpT cmp, iRegI length, uimmI16 index, label labl) %{
8227 match(If cmp (CmpU length index));
8228 effect(USE labl);
8229 predicate(TrapBasedRangeChecks &&
8230 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
8231 PROB_UNLIKELY(_leaf->as_If ()->_prob) >= PROB_ALWAYS &&
8232 Matcher::branches_to_uncommon_trap(_leaf));
8233 ins_cost(1);
8234 // TODO: s390 port size(FIXED_SIZE);
8235
8236 ins_is_TrapBasedCheckNode(true);
8237
8238 format %{ "RangeCheck len=$length cmp=$cmp idx=$index => trap $labl" %}
8239 ins_encode %{ __ z_clfit($length$$Register, $index$$constant, $cmp$$cmpcode); %}
8240 ins_pipe(pipe_class_trap);
8241 %}
8242
8243 // Match range check 'If lt (CmpU index length)'
8244 instruct rangeCheck_iReg_iReg(cmpOpT cmp, iRegI index, iRegI length, label labl, flagsReg cr) %{
8245 match(If cmp (CmpU index length));
8246 effect(USE labl, KILL cr);
8247 predicate(TrapBasedRangeChecks &&
8248 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8249 _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8250 Matcher::branches_to_uncommon_trap(_leaf));
8251 ins_cost(1);
8252 // TODO: s390 port size(FIXED_SIZE);
8253
8254 ins_is_TrapBasedCheckNode(true);
8255
8256 format %{ "RangeCheck idx=$index cmp=$cmp len=$length => trap $labl" %}
8257 ins_encode %{ __ z_clrt($index$$Register, $length$$Register, $cmp$$cmpcode); %}
8258 ins_pipe(pipe_class_trap);
8259 %}
8260
8261 // Match range check 'If lt (CmpU index length)'
8262 instruct rangeCheck_uimmI16_iReg(cmpOpT cmp, iRegI index, uimmI16 length, label labl) %{
8263 match(If cmp (CmpU index length));
8264 effect(USE labl);
8265 predicate(TrapBasedRangeChecks &&
8266 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8267 _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8268 Matcher::branches_to_uncommon_trap(_leaf));
8269 ins_cost(1);
8270 // TODO: s390 port size(FIXED_SIZE);
8271
8272 ins_is_TrapBasedCheckNode(true);
8273
8274 format %{ "RangeCheck idx=$index cmp=$cmp len= $length => trap $labl" %}
8275 ins_encode %{ __ z_clfit($index$$Register, $length$$constant, $cmp$$cmpcode); %}
8276 ins_pipe(pipe_class_trap);
8277 %}
8278
8279 // Implicit zero checks (more implicit null checks).
8280 instruct zeroCheckP_iReg_imm0(cmpOpT cmp, iRegP_N2P value, immP0 zero, label labl) %{
8281 match(If cmp (CmpP value zero));
8282 effect(USE labl);
8283 predicate(TrapBasedNullChecks &&
8284 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8285 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8286 Matcher::branches_to_uncommon_trap(_leaf));
8287 size(6);
8288
8289 ins_is_TrapBasedCheckNode(true);
8290
8291 format %{ "ZeroCheckP value=$value cmp=$cmp zero=$zero => trap $labl" %}
8292 ins_encode %{ __ z_cgit($value$$Register, 0, $cmp$$cmpcode); %}
8293 ins_pipe(pipe_class_trap);
8294 %}
8295
8296 // Implicit zero checks (more implicit null checks).
8297 instruct zeroCheckN_iReg_imm0(cmpOpT cmp, iRegN_P2N value, immN0 zero, label labl) %{
8298 match(If cmp (CmpN value zero));
8299 effect(USE labl);
8300 predicate(TrapBasedNullChecks &&
8301 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8302 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8303 Matcher::branches_to_uncommon_trap(_leaf));
8304 size(6);
8305
8306 ins_is_TrapBasedCheckNode(true);
8307
8308 format %{ "ZeroCheckN value=$value cmp=$cmp zero=$zero => trap $labl" %}
8309 ins_encode %{ __ z_cit($value$$Register, 0, $cmp$$cmpcode); %}
8310 ins_pipe(pipe_class_trap);
8311 %}
8312
8313 //----------Compare instructions-----------------------------------------------
8314
8315 // INT signed
8316
8317 // Compare Integers
8318 instruct compI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8319 match(Set cr (CmpI op1 op2));
8320 size(2);
8321 format %{ "CR $op1,$op2" %}
8322 opcode(CR_ZOPC);
8323 ins_encode(z_rrform(op1, op2));
8324 ins_pipe(pipe_class_dummy);
8325 %}
8326
8327 instruct compI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
8328 match(Set cr (CmpI op1 op2));
8329 size(6);
8330 format %{ "CFI $op1,$op2" %}
8331 opcode(CFI_ZOPC);
8332 ins_encode(z_rilform_signed(op1, op2));
8333 ins_pipe(pipe_class_dummy);
8334 %}
8335
8336 instruct compI_reg_imm16(flagsReg cr, iRegI op1, immI16 op2) %{
8337 match(Set cr (CmpI op1 op2));
8338 size(4);
8339 format %{ "CHI $op1,$op2" %}
8340 opcode(CHI_ZOPC);
8341 ins_encode(z_riform_signed(op1, op2));
8342 ins_pipe(pipe_class_dummy);
8343 %}
8344
8345 instruct compI_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{
8346 match(Set cr (CmpI op1 zero));
8347 ins_cost(DEFAULT_COST_LOW);
8348 size(2);
8349 format %{ "LTR $op1,$op1" %}
8350 opcode(LTR_ZOPC);
8351 ins_encode(z_rrform(op1, op1));
8352 ins_pipe(pipe_class_dummy);
8353 %}
8354
8355 instruct compI_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8356 match(Set cr (CmpI op1 (LoadI op2)));
8357 ins_cost(MEMORY_REF_COST);
8358 // TODO: s390 port size(VARIABLE_SIZE);
8359 format %{ "C(Y) $op1, $op2\t # int" %}
8360 opcode(CY_ZOPC, C_ZOPC);
8361 ins_encode(z_form_rt_mem_opt(op1, op2));
8362 ins_pipe(pipe_class_dummy);
8363 %}
8364
8365 // INT unsigned
8366
8367 instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8368 match(Set cr (CmpU op1 op2));
8369 size(2);
8370 format %{ "CLR $op1,$op2\t # unsigned" %}
8371 opcode(CLR_ZOPC);
8372 ins_encode(z_rrform(op1, op2));
8373 ins_pipe(pipe_class_dummy);
8374 %}
8375
8376 instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{
8377 match(Set cr (CmpU op1 op2));
8378 size(6);
8379 format %{ "CLFI $op1,$op2\t # unsigned" %}
8380 opcode(CLFI_ZOPC);
8381 ins_encode(z_rilform_unsigned(op1, op2));
8382 ins_pipe(pipe_class_dummy);
8383 %}
8384
8385 instruct compU_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{
8386 match(Set cr (CmpU op1 zero));
8387 ins_cost(DEFAULT_COST_LOW);
8388 size(2);
8389 format %{ "LTR $op1,$op1\t # unsigned" %}
8390 opcode(LTR_ZOPC);
8391 ins_encode(z_rrform(op1, op1));
8392 ins_pipe(pipe_class_dummy);
8393 %}
8394
8395 instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8396 match(Set cr (CmpU op1 (LoadI op2)));
8397 ins_cost(MEMORY_REF_COST);
8398 // TODO: s390 port size(VARIABLE_SIZE);
8399 format %{ "CL(Y) $op1, $op2\t # unsigned" %}
8400 opcode(CLY_ZOPC, CL_ZOPC);
8401 ins_encode(z_form_rt_mem_opt(op1, op2));
8402 ins_pipe(pipe_class_dummy);
8403 %}
8404
8405 // LONG signed
8406
8407 instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8408 match(Set cr (CmpL op1 op2));
8409 size(4);
8410 format %{ "CGR $op1,$op2\t # long" %}
8411 opcode(CGR_ZOPC);
8412 ins_encode(z_rreform(op1, op2));
8413 ins_pipe(pipe_class_dummy);
8414 %}
8415
8416 instruct compL_reg_regI(flagsReg cr, iRegL op1, iRegI op2) %{
8417 match(Set cr (CmpL op1 (ConvI2L op2)));
8418 size(4);
8419 format %{ "CGFR $op1,$op2\t # long/int" %}
8420 opcode(CGFR_ZOPC);
8421 ins_encode(z_rreform(op1, op2));
8422 ins_pipe(pipe_class_dummy);
8423 %}
8424
8425 instruct compL_reg_imm32(flagsReg cr, iRegL op1, immL32 con) %{
8426 match(Set cr (CmpL op1 con));
8427 size(6);
8428 format %{ "CGFI $op1,$con" %}
8429 opcode(CGFI_ZOPC);
8430 ins_encode(z_rilform_signed(op1, con));
8431 ins_pipe(pipe_class_dummy);
8432 %}
8433
8434 instruct compL_reg_imm16(flagsReg cr, iRegL op1, immL16 con) %{
8435 match(Set cr (CmpL op1 con));
8436 size(4);
8437 format %{ "CGHI $op1,$con" %}
8438 opcode(CGHI_ZOPC);
8439 ins_encode(z_riform_signed(op1, con));
8440 ins_pipe(pipe_class_dummy);
8441 %}
8442
8443 instruct compL_reg_imm0(flagsReg cr, iRegL op1, immL_0 con) %{
8444 match(Set cr (CmpL op1 con));
8445 ins_cost(DEFAULT_COST_LOW);
8446 size(4);
8447 format %{ "LTGR $op1,$op1" %}
8448 opcode(LTGR_ZOPC);
8449 ins_encode(z_rreform(op1, op1));
8450 ins_pipe(pipe_class_dummy);
8451 %}
8452
8453 instruct compL_conv_reg_imm0(flagsReg cr, iRegI op1, immL_0 con) %{
8454 match(Set cr (CmpL (ConvI2L op1) con));
8455 ins_cost(DEFAULT_COST_LOW);
8456 size(4);
8457 format %{ "LTGFR $op1,$op1" %}
8458 opcode(LTGFR_ZOPC);
8459 ins_encode(z_rreform(op1, op1));
8460 ins_pipe(pipe_class_dummy);
8461 %}
8462
8463 instruct compL_reg_mem(iRegL dst, memory src, flagsReg cr)%{
8464 match(Set cr (CmpL dst (LoadL src)));
8465 ins_cost(MEMORY_REF_COST);
8466 size(Z_DISP3_SIZE);
8467 format %{ "CG $dst, $src\t # long" %}
8468 opcode(CG_ZOPC, CG_ZOPC);
8469 ins_encode(z_form_rt_mem_opt(dst, src));
8470 ins_pipe(pipe_class_dummy);
8471 %}
8472
8473 instruct compL_reg_memI(iRegL dst, memory src, flagsReg cr)%{
8474 match(Set cr (CmpL dst (ConvI2L (LoadI src))));
8475 ins_cost(MEMORY_REF_COST);
8476 size(Z_DISP3_SIZE);
8477 format %{ "CGF $dst, $src\t # long/int" %}
8478 opcode(CGF_ZOPC, CGF_ZOPC);
8479 ins_encode(z_form_rt_mem_opt(dst, src));
8480 ins_pipe(pipe_class_dummy);
8481 %}
8482
8483 // LONG unsigned
8484
8485 // PTR unsigned
8486
8487 instruct compP_reg_reg(flagsReg cr, iRegP_N2P op1, iRegP_N2P op2) %{
8488 match(Set cr (CmpP op1 op2));
8489 size(4);
8490 format %{ "CLGR $op1,$op2\t # ptr" %}
8491 opcode(CLGR_ZOPC);
8492 ins_encode(z_rreform(op1, op2));
8493 ins_pipe(pipe_class_dummy);
8494 %}
8495
8496 instruct compP_reg_imm0(flagsReg cr, iRegP_N2P op1, immP0 op2) %{
8497 match(Set cr (CmpP op1 op2));
8498 ins_cost(DEFAULT_COST_LOW);
8499 size(4);
8500 format %{ "LTGR $op1, $op1\t # ptr" %}
8501 opcode(LTGR_ZOPC);
8502 ins_encode(z_rreform(op1, op1));
8503 ins_pipe(pipe_class_dummy);
8504 %}
8505
8506 // Don't use LTGFR which performs sign extend.
8507 instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{
8508 match(Set cr (CmpP (DecodeN op1) op2));
8509 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
8510 ins_cost(DEFAULT_COST_LOW);
8511 size(2);
8512 format %{ "LTR $op1, $op1\t # ptr" %}
8513 opcode(LTR_ZOPC);
8514 ins_encode(z_rrform(op1, op1));
8515 ins_pipe(pipe_class_dummy);
8516 %}
8517
8518 instruct compP_reg_mem(iRegP dst, memory src, flagsReg cr)%{
8519 match(Set cr (CmpP dst (LoadP src)));
8520 ins_cost(MEMORY_REF_COST);
8521 size(Z_DISP3_SIZE);
8522 format %{ "CLG $dst, $src\t # ptr" %}
8523 opcode(CLG_ZOPC, CLG_ZOPC);
8524 ins_encode(z_form_rt_mem_opt(dst, src));
8525 ins_pipe(pipe_class_dummy);
8526 %}
8527
8528 //----------Max and Min--------------------------------------------------------
8529
8530 // Max Register with Register
8531 instruct z196_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8532 match(Set dst (MinI src1 src2));
8533 effect(KILL cr);
8534 predicate(VM_Version::has_LoadStoreConditional());
8535 ins_cost(3 * DEFAULT_COST);
8536 // TODO: s390 port size(VARIABLE_SIZE);
8537 format %{ "MinI $dst $src1,$src2\t MinI (z196 only)" %}
8538 ins_encode %{
8539 Register Rdst = $dst$$Register;
8540 Register Rsrc1 = $src1$$Register;
8541 Register Rsrc2 = $src2$$Register;
8542
8543 if (Rsrc1 == Rsrc2) {
8544 if (Rdst != Rsrc1) {
8545 __ z_lgfr(Rdst, Rsrc1);
8546 }
8547 } else if (Rdst == Rsrc1) { // Rdst preset with src1.
8548 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotLow.
8549 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8550 } else if (Rdst == Rsrc2) { // Rdst preset with src2.
8551 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotLow.
8552 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotLow);
8553 } else {
8554 // Rdst is disjoint from operands, move in either case.
8555 __ z_cr(Rsrc1, Rsrc2);
8556 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8557 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8558 }
8559 %}
8560 ins_pipe(pipe_class_dummy);
8561 %}
8562
8563 // Min Register with Register.
8564 instruct z10_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8565 match(Set dst (MinI src1 src2));
8566 effect(KILL cr);
8567 predicate(VM_Version::has_CompareBranch());
8568 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8569 // TODO: s390 port size(VARIABLE_SIZE);
8570 format %{ "MinI $dst $src1,$src2\t MinI (z10 only)" %}
8571 ins_encode %{
8572 Register Rdst = $dst$$Register;
8573 Register Rsrc1 = $src1$$Register;
8574 Register Rsrc2 = $src2$$Register;
8575 Label done;
8576
8577 if (Rsrc1 == Rsrc2) {
8578 if (Rdst != Rsrc1) {
8579 __ z_lgfr(Rdst, Rsrc1);
8580 }
8581 } else if (Rdst == Rsrc1) {
8582 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8583 __ z_lgfr(Rdst, Rsrc2);
8584 } else if (Rdst == Rsrc2) {
8585 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondLow, done);
8586 __ z_lgfr(Rdst, Rsrc1);
8587 } else {
8588 __ z_lgfr(Rdst, Rsrc1);
8589 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8590 __ z_lgfr(Rdst, Rsrc2);
8591 }
8592 __ bind(done);
8593 %}
8594 ins_pipe(pipe_class_dummy);
8595 %}
8596
8597 instruct minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8598 match(Set dst (MinI src1 src2));
8599 effect(KILL cr);
8600 predicate(!VM_Version::has_CompareBranch());
8601 ins_cost(3 * DEFAULT_COST + BRANCH_COST);
8602 // TODO: s390 port size(VARIABLE_SIZE);
8603 format %{ "MinI $dst $src1,$src2\t MinI" %}
8604 ins_encode %{
8605 Register Rdst = $dst$$Register;
8606 Register Rsrc1 = $src1$$Register;
8607 Register Rsrc2 = $src2$$Register;
8608 Label done;
8609
8610 if (Rsrc1 == Rsrc2) {
8611 if (Rdst != Rsrc1) {
8612 __ z_lgfr(Rdst, Rsrc1);
8613 }
8614 } else if (Rdst == Rsrc1) {
8615 __ z_cr(Rsrc1, Rsrc2);
8616 __ z_brl(done);
8617 __ z_lgfr(Rdst, Rsrc2);
8618 } else if (Rdst == Rsrc2) {
8619 __ z_cr(Rsrc2, Rsrc1);
8620 __ z_brl(done);
8621 __ z_lgfr(Rdst, Rsrc1);
8622 } else {
8623 __ z_lgfr(Rdst, Rsrc1);
8624 __ z_cr(Rsrc1, Rsrc2);
8625 __ z_brl(done);
8626 __ z_lgfr(Rdst, Rsrc2);
8627 }
8628 __ bind(done);
8629 %}
8630 ins_pipe(pipe_class_dummy);
8631 %}
8632
8633 instruct z196_minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8634 match(Set dst (MinI src1 src2));
8635 effect(KILL cr);
8636 predicate(VM_Version::has_LoadStoreConditional());
8637 ins_cost(3 * DEFAULT_COST);
8638 // TODO: s390 port size(VARIABLE_SIZE);
8639 format %{ "MinI $dst $src1,$src2\t MinI const32 (z196 only)" %}
8640 ins_encode %{
8641 Register Rdst = $dst$$Register;
8642 Register Rsrc1 = $src1$$Register;
8643 int Isrc2 = $src2$$constant;
8644
8645 if (Rdst == Rsrc1) {
8646 __ load_const_optimized(Z_R0_scratch, Isrc2);
8647 __ z_cfi(Rsrc1, Isrc2);
8648 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8649 } else {
8650 __ load_const_optimized(Rdst, Isrc2);
8651 __ z_cfi(Rsrc1, Isrc2);
8652 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8653 }
8654 %}
8655 ins_pipe(pipe_class_dummy);
8656 %}
8657
8658 instruct minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8659 match(Set dst (MinI src1 src2));
8660 effect(KILL cr);
8661 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8662 // TODO: s390 port size(VARIABLE_SIZE);
8663 format %{ "MinI $dst $src1,$src2\t MinI const32" %}
8664 ins_encode %{
8665 Label done;
8666 if ($dst$$Register != $src1$$Register) {
8667 __ z_lgfr($dst$$Register, $src1$$Register);
8668 }
8669 __ z_cfi($src1$$Register, $src2$$constant);
8670 __ z_brl(done);
8671 __ z_lgfi($dst$$Register, $src2$$constant);
8672 __ bind(done);
8673 %}
8674 ins_pipe(pipe_class_dummy);
8675 %}
8676
8677 instruct z196_minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8678 match(Set dst (MinI src1 src2));
8679 effect(KILL cr);
8680 predicate(VM_Version::has_LoadStoreConditional());
8681 ins_cost(3 * DEFAULT_COST);
8682 // TODO: s390 port size(VARIABLE_SIZE);
8683 format %{ "MinI $dst $src1,$src2\t MinI const16 (z196 only)" %}
8684 ins_encode %{
8685 Register Rdst = $dst$$Register;
8686 Register Rsrc1 = $src1$$Register;
8687 int Isrc2 = $src2$$constant;
8688
8689 if (Rdst == Rsrc1) {
8690 __ load_const_optimized(Z_R0_scratch, Isrc2);
8691 __ z_chi(Rsrc1, Isrc2);
8692 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8693 } else {
8694 __ load_const_optimized(Rdst, Isrc2);
8695 __ z_chi(Rsrc1, Isrc2);
8696 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8697 }
8698 %}
8699 ins_pipe(pipe_class_dummy);
8700 %}
8701
8702 instruct minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8703 match(Set dst (MinI src1 src2));
8704 effect(KILL cr);
8705 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8706 // TODO: s390 port size(VARIABLE_SIZE);
8707 format %{ "MinI $dst $src1,$src2\t MinI const16" %}
8708 ins_encode %{
8709 Label done;
8710 if ($dst$$Register != $src1$$Register) {
8711 __ z_lgfr($dst$$Register, $src1$$Register);
8712 }
8713 __ z_chi($src1$$Register, $src2$$constant);
8714 __ z_brl(done);
8715 __ z_lghi($dst$$Register, $src2$$constant);
8716 __ bind(done);
8717 %}
8718 ins_pipe(pipe_class_dummy);
8719 %}
8720
8721 instruct z10_minI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
8722 match(Set dst (MinI src1 src2));
8723 effect(KILL cr);
8724 predicate(VM_Version::has_CompareBranch());
8725 ins_cost(DEFAULT_COST + BRANCH_COST);
8726 // TODO: s390 port size(VARIABLE_SIZE);
8727 format %{ "MinI $dst $src1,$src2\t MinI const8 (z10 only)" %}
8728 ins_encode %{
8729 Label done;
8730 if ($dst$$Register != $src1$$Register) {
8731 __ z_lgfr($dst$$Register, $src1$$Register);
8732 }
8733 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondLow, done);
8734 __ z_lghi($dst$$Register, $src2$$constant);
8735 __ bind(done);
8736 %}
8737 ins_pipe(pipe_class_dummy);
8738 %}
8739
8740 // Max Register with Register
8741 instruct z196_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8742 match(Set dst (MaxI src1 src2));
8743 effect(KILL cr);
8744 predicate(VM_Version::has_LoadStoreConditional());
8745 ins_cost(3 * DEFAULT_COST);
8746 // TODO: s390 port size(VARIABLE_SIZE);
8747 format %{ "MaxI $dst $src1,$src2\t MaxI (z196 only)" %}
8748 ins_encode %{
8749 Register Rdst = $dst$$Register;
8750 Register Rsrc1 = $src1$$Register;
8751 Register Rsrc2 = $src2$$Register;
8752
8753 if (Rsrc1 == Rsrc2) {
8754 if (Rdst != Rsrc1) {
8755 __ z_lgfr(Rdst, Rsrc1);
8756 }
8757 } else if (Rdst == Rsrc1) { // Rdst preset with src1.
8758 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotHigh.
8759 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
8760 } else if (Rdst == Rsrc2) { // Rdst preset with src2.
8761 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotHigh.
8762 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotHigh);
8763 } else { // Rdst is disjoint from operands, move in either case.
8764 __ z_cr(Rsrc1, Rsrc2);
8765 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
8766 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8767 }
8768 %}
8769 ins_pipe(pipe_class_dummy);
8770 %}
8771
8772 // Max Register with Register
8773 instruct z10_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8774 match(Set dst (MaxI src1 src2));
8775 effect(KILL cr);
8776 predicate(VM_Version::has_CompareBranch());
8777 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8778 // TODO: s390 port size(VARIABLE_SIZE);
8779 format %{ "MaxI $dst $src1,$src2\t MaxI (z10 only)" %}
8780 ins_encode %{
8781 Register Rdst = $dst$$Register;
8782 Register Rsrc1 = $src1$$Register;
8783 Register Rsrc2 = $src2$$Register;
8784 Label done;
8785
8786 if (Rsrc1 == Rsrc2) {
8787 if (Rdst != Rsrc1) {
8788 __ z_lgfr(Rdst, Rsrc1);
8789 }
8790 } else if (Rdst == Rsrc1) {
8791 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
8792 __ z_lgfr(Rdst, Rsrc2);
8793 } else if (Rdst == Rsrc2) {
8794 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondHigh, done);
8795 __ z_lgfr(Rdst, Rsrc1);
8796 } else {
8797 __ z_lgfr(Rdst, Rsrc1);
8798 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
8799 __ z_lgfr(Rdst, Rsrc2);
8800 }
8801 __ bind(done);
8802 %}
8803 ins_pipe(pipe_class_dummy);
8804 %}
8805
8806 instruct maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8807 match(Set dst (MaxI src1 src2));
8808 effect(KILL cr);
8809 predicate(!VM_Version::has_CompareBranch());
8810 ins_cost(3 * DEFAULT_COST + BRANCH_COST);
8811 // TODO: s390 port size(VARIABLE_SIZE);
8812 format %{ "MaxI $dst $src1,$src2\t MaxI" %}
8813 ins_encode %{
8814 Register Rdst = $dst$$Register;
8815 Register Rsrc1 = $src1$$Register;
8816 Register Rsrc2 = $src2$$Register;
8817 Label done;
8818
8819 if (Rsrc1 == Rsrc2) {
8820 if (Rdst != Rsrc1) {
8821 __ z_lgfr(Rdst, Rsrc1);
8822 }
8823 } else if (Rdst == Rsrc1) {
8824 __ z_cr(Rsrc1, Rsrc2);
8825 __ z_brh(done);
8826 __ z_lgfr(Rdst, Rsrc2);
8827 } else if (Rdst == Rsrc2) {
8828 __ z_cr(Rsrc2, Rsrc1);
8829 __ z_brh(done);
8830 __ z_lgfr(Rdst, Rsrc1);
8831 } else {
8832 __ z_lgfr(Rdst, Rsrc1);
8833 __ z_cr(Rsrc1, Rsrc2);
8834 __ z_brh(done);
8835 __ z_lgfr(Rdst, Rsrc2);
8836 }
8837
8838 __ bind(done);
8839 %}
8840
8841 ins_pipe(pipe_class_dummy);
8842 %}
8843
8844 instruct z196_maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8845 match(Set dst (MaxI src1 src2));
8846 effect(KILL cr);
8847 predicate(VM_Version::has_LoadStoreConditional());
8848 ins_cost(3 * DEFAULT_COST);
8849 // TODO: s390 port size(VARIABLE_SIZE);
8850 format %{ "MaxI $dst $src1,$src2\t MaxI const32 (z196 only)" %}
8851 ins_encode %{
8852 Register Rdst = $dst$$Register;
8853 Register Rsrc1 = $src1$$Register;
8854 int Isrc2 = $src2$$constant;
8855
8856 if (Rdst == Rsrc1) {
8857 __ load_const_optimized(Z_R0_scratch, Isrc2);
8858 __ z_cfi(Rsrc1, Isrc2);
8859 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
8860 } else {
8861 __ load_const_optimized(Rdst, Isrc2);
8862 __ z_cfi(Rsrc1, Isrc2);
8863 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8864 }
8865 %}
8866 ins_pipe(pipe_class_dummy);
8867 %}
8868
8869 instruct maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8870 match(Set dst (MaxI src1 src2));
8871 effect(KILL cr);
8872 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8873 // TODO: s390 port size(VARIABLE_SIZE);
8874 format %{ "MaxI $dst $src1,$src2\t MaxI const32" %}
8875 ins_encode %{
8876 Label done;
8877 if ($dst$$Register != $src1$$Register) {
8878 __ z_lgfr($dst$$Register, $src1$$Register);
8879 }
8880 __ z_cfi($src1$$Register, $src2$$constant);
8881 __ z_brh(done);
8882 __ z_lgfi($dst$$Register, $src2$$constant);
8883 __ bind(done);
8884 %}
8885 ins_pipe(pipe_class_dummy);
8886 %}
8887
8888 instruct z196_maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8889 match(Set dst (MaxI src1 src2));
8890 effect(KILL cr);
8891 predicate(VM_Version::has_LoadStoreConditional());
8892 ins_cost(3 * DEFAULT_COST);
8893 // TODO: s390 port size(VARIABLE_SIZE);
8894 format %{ "MaxI $dst $src1,$src2\t MaxI const16 (z196 only)" %}
8895 ins_encode %{
8896 Register Rdst = $dst$$Register;
8897 Register Rsrc1 = $src1$$Register;
8898 int Isrc2 = $src2$$constant;
8899 if (Rdst == Rsrc1) {
8900 __ load_const_optimized(Z_R0_scratch, Isrc2);
8901 __ z_chi(Rsrc1, Isrc2);
8902 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
8903 } else {
8904 __ load_const_optimized(Rdst, Isrc2);
8905 __ z_chi(Rsrc1, Isrc2);
8906 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8907 }
8908 %}
8909 ins_pipe(pipe_class_dummy);
8910 %}
8911
8912 instruct maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8913 match(Set dst (MaxI src1 src2));
8914 effect(KILL cr);
8915 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8916 // TODO: s390 port size(VARIABLE_SIZE);
8917 format %{ "MaxI $dst $src1,$src2\t MaxI const16" %}
8918 ins_encode %{
8919 Label done;
8920 if ($dst$$Register != $src1$$Register) {
8921 __ z_lgfr($dst$$Register, $src1$$Register);
8922 }
8923 __ z_chi($src1$$Register, $src2$$constant);
8924 __ z_brh(done);
8925 __ z_lghi($dst$$Register, $src2$$constant);
8926 __ bind(done);
8927 %}
8928 ins_pipe(pipe_class_dummy);
8929 %}
8930
8931 instruct z10_maxI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
8932 match(Set dst (MaxI src1 src2));
8933 effect(KILL cr);
8934 predicate(VM_Version::has_CompareBranch());
8935 ins_cost(DEFAULT_COST + BRANCH_COST);
8936 // TODO: s390 port size(VARIABLE_SIZE);
8937 format %{ "MaxI $dst $src1,$src2\t MaxI const8" %}
8938 ins_encode %{
8939 Label done;
8940 if ($dst$$Register != $src1$$Register) {
8941 __ z_lgfr($dst$$Register, $src1$$Register);
8942 }
8943 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondHigh, done);
8944 __ z_lghi($dst$$Register, $src2$$constant);
8945 __ bind(done);
8946 %}
8947 ins_pipe(pipe_class_dummy);
8948 %}
8949
8950 //----------Abs---------------------------------------------------------------
8951
8952 instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{
8953 match(Set dst (AbsI src));
8954 effect(KILL cr);
8955 ins_cost(DEFAULT_COST_LOW);
8956 // TODO: s390 port size(FIXED_SIZE);
8957 format %{ "LPR $dst, $src" %}
8958 opcode(LPR_ZOPC);
8959 ins_encode(z_rrform(dst, src));
8960 ins_pipe(pipe_class_dummy);
8961 %}
8962
8963 instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{
8964 match(Set dst (SubI zero (AbsI src)));
8965 effect(KILL cr);
8966 ins_cost(DEFAULT_COST_LOW);
8967 // TODO: s390 port size(FIXED_SIZE);
8968 format %{ "LNR $dst, $src" %}
8969 opcode(LNR_ZOPC);
8970 ins_encode(z_rrform(dst, src));
8971 ins_pipe(pipe_class_dummy);
8972 %}
8973
8974 //----------Float Compares----------------------------------------------------
8975
8976 // Compare floating, generate condition code.
8977 instruct cmpF_cc(flagsReg cr, regF src1, regF src2) %{
8978 match(Set cr (CmpF src1 src2));
8979 ins_cost(ALU_REG_COST);
8980 size(4);
8981 format %{ "FCMPcc $src1,$src2\t # float" %}
8982 ins_encode %{ __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); %}
8983 ins_pipe(pipe_class_dummy);
8984 %}
8985
8986 instruct cmpD_cc(flagsReg cr, regD src1, regD src2) %{
8987 match(Set cr (CmpD src1 src2));
8988 ins_cost(ALU_REG_COST);
8989 size(4);
8990 format %{ "FCMPcc $src1,$src2 \t # double" %}
8991 ins_encode %{ __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); %}
8992 ins_pipe(pipe_class_dummy);
8993 %}
8994
8995 instruct cmpF_cc_mem(flagsReg cr, regF src1, memoryRX src2) %{
8996 match(Set cr (CmpF src1 (LoadF src2)));
8997 ins_cost(ALU_MEMORY_COST);
8998 size(6);
8999 format %{ "FCMPcc_mem $src1,$src2\t # floatMemory" %}
9000 opcode(CEB_ZOPC);
9001 ins_encode(z_form_rt_memFP(src1, src2));
9002 ins_pipe(pipe_class_dummy);
9003 %}
9004
9005 instruct cmpD_cc_mem(flagsReg cr, regD src1, memoryRX src2) %{
9006 match(Set cr (CmpD src1 (LoadD src2)));
9007 ins_cost(ALU_MEMORY_COST);
9008 size(6);
9009 format %{ "DCMPcc_mem $src1,$src2\t # doubleMemory" %}
9010 opcode(CDB_ZOPC);
9011 ins_encode(z_form_rt_memFP(src1, src2));
9012 ins_pipe(pipe_class_dummy);
9013 %}
9014
9015 // Compare floating, generate condition code
9016 instruct cmpF0_cc(flagsReg cr, regF src1, immFpm0 src2) %{
9017 match(Set cr (CmpF src1 src2));
9018 ins_cost(DEFAULT_COST);
9019 size(4);
9020 format %{ "LTEBR $src1,$src1\t # float" %}
9021 opcode(LTEBR_ZOPC);
9022 ins_encode(z_rreform(src1, src1));
9023 ins_pipe(pipe_class_dummy);
9024 %}
9025
9026 instruct cmpD0_cc(flagsReg cr, regD src1, immDpm0 src2) %{
9027 match(Set cr (CmpD src1 src2));
9028 ins_cost(DEFAULT_COST);
9029 size(4);
9030 format %{ "LTDBR $src1,$src1 \t # double" %}
9031 opcode(LTDBR_ZOPC);
9032 ins_encode(z_rreform(src1, src1));
9033 ins_pipe(pipe_class_dummy);
9034 %}
9035
9036 // Compare floating, generate -1,0,1
9037 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg cr) %{
9038 match(Set dst (CmpF3 src1 src2));
9039 effect(KILL cr);
9040 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9041 size(24);
9042 format %{ "CmpF3 $dst,$src1,$src2" %}
9043 ins_encode %{
9044 // compare registers
9045 __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister);
9046 // Convert condition code into -1,0,1, where
9047 // -1 means unordered or less
9048 // 0 means equal
9049 // 1 means greater.
9050 if (VM_Version::has_LoadStoreConditional()) {
9051 Register one = Z_R0_scratch;
9052 Register minus_one = Z_R1_scratch;
9053 __ z_lghi(minus_one, -1);
9054 __ z_lghi(one, 1);
9055 __ z_lghi( $dst$$Register, 0);
9056 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9057 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9058 } else {
9059 Label done;
9060 __ clear_reg($dst$$Register, true, false);
9061 __ z_bre(done);
9062 __ z_lhi($dst$$Register, 1);
9063 __ z_brh(done);
9064 __ z_lhi($dst$$Register, -1);
9065 __ bind(done);
9066 }
9067 %}
9068 ins_pipe(pipe_class_dummy);
9069 %}
9070
9071 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg cr) %{
9072 match(Set dst (CmpD3 src1 src2));
9073 effect(KILL cr);
9074 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9075 size(24);
9076 format %{ "CmpD3 $dst,$src1,$src2" %}
9077 ins_encode %{
9078 // compare registers
9079 __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister);
9080 // Convert condition code into -1,0,1, where
9081 // -1 means unordered or less
9082 // 0 means equal
9083 // 1 means greater.
9084 if (VM_Version::has_LoadStoreConditional()) {
9085 Register one = Z_R0_scratch;
9086 Register minus_one = Z_R1_scratch;
9087 __ z_lghi(minus_one, -1);
9088 __ z_lghi(one, 1);
9089 __ z_lghi( $dst$$Register, 0);
9090 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9091 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9092 } else {
9093 Label done;
9094 // indicate unused result
9095 (void) __ clear_reg($dst$$Register, true, false);
9096 __ z_bre(done);
9097 __ z_lhi($dst$$Register, 1);
9098 __ z_brh(done);
9099 __ z_lhi($dst$$Register, -1);
9100 __ bind(done);
9101 }
9102 %}
9103 ins_pipe(pipe_class_dummy);
9104 %}
9105
9106 //----------Branches---------------------------------------------------------
9107 // Jump
9108
9109 // Direct Branch.
9110 instruct branch(label labl) %{
9111 match(Goto);
9112 effect(USE labl);
9113 ins_cost(BRANCH_COST);
9114 size(4);
9115 format %{ "BRU $labl" %}
9116 ins_encode(z_enc_bru(labl));
9117 ins_pipe(pipe_class_dummy);
9118 // If set to 1 this indicates that the current instruction is a
9119 // short variant of a long branch. This avoids using this
9120 // instruction in first-pass matching. It will then only be used in
9121 // the `Shorten_branches' pass.
9122 ins_short_branch(1);
9123 %}
9124
9125 // Direct Branch.
9126 instruct branchFar(label labl) %{
9127 match(Goto);
9128 effect(USE labl);
9129 ins_cost(BRANCH_COST);
9130 size(6);
9131 format %{ "BRUL $labl" %}
9132 ins_encode(z_enc_brul(labl));
9133 ins_pipe(pipe_class_dummy);
9134 // This is not a short variant of a branch, but the long variant.
9135 ins_short_branch(0);
9136 %}
9137
9138 // Conditional Near Branch
9139 instruct branchCon(cmpOp cmp, flagsReg cr, label lbl) %{
9140 // Same match rule as `branchConFar'.
9141 match(If cmp cr);
9142 effect(USE lbl);
9143 ins_cost(BRANCH_COST);
9144 size(4);
9145 format %{ "branch_con_short,$cmp $cr, $lbl" %}
9146 ins_encode(z_enc_branch_con_short(cmp, lbl));
9147 ins_pipe(pipe_class_dummy);
9148 // If set to 1 this indicates that the current instruction is a
9149 // short variant of a long branch. This avoids using this
9150 // instruction in first-pass matching. It will then only be used in
9151 // the `Shorten_branches' pass.
9152 ins_short_branch(1);
9153 %}
9154
9155 // This is for cases when the z/Architecture conditional branch instruction
9156 // does not reach far enough. So we emit a far branch here, which is
9157 // more expensive.
9158 //
9159 // Conditional Far Branch
9160 instruct branchConFar(cmpOp cmp, flagsReg cr, label lbl) %{
9161 // Same match rule as `branchCon'.
9162 match(If cmp cr);
9163 effect(USE cr, USE lbl);
9164 // Make more expensive to prefer compare_and_branch over separate instructions.
9165 ins_cost(2 * BRANCH_COST);
9166 size(6);
9167 format %{ "branch_con_far,$cmp $cr, $lbl" %}
9168 ins_encode(z_enc_branch_con_far(cmp, lbl));
9169 ins_pipe(pipe_class_dummy);
9170 // This is not a short variant of a branch, but the long variant..
9171 ins_short_branch(0);
9172 %}
9173
9174 instruct branchLoopEnd(cmpOp cmp, flagsReg cr, label labl) %{
9175 match(CountedLoopEnd cmp cr);
9176 effect(USE labl);
9177 ins_cost(BRANCH_COST);
9178 size(4);
9179 format %{ "branch_con_short,$cmp $labl\t # counted loop end" %}
9180 ins_encode(z_enc_branch_con_short(cmp, labl));
9181 ins_pipe(pipe_class_dummy);
9182 // If set to 1 this indicates that the current instruction is a
9183 // short variant of a long branch. This avoids using this
9184 // instruction in first-pass matching. It will then only be used in
9185 // the `Shorten_branches' pass.
9186 ins_short_branch(1);
9187 %}
9188
9189 instruct branchLoopEndFar(cmpOp cmp, flagsReg cr, label labl) %{
9190 match(CountedLoopEnd cmp cr);
9191 effect(USE labl);
9192 ins_cost(BRANCH_COST);
9193 size(6);
9194 format %{ "branch_con_far,$cmp $labl\t # counted loop end" %}
9195 ins_encode(z_enc_branch_con_far(cmp, labl));
9196 ins_pipe(pipe_class_dummy);
9197 // This is not a short variant of a branch, but the long variant.
9198 ins_short_branch(0);
9199 %}
9200
9201 //----------Compare and Branch (short distance)------------------------------
9202
9203 // INT REG operands for loop counter processing.
9204 instruct testAndBranchLoopEnd_Reg(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9205 match(CountedLoopEnd boolnode (CmpI src1 src2));
9206 effect(USE labl, KILL cr);
9207 predicate(VM_Version::has_CompareBranch());
9208 ins_cost(BRANCH_COST);
9209 // TODO: s390 port size(FIXED_SIZE);
9210 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %}
9211 opcode(CRJ_ZOPC);
9212 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9213 ins_pipe(pipe_class_dummy);
9214 ins_short_branch(1);
9215 %}
9216
9217 // INT REG operands.
9218 instruct cmpb_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9219 match(If boolnode (CmpI src1 src2));
9220 effect(USE labl, KILL cr);
9221 predicate(VM_Version::has_CompareBranch());
9222 ins_cost(BRANCH_COST);
9223 // TODO: s390 port size(FIXED_SIZE);
9224 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9225 opcode(CRJ_ZOPC);
9226 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9227 ins_pipe(pipe_class_dummy);
9228 ins_short_branch(1);
9229 %}
9230
9231 // Unsigned INT REG operands
9232 instruct cmpbU_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9233 match(If boolnode (CmpU src1 src2));
9234 effect(USE labl, KILL cr);
9235 predicate(VM_Version::has_CompareBranch());
9236 ins_cost(BRANCH_COST);
9237 // TODO: s390 port size(FIXED_SIZE);
9238 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9239 opcode(CLRJ_ZOPC);
9240 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9241 ins_pipe(pipe_class_dummy);
9242 ins_short_branch(1);
9243 %}
9244
9245 // LONG REG operands
9246 instruct cmpb_RegL(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9247 match(If boolnode (CmpL src1 src2));
9248 effect(USE labl, KILL cr);
9249 predicate(VM_Version::has_CompareBranch());
9250 ins_cost(BRANCH_COST);
9251 // TODO: s390 port size(FIXED_SIZE);
9252 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9253 opcode(CGRJ_ZOPC);
9254 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9255 ins_pipe(pipe_class_dummy);
9256 ins_short_branch(1);
9257 %}
9258
9259 // PTR REG operands
9260
9261 // Separate rules for regular and narrow oops. ADLC can't recognize
9262 // rules with polymorphic operands to be sisters -> shorten_branches
9263 // will not shorten.
9264
9265 instruct cmpb_RegPP(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9266 match(If boolnode (CmpP src1 src2));
9267 effect(USE labl, KILL cr);
9268 predicate(VM_Version::has_CompareBranch());
9269 ins_cost(BRANCH_COST);
9270 // TODO: s390 port size(FIXED_SIZE);
9271 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9272 opcode(CLGRJ_ZOPC);
9273 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9274 ins_pipe(pipe_class_dummy);
9275 ins_short_branch(1);
9276 %}
9277
9278 instruct cmpb_RegNN(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9279 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9280 effect(USE labl, KILL cr);
9281 predicate(VM_Version::has_CompareBranch());
9282 ins_cost(BRANCH_COST);
9283 // TODO: s390 port size(FIXED_SIZE);
9284 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9285 opcode(CLGRJ_ZOPC);
9286 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9287 ins_pipe(pipe_class_dummy);
9288 ins_short_branch(1);
9289 %}
9290
9291 // INT REG/IMM operands for loop counter processing
9292 instruct testAndBranchLoopEnd_Imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9293 match(CountedLoopEnd boolnode (CmpI src1 src2));
9294 effect(USE labl, KILL cr);
9295 predicate(VM_Version::has_CompareBranch());
9296 ins_cost(BRANCH_COST);
9297 // TODO: s390 port size(FIXED_SIZE);
9298 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %}
9299 opcode(CIJ_ZOPC);
9300 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9301 ins_pipe(pipe_class_dummy);
9302 ins_short_branch(1);
9303 %}
9304
9305 // INT REG/IMM operands
9306 instruct cmpb_RegI_imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9307 match(If boolnode (CmpI src1 src2));
9308 effect(USE labl, KILL cr);
9309 predicate(VM_Version::has_CompareBranch());
9310 ins_cost(BRANCH_COST);
9311 // TODO: s390 port size(FIXED_SIZE);
9312 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9313 opcode(CIJ_ZOPC);
9314 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9315 ins_pipe(pipe_class_dummy);
9316 ins_short_branch(1);
9317 %}
9318
9319 // INT REG/IMM operands
9320 instruct cmpbU_RegI_imm(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9321 match(If boolnode (CmpU src1 src2));
9322 effect(USE labl, KILL cr);
9323 predicate(VM_Version::has_CompareBranch());
9324 ins_cost(BRANCH_COST);
9325 // TODO: s390 port size(FIXED_SIZE);
9326 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9327 opcode(CLIJ_ZOPC);
9328 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9329 ins_pipe(pipe_class_dummy);
9330 ins_short_branch(1);
9331 %}
9332
9333 // LONG REG/IMM operands
9334 instruct cmpb_RegL_imm(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9335 match(If boolnode (CmpL src1 src2));
9336 effect(USE labl, KILL cr);
9337 predicate(VM_Version::has_CompareBranch());
9338 ins_cost(BRANCH_COST);
9339 // TODO: s390 port size(FIXED_SIZE);
9340 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9341 opcode(CGIJ_ZOPC);
9342 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9343 ins_pipe(pipe_class_dummy);
9344 ins_short_branch(1);
9345 %}
9346
9347 // PTR REG-imm operands
9348
9349 // Separate rules for regular and narrow oops. ADLC can't recognize
9350 // rules with polymorphic operands to be sisters -> shorten_branches
9351 // will not shorten.
9352
9353 instruct cmpb_RegP_immP(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9354 match(If boolnode (CmpP src1 src2));
9355 effect(USE labl, KILL cr);
9356 predicate(VM_Version::has_CompareBranch());
9357 ins_cost(BRANCH_COST);
9358 // TODO: s390 port size(FIXED_SIZE);
9359 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9360 opcode(CLGIJ_ZOPC);
9361 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9362 ins_pipe(pipe_class_dummy);
9363 ins_short_branch(1);
9364 %}
9365
9366 // Compare against zero only, do not mix N and P oops (encode/decode required).
9367 instruct cmpb_RegN_immP0(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9368 match(If boolnode (CmpP (DecodeN src1) src2));
9369 effect(USE labl, KILL cr);
9370 predicate(VM_Version::has_CompareBranch());
9371 ins_cost(BRANCH_COST);
9372 // TODO: s390 port size(FIXED_SIZE);
9373 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9374 opcode(CLGIJ_ZOPC);
9375 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9376 ins_pipe(pipe_class_dummy);
9377 ins_short_branch(1);
9378 %}
9379
9380 instruct cmpb_RegN_imm(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9381 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9382 effect(USE labl, KILL cr);
9383 predicate(VM_Version::has_CompareBranch());
9384 ins_cost(BRANCH_COST);
9385 // TODO: s390 port size(FIXED_SIZE);
9386 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9387 opcode(CLGIJ_ZOPC);
9388 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9389 ins_pipe(pipe_class_dummy);
9390 ins_short_branch(1);
9391 %}
9392
9393
9394 //----------Compare and Branch (far distance)------------------------------
9395
9396 // INT REG operands for loop counter processing
9397 instruct testAndBranchLoopEnd_RegFar(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9398 match(CountedLoopEnd boolnode (CmpI src1 src2));
9399 effect(USE labl, KILL cr);
9400 predicate(VM_Version::has_CompareBranch());
9401 ins_cost(BRANCH_COST+DEFAULT_COST);
9402 // TODO: s390 port size(FIXED_SIZE);
9403 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %}
9404 opcode(CR_ZOPC, BRCL_ZOPC);
9405 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9406 ins_pipe(pipe_class_dummy);
9407 ins_short_branch(0);
9408 %}
9409
9410 // INT REG operands
9411 instruct cmpb_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9412 match(If boolnode (CmpI src1 src2));
9413 effect(USE labl, KILL cr);
9414 predicate(VM_Version::has_CompareBranch());
9415 ins_cost(BRANCH_COST+DEFAULT_COST);
9416 // TODO: s390 port size(FIXED_SIZE);
9417 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9418 opcode(CR_ZOPC, BRCL_ZOPC);
9419 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9420 ins_pipe(pipe_class_dummy);
9421 ins_short_branch(0);
9422 %}
9423
9424 // INT REG operands
9425 instruct cmpbU_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9426 match(If boolnode (CmpU src1 src2));
9427 effect(USE labl, KILL cr);
9428 predicate(VM_Version::has_CompareBranch());
9429 ins_cost(BRANCH_COST+DEFAULT_COST);
9430 // TODO: s390 port size(FIXED_SIZE);
9431 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9432 opcode(CLR_ZOPC, BRCL_ZOPC);
9433 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9434 ins_pipe(pipe_class_dummy);
9435 ins_short_branch(0);
9436 %}
9437
9438 // LONG REG operands
9439 instruct cmpb_RegL_Far(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9440 match(If boolnode (CmpL src1 src2));
9441 effect(USE labl, KILL cr);
9442 predicate(VM_Version::has_CompareBranch());
9443 ins_cost(BRANCH_COST+DEFAULT_COST);
9444 // TODO: s390 port size(FIXED_SIZE);
9445 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9446 opcode(CGR_ZOPC, BRCL_ZOPC);
9447 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9448 ins_pipe(pipe_class_dummy);
9449 ins_short_branch(0);
9450 %}
9451
9452 // PTR REG operands
9453
9454 // Separate rules for regular and narrow oops. ADLC can't recognize
9455 // rules with polymorphic operands to be sisters -> shorten_branches
9456 // will not shorten.
9457
9458 instruct cmpb_RegPP_Far(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9459 match(If boolnode (CmpP src1 src2));
9460 effect(USE labl, KILL cr);
9461 predicate(VM_Version::has_CompareBranch());
9462 ins_cost(BRANCH_COST+DEFAULT_COST);
9463 // TODO: s390 port size(FIXED_SIZE);
9464 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9465 opcode(CLGR_ZOPC, BRCL_ZOPC);
9466 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9467 ins_pipe(pipe_class_dummy);
9468 ins_short_branch(0);
9469 %}
9470
9471 instruct cmpb_RegNN_Far(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9472 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9473 effect(USE labl, KILL cr);
9474 predicate(VM_Version::has_CompareBranch());
9475 ins_cost(BRANCH_COST+DEFAULT_COST);
9476 // TODO: s390 port size(FIXED_SIZE);
9477 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9478 opcode(CLGR_ZOPC, BRCL_ZOPC);
9479 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9480 ins_pipe(pipe_class_dummy);
9481 ins_short_branch(0);
9482 %}
9483
9484 // INT REG/IMM operands for loop counter processing
9485 instruct testAndBranchLoopEnd_ImmFar(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9486 match(CountedLoopEnd boolnode (CmpI src1 src2));
9487 effect(USE labl, KILL cr);
9488 predicate(VM_Version::has_CompareBranch());
9489 ins_cost(BRANCH_COST+DEFAULT_COST);
9490 // TODO: s390 port size(FIXED_SIZE);
9491 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %}
9492 opcode(CHI_ZOPC, BRCL_ZOPC);
9493 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9494 ins_pipe(pipe_class_dummy);
9495 ins_short_branch(0);
9496 %}
9497
9498 // INT REG/IMM operands
9499 instruct cmpb_RegI_imm_Far(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9500 match(If boolnode (CmpI src1 src2));
9501 effect(USE labl, KILL cr);
9502 predicate(VM_Version::has_CompareBranch());
9503 ins_cost(BRANCH_COST+DEFAULT_COST);
9504 // TODO: s390 port size(FIXED_SIZE);
9505 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9506 opcode(CHI_ZOPC, BRCL_ZOPC);
9507 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9508 ins_pipe(pipe_class_dummy);
9509 ins_short_branch(0);
9510 %}
9511
9512 // INT REG/IMM operands
9513 instruct cmpbU_RegI_imm_Far(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9514 match(If boolnode (CmpU src1 src2));
9515 effect(USE labl, KILL cr);
9516 predicate(VM_Version::has_CompareBranch());
9517 ins_cost(BRANCH_COST+DEFAULT_COST);
9518 // TODO: s390 port size(FIXED_SIZE);
9519 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9520 opcode(CLFI_ZOPC, BRCL_ZOPC);
9521 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9522 ins_pipe(pipe_class_dummy);
9523 ins_short_branch(0);
9524 %}
9525
9526 // LONG REG/IMM operands
9527 instruct cmpb_RegL_imm_Far(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9528 match(If boolnode (CmpL src1 src2));
9529 effect(USE labl, KILL cr);
9530 predicate(VM_Version::has_CompareBranch());
9531 ins_cost(BRANCH_COST+DEFAULT_COST);
9532 // TODO: s390 port size(FIXED_SIZE);
9533 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9534 opcode(CGHI_ZOPC, BRCL_ZOPC);
9535 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9536 ins_pipe(pipe_class_dummy);
9537 ins_short_branch(0);
9538 %}
9539
9540 // PTR REG-imm operands
9541
9542 // Separate rules for regular and narrow oops. ADLC can't recognize
9543 // rules with polymorphic operands to be sisters -> shorten_branches
9544 // will not shorten.
9545
9546 instruct cmpb_RegP_immP_Far(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9547 match(If boolnode (CmpP src1 src2));
9548 effect(USE labl, KILL cr);
9549 predicate(VM_Version::has_CompareBranch());
9550 ins_cost(BRANCH_COST+DEFAULT_COST);
9551 // TODO: s390 port size(FIXED_SIZE);
9552 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9553 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9554 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9555 ins_pipe(pipe_class_dummy);
9556 ins_short_branch(0);
9557 %}
9558
9559 // Compare against zero only, do not mix N and P oops (encode/decode required).
9560 instruct cmpb_RegN_immP0_Far(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9561 match(If boolnode (CmpP (DecodeN src1) src2));
9562 effect(USE labl, KILL cr);
9563 predicate(VM_Version::has_CompareBranch());
9564 ins_cost(BRANCH_COST+DEFAULT_COST);
9565 // TODO: s390 port size(FIXED_SIZE);
9566 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9567 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9568 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9569 ins_pipe(pipe_class_dummy);
9570 ins_short_branch(0);
9571 %}
9572
9573 instruct cmpb_RegN_immN_Far(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9574 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9575 effect(USE labl, KILL cr);
9576 predicate(VM_Version::has_CompareBranch());
9577 ins_cost(BRANCH_COST+DEFAULT_COST);
9578 // TODO: s390 port size(FIXED_SIZE);
9579 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9580 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9581 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9582 ins_pipe(pipe_class_dummy);
9583 ins_short_branch(0);
9584 %}
9585
9586 // ============================================================================
9587 // Long Compare
9588
9589 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9590 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9591 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9592 // are collapsed internally in the ADLC's dfa-gen code. The match for
9593 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9594 // foo match ends up with the wrong leaf. One fix is to not match both
9595 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9596 // both forms beat the trinary form of long-compare and both are very useful
9597 // on platforms which have few registers.
9598
9599 // Manifest a CmpL3 result in an integer register. Very painful.
9600 // This is the test to avoid.
9601 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr) %{
9602 match(Set dst (CmpL3 src1 src2));
9603 effect(KILL cr);
9604 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9605 size(24);
9606 format %{ "CmpL3 $dst,$src1,$src2" %}
9607 ins_encode %{
9608 Label done;
9609 // compare registers
9610 __ z_cgr($src1$$Register, $src2$$Register);
9611 // Convert condition code into -1,0,1, where
9612 // -1 means less
9613 // 0 means equal
9614 // 1 means greater.
9615 if (VM_Version::has_LoadStoreConditional()) {
9616 Register one = Z_R0_scratch;
9617 Register minus_one = Z_R1_scratch;
9618 __ z_lghi(minus_one, -1);
9619 __ z_lghi(one, 1);
9620 __ z_lghi( $dst$$Register, 0);
9621 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9622 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLow);
9623 } else {
9624 __ clear_reg($dst$$Register, true, false);
9625 __ z_bre(done);
9626 __ z_lhi($dst$$Register, 1);
9627 __ z_brh(done);
9628 __ z_lhi($dst$$Register, -1);
9629 }
9630 __ bind(done);
9631 %}
9632 ins_pipe(pipe_class_dummy);
9633 %}
9634
9635 // ============================================================================
9636 // Safepoint Instruction
9637
9638 instruct safePoint() %{
9639 match(SafePoint);
9640 predicate(false);
9641 // TODO: s390 port size(FIXED_SIZE);
9642 format %{ "UNIMPLEMENTED Safepoint_ " %}
9643 ins_encode(enc_unimplemented());
9644 ins_pipe(pipe_class_dummy);
9645 %}
9646
9647 instruct safePoint_poll(iRegP poll, flagsReg cr) %{
9648 match(SafePoint poll);
9649 effect(USE poll, KILL cr); // R0 is killed, too.
9650 // TODO: s390 port size(FIXED_SIZE);
9651 format %{ "TM #0[,$poll],#111\t # Safepoint: poll for GC" %}
9652 ins_encode %{
9653 // Mark the code position where the load from the safepoint
9654 // polling page was emitted as relocInfo::poll_type.
9655 __ relocate(relocInfo::poll_type);
9656 __ load_from_polling_page($poll$$Register);
9657 %}
9658 ins_pipe(pipe_class_dummy);
9659 %}
9660
9661 // ============================================================================
9662
9663 // Call Instructions
9664
9665 // Call Java Static Instruction
9666 instruct CallStaticJavaDirect_dynTOC(method meth) %{
9667 match(CallStaticJava);
9668 effect(USE meth);
9669 ins_cost(CALL_COST);
9670 // TODO: s390 port size(VARIABLE_SIZE);
9671 format %{ "CALL,static dynTOC $meth; ==> " %}
9672 ins_encode( z_enc_java_static_call(meth) );
9673 ins_pipe(pipe_class_dummy);
9674 ins_alignment(2);
9675 %}
9676
9677 // Call Java Dynamic Instruction
9678 instruct CallDynamicJavaDirect_dynTOC(method meth) %{
9679 match(CallDynamicJava);
9680 effect(USE meth);
9681 ins_cost(CALL_COST);
9682 // TODO: s390 port size(VARIABLE_SIZE);
9683 format %{ "CALL,dynamic dynTOC $meth; ==> " %}
9684 ins_encode(z_enc_java_dynamic_call(meth));
9685 ins_pipe(pipe_class_dummy);
9686 ins_alignment(2);
9687 %}
9688
9689 // Call Runtime Instruction
9690 instruct CallRuntimeDirect(method meth) %{
9691 match(CallRuntime);
9692 effect(USE meth);
9693 ins_cost(CALL_COST);
9694 // TODO: s390 port size(VARIABLE_SIZE);
9695 ins_num_consts(1);
9696 ins_alignment(2);
9697 format %{ "CALL,runtime" %}
9698 ins_encode( z_enc_java_to_runtime_call(meth) );
9699 ins_pipe(pipe_class_dummy);
9700 %}
9701
9702 // Call runtime without safepoint - same as CallRuntime
9703 instruct CallLeafDirect(method meth) %{
9704 match(CallLeaf);
9705 effect(USE meth);
9706 ins_cost(CALL_COST);
9707 // TODO: s390 port size(VARIABLE_SIZE);
9708 ins_num_consts(1);
9709 ins_alignment(2);
9710 format %{ "CALL,runtime leaf $meth" %}
9711 ins_encode( z_enc_java_to_runtime_call(meth) );
9712 ins_pipe(pipe_class_dummy);
9713 %}
9714
9715 // Call runtime without safepoint - same as CallLeaf
9716 instruct CallLeafNoFPDirect(method meth) %{
9717 match(CallLeafNoFP);
9718 effect(USE meth);
9719 ins_cost(CALL_COST);
9720 // TODO: s390 port size(VARIABLE_SIZE);
9721 ins_num_consts(1);
9722 format %{ "CALL,runtime leaf nofp $meth" %}
9723 ins_encode( z_enc_java_to_runtime_call(meth) );
9724 ins_pipe(pipe_class_dummy);
9725 ins_alignment(2);
9726 %}
9727
9728 // Tail Call; Jump from runtime stub to Java code.
9729 // Also known as an 'interprocedural jump'.
9730 // Target of jump will eventually return to caller.
9731 // TailJump below removes the return address.
9732 instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_oop) %{
9733 match(TailCall jump_target method_oop);
9734 ins_cost(CALL_COST);
9735 size(2);
9736 format %{ "Jmp $jump_target\t# $method_oop holds method oop" %}
9737 ins_encode %{ __ z_br($jump_target$$Register); %}
9738 ins_pipe(pipe_class_dummy);
9739 %}
9740
9741 // Return Instruction
9742 instruct Ret() %{
9743 match(Return);
9744 size(2);
9745 format %{ "BR(Z_R14) // branch to link register" %}
9746 ins_encode %{ __ z_br(Z_R14); %}
9747 ins_pipe(pipe_class_dummy);
9748 %}
9749
9750 // Tail Jump; remove the return address; jump to target.
9751 // TailCall above leaves the return address around.
9752 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9753 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9754 // "restore" before this instruction (in Epilogue), we need to materialize it
9755 // in %i0.
9756 instruct tailjmpInd(iRegP jump_target, rarg1RegP ex_oop) %{
9757 match(TailJump jump_target ex_oop);
9758 ins_cost(CALL_COST);
9759 size(8);
9760 format %{ "TailJump $jump_target" %}
9761 ins_encode %{
9762 __ z_lg(Z_ARG2/* issuing pc */, _z_abi(return_pc), Z_SP);
9763 __ z_br($jump_target$$Register);
9764 %}
9765 ins_pipe(pipe_class_dummy);
9766 %}
9767
9768 // Create exception oop: created by stack-crawling runtime code.
9769 // Created exception is now available to this handler, and is setup
9770 // just prior to jumping to this handler. No code emitted.
9771 instruct CreateException(rarg1RegP ex_oop) %{
9772 match(Set ex_oop (CreateEx));
9773 ins_cost(0);
9774 size(0);
9775 format %{ "# exception oop; no code emitted" %}
9776 ins_encode(/*empty*/);
9777 ins_pipe(pipe_class_dummy);
9778 %}
9779
9780 // Rethrow exception: The exception oop will come in the first
9781 // argument position. Then JUMP (not call) to the rethrow stub code.
9782 instruct RethrowException() %{
9783 match(Rethrow);
9784 ins_cost(CALL_COST);
9785 // TODO: s390 port size(VARIABLE_SIZE);
9786 format %{ "Jmp rethrow_stub" %}
9787 ins_encode %{
9788 cbuf.set_insts_mark();
9789 __ load_const_optimized(Z_R1_scratch, (address)OptoRuntime::rethrow_stub());
9790 __ z_br(Z_R1_scratch);
9791 %}
9792 ins_pipe(pipe_class_dummy);
9793 %}
9794
9795 // Die now.
9796 instruct ShouldNotReachHere() %{
9797 match(Halt);
9798 ins_cost(CALL_COST);
9799 size(2);
9800 format %{ "ILLTRAP; ShouldNotReachHere" %}
9801 ins_encode %{ __ z_illtrap(); %}
9802 ins_pipe(pipe_class_dummy);
9803 %}
9804
9805 // ============================================================================
9806 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9807 // array for an instance of the superklass. Set a hidden internal cache on a
9808 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9809 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9810 instruct partialSubtypeCheck(rarg1RegP index, rarg2RegP sub, rarg3RegP super, flagsReg pcc,
9811 rarg4RegP scratch1, rarg5RegP scratch2) %{
9812 match(Set index (PartialSubtypeCheck sub super));
9813 effect(KILL pcc, KILL scratch1, KILL scratch2);
9814 ins_cost(10 * DEFAULT_COST);
9815 size(12);
9816 format %{ " CALL PartialSubtypeCheck\n" %}
9817 ins_encode %{
9818 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
9819 __ load_const_optimized(Z_ARG4, stub_address);
9820 __ z_basr(Z_R14, Z_ARG4);
9821 %}
9822 ins_pipe(pipe_class_dummy);
9823 %}
9824
9825 instruct partialSubtypeCheck_vs_zero(flagsReg pcc, rarg2RegP sub, rarg3RegP super, immP0 zero,
9826 rarg1RegP index, rarg4RegP scratch1, rarg5RegP scratch2) %{
9827 match(Set pcc (CmpI (PartialSubtypeCheck sub super) zero));
9828 effect(KILL scratch1, KILL scratch2, KILL index);
9829 ins_cost(10 * DEFAULT_COST);
9830 // TODO: s390 port size(FIXED_SIZE);
9831 format %{ "CALL PartialSubtypeCheck_vs_zero\n" %}
9832 ins_encode %{
9833 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
9834 __ load_const_optimized(Z_ARG4, stub_address);
9835 __ z_basr(Z_R14, Z_ARG4);
9836 %}
9837 ins_pipe(pipe_class_dummy);
9838 %}
9839
9840 // ============================================================================
9841 // inlined locking and unlocking
9842
9843 instruct cmpFastLock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
9844 match(Set pcc (FastLock oop box));
9845 effect(TEMP tmp1, TEMP tmp2);
9846 ins_cost(100);
9847 // TODO: s390 port size(VARIABLE_SIZE); // Uses load_const_optimized.
9848 format %{ "FASTLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %}
9849 ins_encode %{ __ compiler_fast_lock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register,
9850 UseBiasedLocking && !UseOptoBiasInlining); %}
9851 ins_pipe(pipe_class_dummy);
9852 %}
9853
9854 instruct cmpFastUnlock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
9855 match(Set pcc (FastUnlock oop box));
9856 effect(TEMP tmp1, TEMP tmp2);
9857 ins_cost(100);
9858 // TODO: s390 port size(FIXED_SIZE); // emitted code depends on UseBiasedLocking being on/off.
9859 format %{ "FASTUNLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %}
9860 ins_encode %{ __ compiler_fast_unlock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register,
9861 UseBiasedLocking && !UseOptoBiasInlining); %}
9862 ins_pipe(pipe_class_dummy);
9863 %}
9864
9865 instruct inlineCallClearArrayConst(SSlenDW cnt, iRegP_N2P base, Universe dummy, flagsReg cr) %{
9866 match(Set dummy (ClearArray cnt base));
9867 effect(KILL cr);
9868 ins_cost(100);
9869 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to varying #instructions.
9870 format %{ "ClearArrayConst $cnt,$base" %}
9871 ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %}
9872 ins_pipe(pipe_class_dummy);
9873 %}
9874
9875 instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, revenRegL srcA, roddRegL srcL, flagsReg cr) %{
9876 match(Set dummy (ClearArray cnt base));
9877 effect(TEMP srcA, TEMP srcL, KILL cr); // R0, R1 are killed, too.
9878 ins_cost(200);
9879 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to optimized constant loader.
9880 format %{ "ClearArrayConstBig $cnt,$base" %}
9881 ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $srcA$$Register, $srcL$$Register); %}
9882 ins_pipe(pipe_class_dummy);
9883 %}
9884
9885 instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, revenRegL srcA, roddRegL srcL, flagsReg cr) %{
9886 match(Set dummy (ClearArray cnt base));
9887 effect(TEMP srcA, TEMP srcL, KILL cr); // R0, R1 are killed, too.
9888 ins_cost(300);
9889 // TODO: s390 port size(FIXED_SIZE); // z/Architecture: emitted code depends on PreferLAoverADD being on/off.
9890 format %{ "ClearArrayVar $cnt,$base" %}
9891 ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $srcA$$Register, $srcL$$Register); %}
9892 ins_pipe(pipe_class_dummy);
9893 %}
9894
9895 // ============================================================================
9896 // CompactStrings
9897
9898 // String equals
9899 instruct string_equalsL(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
9900 match(Set result (StrEquals (Binary str1 str2) cnt));
9901 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
9902 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
9903 ins_cost(300);
9904 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
9905 ins_encode %{
9906 __ array_equals(false, $str1$$Register, $str2$$Register,
9907 $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
9908 $result$$Register, true /* byte */);
9909 %}
9910 ins_pipe(pipe_class_dummy);
9911 %}
9912
9913 instruct string_equalsU(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
9914 match(Set result (StrEquals (Binary str1 str2) cnt));
9915 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
9916 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
9917 ins_cost(300);
9918 format %{ "String Equals char[] $str1,$str2,$cnt -> $result" %}
9919 ins_encode %{
9920 __ array_equals(false, $str1$$Register, $str2$$Register,
9921 $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
9922 $result$$Register, false /* byte */);
9923 %}
9924 ins_pipe(pipe_class_dummy);
9925 %}
9926
9927 instruct string_equals_imm(iRegP str1, iRegP str2, uimmI8 cnt, iRegI result, flagsReg cr) %{
9928 match(Set result (StrEquals (Binary str1 str2) cnt));
9929 effect(KILL cr); // R0 is killed, too.
9930 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
9931 ins_cost(100);
9932 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
9933 ins_encode %{
9934 const int cnt_imm = $cnt$$constant;
9935 if (cnt_imm) { __ z_clc(0, cnt_imm - 1, $str1$$Register, 0, $str2$$Register); }
9936 __ z_lhi($result$$Register, 1);
9937 if (cnt_imm) {
9938 if (VM_Version::has_LoadStoreConditional()) {
9939 __ z_lhi(Z_R0_scratch, 0);
9940 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
9941 } else {
9942 Label Lskip;
9943 __ z_bre(Lskip);
9944 __ clear_reg($result$$Register);
9945 __ bind(Lskip);
9946 }
9947 }
9948 %}
9949 ins_pipe(pipe_class_dummy);
9950 %}
9951
9952 instruct string_equalsC_imm(iRegP str1, iRegP str2, immI8 cnt, iRegI result, flagsReg cr) %{
9953 match(Set result (StrEquals (Binary str1 str2) cnt));
9954 effect(KILL cr); // R0 is killed, too.
9955 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
9956 ins_cost(100);
9957 format %{ "String Equals $str1,$str2,$cnt -> $result" %}
9958 ins_encode %{
9959 const int cnt_imm = $cnt$$constant; // positive immI8 (7 bits used)
9960 if (cnt_imm) { __ z_clc(0, (cnt_imm << 1) - 1, $str1$$Register, 0, $str2$$Register); }
9961 __ z_lhi($result$$Register, 1);
9962 if (cnt_imm) {
9963 if (VM_Version::has_LoadStoreConditional()) {
9964 __ z_lhi(Z_R0_scratch, 0);
9965 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
9966 } else {
9967 Label Lskip;
9968 __ z_bre(Lskip);
9969 __ clear_reg($result$$Register);
9970 __ bind(Lskip);
9971 }
9972 }
9973 %}
9974 ins_pipe(pipe_class_dummy);
9975 %}
9976
9977 // Array equals
9978 instruct array_equalsB(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
9979 match(Set result (AryEq ary1 ary2));
9980 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
9981 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
9982 ins_cost(300);
9983 format %{ "Array Equals $ary1,$ary2 -> $result" %}
9984 ins_encode %{
9985 __ array_equals(true, $ary1$$Register, $ary2$$Register,
9986 noreg, $oddReg$$Register, $evenReg$$Register,
9987 $result$$Register, true /* byte */);
9988 %}
9989 ins_pipe(pipe_class_dummy);
9990 %}
9991
9992 instruct array_equalsC(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
9993 match(Set result (AryEq ary1 ary2));
9994 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
9995 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
9996 ins_cost(300);
9997 format %{ "Array Equals $ary1,$ary2 -> $result" %}
9998 ins_encode %{
9999 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10000 noreg, $oddReg$$Register, $evenReg$$Register,
10001 $result$$Register, false /* byte */);
10002 %}
10003 ins_pipe(pipe_class_dummy);
10004 %}
10005
10006 // String CompareTo
10007 instruct string_compareL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10008 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10009 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10010 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10011 ins_cost(300);
10012 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10013 ins_encode %{
10014 __ string_compare($str1$$Register, $str2$$Register,
10015 $cnt1$$Register, $cnt2$$Register,
10016 $oddReg$$Register, $evenReg$$Register,
10017 $result$$Register, StrIntrinsicNode::LL);
10018 %}
10019 ins_pipe(pipe_class_dummy);
10020 %}
10021
10022 instruct string_compareU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10023 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10024 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10025 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrCompNode*)n)->encoding() == StrIntrinsicNode::none);
10026 ins_cost(300);
10027 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10028 ins_encode %{
10029 __ string_compare($str1$$Register, $str2$$Register,
10030 $cnt1$$Register, $cnt2$$Register,
10031 $oddReg$$Register, $evenReg$$Register,
10032 $result$$Register, StrIntrinsicNode::UU);
10033 %}
10034 ins_pipe(pipe_class_dummy);
10035 %}
10036
10037 instruct string_compareLU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10038 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10039 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10040 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10041 ins_cost(300);
10042 format %{ "String Compare byte[],char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10043 ins_encode %{
10044 __ string_compare($str1$$Register, $str2$$Register,
10045 $cnt1$$Register, $cnt2$$Register,
10046 $oddReg$$Register, $evenReg$$Register,
10047 $result$$Register, StrIntrinsicNode::LU);
10048 %}
10049 ins_pipe(pipe_class_dummy);
10050 %}
10051
10052 instruct string_compareUL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10053 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10054 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10055 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10056 ins_cost(300);
10057 format %{ "String Compare char[],byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10058 ins_encode %{
10059 __ string_compare($str2$$Register, $str1$$Register,
10060 $cnt2$$Register, $cnt1$$Register,
10061 $oddReg$$Register, $evenReg$$Register,
10062 $result$$Register, StrIntrinsicNode::UL);
10063 %}
10064 ins_pipe(pipe_class_dummy);
10065 %}
10066
10067 // String IndexOfChar
10068 instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10069 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10070 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10071 ins_cost(200);
10072 format %{ "String IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10073 ins_encode %{
10074 __ string_indexof_char($result$$Register,
10075 $haystack$$Register, $haycnt$$Register,
10076 $ch$$Register, 0 /* unused, ch is in register */,
10077 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10078 %}
10079 ins_pipe(pipe_class_dummy);
10080 %}
10081
10082 instruct indexOf_imm1_U(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10083 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10084 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10085 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10086 ins_cost(200);
10087 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10088 ins_encode %{
10089 immPOper *needleOper = (immPOper *)$needle;
10090 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10091 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10092 jchar chr;
10093 #ifdef VM_LITTLE_ENDIAN
10094 Unimplemented();
10095 #else
10096 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
10097 ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
10098 #endif
10099 __ string_indexof_char($result$$Register,
10100 $haystack$$Register, $haycnt$$Register,
10101 noreg, chr,
10102 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10103 %}
10104 ins_pipe(pipe_class_dummy);
10105 %}
10106
10107 instruct indexOf_imm1_L(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10108 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10109 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10110 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10111 ins_cost(200);
10112 format %{ "String IndexOf L [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10113 ins_encode %{
10114 immPOper *needleOper = (immPOper *)$needle;
10115 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10116 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10117 jchar chr = (jchar)needle_values->element_value(0).as_byte();
10118 __ string_indexof_char($result$$Register,
10119 $haystack$$Register, $haycnt$$Register,
10120 noreg, chr,
10121 $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10122 %}
10123 ins_pipe(pipe_class_dummy);
10124 %}
10125
10126 instruct indexOf_imm1_UL(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10127 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10128 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10129 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10130 ins_cost(200);
10131 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10132 ins_encode %{
10133 immPOper *needleOper = (immPOper *)$needle;
10134 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10135 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10136 jchar chr = (jchar)needle_values->element_value(0).as_byte();
10137 __ string_indexof_char($result$$Register,
10138 $haystack$$Register, $haycnt$$Register,
10139 noreg, chr,
10140 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10141 %}
10142 ins_pipe(pipe_class_dummy);
10143 %}
10144
10145 // String IndexOf
10146 instruct indexOf_imm_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10147 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10148 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10149 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10150 ins_cost(250);
10151 format %{ "String IndexOf U [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10152 ins_encode %{
10153 __ string_indexof($result$$Register,
10154 $haystack$$Register, $haycnt$$Register,
10155 $needle$$Register, noreg, $needlecntImm$$constant,
10156 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10157 %}
10158 ins_pipe(pipe_class_dummy);
10159 %}
10160
10161 instruct indexOf_imm_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10162 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10163 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10164 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10165 ins_cost(250);
10166 format %{ "String IndexOf L [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10167 ins_encode %{
10168 __ string_indexof($result$$Register,
10169 $haystack$$Register, $haycnt$$Register,
10170 $needle$$Register, noreg, $needlecntImm$$constant,
10171 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10172 %}
10173 ins_pipe(pipe_class_dummy);
10174 %}
10175
10176 instruct indexOf_imm_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10177 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10178 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10179 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10180 ins_cost(250);
10181 format %{ "String IndexOf UL [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10182 ins_encode %{
10183 __ string_indexof($result$$Register,
10184 $haystack$$Register, $haycnt$$Register,
10185 $needle$$Register, noreg, $needlecntImm$$constant,
10186 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10187 %}
10188 ins_pipe(pipe_class_dummy);
10189 %}
10190
10191 instruct indexOf_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10192 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10193 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10194 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10195 ins_cost(300);
10196 format %{ "String IndexOf U [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10197 ins_encode %{
10198 __ string_indexof($result$$Register,
10199 $haystack$$Register, $haycnt$$Register,
10200 $needle$$Register, $needlecnt$$Register, 0,
10201 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10202 %}
10203 ins_pipe(pipe_class_dummy);
10204 %}
10205
10206 instruct indexOf_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10207 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10208 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10209 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10210 ins_cost(300);
10211 format %{ "String IndexOf L [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10212 ins_encode %{
10213 __ string_indexof($result$$Register,
10214 $haystack$$Register, $haycnt$$Register,
10215 $needle$$Register, $needlecnt$$Register, 0,
10216 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10217 %}
10218 ins_pipe(pipe_class_dummy);
10219 %}
10220
10221 instruct indexOf_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10222 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10223 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10224 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10225 ins_cost(300);
10226 format %{ "String IndexOf UL [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10227 ins_encode %{
10228 __ string_indexof($result$$Register,
10229 $haystack$$Register, $haycnt$$Register,
10230 $needle$$Register, $needlecnt$$Register, 0,
10231 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10232 %}
10233 ins_pipe(pipe_class_dummy);
10234 %}
10235
10236 // char[] to byte[] compression
10237 instruct string_compress(iRegP src, rarg5RegP dst, iRegI result, roddRegI len, revenRegI evenReg, iRegI tmp, flagsReg cr) %{
10238 match(Set result (StrCompressedCopy src (Binary dst len)));
10239 effect(TEMP_DEF result, USE_KILL dst, USE_KILL len, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10240 ins_cost(300);
10241 format %{ "String Compress $src->$dst($len) -> $result" %}
10242 ins_encode %{
10243 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10244 $evenReg$$Register, $tmp$$Register);
10245 %}
10246 ins_pipe(pipe_class_dummy);
10247 %}
10248
10249 // byte[] to char[] inflation. trot implementation is shorter, but slower than the unrolled icm(h) loop.
10250 //instruct string_inflate_trot(Universe dummy, iRegP src, revenRegP dst, roddRegI len, iRegI tmp, flagsReg cr) %{
10251 // match(Set dummy (StrInflatedCopy src (Binary dst len)));
10252 // effect(USE_KILL dst, USE_KILL len, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10253 // predicate(VM_Version::has_ETF2Enhancements());
10254 // ins_cost(300);
10255 // format %{ "String Inflate (trot) $dst,$src($len)" %}
10256 // ins_encode %{
10257 // __ string_inflate_trot($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register);
10258 // %}
10259 // ins_pipe(pipe_class_dummy);
10260 //%}
10261
10262 // byte[] to char[] inflation
10263 instruct string_inflate(Universe dummy, rarg5RegP src, iRegP dst, roddRegI len, revenRegI evenReg, iRegI tmp, flagsReg cr) %{
10264 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10265 effect(USE_KILL src, USE_KILL len, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10266 ins_cost(300);
10267 format %{ "String Inflate $src->$dst($len)" %}
10268 ins_encode %{
10269 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $evenReg$$Register, $tmp$$Register);
10270 %}
10271 ins_pipe(pipe_class_dummy);
10272 %}
10273
10274 // StringCoding.java intrinsics
10275 instruct has_negatives(rarg5RegP ary1, iRegI len, iRegI result, roddRegI oddReg, revenRegI evenReg, iRegI tmp, flagsReg cr) %{
10276 match(Set result (HasNegatives ary1 len));
10277 effect(TEMP_DEF result, USE_KILL ary1, TEMP oddReg, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10278 ins_cost(300);
10279 format %{ "has negatives byte[] $ary1($len) -> $result" %}
10280 ins_encode %{
10281 __ has_negatives($result$$Register, $ary1$$Register, $len$$Register,
10282 $oddReg$$Register, $evenReg$$Register, $tmp$$Register);
10283 %}
10284 ins_pipe(pipe_class_dummy);
10285 %}
10286
10287 // encode char[] to byte[] in ISO_8859_1
10288 instruct encode_iso_array(rarg5RegP src, iRegP dst, iRegI result, roddRegI len, revenRegI evenReg, iRegI tmp, iRegI tmp2, flagsReg cr) %{
10289 match(Set result (EncodeISOArray src (Binary dst len)));
10290 effect(TEMP_DEF result, USE_KILL src, USE_KILL len, TEMP evenReg, TEMP tmp, TEMP tmp2, KILL cr); // R0, R1 are killed, too.
10291 ins_cost(300);
10292 format %{ "Encode array $src->$dst($len) -> $result" %}
10293 ins_encode %{
10294 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10295 $evenReg$$Register, $tmp$$Register, $tmp2$$Register);
10296 %}
10297 ins_pipe(pipe_class_dummy);
10298 %}
10299
10300
10301 //----------PEEPHOLE RULES-----------------------------------------------------
10302 // These must follow all instruction definitions as they use the names
10303 // defined in the instructions definitions.
10304 //
10305 // peepmatch (root_instr_name [preceeding_instruction]*);
10306 //
10307 // peepconstraint %{
10308 // (instruction_number.operand_name relational_op instruction_number.operand_name
10309 // [, ...]);
10310 // // instruction numbers are zero-based using left to right order in peepmatch
10311 //
10312 // peepreplace (instr_name([instruction_number.operand_name]*));
10313 // // provide an instruction_number.operand_name for each operand that appears
10314 // // in the replacement instruction's match rule
10315 //
10316 // ---------VM FLAGS---------------------------------------------------------
10317 //
10318 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10319 //
10320 // Each peephole rule is given an identifying number starting with zero and
10321 // increasing by one in the order seen by the parser. An individual peephole
10322 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10323 // on the command-line.
10324 //
10325 // ---------CURRENT LIMITATIONS----------------------------------------------
10326 //
10327 // Only match adjacent instructions in same basic block
10328 // Only equality constraints
10329 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10330 // Only one replacement instruction
10331 //
10332 // ---------EXAMPLE----------------------------------------------------------
10333 //
10334 // // pertinent parts of existing instructions in architecture description
10335 // instruct movI(eRegI dst, eRegI src) %{
10336 // match(Set dst (CopyI src));
10337 // %}
10338 //
10339 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10340 // match(Set dst (AddI dst src));
10341 // effect(KILL cr);
10342 // %}
10343 //
10344 // // Change (inc mov) to lea
10345 // peephole %{
10346 // // increment preceeded by register-register move
10347 // peepmatch (incI_eReg movI);
10348 // // require that the destination register of the increment
10349 // // match the destination register of the move
10350 // peepconstraint (0.dst == 1.dst);
10351 // // construct a replacement instruction that sets
10352 // // the destination to (move's source register + one)
10353 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10354 // %}
10355 //
10356 // Implementation no longer uses movX instructions since
10357 // machine-independent system no longer uses CopyX nodes.
10358 //
10359 // peephole %{
10360 // peepmatch (incI_eReg movI);
10361 // peepconstraint (0.dst == 1.dst);
10362 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10363 // %}
10364 //
10365 // peephole %{
10366 // peepmatch (decI_eReg movI);
10367 // peepconstraint (0.dst == 1.dst);
10368 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10369 // %}
10370 //
10371 // peephole %{
10372 // peepmatch (addI_eReg_imm movI);
10373 // peepconstraint (0.dst == 1.dst);
10374 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10375 // %}
10376 //
10377 // peephole %{
10378 // peepmatch (addP_eReg_imm movP);
10379 // peepconstraint (0.dst == 1.dst);
10380 // peepreplace (leaP_eReg_immI(0.dst 1.src 0.src));
10381 // %}
10382
10383
10384 // This peephole rule does not work, probably because ADLC can't handle two effects:
10385 // Effect 1 is defining 0.op1 and effect 2 is setting CC
10386 // condense a load from memory and subsequent test for zero
10387 // into a single, more efficient ICM instruction.
10388 // peephole %{
10389 // peepmatch (compI_iReg_imm0 loadI);
10390 // peepconstraint (1.dst == 0.op1);
10391 // peepreplace (loadtest15_iReg_mem(0.op1 0.op1 1.mem));
10392 // %}
10393
10394 // // Change load of spilled value to only a spill
10395 // instruct storeI(memory mem, eRegI src) %{
10396 // match(Set mem (StoreI mem src));
10397 // %}
10398 //
10399 // instruct loadI(eRegI dst, memory mem) %{
10400 // match(Set dst (LoadI mem));
10401 // %}
10402 //
10403 peephole %{
10404 peepmatch (loadI storeI);
10405 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10406 peepreplace (storeI(1.mem 1.mem 1.src));
10407 %}
10408
10409 peephole %{
10410 peepmatch (loadL storeL);
10411 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10412 peepreplace (storeL(1.mem 1.mem 1.src));
10413 %}
10414
10415 peephole %{
10416 peepmatch (loadP storeP);
10417 peepconstraint (1.src == 0.dst, 1.dst == 0.mem);
10418 peepreplace (storeP(1.dst 1.dst 1.src));
10419 %}
10420
10421 //----------SUPERWORD RULES---------------------------------------------------
10422
10423 // Expand rules for special cases
10424
10425 instruct expand_storeF(stackSlotF mem, regF src) %{
10426 // No match rule, false predicate, for expand only.
10427 effect(DEF mem, USE src);
10428 predicate(false);
10429 ins_cost(MEMORY_REF_COST);
10430 // TODO: s390 port size(FIXED_SIZE);
10431 format %{ "STE $src,$mem\t # replicate(float2stack)" %}
10432 opcode(STE_ZOPC, STE_ZOPC);
10433 ins_encode(z_form_rt_mem(src, mem));
10434 ins_pipe(pipe_class_dummy);
10435 %}
10436
10437 instruct expand_LoadLogical_I2L(iRegL dst, stackSlotF mem) %{
10438 // No match rule, false predicate, for expand only.
10439 effect(DEF dst, USE mem);
10440 predicate(false);
10441 ins_cost(MEMORY_REF_COST);
10442 // TODO: s390 port size(FIXED_SIZE);
10443 format %{ "LLGF $dst,$mem\t # replicate(stack2reg(unsigned))" %}
10444 opcode(LLGF_ZOPC, LLGF_ZOPC);
10445 ins_encode(z_form_rt_mem(dst, mem));
10446 ins_pipe(pipe_class_dummy);
10447 %}
10448
10449 // Replicate scalar int to packed int values (8 Bytes)
10450 instruct expand_Repl2I_reg(iRegL dst, iRegL src) %{
10451 // Dummy match rule, false predicate, for expand only.
10452 match(Set dst (ConvI2L src));
10453 predicate(false);
10454 ins_cost(DEFAULT_COST);
10455 // TODO: s390 port size(FIXED_SIZE);
10456 format %{ "REPLIC2F $dst,$src\t # replicate(pack2F)" %}
10457 ins_encode %{
10458 if ($dst$$Register == $src$$Register) {
10459 __ z_sllg(Z_R0_scratch, $src$$Register, 64-32);
10460 __ z_ogr($dst$$Register, Z_R0_scratch);
10461 } else {
10462 __ z_sllg($dst$$Register, $src$$Register, 64-32);
10463 __ z_ogr( $dst$$Register, $src$$Register);
10464 }
10465 %}
10466 ins_pipe(pipe_class_dummy);
10467 %}
10468
10469 // Replication
10470
10471 // Exploit rotate_then_insert, if available
10472 // Replicate scalar byte to packed byte values (8 Bytes).
10473 instruct Repl8B_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10474 match(Set dst (ReplicateB src));
10475 effect(KILL cr);
10476 predicate((n->as_Vector()->length() == 8));
10477 format %{ "REPLIC8B $dst,$src\t # pack8B" %}
10478 ins_encode %{
10479 if ($dst$$Register != $src$$Register) {
10480 __ z_lgr($dst$$Register, $src$$Register);
10481 }
10482 __ rotate_then_insert($dst$$Register, $dst$$Register, 48, 55, 8, false);
10483 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10484 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10485 %}
10486 ins_pipe(pipe_class_dummy);
10487 %}
10488
10489 // Replicate scalar byte to packed byte values (8 Bytes).
10490 instruct Repl8B_imm(iRegL dst, immB_n0m1 src) %{
10491 match(Set dst (ReplicateB src));
10492 predicate(n->as_Vector()->length() == 8);
10493 ins_should_rematerialize(true);
10494 format %{ "REPLIC8B $dst,$src\t # pack8B imm" %}
10495 ins_encode %{
10496 int64_t Isrc8 = $src$$constant & 0x000000ff;
10497 int64_t Isrc16 = Isrc8 << 8 | Isrc8;
10498 int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10499 assert(Isrc8 != 0x000000ff && Isrc8 != 0, "should be handled by other match rules.");
10500
10501 __ z_llilf($dst$$Register, Isrc32);
10502 __ z_iihf($dst$$Register, Isrc32);
10503 %}
10504 ins_pipe(pipe_class_dummy);
10505 %}
10506
10507 // Replicate scalar byte to packed byte values (8 Bytes).
10508 instruct Repl8B_imm0(iRegL dst, immI_0 src) %{
10509 match(Set dst (ReplicateB src));
10510 predicate(n->as_Vector()->length() == 8);
10511 ins_should_rematerialize(true);
10512 format %{ "REPLIC8B $dst,$src\t # pack8B imm0" %}
10513 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10514 ins_pipe(pipe_class_dummy);
10515 %}
10516
10517 // Replicate scalar byte to packed byte values (8 Bytes).
10518 instruct Repl8B_immm1(iRegL dst, immB_minus1 src) %{
10519 match(Set dst (ReplicateB src));
10520 predicate(n->as_Vector()->length() == 8);
10521 ins_should_rematerialize(true);
10522 format %{ "REPLIC8B $dst,$src\t # pack8B immm1" %}
10523 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10524 ins_pipe(pipe_class_dummy);
10525 %}
10526
10527 // Exploit rotate_then_insert, if available
10528 // Replicate scalar short to packed short values (8 Bytes).
10529 instruct Repl4S_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10530 match(Set dst (ReplicateS src));
10531 effect(KILL cr);
10532 predicate((n->as_Vector()->length() == 4));
10533 format %{ "REPLIC4S $dst,$src\t # pack4S" %}
10534 ins_encode %{
10535 if ($dst$$Register != $src$$Register) {
10536 __ z_lgr($dst$$Register, $src$$Register);
10537 }
10538 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10539 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10540 %}
10541 ins_pipe(pipe_class_dummy);
10542 %}
10543
10544 // Replicate scalar short to packed short values (8 Bytes).
10545 instruct Repl4S_imm(iRegL dst, immS_n0m1 src) %{
10546 match(Set dst (ReplicateS src));
10547 predicate(n->as_Vector()->length() == 4);
10548 ins_should_rematerialize(true);
10549 format %{ "REPLIC4S $dst,$src\t # pack4S imm" %}
10550 ins_encode %{
10551 int64_t Isrc16 = $src$$constant & 0x0000ffff;
10552 int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10553 assert(Isrc16 != 0x0000ffff && Isrc16 != 0, "Repl4S_imm: (src == " INT64_FORMAT
10554 ") should be handled by other match rules.", $src$$constant);
10555
10556 __ z_llilf($dst$$Register, Isrc32);
10557 __ z_iihf($dst$$Register, Isrc32);
10558 %}
10559 ins_pipe(pipe_class_dummy);
10560 %}
10561
10562 // Replicate scalar short to packed short values (8 Bytes).
10563 instruct Repl4S_imm0(iRegL dst, immI_0 src) %{
10564 match(Set dst (ReplicateS src));
10565 predicate(n->as_Vector()->length() == 4);
10566 ins_should_rematerialize(true);
10567 format %{ "REPLIC4S $dst,$src\t # pack4S imm0" %}
10568 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10569 ins_pipe(pipe_class_dummy);
10570 %}
10571
10572 // Replicate scalar short to packed short values (8 Bytes).
10573 instruct Repl4S_immm1(iRegL dst, immS_minus1 src) %{
10574 match(Set dst (ReplicateS src));
10575 predicate(n->as_Vector()->length() == 4);
10576 ins_should_rematerialize(true);
10577 format %{ "REPLIC4S $dst,$src\t # pack4S immm1" %}
10578 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10579 ins_pipe(pipe_class_dummy);
10580 %}
10581
10582 // Exploit rotate_then_insert, if available.
10583 // Replicate scalar int to packed int values (8 Bytes).
10584 instruct Repl2I_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10585 match(Set dst (ReplicateI src));
10586 effect(KILL cr);
10587 predicate((n->as_Vector()->length() == 2));
10588 format %{ "REPLIC2I $dst,$src\t # pack2I" %}
10589 ins_encode %{
10590 if ($dst$$Register != $src$$Register) {
10591 __ z_lgr($dst$$Register, $src$$Register);
10592 }
10593 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10594 %}
10595 ins_pipe(pipe_class_dummy);
10596 %}
10597
10598 // Replicate scalar int to packed int values (8 Bytes).
10599 instruct Repl2I_imm(iRegL dst, immI_n0m1 src) %{
10600 match(Set dst (ReplicateI src));
10601 predicate(n->as_Vector()->length() == 2);
10602 ins_should_rematerialize(true);
10603 format %{ "REPLIC2I $dst,$src\t # pack2I imm" %}
10604 ins_encode %{
10605 int64_t Isrc32 = $src$$constant;
10606 assert(Isrc32 != -1 && Isrc32 != 0, "should be handled by other match rules.");
10607
10608 __ z_llilf($dst$$Register, Isrc32);
10609 __ z_iihf($dst$$Register, Isrc32);
10610 %}
10611 ins_pipe(pipe_class_dummy);
10612 %}
10613
10614 // Replicate scalar int to packed int values (8 Bytes).
10615 instruct Repl2I_imm0(iRegL dst, immI_0 src) %{
10616 match(Set dst (ReplicateI src));
10617 predicate(n->as_Vector()->length() == 2);
10618 ins_should_rematerialize(true);
10619 format %{ "REPLIC2I $dst,$src\t # pack2I imm0" %}
10620 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10621 ins_pipe(pipe_class_dummy);
10622 %}
10623
10624 // Replicate scalar int to packed int values (8 Bytes).
10625 instruct Repl2I_immm1(iRegL dst, immI_minus1 src) %{
10626 match(Set dst (ReplicateI src));
10627 predicate(n->as_Vector()->length() == 2);
10628 ins_should_rematerialize(true);
10629 format %{ "REPLIC2I $dst,$src\t # pack2I immm1" %}
10630 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10631 ins_pipe(pipe_class_dummy);
10632 %}
10633
10634 //
10635
10636 instruct Repl2F_reg_indirect(iRegL dst, regF src, flagsReg cr) %{
10637 match(Set dst (ReplicateF src));
10638 effect(KILL cr);
10639 predicate(!VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2);
10640 format %{ "REPLIC2F $dst,$src\t # pack2F indirect" %}
10641 expand %{
10642 stackSlotF tmp;
10643 iRegL tmp2;
10644 expand_storeF(tmp, src);
10645 expand_LoadLogical_I2L(tmp2, tmp);
10646 expand_Repl2I_reg(dst, tmp2);
10647 %}
10648 %}
10649
10650 // Replicate scalar float to packed float values in GREG (8 Bytes).
10651 instruct Repl2F_reg_direct(iRegL dst, regF src, flagsReg cr) %{
10652 match(Set dst (ReplicateF src));
10653 effect(KILL cr);
10654 predicate(VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2);
10655 format %{ "REPLIC2F $dst,$src\t # pack2F direct" %}
10656 ins_encode %{
10657 assert(VM_Version::has_FPSupportEnhancements(), "encoder should never be called on old H/W");
10658 __ z_lgdr($dst$$Register, $src$$FloatRegister);
10659
10660 __ z_srlg(Z_R0_scratch, $dst$$Register, 32); // Floats are left-justified in 64bit reg.
10661 __ z_iilf($dst$$Register, 0); // Save a "result not ready" stall.
10662 __ z_ogr($dst$$Register, Z_R0_scratch);
10663 %}
10664 ins_pipe(pipe_class_dummy);
10665 %}
10666
10667 // Replicate scalar float immediate to packed float values in GREG (8 Bytes).
10668 instruct Repl2F_imm(iRegL dst, immF src) %{
10669 match(Set dst (ReplicateF src));
10670 predicate(n->as_Vector()->length() == 2);
10671 ins_should_rematerialize(true);
10672 format %{ "REPLIC2F $dst,$src\t # pack2F imm" %}
10673 ins_encode %{
10674 union {
10675 int Isrc32;
10676 float Fsrc32;
10677 };
10678 Fsrc32 = $src$$constant;
10679 __ z_llilf($dst$$Register, Isrc32);
10680 __ z_iihf($dst$$Register, Isrc32);
10681 %}
10682 ins_pipe(pipe_class_dummy);
10683 %}
10684
10685 // Replicate scalar float immediate zeroes to packed float values in GREG (8 Bytes).
10686 // Do this only for 'real' zeroes, especially don't loose sign of negative zeroes.
10687 instruct Repl2F_imm0(iRegL dst, immFp0 src) %{
10688 match(Set dst (ReplicateF src));
10689 predicate(n->as_Vector()->length() == 2);
10690 ins_should_rematerialize(true);
10691 format %{ "REPLIC2F $dst,$src\t # pack2F imm0" %}
10692 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10693 ins_pipe(pipe_class_dummy);
10694 %}
10695
10696 // Store
10697
10698 // Store Aligned Packed Byte register to memory (8 Bytes).
10699 instruct storeA8B(memory mem, iRegL src) %{
10700 match(Set mem (StoreVector mem src));
10701 predicate(n->as_StoreVector()->memory_size() == 8);
10702 ins_cost(MEMORY_REF_COST);
10703 // TODO: s390 port size(VARIABLE_SIZE);
10704 format %{ "STG $src,$mem\t # ST(packed8B)" %}
10705 opcode(STG_ZOPC, STG_ZOPC);
10706 ins_encode(z_form_rt_mem_opt(src, mem));
10707 ins_pipe(pipe_class_dummy);
10708 %}
10709
10710 // Load
10711
10712 instruct loadV8(iRegL dst, memory mem) %{
10713 match(Set dst (LoadVector mem));
10714 predicate(n->as_LoadVector()->memory_size() == 8);
10715 ins_cost(MEMORY_REF_COST);
10716 // TODO: s390 port size(VARIABLE_SIZE);
10717 format %{ "LG $dst,$mem\t # L(packed8B)" %}
10718 opcode(LG_ZOPC, LG_ZOPC);
10719 ins_encode(z_form_rt_mem_opt(dst, mem));
10720 ins_pipe(pipe_class_dummy);
10721 %}
10722
10723 //----------POPULATION COUNT RULES--------------------------------------------
10724
10725 // Byte reverse
10726
10727 instruct bytes_reverse_int(iRegI dst, iRegI src) %{
10728 match(Set dst (ReverseBytesI src));
10729 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
10730 ins_cost(DEFAULT_COST);
10731 size(4);
10732 format %{ "LRVR $dst,$src\t# byte reverse int" %}
10733 opcode(LRVR_ZOPC);
10734 ins_encode(z_rreform(dst, src));
10735 ins_pipe(pipe_class_dummy);
10736 %}
10737
10738 instruct bytes_reverse_long(iRegL dst, iRegL src) %{
10739 match(Set dst (ReverseBytesL src));
10740 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
10741 ins_cost(DEFAULT_COST);
10742 // TODO: s390 port size(FIXED_SIZE);
10743 format %{ "LRVGR $dst,$src\t# byte reverse long" %}
10744 opcode(LRVGR_ZOPC);
10745 ins_encode(z_rreform(dst, src));
10746 ins_pipe(pipe_class_dummy);
10747 %}
10748
10749 // Leading zeroes
10750
10751 // The instruction FLOGR (Find Leftmost One in Grande (64bit) Register)
10752 // returns the bit position of the leftmost 1 in the 64bit source register.
10753 // As the bits are numbered from left to right (0..63), the returned
10754 // position index is equivalent to the number of leading zeroes.
10755 // If no 1-bit is found (i.e. the regsiter contains zero), the instruction
10756 // returns position 64. That's exactly what we need.
10757
10758 instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
10759 match(Set dst (CountLeadingZerosI src));
10760 effect(KILL tmp, KILL cr);
10761 ins_cost(3 * DEFAULT_COST);
10762 size(14);
10763 format %{ "SLLG $dst,$src,32\t# no need to always count 32 zeroes first\n\t"
10764 "IILH $dst,0x8000 \t# insert \"stop bit\" to force result 32 for zero src.\n\t"
10765 "FLOGR $dst,$dst"
10766 %}
10767 ins_encode %{
10768 // Performance experiments indicate that "FLOGR" is using some kind of
10769 // iteration to find the leftmost "1" bit.
10770 //
10771 // The prior implementation zero-extended the 32-bit argument to 64 bit,
10772 // thus forcing "FLOGR" to count 32 bits of which we know they are zero.
10773 // We could gain measurable speedup in micro benchmark:
10774 //
10775 // leading trailing
10776 // z10: int 2.04 1.68
10777 // long 1.00 1.02
10778 // z196: int 0.99 1.23
10779 // long 1.00 1.11
10780 //
10781 // By shifting the argument into the high-word instead of zero-extending it.
10782 // The add'l branch on condition (taken for a zero argument, very infrequent,
10783 // good prediction) is well compensated for by the savings.
10784 //
10785 // We leave the previous implementation in for some time in the future when
10786 // the "FLOGR" instruction may become less iterative.
10787
10788 // Version 2: shows 62%(z9), 204%(z10), -1%(z196) improvement over original
10789 __ z_sllg($dst$$Register, $src$$Register, 32); // No need to always count 32 zeroes first.
10790 __ z_iilh($dst$$Register, 0x8000); // Insert "stop bit" to force result 32 for zero src.
10791 __ z_flogr($dst$$Register, $dst$$Register);
10792 %}
10793 ins_pipe(pipe_class_dummy);
10794 %}
10795
10796 instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{
10797 match(Set dst (CountLeadingZerosL src));
10798 effect(KILL tmp, KILL cr);
10799 ins_cost(DEFAULT_COST);
10800 size(4);
10801 format %{ "FLOGR $dst,$src \t# count leading zeros (long)\n\t" %}
10802 ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %}
10803 ins_pipe(pipe_class_dummy);
10804 %}
10805
10806 // trailing zeroes
10807
10808 // We transform the trailing zeroes problem to a leading zeroes problem
10809 // such that can use the FLOGR instruction to our advantage.
10810
10811 // With
10812 // tmp1 = src - 1
10813 // we flip all trailing zeroes to ones and the rightmost one to zero.
10814 // All other bits remain unchanged.
10815 // With the complement
10816 // tmp2 = ~src
10817 // we get all ones in the trailing zeroes positions. Thus,
10818 // tmp3 = tmp1 & tmp2
10819 // yields ones in the trailing zeroes positions and zeroes elsewhere.
10820 // Now we can apply FLOGR and get 64-(trailing zeroes).
10821 instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
10822 match(Set dst (CountTrailingZerosI src));
10823 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10824 ins_cost(8 * DEFAULT_COST);
10825 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off.
10826 format %{ "LLGFR $dst,$src \t# clear upper 32 bits (we are dealing with int)\n\t"
10827 "LCGFR $tmp,$src \t# load 2's complement (32->64 bit)\n\t"
10828 "AGHI $dst,-1 \t# tmp1 = src-1\n\t"
10829 "AGHI $tmp,-1 \t# tmp2 = -src-1 = ~src\n\t"
10830 "NGR $dst,$tmp \t# tmp3 = tmp1&tmp2\n\t"
10831 "FLOGR $dst,$dst \t# count trailing zeros (int)\n\t"
10832 "AHI $dst,-64 \t# tmp4 = 64-(trailing zeroes)-64\n\t"
10833 "LCR $dst,$dst \t# res = -tmp4"
10834 %}
10835 ins_encode %{
10836 Register Rdst = $dst$$Register;
10837 Register Rsrc = $src$$Register;
10838 // Rtmp only needed for for zero-argument shortcut. With kill effect in
10839 // match rule Rsrc = roddReg would be possible, saving one register.
10840 Register Rtmp = $tmp$$Register;
10841
10842 assert_different_registers(Rdst, Rsrc, Rtmp);
10843
10844 // Algorithm:
10845 // - Isolate the least significant (rightmost) set bit using (src & (-src)).
10846 // All other bits in the result are zero.
10847 // - Find the "leftmost one" bit position in the single-bit result from previous step.
10848 // - 63-("leftmost one" bit position) gives the # of trailing zeros.
10849
10850 // Version 2: shows 79%(z9), 68%(z10), 23%(z196) improvement over original.
10851 Label done;
10852 __ load_const_optimized(Rdst, 32); // Prepare for shortcut (zero argument), result will be 32.
10853 __ z_lcgfr(Rtmp, Rsrc);
10854 __ z_bre(done); // Taken very infrequently, good prediction, no BHT entry.
10855
10856 __ z_nr(Rtmp, Rsrc); // (src) & (-src) leaves nothing but least significant bit.
10857 __ z_ahi(Rtmp, -1); // Subtract one to fill all trailing zero positions with ones.
10858 // Use 32bit op to prevent borrow propagation (case Rdst = 0x80000000)
10859 // into upper half of reg. Not relevant with sllg below.
10860 __ z_sllg(Rdst, Rtmp, 32); // Shift interesting contents to upper half of register.
10861 __ z_bre(done); // Shortcut for argument = 1, result will be 0.
10862 // Depends on CC set by ahi above.
10863 // Taken very infrequently, good prediction, no BHT entry.
10864 // Branch delayed to have Rdst set correctly (Rtmp == 0(32bit)
10865 // after SLLG Rdst == 0(64bit)).
10866 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
10867 __ add2reg(Rdst, -32); // 32-pos(leftmost1) is #trailing zeros
10868 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
10869 __ bind(done);
10870 %}
10871 ins_pipe(pipe_class_dummy);
10872 %}
10873
10874 instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{
10875 match(Set dst (CountTrailingZerosL src));
10876 effect(TEMP_DEF dst, KILL tmp, KILL cr);
10877 ins_cost(8 * DEFAULT_COST);
10878 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off.
10879 format %{ "LCGR $dst,$src \t# preserve src\n\t"
10880 "NGR $dst,$src \t#"
10881 "AGHI $dst,-1 \t# tmp1 = src-1\n\t"
10882 "FLOGR $dst,$dst \t# count trailing zeros (long), kill $tmp\n\t"
10883 "AHI $dst,-64 \t# tmp4 = 64-(trailing zeroes)-64\n\t"
10884 "LCR $dst,$dst \t#"
10885 %}
10886 ins_encode %{
10887 Register Rdst = $dst$$Register;
10888 Register Rsrc = $src$$Register;
10889 assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed.
10890
10891 // New version: shows 5%(z9), 2%(z10), 11%(z196) improvement over original.
10892 __ z_lcgr(Rdst, Rsrc);
10893 __ z_ngr(Rdst, Rsrc);
10894 __ add2reg(Rdst, -1);
10895 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
10896 __ add2reg(Rdst, -64);
10897 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
10898 %}
10899 ins_pipe(pipe_class_dummy);
10900 %}
10901
10902
10903 // bit count
10904
10905 instruct popCountI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
10906 match(Set dst (PopCountI src));
10907 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10908 predicate(UsePopCountInstruction && VM_Version::has_PopCount());
10909 ins_cost(DEFAULT_COST);
10910 size(24);
10911 format %{ "POPCNT $dst,$src\t# pop count int" %}
10912 ins_encode %{
10913 Register Rdst = $dst$$Register;
10914 Register Rsrc = $src$$Register;
10915 Register Rtmp = $tmp$$Register;
10916
10917 // Prefer compile-time assertion over run-time SIGILL.
10918 assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI");
10919 assert_different_registers(Rdst, Rtmp);
10920
10921 // Version 2: shows 10%(z196) improvement over original.
10922 __ z_popcnt(Rdst, Rsrc);
10923 __ z_srlg(Rtmp, Rdst, 16); // calc byte4+byte6 and byte5+byte7
10924 __ z_alr(Rdst, Rtmp); // into byte6 and byte7
10925 __ z_srlg(Rtmp, Rdst, 8); // calc (byte4+byte6) + (byte5+byte7)
10926 __ z_alr(Rdst, Rtmp); // into byte7
10927 __ z_llgcr(Rdst, Rdst); // zero-extend sum
10928 %}
10929 ins_pipe(pipe_class_dummy);
10930 %}
10931
10932 instruct popCountL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
10933 match(Set dst (PopCountL src));
10934 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10935 predicate(UsePopCountInstruction && VM_Version::has_PopCount());
10936 ins_cost(DEFAULT_COST);
10937 // TODO: s390 port size(FIXED_SIZE);
10938 format %{ "POPCNT $dst,$src\t# pop count long" %}
10939 ins_encode %{
10940 Register Rdst = $dst$$Register;
10941 Register Rsrc = $src$$Register;
10942 Register Rtmp = $tmp$$Register;
10943
10944 // Prefer compile-time assertion over run-time SIGILL.
10945 assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI");
10946 assert_different_registers(Rdst, Rtmp);
10947
10948 // Original version. Using LA instead of algr seems to be a really bad idea (-35%).
10949 __ z_popcnt(Rdst, Rsrc);
10950 __ z_ahhlr(Rdst, Rdst, Rdst);
10951 __ z_sllg(Rtmp, Rdst, 16);
10952 __ z_algr(Rdst, Rtmp);
10953 __ z_sllg(Rtmp, Rdst, 8);
10954 __ z_algr(Rdst, Rtmp);
10955 __ z_srlg(Rdst, Rdst, 56);
10956 %}
10957 ins_pipe(pipe_class_dummy);
10958 %}
10959
10960 //----------SMARTSPILL RULES---------------------------------------------------
10961 // These must follow all instruction definitions as they use the names
10962 // defined in the instructions definitions.
10963
10964 // ============================================================================
10965 // TYPE PROFILING RULES
10966