1 // 2 // Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved. 3 // Copyright (c) 2016 SAP SE. All rights reserved. 4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 // 6 // This code is free software; you can redistribute it and/or modify it 7 // under the terms of the GNU General Public License version 2 only, as 8 // published by the Free Software Foundation. 9 // 10 // This code is distributed in the hope that it will be useful, but WITHOUT 11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 // version 2 for more details (a copy is included in the LICENSE file that 14 // accompanied this code). 15 // 16 // You should have received a copy of the GNU General Public License version 17 // 2 along with this work; if not, write to the Free Software Foundation, 18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 // 20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 // or visit www.oracle.com if you need additional information or have any 22 // questions. 23 // 24 25 // z/Architecture Architecture Description File 26 27 // Major contributions by AS, JL, LS. 28 29 // 30 // Following information is derived from private mail communication 31 // (Oct. 2011). 32 // 33 // General branch target alignment considerations 34 // 35 // z/Architecture does not imply a general branch target alignment requirement. 36 // There are side effects and side considerations, though, which may 37 // provide some performance benefit. These are: 38 // - Align branch target on octoword (32-byte) boundary 39 // On more recent models (from z9 on), I-fetch is done on a Octoword 40 // (32 bytes at a time) basis. To avoid I-fetching unnecessary 41 // instructions, branch targets should be 32-byte aligend. If this 42 // exact alingment cannot be achieved, having the branch target in 43 // the first doubleword still provides some benefit. 44 // - Avoid branch targets at the end of cache lines (> 64 bytes distance). 45 // Sequential instruction prefetching after the branch target starts 46 // immediately after having fetched the octoword containing the 47 // branch target. When I-fetching crosses a cache line, there may be 48 // a small stall. The worst case: the branch target (at the end of 49 // a cache line) is a L1 I-cache miss and the next line as well. 50 // Then, the entire target line must be filled first (to contine at the 51 // branch target). Only then can the next sequential line be filled. 52 // - Avoid multiple poorly predicted branches in a row. 53 // 54 55 //----------REGISTER DEFINITION BLOCK------------------------------------------ 56 // This information is used by the matcher and the register allocator to 57 // describe individual registers and classes of registers within the target 58 // architecture. 59 60 register %{ 61 62 //----------Architecture Description Register Definitions---------------------- 63 // General Registers 64 // "reg_def" name (register save type, C convention save type, 65 // ideal register type, encoding); 66 // 67 // Register Save Types: 68 // 69 // NS = No-Save: The register allocator assumes that these registers 70 // can be used without saving upon entry to the method, & 71 // that they do not need to be saved at call sites. 72 // 73 // SOC = Save-On-Call: The register allocator assumes that these registers 74 // can be used without saving upon entry to the method, 75 // but that they must be saved at call sites. 76 // 77 // SOE = Save-On-Entry: The register allocator assumes that these registers 78 // must be saved before using them upon entry to the 79 // method, but they do not need to be saved at call sites. 80 // 81 // AS = Always-Save: The register allocator assumes that these registers 82 // must be saved before using them upon entry to the 83 // method, & that they must be saved at call sites. 84 // 85 // Ideal Register Type is used to determine how to save & restore a 86 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 87 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 88 // 89 // The encoding number is the actual bit-pattern placed into the opcodes. 90 91 // z/Architecture register definitions, based on the z/Architecture Principles 92 // of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement, 93 // 5th Edition, March 2001. 94 // 95 // For each 64-bit register we must define two registers: the register 96 // itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half', 97 // e.g. Z_R3_H, which is needed by the allocator, but is not used 98 // for stores, loads, etc. 99 100 // Integer/Long Registers 101 // ---------------------------- 102 103 // z/Architecture has 16 64-bit integer registers. 104 105 // types: v = volatile, nv = non-volatile, s = system 106 reg_def Z_R0 (SOC, SOC, Op_RegI, 0, Z_R0->as_VMReg()); // v scratch1 107 reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next()); 108 reg_def Z_R1 (SOC, SOC, Op_RegI, 1, Z_R1->as_VMReg()); // v scratch2 109 reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next()); 110 reg_def Z_R2 (SOC, SOC, Op_RegI, 2, Z_R2->as_VMReg()); // v iarg1 & iret 111 reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next()); 112 reg_def Z_R3 (SOC, SOC, Op_RegI, 3, Z_R3->as_VMReg()); // v iarg2 113 reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next()); 114 reg_def Z_R4 (SOC, SOC, Op_RegI, 4, Z_R4->as_VMReg()); // v iarg3 115 reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next()); 116 reg_def Z_R5 (SOC, SOC, Op_RegI, 5, Z_R5->as_VMReg()); // v iarg4 117 reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next()); 118 reg_def Z_R6 (SOC, SOE, Op_RegI, 6, Z_R6->as_VMReg()); // v iarg5 119 reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next()); 120 reg_def Z_R7 (SOC, SOE, Op_RegI, 7, Z_R7->as_VMReg()); 121 reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next()); 122 reg_def Z_R8 (SOC, SOE, Op_RegI, 8, Z_R8->as_VMReg()); 123 reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next()); 124 reg_def Z_R9 (SOC, SOE, Op_RegI, 9, Z_R9->as_VMReg()); 125 reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next()); 126 reg_def Z_R10 (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg()); 127 reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next()); 128 reg_def Z_R11 (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg()); 129 reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next()); 130 reg_def Z_R12 (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg()); 131 reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next()); 132 reg_def Z_R13 (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg()); 133 reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next()); 134 reg_def Z_R14 (NS, NS, Op_RegI, 14, Z_R14->as_VMReg()); // s return_pc 135 reg_def Z_R14_H(NS, NS, Op_RegI, 99, Z_R14->as_VMReg()->next()); 136 reg_def Z_R15 (NS, NS, Op_RegI, 15, Z_R15->as_VMReg()); // s SP 137 reg_def Z_R15_H(NS, NS, Op_RegI, 99, Z_R15->as_VMReg()->next()); 138 139 // Float/Double Registers 140 141 // The rules of ADL require that double registers be defined in pairs. 142 // Each pair must be two 32-bit values, but not necessarily a pair of 143 // single float registers. In each pair, ADLC-assigned register numbers 144 // must be adjacent, with the lower number even. Finally, when the 145 // CPU stores such a register pair to memory, the word associated with 146 // the lower ADLC-assigned number must be stored to the lower address. 147 148 // z/Architecture has 16 64-bit floating-point registers. Each can store a single 149 // or double precision floating-point value. 150 151 // types: v = volatile, nv = non-volatile, s = system 152 reg_def Z_F0 (SOC, SOC, Op_RegF, 0, Z_F0->as_VMReg()); // v farg1 & fret 153 reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next()); 154 reg_def Z_F1 (SOC, SOC, Op_RegF, 1, Z_F1->as_VMReg()); 155 reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next()); 156 reg_def Z_F2 (SOC, SOC, Op_RegF, 2, Z_F2->as_VMReg()); // v farg2 157 reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next()); 158 reg_def Z_F3 (SOC, SOC, Op_RegF, 3, Z_F3->as_VMReg()); 159 reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next()); 160 reg_def Z_F4 (SOC, SOC, Op_RegF, 4, Z_F4->as_VMReg()); // v farg3 161 reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next()); 162 reg_def Z_F5 (SOC, SOC, Op_RegF, 5, Z_F5->as_VMReg()); 163 reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next()); 164 reg_def Z_F6 (SOC, SOC, Op_RegF, 6, Z_F6->as_VMReg()); 165 reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next()); 166 reg_def Z_F7 (SOC, SOC, Op_RegF, 7, Z_F7->as_VMReg()); 167 reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next()); 168 reg_def Z_F8 (SOC, SOE, Op_RegF, 8, Z_F8->as_VMReg()); 169 reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next()); 170 reg_def Z_F9 (SOC, SOE, Op_RegF, 9, Z_F9->as_VMReg()); 171 reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next()); 172 reg_def Z_F10 (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg()); 173 reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next()); 174 reg_def Z_F11 (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg()); 175 reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next()); 176 reg_def Z_F12 (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg()); 177 reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next()); 178 reg_def Z_F13 (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg()); 179 reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next()); 180 reg_def Z_F14 (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg()); 181 reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next()); 182 reg_def Z_F15 (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg()); 183 reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next()); 184 185 186 // Special Registers 187 188 // Condition Codes Flag Registers 189 190 // z/Architecture has the PSW (program status word) that contains 191 // (among other information) the condition code. We treat this 192 // part of the PSW as a condition register CR. It consists of 4 193 // bits. Floating point instructions influence the same condition register CR. 194 195 reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg()); // volatile 196 197 198 // Specify priority of register selection within phases of register 199 // allocation. Highest priority is first. A useful heuristic is to 200 // give registers a low priority when they are required by machine 201 // instructions, and choose no-save registers before save-on-call, and 202 // save-on-call before save-on-entry. Registers which participate in 203 // fix calling sequences should come last. Registers which are used 204 // as pairs must fall on an even boundary. 205 206 // It's worth about 1% on SPEC geomean to get this right. 207 208 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration 209 // in adGlobals_s390.hpp which defines the <register>_num values, e.g. 210 // Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not) 211 // the same as Z_R3->encoding()! Furthermore, we cannot make any 212 // assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num. 213 // Additionally, the function 214 // static enum RC rc_class(OptoReg::Name reg) 215 // maps a given <register>_num value to its chunk type (except for flags) 216 // and its current implementation relies on chunk0 and chunk1 having a 217 // size of 64 each. 218 219 alloc_class chunk0( 220 // chunk0 contains *all* 32 integer registers halves. 221 222 // potential SOE regs 223 Z_R13,Z_R13_H, 224 Z_R12,Z_R12_H, 225 Z_R11,Z_R11_H, 226 Z_R10,Z_R10_H, 227 228 Z_R9,Z_R9_H, 229 Z_R8,Z_R8_H, 230 Z_R7,Z_R7_H, 231 232 Z_R1,Z_R1_H, 233 Z_R0,Z_R0_H, 234 235 // argument registers 236 Z_R6,Z_R6_H, 237 Z_R5,Z_R5_H, 238 Z_R4,Z_R4_H, 239 Z_R3,Z_R3_H, 240 Z_R2,Z_R2_H, 241 242 // special registers 243 Z_R14,Z_R14_H, 244 Z_R15,Z_R15_H 245 ); 246 247 alloc_class chunk1( 248 // Chunk1 contains *all* 64 floating-point registers halves. 249 250 Z_F15,Z_F15_H, 251 Z_F14,Z_F14_H, 252 Z_F13,Z_F13_H, 253 Z_F12,Z_F12_H, 254 Z_F11,Z_F11_H, 255 Z_F10,Z_F10_H, 256 Z_F9,Z_F9_H, 257 Z_F8,Z_F8_H, 258 // scratch register 259 Z_F7,Z_F7_H, 260 Z_F5,Z_F5_H, 261 Z_F3,Z_F3_H, 262 Z_F1,Z_F1_H, 263 // argument registers 264 Z_F6,Z_F6_H, 265 Z_F4,Z_F4_H, 266 Z_F2,Z_F2_H, 267 Z_F0,Z_F0_H 268 ); 269 270 alloc_class chunk2( 271 Z_CR 272 ); 273 274 275 //-------Architecture Description Register Classes----------------------- 276 277 // Several register classes are automatically defined based upon 278 // information in this architecture description. 279 280 // 1) reg_class inline_cache_reg (as defined in frame section) 281 // 2) reg_class compiler_method_oop_reg (as defined in frame section) 282 // 2) reg_class interpreter_method_oop_reg (as defined in frame section) 283 // 3) reg_class stack_slots(/* one chunk of stack-based "registers" */) 284 285 // Integer Register Classes 286 reg_class z_int_reg( 287 /*Z_R0*/ // R0 288 /*Z_R1*/ 289 Z_R2, 290 Z_R3, 291 Z_R4, 292 Z_R5, 293 Z_R6, 294 Z_R7, 295 /*Z_R8,*/ // Z_thread 296 Z_R9, 297 Z_R10, 298 Z_R11, 299 Z_R12, 300 Z_R13 301 /*Z_R14*/ // return_pc 302 /*Z_R15*/ // SP 303 ); 304 305 reg_class z_no_odd_int_reg( 306 /*Z_R0*/ // R0 307 /*Z_R1*/ 308 Z_R2, 309 Z_R3, 310 Z_R4, 311 /*Z_R5,*/ // odd part of fix register pair 312 Z_R6, 313 Z_R7, 314 /*Z_R8,*/ // Z_thread 315 Z_R9, 316 Z_R10, 317 Z_R11, 318 Z_R12, 319 Z_R13 320 /*Z_R14*/ // return_pc 321 /*Z_R15*/ // SP 322 ); 323 324 reg_class z_no_arg_int_reg( 325 /*Z_R0*/ // R0 326 /*Z_R1*/ // scratch 327 /*Z_R2*/ 328 /*Z_R3*/ 329 /*Z_R4*/ 330 /*Z_R5*/ 331 /*Z_R6*/ 332 Z_R7, 333 /*Z_R8*/ // Z_thread 334 Z_R9, 335 Z_R10, 336 Z_R11, 337 Z_R12, 338 Z_R13 339 /*Z_R14*/ // return_pc 340 /*Z_R15*/ // SP 341 ); 342 343 reg_class z_rarg1_int_reg(Z_R2); 344 reg_class z_rarg2_int_reg(Z_R3); 345 reg_class z_rarg3_int_reg(Z_R4); 346 reg_class z_rarg4_int_reg(Z_R5); 347 reg_class z_rarg5_int_reg(Z_R6); 348 349 // Pointer Register Classes 350 351 // 64-bit build means 64-bit pointers means hi/lo pairs. 352 353 reg_class z_rarg5_ptrN_reg(Z_R6); 354 355 reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2); 356 reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3); 357 reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4); 358 reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5); 359 reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6); 360 reg_class z_thread_ptr_reg(Z_R8_H,Z_R8); 361 362 reg_class z_ptr_reg( 363 /*Z_R0_H,Z_R0*/ // R0 364 /*Z_R1_H,Z_R1*/ 365 Z_R2_H,Z_R2, 366 Z_R3_H,Z_R3, 367 Z_R4_H,Z_R4, 368 Z_R5_H,Z_R5, 369 Z_R6_H,Z_R6, 370 Z_R7_H,Z_R7, 371 /*Z_R8_H,Z_R8,*/ // Z_thread 372 Z_R9_H,Z_R9, 373 Z_R10_H,Z_R10, 374 Z_R11_H,Z_R11, 375 Z_R12_H,Z_R12, 376 Z_R13_H,Z_R13 377 /*Z_R14_H,Z_R14*/ // return_pc 378 /*Z_R15_H,Z_R15*/ // SP 379 ); 380 381 reg_class z_lock_ptr_reg( 382 /*Z_R0_H,Z_R0*/ // R0 383 /*Z_R1_H,Z_R1*/ 384 Z_R2_H,Z_R2, 385 Z_R3_H,Z_R3, 386 Z_R4_H,Z_R4, 387 /*Z_R5_H,Z_R5,*/ 388 /*Z_R6_H,Z_R6,*/ 389 Z_R7_H,Z_R7, 390 /*Z_R8_H,Z_R8,*/ // Z_thread 391 Z_R9_H,Z_R9, 392 Z_R10_H,Z_R10, 393 Z_R11_H,Z_R11, 394 Z_R12_H,Z_R12, 395 Z_R13_H,Z_R13 396 /*Z_R14_H,Z_R14*/ // return_pc 397 /*Z_R15_H,Z_R15*/ // SP 398 ); 399 400 reg_class z_no_arg_ptr_reg( 401 /*Z_R0_H,Z_R0*/ // R0 402 /*Z_R1_H,Z_R1*/ // scratch 403 /*Z_R2_H,Z_R2*/ 404 /*Z_R3_H,Z_R3*/ 405 /*Z_R4_H,Z_R4*/ 406 /*Z_R5_H,Z_R5*/ 407 /*Z_R6_H,Z_R6*/ 408 Z_R7_H, Z_R7, 409 /*Z_R8_H,Z_R8*/ // Z_thread 410 Z_R9_H,Z_R9, 411 Z_R10_H,Z_R10, 412 Z_R11_H,Z_R11, 413 Z_R12_H,Z_R12, 414 Z_R13_H,Z_R13 415 /*Z_R14_H,Z_R14*/ // return_pc 416 /*Z_R15_H,Z_R15*/ // SP 417 ); 418 419 // Special class for storeP instructions, which can store SP or RPC to 420 // TLS. (Note: Do not generalize this to "any_reg". If you add 421 // another register, such as FP, to this mask, the allocator may try 422 // to put a temp in it.) 423 // Register class for memory access base registers, 424 // This class is a superset of z_ptr_reg including Z_thread. 425 reg_class z_memory_ptr_reg( 426 /*Z_R0_H,Z_R0*/ // R0 427 /*Z_R1_H,Z_R1*/ 428 Z_R2_H,Z_R2, 429 Z_R3_H,Z_R3, 430 Z_R4_H,Z_R4, 431 Z_R5_H,Z_R5, 432 Z_R6_H,Z_R6, 433 Z_R7_H,Z_R7, 434 Z_R8_H,Z_R8, // Z_thread 435 Z_R9_H,Z_R9, 436 Z_R10_H,Z_R10, 437 Z_R11_H,Z_R11, 438 Z_R12_H,Z_R12, 439 Z_R13_H,Z_R13 440 /*Z_R14_H,Z_R14*/ // return_pc 441 /*Z_R15_H,Z_R15*/ // SP 442 ); 443 444 // Other special pointer regs. 445 reg_class z_r1_regP(Z_R1_H,Z_R1); 446 reg_class z_r9_regP(Z_R9_H,Z_R9); 447 448 449 // Long Register Classes 450 451 reg_class z_rarg1_long_reg(Z_R2_H,Z_R2); 452 reg_class z_rarg2_long_reg(Z_R3_H,Z_R3); 453 reg_class z_rarg3_long_reg(Z_R4_H,Z_R4); 454 reg_class z_rarg4_long_reg(Z_R5_H,Z_R5); 455 reg_class z_rarg5_long_reg(Z_R6_H,Z_R6); 456 457 // Longs in 1 register. Aligned adjacent hi/lo pairs. 458 reg_class z_long_reg( 459 /*Z_R0_H,Z_R0*/ // R0 460 /*Z_R1_H,Z_R1*/ 461 Z_R2_H,Z_R2, 462 Z_R3_H,Z_R3, 463 Z_R4_H,Z_R4, 464 Z_R5_H,Z_R5, 465 Z_R6_H,Z_R6, 466 Z_R7_H,Z_R7, 467 /*Z_R8_H,Z_R8,*/ // Z_thread 468 Z_R9_H,Z_R9, 469 Z_R10_H,Z_R10, 470 Z_R11_H,Z_R11, 471 Z_R12_H,Z_R12, 472 Z_R13_H,Z_R13 473 /*Z_R14_H,Z_R14,*/ // return_pc 474 /*Z_R15_H,Z_R15*/ // SP 475 ); 476 477 478 // Special Class for Condition Code Flags Register 479 480 reg_class z_condition_reg( 481 Z_CR 482 ); 483 484 // Scratch register for late profiling. Callee saved. 485 reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2); 486 487 488 // Float Register Classes 489 490 reg_class z_flt_reg( 491 Z_F0, 492 /*Z_F1,*/ // scratch 493 Z_F2, 494 Z_F3, 495 Z_F4, 496 Z_F5, 497 Z_F6, 498 Z_F7, 499 Z_F8, 500 Z_F9, 501 Z_F10, 502 Z_F11, 503 Z_F12, 504 Z_F13, 505 Z_F14, 506 Z_F15 507 ); 508 reg_class z_rscratch1_flt_reg(Z_F1); 509 510 // Double precision float registers have virtual `high halves' that 511 // are needed by the allocator. 512 reg_class z_dbl_reg( 513 Z_F0,Z_F0_H, 514 /*Z_F1,Z_F1_H,*/ // scratch 515 Z_F2,Z_F2_H, 516 Z_F3,Z_F3_H, 517 Z_F4,Z_F4_H, 518 Z_F5,Z_F5_H, 519 Z_F6,Z_F6_H, 520 Z_F7,Z_F7_H, 521 Z_F8,Z_F8_H, 522 Z_F9,Z_F9_H, 523 Z_F10,Z_F10_H, 524 Z_F11,Z_F11_H, 525 Z_F12,Z_F12_H, 526 Z_F13,Z_F13_H, 527 Z_F14,Z_F14_H, 528 Z_F15,Z_F15_H 529 ); 530 reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H); 531 532 %} 533 534 //----------DEFINITION BLOCK--------------------------------------------------- 535 // Define 'name --> value' mappings to inform the ADLC of an integer valued name. 536 // Current support includes integer values in the range [0, 0x7FFFFFFF]. 537 // Format: 538 // int_def <name> (<int_value>, <expression>); 539 // Generated Code in ad_<arch>.hpp 540 // #define <name> (<expression>) 541 // // value == <int_value> 542 // Generated code in ad_<arch>.cpp adlc_verification() 543 // assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 544 // 545 definitions %{ 546 // The default cost (of an ALU instruction). 547 int_def DEFAULT_COST ( 100, 100); 548 int_def DEFAULT_COST_LOW ( 80, 80); 549 int_def DEFAULT_COST_HIGH ( 120, 120); 550 int_def HUGE_COST (1000000, 1000000); 551 552 // Put an advantage on REG_MEM vs. MEM+REG_REG operations. 553 int_def ALU_REG_COST ( 100, DEFAULT_COST); 554 int_def ALU_MEMORY_COST ( 150, 150); 555 556 // Memory refs are twice as expensive as run-of-the-mill. 557 int_def MEMORY_REF_COST_HI ( 220, 2 * DEFAULT_COST+20); 558 int_def MEMORY_REF_COST ( 200, 2 * DEFAULT_COST); 559 int_def MEMORY_REF_COST_LO ( 180, 2 * DEFAULT_COST-20); 560 561 // Branches are even more expensive. 562 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 563 int_def CALL_COST ( 300, DEFAULT_COST * 3); 564 %} 565 566 source %{ 567 568 #ifdef PRODUCT 569 #define BLOCK_COMMENT(str) 570 #define BIND(label) __ bind(label) 571 #else 572 #define BLOCK_COMMENT(str) __ block_comment(str) 573 #define BIND(label) __ bind(label); BLOCK_COMMENT(#label ":") 574 #endif 575 576 #define __ _masm. 577 578 #define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ? 4 : 6 579 #define Z_DISP3_SIZE 6 580 581 // Tertiary op of a LoadP or StoreP encoding. 582 #define REGP_OP true 583 584 // Given a register encoding, produce an Integer Register object. 585 static Register reg_to_register_object(int register_encoding); 586 587 // **************************************************************************** 588 589 // REQUIRED FUNCTIONALITY 590 591 // !!!!! Special hack to get all type of calls to specify the byte offset 592 // from the start of the call to the point where the return address 593 // will point. 594 595 int MachCallStaticJavaNode::ret_addr_offset() { 596 if (_method) { 597 return 8; 598 } else { 599 return MacroAssembler::call_far_patchable_ret_addr_offset(); 600 } 601 } 602 603 int MachCallDynamicJavaNode::ret_addr_offset() { 604 // Consider size of receiver type profiling (C2 tiers). 605 int profile_receiver_type_size = 0; 606 607 int vtable_index = this->_vtable_index; 608 if (vtable_index == -4) { 609 return 14 + profile_receiver_type_size; 610 } else { 611 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 612 return 36 + profile_receiver_type_size; 613 } 614 } 615 616 int MachCallRuntimeNode::ret_addr_offset() { 617 return 12 + MacroAssembler::call_far_patchable_ret_addr_offset(); 618 } 619 620 // Compute padding required for nodes which need alignment 621 // 622 // The addresses of the call instructions needs to be 4-byte aligned to 623 // ensure that they don't span a cache line so that they are atomically patchable. 624 // The actual calls get emitted at different offsets within the node emitters. 625 // ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted. 626 627 int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const { 628 return (0 - current_offset) & 2; 629 } 630 631 int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const { 632 return (6 - current_offset) & 2; 633 } 634 635 int CallRuntimeDirectNode::compute_padding(int current_offset) const { 636 return (12 - current_offset) & 2; 637 } 638 639 int CallLeafDirectNode::compute_padding(int current_offset) const { 640 return (12 - current_offset) & 2; 641 } 642 643 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const { 644 return (12 - current_offset) & 2; 645 } 646 647 // Indicate if the safepoint node needs the polling page as an input. 648 // Since z/Architecture does not have absolute addressing, it does. 649 bool SafePointNode::needs_polling_address_input() { 650 return true; 651 } 652 653 void emit_nop(CodeBuffer &cbuf) { 654 MacroAssembler _masm(&cbuf); 655 __ z_nop(); 656 } 657 658 // Emit an interrupt that is caught by the debugger (for debugging compiler). 659 void emit_break(CodeBuffer &cbuf) { 660 MacroAssembler _masm(&cbuf); 661 __ z_illtrap(); 662 } 663 664 #if !defined(PRODUCT) 665 void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const { 666 os->print("TA"); 667 } 668 #endif 669 670 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 671 emit_break(cbuf); 672 } 673 674 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 675 return MachNode::size(ra_); 676 } 677 678 static inline void z_emit16(CodeBuffer &cbuf, long value) { 679 // 32bit instructions may become sign extended. 680 assert(value >= 0, "unintended sign extension (int->long)"); 681 assert(value < (1L << 16), "instruction too large"); 682 *((unsigned short*)(cbuf.insts_end())) = (unsigned short)value; 683 cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned short)); 684 } 685 686 static inline void z_emit32(CodeBuffer &cbuf, long value) { 687 // 32bit instructions may become sign extended. 688 assert(value < (1L << 32), "instruction too large"); 689 *((unsigned int*)(cbuf.insts_end())) = (unsigned int)value; 690 cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned int)); 691 } 692 693 static inline void z_emit48(CodeBuffer &cbuf, long value) { 694 // 32bit instructions may become sign extended. 695 assert(value >= 0, "unintended sign extension (int->long)"); 696 assert(value < (1L << 48), "instruction too large"); 697 value = value<<16; 698 memcpy(cbuf.insts_end(), (unsigned char*)&value, 6); 699 cbuf.set_insts_end(cbuf.insts_end() + 6); 700 } 701 702 static inline unsigned int z_emit_inst(CodeBuffer &cbuf, long value) { 703 if (value < 0) { 704 // There obviously has been an unintended sign extension (int->long). Revert it. 705 value = (long)((unsigned long)((unsigned int)value)); 706 } 707 708 if (value < (1L << 16)) { // 2-byte instruction 709 z_emit16(cbuf, value); 710 return 2; 711 } 712 713 if (value < (1L << 32)) { // 4-byte instruction, might be unaligned store 714 z_emit32(cbuf, value); 715 return 4; 716 } 717 718 // 6-byte instruction, probably unaligned store. 719 z_emit48(cbuf, value); 720 return 6; 721 } 722 723 // Check effective address (at runtime) for required alignment. 724 static inline void z_assert_aligned(CodeBuffer &cbuf, int disp, Register index, Register base, int alignment) { 725 MacroAssembler _masm(&cbuf); 726 727 __ z_lay(Z_R0, disp, index, base); 728 __ z_nill(Z_R0, alignment-1); 729 __ z_brc(Assembler::bcondEqual, +3); 730 __ z_illtrap(); 731 } 732 733 int emit_call_reloc(MacroAssembler &_masm, intptr_t entry_point, relocInfo::relocType rtype, 734 PhaseRegAlloc* ra_, bool is_native_call = false) { 735 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp(). 736 address old_mark = __ inst_mark(); 737 unsigned int start_off = __ offset(); 738 739 if (is_native_call) { 740 ShouldNotReachHere(); 741 } 742 743 if (rtype == relocInfo::runtime_call_w_cp_type) { 744 assert((__ offset() & 2) == 0, "misaligned emit_call_reloc"); 745 address call_addr = __ call_c_opt((address)entry_point); 746 if (call_addr == NULL) { 747 Compile::current()->env()->record_out_of_memory_failure(); 748 return -1; 749 } 750 } else { 751 assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type || 752 rtype == relocInfo::static_call_type, "unexpected rtype"); 753 __ relocate(rtype); 754 // BRASL must be prepended with a nop to identify it in the instruction stream. 755 __ z_nop(); 756 __ z_brasl(Z_R14, (address)entry_point); 757 } 758 759 unsigned int ret_off = __ offset(); 760 761 return (ret_off - start_off); 762 } 763 764 static int emit_call_reloc(MacroAssembler &_masm, intptr_t entry_point, RelocationHolder const& rspec) { 765 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp(). 766 address old_mark = __ inst_mark(); 767 unsigned int start_off = __ offset(); 768 769 relocInfo::relocType rtype = rspec.type(); 770 assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type, 771 "unexpected rtype"); 772 773 __ relocate(rspec); 774 __ z_nop(); 775 __ z_brasl(Z_R14, (address)entry_point); 776 777 unsigned int ret_off = __ offset(); 778 779 return (ret_off - start_off); 780 } 781 782 //============================================================================= 783 784 const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask; 785 int Compile::ConstantTable::calculate_table_base_offset() const { 786 return 0; // absolute addressing, no offset 787 } 788 789 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } 790 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 791 ShouldNotReachHere(); 792 } 793 794 // Even with PC-relative TOC addressing, we still need this node. 795 // Float loads/stores do not support PC-relative addresses. 796 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 797 MacroAssembler _masm(&cbuf); 798 Register Rtoc = as_Register(ra_->get_encode(this)); 799 __ load_toc(Rtoc); 800 } 801 802 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { 803 // PCrelative TOC access. 804 return 6; // sizeof(LARL) 805 } 806 807 #if !defined(PRODUCT) 808 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 809 Register r = as_Register(ra_->get_encode(this)); 810 st->print("LARL %s,&constant_pool # MachConstantBaseNode", r->name()); 811 } 812 #endif 813 814 //============================================================================= 815 816 #if !defined(PRODUCT) 817 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 818 Compile* C = ra_->C; 819 st->print_cr("--- MachPrologNode ---"); 820 st->print("\t"); 821 for (int i = 0; i < OptoPrologueNops; i++) { 822 st->print_cr("NOP"); st->print("\t"); 823 } 824 825 if (VerifyThread) { 826 st->print_cr("Verify_Thread"); 827 st->print("\t"); 828 } 829 830 long framesize = C->frame_size_in_bytes(); 831 int bangsize = C->bang_size_in_bytes(); 832 833 // Calls to C2R adapters often do not accept exceptional returns. 834 // We require that their callers must bang for them. But be 835 // careful, because some VM calls (such as call site linkage) can 836 // use several kilobytes of stack. But the stack safety zone should 837 // account for that. See bugs 4446381, 4468289, 4497237. 838 if (C->need_stack_bang(bangsize) && UseStackBanging) { 839 st->print_cr("# stack bang"); st->print("\t"); 840 } 841 st->print_cr("push_frame %d", (int)-framesize); 842 st->print("\t"); 843 } 844 #endif 845 846 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 847 Compile* C = ra_->C; 848 MacroAssembler _masm(&cbuf); 849 850 __ verify_thread(); 851 852 size_t framesize = C->frame_size_in_bytes(); 853 size_t bangsize = C->bang_size_in_bytes(); 854 855 assert(framesize % wordSize == 0, "must preserve wordSize alignment"); 856 857 // Calls to C2R adapters often do not accept exceptional returns. 858 // We require that their callers must bang for them. But be 859 // careful, because some VM calls (such as call site linkage) can 860 // use several kilobytes of stack. But the stack safety zone should 861 // account for that. See bugs 4446381, 4468289, 4497237. 862 if (C->need_stack_bang(bangsize) && UseStackBanging) { 863 __ generate_stack_overflow_check(bangsize); 864 } 865 866 assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!"); 867 __ save_return_pc(); 868 869 // The z/Architecture abi is already accounted for in `framesize' via the 870 // 'out_preserve_stack_slots' declaration. 871 __ push_frame((unsigned int)framesize/*includes JIT ABI*/); 872 873 if (C->has_mach_constant_base_node()) { 874 // NOTE: We set the table base offset here because users might be 875 // emitted before MachConstantBaseNode. 876 Compile::ConstantTable& constant_table = C->constant_table(); 877 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); 878 } 879 } 880 881 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 882 // Variable size. Determine dynamically. 883 return MachNode::size(ra_); 884 } 885 886 int MachPrologNode::reloc() const { 887 // Return number of relocatable values contained in this instruction. 888 return 1; // One reloc entry for load_const(toc). 889 } 890 891 //============================================================================= 892 893 #if !defined(PRODUCT) 894 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const { 895 os->print_cr("epilog"); 896 os->print("\t"); 897 if (do_polling() && ra_->C->is_method_compilation()) { 898 os->print_cr("load_from_polling_page Z_R1_scratch"); 899 os->print("\t"); 900 } 901 } 902 #endif 903 904 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 905 MacroAssembler _masm(&cbuf); 906 Compile* C = ra_->C; 907 __ verify_thread(); 908 909 // If this does safepoint polling, then do it here. 910 bool need_polling = do_polling() && C->is_method_compilation(); 911 912 // Pop frame, restore return_pc, and all stuff needed by interpreter. 913 // Pop frame by add instead of load (a penny saved is a penny got :-). 914 int frame_size_in_bytes = Assembler::align((C->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes); 915 int retPC_offset = frame_size_in_bytes + _z_abi16(return_pc); 916 if (Displacement::is_validDisp(retPC_offset)) { 917 __ z_lg(Z_R14, retPC_offset, Z_SP); 918 __ add2reg(Z_SP, frame_size_in_bytes); 919 } else { 920 __ add2reg(Z_SP, frame_size_in_bytes); 921 __ restore_return_pc(); 922 } 923 924 if (StackReservedPages > 0 && C->has_reserved_stack_access()) { 925 __ reserved_stack_check(Z_R14); 926 } 927 928 // Touch the polling page. 929 if (need_polling) { 930 AddressLiteral pp(os::get_polling_page()); 931 __ load_const_optimized(Z_R1_scratch, pp); 932 // We need to mark the code position where the load from the safepoint 933 // polling page was emitted as relocInfo::poll_return_type here. 934 __ relocate(relocInfo::poll_return_type); 935 __ load_from_polling_page(Z_R1_scratch); 936 } 937 } 938 939 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 940 // Variable size. determine dynamically. 941 return MachNode::size(ra_); 942 } 943 944 int MachEpilogNode::reloc() const { 945 // Return number of relocatable values contained in this instruction. 946 return 1; // One for load_from_polling_page. 947 } 948 949 const Pipeline * MachEpilogNode::pipeline() const { 950 return MachNode::pipeline_class(); 951 } 952 953 int MachEpilogNode::safepoint_offset() const { 954 assert(do_polling(), "no return for this epilog node"); 955 return 0; 956 } 957 958 //============================================================================= 959 960 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack. 961 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 962 963 static enum RC rc_class(OptoReg::Name reg) { 964 // Return the register class for the given register. The given register 965 // reg is a <register>_num value, which is an index into the MachRegisterNumbers 966 // enumeration in adGlobals_s390.hpp. 967 968 if (reg == OptoReg::Bad) { 969 return rc_bad; 970 } 971 972 // We have 32 integer register halves, starting at index 0. 973 if (reg < 32) { 974 return rc_int; 975 } 976 977 // We have 32 floating-point register halves, starting at index 32. 978 if (reg < 32+32) { 979 return rc_float; 980 } 981 982 // Between float regs & stack are the flags regs. 983 assert(reg >= OptoReg::stack0(), "blow up if spilling flags"); 984 return rc_stack; 985 } 986 987 // Returns size as obtained from z_emit_instr. 988 static unsigned int z_ld_st_helper(CodeBuffer *cbuf, const char *op_str, unsigned long opcode, 989 int reg, int offset, bool do_print, outputStream *os) { 990 991 if (cbuf) { 992 if (opcode > (1L<<32)) { 993 return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 48) | 994 Assembler::simm20(offset) | Assembler::reg(Z_R0, 12, 48) | Assembler::regz(Z_SP, 16, 48)); 995 } else { 996 return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 32) | 997 Assembler::uimm12(offset, 20, 32) | Assembler::reg(Z_R0, 12, 32) | Assembler::regz(Z_SP, 16, 32)); 998 } 999 } 1000 1001 #if !defined(PRODUCT) 1002 if (do_print) { 1003 os->print("%s %s,#%d[,SP]\t # MachCopy spill code",op_str, Matcher::regName[reg], offset); 1004 } 1005 #endif 1006 return (opcode > (1L << 32)) ? 6 : 4; 1007 } 1008 1009 static unsigned int z_mvc_helper(CodeBuffer *cbuf, int len, int dst_off, int src_off, bool do_print, outputStream *os) { 1010 if (cbuf) { 1011 MacroAssembler _masm(cbuf); 1012 __ z_mvc(dst_off, len-1, Z_SP, src_off, Z_SP); 1013 } 1014 1015 #if !defined(PRODUCT) 1016 else if (do_print) { 1017 os->print("MVC %d(%d,SP),%d(SP)\t # MachCopy spill code",dst_off, len, src_off); 1018 } 1019 #endif 1020 1021 return 6; 1022 } 1023 1024 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *os) const { 1025 // Get registers to move. 1026 OptoReg::Name src_hi = ra_->get_reg_second(in(1)); 1027 OptoReg::Name src_lo = ra_->get_reg_first(in(1)); 1028 OptoReg::Name dst_hi = ra_->get_reg_second(this); 1029 OptoReg::Name dst_lo = ra_->get_reg_first(this); 1030 1031 enum RC src_hi_rc = rc_class(src_hi); 1032 enum RC src_lo_rc = rc_class(src_lo); 1033 enum RC dst_hi_rc = rc_class(dst_hi); 1034 enum RC dst_lo_rc = rc_class(dst_lo); 1035 1036 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register"); 1037 bool is64 = (src_hi_rc != rc_bad); 1038 assert(!is64 || 1039 ((src_lo&1) == 0 && src_lo+1 == src_hi && (dst_lo&1) == 0 && dst_lo+1 == dst_hi), 1040 "expected aligned-adjacent pairs"); 1041 1042 // Generate spill code! 1043 1044 if (src_lo == dst_lo && src_hi == dst_hi) { 1045 return 0; // Self copy, no move. 1046 } 1047 1048 int src_offset = ra_->reg2offset(src_lo); 1049 int dst_offset = ra_->reg2offset(dst_lo); 1050 bool print = !do_size; 1051 bool src12 = Immediate::is_uimm12(src_offset); 1052 bool dst12 = Immediate::is_uimm12(dst_offset); 1053 1054 const char *mnemo = NULL; 1055 unsigned long opc = 0; 1056 1057 // Memory->Memory Spill. Use Z_R0 to hold the value. 1058 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1059 1060 assert(!is64 || (src_hi_rc==rc_stack && dst_hi_rc==rc_stack), 1061 "expected same type of move for high parts"); 1062 1063 if (src12 && dst12) { 1064 return z_mvc_helper(cbuf, is64 ? 8 : 4, dst_offset, src_offset, print, os); 1065 } 1066 1067 int r0 = Z_R0_num; 1068 if (is64) { 1069 return z_ld_st_helper(cbuf, "LG ", LG_ZOPC, r0, src_offset, print, os) + 1070 z_ld_st_helper(cbuf, "STG ", STG_ZOPC, r0, dst_offset, print, os); 1071 } 1072 1073 return z_ld_st_helper(cbuf, "LY ", LY_ZOPC, r0, src_offset, print, os) + 1074 z_ld_st_helper(cbuf, "STY ", STY_ZOPC, r0, dst_offset, print, os); 1075 } 1076 1077 // Check for float->int copy. Requires a trip through memory. 1078 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1079 Unimplemented(); // Unsafe, do not remove! 1080 } 1081 1082 // Check for integer reg-reg copy. 1083 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1084 if (cbuf) { 1085 MacroAssembler _masm(cbuf); 1086 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1087 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1088 __ z_lgr(Rdst, Rsrc); 1089 return 4; 1090 } 1091 #if !defined(PRODUCT) 1092 // else 1093 if (print) { 1094 os->print("LGR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1095 } 1096 #endif 1097 return 4; 1098 } 1099 1100 // Check for integer store. 1101 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1102 assert(!is64 || (src_hi_rc==rc_int && dst_hi_rc==rc_stack), 1103 "expected same type of move for high parts"); 1104 1105 if (is64) { 1106 return z_ld_st_helper(cbuf, "STG ", STG_ZOPC, src_lo, dst_offset, print, os); 1107 } 1108 1109 // else 1110 mnemo = dst12 ? "ST " : "STY "; 1111 opc = dst12 ? ST_ZOPC : STY_ZOPC; 1112 1113 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os); 1114 } 1115 1116 // Check for integer load 1117 // Always load cOops zero-extended. That doesn't hurt int loads. 1118 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1119 1120 assert(!is64 || (dst_hi_rc==rc_int && src_hi_rc==rc_stack), 1121 "expected same type of move for high parts"); 1122 1123 mnemo = is64 ? "LG " : "LLGF"; 1124 opc = is64 ? LG_ZOPC : LLGF_ZOPC; 1125 1126 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os); 1127 } 1128 1129 // Check for float reg-reg copy. 1130 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1131 if (cbuf) { 1132 MacroAssembler _masm(cbuf); 1133 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]); 1134 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]); 1135 __ z_ldr(Rdst, Rsrc); 1136 return 2; 1137 } 1138 #if !defined(PRODUCT) 1139 // else 1140 if (print) { 1141 os->print("LDR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1142 } 1143 #endif 1144 return 2; 1145 } 1146 1147 // Check for float store. 1148 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1149 assert(!is64 || (src_hi_rc==rc_float && dst_hi_rc==rc_stack), 1150 "expected same type of move for high parts"); 1151 1152 if (is64) { 1153 mnemo = dst12 ? "STD " : "STDY "; 1154 opc = dst12 ? STD_ZOPC : STDY_ZOPC; 1155 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os); 1156 } 1157 // else 1158 1159 mnemo = dst12 ? "STE " : "STEY "; 1160 opc = dst12 ? STE_ZOPC : STEY_ZOPC; 1161 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os); 1162 } 1163 1164 // Check for float load. 1165 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1166 assert(!is64 || (dst_hi_rc==rc_float && src_hi_rc==rc_stack), 1167 "expected same type of move for high parts"); 1168 1169 if (is64) { 1170 mnemo = src12 ? "LD " : "LDY "; 1171 opc = src12 ? LD_ZOPC : LDY_ZOPC; 1172 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os); 1173 } 1174 // else 1175 1176 mnemo = src12 ? "LE " : "LEY "; 1177 opc = src12 ? LE_ZOPC : LEY_ZOPC; 1178 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os); 1179 } 1180 1181 // -------------------------------------------------------------------- 1182 // Check for hi bits still needing moving. Only happens for misaligned 1183 // arguments to native calls. 1184 if (src_hi == dst_hi) { 1185 return 0; // Self copy, no move. 1186 } 1187 1188 assert(is64 && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad"); 1189 Unimplemented(); // Unsafe, do not remove! 1190 1191 return 0; // never reached, but make the compiler shut up! 1192 } 1193 1194 #if !defined(PRODUCT) 1195 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *os) const { 1196 if (ra_ && ra_->node_regs_max_index() > 0) { 1197 implementation(NULL, ra_, false, os); 1198 } else { 1199 if (req() == 2 && in(1)) { 1200 os->print("N%d = N%d\n", _idx, in(1)->_idx); 1201 } else { 1202 const char *c = "("; 1203 os->print("N%d = ", _idx); 1204 for (uint i = 1; i < req(); ++i) { 1205 os->print("%sN%d", c, in(i)->_idx); 1206 c = ", "; 1207 } 1208 os->print(")"); 1209 } 1210 } 1211 } 1212 #endif 1213 1214 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1215 implementation(&cbuf, ra_, false, NULL); 1216 } 1217 1218 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1219 return implementation(NULL, ra_, true, NULL); 1220 } 1221 1222 //============================================================================= 1223 1224 #if !defined(PRODUCT) 1225 void MachNopNode::format(PhaseRegAlloc *, outputStream *os) const { 1226 os->print("NOP # pad for alignment (%d nops, %d bytes)", _count, _count*MacroAssembler::nop_size()); 1227 } 1228 #endif 1229 1230 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ra_) const { 1231 MacroAssembler _masm(&cbuf); 1232 1233 int rem_space = 0; 1234 if (!(ra_->C->in_scratch_emit_size())) { 1235 rem_space = cbuf.insts()->remaining(); 1236 if (rem_space <= _count*2 + 8) { 1237 tty->print("NopNode: _count = %3.3d, remaining space before = %d", _count, rem_space); 1238 } 1239 } 1240 1241 for (int i = 0; i < _count; i++) { 1242 __ z_nop(); 1243 } 1244 1245 if (!(ra_->C->in_scratch_emit_size())) { 1246 if (rem_space <= _count*2 + 8) { 1247 int rem_space2 = cbuf.insts()->remaining(); 1248 tty->print_cr(", after = %d", rem_space2); 1249 } 1250 } 1251 } 1252 1253 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1254 return 2 * _count; 1255 } 1256 1257 #if !defined(PRODUCT) 1258 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *os) const { 1259 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1260 if (ra_ && ra_->node_regs_max_index() > 0) { 1261 int reg = ra_->get_reg_first(this); 1262 os->print("ADDHI %s, SP, %d\t//box node", Matcher::regName[reg], offset); 1263 } else { 1264 os->print("ADDHI N%d = SP + %d\t// box node", _idx, offset); 1265 } 1266 } 1267 #endif 1268 1269 // Take care of the size function, if you make changes here! 1270 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1271 MacroAssembler _masm(&cbuf); 1272 1273 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1274 int reg = ra_->get_encode(this); 1275 __ z_lay(as_Register(reg), offset, Z_SP); 1276 } 1277 1278 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1279 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1280 return 6; 1281 } 1282 1283 %} // end source section 1284 1285 //----------SOURCE BLOCK------------------------------------------------------- 1286 // This is a block of C++ code which provides values, functions, and 1287 // definitions necessary in the rest of the architecture description 1288 1289 source_hpp %{ 1290 1291 // Header information of the source block. 1292 // Method declarations/definitions which are used outside 1293 // the ad-scope can conveniently be defined here. 1294 // 1295 // To keep related declarations/definitions/uses close together, 1296 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 1297 1298 //-------------------------------------------------------------- 1299 // Used for optimization in Compile::Shorten_branches 1300 //-------------------------------------------------------------- 1301 1302 class CallStubImpl { 1303 public: 1304 1305 // call trampolines 1306 // Size of call trampoline stub. For add'l comments, see size_java_to_interp(). 1307 static uint size_call_trampoline() { 1308 return 0; // no call trampolines on this platform 1309 } 1310 1311 // call trampolines 1312 // Number of relocations needed by a call trampoline stub. 1313 static uint reloc_call_trampoline() { 1314 return 0; // No call trampolines on this platform. 1315 } 1316 }; 1317 1318 %} // end source_hpp section 1319 1320 source %{ 1321 1322 #if !defined(PRODUCT) 1323 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const { 1324 os->print_cr("---- MachUEPNode ----"); 1325 os->print_cr("\tTA"); 1326 os->print_cr("\tload_const Z_R1, SharedRuntime::get_ic_miss_stub()"); 1327 os->print_cr("\tBR(Z_R1)"); 1328 os->print_cr("\tTA # pad with illtraps"); 1329 os->print_cr("\t..."); 1330 os->print_cr("\tTA"); 1331 os->print_cr("\tLTGR Z_R2, Z_R2"); 1332 os->print_cr("\tBRU ic_miss"); 1333 } 1334 #endif 1335 1336 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1337 MacroAssembler _masm(&cbuf); 1338 const int ic_miss_offset = 2; 1339 1340 // Inline_cache contains a klass. 1341 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode()); 1342 // ARG1 is the receiver oop. 1343 Register R2_receiver = Z_ARG1; 1344 int klass_offset = oopDesc::klass_offset_in_bytes(); 1345 AddressLiteral icmiss(SharedRuntime::get_ic_miss_stub()); 1346 Register R1_ic_miss_stub_addr = Z_R1_scratch; 1347 1348 // Null check of receiver. 1349 // This is the null check of the receiver that actually should be 1350 // done in the caller. It's here because in case of implicit null 1351 // checks we get it for free. 1352 assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()), 1353 "second word in oop should not require explicit null check."); 1354 if (!ImplicitNullChecks) { 1355 Label valid; 1356 if (VM_Version::has_CompareBranch()) { 1357 __ z_cgij(R2_receiver, 0, Assembler::bcondNotEqual, valid); 1358 } else { 1359 __ z_ltgr(R2_receiver, R2_receiver); 1360 __ z_bre(valid); 1361 } 1362 // The ic_miss_stub will handle the null pointer exception. 1363 __ load_const_optimized(R1_ic_miss_stub_addr, icmiss); 1364 __ z_br(R1_ic_miss_stub_addr); 1365 __ bind(valid); 1366 } 1367 1368 // Check whether this method is the proper implementation for the class of 1369 // the receiver (ic miss check). 1370 { 1371 Label valid; 1372 // Compare cached class against klass from receiver. 1373 // This also does an implicit null check! 1374 __ compare_klass_ptr(ic_klass, klass_offset, R2_receiver, false); 1375 __ z_bre(valid); 1376 // The inline cache points to the wrong method. Call the 1377 // ic_miss_stub to find the proper method. 1378 __ load_const_optimized(R1_ic_miss_stub_addr, icmiss); 1379 __ z_br(R1_ic_miss_stub_addr); 1380 __ bind(valid); 1381 } 1382 1383 } 1384 1385 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1386 // Determine size dynamically. 1387 return MachNode::size(ra_); 1388 } 1389 1390 //============================================================================= 1391 1392 %} // interrupt source section 1393 1394 source_hpp %{ // Header information of the source block. 1395 1396 class HandlerImpl { 1397 public: 1398 1399 static int emit_exception_handler(CodeBuffer &cbuf); 1400 static int emit_deopt_handler(CodeBuffer& cbuf); 1401 1402 static uint size_exception_handler() { 1403 return NativeJump::max_instruction_size(); 1404 } 1405 1406 static uint size_deopt_handler() { 1407 return NativeCall::max_instruction_size(); 1408 } 1409 }; 1410 1411 %} // end source_hpp section 1412 1413 source %{ 1414 1415 // This exception handler code snippet is placed after the method's 1416 // code. It is the return point if an exception occurred. it jumps to 1417 // the exception blob. 1418 // 1419 // If the method gets deoptimized, the method and this code snippet 1420 // get patched. 1421 // 1422 // 1) Trampoline code gets patched into the end of this exception 1423 // handler. the trampoline code jumps to the deoptimization blob. 1424 // 1425 // 2) The return address in the method's code will get patched such 1426 // that it jumps to the trampoline. 1427 // 1428 // 3) The handler will get patched such that it does not jump to the 1429 // exception blob, but to an entry in the deoptimization blob being 1430 // aware of the exception. 1431 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) { 1432 Register temp_reg = Z_R1; 1433 MacroAssembler _masm(&cbuf); 1434 1435 address base = __ start_a_stub(size_exception_handler()); 1436 if (base == NULL) { 1437 return 0; // CodeBuffer::expand failed 1438 } 1439 1440 int offset = __ offset(); 1441 // Use unconditional pc-relative jump with 32-bit range here. 1442 __ load_const_optimized(temp_reg, (address)OptoRuntime::exception_blob()->content_begin()); 1443 __ z_br(temp_reg); 1444 1445 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1446 1447 __ end_a_stub(); 1448 1449 return offset; 1450 } 1451 1452 // Emit deopt handler code. 1453 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 1454 MacroAssembler _masm(&cbuf); 1455 address base = __ start_a_stub(size_deopt_handler()); 1456 1457 if (base == NULL) { 1458 return 0; // CodeBuffer::expand failed 1459 } 1460 1461 int offset = __ offset(); 1462 1463 // Size_deopt_handler() must be exact on zarch, so for simplicity 1464 // we do not use load_const_opt here. 1465 __ load_const(Z_R1, SharedRuntime::deopt_blob()->unpack()); 1466 __ call(Z_R1); 1467 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size"); 1468 1469 __ end_a_stub(); 1470 return offset; 1471 } 1472 1473 //============================================================================= 1474 1475 1476 // Given a register encoding, produce an Integer Register object. 1477 static Register reg_to_register_object(int register_encoding) { 1478 assert(Z_R12->encoding() == Z_R12_enc, "wrong coding"); 1479 return as_Register(register_encoding); 1480 } 1481 1482 const bool Matcher::match_rule_supported(int opcode) { 1483 if (!has_match_rule(opcode)) return false; 1484 1485 switch (opcode) { 1486 case Op_CountLeadingZerosI: 1487 case Op_CountLeadingZerosL: 1488 case Op_CountTrailingZerosI: 1489 case Op_CountTrailingZerosL: 1490 // Implementation requires FLOGR instruction, which is available since z9. 1491 return true; 1492 1493 case Op_ReverseBytesI: 1494 case Op_ReverseBytesL: 1495 return UseByteReverseInstruction; 1496 1497 // PopCount supported by H/W from z/Architecture G5 (z196) on. 1498 case Op_PopCountI: 1499 case Op_PopCountL: 1500 return UsePopCountInstruction && VM_Version::has_PopCount(); 1501 1502 case Op_StrComp: 1503 return SpecialStringCompareTo; 1504 case Op_StrEquals: 1505 return SpecialStringEquals; 1506 case Op_StrIndexOf: 1507 case Op_StrIndexOfChar: 1508 return SpecialStringIndexOf; 1509 1510 case Op_GetAndAddI: 1511 case Op_GetAndAddL: 1512 return true; 1513 // return VM_Version::has_AtomicMemWithImmALUOps(); 1514 case Op_GetAndSetI: 1515 case Op_GetAndSetL: 1516 case Op_GetAndSetP: 1517 case Op_GetAndSetN: 1518 return true; // General CAS implementation, always available. 1519 1520 default: 1521 return true; // Per default match rules are supported. 1522 // BUT: make sure match rule is not disabled by a false predicate! 1523 } 1524 1525 return true; // Per default match rules are supported. 1526 // BUT: make sure match rule is not disabled by a false predicate! 1527 } 1528 1529 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) { 1530 // TODO 1531 // Identify extra cases that we might want to provide match rules for 1532 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen. 1533 bool ret_value = match_rule_supported(opcode); 1534 // Add rules here. 1535 1536 return ret_value; // Per default match rules are supported. 1537 } 1538 1539 int Matcher::regnum_to_fpu_offset(int regnum) { 1540 ShouldNotReachHere(); 1541 return regnum - 32; // The FP registers are in the second chunk. 1542 } 1543 1544 const bool Matcher::has_predicated_vectors(void) { 1545 return false; 1546 } 1547 1548 const int Matcher::float_pressure(int default_pressure_threshold) { 1549 return default_pressure_threshold; 1550 } 1551 1552 const bool Matcher::convL2FSupported(void) { 1553 return true; // False means that conversion is done by runtime call. 1554 } 1555 1556 //----------SUPERWORD HELPERS---------------------------------------- 1557 1558 // Vector width in bytes. 1559 const int Matcher::vector_width_in_bytes(BasicType bt) { 1560 assert(MaxVectorSize == 8, ""); 1561 return 8; 1562 } 1563 1564 // Vector ideal reg. 1565 const int Matcher::vector_ideal_reg(int size) { 1566 assert(MaxVectorSize == 8 && size == 8, ""); 1567 return Op_RegL; 1568 } 1569 1570 // Limits on vector size (number of elements) loaded into vector. 1571 const int Matcher::max_vector_size(const BasicType bt) { 1572 assert(is_java_primitive(bt), "only primitive type vectors"); 1573 return vector_width_in_bytes(bt)/type2aelembytes(bt); 1574 } 1575 1576 const int Matcher::min_vector_size(const BasicType bt) { 1577 return max_vector_size(bt); // Same as max. 1578 } 1579 1580 const int Matcher::vector_shift_count_ideal_reg(int size) { 1581 fatal("vector shift is not supported"); 1582 return Node::NotAMachineReg; 1583 } 1584 1585 // z/Architecture does support misaligned store/load at minimal extra cost. 1586 const bool Matcher::misaligned_vectors_ok() { 1587 return true; 1588 } 1589 1590 // Not yet ported to z/Architecture. 1591 const bool Matcher::pass_original_key_for_aes() { 1592 return false; 1593 } 1594 1595 // RETURNS: whether this branch offset is short enough that a short 1596 // branch can be used. 1597 // 1598 // If the platform does not provide any short branch variants, then 1599 // this method should return `false' for offset 0. 1600 // 1601 // `Compile::Fill_buffer' will decide on basis of this information 1602 // whether to do the pass `Compile::Shorten_branches' at all. 1603 // 1604 // And `Compile::Shorten_branches' will decide on basis of this 1605 // information whether to replace particular branch sites by short 1606 // ones. 1607 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 1608 // On zarch short branches use a 16 bit signed immediate that 1609 // is the pc-relative offset in halfword (= 2 bytes) units. 1610 return Assembler::is_within_range_of_RelAddr16((address)((long)offset), (address)0); 1611 } 1612 1613 const bool Matcher::isSimpleConstant64(jlong value) { 1614 // Probably always true, even if a temp register is required. 1615 return true; 1616 } 1617 1618 // Should correspond to setting above 1619 const bool Matcher::init_array_count_is_in_bytes = false; 1620 1621 // Suppress CMOVL. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet. 1622 const int Matcher::long_cmove_cost() { return ConditionalMoveLimit; } 1623 1624 // Suppress CMOVF. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet. 1625 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } 1626 1627 // Does the CPU require postalloc expand (see block.cpp for description of postalloc expand)? 1628 const bool Matcher::require_postalloc_expand = false; 1629 1630 // Do we need to mask the count passed to shift instructions or does 1631 // the cpu only look at the lower 5/6 bits anyway? 1632 // 32bit shifts mask in emitter, 64bit shifts need no mask. 1633 // Constant shift counts are handled in Ideal phase. 1634 const bool Matcher::need_masked_shift_count = false; 1635 1636 // Set this as clone_shift_expressions. 1637 bool Matcher::narrow_oop_use_complex_address() { 1638 if (Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0) return true; 1639 return false; 1640 } 1641 1642 bool Matcher::narrow_klass_use_complex_address() { 1643 NOT_LP64(ShouldNotCallThis()); 1644 assert(UseCompressedClassPointers, "only for compressed klass code"); 1645 // TODO HS25: z port if (MatchDecodeNodes) return true; 1646 return false; 1647 } 1648 1649 bool Matcher::const_oop_prefer_decode() { 1650 // Prefer ConN+DecodeN over ConP in simple compressed oops mode. 1651 return Universe::narrow_oop_base() == NULL; 1652 } 1653 1654 bool Matcher::const_klass_prefer_decode() { 1655 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode. 1656 return Universe::narrow_klass_base() == NULL; 1657 } 1658 1659 // Is it better to copy float constants, or load them directly from memory? 1660 // Most RISCs will have to materialize an address into a 1661 // register first, so they would do better to copy the constant from stack. 1662 const bool Matcher::rematerialize_float_constants = false; 1663 1664 // If CPU can load and store mis-aligned doubles directly then no fixup is 1665 // needed. Else we split the double into 2 integer pieces and move it 1666 // piece-by-piece. Only happens when passing doubles into C code as the 1667 // Java calling convention forces doubles to be aligned. 1668 const bool Matcher::misaligned_doubles_ok = true; 1669 1670 // Advertise here if the CPU requires explicit rounding operations 1671 // to implement the UseStrictFP mode. 1672 const bool Matcher::strict_fp_requires_explicit_rounding = false; 1673 1674 // Do floats take an entire double register or just half? 1675 // 1676 // A float in resides in a zarch double register. When storing it by 1677 // z_std, it cannot be restored in C-code by reloading it as a double 1678 // and casting it into a float afterwards. 1679 bool Matcher::float_in_double() { return false; } 1680 1681 // Do ints take an entire long register or just half? 1682 // The relevant question is how the int is callee-saved: 1683 // the whole long is written but de-opt'ing will have to extract 1684 // the relevant 32 bits. 1685 const bool Matcher::int_in_long = true; 1686 1687 // Constants for c2c and c calling conventions. 1688 1689 const MachRegisterNumbers z_iarg_reg[5] = { 1690 Z_R2_num, Z_R3_num, Z_R4_num, Z_R5_num, Z_R6_num 1691 }; 1692 1693 const MachRegisterNumbers z_farg_reg[4] = { 1694 Z_F0_num, Z_F2_num, Z_F4_num, Z_F6_num 1695 }; 1696 1697 const int z_num_iarg_registers = sizeof(z_iarg_reg) / sizeof(z_iarg_reg[0]); 1698 1699 const int z_num_farg_registers = sizeof(z_farg_reg) / sizeof(z_farg_reg[0]); 1700 1701 // Return whether or not this register is ever used as an argument. This 1702 // function is used on startup to build the trampoline stubs in generateOptoStub. 1703 // Registers not mentioned will be killed by the VM call in the trampoline, and 1704 // arguments in those registers not be available to the callee. 1705 bool Matcher::can_be_java_arg(int reg) { 1706 // We return true for all registers contained in z_iarg_reg[] and 1707 // z_farg_reg[] and their virtual halves. 1708 // We must include the virtual halves in order to get STDs and LDs 1709 // instead of STWs and LWs in the trampoline stubs. 1710 1711 if (reg == Z_R2_num || reg == Z_R2_H_num || 1712 reg == Z_R3_num || reg == Z_R3_H_num || 1713 reg == Z_R4_num || reg == Z_R4_H_num || 1714 reg == Z_R5_num || reg == Z_R5_H_num || 1715 reg == Z_R6_num || reg == Z_R6_H_num) { 1716 return true; 1717 } 1718 1719 if (reg == Z_F0_num || reg == Z_F0_H_num || 1720 reg == Z_F2_num || reg == Z_F2_H_num || 1721 reg == Z_F4_num || reg == Z_F4_H_num || 1722 reg == Z_F6_num || reg == Z_F6_H_num) { 1723 return true; 1724 } 1725 1726 return false; 1727 } 1728 1729 bool Matcher::is_spillable_arg(int reg) { 1730 return can_be_java_arg(reg); 1731 } 1732 1733 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) { 1734 return false; 1735 } 1736 1737 // Register for DIVI projection of divmodI 1738 RegMask Matcher::divI_proj_mask() { 1739 return _Z_RARG4_INT_REG_mask; 1740 } 1741 1742 // Register for MODI projection of divmodI 1743 RegMask Matcher::modI_proj_mask() { 1744 return _Z_RARG3_INT_REG_mask; 1745 } 1746 1747 // Register for DIVL projection of divmodL 1748 RegMask Matcher::divL_proj_mask() { 1749 return _Z_RARG4_LONG_REG_mask; 1750 } 1751 1752 // Register for MODL projection of divmodL 1753 RegMask Matcher::modL_proj_mask() { 1754 return _Z_RARG3_LONG_REG_mask; 1755 } 1756 1757 // Copied from sparc. 1758 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1759 return RegMask(); 1760 } 1761 1762 const bool Matcher::convi2l_type_required = true; 1763 1764 // Should the Matcher clone shifts on addressing modes, expecting them 1765 // to be subsumed into complex addressing expressions or compute them 1766 // into registers? 1767 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) { 1768 return clone_base_plus_offset_address(m, mstack, address_visited); 1769 } 1770 1771 void Compile::reshape_address(AddPNode* addp) { 1772 } 1773 1774 %} // source 1775 1776 //----------ENCODING BLOCK----------------------------------------------------- 1777 // This block specifies the encoding classes used by the compiler to output 1778 // byte streams. Encoding classes are parameterized macros used by 1779 // Machine Instruction Nodes in order to generate the bit encoding of the 1780 // instruction. Operands specify their base encoding interface with the 1781 // interface keyword. There are currently supported four interfaces, 1782 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1783 // operand to generate a function which returns its register number when 1784 // queried. CONST_INTER causes an operand to generate a function which 1785 // returns the value of the constant when queried. MEMORY_INTER causes an 1786 // operand to generate four functions which return the Base Register, the 1787 // Index Register, the Scale Value, and the Offset Value of the operand when 1788 // queried. COND_INTER causes an operand to generate six functions which 1789 // return the encoding code (ie - encoding bits for the instruction) 1790 // associated with each basic boolean condition for a conditional instruction. 1791 // 1792 // Instructions specify two basic values for encoding. Again, a function 1793 // is available to check if the constant displacement is an oop. They use the 1794 // ins_encode keyword to specify their encoding classes (which must be 1795 // a sequence of enc_class names, and their parameters, specified in 1796 // the encoding block), and they use the 1797 // opcode keyword to specify, in order, their primary, secondary, and 1798 // tertiary opcode. Only the opcode sections which a particular instruction 1799 // needs for encoding need to be specified. 1800 encode %{ 1801 enc_class enc_unimplemented %{ 1802 MacroAssembler _masm(&cbuf); 1803 __ unimplemented("Unimplemented mach node encoding in AD file.", 13); 1804 %} 1805 1806 enc_class enc_untested %{ 1807 #ifdef ASSERT 1808 MacroAssembler _masm(&cbuf); 1809 __ untested("Untested mach node encoding in AD file."); 1810 #endif 1811 %} 1812 1813 enc_class z_rrform(iRegI dst, iRegI src) %{ 1814 assert((($primary >> 14) & 0x03) == 0, "Instruction format error"); 1815 assert( ($primary >> 16) == 0, "Instruction format error"); 1816 z_emit16(cbuf, $primary | 1817 Assembler::reg($dst$$reg,8,16) | 1818 Assembler::reg($src$$reg,12,16)); 1819 %} 1820 1821 enc_class z_rreform(iRegI dst1, iRegI src2) %{ 1822 assert((($primary >> 30) & 0x03) == 2, "Instruction format error"); 1823 z_emit32(cbuf, $primary | 1824 Assembler::reg($dst1$$reg,24,32) | 1825 Assembler::reg($src2$$reg,28,32)); 1826 %} 1827 1828 enc_class z_rrfform(iRegI dst1, iRegI src2, iRegI src3) %{ 1829 assert((($primary >> 30) & 0x03) == 2, "Instruction format error"); 1830 z_emit32(cbuf, $primary | 1831 Assembler::reg($dst1$$reg,24,32) | 1832 Assembler::reg($src2$$reg,28,32) | 1833 Assembler::reg($src3$$reg,16,32)); 1834 %} 1835 1836 enc_class z_riform_signed(iRegI dst, immI16 src) %{ 1837 assert((($primary>>30) & 0x03) == 2, "Instruction format error"); 1838 z_emit32(cbuf, $primary | 1839 Assembler::reg($dst$$reg,8,32) | 1840 Assembler::simm16($src$$constant,16,32)); 1841 %} 1842 1843 enc_class z_riform_unsigned(iRegI dst, uimmI16 src) %{ 1844 assert((($primary>>30) & 0x03) == 2, "Instruction format error"); 1845 z_emit32(cbuf, $primary | 1846 Assembler::reg($dst$$reg,8,32) | 1847 Assembler::uimm16($src$$constant,16,32)); 1848 %} 1849 1850 enc_class z_rieform_d(iRegI dst1, iRegI src3, immI src2) %{ 1851 assert((($primary>>46) & 0x03) == 3, "Instruction format error"); 1852 z_emit48(cbuf, $primary | 1853 Assembler::reg($dst1$$reg,8,48) | 1854 Assembler::reg($src3$$reg,12,48) | 1855 Assembler::simm16($src2$$constant,16,48)); 1856 %} 1857 1858 enc_class z_rilform_signed(iRegI dst, immL32 src) %{ 1859 assert((($primary>>46) & 0x03) == 3, "Instruction format error"); 1860 z_emit48(cbuf, $primary | 1861 Assembler::reg($dst$$reg,8,48) | 1862 Assembler::simm32($src$$constant,16,48)); 1863 %} 1864 1865 enc_class z_rilform_unsigned(iRegI dst, uimmL32 src) %{ 1866 assert((($primary>>46) & 0x03) == 3, "Instruction format error"); 1867 z_emit48(cbuf, $primary | 1868 Assembler::reg($dst$$reg,8,48) | 1869 Assembler::uimm32($src$$constant,16,48)); 1870 %} 1871 1872 enc_class z_rsyform_const(iRegI dst, iRegI src1, immI src2) %{ 1873 z_emit48(cbuf, $primary | 1874 Assembler::reg($dst$$reg,8,48) | 1875 Assembler::reg($src1$$reg,12,48) | 1876 Assembler::simm20($src2$$constant)); 1877 %} 1878 1879 enc_class z_rsyform_reg_reg(iRegI dst, iRegI src, iRegI shft) %{ 1880 z_emit48(cbuf, $primary | 1881 Assembler::reg($dst$$reg,8,48) | 1882 Assembler::reg($src$$reg,12,48) | 1883 Assembler::reg($shft$$reg,16,48) | 1884 Assembler::simm20(0)); 1885 %} 1886 1887 enc_class z_rxform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{ 1888 assert((($primary>>30) & 0x03) == 1, "Instruction format error"); 1889 z_emit32(cbuf, $primary | 1890 Assembler::reg($dst$$reg,8,32) | 1891 Assembler::reg($src1$$reg,12,32) | 1892 Assembler::reg($src2$$reg,16,32) | 1893 Assembler::uimm12($con$$constant,20,32)); 1894 %} 1895 1896 enc_class z_rxform_imm_reg(iRegL dst, immL con, iRegL src) %{ 1897 assert((($primary>>30) & 0x03) == 1, "Instruction format error"); 1898 z_emit32(cbuf, $primary | 1899 Assembler::reg($dst$$reg,8,32) | 1900 Assembler::reg($src$$reg,16,32) | 1901 Assembler::uimm12($con$$constant,20,32)); 1902 %} 1903 1904 enc_class z_rxyform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{ 1905 z_emit48(cbuf, $primary | 1906 Assembler::reg($dst$$reg,8,48) | 1907 Assembler::reg($src1$$reg,12,48) | 1908 Assembler::reg($src2$$reg,16,48) | 1909 Assembler::simm20($con$$constant)); 1910 %} 1911 1912 enc_class z_rxyform_imm_reg(iRegL dst, immL con, iRegL src) %{ 1913 z_emit48(cbuf, $primary | 1914 Assembler::reg($dst$$reg,8,48) | 1915 Assembler::reg($src$$reg,16,48) | 1916 Assembler::simm20($con$$constant)); 1917 %} 1918 1919 // Direct memory arithmetic. 1920 enc_class z_siyform(memoryRSY mem, immI8 src) %{ 1921 int disp = $mem$$disp; 1922 Register base = reg_to_register_object($mem$$base); 1923 int con = $src$$constant; 1924 1925 assert(VM_Version::has_MemWithImmALUOps(), "unsupported CPU"); 1926 z_emit_inst(cbuf, $primary | 1927 Assembler::regz(base,16,48) | 1928 Assembler::simm20(disp) | 1929 Assembler::simm8(con,8,48)); 1930 %} 1931 1932 enc_class z_silform(memoryRS mem, immI16 src) %{ 1933 z_emit_inst(cbuf, $primary | 1934 Assembler::regz(reg_to_register_object($mem$$base),16,48) | 1935 Assembler::uimm12($mem$$disp,20,48) | 1936 Assembler::simm16($src$$constant,32,48)); 1937 %} 1938 1939 // Encoder for FP ALU reg/mem instructions (support only short displacements). 1940 enc_class z_form_rt_memFP(RegF dst, memoryRX mem) %{ 1941 Register Ridx = $mem$$index$$Register; 1942 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0. 1943 if ($primary > (1L << 32)) { 1944 z_emit_inst(cbuf, $primary | 1945 Assembler::reg($dst$$reg, 8, 48) | 1946 Assembler::uimm12($mem$$disp, 20, 48) | 1947 Assembler::reg(Ridx, 12, 48) | 1948 Assembler::regz(reg_to_register_object($mem$$base), 16, 48)); 1949 } else { 1950 z_emit_inst(cbuf, $primary | 1951 Assembler::reg($dst$$reg, 8, 32) | 1952 Assembler::uimm12($mem$$disp, 20, 32) | 1953 Assembler::reg(Ridx, 12, 32) | 1954 Assembler::regz(reg_to_register_object($mem$$base), 16, 32)); 1955 } 1956 %} 1957 1958 enc_class z_form_rt_mem(iRegI dst, memory mem) %{ 1959 Register Ridx = $mem$$index$$Register; 1960 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0. 1961 if ($primary > (1L<<32)) { 1962 z_emit_inst(cbuf, $primary | 1963 Assembler::reg($dst$$reg, 8, 48) | 1964 Assembler::simm20($mem$$disp) | 1965 Assembler::reg(Ridx, 12, 48) | 1966 Assembler::regz(reg_to_register_object($mem$$base), 16, 48)); 1967 } else { 1968 z_emit_inst(cbuf, $primary | 1969 Assembler::reg($dst$$reg, 8, 32) | 1970 Assembler::uimm12($mem$$disp, 20, 32) | 1971 Assembler::reg(Ridx, 12, 32) | 1972 Assembler::regz(reg_to_register_object($mem$$base), 16, 32)); 1973 } 1974 %} 1975 1976 enc_class z_form_rt_mem_opt(iRegI dst, memory mem) %{ 1977 int isize = $secondary > 1L << 32 ? 48 : 32; 1978 Register Ridx = $mem$$index$$Register; 1979 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0. 1980 1981 if (Displacement::is_shortDisp((long)$mem$$disp)) { 1982 z_emit_inst(cbuf, $secondary | 1983 Assembler::reg($dst$$reg, 8, isize) | 1984 Assembler::uimm12($mem$$disp, 20, isize) | 1985 Assembler::reg(Ridx, 12, isize) | 1986 Assembler::regz(reg_to_register_object($mem$$base), 16, isize)); 1987 } else if (Displacement::is_validDisp((long)$mem$$disp)) { 1988 z_emit_inst(cbuf, $primary | 1989 Assembler::reg($dst$$reg, 8, 48) | 1990 Assembler::simm20($mem$$disp) | 1991 Assembler::reg(Ridx, 12, 48) | 1992 Assembler::regz(reg_to_register_object($mem$$base), 16, 48)); 1993 } else { 1994 MacroAssembler _masm(&cbuf); 1995 __ load_const_optimized(Z_R1_scratch, $mem$$disp); 1996 if (Ridx != Z_R0) { __ z_agr(Z_R1_scratch, Ridx); } 1997 z_emit_inst(cbuf, $secondary | 1998 Assembler::reg($dst$$reg, 8, isize) | 1999 Assembler::uimm12(0, 20, isize) | 2000 Assembler::reg(Z_R1_scratch, 12, isize) | 2001 Assembler::regz(reg_to_register_object($mem$$base), 16, isize)); 2002 } 2003 %} 2004 2005 enc_class z_enc_brul(Label lbl) %{ 2006 MacroAssembler _masm(&cbuf); 2007 Label* p = $lbl$$label; 2008 2009 // 'p' is `NULL' when this encoding class is used only to 2010 // determine the size of the encoded instruction. 2011 // Use a bound dummy label in that case. 2012 Label d; 2013 __ bind(d); 2014 Label& l = (NULL == p) ? d : *(p); 2015 __ z_brul(l); 2016 %} 2017 2018 enc_class z_enc_bru(Label lbl) %{ 2019 MacroAssembler _masm(&cbuf); 2020 Label* p = $lbl$$label; 2021 2022 // 'p' is `NULL' when this encoding class is used only to 2023 // determine the size of the encoded instruction. 2024 // Use a bound dummy label in that case. 2025 Label d; 2026 __ bind(d); 2027 Label& l = (NULL == p) ? d : *(p); 2028 __ z_bru(l); 2029 %} 2030 2031 enc_class z_enc_branch_con_far(cmpOp cmp, Label lbl) %{ 2032 MacroAssembler _masm(&cbuf); 2033 Label* p = $lbl$$label; 2034 2035 // 'p' is `NULL' when this encoding class is used only to 2036 // determine the size of the encoded instruction. 2037 // Use a bound dummy label in that case. 2038 Label d; 2039 __ bind(d); 2040 Label& l = (NULL == p) ? d : *(p); 2041 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l); 2042 %} 2043 2044 enc_class z_enc_branch_con_short(cmpOp cmp, Label lbl) %{ 2045 MacroAssembler _masm(&cbuf); 2046 Label* p = $lbl$$label; 2047 2048 // 'p' is `NULL' when this encoding class is used only to 2049 // determine the size of the encoded instruction. 2050 // Use a bound dummy label in that case. 2051 Label d; 2052 __ bind(d); 2053 Label& l = (NULL == p) ? d : *(p); 2054 __ z_brc((Assembler::branch_condition)$cmp$$cmpcode, l); 2055 %} 2056 2057 enc_class z_enc_cmpb_regreg(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{ 2058 MacroAssembler _masm(&cbuf); 2059 Label* p = $lbl$$label; 2060 2061 // 'p' is `NULL' when this encoding class is used only to 2062 // determine the size of the encoded instruction. 2063 // Use a bound dummy label in that case. 2064 Label d; 2065 __ bind(d); 2066 Label& l = (NULL == p) ? d : *(p); 2067 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; 2068 unsigned long instr = $primary; 2069 if (instr == CRJ_ZOPC) { 2070 __ z_crj($src1$$Register, $src2$$Register, cc, l); 2071 } else if (instr == CLRJ_ZOPC) { 2072 __ z_clrj($src1$$Register, $src2$$Register, cc, l); 2073 } else if (instr == CGRJ_ZOPC) { 2074 __ z_cgrj($src1$$Register, $src2$$Register, cc, l); 2075 } else { 2076 guarantee(instr == CLGRJ_ZOPC, "opcode not implemented"); 2077 __ z_clgrj($src1$$Register, $src2$$Register, cc, l); 2078 } 2079 %} 2080 2081 enc_class z_enc_cmpb_regregFar(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{ 2082 MacroAssembler _masm(&cbuf); 2083 Label* p = $lbl$$label; 2084 2085 // 'p' is `NULL' when this encoding class is used only to 2086 // determine the size of the encoded instruction. 2087 // Use a bound dummy label in that case. 2088 Label d; 2089 __ bind(d); 2090 Label& l = (NULL == p) ? d : *(p); 2091 2092 unsigned long instr = $primary; 2093 if (instr == CR_ZOPC) { 2094 __ z_cr($src1$$Register, $src2$$Register); 2095 } else if (instr == CLR_ZOPC) { 2096 __ z_clr($src1$$Register, $src2$$Register); 2097 } else if (instr == CGR_ZOPC) { 2098 __ z_cgr($src1$$Register, $src2$$Register); 2099 } else { 2100 guarantee(instr == CLGR_ZOPC, "opcode not implemented"); 2101 __ z_clgr($src1$$Register, $src2$$Register); 2102 } 2103 2104 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l); 2105 %} 2106 2107 enc_class z_enc_cmpb_regimm(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{ 2108 MacroAssembler _masm(&cbuf); 2109 Label* p = $lbl$$label; 2110 2111 // 'p' is `NULL' when this encoding class is used only to 2112 // determine the size of the encoded instruction. 2113 // Use a bound dummy label in that case. 2114 Label d; 2115 __ bind(d); 2116 Label& l = (NULL == p) ? d : *(p); 2117 2118 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; 2119 unsigned long instr = $primary; 2120 if (instr == CIJ_ZOPC) { 2121 __ z_cij($src1$$Register, $src2$$constant, cc, l); 2122 } else if (instr == CLIJ_ZOPC) { 2123 __ z_clij($src1$$Register, $src2$$constant, cc, l); 2124 } else if (instr == CGIJ_ZOPC) { 2125 __ z_cgij($src1$$Register, $src2$$constant, cc, l); 2126 } else { 2127 guarantee(instr == CLGIJ_ZOPC, "opcode not implemented"); 2128 __ z_clgij($src1$$Register, $src2$$constant, cc, l); 2129 } 2130 %} 2131 2132 enc_class z_enc_cmpb_regimmFar(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{ 2133 MacroAssembler _masm(&cbuf); 2134 Label* p = $lbl$$label; 2135 2136 // 'p' is `NULL' when this encoding class is used only to 2137 // determine the size of the encoded instruction. 2138 // Use a bound dummy label in that case. 2139 Label d; 2140 __ bind(d); 2141 Label& l = (NULL == p) ? d : *(p); 2142 2143 unsigned long instr = $primary; 2144 if (instr == CHI_ZOPC) { 2145 __ z_chi($src1$$Register, $src2$$constant); 2146 } else if (instr == CLFI_ZOPC) { 2147 __ z_clfi($src1$$Register, $src2$$constant); 2148 } else if (instr == CGHI_ZOPC) { 2149 __ z_cghi($src1$$Register, $src2$$constant); 2150 } else { 2151 guarantee(instr == CLGFI_ZOPC, "opcode not implemented"); 2152 __ z_clgfi($src1$$Register, $src2$$constant); 2153 } 2154 2155 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l); 2156 %} 2157 2158 // Call from Java to runtime. 2159 enc_class z_enc_java_to_runtime_call(method meth) %{ 2160 MacroAssembler _masm(&cbuf); 2161 2162 // Save return pc before call to the place where we need it, since 2163 // callee doesn't. 2164 unsigned int start_off = __ offset(); 2165 // Compute size of "larl + stg + call_c_opt". 2166 const int size_of_code = 6 + 6 + MacroAssembler::call_far_patchable_size(); 2167 __ get_PC(Z_R14, size_of_code); 2168 __ save_return_pc(); 2169 assert(__ offset() - start_off == 12, "bad prelude len: %d", __ offset() - start_off); 2170 2171 assert((__ offset() & 2) == 0, "misaligned z_enc_java_to_runtime_call"); 2172 address call_addr = __ call_c_opt((address)$meth$$method); 2173 if (call_addr == NULL) { 2174 Compile::current()->env()->record_out_of_memory_failure(); 2175 return; 2176 } 2177 2178 #ifdef ASSERT 2179 // Plausibility check for size_of_code assumptions. 2180 unsigned int actual_ret_off = __ offset(); 2181 assert(start_off + size_of_code == actual_ret_off, "wrong return_pc"); 2182 #endif 2183 %} 2184 2185 enc_class z_enc_java_static_call(method meth) %{ 2186 // Call to fixup routine. Fixup routine uses ScopeDesc info to determine 2187 // whom we intended to call. 2188 MacroAssembler _masm(&cbuf); 2189 int ret_offset = 0; 2190 2191 if (!_method) { 2192 ret_offset = emit_call_reloc(_masm, $meth$$method, 2193 relocInfo::runtime_call_w_cp_type, ra_); 2194 } else { 2195 int method_index = resolved_method_index(cbuf); 2196 if (_optimized_virtual) { 2197 ret_offset = emit_call_reloc(_masm, $meth$$method, 2198 opt_virtual_call_Relocation::spec(method_index)); 2199 } else { 2200 ret_offset = emit_call_reloc(_masm, $meth$$method, 2201 static_call_Relocation::spec(method_index)); 2202 } 2203 } 2204 assert(__ inst_mark() != NULL, "emit_call_reloc must set_inst_mark()"); 2205 2206 if (_method) { // Emit stub for static call. 2207 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); 2208 if (stub == NULL) { 2209 ciEnv::current()->record_failure("CodeCache is full"); 2210 return; 2211 } 2212 } 2213 %} 2214 2215 // Java dynamic call 2216 enc_class z_enc_java_dynamic_call(method meth) %{ 2217 MacroAssembler _masm(&cbuf); 2218 unsigned int start_off = __ offset(); 2219 2220 int vtable_index = this->_vtable_index; 2221 if (vtable_index == -4) { 2222 Register ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2223 address virtual_call_oop_addr = NULL; 2224 2225 AddressLiteral empty_ic((address) Universe::non_oop_word()); 2226 virtual_call_oop_addr = __ pc(); 2227 bool success = __ load_const_from_toc(ic_reg, empty_ic); 2228 if (!success) { 2229 Compile::current()->env()->record_out_of_memory_failure(); 2230 return; 2231 } 2232 2233 // Call to fixup routine. Fixup routine uses ScopeDesc info 2234 // to determine who we intended to call. 2235 int method_index = resolved_method_index(cbuf); 2236 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index)); 2237 unsigned int ret_off = __ offset(); 2238 assert(__ offset() - start_off == 6, "bad prelude len: %d", __ offset() - start_off); 2239 ret_off += emit_call_reloc(_masm, $meth$$method, relocInfo::none, ra_); 2240 assert(_method, "lazy_constant may be wrong when _method==null"); 2241 } else { 2242 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2243 // Go through the vtable. Get receiver klass. Receiver already 2244 // checked for non-null. If we'll go thru a C2I adapter, the 2245 // interpreter expects method in Z_method. 2246 // Use Z_method to temporarily hold the klass oop. Z_R1_scratch is destroyed 2247 // by load_heap_oop_not_null. 2248 __ load_klass(Z_method, Z_R2); 2249 2250 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes(); 2251 int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); 2252 2253 if (Displacement::is_validDisp(v_off) ) { 2254 // Can use load instruction with large offset. 2255 __ z_lg(Z_method, Address(Z_method /*class oop*/, v_off /*method offset*/)); 2256 } else { 2257 // Worse case, must load offset into register. 2258 __ load_const(Z_R1_scratch, v_off); 2259 __ z_lg(Z_method, Address(Z_method /*class oop*/, Z_R1_scratch /*method offset*/)); 2260 } 2261 // NOTE: for vtable dispatches, the vtable entry will never be 2262 // null. However it may very well end up in handle_wrong_method 2263 // if the method is abstract for the particular class. 2264 __ z_lg(Z_R1_scratch, Address(Z_method, Method::from_compiled_offset())); 2265 // Call target. Either compiled code or C2I adapter. 2266 __ z_basr(Z_R14, Z_R1_scratch); 2267 unsigned int ret_off = __ offset(); 2268 } 2269 %} 2270 2271 enc_class z_enc_cmov_reg(cmpOp cmp, iRegI dst, iRegI src) %{ 2272 MacroAssembler _masm(&cbuf); 2273 Register Rdst = reg_to_register_object($dst$$reg); 2274 Register Rsrc = reg_to_register_object($src$$reg); 2275 2276 // Don't emit code if operands are identical (same register). 2277 if (Rsrc != Rdst) { 2278 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; 2279 2280 if (VM_Version::has_LoadStoreConditional()) { 2281 __ z_locgr(Rdst, Rsrc, cc); 2282 } else { 2283 // Branch if not (cmp cr). 2284 Label done; 2285 __ z_brc(Assembler::inverse_condition(cc), done); 2286 __ z_lgr(Rdst, Rsrc); // Used for int and long+ptr. 2287 __ bind(done); 2288 } 2289 } 2290 %} 2291 2292 enc_class z_enc_cmov_imm(cmpOp cmp, iRegI dst, immI16 src) %{ 2293 MacroAssembler _masm(&cbuf); 2294 Register Rdst = reg_to_register_object($dst$$reg); 2295 int Csrc = $src$$constant; 2296 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; 2297 Label done; 2298 // Branch if not (cmp cr). 2299 __ z_brc(Assembler::inverse_condition(cc), done); 2300 if (Csrc == 0) { 2301 // Don't set CC. 2302 __ clear_reg(Rdst, true, false); // Use for int, long & ptr. 2303 } else { 2304 __ z_lghi(Rdst, Csrc); // Use for int, long & ptr. 2305 } 2306 __ bind(done); 2307 %} 2308 2309 enc_class z_enc_cctobool(iRegI res) %{ 2310 MacroAssembler _masm(&cbuf); 2311 Register Rres = reg_to_register_object($res$$reg); 2312 2313 if (VM_Version::has_LoadStoreConditional()) { 2314 __ load_const_optimized(Z_R0_scratch, 0L); // false (failed) 2315 __ load_const_optimized(Rres, 1L); // true (succeed) 2316 __ z_locgr(Rres, Z_R0_scratch, Assembler::bcondNotEqual); 2317 } else { 2318 Label done; 2319 __ load_const_optimized(Rres, 0L); // false (failed) 2320 __ z_brne(done); // Assume true to be the common case. 2321 __ load_const_optimized(Rres, 1L); // true (succeed) 2322 __ bind(done); 2323 } 2324 %} 2325 2326 enc_class z_enc_casI(iRegI compare_value, iRegI exchange_value, iRegP addr_ptr) %{ 2327 MacroAssembler _masm(&cbuf); 2328 Register Rcomp = reg_to_register_object($compare_value$$reg); 2329 Register Rnew = reg_to_register_object($exchange_value$$reg); 2330 Register Raddr = reg_to_register_object($addr_ptr$$reg); 2331 2332 __ z_cs(Rcomp, Rnew, 0, Raddr); 2333 %} 2334 2335 enc_class z_enc_casL(iRegL compare_value, iRegL exchange_value, iRegP addr_ptr) %{ 2336 MacroAssembler _masm(&cbuf); 2337 Register Rcomp = reg_to_register_object($compare_value$$reg); 2338 Register Rnew = reg_to_register_object($exchange_value$$reg); 2339 Register Raddr = reg_to_register_object($addr_ptr$$reg); 2340 2341 __ z_csg(Rcomp, Rnew, 0, Raddr); 2342 %} 2343 2344 enc_class z_enc_SwapI(memoryRSY mem, iRegI dst, iRegI tmp) %{ 2345 MacroAssembler _masm(&cbuf); 2346 Register Rdst = reg_to_register_object($dst$$reg); 2347 Register Rtmp = reg_to_register_object($tmp$$reg); 2348 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF"); 2349 Label retry; 2350 2351 // Iterate until swap succeeds. 2352 __ z_llgf(Rtmp, $mem$$Address); // current contents 2353 __ bind(retry); 2354 // Calculate incremented value. 2355 __ z_csy(Rtmp, Rdst, $mem$$Address); // Try to store new value. 2356 __ z_brne(retry); // Yikes, concurrent update, need to retry. 2357 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value. 2358 %} 2359 2360 enc_class z_enc_SwapL(memoryRSY mem, iRegL dst, iRegL tmp) %{ 2361 MacroAssembler _masm(&cbuf); 2362 Register Rdst = reg_to_register_object($dst$$reg); 2363 Register Rtmp = reg_to_register_object($tmp$$reg); 2364 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF"); 2365 Label retry; 2366 2367 // Iterate until swap succeeds. 2368 __ z_lg(Rtmp, $mem$$Address); // current contents 2369 __ bind(retry); 2370 // Calculate incremented value. 2371 __ z_csg(Rtmp, Rdst, $mem$$Address); // Try to store new value. 2372 __ z_brne(retry); // Yikes, concurrent update, need to retry. 2373 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value. 2374 %} 2375 2376 %} // encode 2377 2378 source %{ 2379 2380 // Check whether outs are all Stores. If so, we can omit clearing the upper 2381 // 32 bits after encoding. 2382 static bool all_outs_are_Stores(const Node *n) { 2383 for (DUIterator_Fast imax, k = n->fast_outs(imax); k < imax; k++) { 2384 Node *out = n->fast_out(k); 2385 if (!out->is_Mach() || out->as_Mach()->ideal_Opcode() != Op_StoreN) { 2386 // Most other outs are SpillCopy, but there are various other. 2387 // jvm98 has arond 9% Encodes where we return false. 2388 return false; 2389 } 2390 } 2391 return true; 2392 } 2393 2394 %} // source 2395 2396 2397 //----------FRAME-------------------------------------------------------------- 2398 // Definition of frame structure and management information. 2399 2400 frame %{ 2401 // What direction does stack grow in (assumed to be same for native & Java). 2402 stack_direction(TOWARDS_LOW); 2403 2404 // These two registers define part of the calling convention between 2405 // compiled code and the interpreter. 2406 2407 // Inline Cache Register 2408 inline_cache_reg(Z_R9); // Z_inline_cache 2409 2410 // Argument pointer for I2C adapters 2411 // 2412 // Tos is loaded in run_compiled_code to Z_ARG5=Z_R6. 2413 // interpreter_arg_ptr_reg(Z_R6); 2414 2415 // Temporary in compiled entry-points 2416 // compiler_method_oop_reg(Z_R1);//Z_R1_scratch 2417 2418 // Method Oop Register when calling interpreter 2419 interpreter_method_oop_reg(Z_R9);//Z_method 2420 2421 // Optional: name the operand used by cisc-spilling to access 2422 // [stack_pointer + offset]. 2423 cisc_spilling_operand_name(indOffset12); 2424 2425 // Number of stack slots consumed by a Monitor enter. 2426 sync_stack_slots(frame::jit_monitor_size_in_4_byte_units); 2427 2428 // Compiled code's Frame Pointer 2429 // 2430 // z/Architecture stack pointer 2431 frame_pointer(Z_R15); // Z_SP 2432 2433 // Interpreter stores its frame pointer in a register which is 2434 // stored to the stack by I2CAdaptors. I2CAdaptors convert from 2435 // interpreted java to compiled java. 2436 // 2437 // Z_state holds pointer to caller's cInterpreter. 2438 interpreter_frame_pointer(Z_R7); // Z_state 2439 2440 // Use alignment_in_bytes instead of log_2_of_alignment_in_bits. 2441 stack_alignment(frame::alignment_in_bytes); 2442 2443 in_preserve_stack_slots(frame::jit_in_preserve_size_in_4_byte_units); 2444 2445 // A `slot' is assumed 4 bytes here! 2446 // out_preserve_stack_slots(frame::jit_out_preserve_size_in_4_byte_units); 2447 2448 // Number of outgoing stack slots killed above the 2449 // out_preserve_stack_slots for calls to C. Supports the var-args 2450 // backing area for register parms. 2451 varargs_C_out_slots_killed(((frame::z_abi_160_size - frame::z_jit_out_preserve_size) / VMRegImpl::stack_slot_size)); 2452 2453 // The after-PROLOG location of the return address. Location of 2454 // return address specifies a type (REG or STACK) and a number 2455 // representing the register number (i.e. - use a register name) or 2456 // stack slot. 2457 return_addr(REG Z_R14); 2458 2459 // This is the body of the function 2460 // 2461 // void Matcher::calling_convention(OptoRegPair* sig /* array of ideal regs */, 2462 // uint length /* length of array */, 2463 // bool is_outgoing) 2464 // 2465 // The `sig' array is to be updated. Sig[j] represents the location 2466 // of the j-th argument, either a register or a stack slot. 2467 2468 // Body of function which returns an integer array locating 2469 // arguments either in registers or in stack slots. Passed an array 2470 // of ideal registers called "sig" and a "length" count. Stack-slot 2471 // offsets are based on outgoing arguments, i.e. a CALLER setting up 2472 // arguments for a CALLEE. Incoming stack arguments are 2473 // automatically biased by the preserve_stack_slots field above. 2474 calling_convention %{ 2475 // No difference between ingoing/outgoing just pass false. 2476 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); 2477 %} 2478 2479 // Body of function which returns an integer array locating 2480 // arguments either in registers or in stack slots. Passed an array 2481 // of ideal registers called "sig" and a "length" count. Stack-slot 2482 // offsets are based on outgoing arguments, i.e. a CALLER setting up 2483 // arguments for a CALLEE. Incoming stack arguments are 2484 // automatically biased by the preserve_stack_slots field above. 2485 c_calling_convention %{ 2486 // This is obviously always outgoing. 2487 // C argument must be in register AND stack slot. 2488 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 2489 %} 2490 2491 // Location of native (C/C++) and interpreter return values. This 2492 // is specified to be the same as Java. In the 32-bit VM, long 2493 // values are actually returned from native calls in O0:O1 and 2494 // returned to the interpreter in I0:I1. The copying to and from 2495 // the register pairs is done by the appropriate call and epilog 2496 // opcodes. This simplifies the register allocator. 2497 // 2498 // Use register pair for c return value. 2499 c_return_value %{ 2500 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values"); 2501 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num }; 2502 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num }; 2503 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 2504 %} 2505 2506 // Use register pair for return value. 2507 // Location of compiled Java return values. Same as C 2508 return_value %{ 2509 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values"); 2510 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num }; 2511 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num }; 2512 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 2513 %} 2514 %} 2515 2516 2517 //----------ATTRIBUTES--------------------------------------------------------- 2518 2519 //----------Operand Attributes------------------------------------------------- 2520 op_attrib op_cost(1); // Required cost attribute 2521 2522 //----------Instruction Attributes--------------------------------------------- 2523 2524 // Cost attribute. required. 2525 ins_attrib ins_cost(DEFAULT_COST); 2526 2527 // Is this instruction a non-matching short branch variant of some 2528 // long branch? Not required. 2529 ins_attrib ins_short_branch(0); 2530 2531 // Indicates this is a trap based check node and final control-flow fixup 2532 // must generate a proper fall through. 2533 ins_attrib ins_is_TrapBasedCheckNode(true); 2534 2535 // Attribute of instruction to tell how many constants the instruction will generate. 2536 // (optional attribute). Default: 0. 2537 ins_attrib ins_num_consts(0); 2538 2539 // Required alignment attribute (must be a power of 2) 2540 // specifies the alignment that some part of the instruction (not 2541 // necessarily the start) requires. If > 1, a compute_padding() 2542 // function must be provided for the instruction. 2543 // 2544 // WARNING: Don't use size(FIXED_SIZE) or size(VARIABLE_SIZE) in 2545 // instructions which depend on the proper alignment, because the 2546 // desired alignment isn't guaranteed for the call to "emit()" during 2547 // the size computation. 2548 ins_attrib ins_alignment(1); 2549 2550 // Enforce/prohibit rematerializations. 2551 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)' 2552 // then rematerialization of that instruction is prohibited and the 2553 // instruction's value will be spilled if necessary. 2554 // - If an instruction is attributed with 'ins_should_rematerialize(true)' 2555 // then rematerialization is enforced and the instruction's value will 2556 // never get spilled. a copy of the instruction will be inserted if 2557 // necessary. 2558 // Note: this may result in rematerializations in front of every use. 2559 // (optional attribute) 2560 ins_attrib ins_cannot_rematerialize(false); 2561 ins_attrib ins_should_rematerialize(false); 2562 2563 //----------OPERANDS----------------------------------------------------------- 2564 // Operand definitions must precede instruction definitions for correct 2565 // parsing in the ADLC because operands constitute user defined types 2566 // which are used in instruction definitions. 2567 2568 //----------Simple Operands---------------------------------------------------- 2569 // Immediate Operands 2570 // Please note: 2571 // Formats are generated automatically for constants and base registers. 2572 2573 //---------------------------------------------- 2574 // SIGNED (shorter than INT) immediate operands 2575 //---------------------------------------------- 2576 2577 // Byte Immediate: constant 'int -1' 2578 operand immB_minus1() %{ 2579 // sign-ext constant zero-ext constant 2580 predicate((n->get_int() == -1) || ((n->get_int()&0x000000ff) == 0x000000ff)); 2581 match(ConI); 2582 op_cost(1); 2583 format %{ %} 2584 interface(CONST_INTER); 2585 %} 2586 2587 // Byte Immediate: constant, but not 'int 0' nor 'int -1'. 2588 operand immB_n0m1() %{ 2589 // sign-ext constant zero-ext constant 2590 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x000000ff) != 0x000000ff); 2591 match(ConI); 2592 op_cost(1); 2593 format %{ %} 2594 interface(CONST_INTER); 2595 %} 2596 2597 // Short Immediate: constant 'int -1' 2598 operand immS_minus1() %{ 2599 // sign-ext constant zero-ext constant 2600 predicate((n->get_int() == -1) || ((n->get_int()&0x0000ffff) == 0x0000ffff)); 2601 match(ConI); 2602 op_cost(1); 2603 format %{ %} 2604 interface(CONST_INTER); 2605 %} 2606 2607 // Short Immediate: constant, but not 'int 0' nor 'int -1'. 2608 operand immS_n0m1() %{ 2609 // sign-ext constant zero-ext constant 2610 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x0000ffff) != 0x0000ffff); 2611 match(ConI); 2612 op_cost(1); 2613 format %{ %} 2614 interface(CONST_INTER); 2615 %} 2616 2617 //----------------------------------------- 2618 // SIGNED INT immediate operands 2619 //----------------------------------------- 2620 2621 // Integer Immediate: 32-bit 2622 operand immI() %{ 2623 match(ConI); 2624 op_cost(1); 2625 format %{ %} 2626 interface(CONST_INTER); 2627 %} 2628 2629 // Int Immediate: 20-bit 2630 operand immI20() %{ 2631 predicate(Immediate::is_simm20(n->get_int())); 2632 match(ConI); 2633 op_cost(1); 2634 format %{ %} 2635 interface(CONST_INTER); 2636 %} 2637 2638 // Integer Immediate: 16-bit 2639 operand immI16() %{ 2640 predicate(Immediate::is_simm16(n->get_int())); 2641 match(ConI); 2642 op_cost(1); 2643 format %{ %} 2644 interface(CONST_INTER); 2645 %} 2646 2647 // Integer Immediate: 8-bit 2648 operand immI8() %{ 2649 predicate(Immediate::is_simm8(n->get_int())); 2650 match(ConI); 2651 op_cost(1); 2652 format %{ %} 2653 interface(CONST_INTER); 2654 %} 2655 2656 // Integer Immediate: constant 'int 0' 2657 operand immI_0() %{ 2658 predicate(n->get_int() == 0); 2659 match(ConI); 2660 op_cost(1); 2661 format %{ %} 2662 interface(CONST_INTER); 2663 %} 2664 2665 // Integer Immediate: constant 'int -1' 2666 operand immI_minus1() %{ 2667 predicate(n->get_int() == -1); 2668 match(ConI); 2669 op_cost(1); 2670 format %{ %} 2671 interface(CONST_INTER); 2672 %} 2673 2674 // Integer Immediate: constant, but not 'int 0' nor 'int -1'. 2675 operand immI_n0m1() %{ 2676 predicate(n->get_int() != 0 && n->get_int() != -1); 2677 match(ConI); 2678 op_cost(1); 2679 format %{ %} 2680 interface(CONST_INTER); 2681 %} 2682 2683 //------------------------------------------- 2684 // UNSIGNED INT immediate operands 2685 //------------------------------------------- 2686 2687 // Unsigned Integer Immediate: 32-bit 2688 operand uimmI() %{ 2689 match(ConI); 2690 op_cost(1); 2691 format %{ %} 2692 interface(CONST_INTER); 2693 %} 2694 2695 // Unsigned Integer Immediate: 16-bit 2696 operand uimmI16() %{ 2697 predicate(Immediate::is_uimm16(n->get_int())); 2698 match(ConI); 2699 op_cost(1); 2700 format %{ %} 2701 interface(CONST_INTER); 2702 %} 2703 2704 // Unsigned Integer Immediate: 12-bit 2705 operand uimmI12() %{ 2706 predicate(Immediate::is_uimm12(n->get_int())); 2707 match(ConI); 2708 op_cost(1); 2709 format %{ %} 2710 interface(CONST_INTER); 2711 %} 2712 2713 // Unsigned Integer Immediate: 12-bit 2714 operand uimmI8() %{ 2715 predicate(Immediate::is_uimm8(n->get_int())); 2716 match(ConI); 2717 op_cost(1); 2718 format %{ %} 2719 interface(CONST_INTER); 2720 %} 2721 2722 // Integer Immediate: 6-bit 2723 operand uimmI6() %{ 2724 predicate(Immediate::is_uimm(n->get_int(), 6)); 2725 match(ConI); 2726 op_cost(1); 2727 format %{ %} 2728 interface(CONST_INTER); 2729 %} 2730 2731 // Integer Immediate: 5-bit 2732 operand uimmI5() %{ 2733 predicate(Immediate::is_uimm(n->get_int(), 5)); 2734 match(ConI); 2735 op_cost(1); 2736 format %{ %} 2737 interface(CONST_INTER); 2738 %} 2739 2740 // Length for SS instructions, given in DWs, 2741 // possible range [1..512], i.e. [8..4096] Bytes 2742 // used range [1..256], i.e. [8..2048] Bytes 2743 // operand type int 2744 // Unsigned Integer Immediate: 9-bit 2745 operand SSlenDW() %{ 2746 predicate(Immediate::is_uimm8(n->get_long()-1)); 2747 match(ConL); 2748 op_cost(1); 2749 format %{ %} 2750 interface(CONST_INTER); 2751 %} 2752 2753 //------------------------------------------ 2754 // (UN)SIGNED INT specific values 2755 //------------------------------------------ 2756 2757 // Integer Immediate: the value 1 2758 operand immI_1() %{ 2759 predicate(n->get_int() == 1); 2760 match(ConI); 2761 op_cost(1); 2762 format %{ %} 2763 interface(CONST_INTER); 2764 %} 2765 2766 // Integer Immediate: the value 16. 2767 operand immI_16() %{ 2768 predicate(n->get_int() == 16); 2769 match(ConI); 2770 op_cost(1); 2771 format %{ %} 2772 interface(CONST_INTER); 2773 %} 2774 2775 // Integer Immediate: the value 24. 2776 operand immI_24() %{ 2777 predicate(n->get_int() == 24); 2778 match(ConI); 2779 op_cost(1); 2780 format %{ %} 2781 interface(CONST_INTER); 2782 %} 2783 2784 // Integer Immediate: the value 255 2785 operand immI_255() %{ 2786 predicate(n->get_int() == 255); 2787 match(ConI); 2788 op_cost(1); 2789 format %{ %} 2790 interface(CONST_INTER); 2791 %} 2792 2793 // Integer Immediate: the values 32-63 2794 operand immI_32_63() %{ 2795 predicate(n->get_int() >= 32 && n->get_int() <= 63); 2796 match(ConI); 2797 op_cost(1); 2798 format %{ %} 2799 interface(CONST_INTER); 2800 %} 2801 2802 // Unsigned Integer Immediate: LL-part, extended by 1s. 2803 operand uimmI_LL1() %{ 2804 predicate((n->get_int() & 0xFFFF0000) == 0xFFFF0000); 2805 match(ConI); 2806 op_cost(1); 2807 format %{ %} 2808 interface(CONST_INTER); 2809 %} 2810 2811 // Unsigned Integer Immediate: LH-part, extended by 1s. 2812 operand uimmI_LH1() %{ 2813 predicate((n->get_int() & 0xFFFF) == 0xFFFF); 2814 match(ConI); 2815 op_cost(1); 2816 format %{ %} 2817 interface(CONST_INTER); 2818 %} 2819 2820 //------------------------------------------ 2821 // SIGNED LONG immediate operands 2822 //------------------------------------------ 2823 2824 operand immL() %{ 2825 match(ConL); 2826 op_cost(1); 2827 format %{ %} 2828 interface(CONST_INTER); 2829 %} 2830 2831 // Long Immediate: 32-bit 2832 operand immL32() %{ 2833 predicate(Immediate::is_simm32(n->get_long())); 2834 match(ConL); 2835 op_cost(1); 2836 format %{ %} 2837 interface(CONST_INTER); 2838 %} 2839 2840 // Long Immediate: 20-bit 2841 operand immL20() %{ 2842 predicate(Immediate::is_simm20(n->get_long())); 2843 match(ConL); 2844 op_cost(1); 2845 format %{ %} 2846 interface(CONST_INTER); 2847 %} 2848 2849 // Long Immediate: 16-bit 2850 operand immL16() %{ 2851 predicate(Immediate::is_simm16(n->get_long())); 2852 match(ConL); 2853 op_cost(1); 2854 format %{ %} 2855 interface(CONST_INTER); 2856 %} 2857 2858 // Long Immediate: 8-bit 2859 operand immL8() %{ 2860 predicate(Immediate::is_simm8(n->get_long())); 2861 match(ConL); 2862 op_cost(1); 2863 format %{ %} 2864 interface(CONST_INTER); 2865 %} 2866 2867 //-------------------------------------------- 2868 // UNSIGNED LONG immediate operands 2869 //-------------------------------------------- 2870 2871 operand uimmL32() %{ 2872 predicate(Immediate::is_uimm32(n->get_long())); 2873 match(ConL); 2874 op_cost(1); 2875 format %{ %} 2876 interface(CONST_INTER); 2877 %} 2878 2879 // Unsigned Long Immediate: 16-bit 2880 operand uimmL16() %{ 2881 predicate(Immediate::is_uimm16(n->get_long())); 2882 match(ConL); 2883 op_cost(1); 2884 format %{ %} 2885 interface(CONST_INTER); 2886 %} 2887 2888 // Unsigned Long Immediate: 12-bit 2889 operand uimmL12() %{ 2890 predicate(Immediate::is_uimm12(n->get_long())); 2891 match(ConL); 2892 op_cost(1); 2893 format %{ %} 2894 interface(CONST_INTER); 2895 %} 2896 2897 // Unsigned Long Immediate: 8-bit 2898 operand uimmL8() %{ 2899 predicate(Immediate::is_uimm8(n->get_long())); 2900 match(ConL); 2901 op_cost(1); 2902 format %{ %} 2903 interface(CONST_INTER); 2904 %} 2905 2906 //------------------------------------------- 2907 // (UN)SIGNED LONG specific values 2908 //------------------------------------------- 2909 2910 // Long Immediate: the value FF 2911 operand immL_FF() %{ 2912 predicate(n->get_long() == 0xFFL); 2913 match(ConL); 2914 op_cost(1); 2915 format %{ %} 2916 interface(CONST_INTER); 2917 %} 2918 2919 // Long Immediate: the value FFFF 2920 operand immL_FFFF() %{ 2921 predicate(n->get_long() == 0xFFFFL); 2922 match(ConL); 2923 op_cost(1); 2924 format %{ %} 2925 interface(CONST_INTER); 2926 %} 2927 2928 // Long Immediate: the value FFFFFFFF 2929 operand immL_FFFFFFFF() %{ 2930 predicate(n->get_long() == 0xFFFFFFFFL); 2931 match(ConL); 2932 op_cost(1); 2933 format %{ %} 2934 interface(CONST_INTER); 2935 %} 2936 2937 operand immL_0() %{ 2938 predicate(n->get_long() == 0L); 2939 match(ConL); 2940 op_cost(1); 2941 format %{ %} 2942 interface(CONST_INTER); 2943 %} 2944 2945 // Unsigned Long Immediate: LL-part, extended by 1s. 2946 operand uimmL_LL1() %{ 2947 predicate((n->get_long() & 0xFFFFFFFFFFFF0000L) == 0xFFFFFFFFFFFF0000L); 2948 match(ConL); 2949 op_cost(1); 2950 format %{ %} 2951 interface(CONST_INTER); 2952 %} 2953 2954 // Unsigned Long Immediate: LH-part, extended by 1s. 2955 operand uimmL_LH1() %{ 2956 predicate((n->get_long() & 0xFFFFFFFF0000FFFFL) == 0xFFFFFFFF0000FFFFL); 2957 match(ConL); 2958 op_cost(1); 2959 format %{ %} 2960 interface(CONST_INTER); 2961 %} 2962 2963 // Unsigned Long Immediate: HL-part, extended by 1s. 2964 operand uimmL_HL1() %{ 2965 predicate((n->get_long() & 0xFFFF0000FFFFFFFFL) == 0xFFFF0000FFFFFFFFL); 2966 match(ConL); 2967 op_cost(1); 2968 format %{ %} 2969 interface(CONST_INTER); 2970 %} 2971 2972 // Unsigned Long Immediate: HH-part, extended by 1s. 2973 operand uimmL_HH1() %{ 2974 predicate((n->get_long() & 0xFFFFFFFFFFFFL) == 0xFFFFFFFFFFFFL); 2975 match(ConL); 2976 op_cost(1); 2977 format %{ %} 2978 interface(CONST_INTER); 2979 %} 2980 2981 // Long Immediate: low 32-bit mask 2982 operand immL_32bits() %{ 2983 predicate(n->get_long() == 0xFFFFFFFFL); 2984 match(ConL); 2985 op_cost(1); 2986 format %{ %} 2987 interface(CONST_INTER); 2988 %} 2989 2990 //-------------------------------------- 2991 // POINTER immediate operands 2992 //-------------------------------------- 2993 2994 // Pointer Immediate: 64-bit 2995 operand immP() %{ 2996 match(ConP); 2997 op_cost(1); 2998 format %{ %} 2999 interface(CONST_INTER); 3000 %} 3001 3002 // Pointer Immediate: 32-bit 3003 operand immP32() %{ 3004 predicate(Immediate::is_uimm32(n->get_ptr())); 3005 match(ConP); 3006 op_cost(1); 3007 format %{ %} 3008 interface(CONST_INTER); 3009 %} 3010 3011 // Pointer Immediate: 16-bit 3012 operand immP16() %{ 3013 predicate(Immediate::is_uimm16(n->get_ptr())); 3014 match(ConP); 3015 op_cost(1); 3016 format %{ %} 3017 interface(CONST_INTER); 3018 %} 3019 3020 // Pointer Immediate: 8-bit 3021 operand immP8() %{ 3022 predicate(Immediate::is_uimm8(n->get_ptr())); 3023 match(ConP); 3024 op_cost(1); 3025 format %{ %} 3026 interface(CONST_INTER); 3027 %} 3028 3029 //----------------------------------- 3030 // POINTER specific values 3031 //----------------------------------- 3032 3033 // Pointer Immediate: NULL 3034 operand immP0() %{ 3035 predicate(n->get_ptr() == 0); 3036 match(ConP); 3037 op_cost(1); 3038 format %{ %} 3039 interface(CONST_INTER); 3040 %} 3041 3042 //--------------------------------------------- 3043 // NARROW POINTER immediate operands 3044 //--------------------------------------------- 3045 3046 // Narrow Pointer Immediate 3047 operand immN() %{ 3048 match(ConN); 3049 op_cost(1); 3050 format %{ %} 3051 interface(CONST_INTER); 3052 %} 3053 3054 operand immNKlass() %{ 3055 match(ConNKlass); 3056 op_cost(1); 3057 format %{ %} 3058 interface(CONST_INTER); 3059 %} 3060 3061 // Narrow Pointer Immediate 3062 operand immN8() %{ 3063 predicate(Immediate::is_uimm8(n->get_narrowcon())); 3064 match(ConN); 3065 op_cost(1); 3066 format %{ %} 3067 interface(CONST_INTER); 3068 %} 3069 3070 // Narrow NULL Pointer Immediate 3071 operand immN0() %{ 3072 predicate(n->get_narrowcon() == 0); 3073 match(ConN); 3074 op_cost(1); 3075 format %{ %} 3076 interface(CONST_INTER); 3077 %} 3078 3079 // FLOAT and DOUBLE immediate operands 3080 3081 // Double Immediate 3082 operand immD() %{ 3083 match(ConD); 3084 op_cost(1); 3085 format %{ %} 3086 interface(CONST_INTER); 3087 %} 3088 3089 // Double Immediate: +-0 3090 operand immDpm0() %{ 3091 predicate(n->getd() == 0); 3092 match(ConD); 3093 op_cost(1); 3094 format %{ %} 3095 interface(CONST_INTER); 3096 %} 3097 3098 // Double Immediate: +0 3099 operand immDp0() %{ 3100 predicate(jlong_cast(n->getd()) == 0); 3101 match(ConD); 3102 op_cost(1); 3103 format %{ %} 3104 interface(CONST_INTER); 3105 %} 3106 3107 // Float Immediate 3108 operand immF() %{ 3109 match(ConF); 3110 op_cost(1); 3111 format %{ %} 3112 interface(CONST_INTER); 3113 %} 3114 3115 // Float Immediate: +-0 3116 operand immFpm0() %{ 3117 predicate(n->getf() == 0); 3118 match(ConF); 3119 op_cost(1); 3120 format %{ %} 3121 interface(CONST_INTER); 3122 %} 3123 3124 // Float Immediate: +0 3125 operand immFp0() %{ 3126 predicate(jint_cast(n->getf()) == 0); 3127 match(ConF); 3128 op_cost(1); 3129 format %{ %} 3130 interface(CONST_INTER); 3131 %} 3132 3133 // End of Immediate Operands 3134 3135 // Integer Register Operands 3136 // Integer Register 3137 operand iRegI() %{ 3138 constraint(ALLOC_IN_RC(z_int_reg)); 3139 match(RegI); 3140 match(noArg_iRegI); 3141 match(rarg1RegI); 3142 match(rarg2RegI); 3143 match(rarg3RegI); 3144 match(rarg4RegI); 3145 match(rarg5RegI); 3146 match(noOdd_iRegI); 3147 match(revenRegI); 3148 match(roddRegI); 3149 format %{ %} 3150 interface(REG_INTER); 3151 %} 3152 3153 operand noArg_iRegI() %{ 3154 constraint(ALLOC_IN_RC(z_no_arg_int_reg)); 3155 match(RegI); 3156 format %{ %} 3157 interface(REG_INTER); 3158 %} 3159 3160 // Revenregi and roddRegI constitute and even-odd-pair. 3161 operand revenRegI() %{ 3162 constraint(ALLOC_IN_RC(z_rarg3_int_reg)); 3163 match(iRegI); 3164 format %{ %} 3165 interface(REG_INTER); 3166 %} 3167 3168 // Revenregi and roddRegI constitute and even-odd-pair. 3169 operand roddRegI() %{ 3170 constraint(ALLOC_IN_RC(z_rarg4_int_reg)); 3171 match(iRegI); 3172 format %{ %} 3173 interface(REG_INTER); 3174 %} 3175 3176 operand rarg1RegI() %{ 3177 constraint(ALLOC_IN_RC(z_rarg1_int_reg)); 3178 match(iRegI); 3179 format %{ %} 3180 interface(REG_INTER); 3181 %} 3182 3183 operand rarg2RegI() %{ 3184 constraint(ALLOC_IN_RC(z_rarg2_int_reg)); 3185 match(iRegI); 3186 format %{ %} 3187 interface(REG_INTER); 3188 %} 3189 3190 operand rarg3RegI() %{ 3191 constraint(ALLOC_IN_RC(z_rarg3_int_reg)); 3192 match(iRegI); 3193 format %{ %} 3194 interface(REG_INTER); 3195 %} 3196 3197 operand rarg4RegI() %{ 3198 constraint(ALLOC_IN_RC(z_rarg4_int_reg)); 3199 match(iRegI); 3200 format %{ %} 3201 interface(REG_INTER); 3202 %} 3203 3204 operand rarg5RegI() %{ 3205 constraint(ALLOC_IN_RC(z_rarg5_int_reg)); 3206 match(iRegI); 3207 format %{ %} 3208 interface(REG_INTER); 3209 %} 3210 3211 operand noOdd_iRegI() %{ 3212 constraint(ALLOC_IN_RC(z_no_odd_int_reg)); 3213 match(RegI); 3214 match(revenRegI); 3215 format %{ %} 3216 interface(REG_INTER); 3217 %} 3218 3219 // Pointer Register 3220 operand iRegP() %{ 3221 constraint(ALLOC_IN_RC(z_ptr_reg)); 3222 match(RegP); 3223 match(noArg_iRegP); 3224 match(rarg1RegP); 3225 match(rarg2RegP); 3226 match(rarg3RegP); 3227 match(rarg4RegP); 3228 match(rarg5RegP); 3229 match(revenRegP); 3230 match(roddRegP); 3231 format %{ %} 3232 interface(REG_INTER); 3233 %} 3234 3235 // thread operand 3236 operand threadRegP() %{ 3237 constraint(ALLOC_IN_RC(z_thread_ptr_reg)); 3238 match(RegP); 3239 format %{ "Z_THREAD" %} 3240 interface(REG_INTER); 3241 %} 3242 3243 operand noArg_iRegP() %{ 3244 constraint(ALLOC_IN_RC(z_no_arg_ptr_reg)); 3245 match(iRegP); 3246 format %{ %} 3247 interface(REG_INTER); 3248 %} 3249 3250 operand rarg1RegP() %{ 3251 constraint(ALLOC_IN_RC(z_rarg1_ptr_reg)); 3252 match(iRegP); 3253 format %{ %} 3254 interface(REG_INTER); 3255 %} 3256 3257 operand rarg2RegP() %{ 3258 constraint(ALLOC_IN_RC(z_rarg2_ptr_reg)); 3259 match(iRegP); 3260 format %{ %} 3261 interface(REG_INTER); 3262 %} 3263 3264 operand rarg3RegP() %{ 3265 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg)); 3266 match(iRegP); 3267 format %{ %} 3268 interface(REG_INTER); 3269 %} 3270 3271 operand rarg4RegP() %{ 3272 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg)); 3273 match(iRegP); 3274 format %{ %} 3275 interface(REG_INTER); 3276 %} 3277 3278 operand rarg5RegP() %{ 3279 constraint(ALLOC_IN_RC(z_rarg5_ptr_reg)); 3280 match(iRegP); 3281 format %{ %} 3282 interface(REG_INTER); 3283 %} 3284 3285 operand memoryRegP() %{ 3286 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3287 match(RegP); 3288 match(iRegP); 3289 match(threadRegP); 3290 format %{ %} 3291 interface(REG_INTER); 3292 %} 3293 3294 // Revenregp and roddRegP constitute and even-odd-pair. 3295 operand revenRegP() %{ 3296 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg)); 3297 match(iRegP); 3298 format %{ %} 3299 interface(REG_INTER); 3300 %} 3301 3302 // Revenregl and roddRegL constitute and even-odd-pair. 3303 operand roddRegP() %{ 3304 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg)); 3305 match(iRegP); 3306 format %{ %} 3307 interface(REG_INTER); 3308 %} 3309 3310 operand lock_ptr_RegP() %{ 3311 constraint(ALLOC_IN_RC(z_lock_ptr_reg)); 3312 match(RegP); 3313 format %{ %} 3314 interface(REG_INTER); 3315 %} 3316 3317 operand rscratch2RegP() %{ 3318 constraint(ALLOC_IN_RC(z_rscratch2_bits64_reg)); 3319 match(RegP); 3320 format %{ %} 3321 interface(REG_INTER); 3322 %} 3323 3324 operand iRegN() %{ 3325 constraint(ALLOC_IN_RC(z_int_reg)); 3326 match(RegN); 3327 match(noArg_iRegN); 3328 match(rarg1RegN); 3329 match(rarg2RegN); 3330 match(rarg3RegN); 3331 match(rarg4RegN); 3332 match(rarg5RegN); 3333 format %{ %} 3334 interface(REG_INTER); 3335 %} 3336 3337 operand noArg_iRegN() %{ 3338 constraint(ALLOC_IN_RC(z_no_arg_int_reg)); 3339 match(iRegN); 3340 format %{ %} 3341 interface(REG_INTER); 3342 %} 3343 3344 operand rarg1RegN() %{ 3345 constraint(ALLOC_IN_RC(z_rarg1_int_reg)); 3346 match(iRegN); 3347 format %{ %} 3348 interface(REG_INTER); 3349 %} 3350 3351 operand rarg2RegN() %{ 3352 constraint(ALLOC_IN_RC(z_rarg2_int_reg)); 3353 match(iRegN); 3354 format %{ %} 3355 interface(REG_INTER); 3356 %} 3357 3358 operand rarg3RegN() %{ 3359 constraint(ALLOC_IN_RC(z_rarg3_int_reg)); 3360 match(iRegN); 3361 format %{ %} 3362 interface(REG_INTER); 3363 %} 3364 3365 operand rarg4RegN() %{ 3366 constraint(ALLOC_IN_RC(z_rarg4_int_reg)); 3367 match(iRegN); 3368 format %{ %} 3369 interface(REG_INTER); 3370 %} 3371 3372 operand rarg5RegN() %{ 3373 constraint(ALLOC_IN_RC(z_rarg5_ptrN_reg)); 3374 match(iRegN); 3375 format %{ %} 3376 interface(REG_INTER); 3377 %} 3378 3379 // Long Register 3380 operand iRegL() %{ 3381 constraint(ALLOC_IN_RC(z_long_reg)); 3382 match(RegL); 3383 match(revenRegL); 3384 match(roddRegL); 3385 match(rarg1RegL); 3386 match(rarg5RegL); 3387 format %{ %} 3388 interface(REG_INTER); 3389 %} 3390 3391 // Revenregl and roddRegL constitute and even-odd-pair. 3392 operand revenRegL() %{ 3393 constraint(ALLOC_IN_RC(z_rarg3_long_reg)); 3394 match(iRegL); 3395 format %{ %} 3396 interface(REG_INTER); 3397 %} 3398 3399 // Revenregl and roddRegL constitute and even-odd-pair. 3400 operand roddRegL() %{ 3401 constraint(ALLOC_IN_RC(z_rarg4_long_reg)); 3402 match(iRegL); 3403 format %{ %} 3404 interface(REG_INTER); 3405 %} 3406 3407 operand rarg1RegL() %{ 3408 constraint(ALLOC_IN_RC(z_rarg1_long_reg)); 3409 match(iRegL); 3410 format %{ %} 3411 interface(REG_INTER); 3412 %} 3413 3414 operand rarg5RegL() %{ 3415 constraint(ALLOC_IN_RC(z_rarg5_long_reg)); 3416 match(iRegL); 3417 format %{ %} 3418 interface(REG_INTER); 3419 %} 3420 3421 // Condition Code Flag Registers 3422 operand flagsReg() %{ 3423 constraint(ALLOC_IN_RC(z_condition_reg)); 3424 match(RegFlags); 3425 format %{ "CR" %} 3426 interface(REG_INTER); 3427 %} 3428 3429 // Condition Code Flag Registers for rules with result tuples 3430 operand TD_flagsReg() %{ 3431 constraint(ALLOC_IN_RC(z_condition_reg)); 3432 match(RegFlags); 3433 format %{ "CR" %} 3434 interface(REG_TUPLE_DEST_INTER); 3435 %} 3436 3437 operand regD() %{ 3438 constraint(ALLOC_IN_RC(z_dbl_reg)); 3439 match(RegD); 3440 format %{ %} 3441 interface(REG_INTER); 3442 %} 3443 3444 operand rscratchRegD() %{ 3445 constraint(ALLOC_IN_RC(z_rscratch1_dbl_reg)); 3446 match(RegD); 3447 format %{ %} 3448 interface(REG_INTER); 3449 %} 3450 3451 operand regF() %{ 3452 constraint(ALLOC_IN_RC(z_flt_reg)); 3453 match(RegF); 3454 format %{ %} 3455 interface(REG_INTER); 3456 %} 3457 3458 operand rscratchRegF() %{ 3459 constraint(ALLOC_IN_RC(z_rscratch1_flt_reg)); 3460 match(RegF); 3461 format %{ %} 3462 interface(REG_INTER); 3463 %} 3464 3465 // Special Registers 3466 3467 // Method Register 3468 operand inline_cache_regP(iRegP reg) %{ 3469 constraint(ALLOC_IN_RC(z_r9_regP)); // inline_cache_reg 3470 match(reg); 3471 format %{ %} 3472 interface(REG_INTER); 3473 %} 3474 3475 operand compiler_method_oop_regP(iRegP reg) %{ 3476 constraint(ALLOC_IN_RC(z_r1_RegP)); // compiler_method_oop_reg 3477 match(reg); 3478 format %{ %} 3479 interface(REG_INTER); 3480 %} 3481 3482 operand interpreter_method_oop_regP(iRegP reg) %{ 3483 constraint(ALLOC_IN_RC(z_r9_regP)); // interpreter_method_oop_reg 3484 match(reg); 3485 format %{ %} 3486 interface(REG_INTER); 3487 %} 3488 3489 // Operands to remove register moves in unscaled mode. 3490 // Match read/write registers with an EncodeP node if neither shift nor add are required. 3491 operand iRegP2N(iRegP reg) %{ 3492 predicate(Universe::narrow_oop_shift() == 0 && _leaf->as_EncodeP()->in(0) == NULL); 3493 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3494 match(EncodeP reg); 3495 format %{ "$reg" %} 3496 interface(REG_INTER) 3497 %} 3498 3499 operand iRegN2P(iRegN reg) %{ 3500 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0 && 3501 _leaf->as_DecodeN()->in(0) == NULL); 3502 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3503 match(DecodeN reg); 3504 format %{ "$reg" %} 3505 interface(REG_INTER) 3506 %} 3507 3508 3509 //----------Complex Operands--------------------------------------------------- 3510 3511 // Indirect Memory Reference 3512 operand indirect(memoryRegP base) %{ 3513 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3514 match(base); 3515 op_cost(1); 3516 format %{ "#0[,$base]" %} 3517 interface(MEMORY_INTER) %{ 3518 base($base); 3519 index(0xffffFFFF); // noreg 3520 scale(0x0); 3521 disp(0x0); 3522 %} 3523 %} 3524 3525 // Indirect with Offset (long) 3526 operand indOffset20(memoryRegP base, immL20 offset) %{ 3527 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3528 match(AddP base offset); 3529 op_cost(1); 3530 format %{ "$offset[,$base]" %} 3531 interface(MEMORY_INTER) %{ 3532 base($base); 3533 index(0xffffFFFF); // noreg 3534 scale(0x0); 3535 disp($offset); 3536 %} 3537 %} 3538 3539 operand indOffset20Narrow(iRegN base, immL20 offset) %{ 3540 predicate(Matcher::narrow_oop_use_complex_address()); 3541 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3542 match(AddP (DecodeN base) offset); 3543 op_cost(1); 3544 format %{ "$offset[,$base]" %} 3545 interface(MEMORY_INTER) %{ 3546 base($base); 3547 index(0xffffFFFF); // noreg 3548 scale(0x0); 3549 disp($offset); 3550 %} 3551 %} 3552 3553 // Indirect with Offset (short) 3554 operand indOffset12(memoryRegP base, uimmL12 offset) %{ 3555 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3556 match(AddP base offset); 3557 op_cost(1); 3558 format %{ "$offset[[,$base]]" %} 3559 interface(MEMORY_INTER) %{ 3560 base($base); 3561 index(0xffffFFFF); // noreg 3562 scale(0x0); 3563 disp($offset); 3564 %} 3565 %} 3566 3567 operand indOffset12Narrow(iRegN base, uimmL12 offset) %{ 3568 predicate(Matcher::narrow_oop_use_complex_address()); 3569 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3570 match(AddP (DecodeN base) offset); 3571 op_cost(1); 3572 format %{ "$offset[[,$base]]" %} 3573 interface(MEMORY_INTER) %{ 3574 base($base); 3575 index(0xffffFFFF); // noreg 3576 scale(0x0); 3577 disp($offset); 3578 %} 3579 %} 3580 3581 // Indirect with Register Index 3582 operand indIndex(memoryRegP base, iRegL index) %{ 3583 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3584 match(AddP base index); 3585 op_cost(1); 3586 format %{ "#0[($index,$base)]" %} 3587 interface(MEMORY_INTER) %{ 3588 base($base); 3589 index($index); 3590 scale(0x0); 3591 disp(0x0); 3592 %} 3593 %} 3594 3595 // Indirect with Offset (long) and index 3596 operand indOffset20index(memoryRegP base, immL20 offset, iRegL index) %{ 3597 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3598 match(AddP (AddP base index) offset); 3599 op_cost(1); 3600 format %{ "$offset[($index,$base)]" %} 3601 interface(MEMORY_INTER) %{ 3602 base($base); 3603 index($index); 3604 scale(0x0); 3605 disp($offset); 3606 %} 3607 %} 3608 3609 operand indOffset20indexNarrow(iRegN base, immL20 offset, iRegL index) %{ 3610 predicate(Matcher::narrow_oop_use_complex_address()); 3611 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3612 match(AddP (AddP (DecodeN base) index) offset); 3613 op_cost(1); 3614 format %{ "$offset[($index,$base)]" %} 3615 interface(MEMORY_INTER) %{ 3616 base($base); 3617 index($index); 3618 scale(0x0); 3619 disp($offset); 3620 %} 3621 %} 3622 3623 // Indirect with Offset (short) and index 3624 operand indOffset12index(memoryRegP base, uimmL12 offset, iRegL index) %{ 3625 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3626 match(AddP (AddP base index) offset); 3627 op_cost(1); 3628 format %{ "$offset[[($index,$base)]]" %} 3629 interface(MEMORY_INTER) %{ 3630 base($base); 3631 index($index); 3632 scale(0x0); 3633 disp($offset); 3634 %} 3635 %} 3636 3637 operand indOffset12indexNarrow(iRegN base, uimmL12 offset, iRegL index) %{ 3638 predicate(Matcher::narrow_oop_use_complex_address()); 3639 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3640 match(AddP (AddP (DecodeN base) index) offset); 3641 op_cost(1); 3642 format %{ "$offset[[($index,$base)]]" %} 3643 interface(MEMORY_INTER) %{ 3644 base($base); 3645 index($index); 3646 scale(0x0); 3647 disp($offset); 3648 %} 3649 %} 3650 3651 //----------Special Memory Operands-------------------------------------------- 3652 3653 // Stack Slot Operand 3654 // This operand is used for loading and storing temporary values on 3655 // the stack where a match requires a value to flow through memory. 3656 operand stackSlotI(sRegI reg) %{ 3657 constraint(ALLOC_IN_RC(stack_slots)); 3658 op_cost(1); 3659 format %{ "[$reg(stackSlotI)]" %} 3660 interface(MEMORY_INTER) %{ 3661 base(0xf); // Z_SP 3662 index(0xffffFFFF); // noreg 3663 scale(0x0); 3664 disp($reg); // stack offset 3665 %} 3666 %} 3667 3668 operand stackSlotP(sRegP reg) %{ 3669 constraint(ALLOC_IN_RC(stack_slots)); 3670 op_cost(1); 3671 format %{ "[$reg(stackSlotP)]" %} 3672 interface(MEMORY_INTER) %{ 3673 base(0xf); // Z_SP 3674 index(0xffffFFFF); // noreg 3675 scale(0x0); 3676 disp($reg); // Stack Offset 3677 %} 3678 %} 3679 3680 operand stackSlotF(sRegF reg) %{ 3681 constraint(ALLOC_IN_RC(stack_slots)); 3682 op_cost(1); 3683 format %{ "[$reg(stackSlotF)]" %} 3684 interface(MEMORY_INTER) %{ 3685 base(0xf); // Z_SP 3686 index(0xffffFFFF); // noreg 3687 scale(0x0); 3688 disp($reg); // Stack Offset 3689 %} 3690 %} 3691 3692 operand stackSlotD(sRegD reg) %{ 3693 constraint(ALLOC_IN_RC(stack_slots)); 3694 op_cost(1); 3695 //match(RegD); 3696 format %{ "[$reg(stackSlotD)]" %} 3697 interface(MEMORY_INTER) %{ 3698 base(0xf); // Z_SP 3699 index(0xffffFFFF); // noreg 3700 scale(0x0); 3701 disp($reg); // Stack Offset 3702 %} 3703 %} 3704 3705 operand stackSlotL(sRegL reg) %{ 3706 constraint(ALLOC_IN_RC(stack_slots)); 3707 op_cost(1); //match(RegL); 3708 format %{ "[$reg(stackSlotL)]" %} 3709 interface(MEMORY_INTER) %{ 3710 base(0xf); // Z_SP 3711 index(0xffffFFFF); // noreg 3712 scale(0x0); 3713 disp($reg); // Stack Offset 3714 %} 3715 %} 3716 3717 // Operands for expressing Control Flow 3718 // NOTE: Label is a predefined operand which should not be redefined in 3719 // the AD file. It is generically handled within the ADLC. 3720 3721 //----------Conditional Branch Operands---------------------------------------- 3722 // Comparison Op - This is the operation of the comparison, and is limited to 3723 // the following set of codes: 3724 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 3725 // 3726 // Other attributes of the comparison, such as unsignedness, are specified 3727 // by the comparison instruction that sets a condition code flags register. 3728 // That result is represented by a flags operand whose subtype is appropriate 3729 // to the unsignedness (etc.) of the comparison. 3730 // 3731 // Later, the instruction which matches both the Comparison Op (a Bool) and 3732 // the flags (produced by the Cmp) specifies the coding of the comparison op 3733 // by matching a specific subtype of Bool operand below. 3734 3735 // INT cmpOps for CompareAndBranch and CompareAndTrap instructions should not 3736 // have mask bit #3 set. 3737 operand cmpOpT() %{ 3738 match(Bool); 3739 format %{ "" %} 3740 interface(COND_INTER) %{ 3741 equal(0x8); // Assembler::bcondEqual 3742 not_equal(0x6); // Assembler::bcondNotEqual 3743 less(0x4); // Assembler::bcondLow 3744 greater_equal(0xa); // Assembler::bcondNotLow 3745 less_equal(0xc); // Assembler::bcondNotHigh 3746 greater(0x2); // Assembler::bcondHigh 3747 overflow(0x1); // Assembler::bcondOverflow 3748 no_overflow(0xe); // Assembler::bcondNotOverflow 3749 %} 3750 %} 3751 3752 // When used for floating point comparisons: unordered is treated as less. 3753 operand cmpOpF() %{ 3754 match(Bool); 3755 format %{ "" %} 3756 interface(COND_INTER) %{ 3757 equal(0x8); 3758 not_equal(0x7); // Includes 'unordered'. 3759 less(0x5); // Includes 'unordered'. 3760 greater_equal(0xa); 3761 less_equal(0xd); // Includes 'unordered'. 3762 greater(0x2); 3763 overflow(0x0); // Not meaningful on z/Architecture. 3764 no_overflow(0x0); // leave unchanged (zero) therefore 3765 %} 3766 %} 3767 3768 // "Regular" cmpOp for int comparisons, includes bit #3 (overflow). 3769 operand cmpOp() %{ 3770 match(Bool); 3771 format %{ "" %} 3772 interface(COND_INTER) %{ 3773 equal(0x8); 3774 not_equal(0x7); // Includes 'unordered'. 3775 less(0x5); // Includes 'unordered'. 3776 greater_equal(0xa); 3777 less_equal(0xd); // Includes 'unordered'. 3778 greater(0x2); 3779 overflow(0x1); // Assembler::bcondOverflow 3780 no_overflow(0xe); // Assembler::bcondNotOverflow 3781 %} 3782 %} 3783 3784 //----------OPERAND CLASSES---------------------------------------------------- 3785 // Operand Classes are groups of operands that are used to simplify 3786 // instruction definitions by not requiring the AD writer to specify 3787 // seperate instructions for every form of operand when the 3788 // instruction accepts multiple operand types with the same basic 3789 // encoding and format. The classic case of this is memory operands. 3790 // Indirect is not included since its use is limited to Compare & Swap 3791 3792 // Most general memory operand, allows base, index, and long displacement. 3793 opclass memory(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow); 3794 opclass memoryRXY(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow); 3795 3796 // General memory operand, allows base, index, and short displacement. 3797 opclass memoryRX(indirect, indIndex, indOffset12, indOffset12Narrow, indOffset12index, indOffset12indexNarrow); 3798 3799 // Memory operand, allows only base and long displacement. 3800 opclass memoryRSY(indirect, indOffset20, indOffset20Narrow); 3801 3802 // Memory operand, allows only base and short displacement. 3803 opclass memoryRS(indirect, indOffset12, indOffset12Narrow); 3804 3805 // Operand classes to match encode and decode. 3806 opclass iRegN_P2N(iRegN); 3807 opclass iRegP_N2P(iRegP); 3808 3809 3810 //----------PIPELINE----------------------------------------------------------- 3811 pipeline %{ 3812 3813 //----------ATTRIBUTES--------------------------------------------------------- 3814 attributes %{ 3815 // z/Architecture instructions are of length 2, 4, or 6 bytes. 3816 variable_size_instructions; 3817 instruction_unit_size = 2; 3818 3819 // Meaningless on z/Architecture. 3820 max_instructions_per_bundle = 1; 3821 3822 // The z/Architecture processor fetches 64 bytes... 3823 instruction_fetch_unit_size = 64; 3824 3825 // ...in one line. 3826 instruction_fetch_units = 1 3827 %} 3828 3829 //----------RESOURCES---------------------------------------------------------- 3830 // Resources are the functional units available to the machine. 3831 resources( 3832 Z_BR, // branch unit 3833 Z_CR, // condition unit 3834 Z_FX1, // integer arithmetic unit 1 3835 Z_FX2, // integer arithmetic unit 2 3836 Z_LDST1, // load/store unit 1 3837 Z_LDST2, // load/store unit 2 3838 Z_FP1, // float arithmetic unit 1 3839 Z_FP2, // float arithmetic unit 2 3840 Z_LDST = Z_LDST1 | Z_LDST2, 3841 Z_FX = Z_FX1 | Z_FX2, 3842 Z_FP = Z_FP1 | Z_FP2 3843 ); 3844 3845 //----------PIPELINE DESCRIPTION----------------------------------------------- 3846 // Pipeline Description specifies the stages in the machine's pipeline. 3847 pipe_desc( 3848 // TODO: adapt 3849 Z_IF, // instruction fetch 3850 Z_IC, 3851 Z_D0, // decode 3852 Z_D1, // decode 3853 Z_D2, // decode 3854 Z_D3, // decode 3855 Z_Xfer1, 3856 Z_GD, // group definition 3857 Z_MP, // map 3858 Z_ISS, // issue 3859 Z_RF, // resource fetch 3860 Z_EX1, // execute (all units) 3861 Z_EX2, // execute (FP, LDST) 3862 Z_EX3, // execute (FP, LDST) 3863 Z_EX4, // execute (FP) 3864 Z_EX5, // execute (FP) 3865 Z_EX6, // execute (FP) 3866 Z_WB, // write back 3867 Z_Xfer2, 3868 Z_CP 3869 ); 3870 3871 //----------PIPELINE CLASSES--------------------------------------------------- 3872 // Pipeline Classes describe the stages in which input and output are 3873 // referenced by the hardware pipeline. 3874 3875 // Providing the `ins_pipe' declarations in the instruction 3876 // specifications seems to be of little use. So we use 3877 // `pipe_class_dummy' for all our instructions at present. 3878 pipe_class pipe_class_dummy() %{ 3879 single_instruction; 3880 fixed_latency(4); 3881 %} 3882 3883 // SIGTRAP based implicit range checks in compiled code. 3884 // Currently, no pipe classes are used on z/Architecture. 3885 pipe_class pipe_class_trap() %{ 3886 single_instruction; 3887 %} 3888 3889 pipe_class pipe_class_fx_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 3890 single_instruction; 3891 dst : Z_EX1(write); 3892 src1 : Z_RF(read); 3893 src2 : Z_RF(read); 3894 Z_FX : Z_RF; 3895 %} 3896 3897 pipe_class pipe_class_ldst(iRegP dst, memory mem) %{ 3898 single_instruction; 3899 mem : Z_RF(read); 3900 dst : Z_WB(write); 3901 Z_LDST : Z_RF; 3902 %} 3903 3904 define %{ 3905 MachNop = pipe_class_dummy; 3906 %} 3907 3908 %} 3909 3910 //----------INSTRUCTIONS------------------------------------------------------- 3911 3912 //---------- Chain stack slots between similar types -------- 3913 3914 // Load integer from stack slot. 3915 instruct stkI_to_regI(iRegI dst, stackSlotI src) %{ 3916 match(Set dst src); 3917 ins_cost(MEMORY_REF_COST); 3918 // TODO: s390 port size(FIXED_SIZE); 3919 format %{ "L $dst,$src\t # stk reload int" %} 3920 opcode(L_ZOPC); 3921 ins_encode(z_form_rt_mem(dst, src)); 3922 ins_pipe(pipe_class_dummy); 3923 %} 3924 3925 // Store integer to stack slot. 3926 instruct regI_to_stkI(stackSlotI dst, iRegI src) %{ 3927 match(Set dst src); 3928 ins_cost(MEMORY_REF_COST); 3929 // TODO: s390 port size(FIXED_SIZE); 3930 format %{ "ST $src,$dst\t # stk spill int" %} 3931 opcode(ST_ZOPC); 3932 ins_encode(z_form_rt_mem(src, dst)); // rs=rt 3933 ins_pipe(pipe_class_dummy); 3934 %} 3935 3936 // Load long from stack slot. 3937 instruct stkL_to_regL(iRegL dst, stackSlotL src) %{ 3938 match(Set dst src); 3939 ins_cost(MEMORY_REF_COST); 3940 // TODO: s390 port size(FIXED_SIZE); 3941 format %{ "LG $dst,$src\t # stk reload long" %} 3942 opcode(LG_ZOPC); 3943 ins_encode(z_form_rt_mem(dst, src)); 3944 ins_pipe(pipe_class_dummy); 3945 %} 3946 3947 // Store long to stack slot. 3948 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 3949 match(Set dst src); 3950 ins_cost(MEMORY_REF_COST); 3951 size(6); 3952 format %{ "STG $src,$dst\t # stk spill long" %} 3953 opcode(STG_ZOPC); 3954 ins_encode(z_form_rt_mem(src, dst)); // rs=rt 3955 ins_pipe(pipe_class_dummy); 3956 %} 3957 3958 // Load pointer from stack slot, 64-bit encoding. 3959 instruct stkP_to_regP(iRegP dst, stackSlotP src) %{ 3960 match(Set dst src); 3961 ins_cost(MEMORY_REF_COST); 3962 // TODO: s390 port size(FIXED_SIZE); 3963 format %{ "LG $dst,$src\t # stk reload ptr" %} 3964 opcode(LG_ZOPC); 3965 ins_encode(z_form_rt_mem(dst, src)); 3966 ins_pipe(pipe_class_dummy); 3967 %} 3968 3969 // Store pointer to stack slot. 3970 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 3971 match(Set dst src); 3972 ins_cost(MEMORY_REF_COST); 3973 // TODO: s390 port size(FIXED_SIZE); 3974 format %{ "STG $src,$dst\t # stk spill ptr" %} 3975 opcode(STG_ZOPC); 3976 ins_encode(z_form_rt_mem(src, dst)); // rs=rt 3977 ins_pipe(pipe_class_dummy); 3978 %} 3979 3980 // Float types 3981 3982 // Load float value from stack slot. 3983 instruct stkF_to_regF(regF dst, stackSlotF src) %{ 3984 match(Set dst src); 3985 ins_cost(MEMORY_REF_COST); 3986 size(4); 3987 format %{ "LE(Y) $dst,$src\t # stk reload float" %} 3988 opcode(LE_ZOPC); 3989 ins_encode(z_form_rt_mem(dst, src)); 3990 ins_pipe(pipe_class_dummy); 3991 %} 3992 3993 // Store float value to stack slot. 3994 instruct regF_to_stkF(stackSlotF dst, regF src) %{ 3995 match(Set dst src); 3996 ins_cost(MEMORY_REF_COST); 3997 size(4); 3998 format %{ "STE(Y) $src,$dst\t # stk spill float" %} 3999 opcode(STE_ZOPC); 4000 ins_encode(z_form_rt_mem(src, dst)); 4001 ins_pipe(pipe_class_dummy); 4002 %} 4003 4004 // Load double value from stack slot. 4005 instruct stkD_to_regD(regD dst, stackSlotD src) %{ 4006 match(Set dst src); 4007 ins_cost(MEMORY_REF_COST); 4008 // TODO: s390 port size(FIXED_SIZE); 4009 format %{ "LD(Y) $dst,$src\t # stk reload double" %} 4010 opcode(LD_ZOPC); 4011 ins_encode(z_form_rt_mem(dst, src)); 4012 ins_pipe(pipe_class_dummy); 4013 %} 4014 4015 // Store double value to stack slot. 4016 instruct regD_to_stkD(stackSlotD dst, regD src) %{ 4017 match(Set dst src); 4018 ins_cost(MEMORY_REF_COST); 4019 size(4); 4020 format %{ "STD(Y) $src,$dst\t # stk spill double" %} 4021 opcode(STD_ZOPC); 4022 ins_encode(z_form_rt_mem(src, dst)); 4023 ins_pipe(pipe_class_dummy); 4024 %} 4025 4026 //----------Load/Store/Move Instructions--------------------------------------- 4027 4028 //----------Load Instructions-------------------------------------------------- 4029 4030 //------------------ 4031 // MEMORY 4032 //------------------ 4033 4034 // BYTE 4035 // Load Byte (8bit signed) 4036 instruct loadB(iRegI dst, memory mem) %{ 4037 match(Set dst (LoadB mem)); 4038 ins_cost(MEMORY_REF_COST); 4039 size(Z_DISP3_SIZE); 4040 format %{ "LB $dst, $mem\t # sign-extend byte to int" %} 4041 opcode(LB_ZOPC, LB_ZOPC); 4042 ins_encode(z_form_rt_mem_opt(dst, mem)); 4043 ins_pipe(pipe_class_dummy); 4044 %} 4045 4046 // Load Byte (8bit signed) 4047 instruct loadB2L(iRegL dst, memory mem) %{ 4048 match(Set dst (ConvI2L (LoadB mem))); 4049 ins_cost(MEMORY_REF_COST); 4050 size(Z_DISP3_SIZE); 4051 format %{ "LGB $dst, $mem\t # sign-extend byte to long" %} 4052 opcode(LGB_ZOPC, LGB_ZOPC); 4053 ins_encode(z_form_rt_mem_opt(dst, mem)); 4054 ins_pipe(pipe_class_dummy); 4055 %} 4056 4057 // Load Unsigned Byte (8bit UNsigned) into an int reg. 4058 instruct loadUB(iRegI dst, memory mem) %{ 4059 match(Set dst (LoadUB mem)); 4060 ins_cost(MEMORY_REF_COST); 4061 size(Z_DISP3_SIZE); 4062 format %{ "LLGC $dst,$mem\t # zero-extend byte to int" %} 4063 opcode(LLGC_ZOPC, LLGC_ZOPC); 4064 ins_encode(z_form_rt_mem_opt(dst, mem)); 4065 ins_pipe(pipe_class_dummy); 4066 %} 4067 4068 // Load Unsigned Byte (8bit UNsigned) into a Long Register. 4069 instruct loadUB2L(iRegL dst, memory mem) %{ 4070 match(Set dst (ConvI2L (LoadUB mem))); 4071 ins_cost(MEMORY_REF_COST); 4072 size(Z_DISP3_SIZE); 4073 format %{ "LLGC $dst,$mem\t # zero-extend byte to long" %} 4074 opcode(LLGC_ZOPC, LLGC_ZOPC); 4075 ins_encode(z_form_rt_mem_opt(dst, mem)); 4076 ins_pipe(pipe_class_dummy); 4077 %} 4078 4079 // CHAR/SHORT 4080 4081 // Load Short (16bit signed) 4082 instruct loadS(iRegI dst, memory mem) %{ 4083 match(Set dst (LoadS mem)); 4084 ins_cost(MEMORY_REF_COST); 4085 size(Z_DISP_SIZE); 4086 format %{ "LH(Y) $dst,$mem\t # sign-extend short to int" %} 4087 opcode(LHY_ZOPC, LH_ZOPC); 4088 ins_encode(z_form_rt_mem_opt(dst, mem)); 4089 ins_pipe(pipe_class_dummy); 4090 %} 4091 4092 // Load Short (16bit signed) 4093 instruct loadS2L(iRegL dst, memory mem) %{ 4094 match(Set dst (ConvI2L (LoadS mem))); 4095 ins_cost(MEMORY_REF_COST); 4096 size(Z_DISP3_SIZE); 4097 format %{ "LGH $dst,$mem\t # sign-extend short to long" %} 4098 opcode(LGH_ZOPC, LGH_ZOPC); 4099 ins_encode(z_form_rt_mem_opt(dst, mem)); 4100 ins_pipe(pipe_class_dummy); 4101 %} 4102 4103 // Load Char (16bit Unsigned) 4104 instruct loadUS(iRegI dst, memory mem) %{ 4105 match(Set dst (LoadUS mem)); 4106 ins_cost(MEMORY_REF_COST); 4107 size(Z_DISP3_SIZE); 4108 format %{ "LLGH $dst,$mem\t # zero-extend short to int" %} 4109 opcode(LLGH_ZOPC, LLGH_ZOPC); 4110 ins_encode(z_form_rt_mem_opt(dst, mem)); 4111 ins_pipe(pipe_class_dummy); 4112 %} 4113 4114 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register. 4115 instruct loadUS2L(iRegL dst, memory mem) %{ 4116 match(Set dst (ConvI2L (LoadUS mem))); 4117 ins_cost(MEMORY_REF_COST); 4118 size(Z_DISP3_SIZE); 4119 format %{ "LLGH $dst,$mem\t # zero-extend short to long" %} 4120 opcode(LLGH_ZOPC, LLGH_ZOPC); 4121 ins_encode(z_form_rt_mem_opt(dst, mem)); 4122 ins_pipe(pipe_class_dummy); 4123 %} 4124 4125 // INT 4126 4127 // Load Integer 4128 instruct loadI(iRegI dst, memory mem) %{ 4129 match(Set dst (LoadI mem)); 4130 ins_cost(MEMORY_REF_COST); 4131 size(Z_DISP_SIZE); 4132 format %{ "L(Y) $dst,$mem\t #" %} 4133 opcode(LY_ZOPC, L_ZOPC); 4134 ins_encode(z_form_rt_mem_opt(dst, mem)); 4135 ins_pipe(pipe_class_dummy); 4136 %} 4137 4138 // Load and convert to long. 4139 instruct loadI2L(iRegL dst, memory mem) %{ 4140 match(Set dst (ConvI2L (LoadI mem))); 4141 ins_cost(MEMORY_REF_COST); 4142 size(Z_DISP3_SIZE); 4143 format %{ "LGF $dst,$mem\t #" %} 4144 opcode(LGF_ZOPC, LGF_ZOPC); 4145 ins_encode(z_form_rt_mem_opt(dst, mem)); 4146 ins_pipe(pipe_class_dummy); 4147 %} 4148 4149 // Load Unsigned Integer into a Long Register 4150 instruct loadUI2L(iRegL dst, memory mem, immL_FFFFFFFF mask) %{ 4151 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 4152 ins_cost(MEMORY_REF_COST); 4153 size(Z_DISP3_SIZE); 4154 format %{ "LLGF $dst,$mem\t # zero-extend int to long" %} 4155 opcode(LLGF_ZOPC, LLGF_ZOPC); 4156 ins_encode(z_form_rt_mem_opt(dst, mem)); 4157 ins_pipe(pipe_class_dummy); 4158 %} 4159 4160 // range = array length (=jint) 4161 // Load Range 4162 instruct loadRange(iRegI dst, memory mem) %{ 4163 match(Set dst (LoadRange mem)); 4164 ins_cost(MEMORY_REF_COST); 4165 size(Z_DISP_SIZE); 4166 format %{ "L(Y) $dst,$mem\t # range" %} 4167 opcode(LY_ZOPC, L_ZOPC); 4168 ins_encode(z_form_rt_mem_opt(dst, mem)); 4169 ins_pipe(pipe_class_dummy); 4170 %} 4171 4172 // LONG 4173 4174 // Load Long - aligned 4175 instruct loadL(iRegL dst, memory mem) %{ 4176 match(Set dst (LoadL mem)); 4177 ins_cost(MEMORY_REF_COST); 4178 size(Z_DISP3_SIZE); 4179 format %{ "LG $dst,$mem\t # long" %} 4180 opcode(LG_ZOPC, LG_ZOPC); 4181 ins_encode(z_form_rt_mem_opt(dst, mem)); 4182 ins_pipe(pipe_class_dummy); 4183 %} 4184 4185 // Load Long - UNaligned 4186 instruct loadL_unaligned(iRegL dst, memory mem) %{ 4187 match(Set dst (LoadL_unaligned mem)); 4188 ins_cost(MEMORY_REF_COST); 4189 size(Z_DISP3_SIZE); 4190 format %{ "LG $dst,$mem\t # unaligned long" %} 4191 opcode(LG_ZOPC, LG_ZOPC); 4192 ins_encode(z_form_rt_mem_opt(dst, mem)); 4193 ins_pipe(pipe_class_dummy); 4194 %} 4195 4196 4197 // PTR 4198 4199 // Load Pointer 4200 instruct loadP(iRegP dst, memory mem) %{ 4201 match(Set dst (LoadP mem)); 4202 ins_cost(MEMORY_REF_COST); 4203 size(Z_DISP3_SIZE); 4204 format %{ "LG $dst,$mem\t # ptr" %} 4205 opcode(LG_ZOPC, LG_ZOPC); 4206 ins_encode(z_form_rt_mem_opt(dst, mem)); 4207 ins_pipe(pipe_class_dummy); 4208 %} 4209 4210 // LoadP + CastP2L 4211 instruct castP2X_loadP(iRegL dst, memory mem) %{ 4212 match(Set dst (CastP2X (LoadP mem))); 4213 ins_cost(MEMORY_REF_COST); 4214 size(Z_DISP3_SIZE); 4215 format %{ "LG $dst,$mem\t # ptr + p2x" %} 4216 opcode(LG_ZOPC, LG_ZOPC); 4217 ins_encode(z_form_rt_mem_opt(dst, mem)); 4218 ins_pipe(pipe_class_dummy); 4219 %} 4220 4221 // Load Klass Pointer 4222 instruct loadKlass(iRegP dst, memory mem) %{ 4223 match(Set dst (LoadKlass mem)); 4224 ins_cost(MEMORY_REF_COST); 4225 size(Z_DISP3_SIZE); 4226 format %{ "LG $dst,$mem\t # klass ptr" %} 4227 opcode(LG_ZOPC, LG_ZOPC); 4228 ins_encode(z_form_rt_mem_opt(dst, mem)); 4229 ins_pipe(pipe_class_dummy); 4230 %} 4231 4232 instruct loadTOC(iRegL dst) %{ 4233 effect(DEF dst); 4234 ins_cost(DEFAULT_COST); 4235 // TODO: s390 port size(FIXED_SIZE); 4236 // TODO: check why this attribute causes many unnecessary rematerializations. 4237 // 4238 // The graphs I saw just had high register pressure. Further the 4239 // register TOC is loaded to is overwritten by the constant short 4240 // after. Here something as round robin register allocation might 4241 // help. But rematerializing seems not to hurt, jack even seems to 4242 // improve slightly. 4243 // 4244 // Without this flag we get spill-split recycle sanity check 4245 // failures in 4246 // spec.benchmarks._228_jack.NfaState::GenerateCode. This happens in 4247 // a block with three loadConP_dynTOC nodes and a tlsLoadP. The 4248 // tlsLoadP has a huge amount of outs and forces the TOC down to the 4249 // stack. Later tlsLoadP is rematerialized, leaving the register 4250 // allocator with TOC on the stack and a badly placed reload. 4251 ins_should_rematerialize(true); 4252 format %{ "LARL $dst, &constant_pool\t; load dynTOC" %} 4253 ins_encode %{ __ load_toc($dst$$Register); %} 4254 ins_pipe(pipe_class_dummy); 4255 %} 4256 4257 // FLOAT 4258 4259 // Load Float 4260 instruct loadF(regF dst, memory mem) %{ 4261 match(Set dst (LoadF mem)); 4262 ins_cost(MEMORY_REF_COST); 4263 size(Z_DISP_SIZE); 4264 format %{ "LE(Y) $dst,$mem" %} 4265 opcode(LEY_ZOPC, LE_ZOPC); 4266 ins_encode(z_form_rt_mem_opt(dst, mem)); 4267 ins_pipe(pipe_class_dummy); 4268 %} 4269 4270 // DOUBLE 4271 4272 // Load Double 4273 instruct loadD(regD dst, memory mem) %{ 4274 match(Set dst (LoadD mem)); 4275 ins_cost(MEMORY_REF_COST); 4276 size(Z_DISP_SIZE); 4277 format %{ "LD(Y) $dst,$mem" %} 4278 opcode(LDY_ZOPC, LD_ZOPC); 4279 ins_encode(z_form_rt_mem_opt(dst, mem)); 4280 ins_pipe(pipe_class_dummy); 4281 %} 4282 4283 // Load Double - UNaligned 4284 instruct loadD_unaligned(regD dst, memory mem) %{ 4285 match(Set dst (LoadD_unaligned mem)); 4286 ins_cost(MEMORY_REF_COST); 4287 size(Z_DISP_SIZE); 4288 format %{ "LD(Y) $dst,$mem" %} 4289 opcode(LDY_ZOPC, LD_ZOPC); 4290 ins_encode(z_form_rt_mem_opt(dst, mem)); 4291 ins_pipe(pipe_class_dummy); 4292 %} 4293 4294 4295 //---------------------- 4296 // IMMEDIATES 4297 //---------------------- 4298 4299 instruct loadConI(iRegI dst, immI src) %{ 4300 match(Set dst src); 4301 ins_cost(DEFAULT_COST); 4302 size(6); 4303 format %{ "LGFI $dst,$src\t # (int)" %} 4304 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. 4305 ins_pipe(pipe_class_dummy); 4306 %} 4307 4308 instruct loadConI16(iRegI dst, immI16 src) %{ 4309 match(Set dst src); 4310 ins_cost(DEFAULT_COST_LOW); 4311 size(4); 4312 format %{ "LGHI $dst,$src\t # (int)" %} 4313 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. 4314 ins_pipe(pipe_class_dummy); 4315 %} 4316 4317 instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{ 4318 match(Set dst src); 4319 effect(KILL cr); 4320 ins_cost(DEFAULT_COST_LOW); 4321 size(4); 4322 format %{ "loadConI $dst,$src\t # (int) XGR because ZERO is loaded" %} 4323 opcode(XGR_ZOPC); 4324 ins_encode(z_rreform(dst, dst)); 4325 ins_pipe(pipe_class_dummy); 4326 %} 4327 4328 instruct loadConUI16(iRegI dst, uimmI16 src) %{ 4329 match(Set dst src); 4330 // TODO: s390 port size(FIXED_SIZE); 4331 format %{ "LLILL $dst,$src" %} 4332 opcode(LLILL_ZOPC); 4333 ins_encode(z_riform_unsigned(dst, src) ); 4334 ins_pipe(pipe_class_dummy); 4335 %} 4336 4337 // Load long constant from TOC with pcrelative address. 4338 instruct loadConL_pcrelTOC(iRegL dst, immL src) %{ 4339 match(Set dst src); 4340 ins_cost(MEMORY_REF_COST_LO); 4341 size(6); 4342 format %{ "LGRL $dst,[pcrelTOC]\t # load long $src from table" %} 4343 ins_encode %{ 4344 address long_address = __ long_constant($src$$constant); 4345 if (long_address == NULL) { 4346 Compile::current()->env()->record_out_of_memory_failure(); 4347 return; 4348 } 4349 __ load_long_pcrelative($dst$$Register, long_address); 4350 %} 4351 ins_pipe(pipe_class_dummy); 4352 %} 4353 4354 instruct loadConL32(iRegL dst, immL32 src) %{ 4355 match(Set dst src); 4356 ins_cost(DEFAULT_COST); 4357 size(6); 4358 format %{ "LGFI $dst,$src\t # (long)" %} 4359 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. 4360 ins_pipe(pipe_class_dummy); 4361 %} 4362 4363 instruct loadConL16(iRegL dst, immL16 src) %{ 4364 match(Set dst src); 4365 ins_cost(DEFAULT_COST_LOW); 4366 size(4); 4367 format %{ "LGHI $dst,$src\t # (long)" %} 4368 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. 4369 ins_pipe(pipe_class_dummy); 4370 %} 4371 4372 instruct loadConL_0(iRegL dst, immL_0 src, flagsReg cr) %{ 4373 match(Set dst src); 4374 effect(KILL cr); 4375 ins_cost(DEFAULT_COST_LOW); 4376 format %{ "LoadConL $dst,$src\t # (long) XGR because ZERO is loaded" %} 4377 opcode(XGR_ZOPC); 4378 ins_encode(z_rreform(dst, dst)); 4379 ins_pipe(pipe_class_dummy); 4380 %} 4381 4382 // Load ptr constant from TOC with pc relative address. 4383 // Special handling for oop constants required. 4384 instruct loadConP_pcrelTOC(iRegP dst, immP src) %{ 4385 match(Set dst src); 4386 ins_cost(MEMORY_REF_COST_LO); 4387 size(6); 4388 format %{ "LGRL $dst,[pcrelTOC]\t # load ptr $src from table" %} 4389 ins_encode %{ 4390 relocInfo::relocType constant_reloc = $src->constant_reloc(); 4391 if (constant_reloc == relocInfo::oop_type) { 4392 AddressLiteral a = __ allocate_oop_address((jobject)$src$$constant); 4393 bool success = __ load_oop_from_toc($dst$$Register, a); 4394 if (!success) { 4395 Compile::current()->env()->record_out_of_memory_failure(); 4396 return; 4397 } 4398 } else if (constant_reloc == relocInfo::metadata_type) { 4399 AddressLiteral a = __ constant_metadata_address((Metadata *)$src$$constant); 4400 address const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 4401 if (const_toc_addr == NULL) { 4402 Compile::current()->env()->record_out_of_memory_failure(); 4403 return; 4404 } 4405 __ load_long_pcrelative($dst$$Register, const_toc_addr); 4406 } else { // Non-oop pointers, e.g. card mark base, heap top. 4407 address long_address = __ long_constant((jlong)$src$$constant); 4408 if (long_address == NULL) { 4409 Compile::current()->env()->record_out_of_memory_failure(); 4410 return; 4411 } 4412 __ load_long_pcrelative($dst$$Register, long_address); 4413 } 4414 %} 4415 ins_pipe(pipe_class_dummy); 4416 %} 4417 4418 // We don't use immP16 to avoid problems with oops. 4419 instruct loadConP0(iRegP dst, immP0 src, flagsReg cr) %{ 4420 match(Set dst src); 4421 effect(KILL cr); 4422 size(4); 4423 format %{ "XGR $dst,$dst\t # NULL ptr" %} 4424 opcode(XGR_ZOPC); 4425 ins_encode(z_rreform(dst, dst)); 4426 ins_pipe(pipe_class_dummy); 4427 %} 4428 4429 //----------Load Float Constant Instructions------------------------------------------------- 4430 4431 // We may not specify this instruction via an `expand' rule. If we do, 4432 // code selection will forget that this instruction needs a floating 4433 // point constant inserted into the code buffer. So `Shorten_branches' 4434 // will fail. 4435 instruct loadConF_dynTOC(regF dst, immF src, flagsReg cr) %{ 4436 match(Set dst src); 4437 effect(KILL cr); 4438 ins_cost(MEMORY_REF_COST); 4439 size(6); 4440 // If this instruction rematerializes, it prolongs the live range 4441 // of the toc node, causing illegal graphs. 4442 ins_cannot_rematerialize(true); 4443 format %{ "LE(Y) $dst,$constantoffset[,$constanttablebase]\t # load FLOAT $src from table" %} 4444 ins_encode %{ 4445 __ load_float_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch); 4446 %} 4447 ins_pipe(pipe_class_dummy); 4448 %} 4449 4450 // E may not specify this instruction via an `expand' rule. If we do, 4451 // code selection will forget that this instruction needs a floating 4452 // point constant inserted into the code buffer. So `Shorten_branches' 4453 // will fail. 4454 instruct loadConD_dynTOC(regD dst, immD src, flagsReg cr) %{ 4455 match(Set dst src); 4456 effect(KILL cr); 4457 ins_cost(MEMORY_REF_COST); 4458 size(6); 4459 // If this instruction rematerializes, it prolongs the live range 4460 // of the toc node, causing illegal graphs. 4461 ins_cannot_rematerialize(true); 4462 format %{ "LD(Y) $dst,$constantoffset[,$constanttablebase]\t # load DOUBLE $src from table" %} 4463 ins_encode %{ 4464 __ load_double_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch); 4465 %} 4466 ins_pipe(pipe_class_dummy); 4467 %} 4468 4469 // Special case: Load Const 0.0F 4470 4471 // There's a special instr to clear a FP register. 4472 instruct loadConF0(regF dst, immFp0 src) %{ 4473 match(Set dst src); 4474 ins_cost(DEFAULT_COST_LOW); 4475 size(4); 4476 format %{ "LZER $dst,$src\t # clear to zero" %} 4477 opcode(LZER_ZOPC); 4478 ins_encode(z_rreform(dst, Z_F0)); 4479 ins_pipe(pipe_class_dummy); 4480 %} 4481 4482 // There's a special instr to clear a FP register. 4483 instruct loadConD0(regD dst, immDp0 src) %{ 4484 match(Set dst src); 4485 ins_cost(DEFAULT_COST_LOW); 4486 size(4); 4487 format %{ "LZDR $dst,$src\t # clear to zero" %} 4488 opcode(LZDR_ZOPC); 4489 ins_encode(z_rreform(dst, Z_F0)); 4490 ins_pipe(pipe_class_dummy); 4491 %} 4492 4493 4494 //----------Store Instructions------------------------------------------------- 4495 4496 // BYTE 4497 4498 // Store Byte 4499 instruct storeB(memory mem, iRegI src) %{ 4500 match(Set mem (StoreB mem src)); 4501 ins_cost(MEMORY_REF_COST); 4502 size(Z_DISP_SIZE); 4503 format %{ "STC(Y) $src,$mem\t # byte" %} 4504 opcode(STCY_ZOPC, STC_ZOPC); 4505 ins_encode(z_form_rt_mem_opt(src, mem)); 4506 ins_pipe(pipe_class_dummy); 4507 %} 4508 4509 instruct storeCM(memory mem, immI_0 src) %{ 4510 match(Set mem (StoreCM mem src)); 4511 ins_cost(MEMORY_REF_COST); 4512 // TODO: s390 port size(VARIABLE_SIZE); 4513 format %{ "STC(Y) $src,$mem\t # CMS card-mark byte (must be 0!)" %} 4514 ins_encode %{ 4515 guarantee($mem$$index$$Register != Z_R0, "content will not be used."); 4516 if ($mem$$index$$Register != noreg) { 4517 // Can't use clear_mem --> load const zero and store character. 4518 __ load_const_optimized(Z_R0_scratch, (long)0); 4519 if (Immediate::is_uimm12($mem$$disp)) { 4520 __ z_stc(Z_R0_scratch, $mem$$Address); 4521 } else { 4522 __ z_stcy(Z_R0_scratch, $mem$$Address); 4523 } 4524 } else { 4525 __ clear_mem(Address($mem$$Address), 1); 4526 } 4527 %} 4528 ins_pipe(pipe_class_dummy); 4529 %} 4530 4531 // CHAR/SHORT 4532 4533 // Store Char/Short 4534 instruct storeC(memory mem, iRegI src) %{ 4535 match(Set mem (StoreC mem src)); 4536 ins_cost(MEMORY_REF_COST); 4537 size(Z_DISP_SIZE); 4538 format %{ "STH(Y) $src,$mem\t # short" %} 4539 opcode(STHY_ZOPC, STH_ZOPC); 4540 ins_encode(z_form_rt_mem_opt(src, mem)); 4541 ins_pipe(pipe_class_dummy); 4542 %} 4543 4544 // INT 4545 4546 // Store Integer 4547 instruct storeI(memory mem, iRegI src) %{ 4548 match(Set mem (StoreI mem src)); 4549 ins_cost(MEMORY_REF_COST); 4550 size(Z_DISP_SIZE); 4551 format %{ "ST(Y) $src,$mem\t # int" %} 4552 opcode(STY_ZOPC, ST_ZOPC); 4553 ins_encode(z_form_rt_mem_opt(src, mem)); 4554 ins_pipe(pipe_class_dummy); 4555 %} 4556 4557 // LONG 4558 4559 // Store Long 4560 instruct storeL(memory mem, iRegL src) %{ 4561 match(Set mem (StoreL mem src)); 4562 ins_cost(MEMORY_REF_COST); 4563 size(Z_DISP3_SIZE); 4564 format %{ "STG $src,$mem\t # long" %} 4565 opcode(STG_ZOPC, STG_ZOPC); 4566 ins_encode(z_form_rt_mem_opt(src, mem)); 4567 ins_pipe(pipe_class_dummy); 4568 %} 4569 4570 // PTR 4571 4572 // Store Pointer 4573 instruct storeP(memory dst, memoryRegP src) %{ 4574 match(Set dst (StoreP dst src)); 4575 ins_cost(MEMORY_REF_COST); 4576 size(Z_DISP3_SIZE); 4577 format %{ "STG $src,$dst\t # ptr" %} 4578 opcode(STG_ZOPC, STG_ZOPC); 4579 ins_encode(z_form_rt_mem_opt(src, dst)); 4580 ins_pipe(pipe_class_dummy); 4581 %} 4582 4583 // FLOAT 4584 4585 // Store Float 4586 instruct storeF(memory mem, regF src) %{ 4587 match(Set mem (StoreF mem src)); 4588 ins_cost(MEMORY_REF_COST); 4589 size(Z_DISP_SIZE); 4590 format %{ "STE(Y) $src,$mem\t # float" %} 4591 opcode(STEY_ZOPC, STE_ZOPC); 4592 ins_encode(z_form_rt_mem_opt(src, mem)); 4593 ins_pipe(pipe_class_dummy); 4594 %} 4595 4596 // DOUBLE 4597 4598 // Store Double 4599 instruct storeD(memory mem, regD src) %{ 4600 match(Set mem (StoreD mem src)); 4601 ins_cost(MEMORY_REF_COST); 4602 size(Z_DISP_SIZE); 4603 format %{ "STD(Y) $src,$mem\t # double" %} 4604 opcode(STDY_ZOPC, STD_ZOPC); 4605 ins_encode(z_form_rt_mem_opt(src, mem)); 4606 ins_pipe(pipe_class_dummy); 4607 %} 4608 4609 // Prefetch instructions. Must be safe to execute with invalid address (cannot fault). 4610 4611 // Should support match rule for PrefetchAllocation. 4612 // Still needed after 8068977 for PrefetchAllocate. 4613 instruct prefetchAlloc(memory mem) %{ 4614 match(PrefetchAllocation mem); 4615 predicate(VM_Version::has_Prefetch()); 4616 ins_cost(DEFAULT_COST); 4617 format %{ "PREFETCH 2, $mem\t # Prefetch allocation, z10 only" %} 4618 ins_encode %{ __ z_pfd(0x02, $mem$$Address); %} 4619 ins_pipe(pipe_class_dummy); 4620 %} 4621 4622 //----------Memory init instructions------------------------------------------ 4623 4624 // Move Immediate to 1-byte memory. 4625 instruct memInitB(memoryRSY mem, immI8 src) %{ 4626 match(Set mem (StoreB mem src)); 4627 ins_cost(MEMORY_REF_COST); 4628 // TODO: s390 port size(VARIABLE_SIZE); 4629 format %{ "MVI $mem,$src\t # direct mem init 1" %} 4630 ins_encode %{ 4631 if (Immediate::is_uimm12((long)$mem$$disp)) { 4632 __ z_mvi($mem$$Address, $src$$constant); 4633 } else { 4634 __ z_mviy($mem$$Address, $src$$constant); 4635 } 4636 %} 4637 ins_pipe(pipe_class_dummy); 4638 %} 4639 4640 // Move Immediate to 2-byte memory. 4641 instruct memInitC(memoryRS mem, immI16 src) %{ 4642 match(Set mem (StoreC mem src)); 4643 ins_cost(MEMORY_REF_COST); 4644 size(6); 4645 format %{ "MVHHI $mem,$src\t # direct mem init 2" %} 4646 opcode(MVHHI_ZOPC); 4647 ins_encode(z_silform(mem, src)); 4648 ins_pipe(pipe_class_dummy); 4649 %} 4650 4651 // Move Immediate to 4-byte memory. 4652 instruct memInitI(memoryRS mem, immI16 src) %{ 4653 match(Set mem (StoreI mem src)); 4654 ins_cost(MEMORY_REF_COST); 4655 size(6); 4656 format %{ "MVHI $mem,$src\t # direct mem init 4" %} 4657 opcode(MVHI_ZOPC); 4658 ins_encode(z_silform(mem, src)); 4659 ins_pipe(pipe_class_dummy); 4660 %} 4661 4662 4663 // Move Immediate to 8-byte memory. 4664 instruct memInitL(memoryRS mem, immL16 src) %{ 4665 match(Set mem (StoreL mem src)); 4666 ins_cost(MEMORY_REF_COST); 4667 size(6); 4668 format %{ "MVGHI $mem,$src\t # direct mem init 8" %} 4669 opcode(MVGHI_ZOPC); 4670 ins_encode(z_silform(mem, src)); 4671 ins_pipe(pipe_class_dummy); 4672 %} 4673 4674 // Move Immediate to 8-byte memory. 4675 instruct memInitP(memoryRS mem, immP16 src) %{ 4676 match(Set mem (StoreP mem src)); 4677 ins_cost(MEMORY_REF_COST); 4678 size(6); 4679 format %{ "MVGHI $mem,$src\t # direct mem init 8" %} 4680 opcode(MVGHI_ZOPC); 4681 ins_encode(z_silform(mem, src)); 4682 ins_pipe(pipe_class_dummy); 4683 %} 4684 4685 4686 //----------Instructions for compressed pointers (cOop and NKlass)------------- 4687 4688 // See cOop encoding classes for elaborate comment. 4689 4690 // Moved here because it is needed in expand rules for encode. 4691 // Long negation. 4692 instruct negL_reg_reg(iRegL dst, immL_0 zero, iRegL src, flagsReg cr) %{ 4693 match(Set dst (SubL zero src)); 4694 effect(KILL cr); 4695 size(4); 4696 format %{ "NEG $dst, $src\t # long" %} 4697 ins_encode %{ __ z_lcgr($dst$$Register, $src$$Register); %} 4698 ins_pipe(pipe_class_dummy); 4699 %} 4700 4701 // Load Compressed Pointer 4702 4703 // Load narrow oop 4704 instruct loadN(iRegN dst, memory mem) %{ 4705 match(Set dst (LoadN mem)); 4706 ins_cost(MEMORY_REF_COST); 4707 size(Z_DISP3_SIZE); 4708 format %{ "LoadN $dst,$mem\t# (cOop)" %} 4709 opcode(LLGF_ZOPC, LLGF_ZOPC); 4710 ins_encode(z_form_rt_mem_opt(dst, mem)); 4711 ins_pipe(pipe_class_dummy); 4712 %} 4713 4714 // Load narrow Klass Pointer 4715 instruct loadNKlass(iRegN dst, memory mem) %{ 4716 match(Set dst (LoadNKlass mem)); 4717 ins_cost(MEMORY_REF_COST); 4718 size(Z_DISP3_SIZE); 4719 format %{ "LoadNKlass $dst,$mem\t# (klass cOop)" %} 4720 opcode(LLGF_ZOPC, LLGF_ZOPC); 4721 ins_encode(z_form_rt_mem_opt(dst, mem)); 4722 ins_pipe(pipe_class_dummy); 4723 %} 4724 4725 // Load constant Compressed Pointer 4726 4727 instruct loadConN(iRegN dst, immN src) %{ 4728 match(Set dst src); 4729 ins_cost(DEFAULT_COST); 4730 size(6); 4731 format %{ "loadConN $dst,$src\t # (cOop)" %} 4732 ins_encode %{ 4733 AddressLiteral cOop = __ constant_oop_address((jobject)$src$$constant); 4734 __ relocate(cOop.rspec(), 1); 4735 __ load_narrow_oop($dst$$Register, (narrowOop)cOop.value()); 4736 %} 4737 ins_pipe(pipe_class_dummy); 4738 %} 4739 4740 instruct loadConN0(iRegN dst, immN0 src, flagsReg cr) %{ 4741 match(Set dst src); 4742 effect(KILL cr); 4743 ins_cost(DEFAULT_COST_LOW); 4744 size(4); 4745 format %{ "loadConN $dst,$src\t # (cOop) XGR because ZERO is loaded" %} 4746 opcode(XGR_ZOPC); 4747 ins_encode(z_rreform(dst, dst)); 4748 ins_pipe(pipe_class_dummy); 4749 %} 4750 4751 instruct loadConNKlass(iRegN dst, immNKlass src) %{ 4752 match(Set dst src); 4753 ins_cost(DEFAULT_COST); 4754 size(6); 4755 format %{ "loadConNKlass $dst,$src\t # (cKlass)" %} 4756 ins_encode %{ 4757 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant); 4758 __ relocate(NKlass.rspec(), 1); 4759 __ load_narrow_klass($dst$$Register, (Klass*)NKlass.value()); 4760 %} 4761 ins_pipe(pipe_class_dummy); 4762 %} 4763 4764 // Load and Decode Compressed Pointer 4765 // optimized variants for Unscaled cOops 4766 4767 instruct decodeLoadN(iRegP dst, memory mem) %{ 4768 match(Set dst (DecodeN (LoadN mem))); 4769 predicate(false && (Universe::narrow_oop_base()==NULL)&&(Universe::narrow_oop_shift()==0)); 4770 ins_cost(MEMORY_REF_COST); 4771 size(Z_DISP3_SIZE); 4772 format %{ "DecodeLoadN $dst,$mem\t# (cOop Load+Decode)" %} 4773 opcode(LLGF_ZOPC, LLGF_ZOPC); 4774 ins_encode(z_form_rt_mem_opt(dst, mem)); 4775 ins_pipe(pipe_class_dummy); 4776 %} 4777 4778 instruct decodeLoadNKlass(iRegP dst, memory mem) %{ 4779 match(Set dst (DecodeNKlass (LoadNKlass mem))); 4780 predicate(false && (Universe::narrow_klass_base()==NULL)&&(Universe::narrow_klass_shift()==0)); 4781 ins_cost(MEMORY_REF_COST); 4782 size(Z_DISP3_SIZE); 4783 format %{ "DecodeLoadNKlass $dst,$mem\t# (load/decode NKlass)" %} 4784 opcode(LLGF_ZOPC, LLGF_ZOPC); 4785 ins_encode(z_form_rt_mem_opt(dst, mem)); 4786 ins_pipe(pipe_class_dummy); 4787 %} 4788 4789 instruct decodeLoadConNKlass(iRegP dst, immNKlass src) %{ 4790 match(Set dst (DecodeNKlass src)); 4791 ins_cost(3 * DEFAULT_COST); 4792 size(12); 4793 format %{ "DecodeLoadConNKlass $dst,$src\t # decode(cKlass)" %} 4794 ins_encode %{ 4795 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant); 4796 __ relocate(NKlass.rspec(), 1); 4797 __ load_const($dst$$Register, (Klass*)NKlass.value()); 4798 %} 4799 ins_pipe(pipe_class_dummy); 4800 %} 4801 4802 // Decode Compressed Pointer 4803 4804 // General decoder 4805 instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{ 4806 match(Set dst (DecodeN src)); 4807 effect(KILL cr); 4808 predicate(Universe::narrow_oop_base() == NULL || !ExpandLoadingBaseDecode); 4809 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST); 4810 // TODO: s390 port size(VARIABLE_SIZE); 4811 format %{ "decodeN $dst,$src\t# (decode cOop)" %} 4812 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true); %} 4813 ins_pipe(pipe_class_dummy); 4814 %} 4815 4816 // General Klass decoder 4817 instruct decodeKlass(iRegP dst, iRegN src, flagsReg cr) %{ 4818 match(Set dst (DecodeNKlass src)); 4819 effect(KILL cr); 4820 ins_cost(3 * DEFAULT_COST); 4821 format %{ "decode_klass $dst,$src" %} 4822 ins_encode %{ __ decode_klass_not_null($dst$$Register, $src$$Register); %} 4823 ins_pipe(pipe_class_dummy); 4824 %} 4825 4826 // General decoder 4827 instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{ 4828 match(Set dst (DecodeN src)); 4829 effect(KILL cr); 4830 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull || 4831 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 4832 (Universe::narrow_oop_base()== NULL || !ExpandLoadingBaseDecode_NN)); 4833 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); 4834 // TODO: s390 port size(VARIABLE_SIZE); 4835 format %{ "decodeN $dst,$src\t# (decode cOop NN)" %} 4836 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %} 4837 ins_pipe(pipe_class_dummy); 4838 %} 4839 4840 instruct loadBase(iRegL dst, immL baseImm) %{ 4841 effect(DEF dst, USE baseImm); 4842 predicate(false); 4843 format %{ "llihl $dst=$baseImm \t// load heap base" %} 4844 ins_encode %{ __ get_oop_base($dst$$Register, $baseImm$$constant); %} 4845 ins_pipe(pipe_class_dummy); 4846 %} 4847 4848 // Decoder for heapbased mode peeling off loading the base. 4849 instruct decodeN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{ 4850 match(Set dst (DecodeN src base)); 4851 // Note: Effect TEMP dst was used with the intention to get 4852 // different regs for dst and base, but this has caused ADLC to 4853 // generate wrong code. Oop_decoder generates additional lgr when 4854 // dst==base. 4855 effect(KILL cr); 4856 predicate(false); 4857 // TODO: s390 port size(VARIABLE_SIZE); 4858 format %{ "decodeN $dst = ($src == 0) ? NULL : ($src << 3) + $base + pow2_offset\t# (decode cOop)" %} 4859 ins_encode %{ 4860 __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register, 4861 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)Universe::narrow_oop_base())); 4862 %} 4863 ins_pipe(pipe_class_dummy); 4864 %} 4865 4866 // Decoder for heapbased mode peeling off loading the base. 4867 instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{ 4868 match(Set dst (DecodeN src base)); 4869 effect(KILL cr); 4870 predicate(false); 4871 // TODO: s390 port size(VARIABLE_SIZE); 4872 format %{ "decodeN $dst = ($src << 3) + $base + pow2_offset\t# (decode cOop)" %} 4873 ins_encode %{ 4874 __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register, 4875 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)Universe::narrow_oop_base())); 4876 %} 4877 ins_pipe(pipe_class_dummy); 4878 %} 4879 4880 // Decoder for heapbased mode peeling off loading the base. 4881 instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{ 4882 match(Set dst (DecodeN src)); 4883 predicate(Universe::narrow_oop_base() != NULL && ExpandLoadingBaseDecode); 4884 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST); 4885 // TODO: s390 port size(VARIABLE_SIZE); 4886 expand %{ 4887 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %} 4888 iRegL base; 4889 loadBase(base, baseImm); 4890 decodeN_base(dst, src, base, cr); 4891 %} 4892 %} 4893 4894 // Decoder for heapbased mode peeling off loading the base. 4895 instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{ 4896 match(Set dst (DecodeN src)); 4897 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull || 4898 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 4899 Universe::narrow_oop_base() != NULL && ExpandLoadingBaseDecode_NN); 4900 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); 4901 // TODO: s390 port size(VARIABLE_SIZE); 4902 expand %{ 4903 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %} 4904 iRegL base; 4905 loadBase(base, baseImm); 4906 decodeN_NN_base(dst, src, base, cr); 4907 %} 4908 %} 4909 4910 // Encode Compressed Pointer 4911 4912 // General encoder 4913 instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{ 4914 match(Set dst (EncodeP src)); 4915 effect(KILL cr); 4916 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) && 4917 (Universe::narrow_oop_base() == 0 || 4918 Universe::narrow_oop_base_disjoint() || 4919 !ExpandLoadingBaseEncode)); 4920 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); 4921 // TODO: s390 port size(VARIABLE_SIZE); 4922 format %{ "encodeP $dst,$src\t# (encode cOop)" %} 4923 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %} 4924 ins_pipe(pipe_class_dummy); 4925 %} 4926 4927 // General class encoder 4928 instruct encodeKlass(iRegN dst, iRegP src, flagsReg cr) %{ 4929 match(Set dst (EncodePKlass src)); 4930 effect(KILL cr); 4931 format %{ "encode_klass $dst,$src" %} 4932 ins_encode %{ __ encode_klass_not_null($dst$$Register, $src$$Register); %} 4933 ins_pipe(pipe_class_dummy); 4934 %} 4935 4936 instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{ 4937 match(Set dst (EncodeP src)); 4938 effect(KILL cr); 4939 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) && 4940 (Universe::narrow_oop_base() == 0 || 4941 Universe::narrow_oop_base_disjoint() || 4942 !ExpandLoadingBaseEncode_NN)); 4943 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); 4944 // TODO: s390 port size(VARIABLE_SIZE); 4945 format %{ "encodeP $dst,$src\t# (encode cOop)" %} 4946 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %} 4947 ins_pipe(pipe_class_dummy); 4948 %} 4949 4950 // Encoder for heapbased mode peeling off loading the base. 4951 instruct encodeP_base(iRegN dst, iRegP src, iRegL base) %{ 4952 match(Set dst (EncodeP src (Binary base dst))); 4953 effect(TEMP_DEF dst); 4954 predicate(false); 4955 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); 4956 // TODO: s390 port size(VARIABLE_SIZE); 4957 format %{ "encodeP $dst = ($src>>3) +$base + pow2_offset\t# (encode cOop)" %} 4958 ins_encode %{ 4959 jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset 4960 (((uint64_t)(intptr_t)Universe::narrow_oop_base()) >> Universe::narrow_oop_shift()); 4961 __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset); 4962 %} 4963 ins_pipe(pipe_class_dummy); 4964 %} 4965 4966 // Encoder for heapbased mode peeling off loading the base. 4967 instruct encodeP_NN_base(iRegN dst, iRegP src, iRegL base, immL pow2_offset) %{ 4968 match(Set dst (EncodeP src base)); 4969 effect(USE pow2_offset); 4970 predicate(false); 4971 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); 4972 // TODO: s390 port size(VARIABLE_SIZE); 4973 format %{ "encodeP $dst = ($src>>3) +$base + $pow2_offset\t# (encode cOop)" %} 4974 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %} 4975 ins_pipe(pipe_class_dummy); 4976 %} 4977 4978 // Encoder for heapbased mode peeling off loading the base. 4979 instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{ 4980 match(Set dst (EncodeP src)); 4981 effect(KILL cr); 4982 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) && 4983 (Universe::narrow_oop_base_overlaps() && ExpandLoadingBaseEncode)); 4984 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); 4985 // TODO: s390 port size(VARIABLE_SIZE); 4986 expand %{ 4987 immL baseImm %{ ((jlong)(intptr_t)Universe::narrow_oop_base()) >> Universe::narrow_oop_shift() %} 4988 immL_0 zero %{ (0) %} 4989 flagsReg ccr; 4990 iRegL base; 4991 iRegL negBase; 4992 loadBase(base, baseImm); 4993 negL_reg_reg(negBase, zero, base, ccr); 4994 encodeP_base(dst, src, negBase); 4995 %} 4996 %} 4997 4998 // Encoder for heapbased mode peeling off loading the base. 4999 instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{ 5000 match(Set dst (EncodeP src)); 5001 effect(KILL cr); 5002 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) && 5003 (Universe::narrow_oop_base_overlaps() && ExpandLoadingBaseEncode_NN)); 5004 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); 5005 // TODO: s390 port size(VARIABLE_SIZE); 5006 expand %{ 5007 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %} 5008 immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)Universe::narrow_oop_base())) %} 5009 immL_0 zero %{ 0 %} 5010 flagsReg ccr; 5011 iRegL base; 5012 iRegL negBase; 5013 loadBase(base, baseImm); 5014 negL_reg_reg(negBase, zero, base, ccr); 5015 encodeP_NN_base(dst, src, negBase, pow2_offset); 5016 %} 5017 %} 5018 5019 // Store Compressed Pointer 5020 5021 // Store Compressed Pointer 5022 instruct storeN(memory mem, iRegN_P2N src) %{ 5023 match(Set mem (StoreN mem src)); 5024 ins_cost(MEMORY_REF_COST); 5025 size(Z_DISP_SIZE); 5026 format %{ "ST $src,$mem\t# (cOop)" %} 5027 opcode(STY_ZOPC, ST_ZOPC); 5028 ins_encode(z_form_rt_mem_opt(src, mem)); 5029 ins_pipe(pipe_class_dummy); 5030 %} 5031 5032 // Store Compressed Klass pointer 5033 instruct storeNKlass(memory mem, iRegN src) %{ 5034 match(Set mem (StoreNKlass mem src)); 5035 ins_cost(MEMORY_REF_COST); 5036 size(Z_DISP_SIZE); 5037 format %{ "ST $src,$mem\t# (cKlass)" %} 5038 opcode(STY_ZOPC, ST_ZOPC); 5039 ins_encode(z_form_rt_mem_opt(src, mem)); 5040 ins_pipe(pipe_class_dummy); 5041 %} 5042 5043 // Compare Compressed Pointers 5044 5045 instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{ 5046 match(Set cr (CmpN src1 src2)); 5047 ins_cost(DEFAULT_COST); 5048 size(2); 5049 format %{ "CLR $src1,$src2\t# (cOop)" %} 5050 opcode(CLR_ZOPC); 5051 ins_encode(z_rrform(src1, src2)); 5052 ins_pipe(pipe_class_dummy); 5053 %} 5054 5055 instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{ 5056 match(Set cr (CmpN src1 src2)); 5057 ins_cost(DEFAULT_COST); 5058 size(6); 5059 format %{ "CLFI $src1,$src2\t# (cOop) compare immediate narrow" %} 5060 ins_encode %{ 5061 AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant); 5062 __ relocate(cOop.rspec(), 1); 5063 __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value()); 5064 %} 5065 ins_pipe(pipe_class_dummy); 5066 %} 5067 5068 instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{ 5069 match(Set cr (CmpN src1 src2)); 5070 ins_cost(DEFAULT_COST); 5071 size(6); 5072 format %{ "CLFI $src1,$src2\t# (NKlass) compare immediate narrow" %} 5073 ins_encode %{ 5074 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant); 5075 __ relocate(NKlass.rspec(), 1); 5076 __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value()); 5077 %} 5078 ins_pipe(pipe_class_dummy); 5079 %} 5080 5081 instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{ 5082 match(Set cr (CmpN src1 src2)); 5083 ins_cost(DEFAULT_COST); 5084 size(2); 5085 format %{ "LTR $src1,$src2\t# (cOop) LTR because comparing against zero" %} 5086 opcode(LTR_ZOPC); 5087 ins_encode(z_rrform(src1, src1)); 5088 ins_pipe(pipe_class_dummy); 5089 %} 5090 5091 5092 //----------MemBar Instructions----------------------------------------------- 5093 5094 // Memory barrier flavors 5095 5096 instruct membar_acquire() %{ 5097 match(MemBarAcquire); 5098 match(LoadFence); 5099 ins_cost(4*MEMORY_REF_COST); 5100 size(0); 5101 format %{ "MEMBAR-acquire" %} 5102 ins_encode %{ __ z_acquire(); %} 5103 ins_pipe(pipe_class_dummy); 5104 %} 5105 5106 instruct membar_acquire_lock() %{ 5107 match(MemBarAcquireLock); 5108 ins_cost(0); 5109 size(0); 5110 format %{ "MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 5111 ins_encode(/*empty*/); 5112 ins_pipe(pipe_class_dummy); 5113 %} 5114 5115 instruct membar_release() %{ 5116 match(MemBarRelease); 5117 match(StoreFence); 5118 ins_cost(4 * MEMORY_REF_COST); 5119 size(0); 5120 format %{ "MEMBAR-release" %} 5121 ins_encode %{ __ z_release(); %} 5122 ins_pipe(pipe_class_dummy); 5123 %} 5124 5125 instruct membar_release_lock() %{ 5126 match(MemBarReleaseLock); 5127 ins_cost(0); 5128 size(0); 5129 format %{ "MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 5130 ins_encode(/*empty*/); 5131 ins_pipe(pipe_class_dummy); 5132 %} 5133 5134 instruct membar_volatile() %{ 5135 match(MemBarVolatile); 5136 ins_cost(4 * MEMORY_REF_COST); 5137 size(2); 5138 format %{ "MEMBAR-volatile" %} 5139 ins_encode %{ __ z_fence(); %} 5140 ins_pipe(pipe_class_dummy); 5141 %} 5142 5143 instruct unnecessary_membar_volatile() %{ 5144 match(MemBarVolatile); 5145 predicate(Matcher::post_store_load_barrier(n)); 5146 ins_cost(0); 5147 size(0); 5148 format %{ "# MEMBAR-volatile (empty)" %} 5149 ins_encode(/*empty*/); 5150 ins_pipe(pipe_class_dummy); 5151 %} 5152 5153 instruct membar_CPUOrder() %{ 5154 match(MemBarCPUOrder); 5155 ins_cost(0); 5156 // TODO: s390 port size(FIXED_SIZE); 5157 format %{ "MEMBAR-CPUOrder (empty)" %} 5158 ins_encode(/*empty*/); 5159 ins_pipe(pipe_class_dummy); 5160 %} 5161 5162 instruct membar_storestore() %{ 5163 match(MemBarStoreStore); 5164 ins_cost(0); 5165 size(0); 5166 format %{ "MEMBAR-storestore (empty)" %} 5167 ins_encode(); 5168 ins_pipe(pipe_class_dummy); 5169 %} 5170 5171 5172 //----------Register Move Instructions----------------------------------------- 5173 instruct roundDouble_nop(regD dst) %{ 5174 match(Set dst (RoundDouble dst)); 5175 ins_cost(0); 5176 // TODO: s390 port size(FIXED_SIZE); 5177 // z/Architecture results are already "rounded" (i.e., normal-format IEEE). 5178 ins_encode(); 5179 ins_pipe(pipe_class_dummy); 5180 %} 5181 5182 instruct roundFloat_nop(regF dst) %{ 5183 match(Set dst (RoundFloat dst)); 5184 ins_cost(0); 5185 // TODO: s390 port size(FIXED_SIZE); 5186 // z/Architecture results are already "rounded" (i.e., normal-format IEEE). 5187 ins_encode(); 5188 ins_pipe(pipe_class_dummy); 5189 %} 5190 5191 // Cast Long to Pointer for unsafe natives. 5192 instruct castX2P(iRegP dst, iRegL src) %{ 5193 match(Set dst (CastX2P src)); 5194 // TODO: s390 port size(VARIABLE_SIZE); 5195 format %{ "LGR $dst,$src\t # CastX2P" %} 5196 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %} 5197 ins_pipe(pipe_class_dummy); 5198 %} 5199 5200 // Cast Pointer to Long for unsafe natives. 5201 instruct castP2X(iRegL dst, iRegP_N2P src) %{ 5202 match(Set dst (CastP2X src)); 5203 // TODO: s390 port size(VARIABLE_SIZE); 5204 format %{ "LGR $dst,$src\t # CastP2X" %} 5205 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %} 5206 ins_pipe(pipe_class_dummy); 5207 %} 5208 5209 instruct stfSSD(stackSlotD stkSlot, regD src) %{ 5210 // %%%% TODO: Tell the coalescer that this kind of node is a copy! 5211 match(Set stkSlot src); // chain rule 5212 ins_cost(MEMORY_REF_COST); 5213 // TODO: s390 port size(FIXED_SIZE); 5214 format %{ " STD $src,$stkSlot\t # stk" %} 5215 opcode(STD_ZOPC); 5216 ins_encode(z_form_rt_mem(src, stkSlot)); 5217 ins_pipe(pipe_class_dummy); 5218 %} 5219 5220 instruct stfSSF(stackSlotF stkSlot, regF src) %{ 5221 // %%%% TODO: Tell the coalescer that this kind of node is a copy! 5222 match(Set stkSlot src); // chain rule 5223 ins_cost(MEMORY_REF_COST); 5224 // TODO: s390 port size(FIXED_SIZE); 5225 format %{ "STE $src,$stkSlot\t # stk" %} 5226 opcode(STE_ZOPC); 5227 ins_encode(z_form_rt_mem(src, stkSlot)); 5228 ins_pipe(pipe_class_dummy); 5229 %} 5230 5231 //----------Conditional Move--------------------------------------------------- 5232 5233 instruct cmovN_reg(cmpOp cmp, flagsReg cr, iRegN dst, iRegN_P2N src) %{ 5234 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src))); 5235 ins_cost(DEFAULT_COST + BRANCH_COST); 5236 // TODO: s390 port size(VARIABLE_SIZE); 5237 format %{ "CMoveN,$cmp $dst,$src" %} 5238 ins_encode(z_enc_cmov_reg(cmp,dst,src)); 5239 ins_pipe(pipe_class_dummy); 5240 %} 5241 5242 instruct cmovN_imm(cmpOp cmp, flagsReg cr, iRegN dst, immN0 src) %{ 5243 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src))); 5244 ins_cost(DEFAULT_COST + BRANCH_COST); 5245 // TODO: s390 port size(VARIABLE_SIZE); 5246 format %{ "CMoveN,$cmp $dst,$src" %} 5247 ins_encode(z_enc_cmov_imm(cmp,dst,src)); 5248 ins_pipe(pipe_class_dummy); 5249 %} 5250 5251 instruct cmovI_reg(cmpOp cmp, flagsReg cr, iRegI dst, iRegI src) %{ 5252 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src))); 5253 ins_cost(DEFAULT_COST + BRANCH_COST); 5254 // TODO: s390 port size(VARIABLE_SIZE); 5255 format %{ "CMoveI,$cmp $dst,$src" %} 5256 ins_encode(z_enc_cmov_reg(cmp,dst,src)); 5257 ins_pipe(pipe_class_dummy); 5258 %} 5259 5260 instruct cmovI_imm(cmpOp cmp, flagsReg cr, iRegI dst, immI16 src) %{ 5261 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src))); 5262 ins_cost(DEFAULT_COST + BRANCH_COST); 5263 // TODO: s390 port size(VARIABLE_SIZE); 5264 format %{ "CMoveI,$cmp $dst,$src" %} 5265 ins_encode(z_enc_cmov_imm(cmp,dst,src)); 5266 ins_pipe(pipe_class_dummy); 5267 %} 5268 5269 instruct cmovP_reg(cmpOp cmp, flagsReg cr, iRegP dst, iRegP_N2P src) %{ 5270 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src))); 5271 ins_cost(DEFAULT_COST + BRANCH_COST); 5272 // TODO: s390 port size(VARIABLE_SIZE); 5273 format %{ "CMoveP,$cmp $dst,$src" %} 5274 ins_encode(z_enc_cmov_reg(cmp,dst,src)); 5275 ins_pipe(pipe_class_dummy); 5276 %} 5277 5278 instruct cmovP_imm(cmpOp cmp, flagsReg cr, iRegP dst, immP0 src) %{ 5279 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src))); 5280 ins_cost(DEFAULT_COST + BRANCH_COST); 5281 // TODO: s390 port size(VARIABLE_SIZE); 5282 format %{ "CMoveP,$cmp $dst,$src" %} 5283 ins_encode(z_enc_cmov_imm(cmp,dst,src)); 5284 ins_pipe(pipe_class_dummy); 5285 %} 5286 5287 instruct cmovF_reg(cmpOpF cmp, flagsReg cr, regF dst, regF src) %{ 5288 match(Set dst (CMoveF (Binary cmp cr) (Binary dst src))); 5289 ins_cost(DEFAULT_COST + BRANCH_COST); 5290 // TODO: s390 port size(VARIABLE_SIZE); 5291 format %{ "CMoveF,$cmp $dst,$src" %} 5292 ins_encode %{ 5293 // Don't emit code if operands are identical (same register). 5294 if ($dst$$FloatRegister != $src$$FloatRegister) { 5295 Label done; 5296 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done); 5297 __ z_ler($dst$$FloatRegister, $src$$FloatRegister); 5298 __ bind(done); 5299 } 5300 %} 5301 ins_pipe(pipe_class_dummy); 5302 %} 5303 5304 instruct cmovD_reg(cmpOpF cmp, flagsReg cr, regD dst, regD src) %{ 5305 match(Set dst (CMoveD (Binary cmp cr) (Binary dst src))); 5306 ins_cost(DEFAULT_COST + BRANCH_COST); 5307 // TODO: s390 port size(VARIABLE_SIZE); 5308 format %{ "CMoveD,$cmp $dst,$src" %} 5309 ins_encode %{ 5310 // Don't emit code if operands are identical (same register). 5311 if ($dst$$FloatRegister != $src$$FloatRegister) { 5312 Label done; 5313 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done); 5314 __ z_ldr($dst$$FloatRegister, $src$$FloatRegister); 5315 __ bind(done); 5316 } 5317 %} 5318 ins_pipe(pipe_class_dummy); 5319 %} 5320 5321 instruct cmovL_reg(cmpOp cmp, flagsReg cr, iRegL dst, iRegL src) %{ 5322 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src))); 5323 ins_cost(DEFAULT_COST + BRANCH_COST); 5324 // TODO: s390 port size(VARIABLE_SIZE); 5325 format %{ "CMoveL,$cmp $dst,$src" %} 5326 ins_encode(z_enc_cmov_reg(cmp,dst,src)); 5327 ins_pipe(pipe_class_dummy); 5328 %} 5329 5330 instruct cmovL_imm(cmpOp cmp, flagsReg cr, iRegL dst, immL16 src) %{ 5331 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src))); 5332 ins_cost(DEFAULT_COST + BRANCH_COST); 5333 // TODO: s390 port size(VARIABLE_SIZE); 5334 format %{ "CMoveL,$cmp $dst,$src" %} 5335 ins_encode(z_enc_cmov_imm(cmp,dst,src)); 5336 ins_pipe(pipe_class_dummy); 5337 %} 5338 5339 //----------OS and Locking Instructions---------------------------------------- 5340 5341 // This name is KNOWN by the ADLC and cannot be changed. 5342 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type 5343 // for this guy. 5344 instruct tlsLoadP(threadRegP dst) %{ 5345 match(Set dst (ThreadLocal)); 5346 ins_cost(0); 5347 size(0); 5348 ins_should_rematerialize(true); 5349 format %{ "# $dst=ThreadLocal" %} 5350 ins_encode(/* empty */); 5351 ins_pipe(pipe_class_dummy); 5352 %} 5353 5354 instruct checkCastPP(iRegP dst) %{ 5355 match(Set dst (CheckCastPP dst)); 5356 size(0); 5357 format %{ "# checkcastPP of $dst" %} 5358 ins_encode(/*empty*/); 5359 ins_pipe(pipe_class_dummy); 5360 %} 5361 5362 instruct castPP(iRegP dst) %{ 5363 match(Set dst (CastPP dst)); 5364 size(0); 5365 format %{ "# castPP of $dst" %} 5366 ins_encode(/*empty*/); 5367 ins_pipe(pipe_class_dummy); 5368 %} 5369 5370 instruct castII(iRegI dst) %{ 5371 match(Set dst (CastII dst)); 5372 size(0); 5373 format %{ "# castII of $dst" %} 5374 ins_encode(/*empty*/); 5375 ins_pipe(pipe_class_dummy); 5376 %} 5377 5378 5379 //----------Conditional_store-------------------------------------------------- 5380 // Conditional-store of the updated heap-top. 5381 // Used during allocation of the shared heap. 5382 // Sets flags (EQ) on success. 5383 5384 // Implement LoadPLocked. Must be ordered against changes of the memory location 5385 // by storePConditional. 5386 // Don't know whether this is ever used. 5387 instruct loadPLocked(iRegP dst, memory mem) %{ 5388 match(Set dst (LoadPLocked mem)); 5389 ins_cost(MEMORY_REF_COST); 5390 size(Z_DISP3_SIZE); 5391 format %{ "LG $dst,$mem\t # LoadPLocked" %} 5392 opcode(LG_ZOPC, LG_ZOPC); 5393 ins_encode(z_form_rt_mem_opt(dst, mem)); 5394 ins_pipe(pipe_class_dummy); 5395 %} 5396 5397 // As compareAndSwapP, but return flag register instead of boolean value in 5398 // int register. 5399 // This instruction is matched if UseTLAB is off. Needed to pass 5400 // option tests. Mem_ptr must be a memory operand, else this node 5401 // does not get Flag_needs_anti_dependence_check set by adlc. If this 5402 // is not set this node can be rematerialized which leads to errors. 5403 instruct storePConditional(indirect mem_ptr, rarg5RegP oldval, iRegP_N2P newval, flagsReg cr) %{ 5404 match(Set cr (StorePConditional mem_ptr (Binary oldval newval))); 5405 effect(KILL oldval); 5406 // TODO: s390 port size(FIXED_SIZE); 5407 format %{ "storePConditional $oldval,$newval,$mem_ptr" %} 5408 ins_encode(z_enc_casL(oldval, newval, mem_ptr)); 5409 ins_pipe(pipe_class_dummy); 5410 %} 5411 5412 // As compareAndSwapL, but return flag register instead of boolean value in 5413 // int register. 5414 // Used by sun/misc/AtomicLongCSImpl.java. Mem_ptr must be a memory 5415 // operand, else this node does not get 5416 // Flag_needs_anti_dependence_check set by adlc. If this is not set 5417 // this node can be rematerialized which leads to errors. 5418 instruct storeLConditional(indirect mem_ptr, rarg5RegL oldval, iRegL newval, flagsReg cr) %{ 5419 match(Set cr (StoreLConditional mem_ptr (Binary oldval newval))); 5420 effect(KILL oldval); 5421 // TODO: s390 port size(FIXED_SIZE); 5422 format %{ "storePConditional $oldval,$newval,$mem_ptr" %} 5423 ins_encode(z_enc_casL(oldval, newval, mem_ptr)); 5424 ins_pipe(pipe_class_dummy); 5425 %} 5426 5427 // No flag versions for CompareAndSwap{P,I,L,N} because matcher can't match them. 5428 5429 instruct compareAndSwapI_bool(iRegP mem_ptr, rarg5RegI oldval, iRegI newval, iRegI res, flagsReg cr) %{ 5430 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 5431 effect(USE mem_ptr, USE_KILL oldval, KILL cr); 5432 size(16); 5433 format %{ "$res = CompareAndSwapI $oldval,$newval,$mem_ptr" %} 5434 ins_encode(z_enc_casI(oldval, newval, mem_ptr), 5435 z_enc_cctobool(res)); 5436 ins_pipe(pipe_class_dummy); 5437 %} 5438 5439 instruct compareAndSwapL_bool(iRegP mem_ptr, rarg5RegL oldval, iRegL newval, iRegI res, flagsReg cr) %{ 5440 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 5441 effect(USE mem_ptr, USE_KILL oldval, KILL cr); 5442 size(18); 5443 format %{ "$res = CompareAndSwapL $oldval,$newval,$mem_ptr" %} 5444 ins_encode(z_enc_casL(oldval, newval, mem_ptr), 5445 z_enc_cctobool(res)); 5446 ins_pipe(pipe_class_dummy); 5447 %} 5448 5449 instruct compareAndSwapP_bool(iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, iRegI res, flagsReg cr) %{ 5450 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 5451 effect(USE mem_ptr, USE_KILL oldval, KILL cr); 5452 size(18); 5453 format %{ "$res = CompareAndSwapP $oldval,$newval,$mem_ptr" %} 5454 ins_encode(z_enc_casL(oldval, newval, mem_ptr), 5455 z_enc_cctobool(res)); 5456 ins_pipe(pipe_class_dummy); 5457 %} 5458 5459 instruct compareAndSwapN_bool(iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, iRegI res, flagsReg cr) %{ 5460 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 5461 effect(USE mem_ptr, USE_KILL oldval, KILL cr); 5462 size(16); 5463 format %{ "$res = CompareAndSwapN $oldval,$newval,$mem_ptr" %} 5464 ins_encode(z_enc_casI(oldval, newval, mem_ptr), 5465 z_enc_cctobool(res)); 5466 ins_pipe(pipe_class_dummy); 5467 %} 5468 5469 //----------Atomic operations on memory (GetAndSet*, GetAndAdd*)--------------- 5470 5471 // Exploit: direct memory arithmetic 5472 // Prereqs: - instructions available 5473 // - instructions guarantee atomicity 5474 // - immediate operand to be added 5475 // - immediate operand is small enough (8-bit signed). 5476 // - result of instruction is not used 5477 instruct addI_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immI8 src, flagsReg cr) %{ 5478 match(Set dummy (GetAndAddI mem src)); 5479 effect(KILL cr); 5480 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used()); 5481 ins_cost(MEMORY_REF_COST); 5482 size(6); 5483 format %{ "ASI [$mem],$src\t # GetAndAddI (atomic)" %} 5484 opcode(ASI_ZOPC); 5485 ins_encode(z_siyform(mem, src)); 5486 ins_pipe(pipe_class_dummy); 5487 %} 5488 5489 // Fallback: direct memory arithmetic not available 5490 // Disadvantages: - CS-Loop required, very expensive. 5491 // - more code generated (26 to xx bytes vs. 6 bytes) 5492 instruct addI_mem_imm16_atomic(memoryRSY mem, iRegI dst, immI16 src, iRegI tmp, flagsReg cr) %{ 5493 match(Set dst (GetAndAddI mem src)); 5494 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5495 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5496 format %{ "BEGIN ATOMIC {\n\t" 5497 " LGF $dst,[$mem]\n\t" 5498 " AHIK $tmp,$dst,$src\n\t" 5499 " CSY $dst,$tmp,$mem\n\t" 5500 " retry if failed\n\t" 5501 "} END ATOMIC" 5502 %} 5503 ins_encode %{ 5504 Register Rdst = $dst$$Register; 5505 Register Rtmp = $tmp$$Register; 5506 int Isrc = $src$$constant; 5507 Label retry; 5508 5509 // Iterate until update with incremented value succeeds. 5510 __ z_lgf(Rdst, $mem$$Address); // current contents 5511 __ bind(retry); 5512 // Calculate incremented value. 5513 if (VM_Version::has_DistinctOpnds()) { 5514 __ z_ahik(Rtmp, Rdst, Isrc); 5515 } else { 5516 __ z_lr(Rtmp, Rdst); 5517 __ z_ahi(Rtmp, Isrc); 5518 } 5519 // Swap into memory location. 5520 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5521 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5522 %} 5523 ins_pipe(pipe_class_dummy); 5524 %} 5525 5526 instruct addI_mem_imm32_atomic(memoryRSY mem, iRegI dst, immI src, iRegI tmp, flagsReg cr) %{ 5527 match(Set dst (GetAndAddI mem src)); 5528 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5529 ins_cost(MEMORY_REF_COST+200*DEFAULT_COST); 5530 format %{ "BEGIN ATOMIC {\n\t" 5531 " LGF $dst,[$mem]\n\t" 5532 " LGR $tmp,$dst\n\t" 5533 " AFI $tmp,$src\n\t" 5534 " CSY $dst,$tmp,$mem\n\t" 5535 " retry if failed\n\t" 5536 "} END ATOMIC" 5537 %} 5538 ins_encode %{ 5539 Register Rdst = $dst$$Register; 5540 Register Rtmp = $tmp$$Register; 5541 int Isrc = $src$$constant; 5542 Label retry; 5543 5544 // Iterate until update with incremented value succeeds. 5545 __ z_lgf(Rdst, $mem$$Address); // current contents 5546 __ bind(retry); 5547 // Calculate incremented value. 5548 __ z_lr(Rtmp, Rdst); 5549 __ z_afi(Rtmp, Isrc); 5550 // Swap into memory location. 5551 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5552 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5553 %} 5554 ins_pipe(pipe_class_dummy); 5555 %} 5556 5557 instruct addI_mem_reg_atomic(memoryRSY mem, iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ 5558 match(Set dst (GetAndAddI mem src)); 5559 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5560 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5561 format %{ "BEGIN ATOMIC {\n\t" 5562 " LGF $dst,[$mem]\n\t" 5563 " ARK $tmp,$dst,$src\n\t" 5564 " CSY $dst,$tmp,$mem\n\t" 5565 " retry if failed\n\t" 5566 "} END ATOMIC" 5567 %} 5568 ins_encode %{ 5569 Register Rsrc = $src$$Register; 5570 Register Rdst = $dst$$Register; 5571 Register Rtmp = $tmp$$Register; 5572 Label retry; 5573 5574 // Iterate until update with incremented value succeeds. 5575 __ z_lgf(Rdst, $mem$$Address); // current contents 5576 __ bind(retry); 5577 // Calculate incremented value. 5578 if (VM_Version::has_DistinctOpnds()) { 5579 __ z_ark(Rtmp, Rdst, Rsrc); 5580 } else { 5581 __ z_lr(Rtmp, Rdst); 5582 __ z_ar(Rtmp, Rsrc); 5583 } 5584 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5585 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5586 %} 5587 ins_pipe(pipe_class_dummy); 5588 %} 5589 5590 5591 // Exploit: direct memory arithmetic 5592 // Prereqs: - instructions available 5593 // - instructions guarantee atomicity 5594 // - immediate operand to be added 5595 // - immediate operand is small enough (8-bit signed). 5596 // - result of instruction is not used 5597 instruct addL_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immL8 src, flagsReg cr) %{ 5598 match(Set dummy (GetAndAddL mem src)); 5599 effect(KILL cr); 5600 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used()); 5601 ins_cost(MEMORY_REF_COST); 5602 size(6); 5603 format %{ "AGSI [$mem],$src\t # GetAndAddL (atomic)" %} 5604 opcode(AGSI_ZOPC); 5605 ins_encode(z_siyform(mem, src)); 5606 ins_pipe(pipe_class_dummy); 5607 %} 5608 5609 // Fallback: direct memory arithmetic not available 5610 // Disadvantages: - CS-Loop required, very expensive. 5611 // - more code generated (26 to xx bytes vs. 6 bytes) 5612 instruct addL_mem_imm16_atomic(memoryRSY mem, iRegL dst, immL16 src, iRegL tmp, flagsReg cr) %{ 5613 match(Set dst (GetAndAddL mem src)); 5614 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5615 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5616 format %{ "BEGIN ATOMIC {\n\t" 5617 " LG $dst,[$mem]\n\t" 5618 " AGHIK $tmp,$dst,$src\n\t" 5619 " CSG $dst,$tmp,$mem\n\t" 5620 " retry if failed\n\t" 5621 "} END ATOMIC" 5622 %} 5623 ins_encode %{ 5624 Register Rdst = $dst$$Register; 5625 Register Rtmp = $tmp$$Register; 5626 int Isrc = $src$$constant; 5627 Label retry; 5628 5629 // Iterate until update with incremented value succeeds. 5630 __ z_lg(Rdst, $mem$$Address); // current contents 5631 __ bind(retry); 5632 // Calculate incremented value. 5633 if (VM_Version::has_DistinctOpnds()) { 5634 __ z_aghik(Rtmp, Rdst, Isrc); 5635 } else { 5636 __ z_lgr(Rtmp, Rdst); 5637 __ z_aghi(Rtmp, Isrc); 5638 } 5639 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5640 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5641 %} 5642 ins_pipe(pipe_class_dummy); 5643 %} 5644 5645 instruct addL_mem_imm32_atomic(memoryRSY mem, iRegL dst, immL32 src, iRegL tmp, flagsReg cr) %{ 5646 match(Set dst (GetAndAddL mem src)); 5647 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5648 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5649 format %{ "BEGIN ATOMIC {\n\t" 5650 " LG $dst,[$mem]\n\t" 5651 " LGR $tmp,$dst\n\t" 5652 " AGFI $tmp,$src\n\t" 5653 " CSG $dst,$tmp,$mem\n\t" 5654 " retry if failed\n\t" 5655 "} END ATOMIC" 5656 %} 5657 ins_encode %{ 5658 Register Rdst = $dst$$Register; 5659 Register Rtmp = $tmp$$Register; 5660 int Isrc = $src$$constant; 5661 Label retry; 5662 5663 // Iterate until update with incremented value succeeds. 5664 __ z_lg(Rdst, $mem$$Address); // current contents 5665 __ bind(retry); 5666 // Calculate incremented value. 5667 __ z_lgr(Rtmp, Rdst); 5668 __ z_agfi(Rtmp, Isrc); 5669 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5670 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5671 %} 5672 ins_pipe(pipe_class_dummy); 5673 %} 5674 5675 instruct addL_mem_reg_atomic(memoryRSY mem, iRegL dst, iRegL src, iRegL tmp, flagsReg cr) %{ 5676 match(Set dst (GetAndAddL mem src)); 5677 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5678 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5679 format %{ "BEGIN ATOMIC {\n\t" 5680 " LG $dst,[$mem]\n\t" 5681 " AGRK $tmp,$dst,$src\n\t" 5682 " CSG $dst,$tmp,$mem\n\t" 5683 " retry if failed\n\t" 5684 "} END ATOMIC" 5685 %} 5686 ins_encode %{ 5687 Register Rsrc = $src$$Register; 5688 Register Rdst = $dst$$Register; 5689 Register Rtmp = $tmp$$Register; 5690 Label retry; 5691 5692 // Iterate until update with incremented value succeeds. 5693 __ z_lg(Rdst, $mem$$Address); // current contents 5694 __ bind(retry); 5695 // Calculate incremented value. 5696 if (VM_Version::has_DistinctOpnds()) { 5697 __ z_agrk(Rtmp, Rdst, Rsrc); 5698 } else { 5699 __ z_lgr(Rtmp, Rdst); 5700 __ z_agr(Rtmp, Rsrc); 5701 } 5702 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5703 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5704 %} 5705 ins_pipe(pipe_class_dummy); 5706 %} 5707 5708 // Increment value in memory, save old value in dst. 5709 instruct addI_mem_reg_atomic_z196(memoryRSY mem, iRegI dst, iRegI src) %{ 5710 match(Set dst (GetAndAddI mem src)); 5711 predicate(VM_Version::has_LoadAndALUAtomicV1()); 5712 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5713 size(6); 5714 format %{ "LAA $dst,$src,[$mem]" %} 5715 ins_encode %{ __ z_laa($dst$$Register, $src$$Register, $mem$$Address); %} 5716 ins_pipe(pipe_class_dummy); 5717 %} 5718 5719 // Increment value in memory, save old value in dst. 5720 instruct addL_mem_reg_atomic_z196(memoryRSY mem, iRegL dst, iRegL src) %{ 5721 match(Set dst (GetAndAddL mem src)); 5722 predicate(VM_Version::has_LoadAndALUAtomicV1()); 5723 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5724 size(6); 5725 format %{ "LAAG $dst,$src,[$mem]" %} 5726 ins_encode %{ __ z_laag($dst$$Register, $src$$Register, $mem$$Address); %} 5727 ins_pipe(pipe_class_dummy); 5728 %} 5729 5730 5731 instruct xchgI_reg_mem(memoryRSY mem, iRegI dst, iRegI tmp, flagsReg cr) %{ 5732 match(Set dst (GetAndSetI mem dst)); 5733 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. 5734 format %{ "XCHGI $dst,[$mem]\t # EXCHANGE (int, atomic), temp $tmp" %} 5735 ins_encode(z_enc_SwapI(mem, dst, tmp)); 5736 ins_pipe(pipe_class_dummy); 5737 %} 5738 5739 instruct xchgL_reg_mem(memoryRSY mem, iRegL dst, iRegL tmp, flagsReg cr) %{ 5740 match(Set dst (GetAndSetL mem dst)); 5741 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. 5742 format %{ "XCHGL $dst,[$mem]\t # EXCHANGE (long, atomic), temp $tmp" %} 5743 ins_encode(z_enc_SwapL(mem, dst, tmp)); 5744 ins_pipe(pipe_class_dummy); 5745 %} 5746 5747 instruct xchgN_reg_mem(memoryRSY mem, iRegN dst, iRegI tmp, flagsReg cr) %{ 5748 match(Set dst (GetAndSetN mem dst)); 5749 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. 5750 format %{ "XCHGN $dst,[$mem]\t # EXCHANGE (coop, atomic), temp $tmp" %} 5751 ins_encode(z_enc_SwapI(mem, dst, tmp)); 5752 ins_pipe(pipe_class_dummy); 5753 %} 5754 5755 instruct xchgP_reg_mem(memoryRSY mem, iRegP dst, iRegL tmp, flagsReg cr) %{ 5756 match(Set dst (GetAndSetP mem dst)); 5757 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. 5758 format %{ "XCHGP $dst,[$mem]\t # EXCHANGE (oop, atomic), temp $tmp" %} 5759 ins_encode(z_enc_SwapL(mem, dst, tmp)); 5760 ins_pipe(pipe_class_dummy); 5761 %} 5762 5763 5764 //----------Arithmetic Instructions-------------------------------------------- 5765 5766 // The rules are sorted by right operand type and operand length. Please keep 5767 // it that way. 5768 // Left operand type is always reg. Left operand len is I, L, P 5769 // Right operand type is reg, imm, mem. Right operand len is S, I, L, P 5770 // Special instruction formats, e.g. multi-operand, are inserted at the end. 5771 5772 // ADD 5773 5774 // REG = REG + REG 5775 5776 // Register Addition 5777 instruct addI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{ 5778 match(Set dst (AddI dst src)); 5779 effect(KILL cr); 5780 // TODO: s390 port size(FIXED_SIZE); 5781 format %{ "AR $dst,$src\t # int CISC ALU" %} 5782 opcode(AR_ZOPC); 5783 ins_encode(z_rrform(dst, src)); 5784 ins_pipe(pipe_class_dummy); 5785 %} 5786 5787 // Avoid use of LA(Y) for general ALU operation. 5788 instruct addI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 5789 match(Set dst (AddI src1 src2)); 5790 effect(KILL cr); 5791 predicate(VM_Version::has_DistinctOpnds()); 5792 ins_cost(DEFAULT_COST); 5793 size(4); 5794 format %{ "ARK $dst,$src1,$src2\t # int RISC ALU" %} 5795 opcode(ARK_ZOPC); 5796 ins_encode(z_rrfform(dst, src1, src2)); 5797 ins_pipe(pipe_class_dummy); 5798 %} 5799 5800 // REG = REG + IMM 5801 5802 // Avoid use of LA(Y) for general ALU operation. 5803 // Immediate Addition 5804 instruct addI_reg_imm16_CISC(iRegI dst, immI16 con, flagsReg cr) %{ 5805 match(Set dst (AddI dst con)); 5806 effect(KILL cr); 5807 ins_cost(DEFAULT_COST); 5808 // TODO: s390 port size(FIXED_SIZE); 5809 format %{ "AHI $dst,$con\t # int CISC ALU" %} 5810 opcode(AHI_ZOPC); 5811 ins_encode(z_riform_signed(dst, con)); 5812 ins_pipe(pipe_class_dummy); 5813 %} 5814 5815 // Avoid use of LA(Y) for general ALU operation. 5816 // Immediate Addition 5817 instruct addI_reg_imm16_RISC(iRegI dst, iRegI src, immI16 con, flagsReg cr) %{ 5818 match(Set dst (AddI src con)); 5819 effect(KILL cr); 5820 predicate( VM_Version::has_DistinctOpnds()); 5821 ins_cost(DEFAULT_COST); 5822 // TODO: s390 port size(FIXED_SIZE); 5823 format %{ "AHIK $dst,$src,$con\t # int RISC ALU" %} 5824 opcode(AHIK_ZOPC); 5825 ins_encode(z_rieform_d(dst, src, con)); 5826 ins_pipe(pipe_class_dummy); 5827 %} 5828 5829 // Immediate Addition 5830 instruct addI_reg_imm32(iRegI dst, immI src, flagsReg cr) %{ 5831 match(Set dst (AddI dst src)); 5832 effect(KILL cr); 5833 ins_cost(DEFAULT_COST_HIGH); 5834 size(6); 5835 format %{ "AFI $dst,$src" %} 5836 opcode(AFI_ZOPC); 5837 ins_encode(z_rilform_signed(dst, src)); 5838 ins_pipe(pipe_class_dummy); 5839 %} 5840 5841 // Immediate Addition 5842 instruct addI_reg_imm12(iRegI dst, iRegI src, uimmI12 con) %{ 5843 match(Set dst (AddI src con)); 5844 predicate(PreferLAoverADD); 5845 ins_cost(DEFAULT_COST_LOW); 5846 size(4); 5847 format %{ "LA $dst,$con(,$src)\t # int d12(,b)" %} 5848 opcode(LA_ZOPC); 5849 ins_encode(z_rxform_imm_reg(dst, con, src)); 5850 ins_pipe(pipe_class_dummy); 5851 %} 5852 5853 // Immediate Addition 5854 instruct addI_reg_imm20(iRegI dst, iRegI src, immI20 con) %{ 5855 match(Set dst (AddI src con)); 5856 predicate(PreferLAoverADD); 5857 ins_cost(DEFAULT_COST); 5858 size(6); 5859 format %{ "LAY $dst,$con(,$src)\t # int d20(,b)" %} 5860 opcode(LAY_ZOPC); 5861 ins_encode(z_rxyform_imm_reg(dst, con, src)); 5862 ins_pipe(pipe_class_dummy); 5863 %} 5864 5865 instruct addI_reg_reg_imm12(iRegI dst, iRegI src1, iRegI src2, uimmI12 con) %{ 5866 match(Set dst (AddI (AddI src1 src2) con)); 5867 predicate( PreferLAoverADD); 5868 ins_cost(DEFAULT_COST_LOW); 5869 size(4); 5870 format %{ "LA $dst,$con($src1,$src2)\t # int d12(x,b)" %} 5871 opcode(LA_ZOPC); 5872 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); 5873 ins_pipe(pipe_class_dummy); 5874 %} 5875 5876 instruct addI_reg_reg_imm20(iRegI dst, iRegI src1, iRegI src2, immI20 con) %{ 5877 match(Set dst (AddI (AddI src1 src2) con)); 5878 predicate(PreferLAoverADD); 5879 ins_cost(DEFAULT_COST); 5880 size(6); 5881 format %{ "LAY $dst,$con($src1,$src2)\t # int d20(x,b)" %} 5882 opcode(LAY_ZOPC); 5883 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); 5884 ins_pipe(pipe_class_dummy); 5885 %} 5886 5887 // REG = REG + MEM 5888 5889 instruct addI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 5890 match(Set dst (AddI dst (LoadI src))); 5891 effect(KILL cr); 5892 ins_cost(MEMORY_REF_COST); 5893 // TODO: s390 port size(VARIABLE_SIZE); 5894 format %{ "A(Y) $dst, $src\t # int" %} 5895 opcode(AY_ZOPC, A_ZOPC); 5896 ins_encode(z_form_rt_mem_opt(dst, src)); 5897 ins_pipe(pipe_class_dummy); 5898 %} 5899 5900 // MEM = MEM + IMM 5901 5902 // Add Immediate to 4-byte memory operand and result 5903 instruct addI_mem_imm(memoryRSY mem, immI8 src, flagsReg cr) %{ 5904 match(Set mem (StoreI mem (AddI (LoadI mem) src))); 5905 effect(KILL cr); 5906 predicate(VM_Version::has_MemWithImmALUOps()); 5907 ins_cost(MEMORY_REF_COST); 5908 size(6); 5909 format %{ "ASI $mem,$src\t # direct mem add 4" %} 5910 opcode(ASI_ZOPC); 5911 ins_encode(z_siyform(mem, src)); 5912 ins_pipe(pipe_class_dummy); 5913 %} 5914 5915 5916 // 5917 5918 // REG = REG + REG 5919 5920 instruct addL_reg_regI(iRegL dst, iRegI src, flagsReg cr) %{ 5921 match(Set dst (AddL dst (ConvI2L src))); 5922 effect(KILL cr); 5923 size(4); 5924 format %{ "AGFR $dst,$src\t # long<-int CISC ALU" %} 5925 opcode(AGFR_ZOPC); 5926 ins_encode(z_rreform(dst, src)); 5927 ins_pipe(pipe_class_dummy); 5928 %} 5929 5930 instruct addL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{ 5931 match(Set dst (AddL dst src)); 5932 effect(KILL cr); 5933 // TODO: s390 port size(FIXED_SIZE); 5934 format %{ "AGR $dst, $src\t # long CISC ALU" %} 5935 opcode(AGR_ZOPC); 5936 ins_encode(z_rreform(dst, src)); 5937 ins_pipe(pipe_class_dummy); 5938 %} 5939 5940 // Avoid use of LA(Y) for general ALU operation. 5941 instruct addL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 5942 match(Set dst (AddL src1 src2)); 5943 effect(KILL cr); 5944 predicate(VM_Version::has_DistinctOpnds()); 5945 ins_cost(DEFAULT_COST); 5946 size(4); 5947 format %{ "AGRK $dst,$src1,$src2\t # long RISC ALU" %} 5948 opcode(AGRK_ZOPC); 5949 ins_encode(z_rrfform(dst, src1, src2)); 5950 ins_pipe(pipe_class_dummy); 5951 %} 5952 5953 // REG = REG + IMM 5954 5955 instruct addL_reg_imm12(iRegL dst, iRegL src, uimmL12 con) %{ 5956 match(Set dst (AddL src con)); 5957 predicate( PreferLAoverADD); 5958 ins_cost(DEFAULT_COST_LOW); 5959 size(4); 5960 format %{ "LA $dst,$con(,$src)\t # long d12(,b)" %} 5961 opcode(LA_ZOPC); 5962 ins_encode(z_rxform_imm_reg(dst, con, src)); 5963 ins_pipe(pipe_class_dummy); 5964 %} 5965 5966 instruct addL_reg_imm20(iRegL dst, iRegL src, immL20 con) %{ 5967 match(Set dst (AddL src con)); 5968 predicate(PreferLAoverADD); 5969 ins_cost(DEFAULT_COST); 5970 size(6); 5971 format %{ "LAY $dst,$con(,$src)\t # long d20(,b)" %} 5972 opcode(LAY_ZOPC); 5973 ins_encode(z_rxyform_imm_reg(dst, con, src)); 5974 ins_pipe(pipe_class_dummy); 5975 %} 5976 5977 instruct addL_reg_imm32(iRegL dst, immL32 con, flagsReg cr) %{ 5978 match(Set dst (AddL dst con)); 5979 effect(KILL cr); 5980 ins_cost(DEFAULT_COST_HIGH); 5981 size(6); 5982 format %{ "AGFI $dst,$con\t # long CISC ALU" %} 5983 opcode(AGFI_ZOPC); 5984 ins_encode(z_rilform_signed(dst, con)); 5985 ins_pipe(pipe_class_dummy); 5986 %} 5987 5988 // Avoid use of LA(Y) for general ALU operation. 5989 instruct addL_reg_imm16_CISC(iRegL dst, immL16 con, flagsReg cr) %{ 5990 match(Set dst (AddL dst con)); 5991 effect(KILL cr); 5992 ins_cost(DEFAULT_COST); 5993 // TODO: s390 port size(FIXED_SIZE); 5994 format %{ "AGHI $dst,$con\t # long CISC ALU" %} 5995 opcode(AGHI_ZOPC); 5996 ins_encode(z_riform_signed(dst, con)); 5997 ins_pipe(pipe_class_dummy); 5998 %} 5999 6000 // Avoid use of LA(Y) for general ALU operation. 6001 instruct addL_reg_imm16_RISC(iRegL dst, iRegL src, immL16 con, flagsReg cr) %{ 6002 match(Set dst (AddL src con)); 6003 effect(KILL cr); 6004 predicate( VM_Version::has_DistinctOpnds()); 6005 ins_cost(DEFAULT_COST); 6006 size(6); 6007 format %{ "AGHIK $dst,$src,$con\t # long RISC ALU" %} 6008 opcode(AGHIK_ZOPC); 6009 ins_encode(z_rieform_d(dst, src, con)); 6010 ins_pipe(pipe_class_dummy); 6011 %} 6012 6013 // REG = REG + MEM 6014 6015 instruct addL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{ 6016 match(Set dst (AddL dst (ConvI2L (LoadI src)))); 6017 effect(KILL cr); 6018 ins_cost(MEMORY_REF_COST); 6019 size(Z_DISP3_SIZE); 6020 format %{ "AGF $dst, $src\t # long/int" %} 6021 opcode(AGF_ZOPC, AGF_ZOPC); 6022 ins_encode(z_form_rt_mem_opt(dst, src)); 6023 ins_pipe(pipe_class_dummy); 6024 %} 6025 6026 instruct addL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 6027 match(Set dst (AddL dst (LoadL src))); 6028 effect(KILL cr); 6029 ins_cost(MEMORY_REF_COST); 6030 size(Z_DISP3_SIZE); 6031 format %{ "AG $dst, $src\t # long" %} 6032 opcode(AG_ZOPC, AG_ZOPC); 6033 ins_encode(z_form_rt_mem_opt(dst, src)); 6034 ins_pipe(pipe_class_dummy); 6035 %} 6036 6037 instruct addL_reg_reg_imm12(iRegL dst, iRegL src1, iRegL src2, uimmL12 con) %{ 6038 match(Set dst (AddL (AddL src1 src2) con)); 6039 predicate( PreferLAoverADD); 6040 ins_cost(DEFAULT_COST_LOW); 6041 size(4); 6042 format %{ "LA $dst,$con($src1,$src2)\t # long d12(x,b)" %} 6043 opcode(LA_ZOPC); 6044 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); 6045 ins_pipe(pipe_class_dummy); 6046 %} 6047 6048 instruct addL_reg_reg_imm20(iRegL dst, iRegL src1, iRegL src2, immL20 con) %{ 6049 match(Set dst (AddL (AddL src1 src2) con)); 6050 predicate(PreferLAoverADD); 6051 ins_cost(DEFAULT_COST); 6052 size(6); 6053 format %{ "LAY $dst,$con($src1,$src2)\t # long d20(x,b)" %} 6054 opcode(LAY_ZOPC); 6055 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); 6056 ins_pipe(pipe_class_dummy); 6057 %} 6058 6059 // MEM = MEM + IMM 6060 6061 // Add Immediate to 8-byte memory operand and result. 6062 instruct addL_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{ 6063 match(Set mem (StoreL mem (AddL (LoadL mem) src))); 6064 effect(KILL cr); 6065 predicate(VM_Version::has_MemWithImmALUOps()); 6066 ins_cost(MEMORY_REF_COST); 6067 size(6); 6068 format %{ "AGSI $mem,$src\t # direct mem add 8" %} 6069 opcode(AGSI_ZOPC); 6070 ins_encode(z_siyform(mem, src)); 6071 ins_pipe(pipe_class_dummy); 6072 %} 6073 6074 6075 // REG = REG + REG 6076 6077 // Ptr Addition 6078 instruct addP_reg_reg_LA(iRegP dst, iRegP_N2P src1, iRegL src2) %{ 6079 match(Set dst (AddP src1 src2)); 6080 predicate( PreferLAoverADD); 6081 ins_cost(DEFAULT_COST); 6082 size(4); 6083 format %{ "LA $dst,#0($src1,$src2)\t # ptr 0(x,b)" %} 6084 opcode(LA_ZOPC); 6085 ins_encode(z_rxform_imm_reg_reg(dst, 0x0, src1, src2)); 6086 ins_pipe(pipe_class_dummy); 6087 %} 6088 6089 // Ptr Addition 6090 // Avoid use of LA(Y) for general ALU operation. 6091 instruct addP_reg_reg_CISC(iRegP dst, iRegL src, flagsReg cr) %{ 6092 match(Set dst (AddP dst src)); 6093 effect(KILL cr); 6094 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds()); 6095 ins_cost(DEFAULT_COST); 6096 // TODO: s390 port size(FIXED_SIZE); 6097 format %{ "ALGR $dst,$src\t # ptr CICS ALU" %} 6098 opcode(ALGR_ZOPC); 6099 ins_encode(z_rreform(dst, src)); 6100 ins_pipe(pipe_class_dummy); 6101 %} 6102 6103 // Ptr Addition 6104 // Avoid use of LA(Y) for general ALU operation. 6105 instruct addP_reg_reg_RISC(iRegP dst, iRegP_N2P src1, iRegL src2, flagsReg cr) %{ 6106 match(Set dst (AddP src1 src2)); 6107 effect(KILL cr); 6108 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds()); 6109 ins_cost(DEFAULT_COST); 6110 // TODO: s390 port size(FIXED_SIZE); 6111 format %{ "ALGRK $dst,$src1,$src2\t # ptr RISC ALU" %} 6112 opcode(ALGRK_ZOPC); 6113 ins_encode(z_rrfform(dst, src1, src2)); 6114 ins_pipe(pipe_class_dummy); 6115 %} 6116 6117 // REG = REG + IMM 6118 6119 instruct addP_reg_imm12(iRegP dst, iRegP_N2P src, uimmL12 con) %{ 6120 match(Set dst (AddP src con)); 6121 predicate( PreferLAoverADD); 6122 ins_cost(DEFAULT_COST_LOW); 6123 size(4); 6124 format %{ "LA $dst,$con(,$src)\t # ptr d12(,b)" %} 6125 opcode(LA_ZOPC); 6126 ins_encode(z_rxform_imm_reg(dst, con, src)); 6127 ins_pipe(pipe_class_dummy); 6128 %} 6129 6130 // Avoid use of LA(Y) for general ALU operation. 6131 instruct addP_reg_imm16_CISC(iRegP dst, immL16 src, flagsReg cr) %{ 6132 match(Set dst (AddP dst src)); 6133 effect(KILL cr); 6134 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds()); 6135 ins_cost(DEFAULT_COST); 6136 // TODO: s390 port size(FIXED_SIZE); 6137 format %{ "AGHI $dst,$src\t # ptr CISC ALU" %} 6138 opcode(AGHI_ZOPC); 6139 ins_encode(z_riform_signed(dst, src)); 6140 ins_pipe(pipe_class_dummy); 6141 %} 6142 6143 // Avoid use of LA(Y) for general ALU operation. 6144 instruct addP_reg_imm16_RISC(iRegP dst, iRegP_N2P src, immL16 con, flagsReg cr) %{ 6145 match(Set dst (AddP src con)); 6146 effect(KILL cr); 6147 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds()); 6148 ins_cost(DEFAULT_COST); 6149 // TODO: s390 port size(FIXED_SIZE); 6150 format %{ "ALGHSIK $dst,$src,$con\t # ptr RISC ALU" %} 6151 opcode(ALGHSIK_ZOPC); 6152 ins_encode(z_rieform_d(dst, src, con)); 6153 ins_pipe(pipe_class_dummy); 6154 %} 6155 6156 instruct addP_reg_imm20(iRegP dst, memoryRegP src, immL20 con) %{ 6157 match(Set dst (AddP src con)); 6158 predicate(PreferLAoverADD); 6159 ins_cost(DEFAULT_COST); 6160 size(6); 6161 format %{ "LAY $dst,$con(,$src)\t # ptr d20(,b)" %} 6162 opcode(LAY_ZOPC); 6163 ins_encode(z_rxyform_imm_reg(dst, con, src)); 6164 ins_pipe(pipe_class_dummy); 6165 %} 6166 6167 // Pointer Immediate Addition 6168 instruct addP_reg_imm32(iRegP dst, immL32 src, flagsReg cr) %{ 6169 match(Set dst (AddP dst src)); 6170 effect(KILL cr); 6171 ins_cost(DEFAULT_COST_HIGH); 6172 // TODO: s390 port size(FIXED_SIZE); 6173 format %{ "AGFI $dst,$src\t # ptr" %} 6174 opcode(AGFI_ZOPC); 6175 ins_encode(z_rilform_signed(dst, src)); 6176 ins_pipe(pipe_class_dummy); 6177 %} 6178 6179 // REG = REG1 + REG2 + IMM 6180 6181 instruct addP_reg_reg_imm12(iRegP dst, memoryRegP src1, iRegL src2, uimmL12 con) %{ 6182 match(Set dst (AddP (AddP src1 src2) con)); 6183 predicate( PreferLAoverADD); 6184 ins_cost(DEFAULT_COST_LOW); 6185 size(4); 6186 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %} 6187 opcode(LA_ZOPC); 6188 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); 6189 ins_pipe(pipe_class_dummy); 6190 %} 6191 6192 instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{ 6193 match(Set dst (AddP (AddP src1 src2) con)); 6194 predicate( PreferLAoverADD && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0); 6195 ins_cost(DEFAULT_COST_LOW); 6196 size(4); 6197 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %} 6198 opcode(LA_ZOPC); 6199 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); 6200 ins_pipe(pipe_class_dummy); 6201 %} 6202 6203 instruct addP_reg_reg_imm20(iRegP dst, memoryRegP src1, iRegL src2, immL20 con) %{ 6204 match(Set dst (AddP (AddP src1 src2) con)); 6205 predicate(PreferLAoverADD); 6206 ins_cost(DEFAULT_COST); 6207 // TODO: s390 port size(FIXED_SIZE); 6208 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %} 6209 opcode(LAY_ZOPC); 6210 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); 6211 ins_pipe(pipe_class_dummy); 6212 %} 6213 6214 instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{ 6215 match(Set dst (AddP (AddP src1 src2) con)); 6216 predicate( PreferLAoverADD && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0); 6217 ins_cost(DEFAULT_COST); 6218 // TODO: s390 port size(FIXED_SIZE); 6219 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %} 6220 opcode(LAY_ZOPC); 6221 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); 6222 ins_pipe(pipe_class_dummy); 6223 %} 6224 6225 // MEM = MEM + IMM 6226 6227 // Add Immediate to 8-byte memory operand and result 6228 instruct addP_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{ 6229 match(Set mem (StoreP mem (AddP (LoadP mem) src))); 6230 effect(KILL cr); 6231 predicate(VM_Version::has_MemWithImmALUOps()); 6232 ins_cost(MEMORY_REF_COST); 6233 size(6); 6234 format %{ "AGSI $mem,$src\t # direct mem add 8 (ptr)" %} 6235 opcode(AGSI_ZOPC); 6236 ins_encode(z_siyform(mem, src)); 6237 ins_pipe(pipe_class_dummy); 6238 %} 6239 6240 // SUB 6241 6242 // Register Subtraction 6243 instruct subI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{ 6244 match(Set dst (SubI dst src)); 6245 effect(KILL cr); 6246 // TODO: s390 port size(FIXED_SIZE); 6247 format %{ "SR $dst,$src\t # int CISC ALU" %} 6248 opcode(SR_ZOPC); 6249 ins_encode(z_rrform(dst, src)); 6250 ins_pipe(pipe_class_dummy); 6251 %} 6252 6253 instruct subI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 6254 match(Set dst (SubI src1 src2)); 6255 effect(KILL cr); 6256 predicate(VM_Version::has_DistinctOpnds()); 6257 ins_cost(DEFAULT_COST); 6258 size(4); 6259 format %{ "SRK $dst,$src1,$src2\t # int RISC ALU" %} 6260 opcode(SRK_ZOPC); 6261 ins_encode(z_rrfform(dst, src1, src2)); 6262 ins_pipe(pipe_class_dummy); 6263 %} 6264 6265 instruct subI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 6266 match(Set dst (SubI dst (LoadI src))); 6267 effect(KILL cr); 6268 ins_cost(MEMORY_REF_COST); 6269 // TODO: s390 port size(VARIABLE_SIZE); 6270 format %{ "S(Y) $dst, $src\t # int" %} 6271 opcode(SY_ZOPC, S_ZOPC); 6272 ins_encode(z_form_rt_mem_opt(dst, src)); 6273 ins_pipe(pipe_class_dummy); 6274 %} 6275 6276 instruct subI_zero_reg(iRegI dst, immI_0 zero, iRegI src, flagsReg cr) %{ 6277 match(Set dst (SubI zero src)); 6278 effect(KILL cr); 6279 size(2); 6280 format %{ "NEG $dst, $src" %} 6281 ins_encode %{ __ z_lcr($dst$$Register, $src$$Register); %} 6282 ins_pipe(pipe_class_dummy); 6283 %} 6284 6285 // 6286 6287 // Long subtraction 6288 instruct subL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{ 6289 match(Set dst (SubL dst src)); 6290 effect(KILL cr); 6291 // TODO: s390 port size(FIXED_SIZE); 6292 format %{ "SGR $dst,$src\t # int CISC ALU" %} 6293 opcode(SGR_ZOPC); 6294 ins_encode(z_rreform(dst, src)); 6295 ins_pipe(pipe_class_dummy); 6296 %} 6297 6298 // Avoid use of LA(Y) for general ALU operation. 6299 instruct subL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 6300 match(Set dst (SubL src1 src2)); 6301 effect(KILL cr); 6302 predicate(VM_Version::has_DistinctOpnds()); 6303 ins_cost(DEFAULT_COST); 6304 size(4); 6305 format %{ "SGRK $dst,$src1,$src2\t # int RISC ALU" %} 6306 opcode(SGRK_ZOPC); 6307 ins_encode(z_rrfform(dst, src1, src2)); 6308 ins_pipe(pipe_class_dummy); 6309 %} 6310 6311 instruct subL_reg_regI_CISC(iRegL dst, iRegI src, flagsReg cr) %{ 6312 match(Set dst (SubL dst (ConvI2L src))); 6313 effect(KILL cr); 6314 size(4); 6315 format %{ "SGFR $dst, $src\t # int CISC ALU" %} 6316 opcode(SGFR_ZOPC); 6317 ins_encode(z_rreform(dst, src)); 6318 ins_pipe(pipe_class_dummy); 6319 %} 6320 6321 instruct subL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{ 6322 match(Set dst (SubL dst (ConvI2L (LoadI src)))); 6323 effect(KILL cr); 6324 ins_cost(MEMORY_REF_COST); 6325 size(Z_DISP3_SIZE); 6326 format %{ "SGF $dst, $src\t # long/int" %} 6327 opcode(SGF_ZOPC, SGF_ZOPC); 6328 ins_encode(z_form_rt_mem_opt(dst, src)); 6329 ins_pipe(pipe_class_dummy); 6330 %} 6331 6332 instruct subL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 6333 match(Set dst (SubL dst (LoadL src))); 6334 effect(KILL cr); 6335 ins_cost(MEMORY_REF_COST); 6336 size(Z_DISP3_SIZE); 6337 format %{ "SG $dst, $src\t # long" %} 6338 opcode(SG_ZOPC, SG_ZOPC); 6339 ins_encode(z_form_rt_mem_opt(dst, src)); 6340 ins_pipe(pipe_class_dummy); 6341 %} 6342 6343 // Moved declaration of negL_reg_reg before encode nodes, where it is used. 6344 6345 // MUL 6346 6347 // Register Multiplication 6348 instruct mulI_reg_reg(iRegI dst, iRegI src) %{ 6349 match(Set dst (MulI dst src)); 6350 ins_cost(DEFAULT_COST); 6351 size(4); 6352 format %{ "MSR $dst, $src" %} 6353 opcode(MSR_ZOPC); 6354 ins_encode(z_rreform(dst, src)); 6355 ins_pipe(pipe_class_dummy); 6356 %} 6357 6358 // Immediate Multiplication 6359 instruct mulI_reg_imm16(iRegI dst, immI16 con) %{ 6360 match(Set dst (MulI dst con)); 6361 ins_cost(DEFAULT_COST); 6362 // TODO: s390 port size(FIXED_SIZE); 6363 format %{ "MHI $dst,$con" %} 6364 opcode(MHI_ZOPC); 6365 ins_encode(z_riform_signed(dst,con)); 6366 ins_pipe(pipe_class_dummy); 6367 %} 6368 6369 // Immediate (32bit) Multiplication 6370 instruct mulI_reg_imm32(iRegI dst, immI con) %{ 6371 match(Set dst (MulI dst con)); 6372 ins_cost(DEFAULT_COST); 6373 size(6); 6374 format %{ "MSFI $dst,$con" %} 6375 opcode(MSFI_ZOPC); 6376 ins_encode(z_rilform_signed(dst,con)); 6377 ins_pipe(pipe_class_dummy); 6378 %} 6379 6380 instruct mulI_Reg_mem(iRegI dst, memory src)%{ 6381 match(Set dst (MulI dst (LoadI src))); 6382 ins_cost(MEMORY_REF_COST); 6383 // TODO: s390 port size(VARIABLE_SIZE); 6384 format %{ "MS(Y) $dst, $src\t # int" %} 6385 opcode(MSY_ZOPC, MS_ZOPC); 6386 ins_encode(z_form_rt_mem_opt(dst, src)); 6387 ins_pipe(pipe_class_dummy); 6388 %} 6389 6390 // 6391 6392 instruct mulL_reg_regI(iRegL dst, iRegI src) %{ 6393 match(Set dst (MulL dst (ConvI2L src))); 6394 ins_cost(DEFAULT_COST); 6395 // TODO: s390 port size(FIXED_SIZE); 6396 format %{ "MSGFR $dst $src\t # long/int" %} 6397 opcode(MSGFR_ZOPC); 6398 ins_encode(z_rreform(dst, src)); 6399 ins_pipe(pipe_class_dummy); 6400 %} 6401 6402 instruct mulL_reg_reg(iRegL dst, iRegL src) %{ 6403 match(Set dst (MulL dst src)); 6404 ins_cost(DEFAULT_COST); 6405 size(4); 6406 format %{ "MSGR $dst $src\t # long" %} 6407 opcode(MSGR_ZOPC); 6408 ins_encode(z_rreform(dst, src)); 6409 ins_pipe(pipe_class_dummy); 6410 %} 6411 6412 // Immediate Multiplication 6413 instruct mulL_reg_imm16(iRegL dst, immL16 src) %{ 6414 match(Set dst (MulL dst src)); 6415 ins_cost(DEFAULT_COST); 6416 // TODO: s390 port size(FIXED_SIZE); 6417 format %{ "MGHI $dst,$src\t # long" %} 6418 opcode(MGHI_ZOPC); 6419 ins_encode(z_riform_signed(dst, src)); 6420 ins_pipe(pipe_class_dummy); 6421 %} 6422 6423 // Immediate (32bit) Multiplication 6424 instruct mulL_reg_imm32(iRegL dst, immL32 con) %{ 6425 match(Set dst (MulL dst con)); 6426 ins_cost(DEFAULT_COST); 6427 size(6); 6428 format %{ "MSGFI $dst,$con" %} 6429 opcode(MSGFI_ZOPC); 6430 ins_encode(z_rilform_signed(dst,con)); 6431 ins_pipe(pipe_class_dummy); 6432 %} 6433 6434 instruct mulL_Reg_memI(iRegL dst, memory src)%{ 6435 match(Set dst (MulL dst (ConvI2L (LoadI src)))); 6436 ins_cost(MEMORY_REF_COST); 6437 size(Z_DISP3_SIZE); 6438 format %{ "MSGF $dst, $src\t # long" %} 6439 opcode(MSGF_ZOPC, MSGF_ZOPC); 6440 ins_encode(z_form_rt_mem_opt(dst, src)); 6441 ins_pipe(pipe_class_dummy); 6442 %} 6443 6444 instruct mulL_Reg_mem(iRegL dst, memory src)%{ 6445 match(Set dst (MulL dst (LoadL src))); 6446 ins_cost(MEMORY_REF_COST); 6447 size(Z_DISP3_SIZE); 6448 format %{ "MSG $dst, $src\t # long" %} 6449 opcode(MSG_ZOPC, MSG_ZOPC); 6450 ins_encode(z_form_rt_mem_opt(dst, src)); 6451 ins_pipe(pipe_class_dummy); 6452 %} 6453 6454 // DIV 6455 6456 // Integer DIVMOD with Register, both quotient and mod results 6457 instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{ 6458 match(DivModI dst1src1 src2); 6459 effect(KILL cr); 6460 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6461 size(VM_Version::has_CompareBranch() ? 24 : 26); 6462 format %{ "DIVMODI ($dst1src1, $dst2) $src2" %} 6463 ins_encode %{ 6464 Register d1s1 = $dst1src1$$Register; 6465 Register d2 = $dst2$$Register; 6466 Register s2 = $src2$$Register; 6467 6468 assert_different_registers(d1s1, s2); 6469 6470 Label do_div, done_div; 6471 if (VM_Version::has_CompareBranch()) { 6472 __ z_cij(s2, -1, Assembler::bcondNotEqual, do_div); 6473 } else { 6474 __ z_chi(s2, -1); 6475 __ z_brne(do_div); 6476 } 6477 __ z_lcr(d1s1, d1s1); 6478 __ clear_reg(d2, false, false); 6479 __ z_bru(done_div); 6480 __ bind(do_div); 6481 __ z_lgfr(d1s1, d1s1); 6482 __ z_dsgfr(d2, s2); 6483 __ bind(done_div); 6484 %} 6485 ins_pipe(pipe_class_dummy); 6486 %} 6487 6488 6489 // Register Division 6490 instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{ 6491 match(Set dst (DivI src1 src2)); 6492 effect(KILL tmp, KILL cr); 6493 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6494 size(VM_Version::has_CompareBranch() ? 20 : 22); 6495 format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %} 6496 ins_encode %{ 6497 Register a = $src1$$Register; 6498 Register b = $src2$$Register; 6499 Register t = $dst$$Register; 6500 6501 assert_different_registers(t, b); 6502 6503 Label do_div, done_div; 6504 if (VM_Version::has_CompareBranch()) { 6505 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div); 6506 } else { 6507 __ z_chi(b, -1); 6508 __ z_brne(do_div); 6509 } 6510 __ z_lcr(t, a); 6511 __ z_bru(done_div); 6512 __ bind(do_div); 6513 __ z_lgfr(t, a); 6514 __ z_dsgfr(t->predecessor()/* t is odd part of a register pair. */, b); 6515 __ bind(done_div); 6516 %} 6517 ins_pipe(pipe_class_dummy); 6518 %} 6519 6520 // Immediate Division 6521 instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, flagsReg cr) %{ 6522 match(Set dst (DivI src1 src2)); 6523 effect(KILL tmp, KILL cr); // R0 is killed, too. 6524 ins_cost(2 * DEFAULT_COST); 6525 // TODO: s390 port size(VARIABLE_SIZE); 6526 format %{ "DIV_const $dst,$src1,$src2" %} 6527 ins_encode %{ 6528 // No sign extension of Rdividend needed here. 6529 if ($src2$$constant != -1) { 6530 __ z_lghi(Z_R0_scratch, $src2$$constant); 6531 __ z_lgfr($dst$$Register, $src1$$Register); 6532 __ z_dsgfr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch); 6533 } else { 6534 __ z_lcr($dst$$Register, $src1$$Register); 6535 } 6536 %} 6537 ins_pipe(pipe_class_dummy); 6538 %} 6539 6540 // Long DIVMOD with Register, both quotient and mod results 6541 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{ 6542 match(DivModL dst1src1 src2); 6543 effect(KILL cr); 6544 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6545 size(VM_Version::has_CompareBranch() ? 22 : 24); 6546 format %{ "DIVMODL ($dst1src1, $dst2) $src2" %} 6547 ins_encode %{ 6548 Register d1s1 = $dst1src1$$Register; 6549 Register d2 = $dst2$$Register; 6550 Register s2 = $src2$$Register; 6551 6552 Label do_div, done_div; 6553 if (VM_Version::has_CompareBranch()) { 6554 __ z_cgij(s2, -1, Assembler::bcondNotEqual, do_div); 6555 } else { 6556 __ z_cghi(s2, -1); 6557 __ z_brne(do_div); 6558 } 6559 __ z_lcgr(d1s1, d1s1); 6560 // indicate unused result 6561 (void) __ clear_reg(d2, true, false); 6562 __ z_bru(done_div); 6563 __ bind(do_div); 6564 __ z_dsgr(d2, s2); 6565 __ bind(done_div); 6566 %} 6567 ins_pipe(pipe_class_dummy); 6568 %} 6569 6570 // Register Long Division 6571 instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{ 6572 match(Set dst (DivL dst src)); 6573 effect(KILL tmp, KILL cr); 6574 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6575 size(VM_Version::has_CompareBranch() ? 18 : 20); 6576 format %{ "DIVG_checked $dst, $src\t # long, treats special case 0x80../-1" %} 6577 ins_encode %{ 6578 Register b = $src$$Register; 6579 Register t = $dst$$Register; 6580 6581 Label done_div; 6582 __ z_lcgr(t, t); // Does no harm. divisor is in other register. 6583 if (VM_Version::has_CompareBranch()) { 6584 __ z_cgij(b, -1, Assembler::bcondEqual, done_div); 6585 } else { 6586 __ z_cghi(b, -1); 6587 __ z_bre(done_div); 6588 } 6589 __ z_lcgr(t, t); // Restore sign. 6590 __ z_dsgr(t->predecessor()/* t is odd part of a register pair. */, b); 6591 __ bind(done_div); 6592 %} 6593 ins_pipe(pipe_class_dummy); 6594 %} 6595 6596 // Immediate Long Division 6597 instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{ 6598 match(Set dst (DivL src1 src2)); 6599 effect(KILL tmp, KILL cr); // R0 is killed, too. 6600 ins_cost(2 * DEFAULT_COST); 6601 // TODO: s390 port size(VARIABLE_SIZE); 6602 format %{ "DIVG_const $dst,$src1,$src2\t # long" %} 6603 ins_encode %{ 6604 if ($src2$$constant != -1) { 6605 __ z_lghi(Z_R0_scratch, $src2$$constant); 6606 __ lgr_if_needed($dst$$Register, $src1$$Register); 6607 __ z_dsgr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch); 6608 } else { 6609 __ z_lcgr($dst$$Register, $src1$$Register); 6610 } 6611 %} 6612 ins_pipe(pipe_class_dummy); 6613 %} 6614 6615 // REM 6616 6617 // Integer Remainder 6618 // Register Remainder 6619 instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp, flagsReg cr) %{ 6620 match(Set dst (ModI src1 src2)); 6621 effect(KILL tmp, KILL cr); 6622 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6623 // TODO: s390 port size(VARIABLE_SIZE); 6624 format %{ "MOD_checked $dst,$src1,$src2" %} 6625 ins_encode %{ 6626 Register a = $src1$$Register; 6627 Register b = $src2$$Register; 6628 Register t = $dst$$Register; 6629 assert_different_registers(t->successor(), b); 6630 6631 Label do_div, done_div; 6632 6633 if ((t->encoding() != b->encoding()) && (t->encoding() != a->encoding())) { 6634 (void) __ clear_reg(t, true, false); // Does no harm. Operands are in other regs. 6635 if (VM_Version::has_CompareBranch()) { 6636 __ z_cij(b, -1, Assembler::bcondEqual, done_div); 6637 } else { 6638 __ z_chi(b, -1); 6639 __ z_bre(done_div); 6640 } 6641 __ z_lgfr(t->successor(), a); 6642 __ z_dsgfr(t/* t is even part of a register pair. */, b); 6643 } else { 6644 if (VM_Version::has_CompareBranch()) { 6645 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div); 6646 } else { 6647 __ z_chi(b, -1); 6648 __ z_brne(do_div); 6649 } 6650 __ clear_reg(t, true, false); 6651 __ z_bru(done_div); 6652 __ bind(do_div); 6653 __ z_lgfr(t->successor(), a); 6654 __ z_dsgfr(t/* t is even part of a register pair. */, b); 6655 } 6656 __ bind(done_div); 6657 %} 6658 ins_pipe(pipe_class_dummy); 6659 %} 6660 6661 // Immediate Remainder 6662 instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{ 6663 match(Set dst (ModI src1 src2)); 6664 effect(KILL tmp, KILL cr); // R0 is killed, too. 6665 ins_cost(3 * DEFAULT_COST); 6666 // TODO: s390 port size(VARIABLE_SIZE); 6667 format %{ "MOD_const $dst,src1,$src2" %} 6668 ins_encode %{ 6669 assert_different_registers($dst$$Register, $src1$$Register); 6670 assert_different_registers($dst$$Register->successor(), $src1$$Register); 6671 int divisor = $src2$$constant; 6672 6673 if (divisor != -1) { 6674 __ z_lghi(Z_R0_scratch, divisor); 6675 __ z_lgfr($dst$$Register->successor(), $src1$$Register); 6676 __ z_dsgfr($dst$$Register/* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp. 6677 } else { 6678 __ clear_reg($dst$$Register, true, false); 6679 } 6680 %} 6681 ins_pipe(pipe_class_dummy); 6682 %} 6683 6684 // Register Long Remainder 6685 instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{ 6686 match(Set dst (ModL src1 src2)); 6687 effect(KILL src1, KILL cr); // R0 is killed, too. 6688 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6689 // TODO: s390 port size(VARIABLE_SIZE); 6690 format %{ "MODG_checked $dst,$src1,$src2" %} 6691 ins_encode %{ 6692 Register a = $src1$$Register; 6693 Register b = $src2$$Register; 6694 Register t = $dst$$Register; 6695 assert(t->successor() == a, "(t,a) is an even-odd pair" ); 6696 6697 Label do_div, done_div; 6698 if (t->encoding() != b->encoding()) { 6699 (void) __ clear_reg(t, true, false); // Does no harm. Dividend is in successor. 6700 if (VM_Version::has_CompareBranch()) { 6701 __ z_cgij(b, -1, Assembler::bcondEqual, done_div); 6702 } else { 6703 __ z_cghi(b, -1); 6704 __ z_bre(done_div); 6705 } 6706 __ z_dsgr(t, b); 6707 } else { 6708 if (VM_Version::has_CompareBranch()) { 6709 __ z_cgij(b, -1, Assembler::bcondNotEqual, do_div); 6710 } else { 6711 __ z_cghi(b, -1); 6712 __ z_brne(do_div); 6713 } 6714 __ clear_reg(t, true, false); 6715 __ z_bru(done_div); 6716 __ bind(do_div); 6717 __ z_dsgr(t, b); 6718 } 6719 __ bind(done_div); 6720 %} 6721 ins_pipe(pipe_class_dummy); 6722 %} 6723 6724 // Register Long Remainder 6725 instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{ 6726 match(Set dst (ModL src1 src2)); 6727 effect(KILL tmp, KILL cr); // R0 is killed, too. 6728 ins_cost(3 * DEFAULT_COST); 6729 // TODO: s390 port size(VARIABLE_SIZE); 6730 format %{ "MODG_const $dst,src1,$src2\t # long" %} 6731 ins_encode %{ 6732 int divisor = $src2$$constant; 6733 if (divisor != -1) { 6734 __ z_lghi(Z_R0_scratch, divisor); 6735 __ z_lgr($dst$$Register->successor(), $src1$$Register); 6736 __ z_dsgr($dst$$Register /* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp. 6737 } else { 6738 __ clear_reg($dst$$Register, true, false); 6739 } 6740 %} 6741 ins_pipe(pipe_class_dummy); 6742 %} 6743 6744 // SHIFT 6745 6746 // Shift left logical 6747 6748 // Register Shift Left variable 6749 instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{ 6750 match(Set dst (LShiftI src nbits)); 6751 effect(KILL cr); // R1 is killed, too. 6752 ins_cost(3 * DEFAULT_COST); 6753 size(14); 6754 format %{ "SLL $dst,$src,[$nbits] & 31\t# use RISC-like SLLG also for int" %} 6755 ins_encode %{ 6756 __ z_lgr(Z_R1_scratch, $nbits$$Register); 6757 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); 6758 __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch); 6759 %} 6760 ins_pipe(pipe_class_dummy); 6761 %} 6762 6763 // Register Shift Left Immediate 6764 // Constant shift count is masked in ideal graph already. 6765 instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{ 6766 match(Set dst (LShiftI src nbits)); 6767 size(6); 6768 format %{ "SLL $dst,$src,$nbits\t# use RISC-like SLLG also for int" %} 6769 ins_encode %{ 6770 int Nbit = $nbits$$constant; 6771 __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); 6772 %} 6773 ins_pipe(pipe_class_dummy); 6774 %} 6775 6776 // Register Shift Left Immediate by 1bit 6777 instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{ 6778 match(Set dst (LShiftI src nbits)); 6779 predicate(PreferLAoverADD); 6780 ins_cost(DEFAULT_COST_LOW); 6781 size(4); 6782 format %{ "LA $dst,#0($src,$src)\t # SLL by 1 (int)" %} 6783 ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %} 6784 ins_pipe(pipe_class_dummy); 6785 %} 6786 6787 // Register Shift Left Long 6788 instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{ 6789 match(Set dst (LShiftL src1 nbits)); 6790 size(6); 6791 format %{ "SLLG $dst,$src1,[$nbits]" %} 6792 opcode(SLLG_ZOPC); 6793 ins_encode(z_rsyform_reg_reg(dst, src1, nbits)); 6794 ins_pipe(pipe_class_dummy); 6795 %} 6796 6797 // Register Shift Left Long Immediate 6798 instruct sllL_reg_imm(iRegL dst, iRegL src1, immI nbits) %{ 6799 match(Set dst (LShiftL src1 nbits)); 6800 size(6); 6801 format %{ "SLLG $dst,$src1,$nbits" %} 6802 opcode(SLLG_ZOPC); 6803 ins_encode(z_rsyform_const(dst, src1, nbits)); 6804 ins_pipe(pipe_class_dummy); 6805 %} 6806 6807 // Register Shift Left Long Immediate by 1bit 6808 instruct sllL_reg_imm_1(iRegL dst, iRegL src1, immI_1 nbits) %{ 6809 match(Set dst (LShiftL src1 nbits)); 6810 predicate(PreferLAoverADD); 6811 ins_cost(DEFAULT_COST_LOW); 6812 size(4); 6813 format %{ "LA $dst,#0($src1,$src1)\t # SLLG by 1 (long)" %} 6814 ins_encode %{ __ z_la($dst$$Register, 0, $src1$$Register, $src1$$Register); %} 6815 ins_pipe(pipe_class_dummy); 6816 %} 6817 6818 // Shift right arithmetic 6819 6820 // Register Arithmetic Shift Right 6821 instruct sraI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 6822 match(Set dst (RShiftI dst src)); 6823 effect(KILL cr); // R1 is killed, too. 6824 ins_cost(3 * DEFAULT_COST); 6825 size(12); 6826 format %{ "SRA $dst,[$src] & 31" %} 6827 ins_encode %{ 6828 __ z_lgr(Z_R1_scratch, $src$$Register); 6829 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); 6830 __ z_sra($dst$$Register, 0, Z_R1_scratch); 6831 %} 6832 ins_pipe(pipe_class_dummy); 6833 %} 6834 6835 // Register Arithmetic Shift Right Immediate 6836 // Constant shift count is masked in ideal graph already. 6837 instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{ 6838 match(Set dst (RShiftI dst src)); 6839 effect(KILL cr); 6840 size(4); 6841 format %{ "SRA $dst,$src" %} 6842 ins_encode %{ 6843 int Nbit = $src$$constant; 6844 __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); 6845 %} 6846 ins_pipe(pipe_class_dummy); 6847 %} 6848 6849 // Register Arithmetic Shift Right Long 6850 instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{ 6851 match(Set dst (RShiftL src1 src2)); 6852 effect(KILL cr); 6853 size(6); 6854 format %{ "SRAG $dst,$src1,[$src2]" %} 6855 opcode(SRAG_ZOPC); 6856 ins_encode(z_rsyform_reg_reg(dst, src1, src2)); 6857 ins_pipe(pipe_class_dummy); 6858 %} 6859 6860 // Register Arithmetic Shift Right Long Immediate 6861 instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{ 6862 match(Set dst (RShiftL src1 src2)); 6863 effect(KILL cr); 6864 size(6); 6865 format %{ "SRAG $dst,$src1,$src2" %} 6866 opcode(SRAG_ZOPC); 6867 ins_encode(z_rsyform_const(dst, src1, src2)); 6868 ins_pipe(pipe_class_dummy); 6869 %} 6870 6871 // Shift right logical 6872 6873 // Register Shift Right 6874 instruct srlI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 6875 match(Set dst (URShiftI dst src)); 6876 effect(KILL cr); // R1 is killed, too. 6877 ins_cost(3 * DEFAULT_COST); 6878 size(12); 6879 format %{ "SRL $dst,[$src] & 31" %} 6880 ins_encode %{ 6881 __ z_lgr(Z_R1_scratch, $src$$Register); 6882 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); 6883 __ z_srl($dst$$Register, 0, Z_R1_scratch); 6884 %} 6885 ins_pipe(pipe_class_dummy); 6886 %} 6887 6888 // Register Shift Right Immediate 6889 // Constant shift count is masked in ideal graph already. 6890 instruct srlI_reg_imm(iRegI dst, immI src) %{ 6891 match(Set dst (URShiftI dst src)); 6892 size(4); 6893 format %{ "SRL $dst,$src" %} 6894 ins_encode %{ 6895 int Nbit = $src$$constant; 6896 __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); 6897 %} 6898 ins_pipe(pipe_class_dummy); 6899 %} 6900 6901 // Register Shift Right Long 6902 instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 6903 match(Set dst (URShiftL src1 src2)); 6904 size(6); 6905 format %{ "SRLG $dst,$src1,[$src2]" %} 6906 opcode(SRLG_ZOPC); 6907 ins_encode(z_rsyform_reg_reg(dst, src1, src2)); 6908 ins_pipe(pipe_class_dummy); 6909 %} 6910 6911 // Register Shift Right Long Immediate 6912 instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{ 6913 match(Set dst (URShiftL src1 src2)); 6914 size(6); 6915 format %{ "SRLG $dst,$src1,$src2" %} 6916 opcode(SRLG_ZOPC); 6917 ins_encode(z_rsyform_const(dst, src1, src2)); 6918 ins_pipe(pipe_class_dummy); 6919 %} 6920 6921 // Register Shift Right Immediate with a CastP2X 6922 instruct srlP_reg_imm(iRegL dst, iRegP_N2P src1, immI src2) %{ 6923 match(Set dst (URShiftL (CastP2X src1) src2)); 6924 size(6); 6925 format %{ "SRLG $dst,$src1,$src2\t # Cast ptr $src1 to long and shift" %} 6926 opcode(SRLG_ZOPC); 6927 ins_encode(z_rsyform_const(dst, src1, src2)); 6928 ins_pipe(pipe_class_dummy); 6929 %} 6930 6931 //----------Rotate Instructions------------------------------------------------ 6932 6933 // Rotate left 32bit. 6934 instruct rotlI_reg_immI8(iRegI dst, iRegI src, immI8 lshift, immI8 rshift) %{ 6935 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift))); 6936 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 6937 size(6); 6938 format %{ "RLL $dst,$src,$lshift\t # ROTL32" %} 6939 opcode(RLL_ZOPC); 6940 ins_encode(z_rsyform_const(dst, src, lshift)); 6941 ins_pipe(pipe_class_dummy); 6942 %} 6943 6944 // Rotate left 64bit. 6945 instruct rotlL_reg_immI8(iRegL dst, iRegL src, immI8 lshift, immI8 rshift) %{ 6946 match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift))); 6947 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); 6948 size(6); 6949 format %{ "RLLG $dst,$src,$lshift\t # ROTL64" %} 6950 opcode(RLLG_ZOPC); 6951 ins_encode(z_rsyform_const(dst, src, lshift)); 6952 ins_pipe(pipe_class_dummy); 6953 %} 6954 6955 // Rotate right 32bit. 6956 instruct rotrI_reg_immI8(iRegI dst, iRegI src, immI8 rshift, immI8 lshift) %{ 6957 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift))); 6958 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 6959 // TODO: s390 port size(FIXED_SIZE); 6960 format %{ "RLL $dst,$src,$rshift\t # ROTR32" %} 6961 opcode(RLL_ZOPC); 6962 ins_encode(z_rsyform_const(dst, src, rshift)); 6963 ins_pipe(pipe_class_dummy); 6964 %} 6965 6966 // Rotate right 64bit. 6967 instruct rotrL_reg_immI8(iRegL dst, iRegL src, immI8 rshift, immI8 lshift) %{ 6968 match(Set dst (OrL (URShiftL src rshift) (LShiftL src lshift))); 6969 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); 6970 // TODO: s390 port size(FIXED_SIZE); 6971 format %{ "RLLG $dst,$src,$rshift\t # ROTR64" %} 6972 opcode(RLLG_ZOPC); 6973 ins_encode(z_rsyform_const(dst, src, rshift)); 6974 ins_pipe(pipe_class_dummy); 6975 %} 6976 6977 6978 //----------Overflow Math Instructions----------------------------------------- 6979 6980 instruct overflowAddI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{ 6981 match(Set cr (OverflowAddI op1 op2)); 6982 effect(DEF cr, USE op1, USE op2); 6983 // TODO: s390 port size(FIXED_SIZE); 6984 format %{ "AR $op1,$op2\t # overflow check int" %} 6985 ins_encode %{ 6986 __ z_lr(Z_R0_scratch, $op1$$Register); 6987 __ z_ar(Z_R0_scratch, $op2$$Register); 6988 %} 6989 ins_pipe(pipe_class_dummy); 6990 %} 6991 6992 instruct overflowAddI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{ 6993 match(Set cr (OverflowAddI op1 op2)); 6994 effect(DEF cr, USE op1, USE op2); 6995 // TODO: s390 port size(VARIABLE_SIZE); 6996 format %{ "AR $op1,$op2\t # overflow check int" %} 6997 ins_encode %{ 6998 __ load_const_optimized(Z_R0_scratch, $op2$$constant); 6999 __ z_ar(Z_R0_scratch, $op1$$Register); 7000 %} 7001 ins_pipe(pipe_class_dummy); 7002 %} 7003 7004 instruct overflowAddL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{ 7005 match(Set cr (OverflowAddL op1 op2)); 7006 effect(DEF cr, USE op1, USE op2); 7007 // TODO: s390 port size(FIXED_SIZE); 7008 format %{ "AGR $op1,$op2\t # overflow check long" %} 7009 ins_encode %{ 7010 __ z_lgr(Z_R0_scratch, $op1$$Register); 7011 __ z_agr(Z_R0_scratch, $op2$$Register); 7012 %} 7013 ins_pipe(pipe_class_dummy); 7014 %} 7015 7016 instruct overflowAddL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{ 7017 match(Set cr (OverflowAddL op1 op2)); 7018 effect(DEF cr, USE op1, USE op2); 7019 // TODO: s390 port size(VARIABLE_SIZE); 7020 format %{ "AGR $op1,$op2\t # overflow check long" %} 7021 ins_encode %{ 7022 __ load_const_optimized(Z_R0_scratch, $op2$$constant); 7023 __ z_agr(Z_R0_scratch, $op1$$Register); 7024 %} 7025 ins_pipe(pipe_class_dummy); 7026 %} 7027 7028 instruct overflowSubI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{ 7029 match(Set cr (OverflowSubI op1 op2)); 7030 effect(DEF cr, USE op1, USE op2); 7031 // TODO: s390 port size(FIXED_SIZE); 7032 format %{ "SR $op1,$op2\t # overflow check int" %} 7033 ins_encode %{ 7034 __ z_lr(Z_R0_scratch, $op1$$Register); 7035 __ z_sr(Z_R0_scratch, $op2$$Register); 7036 %} 7037 ins_pipe(pipe_class_dummy); 7038 %} 7039 7040 instruct overflowSubI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{ 7041 match(Set cr (OverflowSubI op1 op2)); 7042 effect(DEF cr, USE op1, USE op2); 7043 // TODO: s390 port size(VARIABLE_SIZE); 7044 format %{ "SR $op1,$op2\t # overflow check int" %} 7045 ins_encode %{ 7046 __ load_const_optimized(Z_R1_scratch, $op2$$constant); 7047 __ z_lr(Z_R0_scratch, $op1$$Register); 7048 __ z_sr(Z_R0_scratch, Z_R1_scratch); 7049 %} 7050 ins_pipe(pipe_class_dummy); 7051 %} 7052 7053 instruct overflowSubL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{ 7054 match(Set cr (OverflowSubL op1 op2)); 7055 effect(DEF cr, USE op1, USE op2); 7056 // TODO: s390 port size(FIXED_SIZE); 7057 format %{ "SGR $op1,$op2\t # overflow check long" %} 7058 ins_encode %{ 7059 __ z_lgr(Z_R0_scratch, $op1$$Register); 7060 __ z_sgr(Z_R0_scratch, $op2$$Register); 7061 %} 7062 ins_pipe(pipe_class_dummy); 7063 %} 7064 7065 instruct overflowSubL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{ 7066 match(Set cr (OverflowSubL op1 op2)); 7067 effect(DEF cr, USE op1, USE op2); 7068 // TODO: s390 port size(VARIABLE_SIZE); 7069 format %{ "SGR $op1,$op2\t # overflow check long" %} 7070 ins_encode %{ 7071 __ load_const_optimized(Z_R1_scratch, $op2$$constant); 7072 __ z_lgr(Z_R0_scratch, $op1$$Register); 7073 __ z_sgr(Z_R0_scratch, Z_R1_scratch); 7074 %} 7075 ins_pipe(pipe_class_dummy); 7076 %} 7077 7078 instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{ 7079 match(Set cr (OverflowSubI zero op2)); 7080 effect(DEF cr, USE op2); 7081 format %{ "NEG $op2\t# overflow check int" %} 7082 ins_encode %{ 7083 __ clear_reg(Z_R0_scratch, false, false); 7084 __ z_sr(Z_R0_scratch, $op2$$Register); 7085 %} 7086 ins_pipe(pipe_class_dummy); 7087 %} 7088 7089 instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{ 7090 match(Set cr (OverflowSubL zero op2)); 7091 effect(DEF cr, USE op2); 7092 format %{ "NEGG $op2\t# overflow check long" %} 7093 ins_encode %{ 7094 __ clear_reg(Z_R0_scratch, true, false); 7095 __ z_sgr(Z_R0_scratch, $op2$$Register); 7096 %} 7097 ins_pipe(pipe_class_dummy); 7098 %} 7099 7100 // No intrinsics for multiplication, since there is no easy way 7101 // to check for overflow. 7102 7103 7104 //----------Floating Point Arithmetic Instructions----------------------------- 7105 7106 // ADD 7107 7108 // Add float single precision 7109 instruct addF_reg_reg(regF dst, regF src, flagsReg cr) %{ 7110 match(Set dst (AddF dst src)); 7111 effect(KILL cr); 7112 ins_cost(ALU_REG_COST); 7113 size(4); 7114 format %{ "AEBR $dst,$src" %} 7115 opcode(AEBR_ZOPC); 7116 ins_encode(z_rreform(dst, src)); 7117 ins_pipe(pipe_class_dummy); 7118 %} 7119 7120 instruct addF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{ 7121 match(Set dst (AddF dst (LoadF src))); 7122 effect(KILL cr); 7123 ins_cost(ALU_MEMORY_COST); 7124 size(6); 7125 format %{ "AEB $dst,$src\t # floatMemory" %} 7126 opcode(AEB_ZOPC); 7127 ins_encode(z_form_rt_memFP(dst, src)); 7128 ins_pipe(pipe_class_dummy); 7129 %} 7130 7131 // Add float double precision 7132 instruct addD_reg_reg(regD dst, regD src, flagsReg cr) %{ 7133 match(Set dst (AddD dst src)); 7134 effect(KILL cr); 7135 ins_cost(ALU_REG_COST); 7136 size(4); 7137 format %{ "ADBR $dst,$src" %} 7138 opcode(ADBR_ZOPC); 7139 ins_encode(z_rreform(dst, src)); 7140 ins_pipe(pipe_class_dummy); 7141 %} 7142 7143 instruct addD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{ 7144 match(Set dst (AddD dst (LoadD src))); 7145 effect(KILL cr); 7146 ins_cost(ALU_MEMORY_COST); 7147 size(6); 7148 format %{ "ADB $dst,$src\t # doubleMemory" %} 7149 opcode(ADB_ZOPC); 7150 ins_encode(z_form_rt_memFP(dst, src)); 7151 ins_pipe(pipe_class_dummy); 7152 %} 7153 7154 // SUB 7155 7156 // Sub float single precision 7157 instruct subF_reg_reg(regF dst, regF src, flagsReg cr) %{ 7158 match(Set dst (SubF dst src)); 7159 effect(KILL cr); 7160 ins_cost(ALU_REG_COST); 7161 size(4); 7162 format %{ "SEBR $dst,$src" %} 7163 opcode(SEBR_ZOPC); 7164 ins_encode(z_rreform(dst, src)); 7165 ins_pipe(pipe_class_dummy); 7166 %} 7167 7168 instruct subF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{ 7169 match(Set dst (SubF dst (LoadF src))); 7170 effect(KILL cr); 7171 ins_cost(ALU_MEMORY_COST); 7172 size(6); 7173 format %{ "SEB $dst,$src\t # floatMemory" %} 7174 opcode(SEB_ZOPC); 7175 ins_encode(z_form_rt_memFP(dst, src)); 7176 ins_pipe(pipe_class_dummy); 7177 %} 7178 7179 // Sub float double precision 7180 instruct subD_reg_reg(regD dst, regD src, flagsReg cr) %{ 7181 match(Set dst (SubD dst src)); 7182 effect(KILL cr); 7183 ins_cost(ALU_REG_COST); 7184 size(4); 7185 format %{ "SDBR $dst,$src" %} 7186 opcode(SDBR_ZOPC); 7187 ins_encode(z_rreform(dst, src)); 7188 ins_pipe(pipe_class_dummy); 7189 %} 7190 7191 instruct subD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{ 7192 match(Set dst (SubD dst (LoadD src))); 7193 effect(KILL cr); 7194 ins_cost(ALU_MEMORY_COST); 7195 size(6); 7196 format %{ "SDB $dst,$src\t # doubleMemory" %} 7197 opcode(SDB_ZOPC); 7198 ins_encode(z_form_rt_memFP(dst, src)); 7199 ins_pipe(pipe_class_dummy); 7200 %} 7201 7202 // MUL 7203 7204 // Mul float single precision 7205 instruct mulF_reg_reg(regF dst, regF src) %{ 7206 match(Set dst (MulF dst src)); 7207 // CC unchanged by MUL. 7208 ins_cost(ALU_REG_COST); 7209 size(4); 7210 format %{ "MEEBR $dst,$src" %} 7211 opcode(MEEBR_ZOPC); 7212 ins_encode(z_rreform(dst, src)); 7213 ins_pipe(pipe_class_dummy); 7214 %} 7215 7216 instruct mulF_reg_mem(regF dst, memoryRX src)%{ 7217 match(Set dst (MulF dst (LoadF src))); 7218 // CC unchanged by MUL. 7219 ins_cost(ALU_MEMORY_COST); 7220 size(6); 7221 format %{ "MEEB $dst,$src\t # floatMemory" %} 7222 opcode(MEEB_ZOPC); 7223 ins_encode(z_form_rt_memFP(dst, src)); 7224 ins_pipe(pipe_class_dummy); 7225 %} 7226 7227 // Mul float double precision 7228 instruct mulD_reg_reg(regD dst, regD src) %{ 7229 match(Set dst (MulD dst src)); 7230 // CC unchanged by MUL. 7231 ins_cost(ALU_REG_COST); 7232 size(4); 7233 format %{ "MDBR $dst,$src" %} 7234 opcode(MDBR_ZOPC); 7235 ins_encode(z_rreform(dst, src)); 7236 ins_pipe(pipe_class_dummy); 7237 %} 7238 7239 instruct mulD_reg_mem(regD dst, memoryRX src)%{ 7240 match(Set dst (MulD dst (LoadD src))); 7241 // CC unchanged by MUL. 7242 ins_cost(ALU_MEMORY_COST); 7243 size(6); 7244 format %{ "MDB $dst,$src\t # doubleMemory" %} 7245 opcode(MDB_ZOPC); 7246 ins_encode(z_form_rt_memFP(dst, src)); 7247 ins_pipe(pipe_class_dummy); 7248 %} 7249 7250 // Multiply-Accumulate 7251 // src1 * src2 + dst 7252 instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{ 7253 match(Set dst (FmaF dst (Binary src1 src2))); 7254 // CC unchanged by MUL-ADD. 7255 ins_cost(ALU_REG_COST); 7256 size(4); 7257 format %{ "MAEBR $dst, $src1, $src2" %} 7258 ins_encode %{ 7259 __ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 7260 %} 7261 ins_pipe(pipe_class_dummy); 7262 %} 7263 7264 // src1 * src2 + dst 7265 instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{ 7266 match(Set dst (FmaD dst (Binary src1 src2))); 7267 // CC unchanged by MUL-ADD. 7268 ins_cost(ALU_REG_COST); 7269 size(4); 7270 format %{ "MADBR $dst, $src1, $src2" %} 7271 ins_encode %{ 7272 __ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 7273 %} 7274 ins_pipe(pipe_class_dummy); 7275 %} 7276 7277 // src1 * src2 - dst 7278 instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{ 7279 match(Set dst (FmaF (NegF dst) (Binary src1 src2))); 7280 // CC unchanged by MUL-SUB. 7281 ins_cost(ALU_REG_COST); 7282 size(4); 7283 format %{ "MSEBR $dst, $src1, $src2" %} 7284 ins_encode %{ 7285 __ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 7286 %} 7287 ins_pipe(pipe_class_dummy); 7288 %} 7289 7290 // src1 * src2 - dst 7291 instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{ 7292 match(Set dst (FmaD (NegD dst) (Binary src1 src2))); 7293 // CC unchanged by MUL-SUB. 7294 ins_cost(ALU_REG_COST); 7295 size(4); 7296 format %{ "MSDBR $dst, $src1, $src2" %} 7297 ins_encode %{ 7298 __ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 7299 %} 7300 ins_pipe(pipe_class_dummy); 7301 %} 7302 7303 // src1 * src2 + dst 7304 instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{ 7305 match(Set dst (FmaF dst (Binary src1 (LoadF src2)))); 7306 // CC unchanged by MUL-ADD. 7307 ins_cost(ALU_MEMORY_COST); 7308 size(6); 7309 format %{ "MAEB $dst, $src1, $src2" %} 7310 ins_encode %{ 7311 __ z_maeb($dst$$FloatRegister, $src1$$FloatRegister, 7312 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); 7313 %} 7314 ins_pipe(pipe_class_dummy); 7315 %} 7316 7317 // src1 * src2 + dst 7318 instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{ 7319 match(Set dst (FmaD dst (Binary src1 (LoadD src2)))); 7320 // CC unchanged by MUL-ADD. 7321 ins_cost(ALU_MEMORY_COST); 7322 size(6); 7323 format %{ "MADB $dst, $src1, $src2" %} 7324 ins_encode %{ 7325 __ z_madb($dst$$FloatRegister, $src1$$FloatRegister, 7326 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); 7327 %} 7328 ins_pipe(pipe_class_dummy); 7329 %} 7330 7331 // src1 * src2 - dst 7332 instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{ 7333 match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2)))); 7334 // CC unchanged by MUL-SUB. 7335 ins_cost(ALU_MEMORY_COST); 7336 size(6); 7337 format %{ "MSEB $dst, $src1, $src2" %} 7338 ins_encode %{ 7339 __ z_mseb($dst$$FloatRegister, $src1$$FloatRegister, 7340 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); 7341 %} 7342 ins_pipe(pipe_class_dummy); 7343 %} 7344 7345 // src1 * src2 - dst 7346 instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{ 7347 match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2)))); 7348 // CC unchanged by MUL-SUB. 7349 ins_cost(ALU_MEMORY_COST); 7350 size(6); 7351 format %{ "MSDB $dst, $src1, $src2" %} 7352 ins_encode %{ 7353 __ z_msdb($dst$$FloatRegister, $src1$$FloatRegister, 7354 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); 7355 %} 7356 ins_pipe(pipe_class_dummy); 7357 %} 7358 7359 // src1 * src2 + dst 7360 instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{ 7361 match(Set dst (FmaF dst (Binary (LoadF src1) src2))); 7362 // CC unchanged by MUL-ADD. 7363 ins_cost(ALU_MEMORY_COST); 7364 size(6); 7365 format %{ "MAEB $dst, $src1, $src2" %} 7366 ins_encode %{ 7367 __ z_maeb($dst$$FloatRegister, $src2$$FloatRegister, 7368 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); 7369 %} 7370 ins_pipe(pipe_class_dummy); 7371 %} 7372 7373 // src1 * src2 + dst 7374 instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{ 7375 match(Set dst (FmaD dst (Binary (LoadD src1) src2))); 7376 // CC unchanged by MUL-ADD. 7377 ins_cost(ALU_MEMORY_COST); 7378 size(6); 7379 format %{ "MADB $dst, $src1, $src2" %} 7380 ins_encode %{ 7381 __ z_madb($dst$$FloatRegister, $src2$$FloatRegister, 7382 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); 7383 %} 7384 ins_pipe(pipe_class_dummy); 7385 %} 7386 7387 // src1 * src2 - dst 7388 instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{ 7389 match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2))); 7390 // CC unchanged by MUL-SUB. 7391 ins_cost(ALU_MEMORY_COST); 7392 size(6); 7393 format %{ "MSEB $dst, $src1, $src2" %} 7394 ins_encode %{ 7395 __ z_mseb($dst$$FloatRegister, $src2$$FloatRegister, 7396 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); 7397 %} 7398 ins_pipe(pipe_class_dummy); 7399 %} 7400 7401 // src1 * src2 - dst 7402 instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{ 7403 match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2))); 7404 // CC unchanged by MUL-SUB. 7405 ins_cost(ALU_MEMORY_COST); 7406 size(6); 7407 format %{ "MSDB $dst, $src1, $src2" %} 7408 ins_encode %{ 7409 __ z_msdb($dst$$FloatRegister, $src2$$FloatRegister, 7410 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); 7411 %} 7412 ins_pipe(pipe_class_dummy); 7413 %} 7414 7415 // DIV 7416 7417 // Div float single precision 7418 instruct divF_reg_reg(regF dst, regF src) %{ 7419 match(Set dst (DivF dst src)); 7420 // CC unchanged by DIV. 7421 ins_cost(ALU_REG_COST); 7422 size(4); 7423 format %{ "DEBR $dst,$src" %} 7424 opcode(DEBR_ZOPC); 7425 ins_encode(z_rreform(dst, src)); 7426 ins_pipe(pipe_class_dummy); 7427 %} 7428 7429 instruct divF_reg_mem(regF dst, memoryRX src)%{ 7430 match(Set dst (DivF dst (LoadF src))); 7431 // CC unchanged by DIV. 7432 ins_cost(ALU_MEMORY_COST); 7433 size(6); 7434 format %{ "DEB $dst,$src\t # floatMemory" %} 7435 opcode(DEB_ZOPC); 7436 ins_encode(z_form_rt_memFP(dst, src)); 7437 ins_pipe(pipe_class_dummy); 7438 %} 7439 7440 // Div float double precision 7441 instruct divD_reg_reg(regD dst, regD src) %{ 7442 match(Set dst (DivD dst src)); 7443 // CC unchanged by DIV. 7444 ins_cost(ALU_REG_COST); 7445 size(4); 7446 format %{ "DDBR $dst,$src" %} 7447 opcode(DDBR_ZOPC); 7448 ins_encode(z_rreform(dst, src)); 7449 ins_pipe(pipe_class_dummy); 7450 %} 7451 7452 instruct divD_reg_mem(regD dst, memoryRX src)%{ 7453 match(Set dst (DivD dst (LoadD src))); 7454 // CC unchanged by DIV. 7455 ins_cost(ALU_MEMORY_COST); 7456 size(6); 7457 format %{ "DDB $dst,$src\t # doubleMemory" %} 7458 opcode(DDB_ZOPC); 7459 ins_encode(z_form_rt_memFP(dst, src)); 7460 ins_pipe(pipe_class_dummy); 7461 %} 7462 7463 // ABS 7464 7465 // Absolute float single precision 7466 instruct absF_reg(regF dst, regF src, flagsReg cr) %{ 7467 match(Set dst (AbsF src)); 7468 effect(KILL cr); 7469 size(4); 7470 format %{ "LPEBR $dst,$src\t float" %} 7471 opcode(LPEBR_ZOPC); 7472 ins_encode(z_rreform(dst, src)); 7473 ins_pipe(pipe_class_dummy); 7474 %} 7475 7476 // Absolute float double precision 7477 instruct absD_reg(regD dst, regD src, flagsReg cr) %{ 7478 match(Set dst (AbsD src)); 7479 effect(KILL cr); 7480 size(4); 7481 format %{ "LPDBR $dst,$src\t double" %} 7482 opcode(LPDBR_ZOPC); 7483 ins_encode(z_rreform(dst, src)); 7484 ins_pipe(pipe_class_dummy); 7485 %} 7486 7487 // NEG(ABS) 7488 7489 // Negative absolute float single precision 7490 instruct nabsF_reg(regF dst, regF src, flagsReg cr) %{ 7491 match(Set dst (NegF (AbsF src))); 7492 effect(KILL cr); 7493 size(4); 7494 format %{ "LNEBR $dst,$src\t float" %} 7495 opcode(LNEBR_ZOPC); 7496 ins_encode(z_rreform(dst, src)); 7497 ins_pipe(pipe_class_dummy); 7498 %} 7499 7500 // Negative absolute float double precision 7501 instruct nabsD_reg(regD dst, regD src, flagsReg cr) %{ 7502 match(Set dst (NegD (AbsD src))); 7503 effect(KILL cr); 7504 size(4); 7505 format %{ "LNDBR $dst,$src\t double" %} 7506 opcode(LNDBR_ZOPC); 7507 ins_encode(z_rreform(dst, src)); 7508 ins_pipe(pipe_class_dummy); 7509 %} 7510 7511 // NEG 7512 7513 instruct negF_reg(regF dst, regF src, flagsReg cr) %{ 7514 match(Set dst (NegF src)); 7515 effect(KILL cr); 7516 size(4); 7517 format %{ "NegF $dst,$src\t float" %} 7518 ins_encode %{ __ z_lcebr($dst$$FloatRegister, $src$$FloatRegister); %} 7519 ins_pipe(pipe_class_dummy); 7520 %} 7521 7522 instruct negD_reg(regD dst, regD src, flagsReg cr) %{ 7523 match(Set dst (NegD src)); 7524 effect(KILL cr); 7525 size(4); 7526 format %{ "NegD $dst,$src\t double" %} 7527 ins_encode %{ __ z_lcdbr($dst$$FloatRegister, $src$$FloatRegister); %} 7528 ins_pipe(pipe_class_dummy); 7529 %} 7530 7531 // SQRT 7532 7533 // Sqrt float precision 7534 instruct sqrtF_reg(regF dst, regF src) %{ 7535 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7536 // CC remains unchanged. 7537 ins_cost(ALU_REG_COST); 7538 size(4); 7539 format %{ "SQEBR $dst,$src" %} 7540 opcode(SQEBR_ZOPC); 7541 ins_encode(z_rreform(dst, src)); 7542 ins_pipe(pipe_class_dummy); 7543 %} 7544 7545 // Sqrt double precision 7546 instruct sqrtD_reg(regD dst, regD src) %{ 7547 match(Set dst (SqrtD src)); 7548 // CC remains unchanged. 7549 ins_cost(ALU_REG_COST); 7550 size(4); 7551 format %{ "SQDBR $dst,$src" %} 7552 opcode(SQDBR_ZOPC); 7553 ins_encode(z_rreform(dst, src)); 7554 ins_pipe(pipe_class_dummy); 7555 %} 7556 7557 instruct sqrtF_mem(regF dst, memoryRX src) %{ 7558 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7559 // CC remains unchanged. 7560 ins_cost(ALU_MEMORY_COST); 7561 size(6); 7562 format %{ "SQEB $dst,$src\t # floatMemory" %} 7563 opcode(SQEB_ZOPC); 7564 ins_encode(z_form_rt_memFP(dst, src)); 7565 ins_pipe(pipe_class_dummy); 7566 %} 7567 7568 instruct sqrtD_mem(regD dst, memoryRX src) %{ 7569 match(Set dst (SqrtD src)); 7570 // CC remains unchanged. 7571 ins_cost(ALU_MEMORY_COST); 7572 // TODO: s390 port size(FIXED_SIZE); 7573 format %{ "SQDB $dst,$src\t # doubleMemory" %} 7574 opcode(SQDB_ZOPC); 7575 ins_encode(z_form_rt_memFP(dst, src)); 7576 ins_pipe(pipe_class_dummy); 7577 %} 7578 7579 //----------Logical Instructions----------------------------------------------- 7580 7581 // Register And 7582 instruct andI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 7583 match(Set dst (AndI dst src)); 7584 effect(KILL cr); 7585 ins_cost(DEFAULT_COST_LOW); 7586 size(2); 7587 format %{ "NR $dst,$src\t # int" %} 7588 opcode(NR_ZOPC); 7589 ins_encode(z_rrform(dst, src)); 7590 ins_pipe(pipe_class_dummy); 7591 %} 7592 7593 instruct andI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 7594 match(Set dst (AndI dst (LoadI src))); 7595 effect(KILL cr); 7596 ins_cost(MEMORY_REF_COST); 7597 // TODO: s390 port size(VARIABLE_SIZE); 7598 format %{ "N(Y) $dst, $src\t # int" %} 7599 opcode(NY_ZOPC, N_ZOPC); 7600 ins_encode(z_form_rt_mem_opt(dst, src)); 7601 ins_pipe(pipe_class_dummy); 7602 %} 7603 7604 // Immediate And 7605 instruct andI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{ 7606 match(Set dst (AndI dst src)); 7607 effect(KILL cr); 7608 ins_cost(DEFAULT_COST_HIGH); 7609 size(6); 7610 format %{ "NILF $dst,$src" %} 7611 opcode(NILF_ZOPC); 7612 ins_encode(z_rilform_unsigned(dst, src)); 7613 ins_pipe(pipe_class_dummy); 7614 %} 7615 7616 instruct andI_reg_uimmI_LH1(iRegI dst, uimmI_LH1 src, flagsReg cr) %{ 7617 match(Set dst (AndI dst src)); 7618 effect(KILL cr); 7619 ins_cost(DEFAULT_COST); 7620 size(4); 7621 format %{ "NILH $dst,$src" %} 7622 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %} 7623 ins_pipe(pipe_class_dummy); 7624 %} 7625 7626 instruct andI_reg_uimmI_LL1(iRegI dst, uimmI_LL1 src, flagsReg cr) %{ 7627 match(Set dst (AndI dst src)); 7628 effect(KILL cr); 7629 ins_cost(DEFAULT_COST); 7630 size(4); 7631 format %{ "NILL $dst,$src" %} 7632 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %} 7633 ins_pipe(pipe_class_dummy); 7634 %} 7635 7636 // Register And Long 7637 instruct andL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{ 7638 match(Set dst (AndL dst src)); 7639 effect(KILL cr); 7640 ins_cost(DEFAULT_COST); 7641 size(4); 7642 format %{ "NGR $dst,$src\t # long" %} 7643 opcode(NGR_ZOPC); 7644 ins_encode(z_rreform(dst, src)); 7645 ins_pipe(pipe_class_dummy); 7646 %} 7647 7648 instruct andL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 7649 match(Set dst (AndL dst (LoadL src))); 7650 effect(KILL cr); 7651 ins_cost(MEMORY_REF_COST); 7652 size(Z_DISP3_SIZE); 7653 format %{ "NG $dst, $src\t # long" %} 7654 opcode(NG_ZOPC, NG_ZOPC); 7655 ins_encode(z_form_rt_mem_opt(dst, src)); 7656 ins_pipe(pipe_class_dummy); 7657 %} 7658 7659 instruct andL_reg_uimmL_LL1(iRegL dst, uimmL_LL1 src, flagsReg cr) %{ 7660 match(Set dst (AndL dst src)); 7661 effect(KILL cr); 7662 ins_cost(DEFAULT_COST); 7663 size(4); 7664 format %{ "NILL $dst,$src\t # long" %} 7665 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %} 7666 ins_pipe(pipe_class_dummy); 7667 %} 7668 7669 instruct andL_reg_uimmL_LH1(iRegL dst, uimmL_LH1 src, flagsReg cr) %{ 7670 match(Set dst (AndL dst src)); 7671 effect(KILL cr); 7672 ins_cost(DEFAULT_COST); 7673 size(4); 7674 format %{ "NILH $dst,$src\t # long" %} 7675 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %} 7676 ins_pipe(pipe_class_dummy); 7677 %} 7678 7679 instruct andL_reg_uimmL_HL1(iRegL dst, uimmL_HL1 src, flagsReg cr) %{ 7680 match(Set dst (AndL dst src)); 7681 effect(KILL cr); 7682 ins_cost(DEFAULT_COST); 7683 size(4); 7684 format %{ "NIHL $dst,$src\t # long" %} 7685 ins_encode %{ __ z_nihl($dst$$Register, ($src$$constant >> 32) & 0xFFFF); %} 7686 ins_pipe(pipe_class_dummy); 7687 %} 7688 7689 instruct andL_reg_uimmL_HH1(iRegL dst, uimmL_HH1 src, flagsReg cr) %{ 7690 match(Set dst (AndL dst src)); 7691 effect(KILL cr); 7692 ins_cost(DEFAULT_COST); 7693 size(4); 7694 format %{ "NIHH $dst,$src\t # long" %} 7695 ins_encode %{ __ z_nihh($dst$$Register, ($src$$constant >> 48) & 0xFFFF); %} 7696 ins_pipe(pipe_class_dummy); 7697 %} 7698 7699 // OR 7700 7701 // Or Instructions 7702 // Register Or 7703 instruct orI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 7704 match(Set dst (OrI dst src)); 7705 effect(KILL cr); 7706 size(2); 7707 format %{ "OR $dst,$src" %} 7708 opcode(OR_ZOPC); 7709 ins_encode(z_rrform(dst, src)); 7710 ins_pipe(pipe_class_dummy); 7711 %} 7712 7713 instruct orI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 7714 match(Set dst (OrI dst (LoadI src))); 7715 effect(KILL cr); 7716 ins_cost(MEMORY_REF_COST); 7717 // TODO: s390 port size(VARIABLE_SIZE); 7718 format %{ "O(Y) $dst, $src\t # int" %} 7719 opcode(OY_ZOPC, O_ZOPC); 7720 ins_encode(z_form_rt_mem_opt(dst, src)); 7721 ins_pipe(pipe_class_dummy); 7722 %} 7723 7724 // Immediate Or 7725 instruct orI_reg_uimm16(iRegI dst, uimmI16 con, flagsReg cr) %{ 7726 match(Set dst (OrI dst con)); 7727 effect(KILL cr); 7728 size(4); 7729 format %{ "OILL $dst,$con" %} 7730 opcode(OILL_ZOPC); 7731 ins_encode(z_riform_unsigned(dst,con)); 7732 ins_pipe(pipe_class_dummy); 7733 %} 7734 7735 instruct orI_reg_uimm32(iRegI dst, uimmI con, flagsReg cr) %{ 7736 match(Set dst (OrI dst con)); 7737 effect(KILL cr); 7738 ins_cost(DEFAULT_COST_HIGH); 7739 size(6); 7740 format %{ "OILF $dst,$con" %} 7741 opcode(OILF_ZOPC); 7742 ins_encode(z_rilform_unsigned(dst,con)); 7743 ins_pipe(pipe_class_dummy); 7744 %} 7745 7746 // Register Or Long 7747 instruct orL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{ 7748 match(Set dst (OrL dst src)); 7749 effect(KILL cr); 7750 ins_cost(DEFAULT_COST); 7751 size(4); 7752 format %{ "OGR $dst,$src\t # long" %} 7753 opcode(OGR_ZOPC); 7754 ins_encode(z_rreform(dst, src)); 7755 ins_pipe(pipe_class_dummy); 7756 %} 7757 7758 instruct orL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 7759 match(Set dst (OrL dst (LoadL src))); 7760 effect(KILL cr); 7761 ins_cost(MEMORY_REF_COST); 7762 size(Z_DISP3_SIZE); 7763 format %{ "OG $dst, $src\t # long" %} 7764 opcode(OG_ZOPC, OG_ZOPC); 7765 ins_encode(z_form_rt_mem_opt(dst, src)); 7766 ins_pipe(pipe_class_dummy); 7767 %} 7768 7769 // Immediate Or long 7770 instruct orL_reg_uimm16(iRegL dst, uimmL16 con, flagsReg cr) %{ 7771 match(Set dst (OrL dst con)); 7772 effect(KILL cr); 7773 ins_cost(DEFAULT_COST); 7774 size(4); 7775 format %{ "OILL $dst,$con\t # long" %} 7776 opcode(OILL_ZOPC); 7777 ins_encode(z_riform_unsigned(dst,con)); 7778 ins_pipe(pipe_class_dummy); 7779 %} 7780 7781 instruct orL_reg_uimm32(iRegI dst, uimmL32 con, flagsReg cr) %{ 7782 match(Set dst (OrI dst con)); 7783 effect(KILL cr); 7784 ins_cost(DEFAULT_COST_HIGH); 7785 // TODO: s390 port size(FIXED_SIZE); 7786 format %{ "OILF $dst,$con\t # long" %} 7787 opcode(OILF_ZOPC); 7788 ins_encode(z_rilform_unsigned(dst,con)); 7789 ins_pipe(pipe_class_dummy); 7790 %} 7791 7792 // XOR 7793 7794 // Register Xor 7795 instruct xorI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 7796 match(Set dst (XorI dst src)); 7797 effect(KILL cr); 7798 size(2); 7799 format %{ "XR $dst,$src" %} 7800 opcode(XR_ZOPC); 7801 ins_encode(z_rrform(dst, src)); 7802 ins_pipe(pipe_class_dummy); 7803 %} 7804 7805 instruct xorI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 7806 match(Set dst (XorI dst (LoadI src))); 7807 effect(KILL cr); 7808 ins_cost(MEMORY_REF_COST); 7809 // TODO: s390 port size(VARIABLE_SIZE); 7810 format %{ "X(Y) $dst, $src\t # int" %} 7811 opcode(XY_ZOPC, X_ZOPC); 7812 ins_encode(z_form_rt_mem_opt(dst, src)); 7813 ins_pipe(pipe_class_dummy); 7814 %} 7815 7816 // Immediate Xor 7817 instruct xorI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{ 7818 match(Set dst (XorI dst src)); 7819 effect(KILL cr); 7820 ins_cost(DEFAULT_COST_HIGH); 7821 size(6); 7822 format %{ "XILF $dst,$src" %} 7823 opcode(XILF_ZOPC); 7824 ins_encode(z_rilform_unsigned(dst, src)); 7825 ins_pipe(pipe_class_dummy); 7826 %} 7827 7828 // Register Xor Long 7829 instruct xorL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{ 7830 match(Set dst (XorL dst src)); 7831 effect(KILL cr); 7832 ins_cost(DEFAULT_COST); 7833 size(4); 7834 format %{ "XGR $dst,$src\t # long" %} 7835 opcode(XGR_ZOPC); 7836 ins_encode(z_rreform(dst, src)); 7837 ins_pipe(pipe_class_dummy); 7838 %} 7839 7840 instruct xorL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 7841 match(Set dst (XorL dst (LoadL src))); 7842 effect(KILL cr); 7843 ins_cost(MEMORY_REF_COST); 7844 size(Z_DISP3_SIZE); 7845 format %{ "XG $dst, $src\t # long" %} 7846 opcode(XG_ZOPC, XG_ZOPC); 7847 ins_encode(z_form_rt_mem_opt(dst, src)); 7848 ins_pipe(pipe_class_dummy); 7849 %} 7850 7851 // Immediate Xor Long 7852 instruct xorL_reg_uimm32(iRegL dst, uimmL32 con, flagsReg cr) %{ 7853 match(Set dst (XorL dst con)); 7854 effect(KILL cr); 7855 ins_cost(DEFAULT_COST_HIGH); 7856 size(6); 7857 format %{ "XILF $dst,$con\t # long" %} 7858 opcode(XILF_ZOPC); 7859 ins_encode(z_rilform_unsigned(dst,con)); 7860 ins_pipe(pipe_class_dummy); 7861 %} 7862 7863 //----------Convert to Boolean------------------------------------------------- 7864 7865 // Convert integer to boolean. 7866 instruct convI2B(iRegI dst, iRegI src, flagsReg cr) %{ 7867 match(Set dst (Conv2B src)); 7868 effect(KILL cr); 7869 ins_cost(3 * DEFAULT_COST); 7870 size(6); 7871 format %{ "convI2B $dst,$src" %} 7872 ins_encode %{ 7873 __ z_lnr($dst$$Register, $src$$Register); // Rdst := -|Rsrc|, i.e. Rdst == 0 <=> Rsrc == 0 7874 __ z_srl($dst$$Register, 31); // Rdst := sign(Rdest) 7875 %} 7876 ins_pipe(pipe_class_dummy); 7877 %} 7878 7879 instruct convP2B(iRegI dst, iRegP_N2P src, flagsReg cr) %{ 7880 match(Set dst (Conv2B src)); 7881 effect(KILL cr); 7882 ins_cost(3 * DEFAULT_COST); 7883 size(10); 7884 format %{ "convP2B $dst,$src" %} 7885 ins_encode %{ 7886 __ z_lngr($dst$$Register, $src$$Register); // Rdst := -|Rsrc| i.e. Rdst == 0 <=> Rsrc == 0 7887 __ z_srlg($dst$$Register, $dst$$Register, 63); // Rdst := sign(Rdest) 7888 %} 7889 ins_pipe(pipe_class_dummy); 7890 %} 7891 7892 instruct cmpLTMask_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 7893 match(Set dst (CmpLTMask dst src)); 7894 effect(KILL cr); 7895 ins_cost(2 * DEFAULT_COST); 7896 size(18); 7897 format %{ "Set $dst CmpLTMask $dst,$src" %} 7898 ins_encode %{ 7899 // Avoid signed 32 bit overflow: Do sign extend and sub 64 bit. 7900 __ z_lgfr(Z_R0_scratch, $src$$Register); 7901 __ z_lgfr($dst$$Register, $dst$$Register); 7902 __ z_sgr($dst$$Register, Z_R0_scratch); 7903 __ z_srag($dst$$Register, $dst$$Register, 63); 7904 %} 7905 ins_pipe(pipe_class_dummy); 7906 %} 7907 7908 instruct cmpLTMask_reg_zero(iRegI dst, immI_0 zero, flagsReg cr) %{ 7909 match(Set dst (CmpLTMask dst zero)); 7910 effect(KILL cr); 7911 ins_cost(DEFAULT_COST); 7912 size(4); 7913 format %{ "Set $dst CmpLTMask $dst,$zero" %} 7914 ins_encode %{ __ z_sra($dst$$Register, 31); %} 7915 ins_pipe(pipe_class_dummy); 7916 %} 7917 7918 7919 //----------Arithmetic Conversion Instructions--------------------------------- 7920 // The conversions operations are all Alpha sorted. Please keep it that way! 7921 7922 instruct convD2F_reg(regF dst, regD src) %{ 7923 match(Set dst (ConvD2F src)); 7924 // CC remains unchanged. 7925 size(4); 7926 format %{ "LEDBR $dst,$src" %} 7927 opcode(LEDBR_ZOPC); 7928 ins_encode(z_rreform(dst, src)); 7929 ins_pipe(pipe_class_dummy); 7930 %} 7931 7932 instruct convF2I_reg(iRegI dst, regF src, flagsReg cr) %{ 7933 match(Set dst (ConvF2I src)); 7934 effect(KILL cr); 7935 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 7936 size(16); 7937 format %{ "convF2I $dst,$src" %} 7938 ins_encode %{ 7939 Label done; 7940 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0. 7941 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round. 7942 __ z_brno(done); // Result is zero if unordered argument. 7943 __ z_cfebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); 7944 __ bind(done); 7945 %} 7946 ins_pipe(pipe_class_dummy); 7947 %} 7948 7949 instruct convD2I_reg(iRegI dst, regD src, flagsReg cr) %{ 7950 match(Set dst (ConvD2I src)); 7951 effect(KILL cr); 7952 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 7953 size(16); 7954 format %{ "convD2I $dst,$src" %} 7955 ins_encode %{ 7956 Label done; 7957 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0. 7958 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round. 7959 __ z_brno(done); // Result is zero if unordered argument. 7960 __ z_cfdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); 7961 __ bind(done); 7962 %} 7963 ins_pipe(pipe_class_dummy); 7964 %} 7965 7966 instruct convF2L_reg(iRegL dst, regF src, flagsReg cr) %{ 7967 match(Set dst (ConvF2L src)); 7968 effect(KILL cr); 7969 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 7970 size(16); 7971 format %{ "convF2L $dst,$src" %} 7972 ins_encode %{ 7973 Label done; 7974 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0. 7975 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round. 7976 __ z_brno(done); // Result is zero if unordered argument. 7977 __ z_cgebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); 7978 __ bind(done); 7979 %} 7980 ins_pipe(pipe_class_dummy); 7981 %} 7982 7983 instruct convD2L_reg(iRegL dst, regD src, flagsReg cr) %{ 7984 match(Set dst (ConvD2L src)); 7985 effect(KILL cr); 7986 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 7987 size(16); 7988 format %{ "convD2L $dst,$src" %} 7989 ins_encode %{ 7990 Label done; 7991 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0. 7992 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round. 7993 __ z_brno(done); // Result is zero if unordered argument. 7994 __ z_cgdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); 7995 __ bind(done); 7996 %} 7997 ins_pipe(pipe_class_dummy); 7998 %} 7999 8000 instruct convF2D_reg(regD dst, regF src) %{ 8001 match(Set dst (ConvF2D src)); 8002 // CC remains unchanged. 8003 size(4); 8004 format %{ "LDEBR $dst,$src" %} 8005 opcode(LDEBR_ZOPC); 8006 ins_encode(z_rreform(dst, src)); 8007 ins_pipe(pipe_class_dummy); 8008 %} 8009 8010 instruct convF2D_mem(regD dst, memoryRX src) %{ 8011 match(Set dst (ConvF2D src)); 8012 // CC remains unchanged. 8013 size(6); 8014 format %{ "LDEB $dst,$src" %} 8015 opcode(LDEB_ZOPC); 8016 ins_encode(z_form_rt_memFP(dst, src)); 8017 ins_pipe(pipe_class_dummy); 8018 %} 8019 8020 instruct convI2D_reg(regD dst, iRegI src) %{ 8021 match(Set dst (ConvI2D src)); 8022 // CC remains unchanged. 8023 ins_cost(DEFAULT_COST); 8024 size(4); 8025 format %{ "CDFBR $dst,$src" %} 8026 opcode(CDFBR_ZOPC); 8027 ins_encode(z_rreform(dst, src)); 8028 ins_pipe(pipe_class_dummy); 8029 %} 8030 8031 // Optimization that saves up to two memory operations for each conversion. 8032 instruct convI2F_ireg(regF dst, iRegI src) %{ 8033 match(Set dst (ConvI2F src)); 8034 // CC remains unchanged. 8035 ins_cost(DEFAULT_COST); 8036 size(4); 8037 format %{ "CEFBR $dst,$src\t # convert int to float" %} 8038 opcode(CEFBR_ZOPC); 8039 ins_encode(z_rreform(dst, src)); 8040 ins_pipe(pipe_class_dummy); 8041 %} 8042 8043 instruct convI2L_reg(iRegL dst, iRegI src) %{ 8044 match(Set dst (ConvI2L src)); 8045 size(4); 8046 format %{ "LGFR $dst,$src\t # int->long" %} 8047 opcode(LGFR_ZOPC); 8048 ins_encode(z_rreform(dst, src)); 8049 ins_pipe(pipe_class_dummy); 8050 %} 8051 8052 // Zero-extend convert int to long. 8053 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask) %{ 8054 match(Set dst (AndL (ConvI2L src) mask)); 8055 size(4); 8056 format %{ "LLGFR $dst, $src \t # zero-extend int to long" %} 8057 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %} 8058 ins_pipe(pipe_class_dummy); 8059 %} 8060 8061 // Zero-extend convert int to long. 8062 instruct convI2L_mem_zex(iRegL dst, memory src, immL_32bits mask) %{ 8063 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); 8064 // Uses load_const_optmized, so size can vary. 8065 // TODO: s390 port size(VARIABLE_SIZE); 8066 format %{ "LLGF $dst, $src \t # zero-extend int to long" %} 8067 opcode(LLGF_ZOPC, LLGF_ZOPC); 8068 ins_encode(z_form_rt_mem_opt(dst, src)); 8069 ins_pipe(pipe_class_dummy); 8070 %} 8071 8072 // Zero-extend long 8073 instruct zeroExtend_long(iRegL dst, iRegL src, immL_32bits mask) %{ 8074 match(Set dst (AndL src mask)); 8075 size(4); 8076 format %{ "LLGFR $dst, $src \t # zero-extend long to long" %} 8077 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %} 8078 ins_pipe(pipe_class_dummy); 8079 %} 8080 8081 instruct rShiftI16_lShiftI16_reg(iRegI dst, iRegI src, immI_16 amount) %{ 8082 match(Set dst (RShiftI (LShiftI src amount) amount)); 8083 size(4); 8084 format %{ "LHR $dst,$src\t short->int" %} 8085 opcode(LHR_ZOPC); 8086 ins_encode(z_rreform(dst, src)); 8087 ins_pipe(pipe_class_dummy); 8088 %} 8089 8090 instruct rShiftI24_lShiftI24_reg(iRegI dst, iRegI src, immI_24 amount) %{ 8091 match(Set dst (RShiftI (LShiftI src amount) amount)); 8092 size(4); 8093 format %{ "LBR $dst,$src\t byte->int" %} 8094 opcode(LBR_ZOPC); 8095 ins_encode(z_rreform(dst, src)); 8096 ins_pipe(pipe_class_dummy); 8097 %} 8098 8099 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 8100 match(Set dst (MoveF2I src)); 8101 ins_cost(MEMORY_REF_COST); 8102 size(4); 8103 format %{ "L $dst,$src\t # MoveF2I" %} 8104 opcode(L_ZOPC); 8105 ins_encode(z_form_rt_mem(dst, src)); 8106 ins_pipe(pipe_class_dummy); 8107 %} 8108 8109 // javax.imageio.stream.ImageInputStreamImpl.toFloats([B[FII) 8110 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 8111 match(Set dst (MoveI2F src)); 8112 ins_cost(MEMORY_REF_COST); 8113 // TODO: s390 port size(FIXED_SIZE); 8114 format %{ "LE $dst,$src\t # MoveI2F" %} 8115 opcode(LE_ZOPC); 8116 ins_encode(z_form_rt_mem(dst, src)); 8117 ins_pipe(pipe_class_dummy); 8118 %} 8119 8120 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 8121 match(Set dst (MoveD2L src)); 8122 ins_cost(MEMORY_REF_COST); 8123 size(6); 8124 format %{ "LG $src,$dst\t # MoveD2L" %} 8125 opcode(LG_ZOPC); 8126 ins_encode(z_form_rt_mem(dst, src)); 8127 ins_pipe(pipe_class_dummy); 8128 %} 8129 8130 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 8131 match(Set dst (MoveL2D src)); 8132 ins_cost(MEMORY_REF_COST); 8133 size(4); 8134 format %{ "LD $dst,$src\t # MoveL2D" %} 8135 opcode(LD_ZOPC); 8136 ins_encode(z_form_rt_mem(dst, src)); 8137 ins_pipe(pipe_class_dummy); 8138 %} 8139 8140 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 8141 match(Set dst (MoveI2F src)); 8142 ins_cost(MEMORY_REF_COST); 8143 size(4); 8144 format %{ "ST $src,$dst\t # MoveI2F" %} 8145 opcode(ST_ZOPC); 8146 ins_encode(z_form_rt_mem(src, dst)); 8147 ins_pipe(pipe_class_dummy); 8148 %} 8149 8150 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 8151 match(Set dst (MoveD2L src)); 8152 effect(DEF dst, USE src); 8153 ins_cost(MEMORY_REF_COST); 8154 size(4); 8155 format %{ "STD $src,$dst\t # MoveD2L" %} 8156 opcode(STD_ZOPC); 8157 ins_encode(z_form_rt_mem(src,dst)); 8158 ins_pipe(pipe_class_dummy); 8159 %} 8160 8161 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 8162 match(Set dst (MoveL2D src)); 8163 ins_cost(MEMORY_REF_COST); 8164 size(6); 8165 format %{ "STG $src,$dst\t # MoveL2D" %} 8166 opcode(STG_ZOPC); 8167 ins_encode(z_form_rt_mem(src,dst)); 8168 ins_pipe(pipe_class_dummy); 8169 %} 8170 8171 instruct convL2F_reg(regF dst, iRegL src) %{ 8172 match(Set dst (ConvL2F src)); 8173 // CC remains unchanged. 8174 ins_cost(DEFAULT_COST); 8175 size(4); 8176 format %{ "CEGBR $dst,$src" %} 8177 opcode(CEGBR_ZOPC); 8178 ins_encode(z_rreform(dst, src)); 8179 ins_pipe(pipe_class_dummy); 8180 %} 8181 8182 instruct convL2D_reg(regD dst, iRegL src) %{ 8183 match(Set dst (ConvL2D src)); 8184 // CC remains unchanged. 8185 ins_cost(DEFAULT_COST); 8186 size(4); 8187 format %{ "CDGBR $dst,$src" %} 8188 opcode(CDGBR_ZOPC); 8189 ins_encode(z_rreform(dst, src)); 8190 ins_pipe(pipe_class_dummy); 8191 %} 8192 8193 instruct convL2I_reg(iRegI dst, iRegL src) %{ 8194 match(Set dst (ConvL2I src)); 8195 // TODO: s390 port size(VARIABLE_SIZE); 8196 format %{ "LR $dst,$src\t # long->int (if needed)" %} 8197 ins_encode %{ __ lr_if_needed($dst$$Register, $src$$Register); %} 8198 ins_pipe(pipe_class_dummy); 8199 %} 8200 8201 // Register Shift Right Immediate 8202 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt, flagsReg cr) %{ 8203 match(Set dst (ConvL2I (RShiftL src cnt))); 8204 effect(KILL cr); 8205 size(6); 8206 format %{ "SRAG $dst,$src,$cnt" %} 8207 opcode(SRAG_ZOPC); 8208 ins_encode(z_rsyform_const(dst, src, cnt)); 8209 ins_pipe(pipe_class_dummy); 8210 %} 8211 8212 //----------TRAP based zero checks and range checks---------------------------- 8213 8214 // SIGTRAP based implicit range checks in compiled code. 8215 // A range check in the ideal world has one of the following shapes: 8216 // - (If le (CmpU length index)), (IfTrue throw exception) 8217 // - (If lt (CmpU index length)), (IfFalse throw exception) 8218 // 8219 // Match range check 'If le (CmpU length index)' 8220 instruct rangeCheck_iReg_uimmI16(cmpOpT cmp, iRegI length, uimmI16 index, label labl) %{ 8221 match(If cmp (CmpU length index)); 8222 effect(USE labl); 8223 predicate(TrapBasedRangeChecks && 8224 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le && 8225 PROB_UNLIKELY(_leaf->as_If ()->_prob) >= PROB_ALWAYS && 8226 Matcher::branches_to_uncommon_trap(_leaf)); 8227 ins_cost(1); 8228 // TODO: s390 port size(FIXED_SIZE); 8229 8230 ins_is_TrapBasedCheckNode(true); 8231 8232 format %{ "RangeCheck len=$length cmp=$cmp idx=$index => trap $labl" %} 8233 ins_encode %{ __ z_clfit($length$$Register, $index$$constant, $cmp$$cmpcode); %} 8234 ins_pipe(pipe_class_trap); 8235 %} 8236 8237 // Match range check 'If lt (CmpU index length)' 8238 instruct rangeCheck_iReg_iReg(cmpOpT cmp, iRegI index, iRegI length, label labl, flagsReg cr) %{ 8239 match(If cmp (CmpU index length)); 8240 effect(USE labl, KILL cr); 8241 predicate(TrapBasedRangeChecks && 8242 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 8243 _leaf->as_If ()->_prob >= PROB_ALWAYS && 8244 Matcher::branches_to_uncommon_trap(_leaf)); 8245 ins_cost(1); 8246 // TODO: s390 port size(FIXED_SIZE); 8247 8248 ins_is_TrapBasedCheckNode(true); 8249 8250 format %{ "RangeCheck idx=$index cmp=$cmp len=$length => trap $labl" %} 8251 ins_encode %{ __ z_clrt($index$$Register, $length$$Register, $cmp$$cmpcode); %} 8252 ins_pipe(pipe_class_trap); 8253 %} 8254 8255 // Match range check 'If lt (CmpU index length)' 8256 instruct rangeCheck_uimmI16_iReg(cmpOpT cmp, iRegI index, uimmI16 length, label labl) %{ 8257 match(If cmp (CmpU index length)); 8258 effect(USE labl); 8259 predicate(TrapBasedRangeChecks && 8260 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 8261 _leaf->as_If ()->_prob >= PROB_ALWAYS && 8262 Matcher::branches_to_uncommon_trap(_leaf)); 8263 ins_cost(1); 8264 // TODO: s390 port size(FIXED_SIZE); 8265 8266 ins_is_TrapBasedCheckNode(true); 8267 8268 format %{ "RangeCheck idx=$index cmp=$cmp len= $length => trap $labl" %} 8269 ins_encode %{ __ z_clfit($index$$Register, $length$$constant, $cmp$$cmpcode); %} 8270 ins_pipe(pipe_class_trap); 8271 %} 8272 8273 // Implicit zero checks (more implicit null checks). 8274 instruct zeroCheckP_iReg_imm0(cmpOpT cmp, iRegP_N2P value, immP0 zero, label labl) %{ 8275 match(If cmp (CmpP value zero)); 8276 effect(USE labl); 8277 predicate(TrapBasedNullChecks && 8278 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 8279 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) && 8280 Matcher::branches_to_uncommon_trap(_leaf)); 8281 size(6); 8282 8283 ins_is_TrapBasedCheckNode(true); 8284 8285 format %{ "ZeroCheckP value=$value cmp=$cmp zero=$zero => trap $labl" %} 8286 ins_encode %{ __ z_cgit($value$$Register, 0, $cmp$$cmpcode); %} 8287 ins_pipe(pipe_class_trap); 8288 %} 8289 8290 // Implicit zero checks (more implicit null checks). 8291 instruct zeroCheckN_iReg_imm0(cmpOpT cmp, iRegN_P2N value, immN0 zero, label labl) %{ 8292 match(If cmp (CmpN value zero)); 8293 effect(USE labl); 8294 predicate(TrapBasedNullChecks && 8295 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 8296 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) && 8297 Matcher::branches_to_uncommon_trap(_leaf)); 8298 size(6); 8299 8300 ins_is_TrapBasedCheckNode(true); 8301 8302 format %{ "ZeroCheckN value=$value cmp=$cmp zero=$zero => trap $labl" %} 8303 ins_encode %{ __ z_cit($value$$Register, 0, $cmp$$cmpcode); %} 8304 ins_pipe(pipe_class_trap); 8305 %} 8306 8307 //----------Compare instructions----------------------------------------------- 8308 8309 // INT signed 8310 8311 // Compare Integers 8312 instruct compI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{ 8313 match(Set cr (CmpI op1 op2)); 8314 size(2); 8315 format %{ "CR $op1,$op2" %} 8316 opcode(CR_ZOPC); 8317 ins_encode(z_rrform(op1, op2)); 8318 ins_pipe(pipe_class_dummy); 8319 %} 8320 8321 instruct compI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{ 8322 match(Set cr (CmpI op1 op2)); 8323 size(6); 8324 format %{ "CFI $op1,$op2" %} 8325 opcode(CFI_ZOPC); 8326 ins_encode(z_rilform_signed(op1, op2)); 8327 ins_pipe(pipe_class_dummy); 8328 %} 8329 8330 instruct compI_reg_imm16(flagsReg cr, iRegI op1, immI16 op2) %{ 8331 match(Set cr (CmpI op1 op2)); 8332 size(4); 8333 format %{ "CHI $op1,$op2" %} 8334 opcode(CHI_ZOPC); 8335 ins_encode(z_riform_signed(op1, op2)); 8336 ins_pipe(pipe_class_dummy); 8337 %} 8338 8339 instruct compI_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{ 8340 match(Set cr (CmpI op1 zero)); 8341 ins_cost(DEFAULT_COST_LOW); 8342 size(2); 8343 format %{ "LTR $op1,$op1" %} 8344 opcode(LTR_ZOPC); 8345 ins_encode(z_rrform(op1, op1)); 8346 ins_pipe(pipe_class_dummy); 8347 %} 8348 8349 instruct compI_reg_mem(flagsReg cr, iRegI op1, memory op2)%{ 8350 match(Set cr (CmpI op1 (LoadI op2))); 8351 ins_cost(MEMORY_REF_COST); 8352 // TODO: s390 port size(VARIABLE_SIZE); 8353 format %{ "C(Y) $op1, $op2\t # int" %} 8354 opcode(CY_ZOPC, C_ZOPC); 8355 ins_encode(z_form_rt_mem_opt(op1, op2)); 8356 ins_pipe(pipe_class_dummy); 8357 %} 8358 8359 // INT unsigned 8360 8361 instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{ 8362 match(Set cr (CmpU op1 op2)); 8363 size(2); 8364 format %{ "CLR $op1,$op2\t # unsigned" %} 8365 opcode(CLR_ZOPC); 8366 ins_encode(z_rrform(op1, op2)); 8367 ins_pipe(pipe_class_dummy); 8368 %} 8369 8370 instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{ 8371 match(Set cr (CmpU op1 op2)); 8372 size(6); 8373 format %{ "CLFI $op1,$op2\t # unsigned" %} 8374 opcode(CLFI_ZOPC); 8375 ins_encode(z_rilform_unsigned(op1, op2)); 8376 ins_pipe(pipe_class_dummy); 8377 %} 8378 8379 instruct compU_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{ 8380 match(Set cr (CmpU op1 zero)); 8381 ins_cost(DEFAULT_COST_LOW); 8382 size(2); 8383 format %{ "LTR $op1,$op1\t # unsigned" %} 8384 opcode(LTR_ZOPC); 8385 ins_encode(z_rrform(op1, op1)); 8386 ins_pipe(pipe_class_dummy); 8387 %} 8388 8389 instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{ 8390 match(Set cr (CmpU op1 (LoadI op2))); 8391 ins_cost(MEMORY_REF_COST); 8392 // TODO: s390 port size(VARIABLE_SIZE); 8393 format %{ "CL(Y) $op1, $op2\t # unsigned" %} 8394 opcode(CLY_ZOPC, CL_ZOPC); 8395 ins_encode(z_form_rt_mem_opt(op1, op2)); 8396 ins_pipe(pipe_class_dummy); 8397 %} 8398 8399 // LONG signed 8400 8401 instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{ 8402 match(Set cr (CmpL op1 op2)); 8403 size(4); 8404 format %{ "CGR $op1,$op2\t # long" %} 8405 opcode(CGR_ZOPC); 8406 ins_encode(z_rreform(op1, op2)); 8407 ins_pipe(pipe_class_dummy); 8408 %} 8409 8410 instruct compL_reg_regI(flagsReg cr, iRegL op1, iRegI op2) %{ 8411 match(Set cr (CmpL op1 (ConvI2L op2))); 8412 size(4); 8413 format %{ "CGFR $op1,$op2\t # long/int" %} 8414 opcode(CGFR_ZOPC); 8415 ins_encode(z_rreform(op1, op2)); 8416 ins_pipe(pipe_class_dummy); 8417 %} 8418 8419 instruct compL_reg_imm32(flagsReg cr, iRegL op1, immL32 con) %{ 8420 match(Set cr (CmpL op1 con)); 8421 size(6); 8422 format %{ "CGFI $op1,$con" %} 8423 opcode(CGFI_ZOPC); 8424 ins_encode(z_rilform_signed(op1, con)); 8425 ins_pipe(pipe_class_dummy); 8426 %} 8427 8428 instruct compL_reg_imm16(flagsReg cr, iRegL op1, immL16 con) %{ 8429 match(Set cr (CmpL op1 con)); 8430 size(4); 8431 format %{ "CGHI $op1,$con" %} 8432 opcode(CGHI_ZOPC); 8433 ins_encode(z_riform_signed(op1, con)); 8434 ins_pipe(pipe_class_dummy); 8435 %} 8436 8437 instruct compL_reg_imm0(flagsReg cr, iRegL op1, immL_0 con) %{ 8438 match(Set cr (CmpL op1 con)); 8439 ins_cost(DEFAULT_COST_LOW); 8440 size(4); 8441 format %{ "LTGR $op1,$op1" %} 8442 opcode(LTGR_ZOPC); 8443 ins_encode(z_rreform(op1, op1)); 8444 ins_pipe(pipe_class_dummy); 8445 %} 8446 8447 instruct compL_conv_reg_imm0(flagsReg cr, iRegI op1, immL_0 con) %{ 8448 match(Set cr (CmpL (ConvI2L op1) con)); 8449 ins_cost(DEFAULT_COST_LOW); 8450 size(4); 8451 format %{ "LTGFR $op1,$op1" %} 8452 opcode(LTGFR_ZOPC); 8453 ins_encode(z_rreform(op1, op1)); 8454 ins_pipe(pipe_class_dummy); 8455 %} 8456 8457 instruct compL_reg_mem(iRegL dst, memory src, flagsReg cr)%{ 8458 match(Set cr (CmpL dst (LoadL src))); 8459 ins_cost(MEMORY_REF_COST); 8460 size(Z_DISP3_SIZE); 8461 format %{ "CG $dst, $src\t # long" %} 8462 opcode(CG_ZOPC, CG_ZOPC); 8463 ins_encode(z_form_rt_mem_opt(dst, src)); 8464 ins_pipe(pipe_class_dummy); 8465 %} 8466 8467 instruct compL_reg_memI(iRegL dst, memory src, flagsReg cr)%{ 8468 match(Set cr (CmpL dst (ConvI2L (LoadI src)))); 8469 ins_cost(MEMORY_REF_COST); 8470 size(Z_DISP3_SIZE); 8471 format %{ "CGF $dst, $src\t # long/int" %} 8472 opcode(CGF_ZOPC, CGF_ZOPC); 8473 ins_encode(z_form_rt_mem_opt(dst, src)); 8474 ins_pipe(pipe_class_dummy); 8475 %} 8476 8477 // LONG unsigned 8478 8479 // PTR unsigned 8480 8481 instruct compP_reg_reg(flagsReg cr, iRegP_N2P op1, iRegP_N2P op2) %{ 8482 match(Set cr (CmpP op1 op2)); 8483 size(4); 8484 format %{ "CLGR $op1,$op2\t # ptr" %} 8485 opcode(CLGR_ZOPC); 8486 ins_encode(z_rreform(op1, op2)); 8487 ins_pipe(pipe_class_dummy); 8488 %} 8489 8490 instruct compP_reg_imm0(flagsReg cr, iRegP_N2P op1, immP0 op2) %{ 8491 match(Set cr (CmpP op1 op2)); 8492 ins_cost(DEFAULT_COST_LOW); 8493 size(4); 8494 format %{ "LTGR $op1, $op1\t # ptr" %} 8495 opcode(LTGR_ZOPC); 8496 ins_encode(z_rreform(op1, op1)); 8497 ins_pipe(pipe_class_dummy); 8498 %} 8499 8500 // Don't use LTGFR which performs sign extend. 8501 instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{ 8502 match(Set cr (CmpP (DecodeN op1) op2)); 8503 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0); 8504 ins_cost(DEFAULT_COST_LOW); 8505 size(2); 8506 format %{ "LTR $op1, $op1\t # ptr" %} 8507 opcode(LTR_ZOPC); 8508 ins_encode(z_rrform(op1, op1)); 8509 ins_pipe(pipe_class_dummy); 8510 %} 8511 8512 instruct compP_reg_mem(iRegP dst, memory src, flagsReg cr)%{ 8513 match(Set cr (CmpP dst (LoadP src))); 8514 ins_cost(MEMORY_REF_COST); 8515 size(Z_DISP3_SIZE); 8516 format %{ "CLG $dst, $src\t # ptr" %} 8517 opcode(CLG_ZOPC, CLG_ZOPC); 8518 ins_encode(z_form_rt_mem_opt(dst, src)); 8519 ins_pipe(pipe_class_dummy); 8520 %} 8521 8522 //----------Max and Min-------------------------------------------------------- 8523 8524 // Max Register with Register 8525 instruct z196_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8526 match(Set dst (MinI src1 src2)); 8527 effect(KILL cr); 8528 predicate(VM_Version::has_LoadStoreConditional()); 8529 ins_cost(3 * DEFAULT_COST); 8530 // TODO: s390 port size(VARIABLE_SIZE); 8531 format %{ "MinI $dst $src1,$src2\t MinI (z196 only)" %} 8532 ins_encode %{ 8533 Register Rdst = $dst$$Register; 8534 Register Rsrc1 = $src1$$Register; 8535 Register Rsrc2 = $src2$$Register; 8536 8537 if (Rsrc1 == Rsrc2) { 8538 if (Rdst != Rsrc1) { 8539 __ z_lgfr(Rdst, Rsrc1); 8540 } 8541 } else if (Rdst == Rsrc1) { // Rdst preset with src1. 8542 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotLow. 8543 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow); 8544 } else if (Rdst == Rsrc2) { // Rdst preset with src2. 8545 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotLow. 8546 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotLow); 8547 } else { 8548 // Rdst is disjoint from operands, move in either case. 8549 __ z_cr(Rsrc1, Rsrc2); 8550 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow); 8551 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow); 8552 } 8553 %} 8554 ins_pipe(pipe_class_dummy); 8555 %} 8556 8557 // Min Register with Register. 8558 instruct z10_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8559 match(Set dst (MinI src1 src2)); 8560 effect(KILL cr); 8561 predicate(VM_Version::has_CompareBranch()); 8562 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8563 // TODO: s390 port size(VARIABLE_SIZE); 8564 format %{ "MinI $dst $src1,$src2\t MinI (z10 only)" %} 8565 ins_encode %{ 8566 Register Rdst = $dst$$Register; 8567 Register Rsrc1 = $src1$$Register; 8568 Register Rsrc2 = $src2$$Register; 8569 Label done; 8570 8571 if (Rsrc1 == Rsrc2) { 8572 if (Rdst != Rsrc1) { 8573 __ z_lgfr(Rdst, Rsrc1); 8574 } 8575 } else if (Rdst == Rsrc1) { 8576 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done); 8577 __ z_lgfr(Rdst, Rsrc2); 8578 } else if (Rdst == Rsrc2) { 8579 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondLow, done); 8580 __ z_lgfr(Rdst, Rsrc1); 8581 } else { 8582 __ z_lgfr(Rdst, Rsrc1); 8583 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done); 8584 __ z_lgfr(Rdst, Rsrc2); 8585 } 8586 __ bind(done); 8587 %} 8588 ins_pipe(pipe_class_dummy); 8589 %} 8590 8591 instruct minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8592 match(Set dst (MinI src1 src2)); 8593 effect(KILL cr); 8594 predicate(!VM_Version::has_CompareBranch()); 8595 ins_cost(3 * DEFAULT_COST + BRANCH_COST); 8596 // TODO: s390 port size(VARIABLE_SIZE); 8597 format %{ "MinI $dst $src1,$src2\t MinI" %} 8598 ins_encode %{ 8599 Register Rdst = $dst$$Register; 8600 Register Rsrc1 = $src1$$Register; 8601 Register Rsrc2 = $src2$$Register; 8602 Label done; 8603 8604 if (Rsrc1 == Rsrc2) { 8605 if (Rdst != Rsrc1) { 8606 __ z_lgfr(Rdst, Rsrc1); 8607 } 8608 } else if (Rdst == Rsrc1) { 8609 __ z_cr(Rsrc1, Rsrc2); 8610 __ z_brl(done); 8611 __ z_lgfr(Rdst, Rsrc2); 8612 } else if (Rdst == Rsrc2) { 8613 __ z_cr(Rsrc2, Rsrc1); 8614 __ z_brl(done); 8615 __ z_lgfr(Rdst, Rsrc1); 8616 } else { 8617 __ z_lgfr(Rdst, Rsrc1); 8618 __ z_cr(Rsrc1, Rsrc2); 8619 __ z_brl(done); 8620 __ z_lgfr(Rdst, Rsrc2); 8621 } 8622 __ bind(done); 8623 %} 8624 ins_pipe(pipe_class_dummy); 8625 %} 8626 8627 instruct z196_minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{ 8628 match(Set dst (MinI src1 src2)); 8629 effect(KILL cr); 8630 predicate(VM_Version::has_LoadStoreConditional()); 8631 ins_cost(3 * DEFAULT_COST); 8632 // TODO: s390 port size(VARIABLE_SIZE); 8633 format %{ "MinI $dst $src1,$src2\t MinI const32 (z196 only)" %} 8634 ins_encode %{ 8635 Register Rdst = $dst$$Register; 8636 Register Rsrc1 = $src1$$Register; 8637 int Isrc2 = $src2$$constant; 8638 8639 if (Rdst == Rsrc1) { 8640 __ load_const_optimized(Z_R0_scratch, Isrc2); 8641 __ z_cfi(Rsrc1, Isrc2); 8642 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow); 8643 } else { 8644 __ load_const_optimized(Rdst, Isrc2); 8645 __ z_cfi(Rsrc1, Isrc2); 8646 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow); 8647 } 8648 %} 8649 ins_pipe(pipe_class_dummy); 8650 %} 8651 8652 instruct minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{ 8653 match(Set dst (MinI src1 src2)); 8654 effect(KILL cr); 8655 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8656 // TODO: s390 port size(VARIABLE_SIZE); 8657 format %{ "MinI $dst $src1,$src2\t MinI const32" %} 8658 ins_encode %{ 8659 Label done; 8660 if ($dst$$Register != $src1$$Register) { 8661 __ z_lgfr($dst$$Register, $src1$$Register); 8662 } 8663 __ z_cfi($src1$$Register, $src2$$constant); 8664 __ z_brl(done); 8665 __ z_lgfi($dst$$Register, $src2$$constant); 8666 __ bind(done); 8667 %} 8668 ins_pipe(pipe_class_dummy); 8669 %} 8670 8671 instruct z196_minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{ 8672 match(Set dst (MinI src1 src2)); 8673 effect(KILL cr); 8674 predicate(VM_Version::has_LoadStoreConditional()); 8675 ins_cost(3 * DEFAULT_COST); 8676 // TODO: s390 port size(VARIABLE_SIZE); 8677 format %{ "MinI $dst $src1,$src2\t MinI const16 (z196 only)" %} 8678 ins_encode %{ 8679 Register Rdst = $dst$$Register; 8680 Register Rsrc1 = $src1$$Register; 8681 int Isrc2 = $src2$$constant; 8682 8683 if (Rdst == Rsrc1) { 8684 __ load_const_optimized(Z_R0_scratch, Isrc2); 8685 __ z_chi(Rsrc1, Isrc2); 8686 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow); 8687 } else { 8688 __ load_const_optimized(Rdst, Isrc2); 8689 __ z_chi(Rsrc1, Isrc2); 8690 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow); 8691 } 8692 %} 8693 ins_pipe(pipe_class_dummy); 8694 %} 8695 8696 instruct minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{ 8697 match(Set dst (MinI src1 src2)); 8698 effect(KILL cr); 8699 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8700 // TODO: s390 port size(VARIABLE_SIZE); 8701 format %{ "MinI $dst $src1,$src2\t MinI const16" %} 8702 ins_encode %{ 8703 Label done; 8704 if ($dst$$Register != $src1$$Register) { 8705 __ z_lgfr($dst$$Register, $src1$$Register); 8706 } 8707 __ z_chi($src1$$Register, $src2$$constant); 8708 __ z_brl(done); 8709 __ z_lghi($dst$$Register, $src2$$constant); 8710 __ bind(done); 8711 %} 8712 ins_pipe(pipe_class_dummy); 8713 %} 8714 8715 instruct z10_minI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{ 8716 match(Set dst (MinI src1 src2)); 8717 effect(KILL cr); 8718 predicate(VM_Version::has_CompareBranch()); 8719 ins_cost(DEFAULT_COST + BRANCH_COST); 8720 // TODO: s390 port size(VARIABLE_SIZE); 8721 format %{ "MinI $dst $src1,$src2\t MinI const8 (z10 only)" %} 8722 ins_encode %{ 8723 Label done; 8724 if ($dst$$Register != $src1$$Register) { 8725 __ z_lgfr($dst$$Register, $src1$$Register); 8726 } 8727 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondLow, done); 8728 __ z_lghi($dst$$Register, $src2$$constant); 8729 __ bind(done); 8730 %} 8731 ins_pipe(pipe_class_dummy); 8732 %} 8733 8734 // Max Register with Register 8735 instruct z196_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8736 match(Set dst (MaxI src1 src2)); 8737 effect(KILL cr); 8738 predicate(VM_Version::has_LoadStoreConditional()); 8739 ins_cost(3 * DEFAULT_COST); 8740 // TODO: s390 port size(VARIABLE_SIZE); 8741 format %{ "MaxI $dst $src1,$src2\t MaxI (z196 only)" %} 8742 ins_encode %{ 8743 Register Rdst = $dst$$Register; 8744 Register Rsrc1 = $src1$$Register; 8745 Register Rsrc2 = $src2$$Register; 8746 8747 if (Rsrc1 == Rsrc2) { 8748 if (Rdst != Rsrc1) { 8749 __ z_lgfr(Rdst, Rsrc1); 8750 } 8751 } else if (Rdst == Rsrc1) { // Rdst preset with src1. 8752 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotHigh. 8753 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh); 8754 } else if (Rdst == Rsrc2) { // Rdst preset with src2. 8755 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotHigh. 8756 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotHigh); 8757 } else { // Rdst is disjoint from operands, move in either case. 8758 __ z_cr(Rsrc1, Rsrc2); 8759 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh); 8760 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh); 8761 } 8762 %} 8763 ins_pipe(pipe_class_dummy); 8764 %} 8765 8766 // Max Register with Register 8767 instruct z10_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8768 match(Set dst (MaxI src1 src2)); 8769 effect(KILL cr); 8770 predicate(VM_Version::has_CompareBranch()); 8771 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8772 // TODO: s390 port size(VARIABLE_SIZE); 8773 format %{ "MaxI $dst $src1,$src2\t MaxI (z10 only)" %} 8774 ins_encode %{ 8775 Register Rdst = $dst$$Register; 8776 Register Rsrc1 = $src1$$Register; 8777 Register Rsrc2 = $src2$$Register; 8778 Label done; 8779 8780 if (Rsrc1 == Rsrc2) { 8781 if (Rdst != Rsrc1) { 8782 __ z_lgfr(Rdst, Rsrc1); 8783 } 8784 } else if (Rdst == Rsrc1) { 8785 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done); 8786 __ z_lgfr(Rdst, Rsrc2); 8787 } else if (Rdst == Rsrc2) { 8788 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondHigh, done); 8789 __ z_lgfr(Rdst, Rsrc1); 8790 } else { 8791 __ z_lgfr(Rdst, Rsrc1); 8792 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done); 8793 __ z_lgfr(Rdst, Rsrc2); 8794 } 8795 __ bind(done); 8796 %} 8797 ins_pipe(pipe_class_dummy); 8798 %} 8799 8800 instruct maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8801 match(Set dst (MaxI src1 src2)); 8802 effect(KILL cr); 8803 predicate(!VM_Version::has_CompareBranch()); 8804 ins_cost(3 * DEFAULT_COST + BRANCH_COST); 8805 // TODO: s390 port size(VARIABLE_SIZE); 8806 format %{ "MaxI $dst $src1,$src2\t MaxI" %} 8807 ins_encode %{ 8808 Register Rdst = $dst$$Register; 8809 Register Rsrc1 = $src1$$Register; 8810 Register Rsrc2 = $src2$$Register; 8811 Label done; 8812 8813 if (Rsrc1 == Rsrc2) { 8814 if (Rdst != Rsrc1) { 8815 __ z_lgfr(Rdst, Rsrc1); 8816 } 8817 } else if (Rdst == Rsrc1) { 8818 __ z_cr(Rsrc1, Rsrc2); 8819 __ z_brh(done); 8820 __ z_lgfr(Rdst, Rsrc2); 8821 } else if (Rdst == Rsrc2) { 8822 __ z_cr(Rsrc2, Rsrc1); 8823 __ z_brh(done); 8824 __ z_lgfr(Rdst, Rsrc1); 8825 } else { 8826 __ z_lgfr(Rdst, Rsrc1); 8827 __ z_cr(Rsrc1, Rsrc2); 8828 __ z_brh(done); 8829 __ z_lgfr(Rdst, Rsrc2); 8830 } 8831 8832 __ bind(done); 8833 %} 8834 8835 ins_pipe(pipe_class_dummy); 8836 %} 8837 8838 instruct z196_maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{ 8839 match(Set dst (MaxI src1 src2)); 8840 effect(KILL cr); 8841 predicate(VM_Version::has_LoadStoreConditional()); 8842 ins_cost(3 * DEFAULT_COST); 8843 // TODO: s390 port size(VARIABLE_SIZE); 8844 format %{ "MaxI $dst $src1,$src2\t MaxI const32 (z196 only)" %} 8845 ins_encode %{ 8846 Register Rdst = $dst$$Register; 8847 Register Rsrc1 = $src1$$Register; 8848 int Isrc2 = $src2$$constant; 8849 8850 if (Rdst == Rsrc1) { 8851 __ load_const_optimized(Z_R0_scratch, Isrc2); 8852 __ z_cfi(Rsrc1, Isrc2); 8853 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh); 8854 } else { 8855 __ load_const_optimized(Rdst, Isrc2); 8856 __ z_cfi(Rsrc1, Isrc2); 8857 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh); 8858 } 8859 %} 8860 ins_pipe(pipe_class_dummy); 8861 %} 8862 8863 instruct maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{ 8864 match(Set dst (MaxI src1 src2)); 8865 effect(KILL cr); 8866 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8867 // TODO: s390 port size(VARIABLE_SIZE); 8868 format %{ "MaxI $dst $src1,$src2\t MaxI const32" %} 8869 ins_encode %{ 8870 Label done; 8871 if ($dst$$Register != $src1$$Register) { 8872 __ z_lgfr($dst$$Register, $src1$$Register); 8873 } 8874 __ z_cfi($src1$$Register, $src2$$constant); 8875 __ z_brh(done); 8876 __ z_lgfi($dst$$Register, $src2$$constant); 8877 __ bind(done); 8878 %} 8879 ins_pipe(pipe_class_dummy); 8880 %} 8881 8882 instruct z196_maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{ 8883 match(Set dst (MaxI src1 src2)); 8884 effect(KILL cr); 8885 predicate(VM_Version::has_LoadStoreConditional()); 8886 ins_cost(3 * DEFAULT_COST); 8887 // TODO: s390 port size(VARIABLE_SIZE); 8888 format %{ "MaxI $dst $src1,$src2\t MaxI const16 (z196 only)" %} 8889 ins_encode %{ 8890 Register Rdst = $dst$$Register; 8891 Register Rsrc1 = $src1$$Register; 8892 int Isrc2 = $src2$$constant; 8893 if (Rdst == Rsrc1) { 8894 __ load_const_optimized(Z_R0_scratch, Isrc2); 8895 __ z_chi(Rsrc1, Isrc2); 8896 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh); 8897 } else { 8898 __ load_const_optimized(Rdst, Isrc2); 8899 __ z_chi(Rsrc1, Isrc2); 8900 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh); 8901 } 8902 %} 8903 ins_pipe(pipe_class_dummy); 8904 %} 8905 8906 instruct maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{ 8907 match(Set dst (MaxI src1 src2)); 8908 effect(KILL cr); 8909 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8910 // TODO: s390 port size(VARIABLE_SIZE); 8911 format %{ "MaxI $dst $src1,$src2\t MaxI const16" %} 8912 ins_encode %{ 8913 Label done; 8914 if ($dst$$Register != $src1$$Register) { 8915 __ z_lgfr($dst$$Register, $src1$$Register); 8916 } 8917 __ z_chi($src1$$Register, $src2$$constant); 8918 __ z_brh(done); 8919 __ z_lghi($dst$$Register, $src2$$constant); 8920 __ bind(done); 8921 %} 8922 ins_pipe(pipe_class_dummy); 8923 %} 8924 8925 instruct z10_maxI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{ 8926 match(Set dst (MaxI src1 src2)); 8927 effect(KILL cr); 8928 predicate(VM_Version::has_CompareBranch()); 8929 ins_cost(DEFAULT_COST + BRANCH_COST); 8930 // TODO: s390 port size(VARIABLE_SIZE); 8931 format %{ "MaxI $dst $src1,$src2\t MaxI const8" %} 8932 ins_encode %{ 8933 Label done; 8934 if ($dst$$Register != $src1$$Register) { 8935 __ z_lgfr($dst$$Register, $src1$$Register); 8936 } 8937 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondHigh, done); 8938 __ z_lghi($dst$$Register, $src2$$constant); 8939 __ bind(done); 8940 %} 8941 ins_pipe(pipe_class_dummy); 8942 %} 8943 8944 //----------Abs--------------------------------------------------------------- 8945 8946 instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{ 8947 match(Set dst (AbsI src)); 8948 effect(KILL cr); 8949 ins_cost(DEFAULT_COST_LOW); 8950 // TODO: s390 port size(FIXED_SIZE); 8951 format %{ "LPR $dst, $src" %} 8952 opcode(LPR_ZOPC); 8953 ins_encode(z_rrform(dst, src)); 8954 ins_pipe(pipe_class_dummy); 8955 %} 8956 8957 instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{ 8958 match(Set dst (SubI zero (AbsI src))); 8959 effect(KILL cr); 8960 ins_cost(DEFAULT_COST_LOW); 8961 // TODO: s390 port size(FIXED_SIZE); 8962 format %{ "LNR $dst, $src" %} 8963 opcode(LNR_ZOPC); 8964 ins_encode(z_rrform(dst, src)); 8965 ins_pipe(pipe_class_dummy); 8966 %} 8967 8968 //----------Float Compares---------------------------------------------------- 8969 8970 // Compare floating, generate condition code. 8971 instruct cmpF_cc(flagsReg cr, regF src1, regF src2) %{ 8972 match(Set cr (CmpF src1 src2)); 8973 ins_cost(ALU_REG_COST); 8974 size(4); 8975 format %{ "FCMPcc $src1,$src2\t # float" %} 8976 ins_encode %{ __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); %} 8977 ins_pipe(pipe_class_dummy); 8978 %} 8979 8980 instruct cmpD_cc(flagsReg cr, regD src1, regD src2) %{ 8981 match(Set cr (CmpD src1 src2)); 8982 ins_cost(ALU_REG_COST); 8983 size(4); 8984 format %{ "FCMPcc $src1,$src2 \t # double" %} 8985 ins_encode %{ __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); %} 8986 ins_pipe(pipe_class_dummy); 8987 %} 8988 8989 instruct cmpF_cc_mem(flagsReg cr, regF src1, memoryRX src2) %{ 8990 match(Set cr (CmpF src1 (LoadF src2))); 8991 ins_cost(ALU_MEMORY_COST); 8992 size(6); 8993 format %{ "FCMPcc_mem $src1,$src2\t # floatMemory" %} 8994 opcode(CEB_ZOPC); 8995 ins_encode(z_form_rt_memFP(src1, src2)); 8996 ins_pipe(pipe_class_dummy); 8997 %} 8998 8999 instruct cmpD_cc_mem(flagsReg cr, regD src1, memoryRX src2) %{ 9000 match(Set cr (CmpD src1 (LoadD src2))); 9001 ins_cost(ALU_MEMORY_COST); 9002 size(6); 9003 format %{ "DCMPcc_mem $src1,$src2\t # doubleMemory" %} 9004 opcode(CDB_ZOPC); 9005 ins_encode(z_form_rt_memFP(src1, src2)); 9006 ins_pipe(pipe_class_dummy); 9007 %} 9008 9009 // Compare floating, generate condition code 9010 instruct cmpF0_cc(flagsReg cr, regF src1, immFpm0 src2) %{ 9011 match(Set cr (CmpF src1 src2)); 9012 ins_cost(DEFAULT_COST); 9013 size(4); 9014 format %{ "LTEBR $src1,$src1\t # float" %} 9015 opcode(LTEBR_ZOPC); 9016 ins_encode(z_rreform(src1, src1)); 9017 ins_pipe(pipe_class_dummy); 9018 %} 9019 9020 instruct cmpD0_cc(flagsReg cr, regD src1, immDpm0 src2) %{ 9021 match(Set cr (CmpD src1 src2)); 9022 ins_cost(DEFAULT_COST); 9023 size(4); 9024 format %{ "LTDBR $src1,$src1 \t # double" %} 9025 opcode(LTDBR_ZOPC); 9026 ins_encode(z_rreform(src1, src1)); 9027 ins_pipe(pipe_class_dummy); 9028 %} 9029 9030 // Compare floating, generate -1,0,1 9031 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg cr) %{ 9032 match(Set dst (CmpF3 src1 src2)); 9033 effect(KILL cr); 9034 ins_cost(DEFAULT_COST * 5 + BRANCH_COST); 9035 size(24); 9036 format %{ "CmpF3 $dst,$src1,$src2" %} 9037 ins_encode %{ 9038 // compare registers 9039 __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); 9040 // Convert condition code into -1,0,1, where 9041 // -1 means unordered or less 9042 // 0 means equal 9043 // 1 means greater. 9044 if (VM_Version::has_LoadStoreConditional()) { 9045 Register one = Z_R0_scratch; 9046 Register minus_one = Z_R1_scratch; 9047 __ z_lghi(minus_one, -1); 9048 __ z_lghi(one, 1); 9049 __ z_lghi( $dst$$Register, 0); 9050 __ z_locgr($dst$$Register, one, Assembler::bcondHigh); 9051 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered); 9052 } else { 9053 Label done; 9054 __ clear_reg($dst$$Register, true, false); 9055 __ z_bre(done); 9056 __ z_lhi($dst$$Register, 1); 9057 __ z_brh(done); 9058 __ z_lhi($dst$$Register, -1); 9059 __ bind(done); 9060 } 9061 %} 9062 ins_pipe(pipe_class_dummy); 9063 %} 9064 9065 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg cr) %{ 9066 match(Set dst (CmpD3 src1 src2)); 9067 effect(KILL cr); 9068 ins_cost(DEFAULT_COST * 5 + BRANCH_COST); 9069 size(24); 9070 format %{ "CmpD3 $dst,$src1,$src2" %} 9071 ins_encode %{ 9072 // compare registers 9073 __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); 9074 // Convert condition code into -1,0,1, where 9075 // -1 means unordered or less 9076 // 0 means equal 9077 // 1 means greater. 9078 if (VM_Version::has_LoadStoreConditional()) { 9079 Register one = Z_R0_scratch; 9080 Register minus_one = Z_R1_scratch; 9081 __ z_lghi(minus_one, -1); 9082 __ z_lghi(one, 1); 9083 __ z_lghi( $dst$$Register, 0); 9084 __ z_locgr($dst$$Register, one, Assembler::bcondHigh); 9085 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered); 9086 } else { 9087 Label done; 9088 // indicate unused result 9089 (void) __ clear_reg($dst$$Register, true, false); 9090 __ z_bre(done); 9091 __ z_lhi($dst$$Register, 1); 9092 __ z_brh(done); 9093 __ z_lhi($dst$$Register, -1); 9094 __ bind(done); 9095 } 9096 %} 9097 ins_pipe(pipe_class_dummy); 9098 %} 9099 9100 //----------Branches--------------------------------------------------------- 9101 // Jump 9102 9103 // Direct Branch. 9104 instruct branch(label labl) %{ 9105 match(Goto); 9106 effect(USE labl); 9107 ins_cost(BRANCH_COST); 9108 size(4); 9109 format %{ "BRU $labl" %} 9110 ins_encode(z_enc_bru(labl)); 9111 ins_pipe(pipe_class_dummy); 9112 // If set to 1 this indicates that the current instruction is a 9113 // short variant of a long branch. This avoids using this 9114 // instruction in first-pass matching. It will then only be used in 9115 // the `Shorten_branches' pass. 9116 ins_short_branch(1); 9117 %} 9118 9119 // Direct Branch. 9120 instruct branchFar(label labl) %{ 9121 match(Goto); 9122 effect(USE labl); 9123 ins_cost(BRANCH_COST); 9124 size(6); 9125 format %{ "BRUL $labl" %} 9126 ins_encode(z_enc_brul(labl)); 9127 ins_pipe(pipe_class_dummy); 9128 // This is not a short variant of a branch, but the long variant. 9129 ins_short_branch(0); 9130 %} 9131 9132 // Conditional Near Branch 9133 instruct branchCon(cmpOp cmp, flagsReg cr, label lbl) %{ 9134 // Same match rule as `branchConFar'. 9135 match(If cmp cr); 9136 effect(USE lbl); 9137 ins_cost(BRANCH_COST); 9138 size(4); 9139 format %{ "branch_con_short,$cmp $cr, $lbl" %} 9140 ins_encode(z_enc_branch_con_short(cmp, lbl)); 9141 ins_pipe(pipe_class_dummy); 9142 // If set to 1 this indicates that the current instruction is a 9143 // short variant of a long branch. This avoids using this 9144 // instruction in first-pass matching. It will then only be used in 9145 // the `Shorten_branches' pass. 9146 ins_short_branch(1); 9147 %} 9148 9149 // This is for cases when the z/Architecture conditional branch instruction 9150 // does not reach far enough. So we emit a far branch here, which is 9151 // more expensive. 9152 // 9153 // Conditional Far Branch 9154 instruct branchConFar(cmpOp cmp, flagsReg cr, label lbl) %{ 9155 // Same match rule as `branchCon'. 9156 match(If cmp cr); 9157 effect(USE cr, USE lbl); 9158 // Make more expensive to prefer compare_and_branch over separate instructions. 9159 ins_cost(2 * BRANCH_COST); 9160 size(6); 9161 format %{ "branch_con_far,$cmp $cr, $lbl" %} 9162 ins_encode(z_enc_branch_con_far(cmp, lbl)); 9163 ins_pipe(pipe_class_dummy); 9164 // This is not a short variant of a branch, but the long variant.. 9165 ins_short_branch(0); 9166 %} 9167 9168 instruct branchLoopEnd(cmpOp cmp, flagsReg cr, label labl) %{ 9169 match(CountedLoopEnd cmp cr); 9170 effect(USE labl); 9171 ins_cost(BRANCH_COST); 9172 size(4); 9173 format %{ "branch_con_short,$cmp $labl\t # counted loop end" %} 9174 ins_encode(z_enc_branch_con_short(cmp, labl)); 9175 ins_pipe(pipe_class_dummy); 9176 // If set to 1 this indicates that the current instruction is a 9177 // short variant of a long branch. This avoids using this 9178 // instruction in first-pass matching. It will then only be used in 9179 // the `Shorten_branches' pass. 9180 ins_short_branch(1); 9181 %} 9182 9183 instruct branchLoopEndFar(cmpOp cmp, flagsReg cr, label labl) %{ 9184 match(CountedLoopEnd cmp cr); 9185 effect(USE labl); 9186 ins_cost(BRANCH_COST); 9187 size(6); 9188 format %{ "branch_con_far,$cmp $labl\t # counted loop end" %} 9189 ins_encode(z_enc_branch_con_far(cmp, labl)); 9190 ins_pipe(pipe_class_dummy); 9191 // This is not a short variant of a branch, but the long variant. 9192 ins_short_branch(0); 9193 %} 9194 9195 //----------Compare and Branch (short distance)------------------------------ 9196 9197 // INT REG operands for loop counter processing. 9198 instruct testAndBranchLoopEnd_Reg(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9199 match(CountedLoopEnd boolnode (CmpI src1 src2)); 9200 effect(USE labl, KILL cr); 9201 predicate(VM_Version::has_CompareBranch()); 9202 ins_cost(BRANCH_COST); 9203 // TODO: s390 port size(FIXED_SIZE); 9204 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %} 9205 opcode(CRJ_ZOPC); 9206 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9207 ins_pipe(pipe_class_dummy); 9208 ins_short_branch(1); 9209 %} 9210 9211 // INT REG operands. 9212 instruct cmpb_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9213 match(If boolnode (CmpI src1 src2)); 9214 effect(USE labl, KILL cr); 9215 predicate(VM_Version::has_CompareBranch()); 9216 ins_cost(BRANCH_COST); 9217 // TODO: s390 port size(FIXED_SIZE); 9218 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9219 opcode(CRJ_ZOPC); 9220 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9221 ins_pipe(pipe_class_dummy); 9222 ins_short_branch(1); 9223 %} 9224 9225 // Unsigned INT REG operands 9226 instruct cmpbU_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9227 match(If boolnode (CmpU src1 src2)); 9228 effect(USE labl, KILL cr); 9229 predicate(VM_Version::has_CompareBranch()); 9230 ins_cost(BRANCH_COST); 9231 // TODO: s390 port size(FIXED_SIZE); 9232 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9233 opcode(CLRJ_ZOPC); 9234 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9235 ins_pipe(pipe_class_dummy); 9236 ins_short_branch(1); 9237 %} 9238 9239 // LONG REG operands 9240 instruct cmpb_RegL(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{ 9241 match(If boolnode (CmpL src1 src2)); 9242 effect(USE labl, KILL cr); 9243 predicate(VM_Version::has_CompareBranch()); 9244 ins_cost(BRANCH_COST); 9245 // TODO: s390 port size(FIXED_SIZE); 9246 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9247 opcode(CGRJ_ZOPC); 9248 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9249 ins_pipe(pipe_class_dummy); 9250 ins_short_branch(1); 9251 %} 9252 9253 // PTR REG operands 9254 9255 // Separate rules for regular and narrow oops. ADLC can't recognize 9256 // rules with polymorphic operands to be sisters -> shorten_branches 9257 // will not shorten. 9258 9259 instruct cmpb_RegPP(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{ 9260 match(If boolnode (CmpP src1 src2)); 9261 effect(USE labl, KILL cr); 9262 predicate(VM_Version::has_CompareBranch()); 9263 ins_cost(BRANCH_COST); 9264 // TODO: s390 port size(FIXED_SIZE); 9265 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9266 opcode(CLGRJ_ZOPC); 9267 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9268 ins_pipe(pipe_class_dummy); 9269 ins_short_branch(1); 9270 %} 9271 9272 instruct cmpb_RegNN(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{ 9273 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); 9274 effect(USE labl, KILL cr); 9275 predicate(VM_Version::has_CompareBranch()); 9276 ins_cost(BRANCH_COST); 9277 // TODO: s390 port size(FIXED_SIZE); 9278 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9279 opcode(CLGRJ_ZOPC); 9280 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9281 ins_pipe(pipe_class_dummy); 9282 ins_short_branch(1); 9283 %} 9284 9285 // INT REG/IMM operands for loop counter processing 9286 instruct testAndBranchLoopEnd_Imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{ 9287 match(CountedLoopEnd boolnode (CmpI src1 src2)); 9288 effect(USE labl, KILL cr); 9289 predicate(VM_Version::has_CompareBranch()); 9290 ins_cost(BRANCH_COST); 9291 // TODO: s390 port size(FIXED_SIZE); 9292 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %} 9293 opcode(CIJ_ZOPC); 9294 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9295 ins_pipe(pipe_class_dummy); 9296 ins_short_branch(1); 9297 %} 9298 9299 // INT REG/IMM operands 9300 instruct cmpb_RegI_imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{ 9301 match(If boolnode (CmpI src1 src2)); 9302 effect(USE labl, KILL cr); 9303 predicate(VM_Version::has_CompareBranch()); 9304 ins_cost(BRANCH_COST); 9305 // TODO: s390 port size(FIXED_SIZE); 9306 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9307 opcode(CIJ_ZOPC); 9308 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9309 ins_pipe(pipe_class_dummy); 9310 ins_short_branch(1); 9311 %} 9312 9313 // INT REG/IMM operands 9314 instruct cmpbU_RegI_imm(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{ 9315 match(If boolnode (CmpU src1 src2)); 9316 effect(USE labl, KILL cr); 9317 predicate(VM_Version::has_CompareBranch()); 9318 ins_cost(BRANCH_COST); 9319 // TODO: s390 port size(FIXED_SIZE); 9320 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9321 opcode(CLIJ_ZOPC); 9322 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9323 ins_pipe(pipe_class_dummy); 9324 ins_short_branch(1); 9325 %} 9326 9327 // LONG REG/IMM operands 9328 instruct cmpb_RegL_imm(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{ 9329 match(If boolnode (CmpL src1 src2)); 9330 effect(USE labl, KILL cr); 9331 predicate(VM_Version::has_CompareBranch()); 9332 ins_cost(BRANCH_COST); 9333 // TODO: s390 port size(FIXED_SIZE); 9334 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9335 opcode(CGIJ_ZOPC); 9336 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9337 ins_pipe(pipe_class_dummy); 9338 ins_short_branch(1); 9339 %} 9340 9341 // PTR REG-imm operands 9342 9343 // Separate rules for regular and narrow oops. ADLC can't recognize 9344 // rules with polymorphic operands to be sisters -> shorten_branches 9345 // will not shorten. 9346 9347 instruct cmpb_RegP_immP(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{ 9348 match(If boolnode (CmpP src1 src2)); 9349 effect(USE labl, KILL cr); 9350 predicate(VM_Version::has_CompareBranch()); 9351 ins_cost(BRANCH_COST); 9352 // TODO: s390 port size(FIXED_SIZE); 9353 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9354 opcode(CLGIJ_ZOPC); 9355 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9356 ins_pipe(pipe_class_dummy); 9357 ins_short_branch(1); 9358 %} 9359 9360 // Compare against zero only, do not mix N and P oops (encode/decode required). 9361 instruct cmpb_RegN_immP0(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{ 9362 match(If boolnode (CmpP (DecodeN src1) src2)); 9363 effect(USE labl, KILL cr); 9364 predicate(VM_Version::has_CompareBranch()); 9365 ins_cost(BRANCH_COST); 9366 // TODO: s390 port size(FIXED_SIZE); 9367 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9368 opcode(CLGIJ_ZOPC); 9369 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9370 ins_pipe(pipe_class_dummy); 9371 ins_short_branch(1); 9372 %} 9373 9374 instruct cmpb_RegN_imm(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{ 9375 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); 9376 effect(USE labl, KILL cr); 9377 predicate(VM_Version::has_CompareBranch()); 9378 ins_cost(BRANCH_COST); 9379 // TODO: s390 port size(FIXED_SIZE); 9380 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9381 opcode(CLGIJ_ZOPC); 9382 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9383 ins_pipe(pipe_class_dummy); 9384 ins_short_branch(1); 9385 %} 9386 9387 9388 //----------Compare and Branch (far distance)------------------------------ 9389 9390 // INT REG operands for loop counter processing 9391 instruct testAndBranchLoopEnd_RegFar(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9392 match(CountedLoopEnd boolnode (CmpI src1 src2)); 9393 effect(USE labl, KILL cr); 9394 predicate(VM_Version::has_CompareBranch()); 9395 ins_cost(BRANCH_COST+DEFAULT_COST); 9396 // TODO: s390 port size(FIXED_SIZE); 9397 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %} 9398 opcode(CR_ZOPC, BRCL_ZOPC); 9399 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9400 ins_pipe(pipe_class_dummy); 9401 ins_short_branch(0); 9402 %} 9403 9404 // INT REG operands 9405 instruct cmpb_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9406 match(If boolnode (CmpI src1 src2)); 9407 effect(USE labl, KILL cr); 9408 predicate(VM_Version::has_CompareBranch()); 9409 ins_cost(BRANCH_COST+DEFAULT_COST); 9410 // TODO: s390 port size(FIXED_SIZE); 9411 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9412 opcode(CR_ZOPC, BRCL_ZOPC); 9413 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9414 ins_pipe(pipe_class_dummy); 9415 ins_short_branch(0); 9416 %} 9417 9418 // INT REG operands 9419 instruct cmpbU_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9420 match(If boolnode (CmpU src1 src2)); 9421 effect(USE labl, KILL cr); 9422 predicate(VM_Version::has_CompareBranch()); 9423 ins_cost(BRANCH_COST+DEFAULT_COST); 9424 // TODO: s390 port size(FIXED_SIZE); 9425 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9426 opcode(CLR_ZOPC, BRCL_ZOPC); 9427 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9428 ins_pipe(pipe_class_dummy); 9429 ins_short_branch(0); 9430 %} 9431 9432 // LONG REG operands 9433 instruct cmpb_RegL_Far(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{ 9434 match(If boolnode (CmpL src1 src2)); 9435 effect(USE labl, KILL cr); 9436 predicate(VM_Version::has_CompareBranch()); 9437 ins_cost(BRANCH_COST+DEFAULT_COST); 9438 // TODO: s390 port size(FIXED_SIZE); 9439 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9440 opcode(CGR_ZOPC, BRCL_ZOPC); 9441 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9442 ins_pipe(pipe_class_dummy); 9443 ins_short_branch(0); 9444 %} 9445 9446 // PTR REG operands 9447 9448 // Separate rules for regular and narrow oops. ADLC can't recognize 9449 // rules with polymorphic operands to be sisters -> shorten_branches 9450 // will not shorten. 9451 9452 instruct cmpb_RegPP_Far(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{ 9453 match(If boolnode (CmpP src1 src2)); 9454 effect(USE labl, KILL cr); 9455 predicate(VM_Version::has_CompareBranch()); 9456 ins_cost(BRANCH_COST+DEFAULT_COST); 9457 // TODO: s390 port size(FIXED_SIZE); 9458 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9459 opcode(CLGR_ZOPC, BRCL_ZOPC); 9460 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9461 ins_pipe(pipe_class_dummy); 9462 ins_short_branch(0); 9463 %} 9464 9465 instruct cmpb_RegNN_Far(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{ 9466 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); 9467 effect(USE labl, KILL cr); 9468 predicate(VM_Version::has_CompareBranch()); 9469 ins_cost(BRANCH_COST+DEFAULT_COST); 9470 // TODO: s390 port size(FIXED_SIZE); 9471 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9472 opcode(CLGR_ZOPC, BRCL_ZOPC); 9473 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9474 ins_pipe(pipe_class_dummy); 9475 ins_short_branch(0); 9476 %} 9477 9478 // INT REG/IMM operands for loop counter processing 9479 instruct testAndBranchLoopEnd_ImmFar(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{ 9480 match(CountedLoopEnd boolnode (CmpI src1 src2)); 9481 effect(USE labl, KILL cr); 9482 predicate(VM_Version::has_CompareBranch()); 9483 ins_cost(BRANCH_COST+DEFAULT_COST); 9484 // TODO: s390 port size(FIXED_SIZE); 9485 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %} 9486 opcode(CHI_ZOPC, BRCL_ZOPC); 9487 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9488 ins_pipe(pipe_class_dummy); 9489 ins_short_branch(0); 9490 %} 9491 9492 // INT REG/IMM operands 9493 instruct cmpb_RegI_imm_Far(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{ 9494 match(If boolnode (CmpI src1 src2)); 9495 effect(USE labl, KILL cr); 9496 predicate(VM_Version::has_CompareBranch()); 9497 ins_cost(BRANCH_COST+DEFAULT_COST); 9498 // TODO: s390 port size(FIXED_SIZE); 9499 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9500 opcode(CHI_ZOPC, BRCL_ZOPC); 9501 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9502 ins_pipe(pipe_class_dummy); 9503 ins_short_branch(0); 9504 %} 9505 9506 // INT REG/IMM operands 9507 instruct cmpbU_RegI_imm_Far(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{ 9508 match(If boolnode (CmpU src1 src2)); 9509 effect(USE labl, KILL cr); 9510 predicate(VM_Version::has_CompareBranch()); 9511 ins_cost(BRANCH_COST+DEFAULT_COST); 9512 // TODO: s390 port size(FIXED_SIZE); 9513 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9514 opcode(CLFI_ZOPC, BRCL_ZOPC); 9515 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9516 ins_pipe(pipe_class_dummy); 9517 ins_short_branch(0); 9518 %} 9519 9520 // LONG REG/IMM operands 9521 instruct cmpb_RegL_imm_Far(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{ 9522 match(If boolnode (CmpL src1 src2)); 9523 effect(USE labl, KILL cr); 9524 predicate(VM_Version::has_CompareBranch()); 9525 ins_cost(BRANCH_COST+DEFAULT_COST); 9526 // TODO: s390 port size(FIXED_SIZE); 9527 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9528 opcode(CGHI_ZOPC, BRCL_ZOPC); 9529 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9530 ins_pipe(pipe_class_dummy); 9531 ins_short_branch(0); 9532 %} 9533 9534 // PTR REG-imm operands 9535 9536 // Separate rules for regular and narrow oops. ADLC can't recognize 9537 // rules with polymorphic operands to be sisters -> shorten_branches 9538 // will not shorten. 9539 9540 instruct cmpb_RegP_immP_Far(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{ 9541 match(If boolnode (CmpP src1 src2)); 9542 effect(USE labl, KILL cr); 9543 predicate(VM_Version::has_CompareBranch()); 9544 ins_cost(BRANCH_COST+DEFAULT_COST); 9545 // TODO: s390 port size(FIXED_SIZE); 9546 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9547 opcode(CLGFI_ZOPC, BRCL_ZOPC); 9548 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9549 ins_pipe(pipe_class_dummy); 9550 ins_short_branch(0); 9551 %} 9552 9553 // Compare against zero only, do not mix N and P oops (encode/decode required). 9554 instruct cmpb_RegN_immP0_Far(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{ 9555 match(If boolnode (CmpP (DecodeN src1) src2)); 9556 effect(USE labl, KILL cr); 9557 predicate(VM_Version::has_CompareBranch()); 9558 ins_cost(BRANCH_COST+DEFAULT_COST); 9559 // TODO: s390 port size(FIXED_SIZE); 9560 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9561 opcode(CLGFI_ZOPC, BRCL_ZOPC); 9562 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9563 ins_pipe(pipe_class_dummy); 9564 ins_short_branch(0); 9565 %} 9566 9567 instruct cmpb_RegN_immN_Far(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{ 9568 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); 9569 effect(USE labl, KILL cr); 9570 predicate(VM_Version::has_CompareBranch()); 9571 ins_cost(BRANCH_COST+DEFAULT_COST); 9572 // TODO: s390 port size(FIXED_SIZE); 9573 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9574 opcode(CLGFI_ZOPC, BRCL_ZOPC); 9575 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9576 ins_pipe(pipe_class_dummy); 9577 ins_short_branch(0); 9578 %} 9579 9580 // ============================================================================ 9581 // Long Compare 9582 9583 // Due to a shortcoming in the ADLC, it mixes up expressions like: 9584 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9585 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9586 // are collapsed internally in the ADLC's dfa-gen code. The match for 9587 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9588 // foo match ends up with the wrong leaf. One fix is to not match both 9589 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 9590 // both forms beat the trinary form of long-compare and both are very useful 9591 // on platforms which have few registers. 9592 9593 // Manifest a CmpL3 result in an integer register. Very painful. 9594 // This is the test to avoid. 9595 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr) %{ 9596 match(Set dst (CmpL3 src1 src2)); 9597 effect(KILL cr); 9598 ins_cost(DEFAULT_COST * 5 + BRANCH_COST); 9599 size(24); 9600 format %{ "CmpL3 $dst,$src1,$src2" %} 9601 ins_encode %{ 9602 Label done; 9603 // compare registers 9604 __ z_cgr($src1$$Register, $src2$$Register); 9605 // Convert condition code into -1,0,1, where 9606 // -1 means less 9607 // 0 means equal 9608 // 1 means greater. 9609 if (VM_Version::has_LoadStoreConditional()) { 9610 Register one = Z_R0_scratch; 9611 Register minus_one = Z_R1_scratch; 9612 __ z_lghi(minus_one, -1); 9613 __ z_lghi(one, 1); 9614 __ z_lghi( $dst$$Register, 0); 9615 __ z_locgr($dst$$Register, one, Assembler::bcondHigh); 9616 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLow); 9617 } else { 9618 __ clear_reg($dst$$Register, true, false); 9619 __ z_bre(done); 9620 __ z_lhi($dst$$Register, 1); 9621 __ z_brh(done); 9622 __ z_lhi($dst$$Register, -1); 9623 } 9624 __ bind(done); 9625 %} 9626 ins_pipe(pipe_class_dummy); 9627 %} 9628 9629 // ============================================================================ 9630 // Safepoint Instruction 9631 9632 instruct safePoint() %{ 9633 match(SafePoint); 9634 predicate(false); 9635 // TODO: s390 port size(FIXED_SIZE); 9636 format %{ "UNIMPLEMENTED Safepoint_ " %} 9637 ins_encode(enc_unimplemented()); 9638 ins_pipe(pipe_class_dummy); 9639 %} 9640 9641 instruct safePoint_poll(iRegP poll, flagsReg cr) %{ 9642 match(SafePoint poll); 9643 effect(USE poll, KILL cr); // R0 is killed, too. 9644 // TODO: s390 port size(FIXED_SIZE); 9645 format %{ "TM #0[,$poll],#111\t # Safepoint: poll for GC" %} 9646 ins_encode %{ 9647 // Mark the code position where the load from the safepoint 9648 // polling page was emitted as relocInfo::poll_type. 9649 __ relocate(relocInfo::poll_type); 9650 __ load_from_polling_page($poll$$Register); 9651 %} 9652 ins_pipe(pipe_class_dummy); 9653 %} 9654 9655 // ============================================================================ 9656 9657 // Call Instructions 9658 9659 // Call Java Static Instruction 9660 instruct CallStaticJavaDirect_dynTOC(method meth) %{ 9661 match(CallStaticJava); 9662 effect(USE meth); 9663 ins_cost(CALL_COST); 9664 // TODO: s390 port size(VARIABLE_SIZE); 9665 format %{ "CALL,static dynTOC $meth; ==> " %} 9666 ins_encode( z_enc_java_static_call(meth) ); 9667 ins_pipe(pipe_class_dummy); 9668 ins_alignment(2); 9669 %} 9670 9671 // Call Java Dynamic Instruction 9672 instruct CallDynamicJavaDirect_dynTOC(method meth) %{ 9673 match(CallDynamicJava); 9674 effect(USE meth); 9675 ins_cost(CALL_COST); 9676 // TODO: s390 port size(VARIABLE_SIZE); 9677 format %{ "CALL,dynamic dynTOC $meth; ==> " %} 9678 ins_encode(z_enc_java_dynamic_call(meth)); 9679 ins_pipe(pipe_class_dummy); 9680 ins_alignment(2); 9681 %} 9682 9683 // Call Runtime Instruction 9684 instruct CallRuntimeDirect(method meth) %{ 9685 match(CallRuntime); 9686 effect(USE meth); 9687 ins_cost(CALL_COST); 9688 // TODO: s390 port size(VARIABLE_SIZE); 9689 ins_num_consts(1); 9690 ins_alignment(2); 9691 format %{ "CALL,runtime" %} 9692 ins_encode( z_enc_java_to_runtime_call(meth) ); 9693 ins_pipe(pipe_class_dummy); 9694 %} 9695 9696 // Call runtime without safepoint - same as CallRuntime 9697 instruct CallLeafDirect(method meth) %{ 9698 match(CallLeaf); 9699 effect(USE meth); 9700 ins_cost(CALL_COST); 9701 // TODO: s390 port size(VARIABLE_SIZE); 9702 ins_num_consts(1); 9703 ins_alignment(2); 9704 format %{ "CALL,runtime leaf $meth" %} 9705 ins_encode( z_enc_java_to_runtime_call(meth) ); 9706 ins_pipe(pipe_class_dummy); 9707 %} 9708 9709 // Call runtime without safepoint - same as CallLeaf 9710 instruct CallLeafNoFPDirect(method meth) %{ 9711 match(CallLeafNoFP); 9712 effect(USE meth); 9713 ins_cost(CALL_COST); 9714 // TODO: s390 port size(VARIABLE_SIZE); 9715 ins_num_consts(1); 9716 format %{ "CALL,runtime leaf nofp $meth" %} 9717 ins_encode( z_enc_java_to_runtime_call(meth) ); 9718 ins_pipe(pipe_class_dummy); 9719 ins_alignment(2); 9720 %} 9721 9722 // Tail Call; Jump from runtime stub to Java code. 9723 // Also known as an 'interprocedural jump'. 9724 // Target of jump will eventually return to caller. 9725 // TailJump below removes the return address. 9726 instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_oop) %{ 9727 match(TailCall jump_target method_oop); 9728 ins_cost(CALL_COST); 9729 size(2); 9730 format %{ "Jmp $jump_target\t# $method_oop holds method oop" %} 9731 ins_encode %{ __ z_br($jump_target$$Register); %} 9732 ins_pipe(pipe_class_dummy); 9733 %} 9734 9735 // Return Instruction 9736 instruct Ret() %{ 9737 match(Return); 9738 size(2); 9739 format %{ "BR(Z_R14) // branch to link register" %} 9740 ins_encode %{ __ z_br(Z_R14); %} 9741 ins_pipe(pipe_class_dummy); 9742 %} 9743 9744 // Tail Jump; remove the return address; jump to target. 9745 // TailCall above leaves the return address around. 9746 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 9747 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 9748 // "restore" before this instruction (in Epilogue), we need to materialize it 9749 // in %i0. 9750 instruct tailjmpInd(iRegP jump_target, rarg1RegP ex_oop) %{ 9751 match(TailJump jump_target ex_oop); 9752 ins_cost(CALL_COST); 9753 size(8); 9754 format %{ "TailJump $jump_target" %} 9755 ins_encode %{ 9756 __ z_lg(Z_ARG2/* issuing pc */, _z_abi(return_pc), Z_SP); 9757 __ z_br($jump_target$$Register); 9758 %} 9759 ins_pipe(pipe_class_dummy); 9760 %} 9761 9762 // Create exception oop: created by stack-crawling runtime code. 9763 // Created exception is now available to this handler, and is setup 9764 // just prior to jumping to this handler. No code emitted. 9765 instruct CreateException(rarg1RegP ex_oop) %{ 9766 match(Set ex_oop (CreateEx)); 9767 ins_cost(0); 9768 size(0); 9769 format %{ "# exception oop; no code emitted" %} 9770 ins_encode(/*empty*/); 9771 ins_pipe(pipe_class_dummy); 9772 %} 9773 9774 // Rethrow exception: The exception oop will come in the first 9775 // argument position. Then JUMP (not call) to the rethrow stub code. 9776 instruct RethrowException() %{ 9777 match(Rethrow); 9778 ins_cost(CALL_COST); 9779 // TODO: s390 port size(VARIABLE_SIZE); 9780 format %{ "Jmp rethrow_stub" %} 9781 ins_encode %{ 9782 cbuf.set_insts_mark(); 9783 __ load_const_optimized(Z_R1_scratch, (address)OptoRuntime::rethrow_stub()); 9784 __ z_br(Z_R1_scratch); 9785 %} 9786 ins_pipe(pipe_class_dummy); 9787 %} 9788 9789 // Die now. 9790 instruct ShouldNotReachHere() %{ 9791 match(Halt); 9792 ins_cost(CALL_COST); 9793 size(2); 9794 format %{ "ILLTRAP; ShouldNotReachHere" %} 9795 ins_encode %{ __ z_illtrap(); %} 9796 ins_pipe(pipe_class_dummy); 9797 %} 9798 9799 // ============================================================================ 9800 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 9801 // array for an instance of the superklass. Set a hidden internal cache on a 9802 // hit (cache is checked with exposed code in gen_subtype_check()). Return 9803 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 9804 instruct partialSubtypeCheck(rarg1RegP index, rarg2RegP sub, rarg3RegP super, flagsReg pcc, 9805 rarg4RegP scratch1, rarg5RegP scratch2) %{ 9806 match(Set index (PartialSubtypeCheck sub super)); 9807 effect(KILL pcc, KILL scratch1, KILL scratch2); 9808 ins_cost(10 * DEFAULT_COST); 9809 size(12); 9810 format %{ " CALL PartialSubtypeCheck\n" %} 9811 ins_encode %{ 9812 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check()); 9813 __ load_const_optimized(Z_ARG4, stub_address); 9814 __ z_basr(Z_R14, Z_ARG4); 9815 %} 9816 ins_pipe(pipe_class_dummy); 9817 %} 9818 9819 instruct partialSubtypeCheck_vs_zero(flagsReg pcc, rarg2RegP sub, rarg3RegP super, immP0 zero, 9820 rarg1RegP index, rarg4RegP scratch1, rarg5RegP scratch2) %{ 9821 match(Set pcc (CmpI (PartialSubtypeCheck sub super) zero)); 9822 effect(KILL scratch1, KILL scratch2, KILL index); 9823 ins_cost(10 * DEFAULT_COST); 9824 // TODO: s390 port size(FIXED_SIZE); 9825 format %{ "CALL PartialSubtypeCheck_vs_zero\n" %} 9826 ins_encode %{ 9827 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check()); 9828 __ load_const_optimized(Z_ARG4, stub_address); 9829 __ z_basr(Z_R14, Z_ARG4); 9830 %} 9831 ins_pipe(pipe_class_dummy); 9832 %} 9833 9834 // ============================================================================ 9835 // inlined locking and unlocking 9836 9837 instruct cmpFastLock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{ 9838 match(Set pcc (FastLock oop box)); 9839 effect(TEMP tmp1, TEMP tmp2); 9840 ins_cost(100); 9841 // TODO: s390 port size(VARIABLE_SIZE); // Uses load_const_optimized. 9842 format %{ "FASTLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %} 9843 ins_encode %{ __ compiler_fast_lock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register, 9844 UseBiasedLocking && !UseOptoBiasInlining); %} 9845 ins_pipe(pipe_class_dummy); 9846 %} 9847 9848 instruct cmpFastUnlock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{ 9849 match(Set pcc (FastUnlock oop box)); 9850 effect(TEMP tmp1, TEMP tmp2); 9851 ins_cost(100); 9852 // TODO: s390 port size(FIXED_SIZE); // emitted code depends on UseBiasedLocking being on/off. 9853 format %{ "FASTUNLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %} 9854 ins_encode %{ __ compiler_fast_unlock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register, 9855 UseBiasedLocking && !UseOptoBiasInlining); %} 9856 ins_pipe(pipe_class_dummy); 9857 %} 9858 9859 instruct inlineCallClearArrayConst(SSlenDW cnt, iRegP_N2P base, Universe dummy, flagsReg cr) %{ 9860 match(Set dummy (ClearArray cnt base)); 9861 effect(KILL cr); 9862 ins_cost(100); 9863 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to varying #instructions. 9864 format %{ "ClearArrayConst $cnt,$base" %} 9865 ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %} 9866 ins_pipe(pipe_class_dummy); 9867 %} 9868 9869 instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, revenRegL srcA, roddRegL srcL, flagsReg cr) %{ 9870 match(Set dummy (ClearArray cnt base)); 9871 effect(TEMP srcA, TEMP srcL, KILL cr); // R0, R1 are killed, too. 9872 ins_cost(200); 9873 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to optimized constant loader. 9874 format %{ "ClearArrayConstBig $cnt,$base" %} 9875 ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $srcA$$Register, $srcL$$Register); %} 9876 ins_pipe(pipe_class_dummy); 9877 %} 9878 9879 instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, revenRegL srcA, roddRegL srcL, flagsReg cr) %{ 9880 match(Set dummy (ClearArray cnt base)); 9881 effect(TEMP srcA, TEMP srcL, KILL cr); // R0, R1 are killed, too. 9882 ins_cost(300); 9883 // TODO: s390 port size(FIXED_SIZE); // z/Architecture: emitted code depends on PreferLAoverADD being on/off. 9884 format %{ "ClearArrayVar $cnt,$base" %} 9885 ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $srcA$$Register, $srcL$$Register); %} 9886 ins_pipe(pipe_class_dummy); 9887 %} 9888 9889 // ============================================================================ 9890 // CompactStrings 9891 9892 // String equals 9893 instruct string_equalsL(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 9894 match(Set result (StrEquals (Binary str1 str2) cnt)); 9895 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 9896 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL); 9897 ins_cost(300); 9898 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %} 9899 ins_encode %{ 9900 __ array_equals(false, $str1$$Register, $str2$$Register, 9901 $cnt$$Register, $oddReg$$Register, $evenReg$$Register, 9902 $result$$Register, true /* byte */); 9903 %} 9904 ins_pipe(pipe_class_dummy); 9905 %} 9906 9907 instruct string_equalsU(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 9908 match(Set result (StrEquals (Binary str1 str2) cnt)); 9909 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 9910 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none); 9911 ins_cost(300); 9912 format %{ "String Equals char[] $str1,$str2,$cnt -> $result" %} 9913 ins_encode %{ 9914 __ array_equals(false, $str1$$Register, $str2$$Register, 9915 $cnt$$Register, $oddReg$$Register, $evenReg$$Register, 9916 $result$$Register, false /* byte */); 9917 %} 9918 ins_pipe(pipe_class_dummy); 9919 %} 9920 9921 instruct string_equals_imm(iRegP str1, iRegP str2, uimmI8 cnt, iRegI result, flagsReg cr) %{ 9922 match(Set result (StrEquals (Binary str1 str2) cnt)); 9923 effect(KILL cr); // R0 is killed, too. 9924 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU); 9925 ins_cost(100); 9926 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %} 9927 ins_encode %{ 9928 const int cnt_imm = $cnt$$constant; 9929 if (cnt_imm) { __ z_clc(0, cnt_imm - 1, $str1$$Register, 0, $str2$$Register); } 9930 __ z_lhi($result$$Register, 1); 9931 if (cnt_imm) { 9932 if (VM_Version::has_LoadStoreConditional()) { 9933 __ z_lhi(Z_R0_scratch, 0); 9934 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual); 9935 } else { 9936 Label Lskip; 9937 __ z_bre(Lskip); 9938 __ clear_reg($result$$Register); 9939 __ bind(Lskip); 9940 } 9941 } 9942 %} 9943 ins_pipe(pipe_class_dummy); 9944 %} 9945 9946 instruct string_equalsC_imm(iRegP str1, iRegP str2, immI8 cnt, iRegI result, flagsReg cr) %{ 9947 match(Set result (StrEquals (Binary str1 str2) cnt)); 9948 effect(KILL cr); // R0 is killed, too. 9949 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none); 9950 ins_cost(100); 9951 format %{ "String Equals $str1,$str2,$cnt -> $result" %} 9952 ins_encode %{ 9953 const int cnt_imm = $cnt$$constant; // positive immI8 (7 bits used) 9954 if (cnt_imm) { __ z_clc(0, (cnt_imm << 1) - 1, $str1$$Register, 0, $str2$$Register); } 9955 __ z_lhi($result$$Register, 1); 9956 if (cnt_imm) { 9957 if (VM_Version::has_LoadStoreConditional()) { 9958 __ z_lhi(Z_R0_scratch, 0); 9959 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual); 9960 } else { 9961 Label Lskip; 9962 __ z_bre(Lskip); 9963 __ clear_reg($result$$Register); 9964 __ bind(Lskip); 9965 } 9966 } 9967 %} 9968 ins_pipe(pipe_class_dummy); 9969 %} 9970 9971 // Array equals 9972 instruct array_equalsB(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 9973 match(Set result (AryEq ary1 ary2)); 9974 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 9975 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL); 9976 ins_cost(300); 9977 format %{ "Array Equals $ary1,$ary2 -> $result" %} 9978 ins_encode %{ 9979 __ array_equals(true, $ary1$$Register, $ary2$$Register, 9980 noreg, $oddReg$$Register, $evenReg$$Register, 9981 $result$$Register, true /* byte */); 9982 %} 9983 ins_pipe(pipe_class_dummy); 9984 %} 9985 9986 instruct array_equalsC(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 9987 match(Set result (AryEq ary1 ary2)); 9988 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 9989 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU); 9990 ins_cost(300); 9991 format %{ "Array Equals $ary1,$ary2 -> $result" %} 9992 ins_encode %{ 9993 __ array_equals(true, $ary1$$Register, $ary2$$Register, 9994 noreg, $oddReg$$Register, $evenReg$$Register, 9995 $result$$Register, false /* byte */); 9996 %} 9997 ins_pipe(pipe_class_dummy); 9998 %} 9999 10000 // String CompareTo 10001 instruct string_compareL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10002 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10003 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10004 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL); 10005 ins_cost(300); 10006 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %} 10007 ins_encode %{ 10008 __ string_compare($str1$$Register, $str2$$Register, 10009 $cnt1$$Register, $cnt2$$Register, 10010 $oddReg$$Register, $evenReg$$Register, 10011 $result$$Register, StrIntrinsicNode::LL); 10012 %} 10013 ins_pipe(pipe_class_dummy); 10014 %} 10015 10016 instruct string_compareU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10017 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10018 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10019 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrCompNode*)n)->encoding() == StrIntrinsicNode::none); 10020 ins_cost(300); 10021 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result" %} 10022 ins_encode %{ 10023 __ string_compare($str1$$Register, $str2$$Register, 10024 $cnt1$$Register, $cnt2$$Register, 10025 $oddReg$$Register, $evenReg$$Register, 10026 $result$$Register, StrIntrinsicNode::UU); 10027 %} 10028 ins_pipe(pipe_class_dummy); 10029 %} 10030 10031 instruct string_compareLU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10032 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10033 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10034 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU); 10035 ins_cost(300); 10036 format %{ "String Compare byte[],char[] $str1,$cnt1,$str2,$cnt2 -> $result" %} 10037 ins_encode %{ 10038 __ string_compare($str1$$Register, $str2$$Register, 10039 $cnt1$$Register, $cnt2$$Register, 10040 $oddReg$$Register, $evenReg$$Register, 10041 $result$$Register, StrIntrinsicNode::LU); 10042 %} 10043 ins_pipe(pipe_class_dummy); 10044 %} 10045 10046 instruct string_compareUL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10047 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10048 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10049 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL); 10050 ins_cost(300); 10051 format %{ "String Compare char[],byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %} 10052 ins_encode %{ 10053 __ string_compare($str2$$Register, $str1$$Register, 10054 $cnt2$$Register, $cnt1$$Register, 10055 $oddReg$$Register, $evenReg$$Register, 10056 $result$$Register, StrIntrinsicNode::UL); 10057 %} 10058 ins_pipe(pipe_class_dummy); 10059 %} 10060 10061 // String IndexOfChar 10062 instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10063 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch)); 10064 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10065 ins_cost(200); 10066 format %{ "String IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %} 10067 ins_encode %{ 10068 __ string_indexof_char($result$$Register, 10069 $haystack$$Register, $haycnt$$Register, 10070 $ch$$Register, 0 /* unused, ch is in register */, 10071 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/); 10072 %} 10073 ins_pipe(pipe_class_dummy); 10074 %} 10075 10076 instruct indexOf_imm1_U(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10077 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10078 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10079 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none); 10080 ins_cost(200); 10081 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %} 10082 ins_encode %{ 10083 immPOper *needleOper = (immPOper *)$needle; 10084 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 10085 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 10086 jchar chr; 10087 #ifdef VM_LITTLE_ENDIAN 10088 Unimplemented(); 10089 #else 10090 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) | 10091 ((jchar)(unsigned char)needle_values->element_value(1).as_byte()); 10092 #endif 10093 __ string_indexof_char($result$$Register, 10094 $haystack$$Register, $haycnt$$Register, 10095 noreg, chr, 10096 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/); 10097 %} 10098 ins_pipe(pipe_class_dummy); 10099 %} 10100 10101 instruct indexOf_imm1_L(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10102 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10103 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10104 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); 10105 ins_cost(200); 10106 format %{ "String IndexOf L [0..$haycnt]($haystack), [0]($needle) -> $result" %} 10107 ins_encode %{ 10108 immPOper *needleOper = (immPOper *)$needle; 10109 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 10110 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 10111 jchar chr = (jchar)needle_values->element_value(0).as_byte(); 10112 __ string_indexof_char($result$$Register, 10113 $haystack$$Register, $haycnt$$Register, 10114 noreg, chr, 10115 $oddReg$$Register, $evenReg$$Register, true /*is_byte*/); 10116 %} 10117 ins_pipe(pipe_class_dummy); 10118 %} 10119 10120 instruct indexOf_imm1_UL(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10121 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10122 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10123 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); 10124 ins_cost(200); 10125 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %} 10126 ins_encode %{ 10127 immPOper *needleOper = (immPOper *)$needle; 10128 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 10129 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 10130 jchar chr = (jchar)needle_values->element_value(0).as_byte(); 10131 __ string_indexof_char($result$$Register, 10132 $haystack$$Register, $haycnt$$Register, 10133 noreg, chr, 10134 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/); 10135 %} 10136 ins_pipe(pipe_class_dummy); 10137 %} 10138 10139 // String IndexOf 10140 instruct indexOf_imm_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10141 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 10142 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10143 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none); 10144 ins_cost(250); 10145 format %{ "String IndexOf U [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10146 ins_encode %{ 10147 __ string_indexof($result$$Register, 10148 $haystack$$Register, $haycnt$$Register, 10149 $needle$$Register, noreg, $needlecntImm$$constant, 10150 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU); 10151 %} 10152 ins_pipe(pipe_class_dummy); 10153 %} 10154 10155 instruct indexOf_imm_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10156 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 10157 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10158 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); 10159 ins_cost(250); 10160 format %{ "String IndexOf L [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10161 ins_encode %{ 10162 __ string_indexof($result$$Register, 10163 $haystack$$Register, $haycnt$$Register, 10164 $needle$$Register, noreg, $needlecntImm$$constant, 10165 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL); 10166 %} 10167 ins_pipe(pipe_class_dummy); 10168 %} 10169 10170 instruct indexOf_imm_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10171 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 10172 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10173 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); 10174 ins_cost(250); 10175 format %{ "String IndexOf UL [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10176 ins_encode %{ 10177 __ string_indexof($result$$Register, 10178 $haystack$$Register, $haycnt$$Register, 10179 $needle$$Register, noreg, $needlecntImm$$constant, 10180 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL); 10181 %} 10182 ins_pipe(pipe_class_dummy); 10183 %} 10184 10185 instruct indexOf_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10186 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10187 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10188 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none); 10189 ins_cost(300); 10190 format %{ "String IndexOf U [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10191 ins_encode %{ 10192 __ string_indexof($result$$Register, 10193 $haystack$$Register, $haycnt$$Register, 10194 $needle$$Register, $needlecnt$$Register, 0, 10195 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU); 10196 %} 10197 ins_pipe(pipe_class_dummy); 10198 %} 10199 10200 instruct indexOf_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10201 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10202 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10203 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); 10204 ins_cost(300); 10205 format %{ "String IndexOf L [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10206 ins_encode %{ 10207 __ string_indexof($result$$Register, 10208 $haystack$$Register, $haycnt$$Register, 10209 $needle$$Register, $needlecnt$$Register, 0, 10210 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL); 10211 %} 10212 ins_pipe(pipe_class_dummy); 10213 %} 10214 10215 instruct indexOf_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10216 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10217 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10218 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); 10219 ins_cost(300); 10220 format %{ "String IndexOf UL [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10221 ins_encode %{ 10222 __ string_indexof($result$$Register, 10223 $haystack$$Register, $haycnt$$Register, 10224 $needle$$Register, $needlecnt$$Register, 0, 10225 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL); 10226 %} 10227 ins_pipe(pipe_class_dummy); 10228 %} 10229 10230 // char[] to byte[] compression 10231 instruct string_compress(iRegP src, rarg5RegP dst, iRegI result, roddRegI len, revenRegI evenReg, iRegI tmp, flagsReg cr) %{ 10232 match(Set result (StrCompressedCopy src (Binary dst len))); 10233 effect(TEMP_DEF result, USE_KILL dst, USE_KILL len, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too. 10234 ins_cost(300); 10235 format %{ "String Compress $src->$dst($len) -> $result" %} 10236 ins_encode %{ 10237 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register, 10238 $evenReg$$Register, $tmp$$Register); 10239 %} 10240 ins_pipe(pipe_class_dummy); 10241 %} 10242 10243 // byte[] to char[] inflation. trot implementation is shorter, but slower than the unrolled icm(h) loop. 10244 //instruct string_inflate_trot(Universe dummy, iRegP src, revenRegP dst, roddRegI len, iRegI tmp, flagsReg cr) %{ 10245 // match(Set dummy (StrInflatedCopy src (Binary dst len))); 10246 // effect(USE_KILL dst, USE_KILL len, TEMP tmp, KILL cr); // R0, R1 are killed, too. 10247 // predicate(VM_Version::has_ETF2Enhancements()); 10248 // ins_cost(300); 10249 // format %{ "String Inflate (trot) $dst,$src($len)" %} 10250 // ins_encode %{ 10251 // __ string_inflate_trot($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register); 10252 // %} 10253 // ins_pipe(pipe_class_dummy); 10254 //%} 10255 10256 // byte[] to char[] inflation 10257 instruct string_inflate(Universe dummy, rarg5RegP src, iRegP dst, roddRegI len, revenRegI evenReg, iRegI tmp, flagsReg cr) %{ 10258 match(Set dummy (StrInflatedCopy src (Binary dst len))); 10259 effect(USE_KILL src, USE_KILL len, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too. 10260 ins_cost(300); 10261 format %{ "String Inflate $src->$dst($len)" %} 10262 ins_encode %{ 10263 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $evenReg$$Register, $tmp$$Register); 10264 %} 10265 ins_pipe(pipe_class_dummy); 10266 %} 10267 10268 // StringCoding.java intrinsics 10269 instruct has_negatives(rarg5RegP ary1, iRegI len, iRegI result, roddRegI oddReg, revenRegI evenReg, iRegI tmp, flagsReg cr) %{ 10270 match(Set result (HasNegatives ary1 len)); 10271 effect(TEMP_DEF result, USE_KILL ary1, TEMP oddReg, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too. 10272 ins_cost(300); 10273 format %{ "has negatives byte[] $ary1($len) -> $result" %} 10274 ins_encode %{ 10275 __ has_negatives($result$$Register, $ary1$$Register, $len$$Register, 10276 $oddReg$$Register, $evenReg$$Register, $tmp$$Register); 10277 %} 10278 ins_pipe(pipe_class_dummy); 10279 %} 10280 10281 // encode char[] to byte[] in ISO_8859_1 10282 instruct encode_iso_array(rarg5RegP src, iRegP dst, iRegI result, roddRegI len, revenRegI evenReg, iRegI tmp, iRegI tmp2, flagsReg cr) %{ 10283 match(Set result (EncodeISOArray src (Binary dst len))); 10284 effect(TEMP_DEF result, USE_KILL src, USE_KILL len, TEMP evenReg, TEMP tmp, TEMP tmp2, KILL cr); // R0, R1 are killed, too. 10285 ins_cost(300); 10286 format %{ "Encode array $src->$dst($len) -> $result" %} 10287 ins_encode %{ 10288 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register, 10289 $evenReg$$Register, $tmp$$Register, $tmp2$$Register); 10290 %} 10291 ins_pipe(pipe_class_dummy); 10292 %} 10293 10294 10295 //----------PEEPHOLE RULES----------------------------------------------------- 10296 // These must follow all instruction definitions as they use the names 10297 // defined in the instructions definitions. 10298 // 10299 // peepmatch (root_instr_name [preceeding_instruction]*); 10300 // 10301 // peepconstraint %{ 10302 // (instruction_number.operand_name relational_op instruction_number.operand_name 10303 // [, ...]); 10304 // // instruction numbers are zero-based using left to right order in peepmatch 10305 // 10306 // peepreplace (instr_name([instruction_number.operand_name]*)); 10307 // // provide an instruction_number.operand_name for each operand that appears 10308 // // in the replacement instruction's match rule 10309 // 10310 // ---------VM FLAGS--------------------------------------------------------- 10311 // 10312 // All peephole optimizations can be turned off using -XX:-OptoPeephole 10313 // 10314 // Each peephole rule is given an identifying number starting with zero and 10315 // increasing by one in the order seen by the parser. An individual peephole 10316 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 10317 // on the command-line. 10318 // 10319 // ---------CURRENT LIMITATIONS---------------------------------------------- 10320 // 10321 // Only match adjacent instructions in same basic block 10322 // Only equality constraints 10323 // Only constraints between operands, not (0.dest_reg == EAX_enc) 10324 // Only one replacement instruction 10325 // 10326 // ---------EXAMPLE---------------------------------------------------------- 10327 // 10328 // // pertinent parts of existing instructions in architecture description 10329 // instruct movI(eRegI dst, eRegI src) %{ 10330 // match(Set dst (CopyI src)); 10331 // %} 10332 // 10333 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 10334 // match(Set dst (AddI dst src)); 10335 // effect(KILL cr); 10336 // %} 10337 // 10338 // // Change (inc mov) to lea 10339 // peephole %{ 10340 // // increment preceeded by register-register move 10341 // peepmatch (incI_eReg movI); 10342 // // require that the destination register of the increment 10343 // // match the destination register of the move 10344 // peepconstraint (0.dst == 1.dst); 10345 // // construct a replacement instruction that sets 10346 // // the destination to (move's source register + one) 10347 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); 10348 // %} 10349 // 10350 // Implementation no longer uses movX instructions since 10351 // machine-independent system no longer uses CopyX nodes. 10352 // 10353 // peephole %{ 10354 // peepmatch (incI_eReg movI); 10355 // peepconstraint (0.dst == 1.dst); 10356 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); 10357 // %} 10358 // 10359 // peephole %{ 10360 // peepmatch (decI_eReg movI); 10361 // peepconstraint (0.dst == 1.dst); 10362 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); 10363 // %} 10364 // 10365 // peephole %{ 10366 // peepmatch (addI_eReg_imm movI); 10367 // peepconstraint (0.dst == 1.dst); 10368 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); 10369 // %} 10370 // 10371 // peephole %{ 10372 // peepmatch (addP_eReg_imm movP); 10373 // peepconstraint (0.dst == 1.dst); 10374 // peepreplace (leaP_eReg_immI(0.dst 1.src 0.src)); 10375 // %} 10376 10377 10378 // This peephole rule does not work, probably because ADLC can't handle two effects: 10379 // Effect 1 is defining 0.op1 and effect 2 is setting CC 10380 // condense a load from memory and subsequent test for zero 10381 // into a single, more efficient ICM instruction. 10382 // peephole %{ 10383 // peepmatch (compI_iReg_imm0 loadI); 10384 // peepconstraint (1.dst == 0.op1); 10385 // peepreplace (loadtest15_iReg_mem(0.op1 0.op1 1.mem)); 10386 // %} 10387 10388 // // Change load of spilled value to only a spill 10389 // instruct storeI(memory mem, eRegI src) %{ 10390 // match(Set mem (StoreI mem src)); 10391 // %} 10392 // 10393 // instruct loadI(eRegI dst, memory mem) %{ 10394 // match(Set dst (LoadI mem)); 10395 // %} 10396 // 10397 peephole %{ 10398 peepmatch (loadI storeI); 10399 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); 10400 peepreplace (storeI(1.mem 1.mem 1.src)); 10401 %} 10402 10403 peephole %{ 10404 peepmatch (loadL storeL); 10405 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); 10406 peepreplace (storeL(1.mem 1.mem 1.src)); 10407 %} 10408 10409 peephole %{ 10410 peepmatch (loadP storeP); 10411 peepconstraint (1.src == 0.dst, 1.dst == 0.mem); 10412 peepreplace (storeP(1.dst 1.dst 1.src)); 10413 %} 10414 10415 //----------SUPERWORD RULES--------------------------------------------------- 10416 10417 // Expand rules for special cases 10418 10419 instruct expand_storeF(stackSlotF mem, regF src) %{ 10420 // No match rule, false predicate, for expand only. 10421 effect(DEF mem, USE src); 10422 predicate(false); 10423 ins_cost(MEMORY_REF_COST); 10424 // TODO: s390 port size(FIXED_SIZE); 10425 format %{ "STE $src,$mem\t # replicate(float2stack)" %} 10426 opcode(STE_ZOPC, STE_ZOPC); 10427 ins_encode(z_form_rt_mem(src, mem)); 10428 ins_pipe(pipe_class_dummy); 10429 %} 10430 10431 instruct expand_LoadLogical_I2L(iRegL dst, stackSlotF mem) %{ 10432 // No match rule, false predicate, for expand only. 10433 effect(DEF dst, USE mem); 10434 predicate(false); 10435 ins_cost(MEMORY_REF_COST); 10436 // TODO: s390 port size(FIXED_SIZE); 10437 format %{ "LLGF $dst,$mem\t # replicate(stack2reg(unsigned))" %} 10438 opcode(LLGF_ZOPC, LLGF_ZOPC); 10439 ins_encode(z_form_rt_mem(dst, mem)); 10440 ins_pipe(pipe_class_dummy); 10441 %} 10442 10443 // Replicate scalar int to packed int values (8 Bytes) 10444 instruct expand_Repl2I_reg(iRegL dst, iRegL src) %{ 10445 // Dummy match rule, false predicate, for expand only. 10446 match(Set dst (ConvI2L src)); 10447 predicate(false); 10448 ins_cost(DEFAULT_COST); 10449 // TODO: s390 port size(FIXED_SIZE); 10450 format %{ "REPLIC2F $dst,$src\t # replicate(pack2F)" %} 10451 ins_encode %{ 10452 if ($dst$$Register == $src$$Register) { 10453 __ z_sllg(Z_R0_scratch, $src$$Register, 64-32); 10454 __ z_ogr($dst$$Register, Z_R0_scratch); 10455 } else { 10456 __ z_sllg($dst$$Register, $src$$Register, 64-32); 10457 __ z_ogr( $dst$$Register, $src$$Register); 10458 } 10459 %} 10460 ins_pipe(pipe_class_dummy); 10461 %} 10462 10463 // Replication 10464 10465 // Exploit rotate_then_insert, if available 10466 // Replicate scalar byte to packed byte values (8 Bytes). 10467 instruct Repl8B_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{ 10468 match(Set dst (ReplicateB src)); 10469 effect(KILL cr); 10470 predicate((n->as_Vector()->length() == 8)); 10471 format %{ "REPLIC8B $dst,$src\t # pack8B" %} 10472 ins_encode %{ 10473 if ($dst$$Register != $src$$Register) { 10474 __ z_lgr($dst$$Register, $src$$Register); 10475 } 10476 __ rotate_then_insert($dst$$Register, $dst$$Register, 48, 55, 8, false); 10477 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false); 10478 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false); 10479 %} 10480 ins_pipe(pipe_class_dummy); 10481 %} 10482 10483 // Replicate scalar byte to packed byte values (8 Bytes). 10484 instruct Repl8B_imm(iRegL dst, immB_n0m1 src) %{ 10485 match(Set dst (ReplicateB src)); 10486 predicate(n->as_Vector()->length() == 8); 10487 ins_should_rematerialize(true); 10488 format %{ "REPLIC8B $dst,$src\t # pack8B imm" %} 10489 ins_encode %{ 10490 int64_t Isrc8 = $src$$constant & 0x000000ff; 10491 int64_t Isrc16 = Isrc8 << 8 | Isrc8; 10492 int64_t Isrc32 = Isrc16 << 16 | Isrc16; 10493 assert(Isrc8 != 0x000000ff && Isrc8 != 0, "should be handled by other match rules."); 10494 10495 __ z_llilf($dst$$Register, Isrc32); 10496 __ z_iihf($dst$$Register, Isrc32); 10497 %} 10498 ins_pipe(pipe_class_dummy); 10499 %} 10500 10501 // Replicate scalar byte to packed byte values (8 Bytes). 10502 instruct Repl8B_imm0(iRegL dst, immI_0 src) %{ 10503 match(Set dst (ReplicateB src)); 10504 predicate(n->as_Vector()->length() == 8); 10505 ins_should_rematerialize(true); 10506 format %{ "REPLIC8B $dst,$src\t # pack8B imm0" %} 10507 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %} 10508 ins_pipe(pipe_class_dummy); 10509 %} 10510 10511 // Replicate scalar byte to packed byte values (8 Bytes). 10512 instruct Repl8B_immm1(iRegL dst, immB_minus1 src) %{ 10513 match(Set dst (ReplicateB src)); 10514 predicate(n->as_Vector()->length() == 8); 10515 ins_should_rematerialize(true); 10516 format %{ "REPLIC8B $dst,$src\t # pack8B immm1" %} 10517 ins_encode %{ __ z_lghi($dst$$Register, -1); %} 10518 ins_pipe(pipe_class_dummy); 10519 %} 10520 10521 // Exploit rotate_then_insert, if available 10522 // Replicate scalar short to packed short values (8 Bytes). 10523 instruct Repl4S_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{ 10524 match(Set dst (ReplicateS src)); 10525 effect(KILL cr); 10526 predicate((n->as_Vector()->length() == 4)); 10527 format %{ "REPLIC4S $dst,$src\t # pack4S" %} 10528 ins_encode %{ 10529 if ($dst$$Register != $src$$Register) { 10530 __ z_lgr($dst$$Register, $src$$Register); 10531 } 10532 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false); 10533 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false); 10534 %} 10535 ins_pipe(pipe_class_dummy); 10536 %} 10537 10538 // Replicate scalar short to packed short values (8 Bytes). 10539 instruct Repl4S_imm(iRegL dst, immS_n0m1 src) %{ 10540 match(Set dst (ReplicateS src)); 10541 predicate(n->as_Vector()->length() == 4); 10542 ins_should_rematerialize(true); 10543 format %{ "REPLIC4S $dst,$src\t # pack4S imm" %} 10544 ins_encode %{ 10545 int64_t Isrc16 = $src$$constant & 0x0000ffff; 10546 int64_t Isrc32 = Isrc16 << 16 | Isrc16; 10547 assert(Isrc16 != 0x0000ffff && Isrc16 != 0, "Repl4S_imm: (src == " INT64_FORMAT 10548 ") should be handled by other match rules.", $src$$constant); 10549 10550 __ z_llilf($dst$$Register, Isrc32); 10551 __ z_iihf($dst$$Register, Isrc32); 10552 %} 10553 ins_pipe(pipe_class_dummy); 10554 %} 10555 10556 // Replicate scalar short to packed short values (8 Bytes). 10557 instruct Repl4S_imm0(iRegL dst, immI_0 src) %{ 10558 match(Set dst (ReplicateS src)); 10559 predicate(n->as_Vector()->length() == 4); 10560 ins_should_rematerialize(true); 10561 format %{ "REPLIC4S $dst,$src\t # pack4S imm0" %} 10562 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %} 10563 ins_pipe(pipe_class_dummy); 10564 %} 10565 10566 // Replicate scalar short to packed short values (8 Bytes). 10567 instruct Repl4S_immm1(iRegL dst, immS_minus1 src) %{ 10568 match(Set dst (ReplicateS src)); 10569 predicate(n->as_Vector()->length() == 4); 10570 ins_should_rematerialize(true); 10571 format %{ "REPLIC4S $dst,$src\t # pack4S immm1" %} 10572 ins_encode %{ __ z_lghi($dst$$Register, -1); %} 10573 ins_pipe(pipe_class_dummy); 10574 %} 10575 10576 // Exploit rotate_then_insert, if available. 10577 // Replicate scalar int to packed int values (8 Bytes). 10578 instruct Repl2I_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{ 10579 match(Set dst (ReplicateI src)); 10580 effect(KILL cr); 10581 predicate((n->as_Vector()->length() == 2)); 10582 format %{ "REPLIC2I $dst,$src\t # pack2I" %} 10583 ins_encode %{ 10584 if ($dst$$Register != $src$$Register) { 10585 __ z_lgr($dst$$Register, $src$$Register); 10586 } 10587 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false); 10588 %} 10589 ins_pipe(pipe_class_dummy); 10590 %} 10591 10592 // Replicate scalar int to packed int values (8 Bytes). 10593 instruct Repl2I_imm(iRegL dst, immI_n0m1 src) %{ 10594 match(Set dst (ReplicateI src)); 10595 predicate(n->as_Vector()->length() == 2); 10596 ins_should_rematerialize(true); 10597 format %{ "REPLIC2I $dst,$src\t # pack2I imm" %} 10598 ins_encode %{ 10599 int64_t Isrc32 = $src$$constant; 10600 assert(Isrc32 != -1 && Isrc32 != 0, "should be handled by other match rules."); 10601 10602 __ z_llilf($dst$$Register, Isrc32); 10603 __ z_iihf($dst$$Register, Isrc32); 10604 %} 10605 ins_pipe(pipe_class_dummy); 10606 %} 10607 10608 // Replicate scalar int to packed int values (8 Bytes). 10609 instruct Repl2I_imm0(iRegL dst, immI_0 src) %{ 10610 match(Set dst (ReplicateI src)); 10611 predicate(n->as_Vector()->length() == 2); 10612 ins_should_rematerialize(true); 10613 format %{ "REPLIC2I $dst,$src\t # pack2I imm0" %} 10614 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %} 10615 ins_pipe(pipe_class_dummy); 10616 %} 10617 10618 // Replicate scalar int to packed int values (8 Bytes). 10619 instruct Repl2I_immm1(iRegL dst, immI_minus1 src) %{ 10620 match(Set dst (ReplicateI src)); 10621 predicate(n->as_Vector()->length() == 2); 10622 ins_should_rematerialize(true); 10623 format %{ "REPLIC2I $dst,$src\t # pack2I immm1" %} 10624 ins_encode %{ __ z_lghi($dst$$Register, -1); %} 10625 ins_pipe(pipe_class_dummy); 10626 %} 10627 10628 // 10629 10630 instruct Repl2F_reg_indirect(iRegL dst, regF src, flagsReg cr) %{ 10631 match(Set dst (ReplicateF src)); 10632 effect(KILL cr); 10633 predicate(!VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2); 10634 format %{ "REPLIC2F $dst,$src\t # pack2F indirect" %} 10635 expand %{ 10636 stackSlotF tmp; 10637 iRegL tmp2; 10638 expand_storeF(tmp, src); 10639 expand_LoadLogical_I2L(tmp2, tmp); 10640 expand_Repl2I_reg(dst, tmp2); 10641 %} 10642 %} 10643 10644 // Replicate scalar float to packed float values in GREG (8 Bytes). 10645 instruct Repl2F_reg_direct(iRegL dst, regF src, flagsReg cr) %{ 10646 match(Set dst (ReplicateF src)); 10647 effect(KILL cr); 10648 predicate(VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2); 10649 format %{ "REPLIC2F $dst,$src\t # pack2F direct" %} 10650 ins_encode %{ 10651 assert(VM_Version::has_FPSupportEnhancements(), "encoder should never be called on old H/W"); 10652 __ z_lgdr($dst$$Register, $src$$FloatRegister); 10653 10654 __ z_srlg(Z_R0_scratch, $dst$$Register, 32); // Floats are left-justified in 64bit reg. 10655 __ z_iilf($dst$$Register, 0); // Save a "result not ready" stall. 10656 __ z_ogr($dst$$Register, Z_R0_scratch); 10657 %} 10658 ins_pipe(pipe_class_dummy); 10659 %} 10660 10661 // Replicate scalar float immediate to packed float values in GREG (8 Bytes). 10662 instruct Repl2F_imm(iRegL dst, immF src) %{ 10663 match(Set dst (ReplicateF src)); 10664 predicate(n->as_Vector()->length() == 2); 10665 ins_should_rematerialize(true); 10666 format %{ "REPLIC2F $dst,$src\t # pack2F imm" %} 10667 ins_encode %{ 10668 union { 10669 int Isrc32; 10670 float Fsrc32; 10671 }; 10672 Fsrc32 = $src$$constant; 10673 __ z_llilf($dst$$Register, Isrc32); 10674 __ z_iihf($dst$$Register, Isrc32); 10675 %} 10676 ins_pipe(pipe_class_dummy); 10677 %} 10678 10679 // Replicate scalar float immediate zeroes to packed float values in GREG (8 Bytes). 10680 // Do this only for 'real' zeroes, especially don't loose sign of negative zeroes. 10681 instruct Repl2F_imm0(iRegL dst, immFp0 src) %{ 10682 match(Set dst (ReplicateF src)); 10683 predicate(n->as_Vector()->length() == 2); 10684 ins_should_rematerialize(true); 10685 format %{ "REPLIC2F $dst,$src\t # pack2F imm0" %} 10686 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %} 10687 ins_pipe(pipe_class_dummy); 10688 %} 10689 10690 // Store 10691 10692 // Store Aligned Packed Byte register to memory (8 Bytes). 10693 instruct storeA8B(memory mem, iRegL src) %{ 10694 match(Set mem (StoreVector mem src)); 10695 predicate(n->as_StoreVector()->memory_size() == 8); 10696 ins_cost(MEMORY_REF_COST); 10697 // TODO: s390 port size(VARIABLE_SIZE); 10698 format %{ "STG $src,$mem\t # ST(packed8B)" %} 10699 opcode(STG_ZOPC, STG_ZOPC); 10700 ins_encode(z_form_rt_mem_opt(src, mem)); 10701 ins_pipe(pipe_class_dummy); 10702 %} 10703 10704 // Load 10705 10706 instruct loadV8(iRegL dst, memory mem) %{ 10707 match(Set dst (LoadVector mem)); 10708 predicate(n->as_LoadVector()->memory_size() == 8); 10709 ins_cost(MEMORY_REF_COST); 10710 // TODO: s390 port size(VARIABLE_SIZE); 10711 format %{ "LG $dst,$mem\t # L(packed8B)" %} 10712 opcode(LG_ZOPC, LG_ZOPC); 10713 ins_encode(z_form_rt_mem_opt(dst, mem)); 10714 ins_pipe(pipe_class_dummy); 10715 %} 10716 10717 //----------POPULATION COUNT RULES-------------------------------------------- 10718 10719 // Byte reverse 10720 10721 instruct bytes_reverse_int(iRegI dst, iRegI src) %{ 10722 match(Set dst (ReverseBytesI src)); 10723 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported 10724 ins_cost(DEFAULT_COST); 10725 size(4); 10726 format %{ "LRVR $dst,$src\t# byte reverse int" %} 10727 opcode(LRVR_ZOPC); 10728 ins_encode(z_rreform(dst, src)); 10729 ins_pipe(pipe_class_dummy); 10730 %} 10731 10732 instruct bytes_reverse_long(iRegL dst, iRegL src) %{ 10733 match(Set dst (ReverseBytesL src)); 10734 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported 10735 ins_cost(DEFAULT_COST); 10736 // TODO: s390 port size(FIXED_SIZE); 10737 format %{ "LRVGR $dst,$src\t# byte reverse long" %} 10738 opcode(LRVGR_ZOPC); 10739 ins_encode(z_rreform(dst, src)); 10740 ins_pipe(pipe_class_dummy); 10741 %} 10742 10743 // Leading zeroes 10744 10745 // The instruction FLOGR (Find Leftmost One in Grande (64bit) Register) 10746 // returns the bit position of the leftmost 1 in the 64bit source register. 10747 // As the bits are numbered from left to right (0..63), the returned 10748 // position index is equivalent to the number of leading zeroes. 10749 // If no 1-bit is found (i.e. the regsiter contains zero), the instruction 10750 // returns position 64. That's exactly what we need. 10751 10752 instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{ 10753 match(Set dst (CountLeadingZerosI src)); 10754 effect(KILL tmp, KILL cr); 10755 ins_cost(3 * DEFAULT_COST); 10756 size(14); 10757 format %{ "SLLG $dst,$src,32\t# no need to always count 32 zeroes first\n\t" 10758 "IILH $dst,0x8000 \t# insert \"stop bit\" to force result 32 for zero src.\n\t" 10759 "FLOGR $dst,$dst" 10760 %} 10761 ins_encode %{ 10762 // Performance experiments indicate that "FLOGR" is using some kind of 10763 // iteration to find the leftmost "1" bit. 10764 // 10765 // The prior implementation zero-extended the 32-bit argument to 64 bit, 10766 // thus forcing "FLOGR" to count 32 bits of which we know they are zero. 10767 // We could gain measurable speedup in micro benchmark: 10768 // 10769 // leading trailing 10770 // z10: int 2.04 1.68 10771 // long 1.00 1.02 10772 // z196: int 0.99 1.23 10773 // long 1.00 1.11 10774 // 10775 // By shifting the argument into the high-word instead of zero-extending it. 10776 // The add'l branch on condition (taken for a zero argument, very infrequent, 10777 // good prediction) is well compensated for by the savings. 10778 // 10779 // We leave the previous implementation in for some time in the future when 10780 // the "FLOGR" instruction may become less iterative. 10781 10782 // Version 2: shows 62%(z9), 204%(z10), -1%(z196) improvement over original 10783 __ z_sllg($dst$$Register, $src$$Register, 32); // No need to always count 32 zeroes first. 10784 __ z_iilh($dst$$Register, 0x8000); // Insert "stop bit" to force result 32 for zero src. 10785 __ z_flogr($dst$$Register, $dst$$Register); 10786 %} 10787 ins_pipe(pipe_class_dummy); 10788 %} 10789 10790 instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{ 10791 match(Set dst (CountLeadingZerosL src)); 10792 effect(KILL tmp, KILL cr); 10793 ins_cost(DEFAULT_COST); 10794 size(4); 10795 format %{ "FLOGR $dst,$src \t# count leading zeros (long)\n\t" %} 10796 ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %} 10797 ins_pipe(pipe_class_dummy); 10798 %} 10799 10800 // trailing zeroes 10801 10802 // We transform the trailing zeroes problem to a leading zeroes problem 10803 // such that can use the FLOGR instruction to our advantage. 10804 10805 // With 10806 // tmp1 = src - 1 10807 // we flip all trailing zeroes to ones and the rightmost one to zero. 10808 // All other bits remain unchanged. 10809 // With the complement 10810 // tmp2 = ~src 10811 // we get all ones in the trailing zeroes positions. Thus, 10812 // tmp3 = tmp1 & tmp2 10813 // yields ones in the trailing zeroes positions and zeroes elsewhere. 10814 // Now we can apply FLOGR and get 64-(trailing zeroes). 10815 instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{ 10816 match(Set dst (CountTrailingZerosI src)); 10817 effect(TEMP_DEF dst, TEMP tmp, KILL cr); 10818 ins_cost(8 * DEFAULT_COST); 10819 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off. 10820 format %{ "LLGFR $dst,$src \t# clear upper 32 bits (we are dealing with int)\n\t" 10821 "LCGFR $tmp,$src \t# load 2's complement (32->64 bit)\n\t" 10822 "AGHI $dst,-1 \t# tmp1 = src-1\n\t" 10823 "AGHI $tmp,-1 \t# tmp2 = -src-1 = ~src\n\t" 10824 "NGR $dst,$tmp \t# tmp3 = tmp1&tmp2\n\t" 10825 "FLOGR $dst,$dst \t# count trailing zeros (int)\n\t" 10826 "AHI $dst,-64 \t# tmp4 = 64-(trailing zeroes)-64\n\t" 10827 "LCR $dst,$dst \t# res = -tmp4" 10828 %} 10829 ins_encode %{ 10830 Register Rdst = $dst$$Register; 10831 Register Rsrc = $src$$Register; 10832 // Rtmp only needed for for zero-argument shortcut. With kill effect in 10833 // match rule Rsrc = roddReg would be possible, saving one register. 10834 Register Rtmp = $tmp$$Register; 10835 10836 assert_different_registers(Rdst, Rsrc, Rtmp); 10837 10838 // Algorithm: 10839 // - Isolate the least significant (rightmost) set bit using (src & (-src)). 10840 // All other bits in the result are zero. 10841 // - Find the "leftmost one" bit position in the single-bit result from previous step. 10842 // - 63-("leftmost one" bit position) gives the # of trailing zeros. 10843 10844 // Version 2: shows 79%(z9), 68%(z10), 23%(z196) improvement over original. 10845 Label done; 10846 __ load_const_optimized(Rdst, 32); // Prepare for shortcut (zero argument), result will be 32. 10847 __ z_lcgfr(Rtmp, Rsrc); 10848 __ z_bre(done); // Taken very infrequently, good prediction, no BHT entry. 10849 10850 __ z_nr(Rtmp, Rsrc); // (src) & (-src) leaves nothing but least significant bit. 10851 __ z_ahi(Rtmp, -1); // Subtract one to fill all trailing zero positions with ones. 10852 // Use 32bit op to prevent borrow propagation (case Rdst = 0x80000000) 10853 // into upper half of reg. Not relevant with sllg below. 10854 __ z_sllg(Rdst, Rtmp, 32); // Shift interesting contents to upper half of register. 10855 __ z_bre(done); // Shortcut for argument = 1, result will be 0. 10856 // Depends on CC set by ahi above. 10857 // Taken very infrequently, good prediction, no BHT entry. 10858 // Branch delayed to have Rdst set correctly (Rtmp == 0(32bit) 10859 // after SLLG Rdst == 0(64bit)). 10860 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst. 10861 __ add2reg(Rdst, -32); // 32-pos(leftmost1) is #trailing zeros 10862 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost. 10863 __ bind(done); 10864 %} 10865 ins_pipe(pipe_class_dummy); 10866 %} 10867 10868 instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{ 10869 match(Set dst (CountTrailingZerosL src)); 10870 effect(TEMP_DEF dst, KILL tmp, KILL cr); 10871 ins_cost(8 * DEFAULT_COST); 10872 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off. 10873 format %{ "LCGR $dst,$src \t# preserve src\n\t" 10874 "NGR $dst,$src \t#" 10875 "AGHI $dst,-1 \t# tmp1 = src-1\n\t" 10876 "FLOGR $dst,$dst \t# count trailing zeros (long), kill $tmp\n\t" 10877 "AHI $dst,-64 \t# tmp4 = 64-(trailing zeroes)-64\n\t" 10878 "LCR $dst,$dst \t#" 10879 %} 10880 ins_encode %{ 10881 Register Rdst = $dst$$Register; 10882 Register Rsrc = $src$$Register; 10883 assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed. 10884 10885 // New version: shows 5%(z9), 2%(z10), 11%(z196) improvement over original. 10886 __ z_lcgr(Rdst, Rsrc); 10887 __ z_ngr(Rdst, Rsrc); 10888 __ add2reg(Rdst, -1); 10889 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst. 10890 __ add2reg(Rdst, -64); 10891 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost. 10892 %} 10893 ins_pipe(pipe_class_dummy); 10894 %} 10895 10896 10897 // bit count 10898 10899 instruct popCountI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ 10900 match(Set dst (PopCountI src)); 10901 effect(TEMP_DEF dst, TEMP tmp, KILL cr); 10902 predicate(UsePopCountInstruction && VM_Version::has_PopCount()); 10903 ins_cost(DEFAULT_COST); 10904 size(24); 10905 format %{ "POPCNT $dst,$src\t# pop count int" %} 10906 ins_encode %{ 10907 Register Rdst = $dst$$Register; 10908 Register Rsrc = $src$$Register; 10909 Register Rtmp = $tmp$$Register; 10910 10911 // Prefer compile-time assertion over run-time SIGILL. 10912 assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI"); 10913 assert_different_registers(Rdst, Rtmp); 10914 10915 // Version 2: shows 10%(z196) improvement over original. 10916 __ z_popcnt(Rdst, Rsrc); 10917 __ z_srlg(Rtmp, Rdst, 16); // calc byte4+byte6 and byte5+byte7 10918 __ z_alr(Rdst, Rtmp); // into byte6 and byte7 10919 __ z_srlg(Rtmp, Rdst, 8); // calc (byte4+byte6) + (byte5+byte7) 10920 __ z_alr(Rdst, Rtmp); // into byte7 10921 __ z_llgcr(Rdst, Rdst); // zero-extend sum 10922 %} 10923 ins_pipe(pipe_class_dummy); 10924 %} 10925 10926 instruct popCountL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{ 10927 match(Set dst (PopCountL src)); 10928 effect(TEMP_DEF dst, TEMP tmp, KILL cr); 10929 predicate(UsePopCountInstruction && VM_Version::has_PopCount()); 10930 ins_cost(DEFAULT_COST); 10931 // TODO: s390 port size(FIXED_SIZE); 10932 format %{ "POPCNT $dst,$src\t# pop count long" %} 10933 ins_encode %{ 10934 Register Rdst = $dst$$Register; 10935 Register Rsrc = $src$$Register; 10936 Register Rtmp = $tmp$$Register; 10937 10938 // Prefer compile-time assertion over run-time SIGILL. 10939 assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI"); 10940 assert_different_registers(Rdst, Rtmp); 10941 10942 // Original version. Using LA instead of algr seems to be a really bad idea (-35%). 10943 __ z_popcnt(Rdst, Rsrc); 10944 __ z_ahhlr(Rdst, Rdst, Rdst); 10945 __ z_sllg(Rtmp, Rdst, 16); 10946 __ z_algr(Rdst, Rtmp); 10947 __ z_sllg(Rtmp, Rdst, 8); 10948 __ z_algr(Rdst, Rtmp); 10949 __ z_srlg(Rdst, Rdst, 56); 10950 %} 10951 ins_pipe(pipe_class_dummy); 10952 %} 10953 10954 //----------SMARTSPILL RULES--------------------------------------------------- 10955 // These must follow all instruction definitions as they use the names 10956 // defined in the instructions definitions. 10957 10958 // ============================================================================ 10959 // TYPE PROFILING RULES 10960