rev 49827 : 8201593: Print array length in ArrayIndexOutOfBoundsException.

   1 /*
   2  * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "c1/c1_Defs.hpp"
  28 #include "c1/c1_LIRAssembler.hpp"
  29 #include "c1/c1_MacroAssembler.hpp"
  30 #include "c1/c1_Runtime1.hpp"
  31 #include "ci/ciUtilities.hpp"
  32 #include "gc/shared/cardTable.hpp"
  33 #include "gc/shared/cardTableBarrierSet.hpp"
  34 #include "interpreter/interpreter.hpp"
  35 #include "nativeInst_arm.hpp"
  36 #include "oops/compiledICHolder.hpp"
  37 #include "oops/oop.inline.hpp"
  38 #include "prims/jvmtiExport.hpp"
  39 #include "register_arm.hpp"
  40 #include "runtime/sharedRuntime.hpp"
  41 #include "runtime/signature.hpp"
  42 #include "runtime/vframeArray.hpp"
  43 #include "utilities/align.hpp"
  44 #include "vmreg_arm.inline.hpp"
  45 #if INCLUDE_ALL_GCS
  46 #include "gc/g1/g1BarrierSet.hpp"
  47 #include "gc/g1/g1CardTable.hpp"
  48 #include "gc/g1/g1ThreadLocalData.hpp"
  49 #endif
  50 
  51 // Note: Rtemp usage is this file should not impact C2 and should be
  52 // correct as long as it is not implicitly used in lower layers (the
  53 // arm [macro]assembler) and used with care in the other C1 specific
  54 // files.
  55 
  56 // Implementation of StubAssembler
  57 
  58 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) {
  59   mov(R0, Rthread);
  60 
  61   int call_offset = set_last_Java_frame(SP, FP, false, Rtemp);
  62 
  63   call(entry);
  64   if (call_offset == -1) { // PC not saved
  65     call_offset = offset();
  66   }
  67   reset_last_Java_frame(Rtemp);
  68 
  69   assert(frame_size() != no_frame_size, "frame must be fixed");
  70   if (_stub_id != Runtime1::forward_exception_id) {
  71     ldr(R3, Address(Rthread, Thread::pending_exception_offset()));
  72   }
  73 
  74   if (oop_result1->is_valid()) {
  75     assert_different_registers(oop_result1, R3, Rtemp);
  76     get_vm_result(oop_result1, Rtemp);
  77   }
  78   if (metadata_result->is_valid()) {
  79     assert_different_registers(metadata_result, R3, Rtemp);
  80     get_vm_result_2(metadata_result, Rtemp);
  81   }
  82 
  83   // Check for pending exception
  84   // unpack_with_exception_in_tls path is taken through
  85   // Runtime1::exception_handler_for_pc
  86   if (_stub_id != Runtime1::forward_exception_id) {
  87     assert(frame_size() != no_frame_size, "cannot directly call forward_exception_id");
  88 #ifdef AARCH64
  89     Label skip;
  90     cbz(R3, skip);
  91     jump(Runtime1::entry_for(Runtime1::forward_exception_id), relocInfo::runtime_call_type, Rtemp);
  92     bind(skip);
  93 #else
  94     cmp(R3, 0);
  95     jump(Runtime1::entry_for(Runtime1::forward_exception_id), relocInfo::runtime_call_type, Rtemp, ne);
  96 #endif // AARCH64
  97   } else {
  98 #ifdef ASSERT
  99     // Should not have pending exception in forward_exception stub
 100     ldr(R3, Address(Rthread, Thread::pending_exception_offset()));
 101     cmp(R3, 0);
 102     breakpoint(ne);
 103 #endif // ASSERT
 104   }
 105   return call_offset;
 106 }
 107 
 108 
 109 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) {
 110   if (arg1 != R1) {
 111     mov(R1, arg1);
 112   }
 113   return call_RT(oop_result1, metadata_result, entry, 1);
 114 }
 115 
 116 
 117 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) {
 118   assert(arg1 == R1 && arg2 == R2, "cannot handle otherwise");
 119   return call_RT(oop_result1, metadata_result, entry, 2);
 120 }
 121 
 122 
 123 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) {
 124   assert(arg1 == R1 && arg2 == R2 && arg3 == R3, "cannot handle otherwise");
 125   return call_RT(oop_result1, metadata_result, entry, 3);
 126 }
 127 
 128 
 129 #define __ sasm->
 130 
 131 // TODO: ARM - does this duplicate RegisterSaver in SharedRuntime?
 132 #ifdef AARCH64
 133 
 134   //
 135   // On AArch64 registers save area has the following layout:
 136   //
 137   // |---------------------|
 138   // | return address (LR) |
 139   // | FP                  |
 140   // |---------------------|
 141   // | D31                 |
 142   // | ...                 |
 143   // | D0                  |
 144   // |---------------------|
 145   // | padding             |
 146   // |---------------------|
 147   // | R28                 |
 148   // | ...                 |
 149   // | R0                  |
 150   // |---------------------| <-- SP
 151   //
 152 
 153 enum RegisterLayout {
 154   number_of_saved_gprs = 29,
 155   number_of_saved_fprs = FloatRegisterImpl::number_of_registers,
 156 
 157   R0_offset  = 0,
 158   D0_offset  = R0_offset + number_of_saved_gprs + 1,
 159   FP_offset  = D0_offset + number_of_saved_fprs,
 160   LR_offset  = FP_offset + 1,
 161 
 162   reg_save_size = LR_offset + 1,
 163 
 164   arg1_offset = reg_save_size * wordSize,
 165   arg2_offset = (reg_save_size + 1) * wordSize
 166 };
 167 
 168 #else
 169 
 170 enum RegisterLayout {
 171   fpu_save_size = pd_nof_fpu_regs_reg_alloc,
 172 #ifndef __SOFTFP__
 173   D0_offset = 0,
 174 #endif
 175   R0_offset = fpu_save_size,
 176   R1_offset,
 177   R2_offset,
 178   R3_offset,
 179   R4_offset,
 180   R5_offset,
 181   R6_offset,
 182 #if (FP_REG_NUM != 7)
 183   R7_offset,
 184 #endif
 185   R8_offset,
 186   R9_offset,
 187   R10_offset,
 188 #if (FP_REG_NUM != 11)
 189   R11_offset,
 190 #endif
 191   R12_offset,
 192   FP_offset,
 193   LR_offset,
 194   reg_save_size,
 195   arg1_offset = reg_save_size * wordSize,
 196   arg2_offset = (reg_save_size + 1) * wordSize
 197 };
 198 
 199 #endif // AARCH64
 200 
 201 static OopMap* generate_oop_map(StubAssembler* sasm, bool save_fpu_registers = HaveVFP) {
 202   sasm->set_frame_size(reg_save_size /* in words */);
 203 
 204   // Record saved value locations in an OopMap.
 205   // Locations are offsets from sp after runtime call.
 206   OopMap* map = new OopMap(VMRegImpl::slots_per_word * reg_save_size, 0);
 207 
 208 #ifdef AARCH64
 209   for (int i = 0; i < number_of_saved_gprs; i++) {
 210     map->set_callee_saved(VMRegImpl::stack2reg((R0_offset + i) * VMRegImpl::slots_per_word), as_Register(i)->as_VMReg());
 211   }
 212   map->set_callee_saved(VMRegImpl::stack2reg(FP_offset * VMRegImpl::slots_per_word), FP->as_VMReg());
 213   map->set_callee_saved(VMRegImpl::stack2reg(LR_offset * VMRegImpl::slots_per_word), LR->as_VMReg());
 214 
 215   if (save_fpu_registers) {
 216     for (int i = 0; i < number_of_saved_fprs; i++) {
 217       map->set_callee_saved(VMRegImpl::stack2reg((D0_offset + i) * VMRegImpl::slots_per_word), as_FloatRegister(i)->as_VMReg());
 218     }
 219   }
 220 #else
 221   int j=0;
 222   for (int i = R0_offset; i < R10_offset; i++) {
 223     if (j == FP_REG_NUM) {
 224       // skip the FP register, saved below
 225       j++;
 226     }
 227     map->set_callee_saved(VMRegImpl::stack2reg(i), as_Register(j)->as_VMReg());
 228     j++;
 229   }
 230   assert(j == R10->encoding(), "must be");
 231 #if (FP_REG_NUM != 11)
 232   // add R11, if not saved as FP
 233   map->set_callee_saved(VMRegImpl::stack2reg(R11_offset), R11->as_VMReg());
 234 #endif
 235   map->set_callee_saved(VMRegImpl::stack2reg(FP_offset), FP->as_VMReg());
 236   map->set_callee_saved(VMRegImpl::stack2reg(LR_offset), LR->as_VMReg());
 237 
 238   if (save_fpu_registers) {
 239     for (int i = 0; i < fpu_save_size; i++) {
 240       map->set_callee_saved(VMRegImpl::stack2reg(i), as_FloatRegister(i)->as_VMReg());
 241     }
 242   }
 243 #endif // AARCH64
 244 
 245   return map;
 246 }
 247 
 248 static OopMap* save_live_registers(StubAssembler* sasm, bool save_fpu_registers = HaveVFP) {
 249   __ block_comment("save_live_registers");
 250   sasm->set_frame_size(reg_save_size /* in words */);
 251 
 252 #ifdef AARCH64
 253   assert((reg_save_size * wordSize) % StackAlignmentInBytes == 0, "SP should be aligned");
 254 
 255   __ raw_push(FP, LR);
 256 
 257   __ sub(SP, SP, (reg_save_size - 2) * wordSize);
 258 
 259   for (int i = 0; i < align_down((int)number_of_saved_gprs, 2); i += 2) {
 260     __ stp(as_Register(i), as_Register(i+1), Address(SP, (R0_offset + i) * wordSize));
 261   }
 262 
 263   if (is_odd(number_of_saved_gprs)) {
 264     int i = number_of_saved_gprs - 1;
 265     __ str(as_Register(i), Address(SP, (R0_offset + i) * wordSize));
 266   }
 267 
 268   if (save_fpu_registers) {
 269     assert (is_even(number_of_saved_fprs), "adjust this code");
 270     for (int i = 0; i < number_of_saved_fprs; i += 2) {
 271       __ stp_d(as_FloatRegister(i), as_FloatRegister(i+1), Address(SP, (D0_offset + i) * wordSize));
 272     }
 273   }
 274 #else
 275   __ push(RegisterSet(FP) | RegisterSet(LR));
 276   __ push(RegisterSet(R0, R6) | RegisterSet(R8, R10) | R12 | altFP_7_11);
 277   if (save_fpu_registers) {
 278     __ fstmdbd(SP, FloatRegisterSet(D0, fpu_save_size / 2), writeback);
 279   } else {
 280     __ sub(SP, SP, fpu_save_size * wordSize);
 281   }
 282 #endif // AARCH64
 283 
 284   return generate_oop_map(sasm, save_fpu_registers);
 285 }
 286 
 287 
 288 static void restore_live_registers(StubAssembler* sasm,
 289                                    bool restore_R0,
 290                                    bool restore_FP_LR,
 291                                    bool do_return,
 292                                    bool restore_fpu_registers = HaveVFP) {
 293   __ block_comment("restore_live_registers");
 294 
 295 #ifdef AARCH64
 296   if (restore_R0) {
 297     __ ldr(R0, Address(SP, R0_offset * wordSize));
 298   }
 299 
 300   assert(is_odd(number_of_saved_gprs), "adjust this code");
 301   for (int i = 1; i < number_of_saved_gprs; i += 2) {
 302     __ ldp(as_Register(i), as_Register(i+1), Address(SP, (R0_offset + i) * wordSize));
 303   }
 304 
 305   if (restore_fpu_registers) {
 306     assert (is_even(number_of_saved_fprs), "adjust this code");
 307     for (int i = 0; i < number_of_saved_fprs; i += 2) {
 308       __ ldp_d(as_FloatRegister(i), as_FloatRegister(i+1), Address(SP, (D0_offset + i) * wordSize));
 309     }
 310   }
 311 
 312   __ add(SP, SP, (reg_save_size - 2) * wordSize);
 313 
 314   if (restore_FP_LR) {
 315     __ raw_pop(FP, LR);
 316     if (do_return) {
 317       __ ret();
 318     }
 319   } else {
 320     assert (!do_return, "return without restoring FP/LR");
 321   }
 322 #else
 323   if (restore_fpu_registers) {
 324     __ fldmiad(SP, FloatRegisterSet(D0, fpu_save_size / 2), writeback);
 325     if (!restore_R0) {
 326       __ add(SP, SP, (R1_offset - fpu_save_size) * wordSize);
 327     }
 328   } else {
 329     __ add(SP, SP, (restore_R0 ? fpu_save_size : R1_offset) * wordSize);
 330   }
 331   __ pop(RegisterSet((restore_R0 ? R0 : R1), R6) | RegisterSet(R8, R10) | R12 | altFP_7_11);
 332   if (restore_FP_LR) {
 333     __ pop(RegisterSet(FP) | RegisterSet(do_return ? PC : LR));
 334   } else {
 335     assert (!do_return, "return without restoring FP/LR");
 336   }
 337 #endif // AARCH64
 338 }
 339 
 340 
 341 static void restore_live_registers_except_R0(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
 342   restore_live_registers(sasm, false, true, true, restore_fpu_registers);
 343 }
 344 
 345 static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
 346   restore_live_registers(sasm, true, true, true, restore_fpu_registers);
 347 }
 348 
 349 #ifndef AARCH64
 350 static void restore_live_registers_except_FP_LR(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
 351   restore_live_registers(sasm, true, false, false, restore_fpu_registers);
 352 }
 353 #endif // !AARCH64
 354 
 355 static void restore_live_registers_without_return(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
 356   restore_live_registers(sasm, true, true, false, restore_fpu_registers);
 357 }
 358 
 359 
 360 void Runtime1::initialize_pd() {
 361 }
 362 
 363 
 364 OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) {
 365   OopMap* oop_map = save_live_registers(sasm);
 366 
 367   if (has_argument) {
 368     __ ldr(R1, Address(SP, arg1_offset));
 369     __ ldr(R2, Address(SP, arg2_offset));
 370   }
 371 
 372   int call_offset = __ call_RT(noreg, noreg, target);
 373   OopMapSet* oop_maps = new OopMapSet();
 374   oop_maps->add_gc_map(call_offset, oop_map);
 375 
 376   DEBUG_ONLY(STOP("generate_exception_throw");)  // Should not reach here
 377   return oop_maps;
 378 }
 379 
 380 
 381 static void restore_sp_for_method_handle(StubAssembler* sasm) {
 382   // Restore SP from its saved reg (FP) if the exception PC is a MethodHandle call site.
 383   __ ldr_s32(Rtemp, Address(Rthread, JavaThread::is_method_handle_return_offset()));
 384 #ifdef AARCH64
 385   Label skip;
 386   __ cbz(Rtemp, skip);
 387   __ mov(SP, Rmh_SP_save);
 388   __ bind(skip);
 389 #else
 390   __ cmp(Rtemp, 0);
 391   __ mov(SP, Rmh_SP_save, ne);
 392 #endif // AARCH64
 393 }
 394 
 395 
 396 OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler* sasm) {
 397   __ block_comment("generate_handle_exception");
 398 
 399   bool save_fpu_registers = false;
 400 
 401   // Save registers, if required.
 402   OopMapSet* oop_maps = new OopMapSet();
 403   OopMap* oop_map = NULL;
 404 
 405   switch (id) {
 406   case forward_exception_id: {
 407     save_fpu_registers = HaveVFP;
 408     oop_map = generate_oop_map(sasm);
 409     __ ldr(Rexception_obj, Address(Rthread, Thread::pending_exception_offset()));
 410     __ ldr(Rexception_pc, Address(SP, LR_offset * wordSize));
 411     Register zero = __ zero_register(Rtemp);
 412     __ str(zero, Address(Rthread, Thread::pending_exception_offset()));
 413     break;
 414   }
 415   case handle_exception_id:
 416     save_fpu_registers = HaveVFP;
 417     // fall-through
 418   case handle_exception_nofpu_id:
 419     // At this point all registers MAY be live.
 420     oop_map = save_live_registers(sasm, save_fpu_registers);
 421     break;
 422   case handle_exception_from_callee_id:
 423     // At this point all registers except exception oop (R4/R19) and
 424     // exception pc (R5/R20) are dead.
 425     oop_map = save_live_registers(sasm);  // TODO it's not required to save all registers
 426     break;
 427   default:  ShouldNotReachHere();
 428   }
 429 
 430   __ str(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
 431   __ str(Rexception_pc, Address(Rthread, JavaThread::exception_pc_offset()));
 432 
 433   __ str(Rexception_pc, Address(SP, LR_offset * wordSize)); // patch throwing pc into return address
 434 
 435   int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc));
 436   oop_maps->add_gc_map(call_offset, oop_map);
 437 
 438   // Exception handler found
 439   __ str(R0, Address(SP, LR_offset * wordSize)); // patch the return address
 440 
 441   // Restore the registers that were saved at the beginning, remove
 442   // frame and jump to the exception handler.
 443   switch (id) {
 444   case forward_exception_id:
 445   case handle_exception_nofpu_id:
 446   case handle_exception_id:
 447     restore_live_registers(sasm, save_fpu_registers);
 448     // Note: the restore live registers includes the jump to LR (patched to R0)
 449     break;
 450   case handle_exception_from_callee_id:
 451     restore_live_registers_without_return(sasm); // must not jump immediatly to handler
 452     restore_sp_for_method_handle(sasm);
 453     __ ret();
 454     break;
 455   default:  ShouldNotReachHere();
 456   }
 457 
 458   DEBUG_ONLY(STOP("generate_handle_exception");)  // Should not reach here
 459 
 460   return oop_maps;
 461 }
 462 
 463 
 464 void Runtime1::generate_unwind_exception(StubAssembler* sasm) {
 465   // FP no longer used to find the frame start
 466   // on entry, remove_frame() has already been called (restoring FP and LR)
 467 
 468   // search the exception handler address of the caller (using the return address)
 469   __ mov(c_rarg0, Rthread);
 470   __ mov(Rexception_pc, LR);
 471   __ mov(c_rarg1, LR);
 472   __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), c_rarg0, c_rarg1);
 473 
 474   // Exception oop should be still in Rexception_obj and pc in Rexception_pc
 475   // Jump to handler
 476   __ verify_not_null_oop(Rexception_obj);
 477 
 478   // JSR292 extension
 479   restore_sp_for_method_handle(sasm);
 480 
 481   __ jump(R0);
 482 }
 483 
 484 
 485 OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
 486   OopMap* oop_map = save_live_registers(sasm);
 487 
 488   // call the runtime patching routine, returns non-zero if nmethod got deopted.
 489   int call_offset = __ call_RT(noreg, noreg, target);
 490   OopMapSet* oop_maps = new OopMapSet();
 491   oop_maps->add_gc_map(call_offset, oop_map);
 492 
 493   DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
 494   assert(deopt_blob != NULL, "deoptimization blob must have been created");
 495 
 496   __ cmp_32(R0, 0);
 497 
 498 #ifdef AARCH64
 499   Label call_deopt;
 500 
 501   restore_live_registers_without_return(sasm);
 502   __ b(call_deopt, ne);
 503   __ ret();
 504 
 505   __ bind(call_deopt);
 506 #else
 507   restore_live_registers_except_FP_LR(sasm);
 508   __ pop(RegisterSet(FP) | RegisterSet(PC), eq);
 509 
 510   // Deoptimization needed
 511   // TODO: ARM - no need to restore FP & LR because unpack_with_reexecution() stores them back
 512   __ pop(RegisterSet(FP) | RegisterSet(LR));
 513 #endif // AARCH64
 514 
 515   __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, Rtemp);
 516 
 517   DEBUG_ONLY(STOP("generate_patching");)  // Should not reach here
 518   return oop_maps;
 519 }
 520 
 521 
 522 OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
 523   const bool must_gc_arguments = true;
 524   const bool dont_gc_arguments = false;
 525 
 526   OopMapSet* oop_maps = NULL;
 527   bool save_fpu_registers = HaveVFP;
 528 
 529   switch (id) {
 530     case forward_exception_id:
 531       {
 532         oop_maps = generate_handle_exception(id, sasm);
 533         // does not return on ARM
 534       }
 535       break;
 536 
 537 #if INCLUDE_ALL_GCS
 538     case g1_pre_barrier_slow_id:
 539       {
 540         // Input:
 541         // - pre_val pushed on the stack
 542 
 543         __ set_info("g1_pre_barrier_slow_id", dont_gc_arguments);
 544 
 545         BarrierSet* bs = BarrierSet::barrier_set();
 546         if (bs->kind() != BarrierSet::G1BarrierSet) {
 547           __ mov(R0, (int)id);
 548           __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), R0);
 549           __ should_not_reach_here();
 550           break;
 551         }
 552 
 553         // save at least the registers that need saving if the runtime is called
 554 #ifdef AARCH64
 555         __ raw_push(R0, R1);
 556         __ raw_push(R2, R3);
 557         const int nb_saved_regs = 4;
 558 #else // AARCH64
 559         const RegisterSet saved_regs = RegisterSet(R0,R3) | RegisterSet(R12) | RegisterSet(LR);
 560         const int nb_saved_regs = 6;
 561         assert(nb_saved_regs == saved_regs.size(), "fix nb_saved_regs");
 562         __ push(saved_regs);
 563 #endif // AARCH64
 564 
 565         const Register r_pre_val_0  = R0; // must be R0, to be ready for the runtime call
 566         const Register r_index_1    = R1;
 567         const Register r_buffer_2   = R2;
 568 
 569         Address queue_active(Rthread, in_bytes(G1ThreadLocalData::satb_mark_queue_active_offset()));
 570         Address queue_index(Rthread, in_bytes(G1ThreadLocalData::satb_mark_queue_index_offset()));
 571         Address buffer(Rthread, in_bytes(G1ThreadLocalData::satb_mark_queue_buffer_offset()));
 572 
 573         Label done;
 574         Label runtime;
 575 
 576         // Is marking still active?
 577         assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
 578         __ ldrb(R1, queue_active);
 579         __ cbz(R1, done);
 580 
 581         __ ldr(r_index_1, queue_index);
 582         __ ldr(r_pre_val_0, Address(SP, nb_saved_regs*wordSize));
 583         __ ldr(r_buffer_2, buffer);
 584 
 585         __ subs(r_index_1, r_index_1, wordSize);
 586         __ b(runtime, lt);
 587 
 588         __ str(r_index_1, queue_index);
 589         __ str(r_pre_val_0, Address(r_buffer_2, r_index_1));
 590 
 591         __ bind(done);
 592 
 593 #ifdef AARCH64
 594         __ raw_pop(R2, R3);
 595         __ raw_pop(R0, R1);
 596 #else // AARCH64
 597         __ pop(saved_regs);
 598 #endif // AARCH64
 599 
 600         __ ret();
 601 
 602         __ bind(runtime);
 603 
 604         save_live_registers(sasm);
 605 
 606         assert(r_pre_val_0 == c_rarg0, "pre_val should be in R0");
 607         __ mov(c_rarg1, Rthread);
 608         __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), c_rarg0, c_rarg1);
 609 
 610         restore_live_registers_without_return(sasm);
 611 
 612         __ b(done);
 613       }
 614       break;
 615     case g1_post_barrier_slow_id:
 616       {
 617         // Input:
 618         // - store_addr, pushed on the stack
 619 
 620         __ set_info("g1_post_barrier_slow_id", dont_gc_arguments);
 621 
 622         BarrierSet* bs = BarrierSet::barrier_set();
 623         if (bs->kind() != BarrierSet::G1BarrierSet) {
 624           __ mov(R0, (int)id);
 625           __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), R0);
 626           __ should_not_reach_here();
 627           break;
 628         }
 629 
 630         Label done;
 631         Label recheck;
 632         Label runtime;
 633 
 634         Address queue_index(Rthread, in_bytes(G1ThreadLocalData::dirty_card_queue_index_offset()));
 635         Address buffer(Rthread, in_bytes(G1ThreadLocalData::dirty_card_queue_buffer_offset()));
 636 
 637         AddressLiteral cardtable(ci_card_table_address_as<address>(), relocInfo::none);
 638 
 639         // save at least the registers that need saving if the runtime is called
 640 #ifdef AARCH64
 641         __ raw_push(R0, R1);
 642         __ raw_push(R2, R3);
 643         const int nb_saved_regs = 4;
 644 #else // AARCH64
 645         const RegisterSet saved_regs = RegisterSet(R0,R3) | RegisterSet(R12) | RegisterSet(LR);
 646         const int nb_saved_regs = 6;
 647         assert(nb_saved_regs == saved_regs.size(), "fix nb_saved_regs");
 648         __ push(saved_regs);
 649 #endif // AARCH64
 650 
 651         const Register r_card_addr_0 = R0; // must be R0 for the slow case
 652         const Register r_obj_0 = R0;
 653         const Register r_card_base_1 = R1;
 654         const Register r_tmp2 = R2;
 655         const Register r_index_2 = R2;
 656         const Register r_buffer_3 = R3;
 657         const Register tmp1 = Rtemp;
 658 
 659         __ ldr(r_obj_0, Address(SP, nb_saved_regs*wordSize));
 660         // Note: there is a comment in x86 code about not using
 661         // ExternalAddress / lea, due to relocation not working
 662         // properly for that address. Should be OK for arm, where we
 663         // explicitly specify that 'cardtable' has a relocInfo::none
 664         // type.
 665         __ lea(r_card_base_1, cardtable);
 666         __ add(r_card_addr_0, r_card_base_1, AsmOperand(r_obj_0, lsr, CardTable::card_shift));
 667 
 668         // first quick check without barrier
 669         __ ldrb(r_tmp2, Address(r_card_addr_0));
 670 
 671         __ cmp(r_tmp2, (int)G1CardTable::g1_young_card_val());
 672         __ b(recheck, ne);
 673 
 674         __ bind(done);
 675 
 676 #ifdef AARCH64
 677         __ raw_pop(R2, R3);
 678         __ raw_pop(R0, R1);
 679 #else // AARCH64
 680         __ pop(saved_regs);
 681 #endif // AARCH64
 682 
 683         __ ret();
 684 
 685         __ bind(recheck);
 686 
 687         __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad), tmp1);
 688 
 689         // reload card state after the barrier that ensures the stored oop was visible
 690         __ ldrb(r_tmp2, Address(r_card_addr_0));
 691 
 692         assert(CardTable::dirty_card_val() == 0, "adjust this code");
 693         __ cbz(r_tmp2, done);
 694 
 695         // storing region crossing non-NULL, card is clean.
 696         // dirty card and log.
 697 
 698         assert(0 == (int)CardTable::dirty_card_val(), "adjust this code");
 699         if ((ci_card_table_address_as<intptr_t>() & 0xff) == 0) {
 700           // Card table is aligned so the lowest byte of the table address base is zero.
 701           __ strb(r_card_base_1, Address(r_card_addr_0));
 702         } else {
 703           __ strb(__ zero_register(r_tmp2), Address(r_card_addr_0));
 704         }
 705 
 706         __ ldr(r_index_2, queue_index);
 707         __ ldr(r_buffer_3, buffer);
 708 
 709         __ subs(r_index_2, r_index_2, wordSize);
 710         __ b(runtime, lt); // go to runtime if now negative
 711 
 712         __ str(r_index_2, queue_index);
 713 
 714         __ str(r_card_addr_0, Address(r_buffer_3, r_index_2));
 715 
 716         __ b(done);
 717 
 718         __ bind(runtime);
 719 
 720         save_live_registers(sasm);
 721 
 722         assert(r_card_addr_0 == c_rarg0, "card_addr should be in R0");
 723         __ mov(c_rarg1, Rthread);
 724         __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), c_rarg0, c_rarg1);
 725 
 726         restore_live_registers_without_return(sasm);
 727 
 728         __ b(done);
 729       }
 730       break;
 731 #endif // INCLUDE_ALL_GCS
 732     case new_instance_id:
 733     case fast_new_instance_id:
 734     case fast_new_instance_init_check_id:
 735       {
 736         const Register result = R0;
 737         const Register klass  = R1;
 738 
 739         if (UseTLAB && Universe::heap()->supports_inline_contig_alloc() && id != new_instance_id) {
 740           // We come here when TLAB allocation failed.
 741           // In this case we try to allocate directly from eden.
 742           Label slow_case, slow_case_no_pop;
 743 
 744           // Make sure the class is fully initialized
 745           if (id == fast_new_instance_init_check_id) {
 746             __ ldrb(result, Address(klass, InstanceKlass::init_state_offset()));
 747             __ cmp(result, InstanceKlass::fully_initialized);
 748             __ b(slow_case_no_pop, ne);
 749           }
 750 
 751           // Free some temporary registers
 752           const Register obj_size = R4;
 753           const Register tmp1     = R5;
 754           const Register tmp2     = LR;
 755           const Register obj_end  = Rtemp;
 756 
 757           __ raw_push(R4, R5, LR);
 758 
 759           __ ldr_u32(obj_size, Address(klass, Klass::layout_helper_offset()));
 760           __ eden_allocate(result, obj_end, tmp1, tmp2, obj_size, slow_case);        // initializes result and obj_end
 761           __ incr_allocated_bytes(obj_size, tmp2);
 762           __ initialize_object(result, obj_end, klass, noreg /* len */, tmp1, tmp2,
 763                                instanceOopDesc::header_size() * HeapWordSize, -1,
 764                                /* is_tlab_allocated */ false);
 765           __ raw_pop_and_ret(R4, R5);
 766 
 767           __ bind(slow_case);
 768           __ raw_pop(R4, R5, LR);
 769 
 770           __ bind(slow_case_no_pop);
 771         }
 772 
 773         OopMap* map = save_live_registers(sasm);
 774         int call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_instance), klass);
 775         oop_maps = new OopMapSet();
 776         oop_maps->add_gc_map(call_offset, map);
 777 
 778         // MacroAssembler::StoreStore useless (included in the runtime exit path)
 779 
 780         restore_live_registers_except_R0(sasm);
 781       }
 782       break;
 783 
 784     case counter_overflow_id:
 785       {
 786         OopMap* oop_map = save_live_registers(sasm);
 787         __ ldr(R1, Address(SP, arg1_offset));
 788         __ ldr(R2, Address(SP, arg2_offset));
 789         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), R1, R2);
 790         oop_maps = new OopMapSet();
 791         oop_maps->add_gc_map(call_offset, oop_map);
 792         restore_live_registers(sasm);
 793       }
 794       break;
 795 
 796     case new_type_array_id:
 797     case new_object_array_id:
 798       {
 799         if (id == new_type_array_id) {
 800           __ set_info("new_type_array", dont_gc_arguments);
 801         } else {
 802           __ set_info("new_object_array", dont_gc_arguments);
 803         }
 804 
 805         const Register result = R0;
 806         const Register klass  = R1;
 807         const Register length = R2;
 808 
 809         if (UseTLAB && Universe::heap()->supports_inline_contig_alloc()) {
 810           // We come here when TLAB allocation failed.
 811           // In this case we try to allocate directly from eden.
 812           Label slow_case, slow_case_no_pop;
 813 
 814 #ifdef AARCH64
 815           __ mov_slow(Rtemp, C1_MacroAssembler::max_array_allocation_length);
 816           __ cmp_32(length, Rtemp);
 817 #else
 818           __ cmp_32(length, C1_MacroAssembler::max_array_allocation_length);
 819 #endif // AARCH64
 820           __ b(slow_case_no_pop, hs);
 821 
 822           // Free some temporary registers
 823           const Register arr_size = R4;
 824           const Register tmp1     = R5;
 825           const Register tmp2     = LR;
 826           const Register tmp3     = Rtemp;
 827           const Register obj_end  = tmp3;
 828 
 829           __ raw_push(R4, R5, LR);
 830 
 831           // Get the allocation size: round_up((length << (layout_helper & 0xff)) + header_size)
 832           __ ldr_u32(tmp1, Address(klass, Klass::layout_helper_offset()));
 833           __ mov(arr_size, MinObjAlignmentInBytesMask);
 834           __ and_32(tmp2, tmp1, (unsigned int)(Klass::_lh_header_size_mask << Klass::_lh_header_size_shift));
 835 
 836 #ifdef AARCH64
 837           __ lslv_w(tmp3, length, tmp1);
 838           __ add(arr_size, arr_size, tmp3);
 839 #else
 840           __ add(arr_size, arr_size, AsmOperand(length, lsl, tmp1));
 841 #endif // AARCH64
 842 
 843           __ add(arr_size, arr_size, AsmOperand(tmp2, lsr, Klass::_lh_header_size_shift));
 844           __ align_reg(arr_size, arr_size, MinObjAlignmentInBytes);
 845 
 846           // eden_allocate destroys tmp2, so reload header_size after allocation
 847           // eden_allocate initializes result and obj_end
 848           __ eden_allocate(result, obj_end, tmp1, tmp2, arr_size, slow_case);
 849           __ incr_allocated_bytes(arr_size, tmp2);
 850           __ ldrb(tmp2, Address(klass, in_bytes(Klass::layout_helper_offset()) +
 851                                        Klass::_lh_header_size_shift / BitsPerByte));
 852           __ initialize_object(result, obj_end, klass, length, tmp1, tmp2, tmp2, -1, /* is_tlab_allocated */ false);
 853           __ raw_pop_and_ret(R4, R5);
 854 
 855           __ bind(slow_case);
 856           __ raw_pop(R4, R5, LR);
 857           __ bind(slow_case_no_pop);
 858         }
 859 
 860         OopMap* map = save_live_registers(sasm);
 861         int call_offset;
 862         if (id == new_type_array_id) {
 863           call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length);
 864         } else {
 865           call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length);
 866         }
 867         oop_maps = new OopMapSet();
 868         oop_maps->add_gc_map(call_offset, map);
 869 
 870         // MacroAssembler::StoreStore useless (included in the runtime exit path)
 871 
 872         restore_live_registers_except_R0(sasm);
 873       }
 874       break;
 875 
 876     case new_multi_array_id:
 877       {
 878         __ set_info("new_multi_array", dont_gc_arguments);
 879 
 880         // R0: klass
 881         // R2: rank
 882         // SP: address of 1st dimension
 883         const Register result = R0;
 884         OopMap* map = save_live_registers(sasm);
 885 
 886         __ mov(R1, R0);
 887         __ add(R3, SP, arg1_offset);
 888         int call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_multi_array), R1, R2, R3);
 889 
 890         oop_maps = new OopMapSet();
 891         oop_maps->add_gc_map(call_offset, map);
 892 
 893         // MacroAssembler::StoreStore useless (included in the runtime exit path)
 894 
 895         restore_live_registers_except_R0(sasm);
 896       }
 897       break;
 898 
 899     case register_finalizer_id:
 900       {
 901         __ set_info("register_finalizer", dont_gc_arguments);
 902 
 903         // Do not call runtime if JVM_ACC_HAS_FINALIZER flag is not set
 904         __ load_klass(Rtemp, R0);
 905         __ ldr_u32(Rtemp, Address(Rtemp, Klass::access_flags_offset()));
 906 
 907 #ifdef AARCH64
 908         Label L;
 909         __ tbnz(Rtemp, exact_log2(JVM_ACC_HAS_FINALIZER), L);
 910         __ ret();
 911         __ bind(L);
 912 #else
 913         __ tst(Rtemp, JVM_ACC_HAS_FINALIZER);
 914         __ bx(LR, eq);
 915 #endif // AARCH64
 916 
 917         // Call VM
 918         OopMap* map = save_live_registers(sasm);
 919         oop_maps = new OopMapSet();
 920         int call_offset = __ call_RT(noreg, noreg,
 921                                      CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), R0);
 922         oop_maps->add_gc_map(call_offset, map);
 923         restore_live_registers(sasm);
 924       }
 925       break;
 926 
 927     case throw_range_check_failed_id:
 928       {
 929         __ set_info("range_check_failed", dont_gc_arguments);
 930         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true);
 931       }
 932       break;
 933 
 934     case throw_index_exception_id:
 935       {
 936         __ set_info("index_range_check_failed", dont_gc_arguments);
 937 #ifdef AARCH64
 938         __ NOT_TESTED();
 939 #endif
 940         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true);
 941       }
 942       break;
 943 
 944     case throw_div0_exception_id:
 945       {
 946         __ set_info("throw_div0_exception", dont_gc_arguments);
 947         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false);
 948       }
 949       break;
 950 
 951     case throw_null_pointer_exception_id:
 952       {
 953         __ set_info("throw_null_pointer_exception", dont_gc_arguments);
 954         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false);
 955       }
 956       break;
 957 
 958     case handle_exception_nofpu_id:
 959     case handle_exception_id:
 960       {
 961         __ set_info("handle_exception", dont_gc_arguments);
 962         oop_maps = generate_handle_exception(id, sasm);
 963       }
 964       break;
 965 
 966     case handle_exception_from_callee_id:
 967       {
 968         __ set_info("handle_exception_from_callee", dont_gc_arguments);
 969         oop_maps = generate_handle_exception(id, sasm);
 970       }
 971       break;
 972 
 973     case unwind_exception_id:
 974       {
 975         __ set_info("unwind_exception", dont_gc_arguments);
 976         generate_unwind_exception(sasm);
 977       }
 978       break;
 979 
 980     case throw_array_store_exception_id:
 981       {
 982         __ set_info("throw_array_store_exception", dont_gc_arguments);
 983         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true);
 984       }
 985       break;
 986 
 987     case throw_class_cast_exception_id:
 988       {
 989         __ set_info("throw_class_cast_exception", dont_gc_arguments);
 990         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true);
 991       }
 992       break;
 993 
 994     case throw_incompatible_class_change_error_id:
 995       {
 996         __ set_info("throw_incompatible_class_cast_exception", dont_gc_arguments);
 997 #ifdef AARCH64
 998         __ NOT_TESTED();
 999 #endif
1000         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false);
1001       }
1002       break;
1003 
1004     case slow_subtype_check_id:
1005       {
1006         // (in)  R0 - sub, destroyed,
1007         // (in)  R1 - super, not changed
1008         // (out) R0 - result: 1 if check passed, 0 otherwise
1009         __ raw_push(R2, R3, LR);
1010 
1011         // Load an array of secondary_supers
1012         __ ldr(R2, Address(R0, Klass::secondary_supers_offset()));
1013         // Length goes to R3
1014         __ ldr_s32(R3, Address(R2, Array<Klass*>::length_offset_in_bytes()));
1015         __ add(R2, R2, Array<Klass*>::base_offset_in_bytes());
1016 
1017         Label loop, miss;
1018         __ bind(loop);
1019         __ cbz(R3, miss);
1020         __ ldr(LR, Address(R2, wordSize, post_indexed));
1021         __ sub(R3, R3, 1);
1022         __ cmp(LR, R1);
1023         __ b(loop, ne);
1024 
1025         // We get here if an equal cache entry is found
1026         __ str(R1, Address(R0, Klass::secondary_super_cache_offset()));
1027         __ mov(R0, 1);
1028         __ raw_pop_and_ret(R2, R3);
1029 
1030         // A cache entry not found - return false
1031         __ bind(miss);
1032         __ mov(R0, 0);
1033         __ raw_pop_and_ret(R2, R3);
1034       }
1035       break;
1036 
1037     case monitorenter_nofpu_id:
1038       save_fpu_registers = false;
1039       // fall through
1040     case monitorenter_id:
1041       {
1042         __ set_info("monitorenter", dont_gc_arguments);
1043         const Register obj  = R1;
1044         const Register lock = R2;
1045         OopMap* map = save_live_registers(sasm, save_fpu_registers);
1046         __ ldr(obj, Address(SP, arg1_offset));
1047         __ ldr(lock, Address(SP, arg2_offset));
1048         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), obj, lock);
1049         oop_maps = new OopMapSet();
1050         oop_maps->add_gc_map(call_offset, map);
1051         restore_live_registers(sasm, save_fpu_registers);
1052       }
1053       break;
1054 
1055     case monitorexit_nofpu_id:
1056       save_fpu_registers = false;
1057       // fall through
1058     case monitorexit_id:
1059       {
1060         __ set_info("monitorexit", dont_gc_arguments);
1061         const Register lock = R1;
1062         OopMap* map = save_live_registers(sasm, save_fpu_registers);
1063         __ ldr(lock, Address(SP, arg1_offset));
1064         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), lock);
1065         oop_maps = new OopMapSet();
1066         oop_maps->add_gc_map(call_offset, map);
1067         restore_live_registers(sasm, save_fpu_registers);
1068       }
1069       break;
1070 
1071     case deoptimize_id:
1072       {
1073         __ set_info("deoptimize", dont_gc_arguments);
1074         OopMap* oop_map = save_live_registers(sasm);
1075         const Register trap_request = R1;
1076         __ ldr(trap_request, Address(SP, arg1_offset));
1077         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize), trap_request);
1078         oop_maps = new OopMapSet();
1079         oop_maps->add_gc_map(call_offset, oop_map);
1080         restore_live_registers_without_return(sasm);
1081         DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1082         assert(deopt_blob != NULL, "deoptimization blob must have been created");
1083         __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, AARCH64_ONLY(Rtemp) NOT_AARCH64(noreg));
1084       }
1085       break;
1086 
1087     case access_field_patching_id:
1088       {
1089         __ set_info("access_field_patching", dont_gc_arguments);
1090         oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching));
1091       }
1092       break;
1093 
1094     case load_klass_patching_id:
1095       {
1096         __ set_info("load_klass_patching", dont_gc_arguments);
1097         oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching));
1098       }
1099       break;
1100 
1101     case load_appendix_patching_id:
1102       {
1103         __ set_info("load_appendix_patching", dont_gc_arguments);
1104         oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching));
1105       }
1106       break;
1107 
1108     case load_mirror_patching_id:
1109       {
1110         __ set_info("load_mirror_patching", dont_gc_arguments);
1111         oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching));
1112       }
1113       break;
1114 
1115     case predicate_failed_trap_id:
1116       {
1117         __ set_info("predicate_failed_trap", dont_gc_arguments);
1118 
1119         OopMap* oop_map = save_live_registers(sasm);
1120         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap));
1121 
1122         oop_maps = new OopMapSet();
1123         oop_maps->add_gc_map(call_offset, oop_map);
1124 
1125         restore_live_registers_without_return(sasm);
1126 
1127         DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1128         assert(deopt_blob != NULL, "deoptimization blob must have been created");
1129         __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, Rtemp);
1130       }
1131       break;
1132 
1133     default:
1134       {
1135         __ set_info("unimplemented entry", dont_gc_arguments);
1136         STOP("unimplemented entry");
1137       }
1138       break;
1139   }
1140   return oop_maps;
1141 }
1142 
1143 #undef __
1144 
1145 #ifdef __SOFTFP__
1146 const char *Runtime1::pd_name_for_address(address entry) {
1147 
1148 #define FUNCTION_CASE(a, f) \
1149   if ((intptr_t)a == CAST_FROM_FN_PTR(intptr_t, f))  return #f
1150 
1151   FUNCTION_CASE(entry, __aeabi_fadd_glibc);
1152   FUNCTION_CASE(entry, __aeabi_fmul);
1153   FUNCTION_CASE(entry, __aeabi_fsub_glibc);
1154   FUNCTION_CASE(entry, __aeabi_fdiv);
1155 
1156   // __aeabi_XXXX_glibc: Imported code from glibc soft-fp bundle for calculation accuracy improvement. See CR 6757269.
1157   FUNCTION_CASE(entry, __aeabi_dadd_glibc);
1158   FUNCTION_CASE(entry, __aeabi_dmul);
1159   FUNCTION_CASE(entry, __aeabi_dsub_glibc);
1160   FUNCTION_CASE(entry, __aeabi_ddiv);
1161 
1162   FUNCTION_CASE(entry, __aeabi_f2d);
1163   FUNCTION_CASE(entry, __aeabi_d2f);
1164   FUNCTION_CASE(entry, __aeabi_i2f);
1165   FUNCTION_CASE(entry, __aeabi_i2d);
1166   FUNCTION_CASE(entry, __aeabi_f2iz);
1167 
1168   FUNCTION_CASE(entry, SharedRuntime::fcmpl);
1169   FUNCTION_CASE(entry, SharedRuntime::fcmpg);
1170   FUNCTION_CASE(entry, SharedRuntime::dcmpl);
1171   FUNCTION_CASE(entry, SharedRuntime::dcmpg);
1172 
1173   FUNCTION_CASE(entry, SharedRuntime::unordered_fcmplt);
1174   FUNCTION_CASE(entry, SharedRuntime::unordered_dcmplt);
1175   FUNCTION_CASE(entry, SharedRuntime::unordered_fcmple);
1176   FUNCTION_CASE(entry, SharedRuntime::unordered_dcmple);
1177   FUNCTION_CASE(entry, SharedRuntime::unordered_fcmpge);
1178   FUNCTION_CASE(entry, SharedRuntime::unordered_dcmpge);
1179   FUNCTION_CASE(entry, SharedRuntime::unordered_fcmpgt);
1180   FUNCTION_CASE(entry, SharedRuntime::unordered_dcmpgt);
1181 
1182   FUNCTION_CASE(entry, SharedRuntime::fneg);
1183   FUNCTION_CASE(entry, SharedRuntime::dneg);
1184 
1185   FUNCTION_CASE(entry, __aeabi_fcmpeq);
1186   FUNCTION_CASE(entry, __aeabi_fcmplt);
1187   FUNCTION_CASE(entry, __aeabi_fcmple);
1188   FUNCTION_CASE(entry, __aeabi_fcmpge);
1189   FUNCTION_CASE(entry, __aeabi_fcmpgt);
1190 
1191   FUNCTION_CASE(entry, __aeabi_dcmpeq);
1192   FUNCTION_CASE(entry, __aeabi_dcmplt);
1193   FUNCTION_CASE(entry, __aeabi_dcmple);
1194   FUNCTION_CASE(entry, __aeabi_dcmpge);
1195   FUNCTION_CASE(entry, __aeabi_dcmpgt);
1196 #undef FUNCTION_CASE
1197   return "";
1198 }
1199 #else  // __SOFTFP__
1200 const char *Runtime1::pd_name_for_address(address entry) {
1201   return "<unknown function>";
1202 }
1203 #endif // __SOFTFP__
--- EOF ---