2240 case Op_SubVI:
2241 case Op_SubVF:
2242 case Op_SubVD:
2243 case Op_MulVS:
2244 case Op_MulVF:
2245 case Op_MulVD:
2246 case Op_DivVF:
2247 case Op_DivVD:
2248 case Op_AbsVF:
2249 case Op_AbsVD:
2250 case Op_NegVF:
2251 case Op_NegVD:
2252 case Op_SqrtVF:
2253 case Op_SqrtVD:
2254 case Op_AddVL:
2255 case Op_SubVL:
2256 case Op_MulVI:
2257 return SuperwordUseVSX;
2258 case Op_PopCountVI:
2259 return (SuperwordUseVSX && UsePopCountInstruction);
2260 }
2261
2262 return true; // Per default match rules are supported.
2263 }
2264
2265 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2266
2267 // TODO
2268 // identify extra cases that we might want to provide match rules for
2269 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2270 bool ret_value = match_rule_supported(opcode);
2271 // Add rules here.
2272
2273 return ret_value; // Per default match rules are supported.
2274 }
2275
2276 const bool Matcher::has_predicated_vectors(void) {
2277 return false;
2278 }
2279
12381 // registers for new nodes
12382 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12383 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12384
12385 // Insert new nodes.
12386 nodes->push(m1);
12387 nodes->push(m2);
12388 %}
12389 %}
12390
12391 // Compare double, generate -1,0,1
12392 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
12393 match(Set dst (CmpD3 src1 src2));
12394 ins_cost(DEFAULT_COST*5+BRANCH_COST);
12395
12396 expand %{
12397 flagsReg tmp1;
12398 cmpDUnordered_reg_reg(tmp1, src1, src2);
12399 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
12400 %}
12401 %}
12402
12403 //----------Branches---------------------------------------------------------
12404 // Jump
12405
12406 // Direct Branch.
12407 instruct branch(label labl) %{
12408 match(Goto);
12409 effect(USE labl);
12410 ins_cost(BRANCH_COST);
12411
12412 format %{ "B $labl" %}
12413 size(4);
12414 ins_encode %{
12415 // TODO: PPC port $archOpcode(ppc64Opcode_b);
12416 Label d; // dummy
12417 __ bind(d);
12418 Label* p = $labl$$label;
12419 // `p' is `NULL' when this encoding class is used only to
12420 // determine the size of the encoded instruction.
|
2240 case Op_SubVI:
2241 case Op_SubVF:
2242 case Op_SubVD:
2243 case Op_MulVS:
2244 case Op_MulVF:
2245 case Op_MulVD:
2246 case Op_DivVF:
2247 case Op_DivVD:
2248 case Op_AbsVF:
2249 case Op_AbsVD:
2250 case Op_NegVF:
2251 case Op_NegVD:
2252 case Op_SqrtVF:
2253 case Op_SqrtVD:
2254 case Op_AddVL:
2255 case Op_SubVL:
2256 case Op_MulVI:
2257 return SuperwordUseVSX;
2258 case Op_PopCountVI:
2259 return (SuperwordUseVSX && UsePopCountInstruction);
2260 case Op_Digit:
2261 case Op_LowerCase:
2262 case Op_UpperCase:
2263 case Op_Whitespace:
2264 return (UseCharacterCompareIntrinsics && VM_Version::has_darn());
2265 }
2266
2267 return true; // Per default match rules are supported.
2268 }
2269
2270 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2271
2272 // TODO
2273 // identify extra cases that we might want to provide match rules for
2274 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2275 bool ret_value = match_rule_supported(opcode);
2276 // Add rules here.
2277
2278 return ret_value; // Per default match rules are supported.
2279 }
2280
2281 const bool Matcher::has_predicated_vectors(void) {
2282 return false;
2283 }
2284
12386 // registers for new nodes
12387 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12388 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12389
12390 // Insert new nodes.
12391 nodes->push(m1);
12392 nodes->push(m2);
12393 %}
12394 %}
12395
12396 // Compare double, generate -1,0,1
12397 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
12398 match(Set dst (CmpD3 src1 src2));
12399 ins_cost(DEFAULT_COST*5+BRANCH_COST);
12400
12401 expand %{
12402 flagsReg tmp1;
12403 cmpDUnordered_reg_reg(tmp1, src1, src2);
12404 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
12405 %}
12406 %}
12407
12408 // Compare char
12409 instruct cmprb_Digit_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
12410 match(Set dst (Digit src1));
12411 effect(TEMP src2, TEMP crx);
12412 ins_cost(3 * DEFAULT_COST);
12413
12414 format %{ "LI $src2, 0x3930\n\t"
12415 "CMPRB $crx, 0, $src1, $src2\n\t"
12416 "SETB $dst, $crx" %}
12417 size(12);
12418 ins_encode %{
12419 // 0x30: 0, 0x39: 9
12420 __ li($src2$$Register, 0x3930);
12421 // compare src1 with ranges 0x30 to 0x39
12422 __ cmprb($crx$$CondRegister, 0, $src1$$Register, $src2$$Register);
12423 __ setb($dst$$Register, $crx$$CondRegister);
12424 %}
12425 ins_pipe(pipe_class_default);
12426 %}
12427
12428 instruct cmprb_LowerCase_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
12429 match(Set dst (LowerCase src1));
12430 effect(TEMP src2, TEMP crx);
12431 ins_cost(12 * DEFAULT_COST);
12432
12433 format %{ "LI $src2, 0x7A61\n\t"
12434 "CMPRB $crx, 0, $src1, $src2\n\t"
12435 "BGT $crx, done\n\t"
12436 "LIS $src2, (signed short)0xF6DF\n\t"
12437 "ORI $src2, $src2, 0xFFF8\n\t"
12438 "CMPRB $crx, 1, $src1, $src2\n\t"
12439 "BGT $crx, done\n\t"
12440 "LIS $src2, (signed short)0xAAB5\n\t"
12441 "ORI $src2, $src2, 0xBABA\n\t"
12442 "INSRDI $src2, $src2, 32, 0\n\t"
12443 "CMPEQB $crx, 1, $src1, $src2\n"
12444 "done:\n\t"
12445 "SETB $dst, $crx" %}
12446
12447 size(48);
12448 ins_encode %{
12449 Label done;
12450 // 0x61: a, 0x7A: z
12451 __ li($src2$$Register, 0x7A61);
12452 // compare src1 with ranges 0x61 to 0x7A
12453 __ cmprb($crx$$CondRegister, 0, $src1$$Register, $src2$$Register);
12454 __ bgt($crx$$CondRegister, done);
12455
12456 // 0xDF: sharp s, 0xFF: y with diaeresis, 0xF7 is not the lower case
12457 __ lis($src2$$Register, (signed short)0xF6DF);
12458 __ ori($src2$$Register, $src2$$Register, 0xFFF8);
12459 // compare src1 with ranges 0xDF to 0xF6 and 0xF8 to 0xFF
12460 __ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
12461 __ bgt($crx$$CondRegister, done);
12462
12463 // 0xAA: feminine ordinal indicator
12464 // 0xB5: micro sign
12465 // 0xBA: masculine ordinal indicator
12466 __ lis($src2$$Register, (signed short)0xAAB5);
12467 __ ori($src2$$Register, $src2$$Register, 0xBABA);
12468 __ insrdi($src2$$Register, $src2$$Register, 32, 0);
12469 // compare src1 with 0xAA, 0xB5, and 0xBA
12470 __ cmpeqb($crx$$CondRegister, $src1$$Register, $src2$$Register);
12471
12472 __ bind(done);
12473 __ setb($dst$$Register, $crx$$CondRegister);
12474 %}
12475 ins_pipe(pipe_class_default);
12476 %}
12477
12478 instruct cmprb_UpperCase_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
12479 match(Set dst (UpperCase src1));
12480 effect(TEMP src2, TEMP crx);
12481 ins_cost(7 * DEFAULT_COST);
12482
12483 format %{ "LI $src2, 0x5A41\n\t"
12484 "CMPRB $crx, 0, $src1, $src2\n\t"
12485 "BGT $crx, done\n\t"
12486 "LIS $src2, (signed short)0xD6C0\n\t"
12487 "ORI $src2, $src2, 0xDED8\n\t"
12488 "CMPRB $crx, 1, $src1, $src2\n"
12489 "done:\n\t"
12490 "SETB $dst, $crx" %}
12491
12492 size(28);
12493 ins_encode %{
12494 Label done;
12495 // 0x41: A, 0x5A: Z
12496 __ li($src2$$Register, 0x5A41);
12497 // compare src1 with a range 0x41 to 0x5A
12498 __ cmprb($crx$$CondRegister, 0, $src1$$Register, $src2$$Register);
12499 __ bgt($crx$$CondRegister, done);
12500
12501 // 0xC0: a with grave, 0xDE: thorn, 0xD7 is not the upper case
12502 __ lis($src2$$Register, (signed short)0xD6C0);
12503 __ ori($src2$$Register, $src2$$Register, 0xDED8);
12504 // compare src1 with ranges 0xC0 to 0xD6 and 0xD8 to 0xDE
12505 __ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
12506
12507 __ bind(done);
12508 __ setb($dst$$Register, $crx$$CondRegister);
12509 %}
12510 ins_pipe(pipe_class_default);
12511 %}
12512
12513 instruct cmprb_Whitespace_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
12514 match(Set dst (Whitespace src1));
12515 effect(TEMP src2, TEMP crx);
12516 ins_cost(4 * DEFAULT_COST);
12517
12518 format %{ "LI $src2, 0x0D09\n\t"
12519 "ADDIS $src2, 0x201C\n\t"
12520 "CMPRB $crx, 1, $src1, $src2\n\t"
12521 "SETB $dst, $crx" %}
12522 size(16);
12523 ins_encode %{
12524 // 0x09 to 0x0D, 0x1C to 0x20
12525 __ li($src2$$Register, 0x0D09);
12526 __ addis($src2$$Register, $src2$$Register, 0x0201C);
12527 // compare src with ranges 0x09 to 0x0D and 0x1C to 0x20
12528 __ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
12529 __ setb($dst$$Register, $crx$$CondRegister);
12530 %}
12531 ins_pipe(pipe_class_default);
12532 %}
12533
12534 //----------Branches---------------------------------------------------------
12535 // Jump
12536
12537 // Direct Branch.
12538 instruct branch(label labl) %{
12539 match(Goto);
12540 effect(USE labl);
12541 ins_cost(BRANCH_COST);
12542
12543 format %{ "B $labl" %}
12544 size(4);
12545 ins_encode %{
12546 // TODO: PPC port $archOpcode(ppc64Opcode_b);
12547 Label d; // dummy
12548 __ bind(d);
12549 Label* p = $labl$$label;
12550 // `p' is `NULL' when this encoding class is used only to
12551 // determine the size of the encoded instruction.
|