2214 break;
2215 case Op_CountTrailingZerosI:
2216 case Op_CountTrailingZerosL:
2217 if (!UseCountLeadingZerosInstructionsPPC64 &&
2218 !UseCountTrailingZerosInstructionsPPC64)
2219 return false;
2220 break;
2221
2222 case Op_PopCountI:
2223 case Op_PopCountL:
2224 return (UsePopCountInstruction && VM_Version::has_popcntw());
2225
2226 case Op_StrComp:
2227 return SpecialStringCompareTo;
2228 case Op_StrEquals:
2229 return SpecialStringEquals;
2230 case Op_StrIndexOf:
2231 return SpecialStringIndexOf;
2232 case Op_StrIndexOfChar:
2233 return SpecialStringIndexOf;
2234 }
2235
2236 return true; // Per default match rules are supported.
2237 }
2238
2239 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2240
2241 // TODO
2242 // identify extra cases that we might want to provide match rules for
2243 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2244 bool ret_value = match_rule_supported(opcode);
2245 // Add rules here.
2246
2247 return ret_value; // Per default match rules are supported.
2248 }
2249
2250 const bool Matcher::has_predicated_vectors(void) {
2251 return false;
2252 }
2253
12355 // registers for new nodes
12356 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12357 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12358
12359 // Insert new nodes.
12360 nodes->push(m1);
12361 nodes->push(m2);
12362 %}
12363 %}
12364
12365 // Compare double, generate -1,0,1
12366 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
12367 match(Set dst (CmpD3 src1 src2));
12368 ins_cost(DEFAULT_COST*5+BRANCH_COST);
12369
12370 expand %{
12371 flagsReg tmp1;
12372 cmpDUnordered_reg_reg(tmp1, src1, src2);
12373 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
12374 %}
12375 %}
12376
12377 //----------Branches---------------------------------------------------------
12378 // Jump
12379
12380 // Direct Branch.
12381 instruct branch(label labl) %{
12382 match(Goto);
12383 effect(USE labl);
12384 ins_cost(BRANCH_COST);
12385
12386 format %{ "B $labl" %}
12387 size(4);
12388 ins_encode %{
12389 // TODO: PPC port $archOpcode(ppc64Opcode_b);
12390 Label d; // dummy
12391 __ bind(d);
12392 Label* p = $labl$$label;
12393 // `p' is `NULL' when this encoding class is used only to
12394 // determine the size of the encoded instruction.
|
2214 break;
2215 case Op_CountTrailingZerosI:
2216 case Op_CountTrailingZerosL:
2217 if (!UseCountLeadingZerosInstructionsPPC64 &&
2218 !UseCountTrailingZerosInstructionsPPC64)
2219 return false;
2220 break;
2221
2222 case Op_PopCountI:
2223 case Op_PopCountL:
2224 return (UsePopCountInstruction && VM_Version::has_popcntw());
2225
2226 case Op_StrComp:
2227 return SpecialStringCompareTo;
2228 case Op_StrEquals:
2229 return SpecialStringEquals;
2230 case Op_StrIndexOf:
2231 return SpecialStringIndexOf;
2232 case Op_StrIndexOfChar:
2233 return SpecialStringIndexOf;
2234
2235 case Op_Digit:
2236 case Op_LowerCase:
2237 case Op_UpperCase:
2238 case Op_Whitespace:
2239 return UseCharacterCompareIntrinsics;
2240 }
2241
2242 return true; // Per default match rules are supported.
2243 }
2244
2245 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2246
2247 // TODO
2248 // identify extra cases that we might want to provide match rules for
2249 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2250 bool ret_value = match_rule_supported(opcode);
2251 // Add rules here.
2252
2253 return ret_value; // Per default match rules are supported.
2254 }
2255
2256 const bool Matcher::has_predicated_vectors(void) {
2257 return false;
2258 }
2259
12361 // registers for new nodes
12362 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12363 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12364
12365 // Insert new nodes.
12366 nodes->push(m1);
12367 nodes->push(m2);
12368 %}
12369 %}
12370
12371 // Compare double, generate -1,0,1
12372 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
12373 match(Set dst (CmpD3 src1 src2));
12374 ins_cost(DEFAULT_COST*5+BRANCH_COST);
12375
12376 expand %{
12377 flagsReg tmp1;
12378 cmpDUnordered_reg_reg(tmp1, src1, src2);
12379 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
12380 %}
12381 %}
12382
12383 // Compare char
12384 instruct cmprb_Digit_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
12385 match(Set dst (Digit src1));
12386 effect(TEMP src2, TEMP crx);
12387 ins_cost(3 * DEFAULT_COST);
12388
12389 format %{ "LI $src2, 0x3930\n\t"
12390 "CMPRB $crx, 0, $src1, $src2\n\t"
12391 "SETB $dst, $crx" %}
12392 size(12);
12393 ins_encode %{
12394 // 0x30: 0, 0x39: 9
12395 __ li($src2$$Register, 0x3930);
12396 // compare src1 with ranges 0x30 to 0x39
12397 __ cmprb($crx$$CondRegister, 0, $src1$$Register, $src2$$Register);
12398 __ setb($dst$$Register, $crx$$CondRegister);
12399 %}
12400 ins_pipe(pipe_class_default);
12401 %}
12402
12403 instruct cmprb_LowerCase_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
12404 match(Set dst (LowerCase src1));
12405 effect(TEMP src2, TEMP crx);
12406 ins_cost(12 * DEFAULT_COST);
12407
12408 format %{ "LI $src2, 0x7A61\n\t"
12409 "CMPRB $crx, 0, $src1, $src2\n\t"
12410 "BGT $crx, done\n\t"
12411 "LIS $src2, (signed short)0xF6DF\n\t"
12412 "ORI $src2, $src2, 0xFFF8\n\t"
12413 "CMPRB $crx, 1, $src1, $src2\n\t"
12414 "BGT $crx, done\n\t"
12415 "LIS $src2, (signed short)0xAAB5\n\t"
12416 "ORI $src2, $src2, 0xBABA\n\t"
12417 "INSRDI $src2, $src2, 32, 0\n\t"
12418 "CMPEQB $crx, 1, $src1, $src2\n"
12419 "done:\n\t"
12420 "SETB $dst, $crx" %}
12421
12422 size(48);
12423 ins_encode %{
12424 Label done;
12425 // 0x61: a, 0x7A: z
12426 __ li($src2$$Register, 0x7A61);
12427 // compare src1 with ranges 0x61 to 0x7A
12428 __ cmprb($crx$$CondRegister, 0, $src1$$Register, $src2$$Register);
12429 __ bgt($crx$$CondRegister, done);
12430
12431 // 0xDF: sharp s, 0xFF: y with diaeresis, 0xF7 is not the lower case
12432 __ lis($src2$$Register, (signed short)0xF6DF);
12433 __ ori($src2$$Register, $src2$$Register, 0xFFF8);
12434 // compare src1 with ranges 0xDF to 0xF6 and 0xF8 to 0xFF
12435 __ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
12436 __ bgt($crx$$CondRegister, done);
12437
12438 // 0xAA: feminine ordinal indicator
12439 // 0xB5: micro sign
12440 // 0xBA: masculine ordinal indicator
12441 __ lis($src2$$Register, (signed short)0xAAB5);
12442 __ ori($src2$$Register, $src2$$Register, 0xBABA);
12443 __ insrdi($src2$$Register, $src2$$Register, 32, 0);
12444 // compare src1 with 0xAA, 0xB5, and 0xBA
12445 __ cmpeqb($crx$$CondRegister, $src1$$Register, $src2$$Register);
12446
12447 __ bind(done);
12448 __ setb($dst$$Register, $crx$$CondRegister);
12449 %}
12450 ins_pipe(pipe_class_default);
12451 %}
12452
12453 instruct cmprb_UpperCase_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
12454 match(Set dst (UpperCase src1));
12455 effect(TEMP src2, TEMP crx);
12456 ins_cost(7 * DEFAULT_COST);
12457
12458 format %{ "LI $src2, 0x5A41\n\t"
12459 "CMPRB $crx, 0, $src1, $src2\n\t"
12460 "BGT $crx, done\n\t"
12461 "LIS $src2, (signed short)0xD6C0\n\t"
12462 "ORI $src2, $src2, 0xDED8\n\t"
12463 "CMPRB $crx, 1, $src1, $src2\n"
12464 "done:\n\t"
12465 "SETB $dst, $crx" %}
12466
12467 size(28);
12468 ins_encode %{
12469 Label done;
12470 // 0x41: A, 0x5A: Z
12471 __ li($src2$$Register, 0x5A41);
12472 // compare src1 with a range 0x41 to 0x5A
12473 __ cmprb($crx$$CondRegister, 0, $src1$$Register, $src2$$Register);
12474 __ bgt($crx$$CondRegister, done);
12475
12476 // 0xC0: a with grave, 0xDE: thorn, 0xD7 is not the upper case
12477 __ lis($src2$$Register, (signed short)0xD6C0);
12478 __ ori($src2$$Register, $src2$$Register, 0xDED8);
12479 // compare src1 with ranges 0xC0 to 0xD6 and 0xD8 to 0xDE
12480 __ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
12481
12482 __ bind(done);
12483 __ setb($dst$$Register, $crx$$CondRegister);
12484 %}
12485 ins_pipe(pipe_class_default);
12486 %}
12487
12488 instruct cmprb_Whitespace_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
12489 match(Set dst (Whitespace src1));
12490 effect(TEMP src2, TEMP crx);
12491 ins_cost(4 * DEFAULT_COST);
12492
12493 format %{ "LI $src2, 0x0D09\n\t"
12494 "ADDIS $src2, 0x201C\n\t"
12495 "CMPRB $crx, 1, $src1, $src2\n\t"
12496 "SETB $dst, $crx" %}
12497 size(16);
12498 ins_encode %{
12499 // 0x09 to 0x0D, 0x1C to 0x20
12500 __ li($src2$$Register, 0x0D09);
12501 __ addis($src2$$Register, $src2$$Register, 0x0201C);
12502 // compare src with ranges 0x09 to 0x0D and 0x1C to 0x20
12503 __ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
12504 __ setb($dst$$Register, $crx$$CondRegister);
12505 %}
12506 ins_pipe(pipe_class_default);
12507 %}
12508
12509 //----------Branches---------------------------------------------------------
12510 // Jump
12511
12512 // Direct Branch.
12513 instruct branch(label labl) %{
12514 match(Goto);
12515 effect(USE labl);
12516 ins_cost(BRANCH_COST);
12517
12518 format %{ "B $labl" %}
12519 size(4);
12520 ins_encode %{
12521 // TODO: PPC port $archOpcode(ppc64Opcode_b);
12522 Label d; // dummy
12523 __ bind(d);
12524 Label* p = $labl$$label;
12525 // `p' is `NULL' when this encoding class is used only to
12526 // determine the size of the encoded instruction.
|