1 /*
2 * Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_LIRAssembler.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "c1/c1_ValueStack.hpp"
31 #include "ci/ciArrayKlass.hpp"
32 #include "ci/ciInstance.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/cardTableModRefBS.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "nativeInst_sparc.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/sharedRuntime.hpp"
39
40 #define __ _masm->
41
42
43 //------------------------------------------------------------
44
45
46 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
47 if (opr->is_constant()) {
48 LIR_Const* constant = opr->as_constant_ptr();
49 switch (constant->type()) {
50 case T_INT: {
51 jint value = constant->as_jint();
52 return Assembler::is_simm13(value);
53 }
54
55 default:
56 return false;
57 }
58 }
59 return false;
60 }
61
62
63 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
64 switch (op->code()) {
65 case lir_null_check:
66 return true;
67
68
69 case lir_add:
70 case lir_ushr:
71 case lir_shr:
72 case lir_shl:
73 // integer shifts and adds are always one instruction
74 return op->result_opr()->is_single_cpu();
75
76
77 case lir_move: {
78 LIR_Op1* op1 = op->as_Op1();
79 LIR_Opr src = op1->in_opr();
80 LIR_Opr dst = op1->result_opr();
81
82 if (src == dst) {
83 NEEDS_CLEANUP;
84 // this works around a problem where moves with the same src and dst
85 // end up in the delay slot and then the assembler swallows the mov
86 // since it has no effect and then it complains because the delay slot
87 // is empty. returning false stops the optimizer from putting this in
88 // the delay slot
89 return false;
90 }
91
92 // don't put moves involving oops into the delay slot since the VerifyOops code
93 // will make it much larger than a single instruction.
94 if (VerifyOops) {
95 return false;
96 }
97
98 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
99 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
100 return false;
101 }
102
103 if (UseCompressedOops) {
104 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;
105 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;
106 }
107
108 if (UseCompressedClassPointers) {
109 if (src->is_address() && !src->is_stack() && src->type() == T_ADDRESS &&
110 src->as_address_ptr()->disp() == oopDesc::klass_offset_in_bytes()) return false;
111 }
112
113 if (dst->is_register()) {
114 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
115 return !PatchALot;
116 } else if (src->is_single_stack()) {
117 return true;
118 }
119 }
120
121 if (src->is_register()) {
122 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
123 return !PatchALot;
124 } else if (dst->is_single_stack()) {
125 return true;
126 }
127 }
128
129 if (dst->is_register() &&
130 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
131 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
132 return true;
133 }
134
135 return false;
136 }
137
138 default:
139 return false;
140 }
141 ShouldNotReachHere();
142 }
143
144
145 LIR_Opr LIR_Assembler::receiverOpr() {
146 return FrameMap::O0_oop_opr;
147 }
148
149
150 LIR_Opr LIR_Assembler::osrBufferPointer() {
151 return FrameMap::I0_opr;
152 }
153
154
155 int LIR_Assembler::initial_frame_size_in_bytes() const {
156 return in_bytes(frame_map()->framesize_in_bytes());
157 }
158
159
160 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
161 // we fetch the class of the receiver (O0) and compare it with the cached class.
162 // If they do not match we jump to slow case.
163 int LIR_Assembler::check_icache() {
164 int offset = __ offset();
165 __ inline_cache_check(O0, G5_inline_cache_reg);
166 return offset;
167 }
168
169
170 void LIR_Assembler::osr_entry() {
171 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
172 //
173 // 1. Create a new compiled activation.
174 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
175 // at the osr_bci; it is not initialized.
176 // 3. Jump to the continuation address in compiled code to resume execution.
177
178 // OSR entry point
179 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
180 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
181 ValueStack* entry_state = osr_entry->end()->state();
182 int number_of_locks = entry_state->locks_size();
183
184 // Create a frame for the compiled activation.
185 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
186
187 // OSR buffer is
188 //
189 // locals[nlocals-1..0]
190 // monitors[number_of_locks-1..0]
191 //
192 // locals is a direct copy of the interpreter frame so in the osr buffer
193 // so first slot in the local array is the last local from the interpreter
194 // and last slot is local[0] (receiver) from the interpreter
195 //
196 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
197 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
198 // in the interpreter frame (the method lock if a sync method)
199
200 // Initialize monitors in the compiled activation.
201 // I0: pointer to osr buffer
202 //
203 // All other registers are dead at this point and the locals will be
204 // copied into place by code emitted in the IR.
205
206 Register OSR_buf = osrBufferPointer()->as_register();
207 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
208 int monitor_offset = BytesPerWord * method()->max_locals() +
209 (2 * BytesPerWord) * (number_of_locks - 1);
210 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
211 // the OSR buffer using 2 word entries: first the lock and then
212 // the oop.
213 for (int i = 0; i < number_of_locks; i++) {
214 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
215 #ifdef ASSERT
216 // verify the interpreter's monitor has a non-null object
217 {
218 Label L;
219 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
220 __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L);
221 __ stop("locked object is NULL");
222 __ bind(L);
223 }
224 #endif // ASSERT
225 // Copy the lock field into the compiled activation.
226 __ ld_ptr(OSR_buf, slot_offset + 0, O7);
227 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
228 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
229 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
230 }
231 }
232 }
233
234
235 // --------------------------------------------------------------------------------------------
236
237 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
238 if (!GenerateSynchronizationCode) return;
239
240 Register obj_reg = obj_opr->as_register();
241 Register lock_reg = lock_opr->as_register();
242
243 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
244 Register reg = mon_addr.base();
245 int offset = mon_addr.disp();
246 // compute pointer to BasicLock
247 if (mon_addr.is_simm13()) {
248 __ add(reg, offset, lock_reg);
249 }
250 else {
251 __ set(offset, lock_reg);
252 __ add(reg, lock_reg, lock_reg);
253 }
254 // unlock object
255 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
256 // _slow_case_stubs->append(slow_case);
257 // temporary fix: must be created after exceptionhandler, therefore as call stub
258 _slow_case_stubs->append(slow_case);
259 if (UseFastLocking) {
260 // try inlined fast unlocking first, revert to slow locking if it fails
261 // note: lock_reg points to the displaced header since the displaced header offset is 0!
262 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
263 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
264 } else {
265 // always do slow unlocking
266 // note: the slow unlocking code could be inlined here, however if we use
267 // slow unlocking, speed doesn't matter anyway and this solution is
268 // simpler and requires less duplicated code - additionally, the
269 // slow unlocking code is the same in either case which simplifies
270 // debugging
271 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
272 __ delayed()->nop();
273 }
274 // done
275 __ bind(*slow_case->continuation());
276 }
277
278
279 int LIR_Assembler::emit_exception_handler() {
280 // if the last instruction is a call (typically to do a throw which
281 // is coming at the end after block reordering) the return address
282 // must still point into the code area in order to avoid assertion
283 // failures when searching for the corresponding bci => add a nop
284 // (was bug 5/14/1999 - gri)
285 __ nop();
286
287 // generate code for exception handler
288 ciMethod* method = compilation()->method();
289
290 address handler_base = __ start_a_stub(exception_handler_size());
291
292 if (handler_base == NULL) {
293 // not enough space left for the handler
294 bailout("exception handler overflow");
295 return -1;
296 }
297
298 int offset = code_offset();
299
300 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
301 __ delayed()->nop();
302 __ should_not_reach_here();
303 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
304 __ end_a_stub();
305
306 return offset;
307 }
308
309
310 // Emit the code to remove the frame from the stack in the exception
311 // unwind path.
312 int LIR_Assembler::emit_unwind_handler() {
313 #ifndef PRODUCT
314 if (CommentedAssembly) {
315 _masm->block_comment("Unwind handler");
316 }
317 #endif
318
319 int offset = code_offset();
320
321 // Fetch the exception from TLS and clear out exception related thread state
322 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);
323 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
324 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
325
326 __ bind(_unwind_handler_entry);
327 __ verify_not_null_oop(O0);
328 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
329 __ mov(O0, I0); // Preserve the exception
330 }
331
332 // Preform needed unlocking
333 MonitorExitStub* stub = NULL;
334 if (method()->is_synchronized()) {
335 monitor_address(0, FrameMap::I1_opr);
336 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);
337 __ unlock_object(I3, I2, I1, *stub->entry());
338 __ bind(*stub->continuation());
339 }
340
341 if (compilation()->env()->dtrace_method_probes()) {
342 __ mov(G2_thread, O0);
343 __ save_thread(I1); // need to preserve thread in G2 across
344 // runtime call
345 metadata2reg(method()->constant_encoding(), O1);
346 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);
347 __ delayed()->nop();
348 __ restore_thread(I1);
349 }
350
351 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
352 __ mov(I0, O0); // Restore the exception
353 }
354
355 // dispatch to the unwind logic
356 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
357 __ delayed()->nop();
358
359 // Emit the slow path assembly
360 if (stub != NULL) {
361 stub->emit_code(this);
362 }
363
364 return offset;
365 }
366
367
368 int LIR_Assembler::emit_deopt_handler() {
369 // if the last instruction is a call (typically to do a throw which
370 // is coming at the end after block reordering) the return address
371 // must still point into the code area in order to avoid assertion
372 // failures when searching for the corresponding bci => add a nop
373 // (was bug 5/14/1999 - gri)
374 __ nop();
375
376 // generate code for deopt handler
377 ciMethod* method = compilation()->method();
378 address handler_base = __ start_a_stub(deopt_handler_size());
379 if (handler_base == NULL) {
380 // not enough space left for the handler
381 bailout("deopt handler overflow");
382 return -1;
383 }
384
385 int offset = code_offset();
386 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
387 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
388 __ delayed()->nop();
389 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
390 __ end_a_stub();
391
392 return offset;
393 }
394
395
396 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
397 if (o == NULL) {
398 __ set(NULL_WORD, reg);
399 } else {
400 int oop_index = __ oop_recorder()->find_index(o);
401 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(o)), "should be real oop");
402 RelocationHolder rspec = oop_Relocation::spec(oop_index);
403 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
404 }
405 }
406
407
408 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
409 // Allocate a new index in table to hold the object once it's been patched
410 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
411 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
412
413 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
414 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
415 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
416 // NULL will be dynamically patched later and the patched value may be large. We must
417 // therefore generate the sethi/add as a placeholders
418 __ patchable_set(addrlit, reg);
419
420 patching_epilog(patch, lir_patch_normal, reg, info);
421 }
422
423
424 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
425 __ set_metadata_constant(o, reg);
426 }
427
428 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
429 // Allocate a new index in table to hold the klass once it's been patched
430 int index = __ oop_recorder()->allocate_metadata_index(NULL);
431 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
432 AddressLiteral addrlit(NULL, metadata_Relocation::spec(index));
433 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
434 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
435 // NULL will be dynamically patched later and the patched value may be large. We must
436 // therefore generate the sethi/add as a placeholders
437 __ patchable_set(addrlit, reg);
438
439 patching_epilog(patch, lir_patch_normal, reg, info);
440 }
441
442 void LIR_Assembler::emit_op3(LIR_Op3* op) {
443 Register Rdividend = op->in_opr1()->as_register();
444 Register Rdivisor = noreg;
445 Register Rscratch = op->in_opr3()->as_register();
446 Register Rresult = op->result_opr()->as_register();
447 int divisor = -1;
448
449 if (op->in_opr2()->is_register()) {
450 Rdivisor = op->in_opr2()->as_register();
451 } else {
452 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
453 assert(Assembler::is_simm13(divisor), "can only handle simm13");
454 }
455
456 assert(Rdividend != Rscratch, "");
457 assert(Rdivisor != Rscratch, "");
458 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
459
460 if (Rdivisor == noreg && is_power_of_2(divisor)) {
461 // convert division by a power of two into some shifts and logical operations
462 if (op->code() == lir_idiv) {
463 if (divisor == 2) {
464 __ srl(Rdividend, 31, Rscratch);
465 } else {
466 __ sra(Rdividend, 31, Rscratch);
467 __ and3(Rscratch, divisor - 1, Rscratch);
468 }
469 __ add(Rdividend, Rscratch, Rscratch);
470 __ sra(Rscratch, log2_intptr(divisor), Rresult);
471 return;
472 } else {
473 if (divisor == 2) {
474 __ srl(Rdividend, 31, Rscratch);
475 } else {
476 __ sra(Rdividend, 31, Rscratch);
477 __ and3(Rscratch, divisor - 1,Rscratch);
478 }
479 __ add(Rdividend, Rscratch, Rscratch);
480 __ andn(Rscratch, divisor - 1,Rscratch);
481 __ sub(Rdividend, Rscratch, Rresult);
482 return;
483 }
484 }
485
486 __ sra(Rdividend, 31, Rscratch);
487 __ wry(Rscratch);
488
489 add_debug_info_for_div0_here(op->info());
490
491 if (Rdivisor != noreg) {
492 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
493 } else {
494 assert(Assembler::is_simm13(divisor), "can only handle simm13");
495 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
496 }
497
498 Label skip;
499 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
500 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
501 __ bind(skip);
502
503 if (op->code() == lir_irem) {
504 if (Rdivisor != noreg) {
505 __ smul(Rscratch, Rdivisor, Rscratch);
506 } else {
507 __ smul(Rscratch, divisor, Rscratch);
508 }
509 __ sub(Rdividend, Rscratch, Rresult);
510 }
511 }
512
513
514 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
515 #ifdef ASSERT
516 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
517 if (op->block() != NULL) _branch_target_blocks.append(op->block());
518 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
519 #endif
520 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
521
522 if (op->cond() == lir_cond_always) {
523 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
524 } else if (op->code() == lir_cond_float_branch) {
525 assert(op->ublock() != NULL, "must have unordered successor");
526 bool is_unordered = (op->ublock() == op->block());
527 Assembler::Condition acond;
528 switch (op->cond()) {
529 case lir_cond_equal: acond = Assembler::f_equal; break;
530 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
531 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
532 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
533 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
534 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
535 default : ShouldNotReachHere();
536 }
537 __ fb( acond, false, Assembler::pn, *(op->label()));
538 } else {
539 assert (op->code() == lir_branch, "just checking");
540
541 Assembler::Condition acond;
542 switch (op->cond()) {
543 case lir_cond_equal: acond = Assembler::equal; break;
544 case lir_cond_notEqual: acond = Assembler::notEqual; break;
545 case lir_cond_less: acond = Assembler::less; break;
546 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
547 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
548 case lir_cond_greater: acond = Assembler::greater; break;
549 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
550 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
551 default: ShouldNotReachHere();
552 };
553
554 // sparc has different condition codes for testing 32-bit
555 // vs. 64-bit values. We could always test xcc is we could
556 // guarantee that 32-bit loads always sign extended but that isn't
557 // true and since sign extension isn't free, it would impose a
558 // slight cost.
559 if (op->type() == T_INT) {
560 __ br(acond, false, Assembler::pn, *(op->label()));
561 } else
562 __ brx(acond, false, Assembler::pn, *(op->label()));
563 }
564 // The peephole pass fills the delay slot
565 }
566
567
568 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
569 Bytecodes::Code code = op->bytecode();
570 LIR_Opr dst = op->result_opr();
571
572 switch(code) {
573 case Bytecodes::_i2l: {
574 Register rlo = dst->as_register_lo();
575 Register rhi = dst->as_register_hi();
576 Register rval = op->in_opr()->as_register();
577 __ sra(rval, 0, rlo);
578 break;
579 }
580 case Bytecodes::_i2d:
581 case Bytecodes::_i2f: {
582 bool is_double = (code == Bytecodes::_i2d);
583 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
584 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
585 FloatRegister rsrc = op->in_opr()->as_float_reg();
586 if (rsrc != rdst) {
587 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
588 }
589 __ fitof(w, rdst, rdst);
590 break;
591 }
592 case Bytecodes::_f2i:{
593 FloatRegister rsrc = op->in_opr()->as_float_reg();
594 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
595 Label L;
596 // result must be 0 if value is NaN; test by comparing value to itself
597 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
598 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
599 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
600 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
601 // move integer result from float register to int register
602 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
603 __ bind (L);
604 break;
605 }
606 case Bytecodes::_l2i: {
607 Register rlo = op->in_opr()->as_register_lo();
608 Register rhi = op->in_opr()->as_register_hi();
609 Register rdst = dst->as_register();
610 __ sra(rlo, 0, rdst);
611 break;
612 }
613 case Bytecodes::_d2f:
614 case Bytecodes::_f2d: {
615 bool is_double = (code == Bytecodes::_f2d);
616 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
617 LIR_Opr val = op->in_opr();
618 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
619 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
620 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
621 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
622 __ ftof(vw, dw, rval, rdst);
623 break;
624 }
625 case Bytecodes::_i2s:
626 case Bytecodes::_i2b: {
627 Register rval = op->in_opr()->as_register();
628 Register rdst = dst->as_register();
629 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
630 __ sll (rval, shift, rdst);
631 __ sra (rdst, shift, rdst);
632 break;
633 }
634 case Bytecodes::_i2c: {
635 Register rval = op->in_opr()->as_register();
636 Register rdst = dst->as_register();
637 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
638 __ sll (rval, shift, rdst);
639 __ srl (rdst, shift, rdst);
640 break;
641 }
642
643 default: ShouldNotReachHere();
644 }
645 }
646
647
648 void LIR_Assembler::align_call(LIR_Code) {
649 // do nothing since all instructions are word aligned on sparc
650 }
651
652
653 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
654 __ call(op->addr(), rtype);
655 // The peephole pass fills the delay slot, add_call_info is done in
656 // LIR_Assembler::emit_delay.
657 }
658
659
660 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
661 __ ic_call(op->addr(), false);
662 // The peephole pass fills the delay slot, add_call_info is done in
663 // LIR_Assembler::emit_delay.
664 }
665
666
667 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
668 add_debug_info_for_null_check_here(op->info());
669 __ load_klass(O0, G3_scratch);
670 if (Assembler::is_simm13(op->vtable_offset())) {
671 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
672 } else {
673 // This will generate 2 instructions
674 __ set(op->vtable_offset(), G5_method);
675 // ld_ptr, set_hi, set
676 __ ld_ptr(G3_scratch, G5_method, G5_method);
677 }
678 __ ld_ptr(G5_method, Method::from_compiled_offset(), G3_scratch);
679 __ callr(G3_scratch, G0);
680 // the peephole pass fills the delay slot
681 }
682
683 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
684 int store_offset;
685 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
686 assert(base != O7, "destroying register");
687 assert(!unaligned, "can't handle this");
688 // for offsets larger than a simm13 we setup the offset in O7
689 __ set(offset, O7);
690 store_offset = store(from_reg, base, O7, type, wide);
691 } else {
692 if (type == T_ARRAY || type == T_OBJECT) {
693 __ verify_oop(from_reg->as_register());
694 }
695 store_offset = code_offset();
696 switch (type) {
697 case T_BOOLEAN: // fall through
698 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
699 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
700 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
701 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
702 case T_LONG :
703 if (unaligned || PatchALot) {
704 // Don't use O7 here because it may be equal to 'base' (see LIR_Assembler::reg2mem)
705 assert(G3_scratch != base, "can't handle this");
706 assert(G3_scratch != from_reg->as_register_lo(), "can't handle this");
707 __ srax(from_reg->as_register_lo(), 32, G3_scratch);
708 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
709 __ stw(G3_scratch, base, offset + hi_word_offset_in_bytes);
710 } else {
711 __ stx(from_reg->as_register_lo(), base, offset);
712 }
713 break;
714 case T_ADDRESS:
715 case T_METADATA:
716 __ st_ptr(from_reg->as_register(), base, offset);
717 break;
718 case T_ARRAY : // fall through
719 case T_OBJECT:
720 {
721 if (UseCompressedOops && !wide) {
722 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
723 store_offset = code_offset();
724 __ stw(G3_scratch, base, offset);
725 } else {
726 __ st_ptr(from_reg->as_register(), base, offset);
727 }
728 break;
729 }
730
731 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
732 case T_DOUBLE:
733 {
734 FloatRegister reg = from_reg->as_double_reg();
735 // split unaligned stores
736 if (unaligned || PatchALot) {
737 assert(Assembler::is_simm13(offset + 4), "must be");
738 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
739 __ stf(FloatRegisterImpl::S, reg, base, offset);
740 } else {
741 __ stf(FloatRegisterImpl::D, reg, base, offset);
742 }
743 break;
744 }
745 default : ShouldNotReachHere();
746 }
747 }
748 return store_offset;
749 }
750
751
752 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
753 if (type == T_ARRAY || type == T_OBJECT) {
754 __ verify_oop(from_reg->as_register());
755 }
756 int store_offset = code_offset();
757 switch (type) {
758 case T_BOOLEAN: // fall through
759 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
760 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
761 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
762 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
763 case T_LONG :
764 __ stx(from_reg->as_register_lo(), base, disp);
765 break;
766 case T_ADDRESS:
767 __ st_ptr(from_reg->as_register(), base, disp);
768 break;
769 case T_ARRAY : // fall through
770 case T_OBJECT:
771 {
772 if (UseCompressedOops && !wide) {
773 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
774 store_offset = code_offset();
775 __ stw(G3_scratch, base, disp);
776 } else {
777 __ st_ptr(from_reg->as_register(), base, disp);
778 }
779 break;
780 }
781 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
782 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
783 default : ShouldNotReachHere();
784 }
785 return store_offset;
786 }
787
788
789 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
790 int load_offset;
791 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
792 assert(base != O7, "destroying register");
793 assert(!unaligned, "can't handle this");
794 // for offsets larger than a simm13 we setup the offset in O7
795 __ set(offset, O7);
796 load_offset = load(base, O7, to_reg, type, wide);
797 } else {
798 load_offset = code_offset();
799 switch(type) {
800 case T_BOOLEAN: // fall through
801 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
802 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
803 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
804 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
805 case T_LONG :
806 if (!unaligned && !PatchALot) {
807 __ ldx(base, offset, to_reg->as_register_lo());
808 } else {
809 assert(base != to_reg->as_register_lo(), "can't handle this");
810 assert(O7 != to_reg->as_register_lo(), "can't handle this");
811 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
812 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
813 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
814 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
815 }
816 break;
817 case T_METADATA: __ ld_ptr(base, offset, to_reg->as_register()); break;
818 case T_ADDRESS:
819 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
820 __ lduw(base, offset, to_reg->as_register());
821 __ decode_klass_not_null(to_reg->as_register());
822 } else
823 {
824 __ ld_ptr(base, offset, to_reg->as_register());
825 }
826 break;
827 case T_ARRAY : // fall through
828 case T_OBJECT:
829 {
830 if (UseCompressedOops && !wide) {
831 __ lduw(base, offset, to_reg->as_register());
832 __ decode_heap_oop(to_reg->as_register());
833 } else {
834 __ ld_ptr(base, offset, to_reg->as_register());
835 }
836 break;
837 }
838 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
839 case T_DOUBLE:
840 {
841 FloatRegister reg = to_reg->as_double_reg();
842 // split unaligned loads
843 if (unaligned || PatchALot) {
844 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
845 __ ldf(FloatRegisterImpl::S, base, offset, reg);
846 } else {
847 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
848 }
849 break;
850 }
851 default : ShouldNotReachHere();
852 }
853 if (type == T_ARRAY || type == T_OBJECT) {
854 __ verify_oop(to_reg->as_register());
855 }
856 }
857 return load_offset;
858 }
859
860
861 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
862 int load_offset = code_offset();
863 switch(type) {
864 case T_BOOLEAN: // fall through
865 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
866 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
867 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
868 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
869 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
870 case T_ARRAY : // fall through
871 case T_OBJECT:
872 {
873 if (UseCompressedOops && !wide) {
874 __ lduw(base, disp, to_reg->as_register());
875 __ decode_heap_oop(to_reg->as_register());
876 } else {
877 __ ld_ptr(base, disp, to_reg->as_register());
878 }
879 break;
880 }
881 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
882 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
883 case T_LONG :
884 __ ldx(base, disp, to_reg->as_register_lo());
885 break;
886 default : ShouldNotReachHere();
887 }
888 if (type == T_ARRAY || type == T_OBJECT) {
889 __ verify_oop(to_reg->as_register());
890 }
891 return load_offset;
892 }
893
894 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
895 LIR_Const* c = src->as_constant_ptr();
896 switch (c->type()) {
897 case T_INT:
898 case T_FLOAT: {
899 Register src_reg = O7;
900 int value = c->as_jint_bits();
901 if (value == 0) {
902 src_reg = G0;
903 } else {
904 __ set(value, O7);
905 }
906 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
907 __ stw(src_reg, addr.base(), addr.disp());
908 break;
909 }
910 case T_ADDRESS: {
911 Register src_reg = O7;
912 int value = c->as_jint_bits();
913 if (value == 0) {
914 src_reg = G0;
915 } else {
916 __ set(value, O7);
917 }
918 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
919 __ st_ptr(src_reg, addr.base(), addr.disp());
920 break;
921 }
922 case T_OBJECT: {
923 Register src_reg = O7;
924 jobject2reg(c->as_jobject(), src_reg);
925 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
926 __ st_ptr(src_reg, addr.base(), addr.disp());
927 break;
928 }
929 case T_LONG:
930 case T_DOUBLE: {
931 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
932
933 Register tmp = O7;
934 int value_lo = c->as_jint_lo_bits();
935 if (value_lo == 0) {
936 tmp = G0;
937 } else {
938 __ set(value_lo, O7);
939 }
940 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
941 int value_hi = c->as_jint_hi_bits();
942 if (value_hi == 0) {
943 tmp = G0;
944 } else {
945 __ set(value_hi, O7);
946 }
947 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
948 break;
949 }
950 default:
951 Unimplemented();
952 }
953 }
954
955
956 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
957 LIR_Const* c = src->as_constant_ptr();
958 LIR_Address* addr = dest->as_address_ptr();
959 Register base = addr->base()->as_pointer_register();
960 int offset = -1;
961
962 switch (c->type()) {
963 case T_INT:
964 case T_FLOAT:
965 case T_ADDRESS: {
966 LIR_Opr tmp = FrameMap::O7_opr;
967 int value = c->as_jint_bits();
968 if (value == 0) {
969 tmp = FrameMap::G0_opr;
970 } else if (Assembler::is_simm13(value)) {
971 __ set(value, O7);
972 }
973 if (addr->index()->is_valid()) {
974 assert(addr->disp() == 0, "must be zero");
975 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
976 } else {
977 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
978 offset = store(tmp, base, addr->disp(), type, wide, false);
979 }
980 break;
981 }
982 case T_LONG:
983 case T_DOUBLE: {
984 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
985 assert(Assembler::is_simm13(addr->disp()) &&
986 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
987
988 LIR_Opr tmp = FrameMap::O7_opr;
989 int value_lo = c->as_jint_lo_bits();
990 if (value_lo == 0) {
991 tmp = FrameMap::G0_opr;
992 } else {
993 __ set(value_lo, O7);
994 }
995 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false);
996 int value_hi = c->as_jint_hi_bits();
997 if (value_hi == 0) {
998 tmp = FrameMap::G0_opr;
999 } else {
1000 __ set(value_hi, O7);
1001 }
1002 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false);
1003 break;
1004 }
1005 case T_OBJECT: {
1006 jobject obj = c->as_jobject();
1007 LIR_Opr tmp;
1008 if (obj == NULL) {
1009 tmp = FrameMap::G0_opr;
1010 } else {
1011 tmp = FrameMap::O7_opr;
1012 jobject2reg(c->as_jobject(), O7);
1013 }
1014 // handle either reg+reg or reg+disp address
1015 if (addr->index()->is_valid()) {
1016 assert(addr->disp() == 0, "must be zero");
1017 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1018 } else {
1019 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1020 offset = store(tmp, base, addr->disp(), type, wide, false);
1021 }
1022
1023 break;
1024 }
1025 default:
1026 Unimplemented();
1027 }
1028 if (info != NULL) {
1029 assert(offset != -1, "offset should've been set");
1030 add_debug_info_for_null_check(offset, info);
1031 }
1032 }
1033
1034
1035 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1036 LIR_Const* c = src->as_constant_ptr();
1037 LIR_Opr to_reg = dest;
1038
1039 switch (c->type()) {
1040 case T_INT:
1041 case T_ADDRESS:
1042 {
1043 jint con = c->as_jint();
1044 if (to_reg->is_single_cpu()) {
1045 assert(patch_code == lir_patch_none, "no patching handled here");
1046 __ set(con, to_reg->as_register());
1047 } else {
1048 ShouldNotReachHere();
1049 assert(to_reg->is_single_fpu(), "wrong register kind");
1050
1051 __ set(con, O7);
1052 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1053 __ st(O7, temp_slot);
1054 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1055 }
1056 }
1057 break;
1058
1059 case T_LONG:
1060 {
1061 jlong con = c->as_jlong();
1062
1063 if (to_reg->is_double_cpu()) {
1064 __ set(con, to_reg->as_register_lo());
1065 } else if (to_reg->is_single_cpu()) {
1066 __ set(con, to_reg->as_register());
1067 } else {
1068 ShouldNotReachHere();
1069 assert(to_reg->is_double_fpu(), "wrong register kind");
1070 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1071 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1072 __ set(low(con), O7);
1073 __ st(O7, temp_slot_lo);
1074 __ set(high(con), O7);
1075 __ st(O7, temp_slot_hi);
1076 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1077 }
1078 }
1079 break;
1080
1081 case T_OBJECT:
1082 {
1083 if (patch_code == lir_patch_none) {
1084 jobject2reg(c->as_jobject(), to_reg->as_register());
1085 } else {
1086 jobject2reg_with_patching(to_reg->as_register(), info);
1087 }
1088 }
1089 break;
1090
1091 case T_METADATA:
1092 {
1093 if (patch_code == lir_patch_none) {
1094 metadata2reg(c->as_metadata(), to_reg->as_register());
1095 } else {
1096 klass2reg_with_patching(to_reg->as_register(), info);
1097 }
1098 }
1099 break;
1100
1101 case T_FLOAT:
1102 {
1103 address const_addr = __ float_constant(c->as_jfloat());
1104 if (const_addr == NULL) {
1105 bailout("const section overflow");
1106 break;
1107 }
1108 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1109 AddressLiteral const_addrlit(const_addr, rspec);
1110 if (to_reg->is_single_fpu()) {
1111 __ patchable_sethi(const_addrlit, O7);
1112 __ relocate(rspec);
1113 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1114
1115 } else {
1116 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1117
1118 __ set(const_addrlit, O7);
1119 __ ld(O7, 0, to_reg->as_register());
1120 }
1121 }
1122 break;
1123
1124 case T_DOUBLE:
1125 {
1126 address const_addr = __ double_constant(c->as_jdouble());
1127 if (const_addr == NULL) {
1128 bailout("const section overflow");
1129 break;
1130 }
1131 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1132
1133 if (to_reg->is_double_fpu()) {
1134 AddressLiteral const_addrlit(const_addr, rspec);
1135 __ patchable_sethi(const_addrlit, O7);
1136 __ relocate(rspec);
1137 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1138 } else {
1139 assert(to_reg->is_double_cpu(), "Must be a long register.");
1140 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1141 }
1142
1143 }
1144 break;
1145
1146 default:
1147 ShouldNotReachHere();
1148 }
1149 }
1150
1151 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1152 Register reg = addr->base()->as_pointer_register();
1153 LIR_Opr index = addr->index();
1154 if (index->is_illegal()) {
1155 return Address(reg, addr->disp());
1156 } else {
1157 assert (addr->disp() == 0, "unsupported address mode");
1158 return Address(reg, index->as_pointer_register());
1159 }
1160 }
1161
1162
1163 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1164 switch (type) {
1165 case T_INT:
1166 case T_FLOAT: {
1167 Register tmp = O7;
1168 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1169 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1170 __ lduw(from.base(), from.disp(), tmp);
1171 __ stw(tmp, to.base(), to.disp());
1172 break;
1173 }
1174 case T_OBJECT: {
1175 Register tmp = O7;
1176 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1177 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1178 __ ld_ptr(from.base(), from.disp(), tmp);
1179 __ st_ptr(tmp, to.base(), to.disp());
1180 break;
1181 }
1182 case T_LONG:
1183 case T_DOUBLE: {
1184 Register tmp = O7;
1185 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1186 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1187 __ lduw(from.base(), from.disp(), tmp);
1188 __ stw(tmp, to.base(), to.disp());
1189 __ lduw(from.base(), from.disp() + 4, tmp);
1190 __ stw(tmp, to.base(), to.disp() + 4);
1191 break;
1192 }
1193
1194 default:
1195 ShouldNotReachHere();
1196 }
1197 }
1198
1199
1200 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1201 Address base = as_Address(addr);
1202 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1203 }
1204
1205
1206 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1207 Address base = as_Address(addr);
1208 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1209 }
1210
1211
1212 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1213 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1214
1215 assert(type != T_METADATA, "load of metadata ptr not supported");
1216 LIR_Address* addr = src_opr->as_address_ptr();
1217 LIR_Opr to_reg = dest;
1218
1219 Register src = addr->base()->as_pointer_register();
1220 Register disp_reg = noreg;
1221 int disp_value = addr->disp();
1222 bool needs_patching = (patch_code != lir_patch_none);
1223
1224 if (addr->base()->type() == T_OBJECT) {
1225 __ verify_oop(src);
1226 }
1227
1228 PatchingStub* patch = NULL;
1229 if (needs_patching) {
1230 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1231 assert(!to_reg->is_double_cpu() ||
1232 patch_code == lir_patch_none ||
1233 patch_code == lir_patch_normal, "patching doesn't match register");
1234 }
1235
1236 if (addr->index()->is_illegal()) {
1237 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1238 if (needs_patching) {
1239 __ patchable_set(0, O7);
1240 } else {
1241 __ set(disp_value, O7);
1242 }
1243 disp_reg = O7;
1244 }
1245 } else if (unaligned || PatchALot) {
1246 __ add(src, addr->index()->as_pointer_register(), O7);
1247 src = O7;
1248 } else {
1249 disp_reg = addr->index()->as_pointer_register();
1250 assert(disp_value == 0, "can't handle 3 operand addresses");
1251 }
1252
1253 // remember the offset of the load. The patching_epilog must be done
1254 // before the call to add_debug_info, otherwise the PcDescs don't get
1255 // entered in increasing order.
1256 int offset = code_offset();
1257
1258 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1259 if (disp_reg == noreg) {
1260 offset = load(src, disp_value, to_reg, type, wide, unaligned);
1261 } else {
1262 assert(!unaligned, "can't handle this");
1263 offset = load(src, disp_reg, to_reg, type, wide);
1264 }
1265
1266 if (patch != NULL) {
1267 patching_epilog(patch, patch_code, src, info);
1268 }
1269 if (info != NULL) add_debug_info_for_null_check(offset, info);
1270 }
1271
1272
1273 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1274 Address addr;
1275 if (src->is_single_word()) {
1276 addr = frame_map()->address_for_slot(src->single_stack_ix());
1277 } else if (src->is_double_word()) {
1278 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1279 }
1280
1281 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1282 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1283 }
1284
1285
1286 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1287 Address addr;
1288 if (dest->is_single_word()) {
1289 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1290 } else if (dest->is_double_word()) {
1291 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1292 }
1293 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1294 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1295 }
1296
1297
1298 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1299 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1300 if (from_reg->is_double_fpu()) {
1301 // double to double moves
1302 assert(to_reg->is_double_fpu(), "should match");
1303 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1304 } else {
1305 // float to float moves
1306 assert(to_reg->is_single_fpu(), "should match");
1307 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1308 }
1309 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1310 if (from_reg->is_double_cpu()) {
1311 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1312 } else if (to_reg->is_double_cpu()) {
1313 // int to int moves
1314 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1315 } else {
1316 // int to int moves
1317 __ mov(from_reg->as_register(), to_reg->as_register());
1318 }
1319 } else {
1320 ShouldNotReachHere();
1321 }
1322 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1323 __ verify_oop(to_reg->as_register());
1324 }
1325 }
1326
1327
1328 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1329 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1330 bool wide, bool unaligned) {
1331 assert(type != T_METADATA, "store of metadata ptr not supported");
1332 LIR_Address* addr = dest->as_address_ptr();
1333
1334 Register src = addr->base()->as_pointer_register();
1335 Register disp_reg = noreg;
1336 int disp_value = addr->disp();
1337 bool needs_patching = (patch_code != lir_patch_none);
1338
1339 if (addr->base()->is_oop_register()) {
1340 __ verify_oop(src);
1341 }
1342
1343 PatchingStub* patch = NULL;
1344 if (needs_patching) {
1345 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1346 assert(!from_reg->is_double_cpu() ||
1347 patch_code == lir_patch_none ||
1348 patch_code == lir_patch_normal, "patching doesn't match register");
1349 }
1350
1351 if (addr->index()->is_illegal()) {
1352 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1353 if (needs_patching) {
1354 __ patchable_set(0, O7);
1355 } else {
1356 __ set(disp_value, O7);
1357 }
1358 disp_reg = O7;
1359 }
1360 } else if (unaligned || PatchALot) {
1361 __ add(src, addr->index()->as_pointer_register(), O7);
1362 src = O7;
1363 } else {
1364 disp_reg = addr->index()->as_pointer_register();
1365 assert(disp_value == 0, "can't handle 3 operand addresses");
1366 }
1367
1368 // remember the offset of the store. The patching_epilog must be done
1369 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1370 // entered in increasing order.
1371 int offset;
1372
1373 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1374 if (disp_reg == noreg) {
1375 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1376 } else {
1377 assert(!unaligned, "can't handle this");
1378 offset = store(from_reg, src, disp_reg, type, wide);
1379 }
1380
1381 if (patch != NULL) {
1382 patching_epilog(patch, patch_code, src, info);
1383 }
1384
1385 if (info != NULL) add_debug_info_for_null_check(offset, info);
1386 }
1387
1388
1389 void LIR_Assembler::return_op(LIR_Opr result) {
1390 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1391 __ reserved_stack_check();
1392 }
1393 // the poll may need a register so just pick one that isn't the return register
1394 __ set((intptr_t)os::get_polling_page(), L0);
1395 __ relocate(relocInfo::poll_return_type);
1396 __ ld_ptr(L0, 0, G0);
1397 __ ret();
1398 __ delayed()->restore();
1399 }
1400
1401
1402 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1403 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1404 if (info != NULL) {
1405 add_debug_info_for_branch(info);
1406 }
1407 int offset = __ offset();
1408 __ relocate(relocInfo::poll_type);
1409 __ ld_ptr(tmp->as_register(), 0, G0);
1410 return offset;
1411 }
1412
1413
1414 void LIR_Assembler::emit_static_call_stub() {
1415 address call_pc = __ pc();
1416 address stub = __ start_a_stub(call_stub_size());
1417 if (stub == NULL) {
1418 bailout("static call stub overflow");
1419 return;
1420 }
1421
1422 int start = __ offset();
1423 __ relocate(static_stub_Relocation::spec(call_pc));
1424
1425 __ set_metadata(NULL, G5);
1426 // must be set to -1 at code generation time
1427 AddressLiteral addrlit(-1);
1428 __ jump_to(addrlit, G3);
1429 __ delayed()->nop();
1430
1431 assert(__ offset() - start <= call_stub_size(), "stub too big");
1432 __ end_a_stub();
1433 }
1434
1435
1436 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1437 if (opr1->is_single_fpu()) {
1438 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1439 } else if (opr1->is_double_fpu()) {
1440 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1441 } else if (opr1->is_single_cpu()) {
1442 if (opr2->is_constant()) {
1443 switch (opr2->as_constant_ptr()->type()) {
1444 case T_INT:
1445 { jint con = opr2->as_constant_ptr()->as_jint();
1446 if (Assembler::is_simm13(con)) {
1447 __ cmp(opr1->as_register(), con);
1448 } else {
1449 __ set(con, O7);
1450 __ cmp(opr1->as_register(), O7);
1451 }
1452 }
1453 break;
1454
1455 case T_OBJECT:
1456 // there are only equal/notequal comparisions on objects
1457 { jobject con = opr2->as_constant_ptr()->as_jobject();
1458 if (con == NULL) {
1459 __ cmp(opr1->as_register(), 0);
1460 } else {
1461 jobject2reg(con, O7);
1462 __ cmp(opr1->as_register(), O7);
1463 }
1464 }
1465 break;
1466
1467 default:
1468 ShouldNotReachHere();
1469 break;
1470 }
1471 } else {
1472 if (opr2->is_address()) {
1473 LIR_Address * addr = opr2->as_address_ptr();
1474 BasicType type = addr->type();
1475 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1476 else __ ld(as_Address(addr), O7);
1477 __ cmp(opr1->as_register(), O7);
1478 } else {
1479 __ cmp(opr1->as_register(), opr2->as_register());
1480 }
1481 }
1482 } else if (opr1->is_double_cpu()) {
1483 Register xlo = opr1->as_register_lo();
1484 Register xhi = opr1->as_register_hi();
1485 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1486 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1487 __ orcc(xhi, G0, G0);
1488 } else if (opr2->is_register()) {
1489 Register ylo = opr2->as_register_lo();
1490 Register yhi = opr2->as_register_hi();
1491 __ cmp(xlo, ylo);
1492 } else {
1493 ShouldNotReachHere();
1494 }
1495 } else if (opr1->is_address()) {
1496 LIR_Address * addr = opr1->as_address_ptr();
1497 BasicType type = addr->type();
1498 assert (opr2->is_constant(), "Checking");
1499 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1500 else __ ld(as_Address(addr), O7);
1501 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1502 } else {
1503 ShouldNotReachHere();
1504 }
1505 }
1506
1507
1508 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1509 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1510 bool is_unordered_less = (code == lir_ucmp_fd2i);
1511 if (left->is_single_fpu()) {
1512 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1513 } else if (left->is_double_fpu()) {
1514 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1515 } else {
1516 ShouldNotReachHere();
1517 }
1518 } else if (code == lir_cmp_l2i) {
1519 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1520 } else {
1521 ShouldNotReachHere();
1522 }
1523 }
1524
1525
1526 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1527 Assembler::Condition acond;
1528 switch (condition) {
1529 case lir_cond_equal: acond = Assembler::equal; break;
1530 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1531 case lir_cond_less: acond = Assembler::less; break;
1532 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1533 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1534 case lir_cond_greater: acond = Assembler::greater; break;
1535 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1536 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1537 default: ShouldNotReachHere();
1538 };
1539
1540 if (opr1->is_constant() && opr1->type() == T_INT) {
1541 Register dest = result->as_register();
1542 // load up first part of constant before branch
1543 // and do the rest in the delay slot.
1544 if (!Assembler::is_simm13(opr1->as_jint())) {
1545 __ sethi(opr1->as_jint(), dest);
1546 }
1547 } else if (opr1->is_constant()) {
1548 const2reg(opr1, result, lir_patch_none, NULL);
1549 } else if (opr1->is_register()) {
1550 reg2reg(opr1, result);
1551 } else if (opr1->is_stack()) {
1552 stack2reg(opr1, result, result->type());
1553 } else {
1554 ShouldNotReachHere();
1555 }
1556 Label skip;
1557 if (type == T_INT) {
1558 __ br(acond, false, Assembler::pt, skip);
1559 } else
1560 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
1561 if (opr1->is_constant() && opr1->type() == T_INT) {
1562 Register dest = result->as_register();
1563 if (Assembler::is_simm13(opr1->as_jint())) {
1564 __ delayed()->or3(G0, opr1->as_jint(), dest);
1565 } else {
1566 // the sethi has been done above, so just put in the low 10 bits
1567 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1568 }
1569 } else {
1570 // can't do anything useful in the delay slot
1571 __ delayed()->nop();
1572 }
1573 if (opr2->is_constant()) {
1574 const2reg(opr2, result, lir_patch_none, NULL);
1575 } else if (opr2->is_register()) {
1576 reg2reg(opr2, result);
1577 } else if (opr2->is_stack()) {
1578 stack2reg(opr2, result, result->type());
1579 } else {
1580 ShouldNotReachHere();
1581 }
1582 __ bind(skip);
1583 }
1584
1585
1586 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1587 assert(info == NULL, "unused on this code path");
1588 assert(left->is_register(), "wrong items state");
1589 assert(dest->is_register(), "wrong items state");
1590
1591 if (right->is_register()) {
1592 if (dest->is_float_kind()) {
1593
1594 FloatRegister lreg, rreg, res;
1595 FloatRegisterImpl::Width w;
1596 if (right->is_single_fpu()) {
1597 w = FloatRegisterImpl::S;
1598 lreg = left->as_float_reg();
1599 rreg = right->as_float_reg();
1600 res = dest->as_float_reg();
1601 } else {
1602 w = FloatRegisterImpl::D;
1603 lreg = left->as_double_reg();
1604 rreg = right->as_double_reg();
1605 res = dest->as_double_reg();
1606 }
1607
1608 switch (code) {
1609 case lir_add: __ fadd(w, lreg, rreg, res); break;
1610 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1611 case lir_mul: // fall through
1612 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1613 case lir_div: // fall through
1614 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1615 default: ShouldNotReachHere();
1616 }
1617
1618 } else if (dest->is_double_cpu()) {
1619 Register dst_lo = dest->as_register_lo();
1620 Register op1_lo = left->as_pointer_register();
1621 Register op2_lo = right->as_pointer_register();
1622
1623 switch (code) {
1624 case lir_add:
1625 __ add(op1_lo, op2_lo, dst_lo);
1626 break;
1627
1628 case lir_sub:
1629 __ sub(op1_lo, op2_lo, dst_lo);
1630 break;
1631
1632 default: ShouldNotReachHere();
1633 }
1634 } else {
1635 assert (right->is_single_cpu(), "Just Checking");
1636
1637 Register lreg = left->as_register();
1638 Register res = dest->as_register();
1639 Register rreg = right->as_register();
1640 switch (code) {
1641 case lir_add: __ add (lreg, rreg, res); break;
1642 case lir_sub: __ sub (lreg, rreg, res); break;
1643 case lir_mul: __ mulx (lreg, rreg, res); break;
1644 default: ShouldNotReachHere();
1645 }
1646 }
1647 } else {
1648 assert (right->is_constant(), "must be constant");
1649
1650 if (dest->is_single_cpu()) {
1651 Register lreg = left->as_register();
1652 Register res = dest->as_register();
1653 int simm13 = right->as_constant_ptr()->as_jint();
1654
1655 switch (code) {
1656 case lir_add: __ add (lreg, simm13, res); break;
1657 case lir_sub: __ sub (lreg, simm13, res); break;
1658 case lir_mul: __ mulx (lreg, simm13, res); break;
1659 default: ShouldNotReachHere();
1660 }
1661 } else {
1662 Register lreg = left->as_pointer_register();
1663 Register res = dest->as_register_lo();
1664 long con = right->as_constant_ptr()->as_jlong();
1665 assert(Assembler::is_simm13(con), "must be simm13");
1666
1667 switch (code) {
1668 case lir_add: __ add (lreg, (int)con, res); break;
1669 case lir_sub: __ sub (lreg, (int)con, res); break;
1670 case lir_mul: __ mulx (lreg, (int)con, res); break;
1671 default: ShouldNotReachHere();
1672 }
1673 }
1674 }
1675 }
1676
1677
1678 void LIR_Assembler::fpop() {
1679 // do nothing
1680 }
1681
1682
1683 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1684 switch (code) {
1685 case lir_tan: {
1686 assert(thread->is_valid(), "preserve the thread object for performance reasons");
1687 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1688 break;
1689 }
1690 case lir_sqrt: {
1691 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1692 FloatRegister src_reg = value->as_double_reg();
1693 FloatRegister dst_reg = dest->as_double_reg();
1694 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1695 break;
1696 }
1697 case lir_abs: {
1698 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1699 FloatRegister src_reg = value->as_double_reg();
1700 FloatRegister dst_reg = dest->as_double_reg();
1701 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1702 break;
1703 }
1704 default: {
1705 ShouldNotReachHere();
1706 break;
1707 }
1708 }
1709 }
1710
1711
1712 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1713 if (right->is_constant()) {
1714 if (dest->is_single_cpu()) {
1715 int simm13 = right->as_constant_ptr()->as_jint();
1716 switch (code) {
1717 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1718 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1719 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1720 default: ShouldNotReachHere();
1721 }
1722 } else {
1723 long c = right->as_constant_ptr()->as_jlong();
1724 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1725 int simm13 = (int)c;
1726 switch (code) {
1727 case lir_logic_and:
1728 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1729 break;
1730
1731 case lir_logic_or:
1732 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1733 break;
1734
1735 case lir_logic_xor:
1736 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1737 break;
1738
1739 default: ShouldNotReachHere();
1740 }
1741 }
1742 } else {
1743 assert(right->is_register(), "right should be in register");
1744
1745 if (dest->is_single_cpu()) {
1746 switch (code) {
1747 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1748 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1749 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1750 default: ShouldNotReachHere();
1751 }
1752 } else {
1753 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1754 left->as_register_lo();
1755 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1756 right->as_register_lo();
1757
1758 switch (code) {
1759 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
1760 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
1761 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
1762 default: ShouldNotReachHere();
1763 }
1764 }
1765 }
1766 }
1767
1768
1769 int LIR_Assembler::shift_amount(BasicType t) {
1770 int elem_size = type2aelembytes(t);
1771 switch (elem_size) {
1772 case 1 : return 0;
1773 case 2 : return 1;
1774 case 4 : return 2;
1775 case 8 : return 3;
1776 }
1777 ShouldNotReachHere();
1778 return -1;
1779 }
1780
1781
1782 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1783 assert(exceptionOop->as_register() == Oexception, "should match");
1784 assert(exceptionPC->as_register() == Oissuing_pc, "should match");
1785
1786 info->add_register_oop(exceptionOop);
1787
1788 // reuse the debug info from the safepoint poll for the throw op itself
1789 address pc_for_athrow = __ pc();
1790 int pc_for_athrow_offset = __ offset();
1791 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1792 __ set(pc_for_athrow, Oissuing_pc, rspec);
1793 add_call_info(pc_for_athrow_offset, info); // for exception handler
1794
1795 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
1796 __ delayed()->nop();
1797 }
1798
1799
1800 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1801 assert(exceptionOop->as_register() == Oexception, "should match");
1802
1803 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
1804 __ delayed()->nop();
1805 }
1806
1807 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1808 Register src = op->src()->as_register();
1809 Register dst = op->dst()->as_register();
1810 Register src_pos = op->src_pos()->as_register();
1811 Register dst_pos = op->dst_pos()->as_register();
1812 Register length = op->length()->as_register();
1813 Register tmp = op->tmp()->as_register();
1814 Register tmp2 = O7;
1815
1816 int flags = op->flags();
1817 ciArrayKlass* default_type = op->expected_type();
1818 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1819 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1820
1821 // higher 32bits must be null
1822 __ sra(dst_pos, 0, dst_pos);
1823 __ sra(src_pos, 0, src_pos);
1824 __ sra(length, 0, length);
1825
1826 // set up the arraycopy stub information
1827 ArrayCopyStub* stub = op->stub();
1828
1829 // always do stub if no type information is available. it's ok if
1830 // the known type isn't loaded since the code sanity checks
1831 // in debug mode and the type isn't required when we know the exact type
1832 // also check that the type is an array type.
1833 if (op->expected_type() == NULL) {
1834 __ mov(src, O0);
1835 __ mov(src_pos, O1);
1836 __ mov(dst, O2);
1837 __ mov(dst_pos, O3);
1838 __ mov(length, O4);
1839 address copyfunc_addr = StubRoutines::generic_arraycopy();
1840
1841 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
1842 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
1843 } else {
1844 #ifndef PRODUCT
1845 if (PrintC1Statistics) {
1846 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1847 __ inc_counter(counter, G1, G3);
1848 }
1849 #endif
1850 __ call_VM_leaf(tmp, copyfunc_addr);
1851 }
1852
1853 if (copyfunc_addr != NULL) {
1854 __ xor3(O0, -1, tmp);
1855 __ sub(length, tmp, length);
1856 __ add(src_pos, tmp, src_pos);
1857 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
1858 __ delayed()->add(dst_pos, tmp, dst_pos);
1859 } else {
1860 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
1861 __ delayed()->nop();
1862 }
1863 __ bind(*stub->continuation());
1864 return;
1865 }
1866
1867 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1868
1869 // make sure src and dst are non-null and load array length
1870 if (flags & LIR_OpArrayCopy::src_null_check) {
1871 __ tst(src);
1872 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
1873 __ delayed()->nop();
1874 }
1875
1876 if (flags & LIR_OpArrayCopy::dst_null_check) {
1877 __ tst(dst);
1878 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
1879 __ delayed()->nop();
1880 }
1881
1882 // If the compiler was not able to prove that exact type of the source or the destination
1883 // of the arraycopy is an array type, check at runtime if the source or the destination is
1884 // an instance type.
1885 if (flags & LIR_OpArrayCopy::type_check) {
1886 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
1887 __ load_klass(dst, tmp);
1888 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2);
1889 __ cmp(tmp2, Klass::_lh_neutral_value);
1890 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry());
1891 __ delayed()->nop();
1892 }
1893
1894 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
1895 __ load_klass(src, tmp);
1896 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2);
1897 __ cmp(tmp2, Klass::_lh_neutral_value);
1898 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry());
1899 __ delayed()->nop();
1900 }
1901 }
1902
1903 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1904 // test src_pos register
1905 __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry());
1906 __ delayed()->nop();
1907 }
1908
1909 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1910 // test dst_pos register
1911 __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry());
1912 __ delayed()->nop();
1913 }
1914
1915 if (flags & LIR_OpArrayCopy::length_positive_check) {
1916 // make sure length isn't negative
1917 __ cmp_zero_and_br(Assembler::less, length, *stub->entry());
1918 __ delayed()->nop();
1919 }
1920
1921 if (flags & LIR_OpArrayCopy::src_range_check) {
1922 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
1923 __ add(length, src_pos, tmp);
1924 __ cmp(tmp2, tmp);
1925 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
1926 __ delayed()->nop();
1927 }
1928
1929 if (flags & LIR_OpArrayCopy::dst_range_check) {
1930 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
1931 __ add(length, dst_pos, tmp);
1932 __ cmp(tmp2, tmp);
1933 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
1934 __ delayed()->nop();
1935 }
1936
1937 int shift = shift_amount(basic_type);
1938
1939 if (flags & LIR_OpArrayCopy::type_check) {
1940 // We don't know the array types are compatible
1941 if (basic_type != T_OBJECT) {
1942 // Simple test for basic type arrays
1943 if (UseCompressedClassPointers) {
1944 // We don't need decode because we just need to compare
1945 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp);
1946 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
1947 __ cmp(tmp, tmp2);
1948 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
1949 } else {
1950 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
1951 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
1952 __ cmp(tmp, tmp2);
1953 __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry());
1954 }
1955 __ delayed()->nop();
1956 } else {
1957 // For object arrays, if src is a sub class of dst then we can
1958 // safely do the copy.
1959 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1960
1961 Label cont, slow;
1962 assert_different_registers(tmp, tmp2, G3, G1);
1963
1964 __ load_klass(src, G3);
1965 __ load_klass(dst, G1);
1966
1967 __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
1968
1969 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1970 __ delayed()->nop();
1971
1972 __ cmp(G3, 0);
1973 if (copyfunc_addr != NULL) { // use stub if available
1974 // src is not a sub class of dst so we have to do a
1975 // per-element check.
1976 __ br(Assembler::notEqual, false, Assembler::pt, cont);
1977 __ delayed()->nop();
1978
1979 __ bind(slow);
1980
1981 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
1982 if ((flags & mask) != mask) {
1983 // Check that at least both of them object arrays.
1984 assert(flags & mask, "one of the two should be known to be an object array");
1985
1986 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1987 __ load_klass(src, tmp);
1988 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1989 __ load_klass(dst, tmp);
1990 }
1991 int lh_offset = in_bytes(Klass::layout_helper_offset());
1992
1993 __ lduw(tmp, lh_offset, tmp2);
1994
1995 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
1996 __ set(objArray_lh, tmp);
1997 __ cmp(tmp, tmp2);
1998 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
1999 __ delayed()->nop();
2000 }
2001
2002 Register src_ptr = O0;
2003 Register dst_ptr = O1;
2004 Register len = O2;
2005 Register chk_off = O3;
2006 Register super_k = O4;
2007
2008 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2009 if (shift == 0) {
2010 __ add(src_ptr, src_pos, src_ptr);
2011 } else {
2012 __ sll(src_pos, shift, tmp);
2013 __ add(src_ptr, tmp, src_ptr);
2014 }
2015
2016 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2017 if (shift == 0) {
2018 __ add(dst_ptr, dst_pos, dst_ptr);
2019 } else {
2020 __ sll(dst_pos, shift, tmp);
2021 __ add(dst_ptr, tmp, dst_ptr);
2022 }
2023 __ mov(length, len);
2024 __ load_klass(dst, tmp);
2025
2026 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2027 __ ld_ptr(tmp, ek_offset, super_k);
2028
2029 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2030 __ lduw(super_k, sco_offset, chk_off);
2031
2032 __ call_VM_leaf(tmp, copyfunc_addr);
2033
2034 #ifndef PRODUCT
2035 if (PrintC1Statistics) {
2036 Label failed;
2037 __ br_notnull_short(O0, Assembler::pn, failed);
2038 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3);
2039 __ bind(failed);
2040 }
2041 #endif
2042
2043 __ br_null(O0, false, Assembler::pt, *stub->continuation());
2044 __ delayed()->xor3(O0, -1, tmp);
2045
2046 #ifndef PRODUCT
2047 if (PrintC1Statistics) {
2048 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3);
2049 }
2050 #endif
2051
2052 __ sub(length, tmp, length);
2053 __ add(src_pos, tmp, src_pos);
2054 __ br(Assembler::always, false, Assembler::pt, *stub->entry());
2055 __ delayed()->add(dst_pos, tmp, dst_pos);
2056
2057 __ bind(cont);
2058 } else {
2059 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2060 __ delayed()->nop();
2061 __ bind(cont);
2062 }
2063 }
2064 }
2065
2066 #ifdef ASSERT
2067 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2068 // Sanity check the known type with the incoming class. For the
2069 // primitive case the types must match exactly with src.klass and
2070 // dst.klass each exactly matching the default type. For the
2071 // object array case, if no type check is needed then either the
2072 // dst type is exactly the expected type and the src type is a
2073 // subtype which we can't check or src is the same array as dst
2074 // but not necessarily exactly of type default_type.
2075 Label known_ok, halt;
2076 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2077 if (UseCompressedClassPointers) {
2078 // tmp holds the default type. It currently comes uncompressed after the
2079 // load of a constant, so encode it.
2080 __ encode_klass_not_null(tmp);
2081 // load the raw value of the dst klass, since we will be comparing
2082 // uncompressed values directly.
2083 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2084 if (basic_type != T_OBJECT) {
2085 __ cmp(tmp, tmp2);
2086 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2087 // load the raw value of the src klass.
2088 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2);
2089 __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2090 } else {
2091 __ cmp(tmp, tmp2);
2092 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2093 __ delayed()->cmp(src, dst);
2094 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2095 __ delayed()->nop();
2096 }
2097 } else {
2098 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2099 if (basic_type != T_OBJECT) {
2100 __ cmp(tmp, tmp2);
2101 __ brx(Assembler::notEqual, false, Assembler::pn, halt);
2102 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2103 __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2104 } else {
2105 __ cmp(tmp, tmp2);
2106 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2107 __ delayed()->cmp(src, dst);
2108 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2109 __ delayed()->nop();
2110 }
2111 }
2112 __ bind(halt);
2113 __ stop("incorrect type information in arraycopy");
2114 __ bind(known_ok);
2115 }
2116 #endif
2117
2118 #ifndef PRODUCT
2119 if (PrintC1Statistics) {
2120 address counter = Runtime1::arraycopy_count_address(basic_type);
2121 __ inc_counter(counter, G1, G3);
2122 }
2123 #endif
2124
2125 Register src_ptr = O0;
2126 Register dst_ptr = O1;
2127 Register len = O2;
2128
2129 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2130 if (shift == 0) {
2131 __ add(src_ptr, src_pos, src_ptr);
2132 } else {
2133 __ sll(src_pos, shift, tmp);
2134 __ add(src_ptr, tmp, src_ptr);
2135 }
2136
2137 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2138 if (shift == 0) {
2139 __ add(dst_ptr, dst_pos, dst_ptr);
2140 } else {
2141 __ sll(dst_pos, shift, tmp);
2142 __ add(dst_ptr, tmp, dst_ptr);
2143 }
2144
2145 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2146 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2147 const char *name;
2148 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2149
2150 // arraycopy stubs takes a length in number of elements, so don't scale it.
2151 __ mov(length, len);
2152 __ call_VM_leaf(tmp, entry);
2153
2154 __ bind(*stub->continuation());
2155 }
2156
2157
2158 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2159 if (dest->is_single_cpu()) {
2160 if (left->type() == T_OBJECT) {
2161 switch (code) {
2162 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2163 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2164 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2165 default: ShouldNotReachHere();
2166 }
2167 } else
2168 switch (code) {
2169 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2170 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2171 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2172 default: ShouldNotReachHere();
2173 }
2174 } else {
2175 switch (code) {
2176 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2177 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2178 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2179 default: ShouldNotReachHere();
2180 }
2181 }
2182 }
2183
2184
2185 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2186 if (left->type() == T_OBJECT) {
2187 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2188 Register l = left->as_register();
2189 Register d = dest->as_register_lo();
2190 switch (code) {
2191 case lir_shl: __ sllx (l, count, d); break;
2192 case lir_shr: __ srax (l, count, d); break;
2193 case lir_ushr: __ srlx (l, count, d); break;
2194 default: ShouldNotReachHere();
2195 }
2196 return;
2197 }
2198
2199 if (dest->is_single_cpu()) {
2200 count = count & 0x1F; // Java spec
2201 switch (code) {
2202 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2203 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2204 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2205 default: ShouldNotReachHere();
2206 }
2207 } else if (dest->is_double_cpu()) {
2208 count = count & 63; // Java spec
2209 switch (code) {
2210 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2211 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2212 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2213 default: ShouldNotReachHere();
2214 }
2215 } else {
2216 ShouldNotReachHere();
2217 }
2218 }
2219
2220
2221 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2222 assert(op->tmp1()->as_register() == G1 &&
2223 op->tmp2()->as_register() == G3 &&
2224 op->tmp3()->as_register() == G4 &&
2225 op->obj()->as_register() == O0 &&
2226 op->klass()->as_register() == G5, "must be");
2227 if (op->init_check()) {
2228 __ ldub(op->klass()->as_register(),
2229 in_bytes(InstanceKlass::init_state_offset()),
2230 op->tmp1()->as_register());
2231 add_debug_info_for_null_check_here(op->stub()->info());
2232 __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2233 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2234 __ delayed()->nop();
2235 }
2236 __ allocate_object(op->obj()->as_register(),
2237 op->tmp1()->as_register(),
2238 op->tmp2()->as_register(),
2239 op->tmp3()->as_register(),
2240 op->header_size(),
2241 op->object_size(),
2242 op->klass()->as_register(),
2243 *op->stub()->entry());
2244 __ bind(*op->stub()->continuation());
2245 __ verify_oop(op->obj()->as_register());
2246 }
2247
2248
2249 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2250 assert(op->tmp1()->as_register() == G1 &&
2251 op->tmp2()->as_register() == G3 &&
2252 op->tmp3()->as_register() == G4 &&
2253 op->tmp4()->as_register() == O1 &&
2254 op->klass()->as_register() == G5, "must be");
2255
2256 LP64_ONLY( __ signx(op->len()->as_register()); )
2257 if (UseSlowPath ||
2258 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2259 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2260 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2261 __ delayed()->nop();
2262 } else {
2263 __ allocate_array(op->obj()->as_register(),
2264 op->len()->as_register(),
2265 op->tmp1()->as_register(),
2266 op->tmp2()->as_register(),
2267 op->tmp3()->as_register(),
2268 arrayOopDesc::header_size(op->type()),
2269 type2aelembytes(op->type()),
2270 op->klass()->as_register(),
2271 *op->stub()->entry());
2272 }
2273 __ bind(*op->stub()->continuation());
2274 }
2275
2276
2277 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2278 ciMethodData *md, ciProfileData *data,
2279 Register recv, Register tmp1, Label* update_done) {
2280 uint i;
2281 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2282 Label next_test;
2283 // See if the receiver is receiver[n].
2284 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2285 mdo_offset_bias);
2286 __ ld_ptr(receiver_addr, tmp1);
2287 __ verify_klass_ptr(tmp1);
2288 __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test);
2289 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2290 mdo_offset_bias);
2291 __ ld_ptr(data_addr, tmp1);
2292 __ add(tmp1, DataLayout::counter_increment, tmp1);
2293 __ st_ptr(tmp1, data_addr);
2294 __ ba(*update_done);
2295 __ delayed()->nop();
2296 __ bind(next_test);
2297 }
2298
2299 // Didn't find receiver; find next empty slot and fill it in
2300 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2301 Label next_test;
2302 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2303 mdo_offset_bias);
2304 __ ld_ptr(recv_addr, tmp1);
2305 __ br_notnull_short(tmp1, Assembler::pt, next_test);
2306 __ st_ptr(recv, recv_addr);
2307 __ set(DataLayout::counter_increment, tmp1);
2308 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2309 mdo_offset_bias);
2310 __ ba(*update_done);
2311 __ delayed()->nop();
2312 __ bind(next_test);
2313 }
2314 }
2315
2316
2317 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2318 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2319 md = method->method_data_or_null();
2320 assert(md != NULL, "Sanity");
2321 data = md->bci_to_data(bci);
2322 assert(data != NULL, "need data for checkcast");
2323 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2324 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2325 // The offset is large so bias the mdo by the base of the slot so
2326 // that the ld can use simm13s to reference the slots of the data
2327 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2328 }
2329 }
2330
2331 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2332 // we always need a stub for the failure case.
2333 CodeStub* stub = op->stub();
2334 Register obj = op->object()->as_register();
2335 Register k_RInfo = op->tmp1()->as_register();
2336 Register klass_RInfo = op->tmp2()->as_register();
2337 Register dst = op->result_opr()->as_register();
2338 Register Rtmp1 = op->tmp3()->as_register();
2339 ciKlass* k = op->klass();
2340
2341
2342 if (obj == k_RInfo) {
2343 k_RInfo = klass_RInfo;
2344 klass_RInfo = obj;
2345 }
2346
2347 ciMethodData* md;
2348 ciProfileData* data;
2349 int mdo_offset_bias = 0;
2350 if (op->should_profile()) {
2351 ciMethod* method = op->profiled_method();
2352 assert(method != NULL, "Should have method");
2353 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2354
2355 Label not_null;
2356 __ br_notnull_short(obj, Assembler::pn, not_null);
2357 Register mdo = k_RInfo;
2358 Register data_val = Rtmp1;
2359 metadata2reg(md->constant_encoding(), mdo);
2360 if (mdo_offset_bias > 0) {
2361 __ set(mdo_offset_bias, data_val);
2362 __ add(mdo, data_val, mdo);
2363 }
2364 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2365 __ ldub(flags_addr, data_val);
2366 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2367 __ stb(data_val, flags_addr);
2368 __ ba(*obj_is_null);
2369 __ delayed()->nop();
2370 __ bind(not_null);
2371 } else {
2372 __ br_null(obj, false, Assembler::pn, *obj_is_null);
2373 __ delayed()->nop();
2374 }
2375
2376 Label profile_cast_failure, profile_cast_success;
2377 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2378 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2379
2380 // patching may screw with our temporaries on sparc,
2381 // so let's do it before loading the class
2382 if (k->is_loaded()) {
2383 metadata2reg(k->constant_encoding(), k_RInfo);
2384 } else {
2385 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2386 }
2387 assert(obj != k_RInfo, "must be different");
2388
2389 // get object class
2390 // not a safepoint as obj null check happens earlier
2391 __ load_klass(obj, klass_RInfo);
2392 if (op->fast_check()) {
2393 assert_different_registers(klass_RInfo, k_RInfo);
2394 __ cmp(k_RInfo, klass_RInfo);
2395 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
2396 __ delayed()->nop();
2397 } else {
2398 bool need_slow_path = true;
2399 if (k->is_loaded()) {
2400 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset()))
2401 need_slow_path = false;
2402 // perform the fast part of the checking logic
2403 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2404 (need_slow_path ? success_target : NULL),
2405 failure_target, NULL,
2406 RegisterOrConstant(k->super_check_offset()));
2407 } else {
2408 // perform the fast part of the checking logic
2409 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
2410 failure_target, NULL);
2411 }
2412 if (need_slow_path) {
2413 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2414 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2415 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2416 __ delayed()->nop();
2417 __ cmp(G3, 0);
2418 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2419 __ delayed()->nop();
2420 // Fall through to success case
2421 }
2422 }
2423
2424 if (op->should_profile()) {
2425 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2426 assert_different_registers(obj, mdo, recv, tmp1);
2427 __ bind(profile_cast_success);
2428 metadata2reg(md->constant_encoding(), mdo);
2429 if (mdo_offset_bias > 0) {
2430 __ set(mdo_offset_bias, tmp1);
2431 __ add(mdo, tmp1, mdo);
2432 }
2433 __ load_klass(obj, recv);
2434 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
2435 // Jump over the failure case
2436 __ ba(*success);
2437 __ delayed()->nop();
2438 // Cast failure case
2439 __ bind(profile_cast_failure);
2440 metadata2reg(md->constant_encoding(), mdo);
2441 if (mdo_offset_bias > 0) {
2442 __ set(mdo_offset_bias, tmp1);
2443 __ add(mdo, tmp1, mdo);
2444 }
2445 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2446 __ ld_ptr(data_addr, tmp1);
2447 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2448 __ st_ptr(tmp1, data_addr);
2449 __ ba(*failure);
2450 __ delayed()->nop();
2451 }
2452 __ ba(*success);
2453 __ delayed()->nop();
2454 }
2455
2456 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2457 LIR_Code code = op->code();
2458 if (code == lir_store_check) {
2459 Register value = op->object()->as_register();
2460 Register array = op->array()->as_register();
2461 Register k_RInfo = op->tmp1()->as_register();
2462 Register klass_RInfo = op->tmp2()->as_register();
2463 Register Rtmp1 = op->tmp3()->as_register();
2464
2465 __ verify_oop(value);
2466 CodeStub* stub = op->stub();
2467 // check if it needs to be profiled
2468 ciMethodData* md;
2469 ciProfileData* data;
2470 int mdo_offset_bias = 0;
2471 if (op->should_profile()) {
2472 ciMethod* method = op->profiled_method();
2473 assert(method != NULL, "Should have method");
2474 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2475 }
2476 Label profile_cast_success, profile_cast_failure, done;
2477 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2478 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2479
2480 if (op->should_profile()) {
2481 Label not_null;
2482 __ br_notnull_short(value, Assembler::pn, not_null);
2483 Register mdo = k_RInfo;
2484 Register data_val = Rtmp1;
2485 metadata2reg(md->constant_encoding(), mdo);
2486 if (mdo_offset_bias > 0) {
2487 __ set(mdo_offset_bias, data_val);
2488 __ add(mdo, data_val, mdo);
2489 }
2490 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2491 __ ldub(flags_addr, data_val);
2492 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2493 __ stb(data_val, flags_addr);
2494 __ ba_short(done);
2495 __ bind(not_null);
2496 } else {
2497 __ br_null_short(value, Assembler::pn, done);
2498 }
2499 add_debug_info_for_null_check_here(op->info_for_exception());
2500 __ load_klass(array, k_RInfo);
2501 __ load_klass(value, klass_RInfo);
2502
2503 // get instance klass
2504 __ ld_ptr(Address(k_RInfo, ObjArrayKlass::element_klass_offset()), k_RInfo);
2505 // perform the fast part of the checking logic
2506 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
2507
2508 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2509 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2510 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2511 __ delayed()->nop();
2512 __ cmp(G3, 0);
2513 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2514 __ delayed()->nop();
2515 // fall through to the success case
2516
2517 if (op->should_profile()) {
2518 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2519 assert_different_registers(value, mdo, recv, tmp1);
2520 __ bind(profile_cast_success);
2521 metadata2reg(md->constant_encoding(), mdo);
2522 if (mdo_offset_bias > 0) {
2523 __ set(mdo_offset_bias, tmp1);
2524 __ add(mdo, tmp1, mdo);
2525 }
2526 __ load_klass(value, recv);
2527 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2528 __ ba_short(done);
2529 // Cast failure case
2530 __ bind(profile_cast_failure);
2531 metadata2reg(md->constant_encoding(), mdo);
2532 if (mdo_offset_bias > 0) {
2533 __ set(mdo_offset_bias, tmp1);
2534 __ add(mdo, tmp1, mdo);
2535 }
2536 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2537 __ ld_ptr(data_addr, tmp1);
2538 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2539 __ st_ptr(tmp1, data_addr);
2540 __ ba(*stub->entry());
2541 __ delayed()->nop();
2542 }
2543 __ bind(done);
2544 } else if (code == lir_checkcast) {
2545 Register obj = op->object()->as_register();
2546 Register dst = op->result_opr()->as_register();
2547 Label success;
2548 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2549 __ bind(success);
2550 __ mov(obj, dst);
2551 } else if (code == lir_instanceof) {
2552 Register obj = op->object()->as_register();
2553 Register dst = op->result_opr()->as_register();
2554 Label success, failure, done;
2555 emit_typecheck_helper(op, &success, &failure, &failure);
2556 __ bind(failure);
2557 __ set(0, dst);
2558 __ ba_short(done);
2559 __ bind(success);
2560 __ set(1, dst);
2561 __ bind(done);
2562 } else {
2563 ShouldNotReachHere();
2564 }
2565
2566 }
2567
2568
2569 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2570 if (op->code() == lir_cas_long) {
2571 assert(VM_Version::supports_cx8(), "wrong machine");
2572 Register addr = op->addr()->as_pointer_register();
2573 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2574 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2575 Register new_value_lo = op->new_value()->as_register_lo();
2576 Register new_value_hi = op->new_value()->as_register_hi();
2577 Register t1 = op->tmp1()->as_register();
2578 Register t2 = op->tmp2()->as_register();
2579 __ mov(cmp_value_lo, t1);
2580 __ mov(new_value_lo, t2);
2581 // perform the compare and swap operation
2582 __ casx(addr, t1, t2);
2583 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2584 // overwritten with the original value in "addr" and will be equal to t1.
2585 __ cmp(t1, t2);
2586 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2587 Register addr = op->addr()->as_pointer_register();
2588 Register cmp_value = op->cmp_value()->as_register();
2589 Register new_value = op->new_value()->as_register();
2590 Register t1 = op->tmp1()->as_register();
2591 Register t2 = op->tmp2()->as_register();
2592 __ mov(cmp_value, t1);
2593 __ mov(new_value, t2);
2594 if (op->code() == lir_cas_obj) {
2595 if (UseCompressedOops) {
2596 __ encode_heap_oop(t1);
2597 __ encode_heap_oop(t2);
2598 __ cas(addr, t1, t2);
2599 } else {
2600 __ cas_ptr(addr, t1, t2);
2601 }
2602 } else {
2603 __ cas(addr, t1, t2);
2604 }
2605 __ cmp(t1, t2);
2606 } else {
2607 Unimplemented();
2608 }
2609 }
2610
2611 void LIR_Assembler::set_24bit_FPU() {
2612 Unimplemented();
2613 }
2614
2615
2616 void LIR_Assembler::reset_FPU() {
2617 Unimplemented();
2618 }
2619
2620
2621 void LIR_Assembler::breakpoint() {
2622 __ breakpoint_trap();
2623 }
2624
2625
2626 void LIR_Assembler::push(LIR_Opr opr) {
2627 Unimplemented();
2628 }
2629
2630
2631 void LIR_Assembler::pop(LIR_Opr opr) {
2632 Unimplemented();
2633 }
2634
2635
2636 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2637 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2638 Register dst = dst_opr->as_register();
2639 Register reg = mon_addr.base();
2640 int offset = mon_addr.disp();
2641 // compute pointer to BasicLock
2642 if (mon_addr.is_simm13()) {
2643 __ add(reg, offset, dst);
2644 } else {
2645 __ set(offset, dst);
2646 __ add(dst, reg, dst);
2647 }
2648 }
2649
2650 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2651 assert(op->crc()->is_single_cpu(), "crc must be register");
2652 assert(op->val()->is_single_cpu(), "byte value must be register");
2653 assert(op->result_opr()->is_single_cpu(), "result must be register");
2654 Register crc = op->crc()->as_register();
2655 Register val = op->val()->as_register();
2656 Register table = op->result_opr()->as_register();
2657 Register res = op->result_opr()->as_register();
2658
2659 assert_different_registers(val, crc, table);
2660
2661 __ set(ExternalAddress(StubRoutines::crc_table_addr()), table);
2662 __ not1(crc);
2663 __ clruwu(crc);
2664 __ update_byte_crc32(crc, val, table);
2665 __ not1(crc);
2666
2667 __ mov(crc, res);
2668 }
2669
2670 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2671 Register obj = op->obj_opr()->as_register();
2672 Register hdr = op->hdr_opr()->as_register();
2673 Register lock = op->lock_opr()->as_register();
2674
2675 // obj may not be an oop
2676 if (op->code() == lir_lock) {
2677 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2678 if (UseFastLocking) {
2679 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2680 // add debug info for NullPointerException only if one is possible
2681 if (op->info() != NULL) {
2682 add_debug_info_for_null_check_here(op->info());
2683 }
2684 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2685 } else {
2686 // always do slow locking
2687 // note: the slow locking code could be inlined here, however if we use
2688 // slow locking, speed doesn't matter anyway and this solution is
2689 // simpler and requires less duplicated code - additionally, the
2690 // slow locking code is the same in either case which simplifies
2691 // debugging
2692 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2693 __ delayed()->nop();
2694 }
2695 } else {
2696 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2697 if (UseFastLocking) {
2698 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2699 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2700 } else {
2701 // always do slow unlocking
2702 // note: the slow unlocking code could be inlined here, however if we use
2703 // slow unlocking, speed doesn't matter anyway and this solution is
2704 // simpler and requires less duplicated code - additionally, the
2705 // slow unlocking code is the same in either case which simplifies
2706 // debugging
2707 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2708 __ delayed()->nop();
2709 }
2710 }
2711 __ bind(*op->stub()->continuation());
2712 }
2713
2714
2715 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2716 ciMethod* method = op->profiled_method();
2717 int bci = op->profiled_bci();
2718 ciMethod* callee = op->profiled_callee();
2719
2720 // Update counter for all call types
2721 ciMethodData* md = method->method_data_or_null();
2722 assert(md != NULL, "Sanity");
2723 ciProfileData* data = md->bci_to_data(bci);
2724 assert(data->is_CounterData(), "need CounterData for calls");
2725 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2726 Register mdo = op->mdo()->as_register();
2727 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2728 Register tmp1 = op->tmp1()->as_register_lo();
2729 metadata2reg(md->constant_encoding(), mdo);
2730 int mdo_offset_bias = 0;
2731 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2732 data->size_in_bytes())) {
2733 // The offset is large so bias the mdo by the base of the slot so
2734 // that the ld can use simm13s to reference the slots of the data
2735 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2736 __ set(mdo_offset_bias, O7);
2737 __ add(mdo, O7, mdo);
2738 }
2739
2740 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2741 Bytecodes::Code bc = method->java_code_at_bci(bci);
2742 const bool callee_is_static = callee->is_loaded() && callee->is_static();
2743 // Perform additional virtual call profiling for invokevirtual and
2744 // invokeinterface bytecodes
2745 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2746 !callee_is_static && // required for optimized MH invokes
2747 C1ProfileVirtualCalls) {
2748 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2749 Register recv = op->recv()->as_register();
2750 assert_different_registers(mdo, tmp1, recv);
2751 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2752 ciKlass* known_klass = op->known_holder();
2753 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2754 // We know the type that will be seen at this call site; we can
2755 // statically update the MethodData* rather than needing to do
2756 // dynamic tests on the receiver type
2757
2758 // NOTE: we should probably put a lock around this search to
2759 // avoid collisions by concurrent compilations
2760 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2761 uint i;
2762 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2763 ciKlass* receiver = vc_data->receiver(i);
2764 if (known_klass->equals(receiver)) {
2765 Address data_addr(mdo, md->byte_offset_of_slot(data,
2766 VirtualCallData::receiver_count_offset(i)) -
2767 mdo_offset_bias);
2768 __ ld_ptr(data_addr, tmp1);
2769 __ add(tmp1, DataLayout::counter_increment, tmp1);
2770 __ st_ptr(tmp1, data_addr);
2771 return;
2772 }
2773 }
2774
2775 // Receiver type not found in profile data; select an empty slot
2776
2777 // Note that this is less efficient than it should be because it
2778 // always does a write to the receiver part of the
2779 // VirtualCallData rather than just the first time
2780 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2781 ciKlass* receiver = vc_data->receiver(i);
2782 if (receiver == NULL) {
2783 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2784 mdo_offset_bias);
2785 metadata2reg(known_klass->constant_encoding(), tmp1);
2786 __ st_ptr(tmp1, recv_addr);
2787 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2788 mdo_offset_bias);
2789 __ ld_ptr(data_addr, tmp1);
2790 __ add(tmp1, DataLayout::counter_increment, tmp1);
2791 __ st_ptr(tmp1, data_addr);
2792 return;
2793 }
2794 }
2795 } else {
2796 __ load_klass(recv, recv);
2797 Label update_done;
2798 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2799 // Receiver did not match any saved receiver and there is no empty row for it.
2800 // Increment total counter to indicate polymorphic case.
2801 __ ld_ptr(counter_addr, tmp1);
2802 __ add(tmp1, DataLayout::counter_increment, tmp1);
2803 __ st_ptr(tmp1, counter_addr);
2804
2805 __ bind(update_done);
2806 }
2807 } else {
2808 // Static call
2809 __ ld_ptr(counter_addr, tmp1);
2810 __ add(tmp1, DataLayout::counter_increment, tmp1);
2811 __ st_ptr(tmp1, counter_addr);
2812 }
2813 }
2814
2815 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2816 Register obj = op->obj()->as_register();
2817 Register tmp1 = op->tmp()->as_pointer_register();
2818 Register tmp2 = G1;
2819 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2820 ciKlass* exact_klass = op->exact_klass();
2821 intptr_t current_klass = op->current_klass();
2822 bool not_null = op->not_null();
2823 bool no_conflict = op->no_conflict();
2824
2825 Label update, next, none;
2826
2827 bool do_null = !not_null;
2828 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2829 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2830
2831 assert(do_null || do_update, "why are we here?");
2832 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2833
2834 __ verify_oop(obj);
2835
2836 if (tmp1 != obj) {
2837 __ mov(obj, tmp1);
2838 }
2839 if (do_null) {
2840 __ br_notnull_short(tmp1, Assembler::pt, update);
2841 if (!TypeEntries::was_null_seen(current_klass)) {
2842 __ ld_ptr(mdo_addr, tmp1);
2843 __ or3(tmp1, TypeEntries::null_seen, tmp1);
2844 __ st_ptr(tmp1, mdo_addr);
2845 }
2846 if (do_update) {
2847 __ ba(next);
2848 __ delayed()->nop();
2849 }
2850 #ifdef ASSERT
2851 } else {
2852 __ br_notnull_short(tmp1, Assembler::pt, update);
2853 __ stop("unexpect null obj");
2854 #endif
2855 }
2856
2857 __ bind(update);
2858
2859 if (do_update) {
2860 #ifdef ASSERT
2861 if (exact_klass != NULL) {
2862 Label ok;
2863 __ load_klass(tmp1, tmp1);
2864 metadata2reg(exact_klass->constant_encoding(), tmp2);
2865 __ cmp_and_br_short(tmp1, tmp2, Assembler::equal, Assembler::pt, ok);
2866 __ stop("exact klass and actual klass differ");
2867 __ bind(ok);
2868 }
2869 #endif
2870
2871 Label do_update;
2872 __ ld_ptr(mdo_addr, tmp2);
2873
2874 if (!no_conflict) {
2875 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2876 if (exact_klass != NULL) {
2877 metadata2reg(exact_klass->constant_encoding(), tmp1);
2878 } else {
2879 __ load_klass(tmp1, tmp1);
2880 }
2881
2882 __ xor3(tmp1, tmp2, tmp1);
2883 __ btst(TypeEntries::type_klass_mask, tmp1);
2884 // klass seen before, nothing to do. The unknown bit may have been
2885 // set already but no need to check.
2886 __ brx(Assembler::zero, false, Assembler::pt, next);
2887 __ delayed()->
2888
2889 btst(TypeEntries::type_unknown, tmp1);
2890 // already unknown. Nothing to do anymore.
2891 __ brx(Assembler::notZero, false, Assembler::pt, next);
2892
2893 if (TypeEntries::is_type_none(current_klass)) {
2894 __ delayed()->btst(TypeEntries::type_mask, tmp2);
2895 __ brx(Assembler::zero, true, Assembler::pt, do_update);
2896 // first time here. Set profile type.
2897 __ delayed()->or3(tmp2, tmp1, tmp2);
2898 } else {
2899 __ delayed()->nop();
2900 }
2901 } else {
2902 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2903 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2904
2905 __ btst(TypeEntries::type_unknown, tmp2);
2906 // already unknown. Nothing to do anymore.
2907 __ brx(Assembler::notZero, false, Assembler::pt, next);
2908 __ delayed()->nop();
2909 }
2910
2911 // different than before. Cannot keep accurate profile.
2912 __ or3(tmp2, TypeEntries::type_unknown, tmp2);
2913 } else {
2914 // There's a single possible klass at this profile point
2915 assert(exact_klass != NULL, "should be");
2916 if (TypeEntries::is_type_none(current_klass)) {
2917 metadata2reg(exact_klass->constant_encoding(), tmp1);
2918 __ xor3(tmp1, tmp2, tmp1);
2919 __ btst(TypeEntries::type_klass_mask, tmp1);
2920 __ brx(Assembler::zero, false, Assembler::pt, next);
2921 #ifdef ASSERT
2922
2923 {
2924 Label ok;
2925 __ delayed()->btst(TypeEntries::type_mask, tmp2);
2926 __ brx(Assembler::zero, true, Assembler::pt, ok);
2927 __ delayed()->nop();
2928
2929 __ stop("unexpected profiling mismatch");
2930 __ bind(ok);
2931 }
2932 // first time here. Set profile type.
2933 __ or3(tmp2, tmp1, tmp2);
2934 #else
2935 // first time here. Set profile type.
2936 __ delayed()->or3(tmp2, tmp1, tmp2);
2937 #endif
2938
2939 } else {
2940 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2941 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2942
2943 // already unknown. Nothing to do anymore.
2944 __ btst(TypeEntries::type_unknown, tmp2);
2945 __ brx(Assembler::notZero, false, Assembler::pt, next);
2946 __ delayed()->or3(tmp2, TypeEntries::type_unknown, tmp2);
2947 }
2948 }
2949
2950 __ bind(do_update);
2951 __ st_ptr(tmp2, mdo_addr);
2952
2953 __ bind(next);
2954 }
2955 }
2956
2957 void LIR_Assembler::align_backward_branch_target() {
2958 __ align(OptoLoopAlignment);
2959 }
2960
2961
2962 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2963 // make sure we are expecting a delay
2964 // this has the side effect of clearing the delay state
2965 // so we can use _masm instead of _masm->delayed() to do the
2966 // code generation.
2967 __ delayed();
2968
2969 // make sure we only emit one instruction
2970 int offset = code_offset();
2971 op->delay_op()->emit_code(this);
2972 #ifdef ASSERT
2973 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
2974 op->delay_op()->print();
2975 }
2976 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
2977 "only one instruction can go in a delay slot");
2978 #endif
2979
2980 // we may also be emitting the call info for the instruction
2981 // which we are the delay slot of.
2982 CodeEmitInfo* call_info = op->call_info();
2983 if (call_info) {
2984 add_call_info(code_offset(), call_info);
2985 }
2986
2987 if (VerifyStackAtCalls) {
2988 _masm->sub(FP, SP, O7);
2989 _masm->cmp(O7, initial_frame_size_in_bytes());
2990 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
2991 }
2992 }
2993
2994
2995 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
2996 assert(left->is_register(), "can only handle registers");
2997
2998 if (left->is_single_cpu()) {
2999 __ neg(left->as_register(), dest->as_register());
3000 } else if (left->is_single_fpu()) {
3001 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
3002 } else if (left->is_double_fpu()) {
3003 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
3004 } else {
3005 assert (left->is_double_cpu(), "Must be a long");
3006 Register Rlow = left->as_register_lo();
3007 Register Rhi = left->as_register_hi();
3008 __ sub(G0, Rlow, dest->as_register_lo());
3009 }
3010 }
3011
3012
3013 void LIR_Assembler::fxch(int i) {
3014 Unimplemented();
3015 }
3016
3017 void LIR_Assembler::fld(int i) {
3018 Unimplemented();
3019 }
3020
3021 void LIR_Assembler::ffree(int i) {
3022 Unimplemented();
3023 }
3024
3025 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
3026 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3027
3028 // if tmp is invalid, then the function being called doesn't destroy the thread
3029 if (tmp->is_valid()) {
3030 __ save_thread(tmp->as_pointer_register());
3031 }
3032 __ call(dest, relocInfo::runtime_call_type);
3033 __ delayed()->nop();
3034 if (info != NULL) {
3035 add_call_info_here(info);
3036 }
3037 if (tmp->is_valid()) {
3038 __ restore_thread(tmp->as_pointer_register());
3039 }
3040
3041 #ifdef ASSERT
3042 __ verify_thread();
3043 #endif // ASSERT
3044 }
3045
3046
3047 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3048 ShouldNotReachHere();
3049
3050 NEEDS_CLEANUP;
3051 if (type == T_LONG) {
3052 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3053
3054 // (extended to allow indexed as well as constant displaced for JSR-166)
3055 Register idx = noreg; // contains either constant offset or index
3056
3057 int disp = mem_addr->disp();
3058 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
3059 if (!Assembler::is_simm13(disp)) {
3060 idx = O7;
3061 __ set(disp, idx);
3062 }
3063 } else {
3064 assert(disp == 0, "not both indexed and disp");
3065 idx = mem_addr->index()->as_register();
3066 }
3067
3068 int null_check_offset = -1;
3069
3070 Register base = mem_addr->base()->as_register();
3071 if (src->is_register() && dest->is_address()) {
3072 // G4 is high half, G5 is low half
3073 // clear the top bits of G5, and scale up G4
3074 __ srl (src->as_register_lo(), 0, G5);
3075 __ sllx(src->as_register_hi(), 32, G4);
3076 // combine the two halves into the 64 bits of G4
3077 __ or3(G4, G5, G4);
3078 null_check_offset = __ offset();
3079 if (idx == noreg) {
3080 __ stx(G4, base, disp);
3081 } else {
3082 __ stx(G4, base, idx);
3083 }
3084 } else if (src->is_address() && dest->is_register()) {
3085 null_check_offset = __ offset();
3086 if (idx == noreg) {
3087 __ ldx(base, disp, G5);
3088 } else {
3089 __ ldx(base, idx, G5);
3090 }
3091 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
3092 __ mov (G5, dest->as_register_lo()); // copy low half into lo
3093 } else {
3094 Unimplemented();
3095 }
3096 if (info != NULL) {
3097 add_debug_info_for_null_check(null_check_offset, info);
3098 }
3099
3100 } else {
3101 // use normal move for all other volatiles since they don't need
3102 // special handling to remain atomic.
3103 move_op(src, dest, type, lir_patch_none, info, false, false, false);
3104 }
3105 }
3106
3107 void LIR_Assembler::membar() {
3108 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3109 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3110 }
3111
3112 void LIR_Assembler::membar_acquire() {
3113 // no-op on TSO
3114 }
3115
3116 void LIR_Assembler::membar_release() {
3117 // no-op on TSO
3118 }
3119
3120 void LIR_Assembler::membar_loadload() {
3121 // no-op
3122 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3123 }
3124
3125 void LIR_Assembler::membar_storestore() {
3126 // no-op
3127 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3128 }
3129
3130 void LIR_Assembler::membar_loadstore() {
3131 // no-op
3132 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3133 }
3134
3135 void LIR_Assembler::membar_storeload() {
3136 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3137 }
3138
3139 void LIR_Assembler::on_spin_wait() {
3140 Unimplemented();
3141 }
3142
3143 // Pack two sequential registers containing 32 bit values
3144 // into a single 64 bit register.
3145 // src and src->successor() are packed into dst
3146 // src and dst may be the same register.
3147 // Note: src is destroyed
3148 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3149 Register rs = src->as_register();
3150 Register rd = dst->as_register_lo();
3151 __ sllx(rs, 32, rs);
3152 __ srl(rs->successor(), 0, rs->successor());
3153 __ or3(rs, rs->successor(), rd);
3154 }
3155
3156 // Unpack a 64 bit value in a register into
3157 // two sequential registers.
3158 // src is unpacked into dst and dst->successor()
3159 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3160 Register rs = src->as_register_lo();
3161 Register rd = dst->as_register_hi();
3162 assert_different_registers(rs, rd, rd->successor());
3163 __ srlx(rs, 32, rd);
3164 __ srl (rs, 0, rd->successor());
3165 }
3166
3167
3168 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3169 LIR_Address* addr = addr_opr->as_address_ptr();
3170 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
3171
3172 if (Assembler::is_simm13(addr->disp())) {
3173 __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());
3174 } else {
3175 __ set(addr->disp(), G3_scratch);
3176 __ add(addr->base()->as_pointer_register(), G3_scratch, dest->as_pointer_register());
3177 }
3178 }
3179
3180
3181 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3182 assert(result_reg->is_register(), "check");
3183 __ mov(G2_thread, result_reg->as_register());
3184 }
3185
3186 #ifdef ASSERT
3187 // emit run-time assertion
3188 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3189 assert(op->code() == lir_assert, "must be");
3190
3191 if (op->in_opr1()->is_valid()) {
3192 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3193 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3194 } else {
3195 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3196 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3197 }
3198
3199 Label ok;
3200 if (op->condition() != lir_cond_always) {
3201 Assembler::Condition acond;
3202 switch (op->condition()) {
3203 case lir_cond_equal: acond = Assembler::equal; break;
3204 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3205 case lir_cond_less: acond = Assembler::less; break;
3206 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3207 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
3208 case lir_cond_greater: acond = Assembler::greater; break;
3209 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
3210 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
3211 default: ShouldNotReachHere();
3212 };
3213 __ br(acond, false, Assembler::pt, ok);
3214 __ delayed()->nop();
3215 }
3216 if (op->halt()) {
3217 const char* str = __ code_string(op->msg());
3218 __ stop(str);
3219 } else {
3220 breakpoint();
3221 }
3222 __ bind(ok);
3223 }
3224 #endif
3225
3226 void LIR_Assembler::peephole(LIR_List* lir) {
3227 LIR_OpList* inst = lir->instructions_list();
3228 for (int i = 0; i < inst->length(); i++) {
3229 LIR_Op* op = inst->at(i);
3230 switch (op->code()) {
3231 case lir_cond_float_branch:
3232 case lir_branch: {
3233 LIR_OpBranch* branch = op->as_OpBranch();
3234 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3235 LIR_Op* delay_op = NULL;
3236 // we'd like to be able to pull following instructions into
3237 // this slot but we don't know enough to do it safely yet so
3238 // only optimize block to block control flow.
3239 if (LIRFillDelaySlots && branch->block()) {
3240 LIR_Op* prev = inst->at(i - 1);
3241 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3242 // swap previous instruction into delay slot
3243 inst->at_put(i - 1, op);
3244 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3245 #ifndef PRODUCT
3246 if (LIRTracePeephole) {
3247 tty->print_cr("delayed");
3248 inst->at(i - 1)->print();
3249 inst->at(i)->print();
3250 tty->cr();
3251 }
3252 #endif
3253 continue;
3254 }
3255 }
3256
3257 if (!delay_op) {
3258 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3259 }
3260 inst->insert_before(i + 1, delay_op);
3261 break;
3262 }
3263 case lir_static_call:
3264 case lir_virtual_call:
3265 case lir_icvirtual_call:
3266 case lir_optvirtual_call:
3267 case lir_dynamic_call: {
3268 LIR_Op* prev = inst->at(i - 1);
3269 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3270 (op->code() != lir_virtual_call ||
3271 !prev->result_opr()->is_single_cpu() ||
3272 prev->result_opr()->as_register() != O0) &&
3273 LIR_Assembler::is_single_instruction(prev)) {
3274 // Only moves without info can be put into the delay slot.
3275 // Also don't allow the setup of the receiver in the delay
3276 // slot for vtable calls.
3277 inst->at_put(i - 1, op);
3278 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3279 #ifndef PRODUCT
3280 if (LIRTracePeephole) {
3281 tty->print_cr("delayed");
3282 inst->at(i - 1)->print();
3283 inst->at(i)->print();
3284 tty->cr();
3285 }
3286 #endif
3287 } else {
3288 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3289 inst->insert_before(i + 1, delay_op);
3290 i++;
3291 }
3292 break;
3293 }
3294 }
3295 }
3296 }
3297
3298 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3299 LIR_Address* addr = src->as_address_ptr();
3300
3301 assert(data == dest, "swap uses only 2 operands");
3302 assert (code == lir_xchg, "no xadd on sparc");
3303
3304 if (data->type() == T_INT) {
3305 __ swap(as_Address(addr), data->as_register());
3306 } else if (data->is_oop()) {
3307 Register obj = data->as_register();
3308 Register narrow = tmp->as_register();
3309 assert(UseCompressedOops, "swap is 32bit only");
3310 __ encode_heap_oop(obj, narrow);
3311 __ swap(as_Address(addr), narrow);
3312 __ decode_heap_oop(narrow, obj);
3313 } else {
3314 ShouldNotReachHere();
3315 }
3316 }
3317
3318 #undef __