1 /* 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.inline.hpp" 27 #include "code/codeCache.hpp" 28 #include "memory/resourceArea.hpp" 29 #include "nativeInst_sparc.hpp" 30 #include "oops/oop.inline.hpp" 31 #include "runtime/handles.hpp" 32 #include "runtime/sharedRuntime.hpp" 33 #include "runtime/stubRoutines.hpp" 34 #include "utilities/ostream.hpp" 35 #ifdef COMPILER1 36 #include "c1/c1_Runtime1.hpp" 37 #endif 38 39 void NativeInstruction::set_data64_sethi(address instaddr, intptr_t x) { 40 ResourceMark rm; 41 CodeBuffer buf(instaddr, 10 * BytesPerInstWord ); 42 MacroAssembler* _masm = new MacroAssembler(&buf); 43 Register destreg; 44 45 destreg = inv_rd(*(unsigned int *)instaddr); 46 // Generate a the new sequence 47 _masm->patchable_sethi(x, destreg); 48 ICache::invalidate_range(instaddr, 7 * BytesPerInstWord); 49 } 50 51 void NativeInstruction::verify_data64_sethi(address instaddr, intptr_t x) { 52 ResourceMark rm; 53 unsigned char buffer[10 * BytesPerInstWord]; 54 CodeBuffer buf(buffer, 10 * BytesPerInstWord); 55 MacroAssembler masm(&buf); 56 57 Register destreg = inv_rd(*(unsigned int *)instaddr); 58 // Generate the proper sequence into a temporary buffer and compare 59 // it with the original sequence. 60 masm.patchable_sethi(x, destreg); 61 int len = buffer - masm.pc(); 62 for (int i = 0; i < len; i++) { 63 guarantee(instaddr[i] == buffer[i], "instructions must match"); 64 } 65 } 66 67 void NativeInstruction::verify() { 68 // make sure code pattern is actually an instruction address 69 address addr = addr_at(0); 70 if (addr == 0 || ((intptr_t)addr & 3) != 0) { 71 fatal("not an instruction address"); 72 } 73 } 74 75 void NativeInstruction::print() { 76 tty->print_cr(INTPTR_FORMAT ": 0x%x", p2i(addr_at(0)), long_at(0)); 77 } 78 79 void NativeInstruction::set_long_at(int offset, int i) { 80 address addr = addr_at(offset); 81 *(int*)addr = i; 82 ICache::invalidate_word(addr); 83 } 84 85 void NativeInstruction::set_jlong_at(int offset, jlong i) { 86 address addr = addr_at(offset); 87 *(jlong*)addr = i; 88 // Don't need to invalidate 2 words here, because 89 // the flush instruction operates on doublewords. 90 ICache::invalidate_word(addr); 91 } 92 93 void NativeInstruction::set_addr_at(int offset, address x) { 94 address addr = addr_at(offset); 95 assert( ((intptr_t)addr & (wordSize-1)) == 0, "set_addr_at bad address alignment"); 96 *(uintptr_t*)addr = (uintptr_t)x; 97 // Don't need to invalidate 2 words here in the 64-bit case, 98 // because the flush instruction operates on doublewords. 99 ICache::invalidate_word(addr); 100 // The Intel code has this assertion for NativeCall::set_destination, 101 // NativeMovConstReg::set_data, NativeMovRegMem::set_offset, 102 // NativeJump::set_jump_destination, and NativePushImm32::set_data 103 //assert (Patching_lock->owned_by_self(), "must hold lock to patch instruction") 104 } 105 106 bool NativeInstruction::is_zero_test(Register ®) { 107 int x = long_at(0); 108 Assembler::op3s temp = (Assembler::op3s) (Assembler::sub_op3 | Assembler::cc_bit_op3); 109 if (is_op3(x, temp, Assembler::arith_op) && 110 inv_immed(x) && inv_rd(x) == G0) { 111 if (inv_rs1(x) == G0) { 112 reg = inv_rs2(x); 113 return true; 114 } else if (inv_rs2(x) == G0) { 115 reg = inv_rs1(x); 116 return true; 117 } 118 } 119 return false; 120 } 121 122 bool NativeInstruction::is_load_store_with_small_offset(Register reg) { 123 int x = long_at(0); 124 if (is_op(x, Assembler::ldst_op) && 125 inv_rs1(x) == reg && inv_immed(x)) { 126 return true; 127 } 128 return false; 129 } 130 131 void NativeCall::verify() { 132 NativeInstruction::verify(); 133 // make sure code pattern is actually a call instruction 134 int x = long_at(0); 135 if (!is_op(x, Assembler::call_op)) { 136 fatal("not a call: 0x%x @ " INTPTR_FORMAT, x, p2i(instruction_address())); 137 } 138 } 139 140 void NativeCall::print() { 141 tty->print_cr(INTPTR_FORMAT ": call " INTPTR_FORMAT, p2i(instruction_address()), p2i(destination())); 142 } 143 144 145 // MT-safe patching of a call instruction (and following word). 146 // First patches the second word, and then atomicly replaces 147 // the first word with the first new instruction word. 148 // Other processors might briefly see the old first word 149 // followed by the new second word. This is OK if the old 150 // second word is harmless, and the new second word may be 151 // harmlessly executed in the delay slot of the call. 152 void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) { 153 assert(Patching_lock->is_locked() || 154 SafepointSynchronize::is_at_safepoint(), "concurrent code patching"); 155 assert (instr_addr != NULL, "illegal address for code patching"); 156 NativeCall* n_call = nativeCall_at (instr_addr); // checking that it is a call 157 assert(NativeCall::instruction_size == 8, "wrong instruction size; must be 8"); 158 int i0 = ((int*)code_buffer)[0]; 159 int i1 = ((int*)code_buffer)[1]; 160 int* contention_addr = (int*) n_call->addr_at(1*BytesPerInstWord); 161 assert(inv_op(*contention_addr) == Assembler::arith_op || 162 *contention_addr == nop_instruction(), 163 "must not interfere with original call"); 164 // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order 165 n_call->set_long_at(1*BytesPerInstWord, i1); 166 n_call->set_long_at(0*BytesPerInstWord, i0); 167 // NOTE: It is possible that another thread T will execute 168 // only the second patched word. 169 // In other words, since the original instruction is this 170 // call patching_stub; nop (NativeCall) 171 // and the new sequence from the buffer is this: 172 // sethi %hi(K), %r; add %r, %lo(K), %r (NativeMovConstReg) 173 // what T will execute is this: 174 // call patching_stub; add %r, %lo(K), %r 175 // thereby putting garbage into %r before calling the patching stub. 176 // This is OK, because the patching stub ignores the value of %r. 177 178 // Make sure the first-patched instruction, which may co-exist 179 // briefly with the call, will do something harmless. 180 assert(inv_op(*contention_addr) == Assembler::arith_op || 181 *contention_addr == nop_instruction(), 182 "must not interfere with original call"); 183 } 184 185 // Similar to replace_mt_safe, but just changes the destination. The 186 // important thing is that free-running threads are able to execute this 187 // call instruction at all times. Thus, the displacement field must be 188 // instruction-word-aligned. This is always true on SPARC. 189 // 190 // Used in the runtime linkage of calls; see class CompiledIC. 191 void NativeCall::set_destination_mt_safe(address dest) { 192 assert(Patching_lock->is_locked() || 193 SafepointSynchronize::is_at_safepoint(), "concurrent code patching"); 194 // set_destination uses set_long_at which does the ICache::invalidate 195 set_destination(dest); 196 } 197 198 // Code for unit testing implementation of NativeCall class 199 void NativeCall::test() { 200 #ifdef ASSERT 201 ResourceMark rm; 202 CodeBuffer cb("test", 100, 100); 203 MacroAssembler* a = new MacroAssembler(&cb); 204 NativeCall *nc; 205 uint idx; 206 int offsets[] = { 207 0x0, 208 0xfffffff0, 209 0x7ffffff0, 210 0x80000000, 211 0x20, 212 0x4000, 213 }; 214 215 VM_Version::allow_all(); 216 217 a->call( a->pc(), relocInfo::none ); 218 a->delayed()->nop(); 219 nc = nativeCall_at( cb.insts_begin() ); 220 nc->print(); 221 222 nc = nativeCall_overwriting_at( nc->next_instruction_address() ); 223 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) { 224 nc->set_destination( cb.insts_begin() + offsets[idx] ); 225 assert(nc->destination() == (cb.insts_begin() + offsets[idx]), "check unit test"); 226 nc->print(); 227 } 228 229 nc = nativeCall_before( cb.insts_begin() + 8 ); 230 nc->print(); 231 232 VM_Version::revert(); 233 #endif 234 } 235 // End code for unit testing implementation of NativeCall class 236 237 //------------------------------------------------------------------- 238 239 #ifdef _LP64 240 241 void NativeFarCall::set_destination(address dest) { 242 // Address materialized in the instruction stream, so nothing to do. 243 return; 244 #if 0 // What we'd do if we really did want to change the destination 245 if (destination() == dest) { 246 return; 247 } 248 ResourceMark rm; 249 CodeBuffer buf(addr_at(0), instruction_size + 1); 250 MacroAssembler* _masm = new MacroAssembler(&buf); 251 // Generate the new sequence 252 AddressLiteral(dest); 253 _masm->jumpl_to(dest, O7, O7); 254 ICache::invalidate_range(addr_at(0), instruction_size ); 255 #endif 256 } 257 258 void NativeFarCall::verify() { 259 // make sure code pattern is actually a jumpl_to instruction 260 assert((int)instruction_size == (int)NativeJump::instruction_size, "same as jump_to"); 261 assert((int)jmpl_offset == (int)NativeMovConstReg::add_offset, "sethi size ok"); 262 nativeJump_at(addr_at(0))->verify(); 263 } 264 265 bool NativeFarCall::is_call_at(address instr) { 266 return nativeInstruction_at(instr)->is_sethi(); 267 } 268 269 void NativeFarCall::print() { 270 tty->print_cr(INTPTR_FORMAT ": call " INTPTR_FORMAT, p2i(instruction_address()), p2i(destination())); 271 } 272 273 bool NativeFarCall::destination_is_compiled_verified_entry_point() { 274 nmethod* callee = CodeCache::find_nmethod(destination()); 275 if (callee == NULL) { 276 return false; 277 } else { 278 return destination() == callee->verified_entry_point(); 279 } 280 } 281 282 // MT-safe patching of a far call. 283 void NativeFarCall::replace_mt_safe(address instr_addr, address code_buffer) { 284 Unimplemented(); 285 } 286 287 // Code for unit testing implementation of NativeFarCall class 288 void NativeFarCall::test() { 289 Unimplemented(); 290 } 291 // End code for unit testing implementation of NativeFarCall class 292 293 #endif // _LP64 294 295 //------------------------------------------------------------------- 296 297 298 void NativeMovConstReg::verify() { 299 NativeInstruction::verify(); 300 // make sure code pattern is actually a "set_metadata" synthetic instruction 301 // see MacroAssembler::set_oop() 302 int i0 = long_at(sethi_offset); 303 int i1 = long_at(add_offset); 304 305 // verify the pattern "sethi %hi22(imm), reg ; add reg, %lo10(imm), reg" 306 Register rd = inv_rd(i0); 307 #ifndef _LP64 308 if (!(is_op2(i0, Assembler::sethi_op2) && rd != G0 && 309 is_op3(i1, Assembler::add_op3, Assembler::arith_op) && 310 inv_immed(i1) && (unsigned)get_simm13(i1) < (1 << 10) && 311 rd == inv_rs1(i1) && rd == inv_rd(i1))) { 312 fatal("not a set_metadata"); 313 } 314 #else 315 if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) { 316 fatal("not a set_metadata"); 317 } 318 #endif 319 } 320 321 322 void NativeMovConstReg::print() { 323 tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, p2i(instruction_address()), data()); 324 } 325 326 327 #ifdef _LP64 328 intptr_t NativeMovConstReg::data() const { 329 return data64(addr_at(sethi_offset), long_at(add_offset)); 330 } 331 #else 332 intptr_t NativeMovConstReg::data() const { 333 return data32(long_at(sethi_offset), long_at(add_offset)); 334 } 335 #endif 336 337 338 void NativeMovConstReg::set_data(intptr_t x) { 339 #ifdef _LP64 340 set_data64_sethi(addr_at(sethi_offset), x); 341 #else 342 set_long_at(sethi_offset, set_data32_sethi( long_at(sethi_offset), x)); 343 #endif 344 set_long_at(add_offset, set_data32_simm13( long_at(add_offset), x)); 345 346 // also store the value into an oop_Relocation cell, if any 347 CodeBlob* cb = CodeCache::find_blob(instruction_address()); 348 nmethod* nm = cb ? cb->as_nmethod_or_null() : NULL; 349 if (nm != NULL) { 350 RelocIterator iter(nm, instruction_address(), next_instruction_address()); 351 oop* oop_addr = NULL; 352 Metadata** metadata_addr = NULL; 353 while (iter.next()) { 354 if (iter.type() == relocInfo::oop_type) { 355 oop_Relocation *r = iter.oop_reloc(); 356 if (oop_addr == NULL) { 357 oop_addr = r->oop_addr(); 358 *oop_addr = cast_to_oop(x); 359 } else { 360 assert(oop_addr == r->oop_addr(), "must be only one set-oop here"); 361 } 362 } 363 if (iter.type() == relocInfo::metadata_type) { 364 metadata_Relocation *r = iter.metadata_reloc(); 365 if (metadata_addr == NULL) { 366 metadata_addr = r->metadata_addr(); 367 *metadata_addr = (Metadata*)x; 368 } else { 369 assert(metadata_addr == r->metadata_addr(), "must be only one set-metadata here"); 370 } 371 } 372 } 373 } 374 } 375 376 377 // Code for unit testing implementation of NativeMovConstReg class 378 void NativeMovConstReg::test() { 379 #ifdef ASSERT 380 ResourceMark rm; 381 CodeBuffer cb("test", 100, 100); 382 MacroAssembler* a = new MacroAssembler(&cb); 383 NativeMovConstReg* nm; 384 uint idx; 385 int offsets[] = { 386 0x0, 387 0x7fffffff, 388 0x80000000, 389 0xffffffff, 390 0x20, 391 4096, 392 4097, 393 }; 394 395 VM_Version::allow_all(); 396 397 AddressLiteral al1(0xaaaabbbb, relocInfo::external_word_type); 398 a->sethi(al1, I3); 399 a->add(I3, al1.low10(), I3); 400 AddressLiteral al2(0xccccdddd, relocInfo::external_word_type); 401 a->sethi(al2, O2); 402 a->add(O2, al2.low10(), O2); 403 404 nm = nativeMovConstReg_at( cb.insts_begin() ); 405 nm->print(); 406 407 nm = nativeMovConstReg_at( nm->next_instruction_address() ); 408 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) { 409 nm->set_data( offsets[idx] ); 410 assert(nm->data() == offsets[idx], "check unit test"); 411 } 412 nm->print(); 413 414 VM_Version::revert(); 415 #endif 416 } 417 // End code for unit testing implementation of NativeMovConstReg class 418 419 //------------------------------------------------------------------- 420 421 void NativeMovConstReg32::verify() { 422 NativeInstruction::verify(); 423 // make sure code pattern is actually a "set_metadata" synthetic instruction 424 // see MacroAssembler::set_oop() 425 int i0 = long_at(sethi_offset); 426 int i1 = long_at(add_offset); 427 428 // verify the pattern "sethi %hi22(imm), reg ; add reg, %lo10(imm), reg" 429 Register rd = inv_rd(i0); 430 if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) { 431 fatal("not a set_metadata"); 432 } 433 } 434 435 436 void NativeMovConstReg32::print() { 437 tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, p2i(instruction_address()), data()); 438 } 439 440 441 intptr_t NativeMovConstReg32::data() const { 442 return data32(long_at(sethi_offset), long_at(add_offset)); 443 } 444 445 446 void NativeMovConstReg32::set_data(intptr_t x) { 447 set_long_at(sethi_offset, set_data32_sethi( long_at(sethi_offset), x)); 448 set_long_at(add_offset, set_data32_simm13( long_at(add_offset), x)); 449 450 // also store the value into an oop_Relocation cell, if any 451 CodeBlob* cb = CodeCache::find_blob(instruction_address()); 452 nmethod* nm = cb ? cb->as_nmethod_or_null() : NULL; 453 if (nm != NULL) { 454 RelocIterator iter(nm, instruction_address(), next_instruction_address()); 455 oop* oop_addr = NULL; 456 Metadata** metadata_addr = NULL; 457 while (iter.next()) { 458 if (iter.type() == relocInfo::oop_type) { 459 oop_Relocation *r = iter.oop_reloc(); 460 if (oop_addr == NULL) { 461 oop_addr = r->oop_addr(); 462 *oop_addr = cast_to_oop(x); 463 } else { 464 assert(oop_addr == r->oop_addr(), "must be only one set-oop here"); 465 } 466 } 467 if (iter.type() == relocInfo::metadata_type) { 468 metadata_Relocation *r = iter.metadata_reloc(); 469 if (metadata_addr == NULL) { 470 metadata_addr = r->metadata_addr(); 471 *metadata_addr = (Metadata*)x; 472 } else { 473 assert(metadata_addr == r->metadata_addr(), "must be only one set-metadata here"); 474 } 475 } 476 } 477 } 478 } 479 480 //------------------------------------------------------------------- 481 482 void NativeMovConstRegPatching::verify() { 483 NativeInstruction::verify(); 484 // Make sure code pattern is sethi/nop/add. 485 int i0 = long_at(sethi_offset); 486 int i1 = long_at(nop_offset); 487 int i2 = long_at(add_offset); 488 assert((int)nop_offset == (int)NativeMovConstReg::add_offset, "sethi size ok"); 489 490 // Verify the pattern "sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg" 491 // The casual reader should note that on Sparc a nop is a special case if sethi 492 // in which the destination register is %g0. 493 Register rd0 = inv_rd(i0); 494 Register rd1 = inv_rd(i1); 495 if (!(is_op2(i0, Assembler::sethi_op2) && rd0 != G0 && 496 is_op2(i1, Assembler::sethi_op2) && rd1 == G0 && // nop is a special case of sethi 497 is_op3(i2, Assembler::add_op3, Assembler::arith_op) && 498 inv_immed(i2) && (unsigned)get_simm13(i2) < (1 << 10) && 499 rd0 == inv_rs1(i2) && rd0 == inv_rd(i2))) { 500 fatal("not a set_metadata"); 501 } 502 } 503 504 505 void NativeMovConstRegPatching::print() { 506 tty->print_cr(INTPTR_FORMAT ": mov reg, 0x%x", p2i(instruction_address()), data()); 507 } 508 509 510 int NativeMovConstRegPatching::data() const { 511 #ifdef _LP64 512 return data64(addr_at(sethi_offset), long_at(add_offset)); 513 #else 514 return data32(long_at(sethi_offset), long_at(add_offset)); 515 #endif 516 } 517 518 519 void NativeMovConstRegPatching::set_data(int x) { 520 #ifdef _LP64 521 set_data64_sethi(addr_at(sethi_offset), x); 522 #else 523 set_long_at(sethi_offset, set_data32_sethi(long_at(sethi_offset), x)); 524 #endif 525 set_long_at(add_offset, set_data32_simm13(long_at(add_offset), x)); 526 527 // also store the value into an oop_Relocation cell, if any 528 CodeBlob* cb = CodeCache::find_blob(instruction_address()); 529 nmethod* nm = cb ? cb->as_nmethod_or_null() : NULL; 530 if (nm != NULL) { 531 RelocIterator iter(nm, instruction_address(), next_instruction_address()); 532 oop* oop_addr = NULL; 533 Metadata** metadata_addr = NULL; 534 while (iter.next()) { 535 if (iter.type() == relocInfo::oop_type) { 536 oop_Relocation *r = iter.oop_reloc(); 537 if (oop_addr == NULL) { 538 oop_addr = r->oop_addr(); 539 *oop_addr = cast_to_oop(x); 540 } else { 541 assert(oop_addr == r->oop_addr(), "must be only one set-oop here"); 542 } 543 } 544 if (iter.type() == relocInfo::metadata_type) { 545 metadata_Relocation *r = iter.metadata_reloc(); 546 if (metadata_addr == NULL) { 547 metadata_addr = r->metadata_addr(); 548 *metadata_addr = (Metadata*)x; 549 } else { 550 assert(metadata_addr == r->metadata_addr(), "must be only one set-metadata here"); 551 } 552 } 553 } 554 } 555 } 556 557 558 // Code for unit testing implementation of NativeMovConstRegPatching class 559 void NativeMovConstRegPatching::test() { 560 #ifdef ASSERT 561 ResourceMark rm; 562 CodeBuffer cb("test", 100, 100); 563 MacroAssembler* a = new MacroAssembler(&cb); 564 NativeMovConstRegPatching* nm; 565 uint idx; 566 int offsets[] = { 567 0x0, 568 0x7fffffff, 569 0x80000000, 570 0xffffffff, 571 0x20, 572 4096, 573 4097, 574 }; 575 576 VM_Version::allow_all(); 577 578 AddressLiteral al1(0xaaaabbbb, relocInfo::external_word_type); 579 a->sethi(al1, I3); 580 a->nop(); 581 a->add(I3, al1.low10(), I3); 582 AddressLiteral al2(0xccccdddd, relocInfo::external_word_type); 583 a->sethi(al2, O2); 584 a->nop(); 585 a->add(O2, al2.low10(), O2); 586 587 nm = nativeMovConstRegPatching_at( cb.insts_begin() ); 588 nm->print(); 589 590 nm = nativeMovConstRegPatching_at( nm->next_instruction_address() ); 591 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) { 592 nm->set_data( offsets[idx] ); 593 assert(nm->data() == offsets[idx], "check unit test"); 594 } 595 nm->print(); 596 597 VM_Version::revert(); 598 #endif // ASSERT 599 } 600 // End code for unit testing implementation of NativeMovConstRegPatching class 601 602 603 //------------------------------------------------------------------- 604 605 606 void NativeMovRegMem::copy_instruction_to(address new_instruction_address) { 607 Untested("copy_instruction_to"); 608 int instruction_size = next_instruction_address() - instruction_address(); 609 for (int i = 0; i < instruction_size; i += BytesPerInstWord) { 610 *(int*)(new_instruction_address + i) = *(int*)(address(this) + i); 611 } 612 } 613 614 615 void NativeMovRegMem::verify() { 616 NativeInstruction::verify(); 617 // make sure code pattern is actually a "ld" or "st" of some sort. 618 int i0 = long_at(0); 619 int op3 = inv_op3(i0); 620 621 assert((int)add_offset == NativeMovConstReg::add_offset, "sethi size ok"); 622 623 if (!(is_op(i0, Assembler::ldst_op) && 624 inv_immed(i0) && 625 0 != (op3 < op3_ldst_int_limit 626 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st) 627 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf)))) 628 { 629 int i1 = long_at(ldst_offset); 630 Register rd = inv_rd(i0); 631 632 op3 = inv_op3(i1); 633 if (!is_op(i1, Assembler::ldst_op) && rd == inv_rs2(i1) && 634 0 != (op3 < op3_ldst_int_limit 635 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st) 636 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))) { 637 fatal("not a ld* or st* op"); 638 } 639 } 640 } 641 642 643 void NativeMovRegMem::print() { 644 if (is_immediate()) { 645 // offset is a signed 13-bit immediate, so casting it to int will not lose significant bits 646 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + %d]", p2i(instruction_address()), (int)offset()); 647 } else { 648 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + reg]", p2i(instruction_address())); 649 } 650 } 651 652 653 // Code for unit testing implementation of NativeMovRegMem class 654 void NativeMovRegMem::test() { 655 #ifdef ASSERT 656 ResourceMark rm; 657 CodeBuffer cb("test", 1000, 1000); 658 MacroAssembler* a = new MacroAssembler(&cb); 659 NativeMovRegMem* nm; 660 uint idx = 0; 661 uint idx1; 662 int offsets[] = { 663 0x0, 664 0xffffffff, 665 0x7fffffff, 666 0x80000000, 667 4096, 668 4097, 669 0x20, 670 0x4000, 671 }; 672 673 VM_Version::allow_all(); 674 675 AddressLiteral al1(0xffffffff, relocInfo::external_word_type); 676 AddressLiteral al2(0xaaaabbbb, relocInfo::external_word_type); 677 a->ldsw( G5, al1.low10(), G4 ); idx++; 678 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); 679 a->ldsw( G5, I3, G4 ); idx++; 680 a->ldsb( G5, al1.low10(), G4 ); idx++; 681 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); 682 a->ldsb( G5, I3, G4 ); idx++; 683 a->ldsh( G5, al1.low10(), G4 ); idx++; 684 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); 685 a->ldsh( G5, I3, G4 ); idx++; 686 a->lduw( G5, al1.low10(), G4 ); idx++; 687 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); 688 a->lduw( G5, I3, G4 ); idx++; 689 a->ldub( G5, al1.low10(), G4 ); idx++; 690 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); 691 a->ldub( G5, I3, G4 ); idx++; 692 a->lduh( G5, al1.low10(), G4 ); idx++; 693 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); 694 a->lduh( G5, I3, G4 ); idx++; 695 a->ldx( G5, al1.low10(), G4 ); idx++; 696 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); 697 a->ldx( G5, I3, G4 ); idx++; 698 a->ldd( G5, al1.low10(), G4 ); idx++; 699 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); 700 a->ldd( G5, I3, G4 ); idx++; 701 a->ldf( FloatRegisterImpl::D, O2, -1, F14 ); idx++; 702 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); 703 a->ldf( FloatRegisterImpl::S, O0, I3, F15 ); idx++; 704 705 a->stw( G5, G4, al1.low10() ); idx++; 706 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); 707 a->stw( G5, G4, I3 ); idx++; 708 a->stb( G5, G4, al1.low10() ); idx++; 709 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); 710 a->stb( G5, G4, I3 ); idx++; 711 a->sth( G5, G4, al1.low10() ); idx++; 712 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); 713 a->sth( G5, G4, I3 ); idx++; 714 a->stx( G5, G4, al1.low10() ); idx++; 715 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); 716 a->stx( G5, G4, I3 ); idx++; 717 a->std( G5, G4, al1.low10() ); idx++; 718 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); 719 a->std( G5, G4, I3 ); idx++; 720 a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++; 721 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); 722 a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++; 723 724 nm = nativeMovRegMem_at( cb.insts_begin() ); 725 nm->print(); 726 nm->set_offset( low10(0) ); 727 nm->print(); 728 nm->add_offset_in_bytes( low10(0xbb) * wordSize ); 729 nm->print(); 730 731 while (--idx) { 732 nm = nativeMovRegMem_at( nm->next_instruction_address() ); 733 nm->print(); 734 for (idx1 = 0; idx1 < ARRAY_SIZE(offsets); idx1++) { 735 nm->set_offset( nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1] ); 736 assert(nm->offset() == (nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1]), 737 "check unit test"); 738 nm->print(); 739 } 740 nm->add_offset_in_bytes( low10(0xbb) * wordSize ); 741 nm->print(); 742 } 743 744 VM_Version::revert(); 745 #endif // ASSERT 746 } 747 748 // End code for unit testing implementation of NativeMovRegMem class 749 750 751 //-------------------------------------------------------------------------------- 752 753 754 void NativeJump::verify() { 755 NativeInstruction::verify(); 756 int i0 = long_at(sethi_offset); 757 int i1 = long_at(jmpl_offset); 758 assert((int)jmpl_offset == (int)NativeMovConstReg::add_offset, "sethi size ok"); 759 // verify the pattern "sethi %hi22(imm), treg ; jmpl treg, %lo10(imm), lreg" 760 Register rd = inv_rd(i0); 761 #ifndef _LP64 762 if (!(is_op2(i0, Assembler::sethi_op2) && rd != G0 && 763 (is_op3(i1, Assembler::jmpl_op3, Assembler::arith_op)) && 764 inv_immed(i1) && (unsigned)get_simm13(i1) < (1 << 10) && 765 rd == inv_rs1(i1))) { 766 fatal("not a jump_to instruction"); 767 } 768 #else 769 // In LP64, the jump instruction location varies for non relocatable 770 // jumps, for example is could be sethi, xor, jmp instead of the 771 // 7 instructions for sethi. So let's check sethi only. 772 if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) { 773 fatal("not a jump_to instruction"); 774 } 775 #endif 776 } 777 778 779 void NativeJump::print() { 780 tty->print_cr(INTPTR_FORMAT ": jmpl reg, " INTPTR_FORMAT, p2i(instruction_address()), p2i(jump_destination())); 781 } 782 783 784 // Code for unit testing implementation of NativeJump class 785 void NativeJump::test() { 786 #ifdef ASSERT 787 ResourceMark rm; 788 CodeBuffer cb("test", 100, 100); 789 MacroAssembler* a = new MacroAssembler(&cb); 790 NativeJump* nj; 791 uint idx; 792 int offsets[] = { 793 0x0, 794 0xffffffff, 795 0x7fffffff, 796 0x80000000, 797 4096, 798 4097, 799 0x20, 800 0x4000, 801 }; 802 803 VM_Version::allow_all(); 804 805 AddressLiteral al(0x7fffbbbb, relocInfo::external_word_type); 806 a->sethi(al, I3); 807 a->jmpl(I3, al.low10(), G0, RelocationHolder::none); 808 a->delayed()->nop(); 809 a->sethi(al, I3); 810 a->jmpl(I3, al.low10(), L3, RelocationHolder::none); 811 a->delayed()->nop(); 812 813 nj = nativeJump_at( cb.insts_begin() ); 814 nj->print(); 815 816 nj = nativeJump_at( nj->next_instruction_address() ); 817 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) { 818 nj->set_jump_destination( nj->instruction_address() + offsets[idx] ); 819 assert(nj->jump_destination() == (nj->instruction_address() + offsets[idx]), "check unit test"); 820 nj->print(); 821 } 822 823 VM_Version::revert(); 824 #endif // ASSERT 825 } 826 // End code for unit testing implementation of NativeJump class 827 828 829 void NativeJump::insert(address code_pos, address entry) { 830 Unimplemented(); 831 } 832 833 // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie) 834 // The problem: jump_to <dest> is a 3-word instruction (including its delay slot). 835 // Atomic write can be only with 1 word. 836 void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) { 837 // Here's one way to do it: Pre-allocate a three-word jump sequence somewhere 838 // in the header of the nmethod, within a short branch's span of the patch point. 839 // Set up the jump sequence using NativeJump::insert, and then use an annulled 840 // unconditional branch at the target site (an atomic 1-word update). 841 // Limitations: You can only patch nmethods, with any given nmethod patched at 842 // most once, and the patch must be in the nmethod's header. 843 // It's messy, but you can ask the CodeCache for the nmethod containing the 844 // target address. 845 846 // %%%%% For now, do something MT-stupid: 847 ResourceMark rm; 848 int code_size = 1 * BytesPerInstWord; 849 CodeBuffer cb(verified_entry, code_size + 1); 850 MacroAssembler* a = new MacroAssembler(&cb); 851 a->ldsw(G0, 0, O7); // "ld" must agree with code in the signal handler 852 ICache::invalidate_range(verified_entry, code_size); 853 } 854 855 856 void NativeIllegalInstruction::insert(address code_pos) { 857 NativeIllegalInstruction* nii = (NativeIllegalInstruction*) nativeInstruction_at(code_pos); 858 nii->set_long_at(0, illegal_instruction()); 859 } 860 861 static int illegal_instruction_bits = 0; 862 863 int NativeInstruction::illegal_instruction() { 864 if (illegal_instruction_bits == 0) { 865 ResourceMark rm; 866 char buf[40]; 867 CodeBuffer cbuf((address)&buf[0], 20); 868 MacroAssembler* a = new MacroAssembler(&cbuf); 869 address ia = a->pc(); 870 a->trap(ST_RESERVED_FOR_USER_0 + 1); 871 int bits = *(int*)ia; 872 assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction"); 873 illegal_instruction_bits = bits; 874 assert(illegal_instruction_bits != 0, "oops"); 875 } 876 return illegal_instruction_bits; 877 } 878 879 static int ic_miss_trap_bits = 0; 880 881 bool NativeInstruction::is_ic_miss_trap() { 882 if (ic_miss_trap_bits == 0) { 883 ResourceMark rm; 884 char buf[40]; 885 CodeBuffer cbuf((address)&buf[0], 20); 886 MacroAssembler* a = new MacroAssembler(&cbuf); 887 address ia = a->pc(); 888 a->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0 + 2); 889 int bits = *(int*)ia; 890 assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction"); 891 ic_miss_trap_bits = bits; 892 assert(ic_miss_trap_bits != 0, "oops"); 893 } 894 return long_at(0) == ic_miss_trap_bits; 895 } 896 897 898 bool NativeInstruction::is_illegal() { 899 if (illegal_instruction_bits == 0) { 900 return false; 901 } 902 return long_at(0) == illegal_instruction_bits; 903 } 904 905 906 void NativeGeneralJump::verify() { 907 assert(((NativeInstruction *)this)->is_jump() || 908 ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction"); 909 } 910 911 912 void NativeGeneralJump::insert_unconditional(address code_pos, address entry) { 913 Assembler::Condition condition = Assembler::always; 914 int x = Assembler::op2(Assembler::br_op2) | Assembler::annul(false) | 915 Assembler::cond(condition) | Assembler::wdisp((intptr_t)entry, (intptr_t)code_pos, 22); 916 NativeGeneralJump* ni = (NativeGeneralJump*) nativeInstruction_at(code_pos); 917 ni->set_long_at(0, x); 918 } 919 920 921 // MT-safe patching of a jmp instruction (and following word). 922 // First patches the second word, and then atomicly replaces 923 // the first word with the first new instruction word. 924 // Other processors might briefly see the old first word 925 // followed by the new second word. This is OK if the old 926 // second word is harmless, and the new second word may be 927 // harmlessly executed in the delay slot of the call. 928 void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) { 929 assert(Patching_lock->is_locked() || 930 SafepointSynchronize::is_at_safepoint(), "concurrent code patching"); 931 assert (instr_addr != NULL, "illegal address for code patching"); 932 NativeGeneralJump* h_jump = nativeGeneralJump_at (instr_addr); // checking that it is a call 933 assert(NativeGeneralJump::instruction_size == 8, "wrong instruction size; must be 8"); 934 int i0 = ((int*)code_buffer)[0]; 935 int i1 = ((int*)code_buffer)[1]; 936 int* contention_addr = (int*) h_jump->addr_at(1*BytesPerInstWord); 937 assert(inv_op(*contention_addr) == Assembler::arith_op || 938 *contention_addr == nop_instruction(), 939 "must not interfere with original call"); 940 // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order 941 h_jump->set_long_at(1*BytesPerInstWord, i1); 942 h_jump->set_long_at(0*BytesPerInstWord, i0); 943 // NOTE: It is possible that another thread T will execute 944 // only the second patched word. 945 // In other words, since the original instruction is this 946 // jmp patching_stub; nop (NativeGeneralJump) 947 // and the new sequence from the buffer is this: 948 // sethi %hi(K), %r; add %r, %lo(K), %r (NativeMovConstReg) 949 // what T will execute is this: 950 // jmp patching_stub; add %r, %lo(K), %r 951 // thereby putting garbage into %r before calling the patching stub. 952 // This is OK, because the patching stub ignores the value of %r. 953 954 // Make sure the first-patched instruction, which may co-exist 955 // briefly with the call, will do something harmless. 956 assert(inv_op(*contention_addr) == Assembler::arith_op || 957 *contention_addr == nop_instruction(), 958 "must not interfere with original call"); 959 }