1 // 2 // Copyright (c) 1998, 2016, Oracle and/or its affiliates. All rights reserved. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 // 5 // This code is free software; you can redistribute it and/or modify it 6 // under the terms of the GNU General Public License version 2 only, as 7 // published by the Free Software Foundation. 8 // 9 // This code is distributed in the hope that it will be useful, but WITHOUT 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 // version 2 for more details (a copy is included in the LICENSE file that 13 // accompanied this code). 14 // 15 // You should have received a copy of the GNU General Public License version 16 // 2 along with this work; if not, write to the Free Software Foundation, 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 // 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 // or visit www.oracle.com if you need additional information or have any 21 // questions. 22 // 23 // 24 25 // SPARC Architecture Description File 26 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ 28 // This information is used by the matcher and the register allocator to 29 // describe individual registers and classes of registers within the target 30 // archtecture. 31 register %{ 32 //----------Architecture Description Register Definitions---------------------- 33 // General Registers 34 // "reg_def" name ( register save type, C convention save type, 35 // ideal register type, encoding, vm name ); 36 // Register Save Types: 37 // 38 // NS = No-Save: The register allocator assumes that these registers 39 // can be used without saving upon entry to the method, & 40 // that they do not need to be saved at call sites. 41 // 42 // SOC = Save-On-Call: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, 44 // but that they must be saved at call sites. 45 // 46 // SOE = Save-On-Entry: The register allocator assumes that these registers 47 // must be saved before using them upon entry to the 48 // method, but they do not need to be saved at call 49 // sites. 50 // 51 // AS = Always-Save: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, & that they must be saved at call sites. 54 // 55 // Ideal Register Type is used to determine how to save & restore a 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 58 // 59 // The encoding number is the actual bit-pattern placed into the opcodes. 60 61 62 // ---------------------------- 63 // Integer/Long Registers 64 // ---------------------------- 65 66 // Need to expose the hi/lo aspect of 64-bit registers 67 // This register set is used for both the 64-bit build and 68 // the 32-bit build with 1-register longs. 69 70 // Global Registers 0-7 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); 87 88 // Output Registers 0-7 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); 105 106 // Local Registers 0-7 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); 123 124 // Input Registers 0-7 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); 141 142 // ---------------------------- 143 // Float/Double Registers 144 // ---------------------------- 145 146 // Float Registers 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); 179 180 // Double Registers 181 // The rules of ADL require that double registers be defined in pairs. 182 // Each pair must be two 32-bit values, but not necessarily a pair of 183 // single float registers. In each pair, ADLC-assigned register numbers 184 // must be adjacent, with the lower number even. Finally, when the 185 // CPU stores such a register pair to memory, the word associated with 186 // the lower ADLC-assigned number must be stored to the lower address. 187 188 // These definitions specify the actual bit encodings of the sparc 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp 190 // wants 0-63, so we have to convert every time we want to use fp regs 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). 192 // 255 is a flag meaning "don't go here". 193 // I believe we can't handle callee-save doubles D32 and up until 194 // the place in the sparc stack crawler that asserts on the 255 is 195 // fixed up. 196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); 197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); 198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); 199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); 200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); 201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); 202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); 203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); 204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); 205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); 206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); 207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); 208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); 209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); 210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); 211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); 212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); 213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); 214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); 215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); 216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); 217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); 218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); 219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); 220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); 221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); 222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); 223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); 224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); 225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); 226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); 227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); 228 229 230 // ---------------------------- 231 // Special Registers 232 // Condition Codes Flag Registers 233 // I tried to break out ICC and XCC but it's not very pretty. 234 // Every Sparc instruction which defs/kills one also kills the other. 235 // Hence every compare instruction which defs one kind of flags ends 236 // up needing a kill of the other. 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 238 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); 243 244 // ---------------------------- 245 // Specify the enum values for the registers. These enums are only used by the 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed 247 // for visibility to the rest of the vm. The order of this enum influences the 248 // register allocator so having the freedom to set this order and not be stuck 249 // with the order that is natural for the rest of the vm is worth it. 250 alloc_class chunk0( 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); 255 256 // Note that a register is not allocatable unless it is also mentioned 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. 258 259 alloc_class chunk1( 260 // The first registers listed here are those most likely to be used 261 // as temporaries. We move F0..F7 away from the front of the list, 262 // to reduce the likelihood of interferences with parameters and 263 // return values. Likewise, we avoid using F0/F1 for parameters, 264 // since they are used for return values. 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); 274 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); 276 277 //----------Architecture Description Register Classes-------------------------- 278 // Several register classes are automatically defined based upon information in 279 // this architecture description. 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 283 // 284 285 // G0 is not included in integer class since it has special meaning. 286 reg_class g0_reg(R_G0); 287 288 // ---------------------------- 289 // Integer Register Classes 290 // ---------------------------- 291 // Exclusions from i_reg: 292 // R_G0: hardwired zero 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) 294 // R_G6: reserved by Solaris ABI to tools 295 // R_G7: reserved by Solaris ABI to libthread 296 // R_O7: Used as a temp in many encodings 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 298 299 // Class for all integer registers, except the G registers. This is used for 300 // encodings which use G registers as temps. The regular inputs to such 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator 302 // will not put an input into a temp register. 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 304 305 reg_class g1_regI(R_G1); 306 reg_class g3_regI(R_G3); 307 reg_class g4_regI(R_G4); 308 reg_class o0_regI(R_O0); 309 reg_class o7_regI(R_O7); 310 311 // ---------------------------- 312 // Pointer Register Classes 313 // ---------------------------- 314 #ifdef _LP64 315 // 64-bit build means 64-bit pointers means hi/lo pairs 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 320 // Lock encodings use G3 and G4 internally 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 325 // Special class for storeP instructions, which can store SP or RPC to TLS. 326 // It is also used for memory addressing, allowing direct TLS addressing. 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register 332 // We use it to save R_G2 across calls out of Java. 333 reg_class l7_regP(R_L7H,R_L7); 334 335 // Other special pointer regs 336 reg_class g1_regP(R_G1H,R_G1); 337 reg_class g2_regP(R_G2H,R_G2); 338 reg_class g3_regP(R_G3H,R_G3); 339 reg_class g4_regP(R_G4H,R_G4); 340 reg_class g5_regP(R_G5H,R_G5); 341 reg_class i0_regP(R_I0H,R_I0); 342 reg_class o0_regP(R_O0H,R_O0); 343 reg_class o1_regP(R_O1H,R_O1); 344 reg_class o2_regP(R_O2H,R_O2); 345 reg_class o7_regP(R_O7H,R_O7); 346 347 #else // _LP64 348 // 32-bit build means 32-bit pointers means 1 register. 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 353 // Lock encodings use G3 and G4 internally 354 reg_class lock_ptr_reg(R_G1, R_G5, 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 358 // Special class for storeP instructions, which can store SP or RPC to TLS. 359 // It is also used for memory addressing, allowing direct TLS addressing. 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register 365 // We use it to save R_G2 across calls out of Java. 366 reg_class l7_regP(R_L7); 367 368 // Other special pointer regs 369 reg_class g1_regP(R_G1); 370 reg_class g2_regP(R_G2); 371 reg_class g3_regP(R_G3); 372 reg_class g4_regP(R_G4); 373 reg_class g5_regP(R_G5); 374 reg_class i0_regP(R_I0); 375 reg_class o0_regP(R_O0); 376 reg_class o1_regP(R_O1); 377 reg_class o2_regP(R_O2); 378 reg_class o7_regP(R_O7); 379 #endif // _LP64 380 381 382 // ---------------------------- 383 // Long Register Classes 384 // ---------------------------- 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 389 #ifdef _LP64 390 // 64-bit, longs in 1 register: use all 64-bit integer registers 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 394 #endif // _LP64 395 ); 396 397 reg_class g1_regL(R_G1H,R_G1); 398 reg_class g3_regL(R_G3H,R_G3); 399 reg_class o2_regL(R_O2H,R_O2); 400 reg_class o7_regL(R_O7H,R_O7); 401 402 // ---------------------------- 403 // Special Class for Condition Code Flags Register 404 reg_class int_flags(CCR); 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); 406 reg_class float_flag0(FCC0); 407 408 409 // ---------------------------- 410 // Float Point Register Classes 411 // ---------------------------- 412 // Skip F30/F31, they are reserved for mem-mem copies 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 414 415 // Paired floating point registers--they show up in the same order as the floats, 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, 419 /* Use extra V9 double registers; this AD file does not support V8 */ 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x 422 ); 423 424 // Paired floating point registers--they show up in the same order as the floats, 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 426 // This class is usable for mis-aligned loads as happen in I2C adapters. 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 429 %} 430 431 //----------DEFINITION BLOCK--------------------------------------------------- 432 // Define name --> value mappings to inform the ADLC of an integer valued name 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] 434 // Format: 435 // int_def <name> ( <int_value>, <expression>); 436 // Generated Code in ad_<arch>.hpp 437 // #define <name> (<expression>) 438 // // value == <int_value> 439 // Generated code in ad_<arch>.cpp adlc_verification() 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 441 // 442 definitions %{ 443 // The default cost (of an ALU instruction). 444 int_def DEFAULT_COST ( 100, 100); 445 int_def HUGE_COST (1000000, 1000000); 446 447 // Memory refs are twice as expensive as run-of-the-mill. 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); 449 450 // Branches are even more expensive. 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); 453 %} 454 455 456 //----------SOURCE BLOCK------------------------------------------------------- 457 // This is a block of C++ code which provides values, functions, and 458 // definitions necessary in the rest of the architecture description 459 source_hpp %{ 460 // Header information of the source block. 461 // Method declarations/definitions which are used outside 462 // the ad-scope can conveniently be defined here. 463 // 464 // To keep related declarations/definitions/uses close together, 465 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 466 467 // Must be visible to the DFA in dfa_sparc.cpp 468 extern bool can_branch_register( Node *bol, Node *cmp ); 469 470 extern bool use_block_zeroing(Node* count); 471 472 // Macros to extract hi & lo halves from a long pair. 473 // G0 is not part of any long pair, so assert on that. 474 // Prevents accidentally using G1 instead of G0. 475 #define LONG_HI_REG(x) (x) 476 #define LONG_LO_REG(x) (x) 477 478 class CallStubImpl { 479 480 //-------------------------------------------------------------- 481 //---< Used for optimization in Compile::Shorten_branches >--- 482 //-------------------------------------------------------------- 483 484 public: 485 // Size of call trampoline stub. 486 static uint size_call_trampoline() { 487 return 0; // no call trampolines on this platform 488 } 489 490 // number of relocations needed by a call trampoline stub 491 static uint reloc_call_trampoline() { 492 return 0; // no call trampolines on this platform 493 } 494 }; 495 496 class HandlerImpl { 497 498 public: 499 500 static int emit_exception_handler(CodeBuffer &cbuf); 501 static int emit_deopt_handler(CodeBuffer& cbuf); 502 503 static uint size_exception_handler() { 504 return ( NativeJump::instruction_size ); // sethi;jmp;nop 505 } 506 507 static uint size_deopt_handler() { 508 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore 509 } 510 }; 511 512 %} 513 514 source %{ 515 #define __ _masm. 516 517 // tertiary op of a LoadP or StoreP encoding 518 #define REGP_OP true 519 520 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); 521 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); 522 static Register reg_to_register_object(int register_encoding); 523 524 // Used by the DFA in dfa_sparc.cpp. 525 // Check for being able to use a V9 branch-on-register. Requires a 526 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- 527 // extended. Doesn't work following an integer ADD, for example, because of 528 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On 529 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and 530 // replace them with zero, which could become sign-extension in a different OS 531 // release. There's no obvious reason why an interrupt will ever fill these 532 // bits with non-zero junk (the registers are reloaded with standard LD 533 // instructions which either zero-fill or sign-fill). 534 bool can_branch_register( Node *bol, Node *cmp ) { 535 if( !BranchOnRegister ) return false; 536 #ifdef _LP64 537 if( cmp->Opcode() == Op_CmpP ) 538 return true; // No problems with pointer compares 539 #endif 540 if( cmp->Opcode() == Op_CmpL ) 541 return true; // No problems with long compares 542 543 if( !SparcV9RegsHiBitsZero ) return false; 544 if( bol->as_Bool()->_test._test != BoolTest::ne && 545 bol->as_Bool()->_test._test != BoolTest::eq ) 546 return false; 547 548 // Check for comparing against a 'safe' value. Any operation which 549 // clears out the high word is safe. Thus, loads and certain shifts 550 // are safe, as are non-negative constants. Any operation which 551 // preserves zero bits in the high word is safe as long as each of its 552 // inputs are safe. Thus, phis and bitwise booleans are safe if their 553 // inputs are safe. At present, the only important case to recognize 554 // seems to be loads. Constants should fold away, and shifts & 555 // logicals can use the 'cc' forms. 556 Node *x = cmp->in(1); 557 if( x->is_Load() ) return true; 558 if( x->is_Phi() ) { 559 for( uint i = 1; i < x->req(); i++ ) 560 if( !x->in(i)->is_Load() ) 561 return false; 562 return true; 563 } 564 return false; 565 } 566 567 bool use_block_zeroing(Node* count) { 568 // Use BIS for zeroing if count is not constant 569 // or it is >= BlockZeroingLowLimit. 570 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit); 571 } 572 573 // **************************************************************************** 574 575 // REQUIRED FUNCTIONALITY 576 577 // !!!!! Special hack to get all type of calls to specify the byte offset 578 // from the start of the call to the point where the return address 579 // will point. 580 // The "return address" is the address of the call instruction, plus 8. 581 582 int MachCallStaticJavaNode::ret_addr_offset() { 583 int offset = NativeCall::instruction_size; // call; delay slot 584 if (_method_handle_invoke) 585 offset += 4; // restore SP 586 return offset; 587 } 588 589 int MachCallDynamicJavaNode::ret_addr_offset() { 590 int vtable_index = this->_vtable_index; 591 if (vtable_index < 0) { 592 // must be invalid_vtable_index, not nonvirtual_vtable_index 593 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 594 return (NativeMovConstReg::instruction_size + 595 NativeCall::instruction_size); // sethi; setlo; call; delay slot 596 } else { 597 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 598 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes(); 599 int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); 600 int klass_load_size; 601 if (UseCompressedClassPointers) { 602 assert(Universe::heap() != NULL, "java heap should be initialized"); 603 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; 604 } else { 605 klass_load_size = 1*BytesPerInstWord; 606 } 607 if (Assembler::is_simm13(v_off)) { 608 return klass_load_size + 609 (2*BytesPerInstWord + // ld_ptr, ld_ptr 610 NativeCall::instruction_size); // call; delay slot 611 } else { 612 return klass_load_size + 613 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr 614 NativeCall::instruction_size); // call; delay slot 615 } 616 } 617 } 618 619 int MachCallRuntimeNode::ret_addr_offset() { 620 #ifdef _LP64 621 if (MacroAssembler::is_far_target(entry_point())) { 622 return NativeFarCall::instruction_size; 623 } else { 624 return NativeCall::instruction_size; 625 } 626 #else 627 return NativeCall::instruction_size; // call; delay slot 628 #endif 629 } 630 631 // Indicate if the safepoint node needs the polling page as an input. 632 // Since Sparc does not have absolute addressing, it does. 633 bool SafePointNode::needs_polling_address_input() { 634 return true; 635 } 636 637 // emit an interrupt that is caught by the debugger (for debugging compiler) 638 void emit_break(CodeBuffer &cbuf) { 639 MacroAssembler _masm(&cbuf); 640 __ breakpoint_trap(); 641 } 642 643 #ifndef PRODUCT 644 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { 645 st->print("TA"); 646 } 647 #endif 648 649 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 650 emit_break(cbuf); 651 } 652 653 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 654 return MachNode::size(ra_); 655 } 656 657 // Traceable jump 658 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { 659 MacroAssembler _masm(&cbuf); 660 Register rdest = reg_to_register_object(jump_target); 661 __ JMP(rdest, 0); 662 __ delayed()->nop(); 663 } 664 665 // Traceable jump and set exception pc 666 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { 667 MacroAssembler _masm(&cbuf); 668 Register rdest = reg_to_register_object(jump_target); 669 __ JMP(rdest, 0); 670 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); 671 } 672 673 void emit_nop(CodeBuffer &cbuf) { 674 MacroAssembler _masm(&cbuf); 675 __ nop(); 676 } 677 678 void emit_illtrap(CodeBuffer &cbuf) { 679 MacroAssembler _masm(&cbuf); 680 __ illtrap(0); 681 } 682 683 684 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { 685 assert(n->rule() != loadUB_rule, ""); 686 687 intptr_t offset = 0; 688 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP 689 const Node* addr = n->get_base_and_disp(offset, adr_type); 690 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); 691 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); 692 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 693 atype = atype->add_offset(offset); 694 assert(disp32 == offset, "wrong disp32"); 695 return atype->_offset; 696 } 697 698 699 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { 700 assert(n->rule() != loadUB_rule, ""); 701 702 intptr_t offset = 0; 703 Node* addr = n->in(2); 704 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 705 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { 706 Node* a = addr->in(2/*AddPNode::Address*/); 707 Node* o = addr->in(3/*AddPNode::Offset*/); 708 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; 709 atype = a->bottom_type()->is_ptr()->add_offset(offset); 710 assert(atype->isa_oop_ptr(), "still an oop"); 711 } 712 offset = atype->is_ptr()->_offset; 713 if (offset != Type::OffsetBot) offset += disp32; 714 return offset; 715 } 716 717 static inline jlong replicate_immI(int con, int count, int width) { 718 // Load a constant replicated "count" times with width "width" 719 assert(count*width == 8 && width <= 4, "sanity"); 720 int bit_width = width * 8; 721 jlong val = con; 722 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits 723 for (int i = 0; i < count - 1; i++) { 724 val |= (val << bit_width); 725 } 726 return val; 727 } 728 729 static inline jlong replicate_immF(float con) { 730 // Replicate float con 2 times and pack into vector. 731 int val = *((int*)&con); 732 jlong lval = val; 733 lval = (lval << 32) | (lval & 0xFFFFFFFFl); 734 return lval; 735 } 736 737 // Standard Sparc opcode form2 field breakdown 738 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { 739 f0 &= (1<<19)-1; // Mask displacement to 19 bits 740 int op = (f30 << 30) | 741 (f29 << 29) | 742 (f25 << 25) | 743 (f22 << 22) | 744 (f20 << 20) | 745 (f19 << 19) | 746 (f0 << 0); 747 cbuf.insts()->emit_int32(op); 748 } 749 750 // Standard Sparc opcode form2 field breakdown 751 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { 752 f0 >>= 10; // Drop 10 bits 753 f0 &= (1<<22)-1; // Mask displacement to 22 bits 754 int op = (f30 << 30) | 755 (f25 << 25) | 756 (f22 << 22) | 757 (f0 << 0); 758 cbuf.insts()->emit_int32(op); 759 } 760 761 // Standard Sparc opcode form3 field breakdown 762 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { 763 int op = (f30 << 30) | 764 (f25 << 25) | 765 (f19 << 19) | 766 (f14 << 14) | 767 (f5 << 5) | 768 (f0 << 0); 769 cbuf.insts()->emit_int32(op); 770 } 771 772 // Standard Sparc opcode form3 field breakdown 773 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { 774 simm13 &= (1<<13)-1; // Mask to 13 bits 775 int op = (f30 << 30) | 776 (f25 << 25) | 777 (f19 << 19) | 778 (f14 << 14) | 779 (1 << 13) | // bit to indicate immediate-mode 780 (simm13<<0); 781 cbuf.insts()->emit_int32(op); 782 } 783 784 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { 785 simm10 &= (1<<10)-1; // Mask to 10 bits 786 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); 787 } 788 789 #ifdef ASSERT 790 // Helper function for VerifyOops in emit_form3_mem_reg 791 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { 792 warning("VerifyOops encountered unexpected instruction:"); 793 n->dump(2); 794 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 795 } 796 #endif 797 798 799 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary, 800 int src1_enc, int disp32, int src2_enc, int dst_enc) { 801 802 #ifdef ASSERT 803 // The following code implements the +VerifyOops feature. 804 // It verifies oop values which are loaded into or stored out of 805 // the current method activation. +VerifyOops complements techniques 806 // like ScavengeALot, because it eagerly inspects oops in transit, 807 // as they enter or leave the stack, as opposed to ScavengeALot, 808 // which inspects oops "at rest", in the stack or heap, at safepoints. 809 // For this reason, +VerifyOops can sometimes detect bugs very close 810 // to their point of creation. It can also serve as a cross-check 811 // on the validity of oop maps, when used toegether with ScavengeALot. 812 813 // It would be good to verify oops at other points, especially 814 // when an oop is used as a base pointer for a load or store. 815 // This is presently difficult, because it is hard to know when 816 // a base address is biased or not. (If we had such information, 817 // it would be easy and useful to make a two-argument version of 818 // verify_oop which unbiases the base, and performs verification.) 819 820 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); 821 bool is_verified_oop_base = false; 822 bool is_verified_oop_load = false; 823 bool is_verified_oop_store = false; 824 int tmp_enc = -1; 825 if (VerifyOops && src1_enc != R_SP_enc) { 826 // classify the op, mainly for an assert check 827 int st_op = 0, ld_op = 0; 828 switch (primary) { 829 case Assembler::stb_op3: st_op = Op_StoreB; break; 830 case Assembler::sth_op3: st_op = Op_StoreC; break; 831 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 832 case Assembler::stw_op3: st_op = Op_StoreI; break; 833 case Assembler::std_op3: st_op = Op_StoreL; break; 834 case Assembler::stf_op3: st_op = Op_StoreF; break; 835 case Assembler::stdf_op3: st_op = Op_StoreD; break; 836 837 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; 838 case Assembler::ldub_op3: ld_op = Op_LoadUB; break; 839 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; 840 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; 841 case Assembler::ldx_op3: // may become LoadP or stay LoadI 842 case Assembler::ldsw_op3: // may become LoadP or stay LoadI 843 case Assembler::lduw_op3: ld_op = Op_LoadI; break; 844 case Assembler::ldd_op3: ld_op = Op_LoadL; break; 845 case Assembler::ldf_op3: ld_op = Op_LoadF; break; 846 case Assembler::lddf_op3: ld_op = Op_LoadD; break; 847 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; 848 849 default: ShouldNotReachHere(); 850 } 851 if (tertiary == REGP_OP) { 852 if (st_op == Op_StoreI) st_op = Op_StoreP; 853 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; 854 else ShouldNotReachHere(); 855 if (st_op) { 856 // a store 857 // inputs are (0:control, 1:memory, 2:address, 3:value) 858 Node* n2 = n->in(3); 859 if (n2 != NULL) { 860 const Type* t = n2->bottom_type(); 861 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 862 } 863 } else { 864 // a load 865 const Type* t = n->bottom_type(); 866 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 867 } 868 } 869 870 if (ld_op) { 871 // a Load 872 // inputs are (0:control, 1:memory, 2:address) 873 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases 874 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && 875 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && 876 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && 877 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && 878 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && 879 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && 880 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && 881 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && 882 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && 883 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && 884 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) && 885 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) && 886 !(n->rule() == loadUB_rule)) { 887 verify_oops_warning(n, n->ideal_Opcode(), ld_op); 888 } 889 } else if (st_op) { 890 // a Store 891 // inputs are (0:control, 1:memory, 2:address, 3:value) 892 if (!(n->ideal_Opcode()==st_op) && // Following are special cases 893 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && 894 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && 895 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && 896 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && 897 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) && 898 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { 899 verify_oops_warning(n, n->ideal_Opcode(), st_op); 900 } 901 } 902 903 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { 904 Node* addr = n->in(2); 905 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { 906 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? 907 if (atype != NULL) { 908 intptr_t offset = get_offset_from_base(n, atype, disp32); 909 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); 910 if (offset != offset_2) { 911 get_offset_from_base(n, atype, disp32); 912 get_offset_from_base_2(n, atype, disp32); 913 } 914 assert(offset == offset_2, "different offsets"); 915 if (offset == disp32) { 916 // we now know that src1 is a true oop pointer 917 is_verified_oop_base = true; 918 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { 919 if( primary == Assembler::ldd_op3 ) { 920 is_verified_oop_base = false; // Cannot 'ldd' into O7 921 } else { 922 tmp_enc = dst_enc; 923 dst_enc = R_O7_enc; // Load into O7; preserve source oop 924 assert(src1_enc != dst_enc, ""); 925 } 926 } 927 } 928 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) 929 || offset == oopDesc::mark_offset_in_bytes())) { 930 // loading the mark should not be allowed either, but 931 // we don't check this since it conflicts with InlineObjectHash 932 // usage of LoadINode to get the mark. We could keep the 933 // check if we create a new LoadMarkNode 934 // but do not verify the object before its header is initialized 935 ShouldNotReachHere(); 936 } 937 } 938 } 939 } 940 } 941 #endif 942 943 uint instr = (Assembler::ldst_op << 30) 944 | (dst_enc << 25) 945 | (primary << 19) 946 | (src1_enc << 14); 947 948 uint index = src2_enc; 949 int disp = disp32; 950 951 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) { 952 disp += STACK_BIAS; 953 // Check that stack offset fits, load into O7 if not 954 if (!Assembler::is_simm13(disp)) { 955 MacroAssembler _masm(&cbuf); 956 __ set(disp, O7); 957 if (index != R_G0_enc) { 958 __ add(O7, reg_to_register_object(index), O7); 959 } 960 index = R_O7_enc; 961 disp = 0; 962 } 963 } 964 965 if( disp == 0 ) { 966 // use reg-reg form 967 // bit 13 is already zero 968 instr |= index; 969 } else { 970 // use reg-imm form 971 instr |= 0x00002000; // set bit 13 to one 972 instr |= disp & 0x1FFF; 973 } 974 975 cbuf.insts()->emit_int32(instr); 976 977 #ifdef ASSERT 978 if (VerifyOops) { 979 MacroAssembler _masm(&cbuf); 980 if (is_verified_oop_base) { 981 __ verify_oop(reg_to_register_object(src1_enc)); 982 } 983 if (is_verified_oop_store) { 984 __ verify_oop(reg_to_register_object(dst_enc)); 985 } 986 if (tmp_enc != -1) { 987 __ mov(O7, reg_to_register_object(tmp_enc)); 988 } 989 if (is_verified_oop_load) { 990 __ verify_oop(reg_to_register_object(dst_enc)); 991 } 992 } 993 #endif 994 } 995 996 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) { 997 // The method which records debug information at every safepoint 998 // expects the call to be the first instruction in the snippet as 999 // it creates a PcDesc structure which tracks the offset of a call 1000 // from the start of the codeBlob. This offset is computed as 1001 // code_end() - code_begin() of the code which has been emitted 1002 // so far. 1003 // In this particular case we have skirted around the problem by 1004 // putting the "mov" instruction in the delay slot but the problem 1005 // may bite us again at some other point and a cleaner/generic 1006 // solution using relocations would be needed. 1007 MacroAssembler _masm(&cbuf); 1008 __ set_inst_mark(); 1009 1010 // We flush the current window just so that there is a valid stack copy 1011 // the fact that the current window becomes active again instantly is 1012 // not a problem there is nothing live in it. 1013 1014 #ifdef ASSERT 1015 int startpos = __ offset(); 1016 #endif /* ASSERT */ 1017 1018 __ call((address)entry_point, rspec); 1019 1020 if (preserve_g2) __ delayed()->mov(G2, L7); 1021 else __ delayed()->nop(); 1022 1023 if (preserve_g2) __ mov(L7, G2); 1024 1025 #ifdef ASSERT 1026 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { 1027 #ifdef _LP64 1028 // Trash argument dump slots. 1029 __ set(0xb0b8ac0db0b8ac0d, G1); 1030 __ mov(G1, G5); 1031 __ stx(G1, SP, STACK_BIAS + 0x80); 1032 __ stx(G1, SP, STACK_BIAS + 0x88); 1033 __ stx(G1, SP, STACK_BIAS + 0x90); 1034 __ stx(G1, SP, STACK_BIAS + 0x98); 1035 __ stx(G1, SP, STACK_BIAS + 0xA0); 1036 __ stx(G1, SP, STACK_BIAS + 0xA8); 1037 #else // _LP64 1038 // this is also a native call, so smash the first 7 stack locations, 1039 // and the various registers 1040 1041 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], 1042 // while [SP+0x44..0x58] are the argument dump slots. 1043 __ set((intptr_t)0xbaadf00d, G1); 1044 __ mov(G1, G5); 1045 __ sllx(G1, 32, G1); 1046 __ or3(G1, G5, G1); 1047 __ mov(G1, G5); 1048 __ stx(G1, SP, 0x40); 1049 __ stx(G1, SP, 0x48); 1050 __ stx(G1, SP, 0x50); 1051 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot 1052 #endif // _LP64 1053 } 1054 #endif /*ASSERT*/ 1055 } 1056 1057 //============================================================================= 1058 // REQUIRED FUNCTIONALITY for encoding 1059 void emit_lo(CodeBuffer &cbuf, int val) { } 1060 void emit_hi(CodeBuffer &cbuf, int val) { } 1061 1062 1063 //============================================================================= 1064 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask(); 1065 1066 int Compile::ConstantTable::calculate_table_base_offset() const { 1067 if (UseRDPCForConstantTableBase) { 1068 // The table base offset might be less but then it fits into 1069 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit). 1070 return Assembler::min_simm13(); 1071 } else { 1072 int offset = -(size() / 2); 1073 if (!Assembler::is_simm13(offset)) { 1074 offset = Assembler::min_simm13(); 1075 } 1076 return offset; 1077 } 1078 } 1079 1080 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } 1081 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 1082 ShouldNotReachHere(); 1083 } 1084 1085 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1086 Compile* C = ra_->C; 1087 Compile::ConstantTable& constant_table = C->constant_table(); 1088 MacroAssembler _masm(&cbuf); 1089 1090 Register r = as_Register(ra_->get_encode(this)); 1091 CodeSection* consts_section = __ code()->consts(); 1092 int consts_size = consts_section->align_at_start(consts_section->size()); 1093 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size); 1094 1095 if (UseRDPCForConstantTableBase) { 1096 // For the following RDPC logic to work correctly the consts 1097 // section must be allocated right before the insts section. This 1098 // assert checks for that. The layout and the SECT_* constants 1099 // are defined in src/share/vm/asm/codeBuffer.hpp. 1100 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); 1101 int insts_offset = __ offset(); 1102 1103 // Layout: 1104 // 1105 // |----------- consts section ------------|----------- insts section -----------... 1106 // |------ constant table -----|- padding -|------------------x---- 1107 // \ current PC (RDPC instruction) 1108 // |<------------- consts_size ----------->|<- insts_offset ->| 1109 // \ table base 1110 // The table base offset is later added to the load displacement 1111 // so it has to be negative. 1112 int table_base_offset = -(consts_size + insts_offset); 1113 int disp; 1114 1115 // If the displacement from the current PC to the constant table 1116 // base fits into simm13 we set the constant table base to the 1117 // current PC. 1118 if (Assembler::is_simm13(table_base_offset)) { 1119 constant_table.set_table_base_offset(table_base_offset); 1120 disp = 0; 1121 } else { 1122 // Otherwise we set the constant table base offset to the 1123 // maximum negative displacement of load instructions to keep 1124 // the disp as small as possible: 1125 // 1126 // |<------------- consts_size ----------->|<- insts_offset ->| 1127 // |<--------- min_simm13 --------->|<-------- disp --------->| 1128 // \ table base 1129 table_base_offset = Assembler::min_simm13(); 1130 constant_table.set_table_base_offset(table_base_offset); 1131 disp = (consts_size + insts_offset) + table_base_offset; 1132 } 1133 1134 __ rdpc(r); 1135 1136 if (disp != 0) { 1137 assert(r != O7, "need temporary"); 1138 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); 1139 } 1140 } 1141 else { 1142 // Materialize the constant table base. 1143 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); 1144 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); 1145 AddressLiteral base(baseaddr, rspec); 1146 __ set(base, r); 1147 } 1148 } 1149 1150 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { 1151 if (UseRDPCForConstantTableBase) { 1152 // This is really the worst case but generally it's only 1 instruction. 1153 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; 1154 } else { 1155 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; 1156 } 1157 } 1158 1159 #ifndef PRODUCT 1160 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1161 char reg[128]; 1162 ra_->dump_register(this, reg); 1163 if (UseRDPCForConstantTableBase) { 1164 st->print("RDPC %s\t! constant table base", reg); 1165 } else { 1166 st->print("SET &constanttable,%s\t! constant table base", reg); 1167 } 1168 } 1169 #endif 1170 1171 1172 //============================================================================= 1173 1174 #ifndef PRODUCT 1175 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1176 Compile* C = ra_->C; 1177 1178 for (int i = 0; i < OptoPrologueNops; i++) { 1179 st->print_cr("NOP"); st->print("\t"); 1180 } 1181 1182 if( VerifyThread ) { 1183 st->print_cr("Verify_Thread"); st->print("\t"); 1184 } 1185 1186 size_t framesize = C->frame_size_in_bytes(); 1187 int bangsize = C->bang_size_in_bytes(); 1188 1189 // Calls to C2R adapters often do not accept exceptional returns. 1190 // We require that their callers must bang for them. But be careful, because 1191 // some VM calls (such as call site linkage) can use several kilobytes of 1192 // stack. But the stack safety zone should account for that. 1193 // See bugs 4446381, 4468289, 4497237. 1194 if (C->need_stack_bang(bangsize)) { 1195 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t"); 1196 } 1197 1198 if (Assembler::is_simm13(-framesize)) { 1199 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize); 1200 } else { 1201 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t"); 1202 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t"); 1203 st->print ("SAVE R_SP,R_G3,R_SP"); 1204 } 1205 1206 } 1207 #endif 1208 1209 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1210 Compile* C = ra_->C; 1211 MacroAssembler _masm(&cbuf); 1212 1213 for (int i = 0; i < OptoPrologueNops; i++) { 1214 __ nop(); 1215 } 1216 1217 __ verify_thread(); 1218 1219 size_t framesize = C->frame_size_in_bytes(); 1220 assert(framesize >= 16*wordSize, "must have room for reg. save area"); 1221 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); 1222 int bangsize = C->bang_size_in_bytes(); 1223 1224 // Calls to C2R adapters often do not accept exceptional returns. 1225 // We require that their callers must bang for them. But be careful, because 1226 // some VM calls (such as call site linkage) can use several kilobytes of 1227 // stack. But the stack safety zone should account for that. 1228 // See bugs 4446381, 4468289, 4497237. 1229 if (C->need_stack_bang(bangsize)) { 1230 __ generate_stack_overflow_check(bangsize); 1231 } 1232 1233 if (Assembler::is_simm13(-framesize)) { 1234 __ save(SP, -framesize, SP); 1235 } else { 1236 __ sethi(-framesize & ~0x3ff, G3); 1237 __ add(G3, -framesize & 0x3ff, G3); 1238 __ save(SP, G3, SP); 1239 } 1240 C->set_frame_complete( __ offset() ); 1241 1242 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { 1243 // NOTE: We set the table base offset here because users might be 1244 // emitted before MachConstantBaseNode. 1245 Compile::ConstantTable& constant_table = C->constant_table(); 1246 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); 1247 } 1248 } 1249 1250 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1251 return MachNode::size(ra_); 1252 } 1253 1254 int MachPrologNode::reloc() const { 1255 return 10; // a large enough number 1256 } 1257 1258 //============================================================================= 1259 #ifndef PRODUCT 1260 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1261 Compile* C = ra_->C; 1262 1263 if(do_polling() && ra_->C->is_method_compilation()) { 1264 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); 1265 #ifdef _LP64 1266 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); 1267 #else 1268 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); 1269 #endif 1270 } 1271 1272 if(do_polling()) { 1273 if (UseCBCond && !ra_->C->is_method_compilation()) { 1274 st->print("NOP\n\t"); 1275 } 1276 st->print("RET\n\t"); 1277 } 1278 1279 st->print("RESTORE"); 1280 } 1281 #endif 1282 1283 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1284 MacroAssembler _masm(&cbuf); 1285 Compile* C = ra_->C; 1286 1287 __ verify_thread(); 1288 1289 if (StackReservedPages > 0 && C->has_reserved_stack_access()) { 1290 __ reserved_stack_check(); 1291 } 1292 1293 // If this does safepoint polling, then do it here 1294 if(do_polling() && ra_->C->is_method_compilation()) { 1295 AddressLiteral polling_page(os::get_polling_page()); 1296 __ sethi(polling_page, L0); 1297 __ relocate(relocInfo::poll_return_type); 1298 __ ld_ptr(L0, 0, G0); 1299 } 1300 1301 // If this is a return, then stuff the restore in the delay slot 1302 if(do_polling()) { 1303 if (UseCBCond && !ra_->C->is_method_compilation()) { 1304 // Insert extra padding for the case when the epilogue is preceded by 1305 // a cbcond jump, which can't be followed by a CTI instruction 1306 __ nop(); 1307 } 1308 __ ret(); 1309 __ delayed()->restore(); 1310 } else { 1311 __ restore(); 1312 } 1313 } 1314 1315 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1316 return MachNode::size(ra_); 1317 } 1318 1319 int MachEpilogNode::reloc() const { 1320 return 16; // a large enough number 1321 } 1322 1323 const Pipeline * MachEpilogNode::pipeline() const { 1324 return MachNode::pipeline_class(); 1325 } 1326 1327 int MachEpilogNode::safepoint_offset() const { 1328 assert( do_polling(), "no return for this epilog node"); 1329 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; 1330 } 1331 1332 //============================================================================= 1333 1334 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack 1335 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1336 static enum RC rc_class( OptoReg::Name reg ) { 1337 if (!OptoReg::is_valid(reg)) return rc_bad; 1338 if (OptoReg::is_stack(reg)) return rc_stack; 1339 VMReg r = OptoReg::as_VMReg(reg); 1340 if (r->is_Register()) return rc_int; 1341 assert(r->is_FloatRegister(), "must be"); 1342 return rc_float; 1343 } 1344 1345 #ifndef PRODUCT 1346 ATTRIBUTE_PRINTF(2, 3) 1347 static void print_helper(outputStream* st, const char* format, ...) { 1348 if (st->position() > 0) { 1349 st->cr(); 1350 st->sp(); 1351 } 1352 va_list ap; 1353 va_start(ap, format); 1354 st->vprint(format, ap); 1355 va_end(ap); 1356 } 1357 #endif // !PRODUCT 1358 1359 static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) { 1360 if (cbuf) { 1361 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); 1362 } 1363 #ifndef PRODUCT 1364 else { 1365 if (is_load) { 1366 print_helper(st, "%s [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg)); 1367 } else { 1368 print_helper(st, "%s R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset); 1369 } 1370 } 1371 #endif 1372 } 1373 1374 static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) { 1375 if (cbuf) { 1376 emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]); 1377 } 1378 #ifndef PRODUCT 1379 else { 1380 print_helper(st, "%s R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst)); 1381 } 1382 #endif 1383 } 1384 1385 static void mach_spill_copy_implementation_helper(const MachNode* mach, 1386 CodeBuffer *cbuf, 1387 PhaseRegAlloc *ra_, 1388 outputStream* st) { 1389 // Get registers to move 1390 OptoReg::Name src_second = ra_->get_reg_second(mach->in(1)); 1391 OptoReg::Name src_first = ra_->get_reg_first(mach->in(1)); 1392 OptoReg::Name dst_second = ra_->get_reg_second(mach); 1393 OptoReg::Name dst_first = ra_->get_reg_first(mach); 1394 1395 enum RC src_second_rc = rc_class(src_second); 1396 enum RC src_first_rc = rc_class(src_first); 1397 enum RC dst_second_rc = rc_class(dst_second); 1398 enum RC dst_first_rc = rc_class(dst_first); 1399 1400 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register"); 1401 1402 if (src_first == dst_first && src_second == dst_second) { 1403 return; // Self copy, no move 1404 } 1405 1406 // -------------------------------------- 1407 // Check for mem-mem move. Load into unused float registers and fall into 1408 // the float-store case. 1409 if (src_first_rc == rc_stack && dst_first_rc == rc_stack) { 1410 int offset = ra_->reg2offset(src_first); 1411 // Further check for aligned-adjacent pair, so we can use a double load 1412 if ((src_first&1) == 0 && src_first+1 == src_second) { 1413 src_second = OptoReg::Name(R_F31_num); 1414 src_second_rc = rc_float; 1415 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st); 1416 } else { 1417 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st); 1418 } 1419 src_first = OptoReg::Name(R_F30_num); 1420 src_first_rc = rc_float; 1421 } 1422 1423 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { 1424 int offset = ra_->reg2offset(src_second); 1425 impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st); 1426 src_second = OptoReg::Name(R_F31_num); 1427 src_second_rc = rc_float; 1428 } 1429 1430 // -------------------------------------- 1431 // Check for float->int copy; requires a trip through memory 1432 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { 1433 int offset = frame::register_save_words*wordSize; 1434 if (cbuf) { 1435 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16); 1436 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st); 1437 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st); 1438 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16); 1439 } 1440 #ifndef PRODUCT 1441 else { 1442 print_helper(st, "SUB R_SP,16,R_SP"); 1443 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st); 1444 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st); 1445 print_helper(st, "ADD R_SP,16,R_SP"); 1446 } 1447 #endif 1448 } 1449 1450 // Check for float->int copy on T4 1451 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { 1452 // Further check for aligned-adjacent pair, so we can use a double move 1453 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1454 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st); 1455 return; 1456 } 1457 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st); 1458 } 1459 // Check for int->float copy on T4 1460 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { 1461 // Further check for aligned-adjacent pair, so we can use a double move 1462 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1463 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st); 1464 return; 1465 } 1466 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st); 1467 } 1468 1469 // -------------------------------------- 1470 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. 1471 // In such cases, I have to do the big-endian swap. For aligned targets, the 1472 // hardware does the flop for me. Doubles are always aligned, so no problem 1473 // there. Misaligned sources only come from native-long-returns (handled 1474 // special below). 1475 #ifndef _LP64 1476 if (src_first_rc == rc_int && // source is already big-endian 1477 src_second_rc != rc_bad && // 64-bit move 1478 ((dst_first & 1) != 0 || dst_second != dst_first + 1)) { // misaligned dst 1479 assert((src_first & 1) == 0 && src_second == src_first + 1, "source must be aligned"); 1480 // Do the big-endian flop. 1481 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; 1482 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; 1483 } 1484 #endif 1485 1486 // -------------------------------------- 1487 // Check for integer reg-reg copy 1488 if (src_first_rc == rc_int && dst_first_rc == rc_int) { 1489 #ifndef _LP64 1490 if (src_first == R_O0_num && src_second == R_O1_num) { // Check for the evil O0/O1 native long-return case 1491 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1492 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1493 // operand contains the least significant word of the 64-bit value and vice versa. 1494 OptoReg::Name tmp = OptoReg::Name(R_O7_num); 1495 assert((dst_first & 1) == 0 && dst_second == dst_first + 1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); 1496 // Shift O0 left in-place, zero-extend O1, then OR them into the dst 1497 if ( cbuf ) { 1498 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020); 1499 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000); 1500 emit3 (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second]); 1501 #ifndef PRODUCT 1502 } else { 1503 print_helper(st, "SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); 1504 print_helper(st, "SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); 1505 print_helper(st, "OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); 1506 #endif 1507 } 1508 return; 1509 } else if (dst_first == R_I0_num && dst_second == R_I1_num) { 1510 // returning a long value in I0/I1 1511 // a SpillCopy must be able to target a return instruction's reg_class 1512 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1513 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1514 // operand contains the least significant word of the 64-bit value and vice versa. 1515 OptoReg::Name tdest = dst_first; 1516 1517 if (src_first == dst_first) { 1518 tdest = OptoReg::Name(R_O7_num); 1519 } 1520 1521 if (cbuf) { 1522 assert((src_first & 1) == 0 && (src_first + 1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); 1523 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 1524 // ShrL_reg_imm6 1525 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000); 1526 // ShrR_reg_imm6 src, 0, dst 1527 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000); 1528 if (tdest != dst_first) { 1529 emit3 (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest]); 1530 } 1531 } 1532 #ifndef PRODUCT 1533 else { 1534 print_helper(st, "SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); 1535 print_helper(st, "SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); 1536 if (tdest != dst_first) { 1537 print_helper(st, "MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); 1538 } 1539 } 1540 #endif // PRODUCT 1541 return size+8; 1542 } 1543 #endif // !_LP64 1544 // Else normal reg-reg copy 1545 assert(src_second != dst_first, "smashed second before evacuating it"); 1546 impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV ", st); 1547 assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers"); 1548 // This moves an aligned adjacent pair. 1549 // See if we are done. 1550 if (src_first + 1 == src_second && dst_first + 1 == dst_second) { 1551 return; 1552 } 1553 } 1554 1555 // Check for integer store 1556 if (src_first_rc == rc_int && dst_first_rc == rc_stack) { 1557 int offset = ra_->reg2offset(dst_first); 1558 // Further check for aligned-adjacent pair, so we can use a double store 1559 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1560 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st); 1561 return; 1562 } 1563 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st); 1564 } 1565 1566 // Check for integer load 1567 if (dst_first_rc == rc_int && src_first_rc == rc_stack) { 1568 int offset = ra_->reg2offset(src_first); 1569 // Further check for aligned-adjacent pair, so we can use a double load 1570 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1571 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st); 1572 return; 1573 } 1574 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st); 1575 } 1576 1577 // Check for float reg-reg copy 1578 if (src_first_rc == rc_float && dst_first_rc == rc_float) { 1579 // Further check for aligned-adjacent pair, so we can use a double move 1580 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1581 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st); 1582 return; 1583 } 1584 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st); 1585 } 1586 1587 // Check for float store 1588 if (src_first_rc == rc_float && dst_first_rc == rc_stack) { 1589 int offset = ra_->reg2offset(dst_first); 1590 // Further check for aligned-adjacent pair, so we can use a double store 1591 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1592 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st); 1593 return; 1594 } 1595 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st); 1596 } 1597 1598 // Check for float load 1599 if (dst_first_rc == rc_float && src_first_rc == rc_stack) { 1600 int offset = ra_->reg2offset(src_first); 1601 // Further check for aligned-adjacent pair, so we can use a double load 1602 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1603 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st); 1604 return; 1605 } 1606 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st); 1607 } 1608 1609 // -------------------------------------------------------------------- 1610 // Check for hi bits still needing moving. Only happens for misaligned 1611 // arguments to native calls. 1612 if (src_second == dst_second) { 1613 return; // Self copy; no move 1614 } 1615 assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad"); 1616 1617 #ifndef _LP64 1618 // In the LP64 build, all registers can be moved as aligned/adjacent 1619 // pairs, so there's never any need to move the high bits separately. 1620 // The 32-bit builds have to deal with the 32-bit ABI which can force 1621 // all sorts of silly alignment problems. 1622 1623 // Check for integer reg-reg copy. Hi bits are stuck up in the top 1624 // 32-bits of a 64-bit register, but are needed in low bits of another 1625 // register (else it's a hi-bits-to-hi-bits copy which should have 1626 // happened already as part of a 64-bit move) 1627 if (src_second_rc == rc_int && dst_second_rc == rc_int) { 1628 assert((src_second & 1) == 1, "its the evil O0/O1 native return case"); 1629 assert((dst_second & 1) == 0, "should have moved with 1 64-bit move"); 1630 // Shift src_second down to dst_second's low bits. 1631 if (cbuf) { 1632 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020); 1633 #ifndef PRODUCT 1634 } else { 1635 print_helper(st, "SRLX R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second - 1), OptoReg::regname(dst_second)); 1636 #endif 1637 } 1638 return; 1639 } 1640 1641 // Check for high word integer store. Must down-shift the hi bits 1642 // into a temp register, then fall into the case of storing int bits. 1643 if (src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second & 1) == 1) { 1644 // Shift src_second down to dst_second's low bits. 1645 if (cbuf) { 1646 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020); 1647 #ifndef PRODUCT 1648 } else { 1649 print_helper(st, "SRLX R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second-1), OptoReg::regname(R_O7_num)); 1650 #endif 1651 } 1652 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! 1653 } 1654 1655 // Check for high word integer load 1656 if (dst_second_rc == rc_int && src_second_rc == rc_stack) 1657 return impl_helper(this, cbuf, ra_, true, ra_->reg2offset(src_second), dst_second, Assembler::lduw_op3, "LDUW", size, st); 1658 1659 // Check for high word integer store 1660 if (src_second_rc == rc_int && dst_second_rc == rc_stack) 1661 return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stw_op3, "STW ", size, st); 1662 1663 // Check for high word float store 1664 if (src_second_rc == rc_float && dst_second_rc == rc_stack) 1665 return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stf_op3, "STF ", size, st); 1666 1667 #endif // !_LP64 1668 1669 Unimplemented(); 1670 } 1671 1672 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, 1673 PhaseRegAlloc *ra_, 1674 bool do_size, 1675 outputStream* st) const { 1676 assert(!do_size, "not supported"); 1677 mach_spill_copy_implementation_helper(this, cbuf, ra_, st); 1678 return 0; 1679 } 1680 1681 #ifndef PRODUCT 1682 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1683 implementation( NULL, ra_, false, st ); 1684 } 1685 #endif 1686 1687 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1688 implementation( &cbuf, ra_, false, NULL ); 1689 } 1690 1691 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1692 return MachNode::size(ra_); 1693 } 1694 1695 //============================================================================= 1696 #ifndef PRODUCT 1697 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const { 1698 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); 1699 } 1700 #endif 1701 1702 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const { 1703 MacroAssembler _masm(&cbuf); 1704 for (int i = 0; i < _count; i += 1) { 1705 __ nop(); 1706 } 1707 } 1708 1709 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1710 return 4 * _count; 1711 } 1712 1713 1714 //============================================================================= 1715 #ifndef PRODUCT 1716 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1717 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1718 int reg = ra_->get_reg_first(this); 1719 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); 1720 } 1721 #endif 1722 1723 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1724 MacroAssembler _masm(&cbuf); 1725 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; 1726 int reg = ra_->get_encode(this); 1727 1728 if (Assembler::is_simm13(offset)) { 1729 __ add(SP, offset, reg_to_register_object(reg)); 1730 } else { 1731 __ set(offset, O7); 1732 __ add(SP, O7, reg_to_register_object(reg)); 1733 } 1734 } 1735 1736 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1737 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1738 assert(ra_ == ra_->C->regalloc(), "sanity"); 1739 return ra_->C->scratch_emit_size(this); 1740 } 1741 1742 //============================================================================= 1743 #ifndef PRODUCT 1744 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1745 st->print_cr("\nUEP:"); 1746 #ifdef _LP64 1747 if (UseCompressedClassPointers) { 1748 assert(Universe::heap() != NULL, "java heap should be initialized"); 1749 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); 1750 if (Universe::narrow_klass_base() != 0) { 1751 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base"); 1752 if (Universe::narrow_klass_shift() != 0) { 1753 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); 1754 } 1755 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); 1756 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base"); 1757 } else { 1758 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); 1759 } 1760 } else { 1761 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1762 } 1763 st->print_cr("\tCMP R_G5,R_G3" ); 1764 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1765 #else // _LP64 1766 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1767 st->print_cr("\tCMP R_G5,R_G3" ); 1768 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1769 #endif // _LP64 1770 } 1771 #endif 1772 1773 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1774 MacroAssembler _masm(&cbuf); 1775 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 1776 Register temp_reg = G3; 1777 assert( G5_ic_reg != temp_reg, "conflicting registers" ); 1778 1779 // Load klass from receiver 1780 __ load_klass(O0, temp_reg); 1781 // Compare against expected klass 1782 __ cmp(temp_reg, G5_ic_reg); 1783 // Branch to miss code, checks xcc or icc depending 1784 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); 1785 } 1786 1787 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1788 return MachNode::size(ra_); 1789 } 1790 1791 1792 //============================================================================= 1793 1794 1795 // Emit exception handler code. 1796 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) { 1797 Register temp_reg = G3; 1798 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); 1799 MacroAssembler _masm(&cbuf); 1800 1801 address base = __ start_a_stub(size_exception_handler()); 1802 if (base == NULL) { 1803 ciEnv::current()->record_failure("CodeCache is full"); 1804 return 0; // CodeBuffer::expand failed 1805 } 1806 1807 int offset = __ offset(); 1808 1809 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp 1810 __ delayed()->nop(); 1811 1812 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1813 1814 __ end_a_stub(); 1815 1816 return offset; 1817 } 1818 1819 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 1820 // Can't use any of the current frame's registers as we may have deopted 1821 // at a poll and everything (including G3) can be live. 1822 Register temp_reg = L0; 1823 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 1824 MacroAssembler _masm(&cbuf); 1825 1826 address base = __ start_a_stub(size_deopt_handler()); 1827 if (base == NULL) { 1828 ciEnv::current()->record_failure("CodeCache is full"); 1829 return 0; // CodeBuffer::expand failed 1830 } 1831 1832 int offset = __ offset(); 1833 __ save_frame(0); 1834 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp 1835 __ delayed()->restore(); 1836 1837 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1838 1839 __ end_a_stub(); 1840 return offset; 1841 1842 } 1843 1844 // Given a register encoding, produce a Integer Register object 1845 static Register reg_to_register_object(int register_encoding) { 1846 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); 1847 return as_Register(register_encoding); 1848 } 1849 1850 // Given a register encoding, produce a single-precision Float Register object 1851 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { 1852 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); 1853 return as_SingleFloatRegister(register_encoding); 1854 } 1855 1856 // Given a register encoding, produce a double-precision Float Register object 1857 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { 1858 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); 1859 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); 1860 return as_DoubleFloatRegister(register_encoding); 1861 } 1862 1863 const bool Matcher::match_rule_supported(int opcode) { 1864 if (!has_match_rule(opcode)) 1865 return false; 1866 1867 switch (opcode) { 1868 case Op_CountLeadingZerosI: 1869 case Op_CountLeadingZerosL: 1870 case Op_CountTrailingZerosI: 1871 case Op_CountTrailingZerosL: 1872 case Op_PopCountI: 1873 case Op_PopCountL: 1874 if (!UsePopCountInstruction) 1875 return false; 1876 case Op_CompareAndSwapL: 1877 #ifdef _LP64 1878 case Op_CompareAndSwapP: 1879 #endif 1880 if (!VM_Version::supports_cx8()) 1881 return false; 1882 break; 1883 } 1884 1885 return true; // Per default match rules are supported. 1886 } 1887 1888 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) { 1889 1890 // TODO 1891 // identify extra cases that we might want to provide match rules for 1892 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen 1893 bool ret_value = match_rule_supported(opcode); 1894 // Add rules here. 1895 1896 return ret_value; // Per default match rules are supported. 1897 } 1898 1899 const bool Matcher::has_predicated_vectors(void) { 1900 return false; 1901 } 1902 1903 const int Matcher::float_pressure(int default_pressure_threshold) { 1904 return default_pressure_threshold; 1905 } 1906 1907 int Matcher::regnum_to_fpu_offset(int regnum) { 1908 return regnum - 32; // The FP registers are in the second chunk 1909 } 1910 1911 #ifdef ASSERT 1912 address last_rethrow = NULL; // debugging aid for Rethrow encoding 1913 #endif 1914 1915 // Vector width in bytes 1916 const int Matcher::vector_width_in_bytes(BasicType bt) { 1917 assert(MaxVectorSize == 8, ""); 1918 return 8; 1919 } 1920 1921 // Vector ideal reg 1922 const int Matcher::vector_ideal_reg(int size) { 1923 assert(MaxVectorSize == 8, ""); 1924 return Op_RegD; 1925 } 1926 1927 const int Matcher::vector_shift_count_ideal_reg(int size) { 1928 fatal("vector shift is not supported"); 1929 return Node::NotAMachineReg; 1930 } 1931 1932 // Limits on vector size (number of elements) loaded into vector. 1933 const int Matcher::max_vector_size(const BasicType bt) { 1934 assert(is_java_primitive(bt), "only primitive type vectors"); 1935 return vector_width_in_bytes(bt)/type2aelembytes(bt); 1936 } 1937 1938 const int Matcher::min_vector_size(const BasicType bt) { 1939 return max_vector_size(bt); // Same as max. 1940 } 1941 1942 // SPARC doesn't support misaligned vectors store/load. 1943 const bool Matcher::misaligned_vectors_ok() { 1944 return false; 1945 } 1946 1947 // Current (2013) SPARC platforms need to read original key 1948 // to construct decryption expanded key 1949 const bool Matcher::pass_original_key_for_aes() { 1950 return true; 1951 } 1952 1953 // USII supports fxtof through the whole range of number, USIII doesn't 1954 const bool Matcher::convL2FSupported(void) { 1955 return VM_Version::has_fast_fxtof(); 1956 } 1957 1958 // Is this branch offset short enough that a short branch can be used? 1959 // 1960 // NOTE: If the platform does not provide any short branch variants, then 1961 // this method should return false for offset 0. 1962 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 1963 // The passed offset is relative to address of the branch. 1964 // Don't need to adjust the offset. 1965 return UseCBCond && Assembler::is_simm12(offset); 1966 } 1967 1968 const bool Matcher::isSimpleConstant64(jlong value) { 1969 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1970 // Depends on optimizations in MacroAssembler::setx. 1971 int hi = (int)(value >> 32); 1972 int lo = (int)(value & ~0); 1973 return (hi == 0) || (hi == -1) || (lo == 0); 1974 } 1975 1976 // No scaling for the parameter the ClearArray node. 1977 const bool Matcher::init_array_count_is_in_bytes = true; 1978 1979 // No additional cost for CMOVL. 1980 const int Matcher::long_cmove_cost() { return 0; } 1981 1982 // CMOVF/CMOVD are expensive on T4 and on SPARC64. 1983 const int Matcher::float_cmove_cost() { 1984 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; 1985 } 1986 1987 // Does the CPU require late expand (see block.cpp for description of late expand)? 1988 const bool Matcher::require_postalloc_expand = false; 1989 1990 // Do we need to mask the count passed to shift instructions or does 1991 // the cpu only look at the lower 5/6 bits anyway? 1992 const bool Matcher::need_masked_shift_count = false; 1993 1994 bool Matcher::narrow_oop_use_complex_address() { 1995 NOT_LP64(ShouldNotCallThis()); 1996 assert(UseCompressedOops, "only for compressed oops code"); 1997 return false; 1998 } 1999 2000 bool Matcher::narrow_klass_use_complex_address() { 2001 NOT_LP64(ShouldNotCallThis()); 2002 assert(UseCompressedClassPointers, "only for compressed klass code"); 2003 return false; 2004 } 2005 2006 bool Matcher::const_oop_prefer_decode() { 2007 // TODO: Check if loading ConP from TOC in heap-based mode is better: 2008 // Prefer ConN+DecodeN over ConP in simple compressed oops mode. 2009 // return Universe::narrow_oop_base() == NULL; 2010 return true; 2011 } 2012 2013 bool Matcher::const_klass_prefer_decode() { 2014 // TODO: Check if loading ConP from TOC in heap-based mode is better: 2015 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode. 2016 // return Universe::narrow_klass_base() == NULL; 2017 return true; 2018 } 2019 2020 // Is it better to copy float constants, or load them directly from memory? 2021 // Intel can load a float constant from a direct address, requiring no 2022 // extra registers. Most RISCs will have to materialize an address into a 2023 // register first, so they would do better to copy the constant from stack. 2024 const bool Matcher::rematerialize_float_constants = false; 2025 2026 // If CPU can load and store mis-aligned doubles directly then no fixup is 2027 // needed. Else we split the double into 2 integer pieces and move it 2028 // piece-by-piece. Only happens when passing doubles into C code as the 2029 // Java calling convention forces doubles to be aligned. 2030 #ifdef _LP64 2031 const bool Matcher::misaligned_doubles_ok = true; 2032 #else 2033 const bool Matcher::misaligned_doubles_ok = false; 2034 #endif 2035 2036 // No-op on SPARC. 2037 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 2038 } 2039 2040 // Advertise here if the CPU requires explicit rounding operations 2041 // to implement the UseStrictFP mode. 2042 const bool Matcher::strict_fp_requires_explicit_rounding = false; 2043 2044 // Are floats converted to double when stored to stack during deoptimization? 2045 // Sparc does not handle callee-save floats. 2046 bool Matcher::float_in_double() { return false; } 2047 2048 // Do ints take an entire long register or just half? 2049 // Note that we if-def off of _LP64. 2050 // The relevant question is how the int is callee-saved. In _LP64 2051 // the whole long is written but de-opt'ing will have to extract 2052 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. 2053 #ifdef _LP64 2054 const bool Matcher::int_in_long = true; 2055 #else 2056 const bool Matcher::int_in_long = false; 2057 #endif 2058 2059 // Return whether or not this register is ever used as an argument. This 2060 // function is used on startup to build the trampoline stubs in generateOptoStub. 2061 // Registers not mentioned will be killed by the VM call in the trampoline, and 2062 // arguments in those registers not be available to the callee. 2063 bool Matcher::can_be_java_arg( int reg ) { 2064 // Standard sparc 6 args in registers 2065 if( reg == R_I0_num || 2066 reg == R_I1_num || 2067 reg == R_I2_num || 2068 reg == R_I3_num || 2069 reg == R_I4_num || 2070 reg == R_I5_num ) return true; 2071 #ifdef _LP64 2072 // 64-bit builds can pass 64-bit pointers and longs in 2073 // the high I registers 2074 if( reg == R_I0H_num || 2075 reg == R_I1H_num || 2076 reg == R_I2H_num || 2077 reg == R_I3H_num || 2078 reg == R_I4H_num || 2079 reg == R_I5H_num ) return true; 2080 2081 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { 2082 return true; 2083 } 2084 2085 #else 2086 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. 2087 // Longs cannot be passed in O regs, because O regs become I regs 2088 // after a 'save' and I regs get their high bits chopped off on 2089 // interrupt. 2090 if( reg == R_G1H_num || reg == R_G1_num ) return true; 2091 if( reg == R_G4H_num || reg == R_G4_num ) return true; 2092 #endif 2093 // A few float args in registers 2094 if( reg >= R_F0_num && reg <= R_F7_num ) return true; 2095 2096 return false; 2097 } 2098 2099 bool Matcher::is_spillable_arg( int reg ) { 2100 return can_be_java_arg(reg); 2101 } 2102 2103 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { 2104 // Use hardware SDIVX instruction when it is 2105 // faster than a code which use multiply. 2106 return VM_Version::has_fast_idiv(); 2107 } 2108 2109 // Register for DIVI projection of divmodI 2110 RegMask Matcher::divI_proj_mask() { 2111 ShouldNotReachHere(); 2112 return RegMask(); 2113 } 2114 2115 // Register for MODI projection of divmodI 2116 RegMask Matcher::modI_proj_mask() { 2117 ShouldNotReachHere(); 2118 return RegMask(); 2119 } 2120 2121 // Register for DIVL projection of divmodL 2122 RegMask Matcher::divL_proj_mask() { 2123 ShouldNotReachHere(); 2124 return RegMask(); 2125 } 2126 2127 // Register for MODL projection of divmodL 2128 RegMask Matcher::modL_proj_mask() { 2129 ShouldNotReachHere(); 2130 return RegMask(); 2131 } 2132 2133 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 2134 return L7_REGP_mask(); 2135 } 2136 2137 2138 const bool Matcher::convi2l_type_required = true; 2139 2140 // Should the Matcher clone shifts on addressing modes, expecting them 2141 // to be subsumed into complex addressing expressions or compute them 2142 // into registers? 2143 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) { 2144 return clone_base_plus_offset_address(m, mstack, address_visited); 2145 } 2146 2147 void Compile::reshape_address(AddPNode* addp) { 2148 } 2149 2150 %} 2151 2152 2153 // The intptr_t operand types, defined by textual substitution. 2154 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) 2155 #ifdef _LP64 2156 #define immX immL 2157 #define immX13 immL13 2158 #define immX13m7 immL13m7 2159 #define iRegX iRegL 2160 #define g1RegX g1RegL 2161 #else 2162 #define immX immI 2163 #define immX13 immI13 2164 #define immX13m7 immI13m7 2165 #define iRegX iRegI 2166 #define g1RegX g1RegI 2167 #endif 2168 2169 //----------ENCODING BLOCK----------------------------------------------------- 2170 // This block specifies the encoding classes used by the compiler to output 2171 // byte streams. Encoding classes are parameterized macros used by 2172 // Machine Instruction Nodes in order to generate the bit encoding of the 2173 // instruction. Operands specify their base encoding interface with the 2174 // interface keyword. There are currently supported four interfaces, 2175 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 2176 // operand to generate a function which returns its register number when 2177 // queried. CONST_INTER causes an operand to generate a function which 2178 // returns the value of the constant when queried. MEMORY_INTER causes an 2179 // operand to generate four functions which return the Base Register, the 2180 // Index Register, the Scale Value, and the Offset Value of the operand when 2181 // queried. COND_INTER causes an operand to generate six functions which 2182 // return the encoding code (ie - encoding bits for the instruction) 2183 // associated with each basic boolean condition for a conditional instruction. 2184 // 2185 // Instructions specify two basic values for encoding. Again, a function 2186 // is available to check if the constant displacement is an oop. They use the 2187 // ins_encode keyword to specify their encoding classes (which must be 2188 // a sequence of enc_class names, and their parameters, specified in 2189 // the encoding block), and they use the 2190 // opcode keyword to specify, in order, their primary, secondary, and 2191 // tertiary opcode. Only the opcode sections which a particular instruction 2192 // needs for encoding need to be specified. 2193 encode %{ 2194 enc_class enc_untested %{ 2195 #ifdef ASSERT 2196 MacroAssembler _masm(&cbuf); 2197 __ untested("encoding"); 2198 #endif 2199 %} 2200 2201 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 2202 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary, 2203 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2204 %} 2205 2206 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ 2207 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2208 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2209 %} 2210 2211 enc_class form3_mem_prefetch_read( memory mem ) %{ 2212 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2213 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 2214 %} 2215 2216 enc_class form3_mem_prefetch_write( memory mem ) %{ 2217 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2218 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 2219 %} 2220 2221 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 2222 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2223 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2224 guarantee($mem$$index == R_G0_enc, "double index?"); 2225 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 2226 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 2227 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 2228 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 2229 %} 2230 2231 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 2232 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2233 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2234 guarantee($mem$$index == R_G0_enc, "double index?"); 2235 // Load long with 2 instructions 2236 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 2237 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 2238 %} 2239 2240 //%%% form3_mem_plus_4_reg is a hack--get rid of it 2241 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 2242 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 2243 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 2244 %} 2245 2246 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 2247 // Encode a reg-reg copy. If it is useless, then empty encoding. 2248 if( $rs2$$reg != $rd$$reg ) 2249 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); 2250 %} 2251 2252 // Target lo half of long 2253 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ 2254 // Encode a reg-reg copy. If it is useless, then empty encoding. 2255 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) 2256 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); 2257 %} 2258 2259 // Source lo half of long 2260 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ 2261 // Encode a reg-reg copy. If it is useless, then empty encoding. 2262 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) 2263 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); 2264 %} 2265 2266 // Target hi half of long 2267 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ 2268 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); 2269 %} 2270 2271 // Source lo half of long, and leave it sign extended. 2272 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ 2273 // Sign extend low half 2274 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); 2275 %} 2276 2277 // Source hi half of long, and leave it sign extended. 2278 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ 2279 // Shift high half to low half 2280 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); 2281 %} 2282 2283 // Source hi half of long 2284 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ 2285 // Encode a reg-reg copy. If it is useless, then empty encoding. 2286 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) 2287 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); 2288 %} 2289 2290 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ 2291 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); 2292 %} 2293 2294 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ 2295 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); 2296 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); 2297 %} 2298 2299 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ 2300 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); 2301 // clear if nothing else is happening 2302 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); 2303 // blt,a,pn done 2304 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); 2305 // mov dst,-1 in delay slot 2306 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2307 %} 2308 2309 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ 2310 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); 2311 %} 2312 2313 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ 2314 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); 2315 %} 2316 2317 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ 2318 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); 2319 %} 2320 2321 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ 2322 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); 2323 %} 2324 2325 enc_class move_return_pc_to_o1() %{ 2326 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); 2327 %} 2328 2329 #ifdef _LP64 2330 /* %%% merge with enc_to_bool */ 2331 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ 2332 MacroAssembler _masm(&cbuf); 2333 2334 Register src_reg = reg_to_register_object($src$$reg); 2335 Register dst_reg = reg_to_register_object($dst$$reg); 2336 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); 2337 %} 2338 #endif 2339 2340 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ 2341 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) 2342 MacroAssembler _masm(&cbuf); 2343 2344 Register p_reg = reg_to_register_object($p$$reg); 2345 Register q_reg = reg_to_register_object($q$$reg); 2346 Register y_reg = reg_to_register_object($y$$reg); 2347 Register tmp_reg = reg_to_register_object($tmp$$reg); 2348 2349 __ subcc( p_reg, q_reg, p_reg ); 2350 __ add ( p_reg, y_reg, tmp_reg ); 2351 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); 2352 %} 2353 2354 enc_class form_d2i_helper(regD src, regF dst) %{ 2355 // fcmp %fcc0,$src,$src 2356 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2357 // branch %fcc0 not-nan, predict taken 2358 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2359 // fdtoi $src,$dst 2360 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); 2361 // fitos $dst,$dst (if nan) 2362 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2363 // clear $dst (if nan) 2364 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2365 // carry on here... 2366 %} 2367 2368 enc_class form_d2l_helper(regD src, regD dst) %{ 2369 // fcmp %fcc0,$src,$src check for NAN 2370 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2371 // branch %fcc0 not-nan, predict taken 2372 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2373 // fdtox $src,$dst convert in delay slot 2374 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); 2375 // fxtod $dst,$dst (if nan) 2376 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2377 // clear $dst (if nan) 2378 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2379 // carry on here... 2380 %} 2381 2382 enc_class form_f2i_helper(regF src, regF dst) %{ 2383 // fcmps %fcc0,$src,$src 2384 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2385 // branch %fcc0 not-nan, predict taken 2386 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2387 // fstoi $src,$dst 2388 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); 2389 // fitos $dst,$dst (if nan) 2390 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2391 // clear $dst (if nan) 2392 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2393 // carry on here... 2394 %} 2395 2396 enc_class form_f2l_helper(regF src, regD dst) %{ 2397 // fcmps %fcc0,$src,$src 2398 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2399 // branch %fcc0 not-nan, predict taken 2400 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2401 // fstox $src,$dst 2402 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); 2403 // fxtod $dst,$dst (if nan) 2404 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2405 // clear $dst (if nan) 2406 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2407 // carry on here... 2408 %} 2409 2410 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2411 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2412 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2413 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2414 2415 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} 2416 2417 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2418 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} 2419 2420 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ 2421 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2422 %} 2423 2424 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ 2425 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2426 %} 2427 2428 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ 2429 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2430 %} 2431 2432 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ 2433 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2434 %} 2435 2436 enc_class form3_convI2F(regF rs2, regF rd) %{ 2437 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); 2438 %} 2439 2440 // Encloding class for traceable jumps 2441 enc_class form_jmpl(g3RegP dest) %{ 2442 emit_jmpl(cbuf, $dest$$reg); 2443 %} 2444 2445 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ 2446 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); 2447 %} 2448 2449 enc_class form2_nop() %{ 2450 emit_nop(cbuf); 2451 %} 2452 2453 enc_class form2_illtrap() %{ 2454 emit_illtrap(cbuf); 2455 %} 2456 2457 2458 // Compare longs and convert into -1, 0, 1. 2459 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ 2460 // CMP $src1,$src2 2461 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); 2462 // blt,a,pn done 2463 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); 2464 // mov dst,-1 in delay slot 2465 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2466 // bgt,a,pn done 2467 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); 2468 // mov dst,1 in delay slot 2469 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); 2470 // CLR $dst 2471 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); 2472 %} 2473 2474 enc_class enc_PartialSubtypeCheck() %{ 2475 MacroAssembler _masm(&cbuf); 2476 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); 2477 __ delayed()->nop(); 2478 %} 2479 2480 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ 2481 MacroAssembler _masm(&cbuf); 2482 Label* L = $labl$$label; 2483 Assembler::Predict predict_taken = 2484 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2485 2486 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 2487 __ delayed()->nop(); 2488 %} 2489 2490 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ 2491 MacroAssembler _masm(&cbuf); 2492 Label* L = $labl$$label; 2493 Assembler::Predict predict_taken = 2494 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2495 2496 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); 2497 __ delayed()->nop(); 2498 %} 2499 2500 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ 2501 int op = (Assembler::arith_op << 30) | 2502 ($dst$$reg << 25) | 2503 (Assembler::movcc_op3 << 19) | 2504 (1 << 18) | // cc2 bit for 'icc' 2505 ($cmp$$cmpcode << 14) | 2506 (0 << 13) | // select register move 2507 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' 2508 ($src$$reg << 0); 2509 cbuf.insts()->emit_int32(op); 2510 %} 2511 2512 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ 2513 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2514 int op = (Assembler::arith_op << 30) | 2515 ($dst$$reg << 25) | 2516 (Assembler::movcc_op3 << 19) | 2517 (1 << 18) | // cc2 bit for 'icc' 2518 ($cmp$$cmpcode << 14) | 2519 (1 << 13) | // select immediate move 2520 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' 2521 (simm11 << 0); 2522 cbuf.insts()->emit_int32(op); 2523 %} 2524 2525 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ 2526 int op = (Assembler::arith_op << 30) | 2527 ($dst$$reg << 25) | 2528 (Assembler::movcc_op3 << 19) | 2529 (0 << 18) | // cc2 bit for 'fccX' 2530 ($cmp$$cmpcode << 14) | 2531 (0 << 13) | // select register move 2532 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2533 ($src$$reg << 0); 2534 cbuf.insts()->emit_int32(op); 2535 %} 2536 2537 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ 2538 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2539 int op = (Assembler::arith_op << 30) | 2540 ($dst$$reg << 25) | 2541 (Assembler::movcc_op3 << 19) | 2542 (0 << 18) | // cc2 bit for 'fccX' 2543 ($cmp$$cmpcode << 14) | 2544 (1 << 13) | // select immediate move 2545 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2546 (simm11 << 0); 2547 cbuf.insts()->emit_int32(op); 2548 %} 2549 2550 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ 2551 int op = (Assembler::arith_op << 30) | 2552 ($dst$$reg << 25) | 2553 (Assembler::fpop2_op3 << 19) | 2554 (0 << 18) | 2555 ($cmp$$cmpcode << 14) | 2556 (1 << 13) | // select register move 2557 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' 2558 ($primary << 5) | // select single, double or quad 2559 ($src$$reg << 0); 2560 cbuf.insts()->emit_int32(op); 2561 %} 2562 2563 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ 2564 int op = (Assembler::arith_op << 30) | 2565 ($dst$$reg << 25) | 2566 (Assembler::fpop2_op3 << 19) | 2567 (0 << 18) | 2568 ($cmp$$cmpcode << 14) | 2569 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' 2570 ($primary << 5) | // select single, double or quad 2571 ($src$$reg << 0); 2572 cbuf.insts()->emit_int32(op); 2573 %} 2574 2575 // Used by the MIN/MAX encodings. Same as a CMOV, but 2576 // the condition comes from opcode-field instead of an argument. 2577 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ 2578 int op = (Assembler::arith_op << 30) | 2579 ($dst$$reg << 25) | 2580 (Assembler::movcc_op3 << 19) | 2581 (1 << 18) | // cc2 bit for 'icc' 2582 ($primary << 14) | 2583 (0 << 13) | // select register move 2584 (0 << 11) | // cc1, cc0 bits for 'icc' 2585 ($src$$reg << 0); 2586 cbuf.insts()->emit_int32(op); 2587 %} 2588 2589 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ 2590 int op = (Assembler::arith_op << 30) | 2591 ($dst$$reg << 25) | 2592 (Assembler::movcc_op3 << 19) | 2593 (6 << 16) | // cc2 bit for 'xcc' 2594 ($primary << 14) | 2595 (0 << 13) | // select register move 2596 (0 << 11) | // cc1, cc0 bits for 'icc' 2597 ($src$$reg << 0); 2598 cbuf.insts()->emit_int32(op); 2599 %} 2600 2601 enc_class Set13( immI13 src, iRegI rd ) %{ 2602 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); 2603 %} 2604 2605 enc_class SetHi22( immI src, iRegI rd ) %{ 2606 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); 2607 %} 2608 2609 enc_class Set32( immI src, iRegI rd ) %{ 2610 MacroAssembler _masm(&cbuf); 2611 __ set($src$$constant, reg_to_register_object($rd$$reg)); 2612 %} 2613 2614 enc_class call_epilog %{ 2615 if( VerifyStackAtCalls ) { 2616 MacroAssembler _masm(&cbuf); 2617 int framesize = ra_->C->frame_size_in_bytes(); 2618 Register temp_reg = G3; 2619 __ add(SP, framesize, temp_reg); 2620 __ cmp(temp_reg, FP); 2621 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); 2622 } 2623 %} 2624 2625 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value 2626 // to G1 so the register allocator will not have to deal with the misaligned register 2627 // pair. 2628 enc_class adjust_long_from_native_call %{ 2629 #ifndef _LP64 2630 if (returns_long()) { 2631 // sllx O0,32,O0 2632 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); 2633 // srl O1,0,O1 2634 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); 2635 // or O0,O1,G1 2636 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); 2637 } 2638 #endif 2639 %} 2640 2641 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime 2642 // CALL directly to the runtime 2643 // The user of this is responsible for ensuring that R_L7 is empty (killed). 2644 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true); 2645 %} 2646 2647 enc_class preserve_SP %{ 2648 MacroAssembler _masm(&cbuf); 2649 __ mov(SP, L7_mh_SP_save); 2650 %} 2651 2652 enc_class restore_SP %{ 2653 MacroAssembler _masm(&cbuf); 2654 __ mov(L7_mh_SP_save, SP); 2655 %} 2656 2657 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 2658 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2659 // who we intended to call. 2660 if (!_method) { 2661 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec()); 2662 } else { 2663 int method_index = resolved_method_index(cbuf); 2664 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index) 2665 : static_call_Relocation::spec(method_index); 2666 emit_call_reloc(cbuf, $meth$$method, rspec); 2667 2668 // Emit stub for static call. 2669 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); 2670 if (stub == NULL) { 2671 ciEnv::current()->record_failure("CodeCache is full"); 2672 return; 2673 } 2674 } 2675 %} 2676 2677 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 2678 MacroAssembler _masm(&cbuf); 2679 __ set_inst_mark(); 2680 int vtable_index = this->_vtable_index; 2681 // MachCallDynamicJavaNode::ret_addr_offset uses this same test 2682 if (vtable_index < 0) { 2683 // must be invalid_vtable_index, not nonvirtual_vtable_index 2684 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 2685 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2686 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); 2687 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); 2688 __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf)); 2689 } else { 2690 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2691 // Just go thru the vtable 2692 // get receiver klass (receiver already checked for non-null) 2693 // If we end up going thru a c2i adapter interpreter expects method in G5 2694 int off = __ offset(); 2695 __ load_klass(O0, G3_scratch); 2696 int klass_load_size; 2697 if (UseCompressedClassPointers) { 2698 assert(Universe::heap() != NULL, "java heap should be initialized"); 2699 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; 2700 } else { 2701 klass_load_size = 1*BytesPerInstWord; 2702 } 2703 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes(); 2704 int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); 2705 if (Assembler::is_simm13(v_off)) { 2706 __ ld_ptr(G3, v_off, G5_method); 2707 } else { 2708 // Generate 2 instructions 2709 __ Assembler::sethi(v_off & ~0x3ff, G5_method); 2710 __ or3(G5_method, v_off & 0x3ff, G5_method); 2711 // ld_ptr, set_hi, set 2712 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, 2713 "Unexpected instruction size(s)"); 2714 __ ld_ptr(G3, G5_method, G5_method); 2715 } 2716 // NOTE: for vtable dispatches, the vtable entry will never be null. 2717 // However it may very well end up in handle_wrong_method if the 2718 // method is abstract for the particular class. 2719 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch); 2720 // jump to target (either compiled code or c2iadapter) 2721 __ jmpl(G3_scratch, G0, O7); 2722 __ delayed()->nop(); 2723 } 2724 %} 2725 2726 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 2727 MacroAssembler _masm(&cbuf); 2728 2729 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2730 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because 2731 // we might be calling a C2I adapter which needs it. 2732 2733 assert(temp_reg != G5_ic_reg, "conflicting registers"); 2734 // Load nmethod 2735 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg); 2736 2737 // CALL to compiled java, indirect the contents of G3 2738 __ set_inst_mark(); 2739 __ callr(temp_reg, G0); 2740 __ delayed()->nop(); 2741 %} 2742 2743 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ 2744 MacroAssembler _masm(&cbuf); 2745 Register Rdividend = reg_to_register_object($src1$$reg); 2746 Register Rdivisor = reg_to_register_object($src2$$reg); 2747 Register Rresult = reg_to_register_object($dst$$reg); 2748 2749 __ sra(Rdivisor, 0, Rdivisor); 2750 __ sra(Rdividend, 0, Rdividend); 2751 __ sdivx(Rdividend, Rdivisor, Rresult); 2752 %} 2753 2754 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ 2755 MacroAssembler _masm(&cbuf); 2756 2757 Register Rdividend = reg_to_register_object($src1$$reg); 2758 int divisor = $imm$$constant; 2759 Register Rresult = reg_to_register_object($dst$$reg); 2760 2761 __ sra(Rdividend, 0, Rdividend); 2762 __ sdivx(Rdividend, divisor, Rresult); 2763 %} 2764 2765 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ 2766 MacroAssembler _masm(&cbuf); 2767 Register Rsrc1 = reg_to_register_object($src1$$reg); 2768 Register Rsrc2 = reg_to_register_object($src2$$reg); 2769 Register Rdst = reg_to_register_object($dst$$reg); 2770 2771 __ sra( Rsrc1, 0, Rsrc1 ); 2772 __ sra( Rsrc2, 0, Rsrc2 ); 2773 __ mulx( Rsrc1, Rsrc2, Rdst ); 2774 __ srlx( Rdst, 32, Rdst ); 2775 %} 2776 2777 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ 2778 MacroAssembler _masm(&cbuf); 2779 Register Rdividend = reg_to_register_object($src1$$reg); 2780 Register Rdivisor = reg_to_register_object($src2$$reg); 2781 Register Rresult = reg_to_register_object($dst$$reg); 2782 Register Rscratch = reg_to_register_object($scratch$$reg); 2783 2784 assert(Rdividend != Rscratch, ""); 2785 assert(Rdivisor != Rscratch, ""); 2786 2787 __ sra(Rdividend, 0, Rdividend); 2788 __ sra(Rdivisor, 0, Rdivisor); 2789 __ sdivx(Rdividend, Rdivisor, Rscratch); 2790 __ mulx(Rscratch, Rdivisor, Rscratch); 2791 __ sub(Rdividend, Rscratch, Rresult); 2792 %} 2793 2794 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ 2795 MacroAssembler _masm(&cbuf); 2796 2797 Register Rdividend = reg_to_register_object($src1$$reg); 2798 int divisor = $imm$$constant; 2799 Register Rresult = reg_to_register_object($dst$$reg); 2800 Register Rscratch = reg_to_register_object($scratch$$reg); 2801 2802 assert(Rdividend != Rscratch, ""); 2803 2804 __ sra(Rdividend, 0, Rdividend); 2805 __ sdivx(Rdividend, divisor, Rscratch); 2806 __ mulx(Rscratch, divisor, Rscratch); 2807 __ sub(Rdividend, Rscratch, Rresult); 2808 %} 2809 2810 enc_class fabss (sflt_reg dst, sflt_reg src) %{ 2811 MacroAssembler _masm(&cbuf); 2812 2813 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2814 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2815 2816 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); 2817 %} 2818 2819 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ 2820 MacroAssembler _masm(&cbuf); 2821 2822 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2823 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2824 2825 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); 2826 %} 2827 2828 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ 2829 MacroAssembler _masm(&cbuf); 2830 2831 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2832 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2833 2834 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); 2835 %} 2836 2837 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ 2838 MacroAssembler _masm(&cbuf); 2839 2840 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2841 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2842 2843 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); 2844 %} 2845 2846 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ 2847 MacroAssembler _masm(&cbuf); 2848 2849 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2850 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2851 2852 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); 2853 %} 2854 2855 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ 2856 MacroAssembler _masm(&cbuf); 2857 2858 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2859 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2860 2861 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); 2862 %} 2863 2864 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ 2865 MacroAssembler _masm(&cbuf); 2866 2867 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2868 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2869 2870 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); 2871 %} 2872 2873 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2874 MacroAssembler _masm(&cbuf); 2875 2876 Register Roop = reg_to_register_object($oop$$reg); 2877 Register Rbox = reg_to_register_object($box$$reg); 2878 Register Rscratch = reg_to_register_object($scratch$$reg); 2879 Register Rmark = reg_to_register_object($scratch2$$reg); 2880 2881 assert(Roop != Rscratch, ""); 2882 assert(Roop != Rmark, ""); 2883 assert(Rbox != Rscratch, ""); 2884 assert(Rbox != Rmark, ""); 2885 2886 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); 2887 %} 2888 2889 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2890 MacroAssembler _masm(&cbuf); 2891 2892 Register Roop = reg_to_register_object($oop$$reg); 2893 Register Rbox = reg_to_register_object($box$$reg); 2894 Register Rscratch = reg_to_register_object($scratch$$reg); 2895 Register Rmark = reg_to_register_object($scratch2$$reg); 2896 2897 assert(Roop != Rscratch, ""); 2898 assert(Roop != Rmark, ""); 2899 assert(Rbox != Rscratch, ""); 2900 assert(Rbox != Rmark, ""); 2901 2902 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); 2903 %} 2904 2905 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ 2906 MacroAssembler _masm(&cbuf); 2907 Register Rmem = reg_to_register_object($mem$$reg); 2908 Register Rold = reg_to_register_object($old$$reg); 2909 Register Rnew = reg_to_register_object($new$$reg); 2910 2911 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold 2912 __ cmp( Rold, Rnew ); 2913 %} 2914 2915 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ 2916 Register Rmem = reg_to_register_object($mem$$reg); 2917 Register Rold = reg_to_register_object($old$$reg); 2918 Register Rnew = reg_to_register_object($new$$reg); 2919 2920 MacroAssembler _masm(&cbuf); 2921 __ mov(Rnew, O7); 2922 __ casx(Rmem, Rold, O7); 2923 __ cmp( Rold, O7 ); 2924 %} 2925 2926 // raw int cas, used for compareAndSwap 2927 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ 2928 Register Rmem = reg_to_register_object($mem$$reg); 2929 Register Rold = reg_to_register_object($old$$reg); 2930 Register Rnew = reg_to_register_object($new$$reg); 2931 2932 MacroAssembler _masm(&cbuf); 2933 __ mov(Rnew, O7); 2934 __ cas(Rmem, Rold, O7); 2935 __ cmp( Rold, O7 ); 2936 %} 2937 2938 // raw int cas without using tmp register for compareAndExchange 2939 enc_class enc_casi_exch( iRegP mem, iRegL old, iRegL new) %{ 2940 Register Rmem = reg_to_register_object($mem$$reg); 2941 Register Rold = reg_to_register_object($old$$reg); 2942 Register Rnew = reg_to_register_object($new$$reg); 2943 2944 MacroAssembler _masm(&cbuf); 2945 __ cas(Rmem, Rold, Rnew); 2946 %} 2947 2948 // 64-bit cas without using tmp register for compareAndExchange 2949 enc_class enc_casx_exch( iRegP mem, iRegL old, iRegL new) %{ 2950 Register Rmem = reg_to_register_object($mem$$reg); 2951 Register Rold = reg_to_register_object($old$$reg); 2952 Register Rnew = reg_to_register_object($new$$reg); 2953 2954 MacroAssembler _masm(&cbuf); 2955 __ casx(Rmem, Rold, Rnew); 2956 %} 2957 2958 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ 2959 Register Rres = reg_to_register_object($res$$reg); 2960 2961 MacroAssembler _masm(&cbuf); 2962 __ mov(1, Rres); 2963 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); 2964 %} 2965 2966 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ 2967 Register Rres = reg_to_register_object($res$$reg); 2968 2969 MacroAssembler _masm(&cbuf); 2970 __ mov(1, Rres); 2971 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); 2972 %} 2973 2974 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ 2975 MacroAssembler _masm(&cbuf); 2976 Register Rdst = reg_to_register_object($dst$$reg); 2977 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) 2978 : reg_to_DoubleFloatRegister_object($src1$$reg); 2979 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) 2980 : reg_to_DoubleFloatRegister_object($src2$$reg); 2981 2982 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) 2983 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); 2984 %} 2985 2986 enc_class enc_rethrow() %{ 2987 cbuf.set_insts_mark(); 2988 Register temp_reg = G3; 2989 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); 2990 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 2991 MacroAssembler _masm(&cbuf); 2992 #ifdef ASSERT 2993 __ save_frame(0); 2994 AddressLiteral last_rethrow_addrlit(&last_rethrow); 2995 __ sethi(last_rethrow_addrlit, L1); 2996 Address addr(L1, last_rethrow_addrlit.low10()); 2997 __ rdpc(L2); 2998 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to 2999 __ st_ptr(L2, addr); 3000 __ restore(); 3001 #endif 3002 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp 3003 __ delayed()->nop(); 3004 %} 3005 3006 enc_class emit_mem_nop() %{ 3007 // Generates the instruction LDUXA [o6,g0],#0x82,g0 3008 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); 3009 %} 3010 3011 enc_class emit_fadd_nop() %{ 3012 // Generates the instruction FMOVS f31,f31 3013 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); 3014 %} 3015 3016 enc_class emit_br_nop() %{ 3017 // Generates the instruction BPN,PN . 3018 cbuf.insts()->emit_int32((unsigned int) 0x00400000); 3019 %} 3020 3021 enc_class enc_membar_acquire %{ 3022 MacroAssembler _masm(&cbuf); 3023 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); 3024 %} 3025 3026 enc_class enc_membar_release %{ 3027 MacroAssembler _masm(&cbuf); 3028 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); 3029 %} 3030 3031 enc_class enc_membar_volatile %{ 3032 MacroAssembler _masm(&cbuf); 3033 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 3034 %} 3035 3036 %} 3037 3038 //----------FRAME-------------------------------------------------------------- 3039 // Definition of frame structure and management information. 3040 // 3041 // S T A C K L A Y O U T Allocators stack-slot number 3042 // | (to get allocators register number 3043 // G Owned by | | v add VMRegImpl::stack0) 3044 // r CALLER | | 3045 // o | +--------+ pad to even-align allocators stack-slot 3046 // w V | pad0 | numbers; owned by CALLER 3047 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned 3048 // h ^ | in | 5 3049 // | | args | 4 Holes in incoming args owned by SELF 3050 // | | | | 3 3051 // | | +--------+ 3052 // V | | old out| Empty on Intel, window on Sparc 3053 // | old |preserve| Must be even aligned. 3054 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned 3055 // | | in | 3 area for Intel ret address 3056 // Owned by |preserve| Empty on Sparc. 3057 // SELF +--------+ 3058 // | | pad2 | 2 pad to align old SP 3059 // | +--------+ 1 3060 // | | locks | 0 3061 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned 3062 // | | pad1 | 11 pad to align new SP 3063 // | +--------+ 3064 // | | | 10 3065 // | | spills | 9 spills 3066 // V | | 8 (pad0 slot for callee) 3067 // -----------+--------+----> Matcher::_out_arg_limit, unaligned 3068 // ^ | out | 7 3069 // | | args | 6 Holes in outgoing args owned by CALLEE 3070 // Owned by +--------+ 3071 // CALLEE | new out| 6 Empty on Intel, window on Sparc 3072 // | new |preserve| Must be even-aligned. 3073 // | SP-+--------+----> Matcher::_new_SP, even aligned 3074 // | | | 3075 // 3076 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 3077 // known from SELF's arguments and the Java calling convention. 3078 // Region 6-7 is determined per call site. 3079 // Note 2: If the calling convention leaves holes in the incoming argument 3080 // area, those holes are owned by SELF. Holes in the outgoing area 3081 // are owned by the CALLEE. Holes should not be nessecary in the 3082 // incoming area, as the Java calling convention is completely under 3083 // the control of the AD file. Doubles can be sorted and packed to 3084 // avoid holes. Holes in the outgoing arguments may be necessary for 3085 // varargs C calling conventions. 3086 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 3087 // even aligned with pad0 as needed. 3088 // Region 6 is even aligned. Region 6-7 is NOT even aligned; 3089 // region 6-11 is even aligned; it may be padded out more so that 3090 // the region from SP to FP meets the minimum stack alignment. 3091 3092 frame %{ 3093 // What direction does stack grow in (assumed to be same for native & Java) 3094 stack_direction(TOWARDS_LOW); 3095 3096 // These two registers define part of the calling convention 3097 // between compiled code and the interpreter. 3098 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C 3099 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter 3100 3101 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 3102 cisc_spilling_operand_name(indOffset); 3103 3104 // Number of stack slots consumed by a Monitor enter 3105 #ifdef _LP64 3106 sync_stack_slots(2); 3107 #else 3108 sync_stack_slots(1); 3109 #endif 3110 3111 // Compiled code's Frame Pointer 3112 frame_pointer(R_SP); 3113 3114 // Stack alignment requirement 3115 stack_alignment(StackAlignmentInBytes); 3116 // LP64: Alignment size in bytes (128-bit -> 16 bytes) 3117 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) 3118 3119 // Number of stack slots between incoming argument block and the start of 3120 // a new frame. The PROLOG must add this many slots to the stack. The 3121 // EPILOG must remove this many slots. 3122 in_preserve_stack_slots(0); 3123 3124 // Number of outgoing stack slots killed above the out_preserve_stack_slots 3125 // for calls to C. Supports the var-args backing area for register parms. 3126 // ADLC doesn't support parsing expressions, so I folded the math by hand. 3127 #ifdef _LP64 3128 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word 3129 varargs_C_out_slots_killed(12); 3130 #else 3131 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word 3132 varargs_C_out_slots_killed( 7); 3133 #endif 3134 3135 // The after-PROLOG location of the return address. Location of 3136 // return address specifies a type (REG or STACK) and a number 3137 // representing the register number (i.e. - use a register name) or 3138 // stack slot. 3139 return_addr(REG R_I7); // Ret Addr is in register I7 3140 3141 // Body of function which returns an OptoRegs array locating 3142 // arguments either in registers or in stack slots for calling 3143 // java 3144 calling_convention %{ 3145 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); 3146 3147 %} 3148 3149 // Body of function which returns an OptoRegs array locating 3150 // arguments either in registers or in stack slots for calling 3151 // C. 3152 c_calling_convention %{ 3153 // This is obviously always outgoing 3154 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 3155 %} 3156 3157 // Location of native (C/C++) and interpreter return values. This is specified to 3158 // be the same as Java. In the 32-bit VM, long values are actually returned from 3159 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying 3160 // to and from the register pairs is done by the appropriate call and epilog 3161 // opcodes. This simplifies the register allocator. 3162 c_return_value %{ 3163 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3164 #ifdef _LP64 3165 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3166 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3167 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3168 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3169 #else // !_LP64 3170 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3171 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3172 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3173 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3174 #endif 3175 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3176 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3177 %} 3178 3179 // Location of compiled Java return values. Same as C 3180 return_value %{ 3181 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3182 #ifdef _LP64 3183 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3184 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3185 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3186 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3187 #else // !_LP64 3188 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3189 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3190 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3191 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3192 #endif 3193 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3194 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3195 %} 3196 3197 %} 3198 3199 3200 //----------ATTRIBUTES--------------------------------------------------------- 3201 //----------Operand Attributes------------------------------------------------- 3202 op_attrib op_cost(1); // Required cost attribute 3203 3204 //----------Instruction Attributes--------------------------------------------- 3205 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute 3206 ins_attrib ins_size(32); // Required size attribute (in bits) 3207 3208 // avoid_back_to_back attribute is an expression that must return 3209 // one of the following values defined in MachNode: 3210 // AVOID_NONE - instruction can be placed anywhere 3211 // AVOID_BEFORE - instruction cannot be placed after an 3212 // instruction with MachNode::AVOID_AFTER 3213 // AVOID_AFTER - the next instruction cannot be the one 3214 // with MachNode::AVOID_BEFORE 3215 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at 3216 // the same time 3217 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE); 3218 3219 ins_attrib ins_short_branch(0); // Required flag: is this instruction a 3220 // non-matching short branch variant of some 3221 // long branch? 3222 3223 //----------OPERANDS----------------------------------------------------------- 3224 // Operand definitions must precede instruction definitions for correct parsing 3225 // in the ADLC because operands constitute user defined types which are used in 3226 // instruction definitions. 3227 3228 //----------Simple Operands---------------------------------------------------- 3229 // Immediate Operands 3230 // Integer Immediate: 32-bit 3231 operand immI() %{ 3232 match(ConI); 3233 3234 op_cost(0); 3235 // formats are generated automatically for constants and base registers 3236 format %{ %} 3237 interface(CONST_INTER); 3238 %} 3239 3240 // Integer Immediate: 0-bit 3241 operand immI0() %{ 3242 predicate(n->get_int() == 0); 3243 match(ConI); 3244 op_cost(0); 3245 3246 format %{ %} 3247 interface(CONST_INTER); 3248 %} 3249 3250 // Integer Immediate: 5-bit 3251 operand immI5() %{ 3252 predicate(Assembler::is_simm5(n->get_int())); 3253 match(ConI); 3254 op_cost(0); 3255 format %{ %} 3256 interface(CONST_INTER); 3257 %} 3258 3259 // Integer Immediate: 8-bit 3260 operand immI8() %{ 3261 predicate(Assembler::is_simm8(n->get_int())); 3262 match(ConI); 3263 op_cost(0); 3264 format %{ %} 3265 interface(CONST_INTER); 3266 %} 3267 3268 // Integer Immediate: the value 10 3269 operand immI10() %{ 3270 predicate(n->get_int() == 10); 3271 match(ConI); 3272 op_cost(0); 3273 3274 format %{ %} 3275 interface(CONST_INTER); 3276 %} 3277 3278 // Integer Immediate: 11-bit 3279 operand immI11() %{ 3280 predicate(Assembler::is_simm11(n->get_int())); 3281 match(ConI); 3282 op_cost(0); 3283 format %{ %} 3284 interface(CONST_INTER); 3285 %} 3286 3287 // Integer Immediate: 13-bit 3288 operand immI13() %{ 3289 predicate(Assembler::is_simm13(n->get_int())); 3290 match(ConI); 3291 op_cost(0); 3292 3293 format %{ %} 3294 interface(CONST_INTER); 3295 %} 3296 3297 // Integer Immediate: 13-bit minus 7 3298 operand immI13m7() %{ 3299 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); 3300 match(ConI); 3301 op_cost(0); 3302 3303 format %{ %} 3304 interface(CONST_INTER); 3305 %} 3306 3307 // Integer Immediate: 16-bit 3308 operand immI16() %{ 3309 predicate(Assembler::is_simm16(n->get_int())); 3310 match(ConI); 3311 op_cost(0); 3312 format %{ %} 3313 interface(CONST_INTER); 3314 %} 3315 3316 // Integer Immediate: the values 1-31 3317 operand immI_1_31() %{ 3318 predicate(n->get_int() >= 1 && n->get_int() <= 31); 3319 match(ConI); 3320 op_cost(0); 3321 3322 format %{ %} 3323 interface(CONST_INTER); 3324 %} 3325 3326 // Integer Immediate: the values 32-63 3327 operand immI_32_63() %{ 3328 predicate(n->get_int() >= 32 && n->get_int() <= 63); 3329 match(ConI); 3330 op_cost(0); 3331 3332 format %{ %} 3333 interface(CONST_INTER); 3334 %} 3335 3336 // Immediates for special shifts (sign extend) 3337 3338 // Integer Immediate: the value 16 3339 operand immI_16() %{ 3340 predicate(n->get_int() == 16); 3341 match(ConI); 3342 op_cost(0); 3343 3344 format %{ %} 3345 interface(CONST_INTER); 3346 %} 3347 3348 // Integer Immediate: the value 24 3349 operand immI_24() %{ 3350 predicate(n->get_int() == 24); 3351 match(ConI); 3352 op_cost(0); 3353 3354 format %{ %} 3355 interface(CONST_INTER); 3356 %} 3357 // Integer Immediate: the value 255 3358 operand immI_255() %{ 3359 predicate( n->get_int() == 255 ); 3360 match(ConI); 3361 op_cost(0); 3362 3363 format %{ %} 3364 interface(CONST_INTER); 3365 %} 3366 3367 // Integer Immediate: the value 65535 3368 operand immI_65535() %{ 3369 predicate(n->get_int() == 65535); 3370 match(ConI); 3371 op_cost(0); 3372 3373 format %{ %} 3374 interface(CONST_INTER); 3375 %} 3376 3377 // Integer Immediate: the values 0-31 3378 operand immU5() %{ 3379 predicate(n->get_int() >= 0 && n->get_int() <= 31); 3380 match(ConI); 3381 op_cost(0); 3382 3383 format %{ %} 3384 interface(CONST_INTER); 3385 %} 3386 3387 // Integer Immediate: 6-bit 3388 operand immU6() %{ 3389 predicate(n->get_int() >= 0 && n->get_int() <= 63); 3390 match(ConI); 3391 op_cost(0); 3392 format %{ %} 3393 interface(CONST_INTER); 3394 %} 3395 3396 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13) 3397 operand immU12() %{ 3398 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3399 match(ConI); 3400 op_cost(0); 3401 3402 format %{ %} 3403 interface(CONST_INTER); 3404 %} 3405 3406 // Integer Immediate non-negative 3407 operand immU31() 3408 %{ 3409 predicate(n->get_int() >= 0); 3410 match(ConI); 3411 3412 op_cost(0); 3413 format %{ %} 3414 interface(CONST_INTER); 3415 %} 3416 3417 // Long Immediate: the value FF 3418 operand immL_FF() %{ 3419 predicate( n->get_long() == 0xFFL ); 3420 match(ConL); 3421 op_cost(0); 3422 3423 format %{ %} 3424 interface(CONST_INTER); 3425 %} 3426 3427 // Long Immediate: the value FFFF 3428 operand immL_FFFF() %{ 3429 predicate( n->get_long() == 0xFFFFL ); 3430 match(ConL); 3431 op_cost(0); 3432 3433 format %{ %} 3434 interface(CONST_INTER); 3435 %} 3436 3437 // Pointer Immediate: 32 or 64-bit 3438 operand immP() %{ 3439 match(ConP); 3440 3441 op_cost(5); 3442 // formats are generated automatically for constants and base registers 3443 format %{ %} 3444 interface(CONST_INTER); 3445 %} 3446 3447 #ifdef _LP64 3448 // Pointer Immediate: 64-bit 3449 operand immP_set() %{ 3450 predicate(!VM_Version::is_niagara_plus()); 3451 match(ConP); 3452 3453 op_cost(5); 3454 // formats are generated automatically for constants and base registers 3455 format %{ %} 3456 interface(CONST_INTER); 3457 %} 3458 3459 // Pointer Immediate: 64-bit 3460 // From Niagara2 processors on a load should be better than materializing. 3461 operand immP_load() %{ 3462 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); 3463 match(ConP); 3464 3465 op_cost(5); 3466 // formats are generated automatically for constants and base registers 3467 format %{ %} 3468 interface(CONST_INTER); 3469 %} 3470 3471 // Pointer Immediate: 64-bit 3472 operand immP_no_oop_cheap() %{ 3473 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); 3474 match(ConP); 3475 3476 op_cost(5); 3477 // formats are generated automatically for constants and base registers 3478 format %{ %} 3479 interface(CONST_INTER); 3480 %} 3481 #endif 3482 3483 operand immP13() %{ 3484 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); 3485 match(ConP); 3486 op_cost(0); 3487 3488 format %{ %} 3489 interface(CONST_INTER); 3490 %} 3491 3492 operand immP0() %{ 3493 predicate(n->get_ptr() == 0); 3494 match(ConP); 3495 op_cost(0); 3496 3497 format %{ %} 3498 interface(CONST_INTER); 3499 %} 3500 3501 operand immP_poll() %{ 3502 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); 3503 match(ConP); 3504 3505 // formats are generated automatically for constants and base registers 3506 format %{ %} 3507 interface(CONST_INTER); 3508 %} 3509 3510 // Pointer Immediate 3511 operand immN() 3512 %{ 3513 match(ConN); 3514 3515 op_cost(10); 3516 format %{ %} 3517 interface(CONST_INTER); 3518 %} 3519 3520 operand immNKlass() 3521 %{ 3522 match(ConNKlass); 3523 3524 op_cost(10); 3525 format %{ %} 3526 interface(CONST_INTER); 3527 %} 3528 3529 // NULL Pointer Immediate 3530 operand immN0() 3531 %{ 3532 predicate(n->get_narrowcon() == 0); 3533 match(ConN); 3534 3535 op_cost(0); 3536 format %{ %} 3537 interface(CONST_INTER); 3538 %} 3539 3540 operand immL() %{ 3541 match(ConL); 3542 op_cost(40); 3543 // formats are generated automatically for constants and base registers 3544 format %{ %} 3545 interface(CONST_INTER); 3546 %} 3547 3548 operand immL0() %{ 3549 predicate(n->get_long() == 0L); 3550 match(ConL); 3551 op_cost(0); 3552 // formats are generated automatically for constants and base registers 3553 format %{ %} 3554 interface(CONST_INTER); 3555 %} 3556 3557 // Integer Immediate: 5-bit 3558 operand immL5() %{ 3559 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); 3560 match(ConL); 3561 op_cost(0); 3562 format %{ %} 3563 interface(CONST_INTER); 3564 %} 3565 3566 // Long Immediate: 13-bit 3567 operand immL13() %{ 3568 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); 3569 match(ConL); 3570 op_cost(0); 3571 3572 format %{ %} 3573 interface(CONST_INTER); 3574 %} 3575 3576 // Long Immediate: 13-bit minus 7 3577 operand immL13m7() %{ 3578 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); 3579 match(ConL); 3580 op_cost(0); 3581 3582 format %{ %} 3583 interface(CONST_INTER); 3584 %} 3585 3586 // Long Immediate: low 32-bit mask 3587 operand immL_32bits() %{ 3588 predicate(n->get_long() == 0xFFFFFFFFL); 3589 match(ConL); 3590 op_cost(0); 3591 3592 format %{ %} 3593 interface(CONST_INTER); 3594 %} 3595 3596 // Long Immediate: cheap (materialize in <= 3 instructions) 3597 operand immL_cheap() %{ 3598 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); 3599 match(ConL); 3600 op_cost(0); 3601 3602 format %{ %} 3603 interface(CONST_INTER); 3604 %} 3605 3606 // Long Immediate: expensive (materialize in > 3 instructions) 3607 operand immL_expensive() %{ 3608 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); 3609 match(ConL); 3610 op_cost(0); 3611 3612 format %{ %} 3613 interface(CONST_INTER); 3614 %} 3615 3616 // Double Immediate 3617 operand immD() %{ 3618 match(ConD); 3619 3620 op_cost(40); 3621 format %{ %} 3622 interface(CONST_INTER); 3623 %} 3624 3625 // Double Immediate: +0.0d 3626 operand immD0() %{ 3627 predicate(jlong_cast(n->getd()) == 0); 3628 match(ConD); 3629 3630 op_cost(0); 3631 format %{ %} 3632 interface(CONST_INTER); 3633 %} 3634 3635 // Float Immediate 3636 operand immF() %{ 3637 match(ConF); 3638 3639 op_cost(20); 3640 format %{ %} 3641 interface(CONST_INTER); 3642 %} 3643 3644 // Float Immediate: +0.0f 3645 operand immF0() %{ 3646 predicate(jint_cast(n->getf()) == 0); 3647 match(ConF); 3648 3649 op_cost(0); 3650 format %{ %} 3651 interface(CONST_INTER); 3652 %} 3653 3654 // Integer Register Operands 3655 // Integer Register 3656 operand iRegI() %{ 3657 constraint(ALLOC_IN_RC(int_reg)); 3658 match(RegI); 3659 3660 match(notemp_iRegI); 3661 match(g1RegI); 3662 match(o0RegI); 3663 match(iRegIsafe); 3664 3665 format %{ %} 3666 interface(REG_INTER); 3667 %} 3668 3669 operand notemp_iRegI() %{ 3670 constraint(ALLOC_IN_RC(notemp_int_reg)); 3671 match(RegI); 3672 3673 match(o0RegI); 3674 3675 format %{ %} 3676 interface(REG_INTER); 3677 %} 3678 3679 operand o0RegI() %{ 3680 constraint(ALLOC_IN_RC(o0_regI)); 3681 match(iRegI); 3682 3683 format %{ %} 3684 interface(REG_INTER); 3685 %} 3686 3687 // Pointer Register 3688 operand iRegP() %{ 3689 constraint(ALLOC_IN_RC(ptr_reg)); 3690 match(RegP); 3691 3692 match(lock_ptr_RegP); 3693 match(g1RegP); 3694 match(g2RegP); 3695 match(g3RegP); 3696 match(g4RegP); 3697 match(i0RegP); 3698 match(o0RegP); 3699 match(o1RegP); 3700 match(l7RegP); 3701 3702 format %{ %} 3703 interface(REG_INTER); 3704 %} 3705 3706 operand sp_ptr_RegP() %{ 3707 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3708 match(RegP); 3709 match(iRegP); 3710 3711 format %{ %} 3712 interface(REG_INTER); 3713 %} 3714 3715 operand lock_ptr_RegP() %{ 3716 constraint(ALLOC_IN_RC(lock_ptr_reg)); 3717 match(RegP); 3718 match(i0RegP); 3719 match(o0RegP); 3720 match(o1RegP); 3721 match(l7RegP); 3722 3723 format %{ %} 3724 interface(REG_INTER); 3725 %} 3726 3727 operand g1RegP() %{ 3728 constraint(ALLOC_IN_RC(g1_regP)); 3729 match(iRegP); 3730 3731 format %{ %} 3732 interface(REG_INTER); 3733 %} 3734 3735 operand g2RegP() %{ 3736 constraint(ALLOC_IN_RC(g2_regP)); 3737 match(iRegP); 3738 3739 format %{ %} 3740 interface(REG_INTER); 3741 %} 3742 3743 operand g3RegP() %{ 3744 constraint(ALLOC_IN_RC(g3_regP)); 3745 match(iRegP); 3746 3747 format %{ %} 3748 interface(REG_INTER); 3749 %} 3750 3751 operand g1RegI() %{ 3752 constraint(ALLOC_IN_RC(g1_regI)); 3753 match(iRegI); 3754 3755 format %{ %} 3756 interface(REG_INTER); 3757 %} 3758 3759 operand g3RegI() %{ 3760 constraint(ALLOC_IN_RC(g3_regI)); 3761 match(iRegI); 3762 3763 format %{ %} 3764 interface(REG_INTER); 3765 %} 3766 3767 operand g4RegI() %{ 3768 constraint(ALLOC_IN_RC(g4_regI)); 3769 match(iRegI); 3770 3771 format %{ %} 3772 interface(REG_INTER); 3773 %} 3774 3775 operand g4RegP() %{ 3776 constraint(ALLOC_IN_RC(g4_regP)); 3777 match(iRegP); 3778 3779 format %{ %} 3780 interface(REG_INTER); 3781 %} 3782 3783 operand i0RegP() %{ 3784 constraint(ALLOC_IN_RC(i0_regP)); 3785 match(iRegP); 3786 3787 format %{ %} 3788 interface(REG_INTER); 3789 %} 3790 3791 operand o0RegP() %{ 3792 constraint(ALLOC_IN_RC(o0_regP)); 3793 match(iRegP); 3794 3795 format %{ %} 3796 interface(REG_INTER); 3797 %} 3798 3799 operand o1RegP() %{ 3800 constraint(ALLOC_IN_RC(o1_regP)); 3801 match(iRegP); 3802 3803 format %{ %} 3804 interface(REG_INTER); 3805 %} 3806 3807 operand o2RegP() %{ 3808 constraint(ALLOC_IN_RC(o2_regP)); 3809 match(iRegP); 3810 3811 format %{ %} 3812 interface(REG_INTER); 3813 %} 3814 3815 operand o7RegP() %{ 3816 constraint(ALLOC_IN_RC(o7_regP)); 3817 match(iRegP); 3818 3819 format %{ %} 3820 interface(REG_INTER); 3821 %} 3822 3823 operand l7RegP() %{ 3824 constraint(ALLOC_IN_RC(l7_regP)); 3825 match(iRegP); 3826 3827 format %{ %} 3828 interface(REG_INTER); 3829 %} 3830 3831 operand o7RegI() %{ 3832 constraint(ALLOC_IN_RC(o7_regI)); 3833 match(iRegI); 3834 3835 format %{ %} 3836 interface(REG_INTER); 3837 %} 3838 3839 operand iRegN() %{ 3840 constraint(ALLOC_IN_RC(int_reg)); 3841 match(RegN); 3842 3843 format %{ %} 3844 interface(REG_INTER); 3845 %} 3846 3847 // Long Register 3848 operand iRegL() %{ 3849 constraint(ALLOC_IN_RC(long_reg)); 3850 match(RegL); 3851 3852 format %{ %} 3853 interface(REG_INTER); 3854 %} 3855 3856 operand o2RegL() %{ 3857 constraint(ALLOC_IN_RC(o2_regL)); 3858 match(iRegL); 3859 3860 format %{ %} 3861 interface(REG_INTER); 3862 %} 3863 3864 operand o7RegL() %{ 3865 constraint(ALLOC_IN_RC(o7_regL)); 3866 match(iRegL); 3867 3868 format %{ %} 3869 interface(REG_INTER); 3870 %} 3871 3872 operand g1RegL() %{ 3873 constraint(ALLOC_IN_RC(g1_regL)); 3874 match(iRegL); 3875 3876 format %{ %} 3877 interface(REG_INTER); 3878 %} 3879 3880 operand g3RegL() %{ 3881 constraint(ALLOC_IN_RC(g3_regL)); 3882 match(iRegL); 3883 3884 format %{ %} 3885 interface(REG_INTER); 3886 %} 3887 3888 // Int Register safe 3889 // This is 64bit safe 3890 operand iRegIsafe() %{ 3891 constraint(ALLOC_IN_RC(long_reg)); 3892 3893 match(iRegI); 3894 3895 format %{ %} 3896 interface(REG_INTER); 3897 %} 3898 3899 // Condition Code Flag Register 3900 operand flagsReg() %{ 3901 constraint(ALLOC_IN_RC(int_flags)); 3902 match(RegFlags); 3903 3904 format %{ "ccr" %} // both ICC and XCC 3905 interface(REG_INTER); 3906 %} 3907 3908 // Condition Code Register, unsigned comparisons. 3909 operand flagsRegU() %{ 3910 constraint(ALLOC_IN_RC(int_flags)); 3911 match(RegFlags); 3912 3913 format %{ "icc_U" %} 3914 interface(REG_INTER); 3915 %} 3916 3917 // Condition Code Register, pointer comparisons. 3918 operand flagsRegP() %{ 3919 constraint(ALLOC_IN_RC(int_flags)); 3920 match(RegFlags); 3921 3922 #ifdef _LP64 3923 format %{ "xcc_P" %} 3924 #else 3925 format %{ "icc_P" %} 3926 #endif 3927 interface(REG_INTER); 3928 %} 3929 3930 // Condition Code Register, long comparisons. 3931 operand flagsRegL() %{ 3932 constraint(ALLOC_IN_RC(int_flags)); 3933 match(RegFlags); 3934 3935 format %{ "xcc_L" %} 3936 interface(REG_INTER); 3937 %} 3938 3939 // Condition Code Register, floating comparisons, unordered same as "less". 3940 operand flagsRegF() %{ 3941 constraint(ALLOC_IN_RC(float_flags)); 3942 match(RegFlags); 3943 match(flagsRegF0); 3944 3945 format %{ %} 3946 interface(REG_INTER); 3947 %} 3948 3949 operand flagsRegF0() %{ 3950 constraint(ALLOC_IN_RC(float_flag0)); 3951 match(RegFlags); 3952 3953 format %{ %} 3954 interface(REG_INTER); 3955 %} 3956 3957 3958 // Condition Code Flag Register used by long compare 3959 operand flagsReg_long_LTGE() %{ 3960 constraint(ALLOC_IN_RC(int_flags)); 3961 match(RegFlags); 3962 format %{ "icc_LTGE" %} 3963 interface(REG_INTER); 3964 %} 3965 operand flagsReg_long_EQNE() %{ 3966 constraint(ALLOC_IN_RC(int_flags)); 3967 match(RegFlags); 3968 format %{ "icc_EQNE" %} 3969 interface(REG_INTER); 3970 %} 3971 operand flagsReg_long_LEGT() %{ 3972 constraint(ALLOC_IN_RC(int_flags)); 3973 match(RegFlags); 3974 format %{ "icc_LEGT" %} 3975 interface(REG_INTER); 3976 %} 3977 3978 3979 operand regD() %{ 3980 constraint(ALLOC_IN_RC(dflt_reg)); 3981 match(RegD); 3982 3983 match(regD_low); 3984 3985 format %{ %} 3986 interface(REG_INTER); 3987 %} 3988 3989 operand regF() %{ 3990 constraint(ALLOC_IN_RC(sflt_reg)); 3991 match(RegF); 3992 3993 format %{ %} 3994 interface(REG_INTER); 3995 %} 3996 3997 operand regD_low() %{ 3998 constraint(ALLOC_IN_RC(dflt_low_reg)); 3999 match(regD); 4000 4001 format %{ %} 4002 interface(REG_INTER); 4003 %} 4004 4005 // Special Registers 4006 4007 // Method Register 4008 operand inline_cache_regP(iRegP reg) %{ 4009 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 4010 match(reg); 4011 format %{ %} 4012 interface(REG_INTER); 4013 %} 4014 4015 operand interpreter_method_oop_regP(iRegP reg) %{ 4016 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 4017 match(reg); 4018 format %{ %} 4019 interface(REG_INTER); 4020 %} 4021 4022 4023 //----------Complex Operands--------------------------------------------------- 4024 // Indirect Memory Reference 4025 operand indirect(sp_ptr_RegP reg) %{ 4026 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4027 match(reg); 4028 4029 op_cost(100); 4030 format %{ "[$reg]" %} 4031 interface(MEMORY_INTER) %{ 4032 base($reg); 4033 index(0x0); 4034 scale(0x0); 4035 disp(0x0); 4036 %} 4037 %} 4038 4039 // Indirect with simm13 Offset 4040 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ 4041 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4042 match(AddP reg offset); 4043 4044 op_cost(100); 4045 format %{ "[$reg + $offset]" %} 4046 interface(MEMORY_INTER) %{ 4047 base($reg); 4048 index(0x0); 4049 scale(0x0); 4050 disp($offset); 4051 %} 4052 %} 4053 4054 // Indirect with simm13 Offset minus 7 4055 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ 4056 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4057 match(AddP reg offset); 4058 4059 op_cost(100); 4060 format %{ "[$reg + $offset]" %} 4061 interface(MEMORY_INTER) %{ 4062 base($reg); 4063 index(0x0); 4064 scale(0x0); 4065 disp($offset); 4066 %} 4067 %} 4068 4069 // Note: Intel has a swapped version also, like this: 4070 //operand indOffsetX(iRegI reg, immP offset) %{ 4071 // constraint(ALLOC_IN_RC(int_reg)); 4072 // match(AddP offset reg); 4073 // 4074 // op_cost(100); 4075 // format %{ "[$reg + $offset]" %} 4076 // interface(MEMORY_INTER) %{ 4077 // base($reg); 4078 // index(0x0); 4079 // scale(0x0); 4080 // disp($offset); 4081 // %} 4082 //%} 4083 //// However, it doesn't make sense for SPARC, since 4084 // we have no particularly good way to embed oops in 4085 // single instructions. 4086 4087 // Indirect with Register Index 4088 operand indIndex(iRegP addr, iRegX index) %{ 4089 constraint(ALLOC_IN_RC(ptr_reg)); 4090 match(AddP addr index); 4091 4092 op_cost(100); 4093 format %{ "[$addr + $index]" %} 4094 interface(MEMORY_INTER) %{ 4095 base($addr); 4096 index($index); 4097 scale(0x0); 4098 disp(0x0); 4099 %} 4100 %} 4101 4102 //----------Special Memory Operands-------------------------------------------- 4103 // Stack Slot Operand - This operand is used for loading and storing temporary 4104 // values on the stack where a match requires a value to 4105 // flow through memory. 4106 operand stackSlotI(sRegI reg) %{ 4107 constraint(ALLOC_IN_RC(stack_slots)); 4108 op_cost(100); 4109 //match(RegI); 4110 format %{ "[$reg]" %} 4111 interface(MEMORY_INTER) %{ 4112 base(0xE); // R_SP 4113 index(0x0); 4114 scale(0x0); 4115 disp($reg); // Stack Offset 4116 %} 4117 %} 4118 4119 operand stackSlotP(sRegP reg) %{ 4120 constraint(ALLOC_IN_RC(stack_slots)); 4121 op_cost(100); 4122 //match(RegP); 4123 format %{ "[$reg]" %} 4124 interface(MEMORY_INTER) %{ 4125 base(0xE); // R_SP 4126 index(0x0); 4127 scale(0x0); 4128 disp($reg); // Stack Offset 4129 %} 4130 %} 4131 4132 operand stackSlotF(sRegF reg) %{ 4133 constraint(ALLOC_IN_RC(stack_slots)); 4134 op_cost(100); 4135 //match(RegF); 4136 format %{ "[$reg]" %} 4137 interface(MEMORY_INTER) %{ 4138 base(0xE); // R_SP 4139 index(0x0); 4140 scale(0x0); 4141 disp($reg); // Stack Offset 4142 %} 4143 %} 4144 operand stackSlotD(sRegD reg) %{ 4145 constraint(ALLOC_IN_RC(stack_slots)); 4146 op_cost(100); 4147 //match(RegD); 4148 format %{ "[$reg]" %} 4149 interface(MEMORY_INTER) %{ 4150 base(0xE); // R_SP 4151 index(0x0); 4152 scale(0x0); 4153 disp($reg); // Stack Offset 4154 %} 4155 %} 4156 operand stackSlotL(sRegL reg) %{ 4157 constraint(ALLOC_IN_RC(stack_slots)); 4158 op_cost(100); 4159 //match(RegL); 4160 format %{ "[$reg]" %} 4161 interface(MEMORY_INTER) %{ 4162 base(0xE); // R_SP 4163 index(0x0); 4164 scale(0x0); 4165 disp($reg); // Stack Offset 4166 %} 4167 %} 4168 4169 // Operands for expressing Control Flow 4170 // NOTE: Label is a predefined operand which should not be redefined in 4171 // the AD file. It is generically handled within the ADLC. 4172 4173 //----------Conditional Branch Operands---------------------------------------- 4174 // Comparison Op - This is the operation of the comparison, and is limited to 4175 // the following set of codes: 4176 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 4177 // 4178 // Other attributes of the comparison, such as unsignedness, are specified 4179 // by the comparison instruction that sets a condition code flags register. 4180 // That result is represented by a flags operand whose subtype is appropriate 4181 // to the unsignedness (etc.) of the comparison. 4182 // 4183 // Later, the instruction which matches both the Comparison Op (a Bool) and 4184 // the flags (produced by the Cmp) specifies the coding of the comparison op 4185 // by matching a specific subtype of Bool operand below, such as cmpOpU. 4186 4187 operand cmpOp() %{ 4188 match(Bool); 4189 4190 format %{ "" %} 4191 interface(COND_INTER) %{ 4192 equal(0x1); 4193 not_equal(0x9); 4194 less(0x3); 4195 greater_equal(0xB); 4196 less_equal(0x2); 4197 greater(0xA); 4198 overflow(0x7); 4199 no_overflow(0xF); 4200 %} 4201 %} 4202 4203 // Comparison Op, unsigned 4204 operand cmpOpU() %{ 4205 match(Bool); 4206 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4207 n->as_Bool()->_test._test != BoolTest::no_overflow); 4208 4209 format %{ "u" %} 4210 interface(COND_INTER) %{ 4211 equal(0x1); 4212 not_equal(0x9); 4213 less(0x5); 4214 greater_equal(0xD); 4215 less_equal(0x4); 4216 greater(0xC); 4217 overflow(0x7); 4218 no_overflow(0xF); 4219 %} 4220 %} 4221 4222 // Comparison Op, pointer (same as unsigned) 4223 operand cmpOpP() %{ 4224 match(Bool); 4225 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4226 n->as_Bool()->_test._test != BoolTest::no_overflow); 4227 4228 format %{ "p" %} 4229 interface(COND_INTER) %{ 4230 equal(0x1); 4231 not_equal(0x9); 4232 less(0x5); 4233 greater_equal(0xD); 4234 less_equal(0x4); 4235 greater(0xC); 4236 overflow(0x7); 4237 no_overflow(0xF); 4238 %} 4239 %} 4240 4241 // Comparison Op, branch-register encoding 4242 operand cmpOp_reg() %{ 4243 match(Bool); 4244 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4245 n->as_Bool()->_test._test != BoolTest::no_overflow); 4246 4247 format %{ "" %} 4248 interface(COND_INTER) %{ 4249 equal (0x1); 4250 not_equal (0x5); 4251 less (0x3); 4252 greater_equal(0x7); 4253 less_equal (0x2); 4254 greater (0x6); 4255 overflow(0x7); // not supported 4256 no_overflow(0xF); // not supported 4257 %} 4258 %} 4259 4260 // Comparison Code, floating, unordered same as less 4261 operand cmpOpF() %{ 4262 match(Bool); 4263 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4264 n->as_Bool()->_test._test != BoolTest::no_overflow); 4265 4266 format %{ "fl" %} 4267 interface(COND_INTER) %{ 4268 equal(0x9); 4269 not_equal(0x1); 4270 less(0x3); 4271 greater_equal(0xB); 4272 less_equal(0xE); 4273 greater(0x6); 4274 4275 overflow(0x7); // not supported 4276 no_overflow(0xF); // not supported 4277 %} 4278 %} 4279 4280 // Used by long compare 4281 operand cmpOp_commute() %{ 4282 match(Bool); 4283 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4284 n->as_Bool()->_test._test != BoolTest::no_overflow); 4285 4286 format %{ "" %} 4287 interface(COND_INTER) %{ 4288 equal(0x1); 4289 not_equal(0x9); 4290 less(0xA); 4291 greater_equal(0x2); 4292 less_equal(0xB); 4293 greater(0x3); 4294 overflow(0x7); 4295 no_overflow(0xF); 4296 %} 4297 %} 4298 4299 //----------OPERAND CLASSES---------------------------------------------------- 4300 // Operand Classes are groups of operands that are used to simplify 4301 // instruction definitions by not requiring the AD writer to specify separate 4302 // instructions for every form of operand when the instruction accepts 4303 // multiple operand types with the same basic encoding and format. The classic 4304 // case of this is memory operands. 4305 opclass memory( indirect, indOffset13, indIndex ); 4306 opclass indIndexMemory( indIndex ); 4307 4308 //----------PIPELINE----------------------------------------------------------- 4309 pipeline %{ 4310 4311 //----------ATTRIBUTES--------------------------------------------------------- 4312 attributes %{ 4313 fixed_size_instructions; // Fixed size instructions 4314 branch_has_delay_slot; // Branch has delay slot following 4315 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle 4316 instruction_unit_size = 4; // An instruction is 4 bytes long 4317 instruction_fetch_unit_size = 16; // The processor fetches one line 4318 instruction_fetch_units = 1; // of 16 bytes 4319 4320 // List of nop instructions 4321 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); 4322 %} 4323 4324 //----------RESOURCES---------------------------------------------------------- 4325 // Resources are the functional units available to the machine 4326 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); 4327 4328 //----------PIPELINE DESCRIPTION----------------------------------------------- 4329 // Pipeline Description specifies the stages in the machine's pipeline 4330 4331 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); 4332 4333 //----------PIPELINE CLASSES--------------------------------------------------- 4334 // Pipeline Classes describe the stages in which input and output are 4335 // referenced by the hardware pipeline. 4336 4337 // Integer ALU reg-reg operation 4338 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4339 single_instruction; 4340 dst : E(write); 4341 src1 : R(read); 4342 src2 : R(read); 4343 IALU : R; 4344 %} 4345 4346 // Integer ALU reg-reg long operation 4347 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 4348 instruction_count(2); 4349 dst : E(write); 4350 src1 : R(read); 4351 src2 : R(read); 4352 IALU : R; 4353 IALU : R; 4354 %} 4355 4356 // Integer ALU reg-reg long dependent operation 4357 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 4358 instruction_count(1); multiple_bundles; 4359 dst : E(write); 4360 src1 : R(read); 4361 src2 : R(read); 4362 cr : E(write); 4363 IALU : R(2); 4364 %} 4365 4366 // Integer ALU reg-imm operaion 4367 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4368 single_instruction; 4369 dst : E(write); 4370 src1 : R(read); 4371 IALU : R; 4372 %} 4373 4374 // Integer ALU reg-reg operation with condition code 4375 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 4376 single_instruction; 4377 dst : E(write); 4378 cr : E(write); 4379 src1 : R(read); 4380 src2 : R(read); 4381 IALU : R; 4382 %} 4383 4384 // Integer ALU reg-imm operation with condition code 4385 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ 4386 single_instruction; 4387 dst : E(write); 4388 cr : E(write); 4389 src1 : R(read); 4390 IALU : R; 4391 %} 4392 4393 // Integer ALU zero-reg operation 4394 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 4395 single_instruction; 4396 dst : E(write); 4397 src2 : R(read); 4398 IALU : R; 4399 %} 4400 4401 // Integer ALU zero-reg operation with condition code only 4402 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ 4403 single_instruction; 4404 cr : E(write); 4405 src : R(read); 4406 IALU : R; 4407 %} 4408 4409 // Integer ALU reg-reg operation with condition code only 4410 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4411 single_instruction; 4412 cr : E(write); 4413 src1 : R(read); 4414 src2 : R(read); 4415 IALU : R; 4416 %} 4417 4418 // Integer ALU reg-imm operation with condition code only 4419 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4420 single_instruction; 4421 cr : E(write); 4422 src1 : R(read); 4423 IALU : R; 4424 %} 4425 4426 // Integer ALU reg-reg-zero operation with condition code only 4427 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ 4428 single_instruction; 4429 cr : E(write); 4430 src1 : R(read); 4431 src2 : R(read); 4432 IALU : R; 4433 %} 4434 4435 // Integer ALU reg-imm-zero operation with condition code only 4436 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ 4437 single_instruction; 4438 cr : E(write); 4439 src1 : R(read); 4440 IALU : R; 4441 %} 4442 4443 // Integer ALU reg-reg operation with condition code, src1 modified 4444 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4445 single_instruction; 4446 cr : E(write); 4447 src1 : E(write); 4448 src1 : R(read); 4449 src2 : R(read); 4450 IALU : R; 4451 %} 4452 4453 // Integer ALU reg-imm operation with condition code, src1 modified 4454 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4455 single_instruction; 4456 cr : E(write); 4457 src1 : E(write); 4458 src1 : R(read); 4459 IALU : R; 4460 %} 4461 4462 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ 4463 multiple_bundles; 4464 dst : E(write)+4; 4465 cr : E(write); 4466 src1 : R(read); 4467 src2 : R(read); 4468 IALU : R(3); 4469 BR : R(2); 4470 %} 4471 4472 // Integer ALU operation 4473 pipe_class ialu_none(iRegI dst) %{ 4474 single_instruction; 4475 dst : E(write); 4476 IALU : R; 4477 %} 4478 4479 // Integer ALU reg operation 4480 pipe_class ialu_reg(iRegI dst, iRegI src) %{ 4481 single_instruction; may_have_no_code; 4482 dst : E(write); 4483 src : R(read); 4484 IALU : R; 4485 %} 4486 4487 // Integer ALU reg conditional operation 4488 // This instruction has a 1 cycle stall, and cannot execute 4489 // in the same cycle as the instruction setting the condition 4490 // code. We kludge this by pretending to read the condition code 4491 // 1 cycle earlier, and by marking the functional units as busy 4492 // for 2 cycles with the result available 1 cycle later than 4493 // is really the case. 4494 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ 4495 single_instruction; 4496 op2_out : C(write); 4497 op1 : R(read); 4498 cr : R(read); // This is really E, with a 1 cycle stall 4499 BR : R(2); 4500 MS : R(2); 4501 %} 4502 4503 #ifdef _LP64 4504 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ 4505 instruction_count(1); multiple_bundles; 4506 dst : C(write)+1; 4507 src : R(read)+1; 4508 IALU : R(1); 4509 BR : E(2); 4510 MS : E(2); 4511 %} 4512 #endif 4513 4514 // Integer ALU reg operation 4515 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ 4516 single_instruction; may_have_no_code; 4517 dst : E(write); 4518 src : R(read); 4519 IALU : R; 4520 %} 4521 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ 4522 single_instruction; may_have_no_code; 4523 dst : E(write); 4524 src : R(read); 4525 IALU : R; 4526 %} 4527 4528 // Two integer ALU reg operations 4529 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ 4530 instruction_count(2); 4531 dst : E(write); 4532 src : R(read); 4533 A0 : R; 4534 A1 : R; 4535 %} 4536 4537 // Two integer ALU reg operations 4538 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ 4539 instruction_count(2); may_have_no_code; 4540 dst : E(write); 4541 src : R(read); 4542 A0 : R; 4543 A1 : R; 4544 %} 4545 4546 // Integer ALU imm operation 4547 pipe_class ialu_imm(iRegI dst, immI13 src) %{ 4548 single_instruction; 4549 dst : E(write); 4550 IALU : R; 4551 %} 4552 4553 // Integer ALU reg-reg with carry operation 4554 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ 4555 single_instruction; 4556 dst : E(write); 4557 src1 : R(read); 4558 src2 : R(read); 4559 IALU : R; 4560 %} 4561 4562 // Integer ALU cc operation 4563 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ 4564 single_instruction; 4565 dst : E(write); 4566 cc : R(read); 4567 IALU : R; 4568 %} 4569 4570 // Integer ALU cc / second IALU operation 4571 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ 4572 instruction_count(1); multiple_bundles; 4573 dst : E(write)+1; 4574 src : R(read); 4575 IALU : R; 4576 %} 4577 4578 // Integer ALU cc / second IALU operation 4579 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ 4580 instruction_count(1); multiple_bundles; 4581 dst : E(write)+1; 4582 p : R(read); 4583 q : R(read); 4584 IALU : R; 4585 %} 4586 4587 // Integer ALU hi-lo-reg operation 4588 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ 4589 instruction_count(1); multiple_bundles; 4590 dst : E(write)+1; 4591 IALU : R(2); 4592 %} 4593 4594 // Float ALU hi-lo-reg operation (with temp) 4595 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ 4596 instruction_count(1); multiple_bundles; 4597 dst : E(write)+1; 4598 IALU : R(2); 4599 %} 4600 4601 // Long Constant 4602 pipe_class loadConL( iRegL dst, immL src ) %{ 4603 instruction_count(2); multiple_bundles; 4604 dst : E(write)+1; 4605 IALU : R(2); 4606 IALU : R(2); 4607 %} 4608 4609 // Pointer Constant 4610 pipe_class loadConP( iRegP dst, immP src ) %{ 4611 instruction_count(0); multiple_bundles; 4612 fixed_latency(6); 4613 %} 4614 4615 // Polling Address 4616 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ 4617 #ifdef _LP64 4618 instruction_count(0); multiple_bundles; 4619 fixed_latency(6); 4620 #else 4621 dst : E(write); 4622 IALU : R; 4623 #endif 4624 %} 4625 4626 // Long Constant small 4627 pipe_class loadConLlo( iRegL dst, immL src ) %{ 4628 instruction_count(2); 4629 dst : E(write); 4630 IALU : R; 4631 IALU : R; 4632 %} 4633 4634 // [PHH] This is wrong for 64-bit. See LdImmF/D. 4635 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ 4636 instruction_count(1); multiple_bundles; 4637 src : R(read); 4638 dst : M(write)+1; 4639 IALU : R; 4640 MS : E; 4641 %} 4642 4643 // Integer ALU nop operation 4644 pipe_class ialu_nop() %{ 4645 single_instruction; 4646 IALU : R; 4647 %} 4648 4649 // Integer ALU nop operation 4650 pipe_class ialu_nop_A0() %{ 4651 single_instruction; 4652 A0 : R; 4653 %} 4654 4655 // Integer ALU nop operation 4656 pipe_class ialu_nop_A1() %{ 4657 single_instruction; 4658 A1 : R; 4659 %} 4660 4661 // Integer Multiply reg-reg operation 4662 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4663 single_instruction; 4664 dst : E(write); 4665 src1 : R(read); 4666 src2 : R(read); 4667 MS : R(5); 4668 %} 4669 4670 // Integer Multiply reg-imm operation 4671 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4672 single_instruction; 4673 dst : E(write); 4674 src1 : R(read); 4675 MS : R(5); 4676 %} 4677 4678 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4679 single_instruction; 4680 dst : E(write)+4; 4681 src1 : R(read); 4682 src2 : R(read); 4683 MS : R(6); 4684 %} 4685 4686 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4687 single_instruction; 4688 dst : E(write)+4; 4689 src1 : R(read); 4690 MS : R(6); 4691 %} 4692 4693 // Integer Divide reg-reg 4694 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ 4695 instruction_count(1); multiple_bundles; 4696 dst : E(write); 4697 temp : E(write); 4698 src1 : R(read); 4699 src2 : R(read); 4700 temp : R(read); 4701 MS : R(38); 4702 %} 4703 4704 // Integer Divide reg-imm 4705 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ 4706 instruction_count(1); multiple_bundles; 4707 dst : E(write); 4708 temp : E(write); 4709 src1 : R(read); 4710 temp : R(read); 4711 MS : R(38); 4712 %} 4713 4714 // Long Divide 4715 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4716 dst : E(write)+71; 4717 src1 : R(read); 4718 src2 : R(read)+1; 4719 MS : R(70); 4720 %} 4721 4722 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4723 dst : E(write)+71; 4724 src1 : R(read); 4725 MS : R(70); 4726 %} 4727 4728 // Floating Point Add Float 4729 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ 4730 single_instruction; 4731 dst : X(write); 4732 src1 : E(read); 4733 src2 : E(read); 4734 FA : R; 4735 %} 4736 4737 // Floating Point Add Double 4738 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ 4739 single_instruction; 4740 dst : X(write); 4741 src1 : E(read); 4742 src2 : E(read); 4743 FA : R; 4744 %} 4745 4746 // Floating Point Conditional Move based on integer flags 4747 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ 4748 single_instruction; 4749 dst : X(write); 4750 src : E(read); 4751 cr : R(read); 4752 FA : R(2); 4753 BR : R(2); 4754 %} 4755 4756 // Floating Point Conditional Move based on integer flags 4757 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ 4758 single_instruction; 4759 dst : X(write); 4760 src : E(read); 4761 cr : R(read); 4762 FA : R(2); 4763 BR : R(2); 4764 %} 4765 4766 // Floating Point Multiply Float 4767 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ 4768 single_instruction; 4769 dst : X(write); 4770 src1 : E(read); 4771 src2 : E(read); 4772 FM : R; 4773 %} 4774 4775 // Floating Point Multiply Double 4776 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ 4777 single_instruction; 4778 dst : X(write); 4779 src1 : E(read); 4780 src2 : E(read); 4781 FM : R; 4782 %} 4783 4784 // Floating Point Divide Float 4785 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ 4786 single_instruction; 4787 dst : X(write); 4788 src1 : E(read); 4789 src2 : E(read); 4790 FM : R; 4791 FDIV : C(14); 4792 %} 4793 4794 // Floating Point Divide Double 4795 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ 4796 single_instruction; 4797 dst : X(write); 4798 src1 : E(read); 4799 src2 : E(read); 4800 FM : R; 4801 FDIV : C(17); 4802 %} 4803 4804 // Floating Point Move/Negate/Abs Float 4805 pipe_class faddF_reg(regF dst, regF src) %{ 4806 single_instruction; 4807 dst : W(write); 4808 src : E(read); 4809 FA : R(1); 4810 %} 4811 4812 // Floating Point Move/Negate/Abs Double 4813 pipe_class faddD_reg(regD dst, regD src) %{ 4814 single_instruction; 4815 dst : W(write); 4816 src : E(read); 4817 FA : R; 4818 %} 4819 4820 // Floating Point Convert F->D 4821 pipe_class fcvtF2D(regD dst, regF src) %{ 4822 single_instruction; 4823 dst : X(write); 4824 src : E(read); 4825 FA : R; 4826 %} 4827 4828 // Floating Point Convert I->D 4829 pipe_class fcvtI2D(regD dst, regF src) %{ 4830 single_instruction; 4831 dst : X(write); 4832 src : E(read); 4833 FA : R; 4834 %} 4835 4836 // Floating Point Convert LHi->D 4837 pipe_class fcvtLHi2D(regD dst, regD src) %{ 4838 single_instruction; 4839 dst : X(write); 4840 src : E(read); 4841 FA : R; 4842 %} 4843 4844 // Floating Point Convert L->D 4845 pipe_class fcvtL2D(regD dst, regF src) %{ 4846 single_instruction; 4847 dst : X(write); 4848 src : E(read); 4849 FA : R; 4850 %} 4851 4852 // Floating Point Convert L->F 4853 pipe_class fcvtL2F(regD dst, regF src) %{ 4854 single_instruction; 4855 dst : X(write); 4856 src : E(read); 4857 FA : R; 4858 %} 4859 4860 // Floating Point Convert D->F 4861 pipe_class fcvtD2F(regD dst, regF src) %{ 4862 single_instruction; 4863 dst : X(write); 4864 src : E(read); 4865 FA : R; 4866 %} 4867 4868 // Floating Point Convert I->L 4869 pipe_class fcvtI2L(regD dst, regF src) %{ 4870 single_instruction; 4871 dst : X(write); 4872 src : E(read); 4873 FA : R; 4874 %} 4875 4876 // Floating Point Convert D->F 4877 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ 4878 instruction_count(1); multiple_bundles; 4879 dst : X(write)+6; 4880 src : E(read); 4881 FA : R; 4882 %} 4883 4884 // Floating Point Convert D->L 4885 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ 4886 instruction_count(1); multiple_bundles; 4887 dst : X(write)+6; 4888 src : E(read); 4889 FA : R; 4890 %} 4891 4892 // Floating Point Convert F->I 4893 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ 4894 instruction_count(1); multiple_bundles; 4895 dst : X(write)+6; 4896 src : E(read); 4897 FA : R; 4898 %} 4899 4900 // Floating Point Convert F->L 4901 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ 4902 instruction_count(1); multiple_bundles; 4903 dst : X(write)+6; 4904 src : E(read); 4905 FA : R; 4906 %} 4907 4908 // Floating Point Convert I->F 4909 pipe_class fcvtI2F(regF dst, regF src) %{ 4910 single_instruction; 4911 dst : X(write); 4912 src : E(read); 4913 FA : R; 4914 %} 4915 4916 // Floating Point Compare 4917 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ 4918 single_instruction; 4919 cr : X(write); 4920 src1 : E(read); 4921 src2 : E(read); 4922 FA : R; 4923 %} 4924 4925 // Floating Point Compare 4926 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ 4927 single_instruction; 4928 cr : X(write); 4929 src1 : E(read); 4930 src2 : E(read); 4931 FA : R; 4932 %} 4933 4934 // Floating Add Nop 4935 pipe_class fadd_nop() %{ 4936 single_instruction; 4937 FA : R; 4938 %} 4939 4940 // Integer Store to Memory 4941 pipe_class istore_mem_reg(memory mem, iRegI src) %{ 4942 single_instruction; 4943 mem : R(read); 4944 src : C(read); 4945 MS : R; 4946 %} 4947 4948 // Integer Store to Memory 4949 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ 4950 single_instruction; 4951 mem : R(read); 4952 src : C(read); 4953 MS : R; 4954 %} 4955 4956 // Integer Store Zero to Memory 4957 pipe_class istore_mem_zero(memory mem, immI0 src) %{ 4958 single_instruction; 4959 mem : R(read); 4960 MS : R; 4961 %} 4962 4963 // Special Stack Slot Store 4964 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ 4965 single_instruction; 4966 stkSlot : R(read); 4967 src : C(read); 4968 MS : R; 4969 %} 4970 4971 // Special Stack Slot Store 4972 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ 4973 instruction_count(2); multiple_bundles; 4974 stkSlot : R(read); 4975 src : C(read); 4976 MS : R(2); 4977 %} 4978 4979 // Float Store 4980 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ 4981 single_instruction; 4982 mem : R(read); 4983 src : C(read); 4984 MS : R; 4985 %} 4986 4987 // Float Store 4988 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ 4989 single_instruction; 4990 mem : R(read); 4991 MS : R; 4992 %} 4993 4994 // Double Store 4995 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ 4996 instruction_count(1); 4997 mem : R(read); 4998 src : C(read); 4999 MS : R; 5000 %} 5001 5002 // Double Store 5003 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ 5004 single_instruction; 5005 mem : R(read); 5006 MS : R; 5007 %} 5008 5009 // Special Stack Slot Float Store 5010 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ 5011 single_instruction; 5012 stkSlot : R(read); 5013 src : C(read); 5014 MS : R; 5015 %} 5016 5017 // Special Stack Slot Double Store 5018 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ 5019 single_instruction; 5020 stkSlot : R(read); 5021 src : C(read); 5022 MS : R; 5023 %} 5024 5025 // Integer Load (when sign bit propagation not needed) 5026 pipe_class iload_mem(iRegI dst, memory mem) %{ 5027 single_instruction; 5028 mem : R(read); 5029 dst : C(write); 5030 MS : R; 5031 %} 5032 5033 // Integer Load from stack operand 5034 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ 5035 single_instruction; 5036 mem : R(read); 5037 dst : C(write); 5038 MS : R; 5039 %} 5040 5041 // Integer Load (when sign bit propagation or masking is needed) 5042 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ 5043 single_instruction; 5044 mem : R(read); 5045 dst : M(write); 5046 MS : R; 5047 %} 5048 5049 // Float Load 5050 pipe_class floadF_mem(regF dst, memory mem) %{ 5051 single_instruction; 5052 mem : R(read); 5053 dst : M(write); 5054 MS : R; 5055 %} 5056 5057 // Float Load 5058 pipe_class floadD_mem(regD dst, memory mem) %{ 5059 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case 5060 mem : R(read); 5061 dst : M(write); 5062 MS : R; 5063 %} 5064 5065 // Float Load 5066 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ 5067 single_instruction; 5068 stkSlot : R(read); 5069 dst : M(write); 5070 MS : R; 5071 %} 5072 5073 // Float Load 5074 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ 5075 single_instruction; 5076 stkSlot : R(read); 5077 dst : M(write); 5078 MS : R; 5079 %} 5080 5081 // Memory Nop 5082 pipe_class mem_nop() %{ 5083 single_instruction; 5084 MS : R; 5085 %} 5086 5087 pipe_class sethi(iRegP dst, immI src) %{ 5088 single_instruction; 5089 dst : E(write); 5090 IALU : R; 5091 %} 5092 5093 pipe_class loadPollP(iRegP poll) %{ 5094 single_instruction; 5095 poll : R(read); 5096 MS : R; 5097 %} 5098 5099 pipe_class br(Universe br, label labl) %{ 5100 single_instruction_with_delay_slot; 5101 BR : R; 5102 %} 5103 5104 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ 5105 single_instruction_with_delay_slot; 5106 cr : E(read); 5107 BR : R; 5108 %} 5109 5110 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ 5111 single_instruction_with_delay_slot; 5112 op1 : E(read); 5113 BR : R; 5114 MS : R; 5115 %} 5116 5117 // Compare and branch 5118 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 5119 instruction_count(2); has_delay_slot; 5120 cr : E(write); 5121 src1 : R(read); 5122 src2 : R(read); 5123 IALU : R; 5124 BR : R; 5125 %} 5126 5127 // Compare and branch 5128 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ 5129 instruction_count(2); has_delay_slot; 5130 cr : E(write); 5131 src1 : R(read); 5132 IALU : R; 5133 BR : R; 5134 %} 5135 5136 // Compare and branch using cbcond 5137 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ 5138 single_instruction; 5139 src1 : E(read); 5140 src2 : E(read); 5141 IALU : R; 5142 BR : R; 5143 %} 5144 5145 // Compare and branch using cbcond 5146 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ 5147 single_instruction; 5148 src1 : E(read); 5149 IALU : R; 5150 BR : R; 5151 %} 5152 5153 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ 5154 single_instruction_with_delay_slot; 5155 cr : E(read); 5156 BR : R; 5157 %} 5158 5159 pipe_class br_nop() %{ 5160 single_instruction; 5161 BR : R; 5162 %} 5163 5164 pipe_class simple_call(method meth) %{ 5165 instruction_count(2); multiple_bundles; force_serialization; 5166 fixed_latency(100); 5167 BR : R(1); 5168 MS : R(1); 5169 A0 : R(1); 5170 %} 5171 5172 pipe_class compiled_call(method meth) %{ 5173 instruction_count(1); multiple_bundles; force_serialization; 5174 fixed_latency(100); 5175 MS : R(1); 5176 %} 5177 5178 pipe_class call(method meth) %{ 5179 instruction_count(0); multiple_bundles; force_serialization; 5180 fixed_latency(100); 5181 %} 5182 5183 pipe_class tail_call(Universe ignore, label labl) %{ 5184 single_instruction; has_delay_slot; 5185 fixed_latency(100); 5186 BR : R(1); 5187 MS : R(1); 5188 %} 5189 5190 pipe_class ret(Universe ignore) %{ 5191 single_instruction; has_delay_slot; 5192 BR : R(1); 5193 MS : R(1); 5194 %} 5195 5196 pipe_class ret_poll(g3RegP poll) %{ 5197 instruction_count(3); has_delay_slot; 5198 poll : E(read); 5199 MS : R; 5200 %} 5201 5202 // The real do-nothing guy 5203 pipe_class empty( ) %{ 5204 instruction_count(0); 5205 %} 5206 5207 pipe_class long_memory_op() %{ 5208 instruction_count(0); multiple_bundles; force_serialization; 5209 fixed_latency(25); 5210 MS : R(1); 5211 %} 5212 5213 // Check-cast 5214 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ 5215 array : R(read); 5216 match : R(read); 5217 IALU : R(2); 5218 BR : R(2); 5219 MS : R; 5220 %} 5221 5222 // Convert FPU flags into +1,0,-1 5223 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ 5224 src1 : E(read); 5225 src2 : E(read); 5226 dst : E(write); 5227 FA : R; 5228 MS : R(2); 5229 BR : R(2); 5230 %} 5231 5232 // Compare for p < q, and conditionally add y 5233 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ 5234 p : E(read); 5235 q : E(read); 5236 y : E(read); 5237 IALU : R(3) 5238 %} 5239 5240 // Perform a compare, then move conditionally in a branch delay slot. 5241 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ 5242 src2 : E(read); 5243 srcdst : E(read); 5244 IALU : R; 5245 BR : R; 5246 %} 5247 5248 // Define the class for the Nop node 5249 define %{ 5250 MachNop = ialu_nop; 5251 %} 5252 5253 %} 5254 5255 //----------INSTRUCTIONS------------------------------------------------------- 5256 5257 //------------Special Stack Slot instructions - no match rules----------------- 5258 instruct stkI_to_regF(regF dst, stackSlotI src) %{ 5259 // No match rule to avoid chain rule match. 5260 effect(DEF dst, USE src); 5261 ins_cost(MEMORY_REF_COST); 5262 format %{ "LDF $src,$dst\t! stkI to regF" %} 5263 opcode(Assembler::ldf_op3); 5264 ins_encode(simple_form3_mem_reg(src, dst)); 5265 ins_pipe(floadF_stk); 5266 %} 5267 5268 instruct stkL_to_regD(regD dst, stackSlotL src) %{ 5269 // No match rule to avoid chain rule match. 5270 effect(DEF dst, USE src); 5271 ins_cost(MEMORY_REF_COST); 5272 format %{ "LDDF $src,$dst\t! stkL to regD" %} 5273 opcode(Assembler::lddf_op3); 5274 ins_encode(simple_form3_mem_reg(src, dst)); 5275 ins_pipe(floadD_stk); 5276 %} 5277 5278 instruct regF_to_stkI(stackSlotI dst, regF src) %{ 5279 // No match rule to avoid chain rule match. 5280 effect(DEF dst, USE src); 5281 ins_cost(MEMORY_REF_COST); 5282 format %{ "STF $src,$dst\t! regF to stkI" %} 5283 opcode(Assembler::stf_op3); 5284 ins_encode(simple_form3_mem_reg(dst, src)); 5285 ins_pipe(fstoreF_stk_reg); 5286 %} 5287 5288 instruct regD_to_stkL(stackSlotL dst, regD src) %{ 5289 // No match rule to avoid chain rule match. 5290 effect(DEF dst, USE src); 5291 ins_cost(MEMORY_REF_COST); 5292 format %{ "STDF $src,$dst\t! regD to stkL" %} 5293 opcode(Assembler::stdf_op3); 5294 ins_encode(simple_form3_mem_reg(dst, src)); 5295 ins_pipe(fstoreD_stk_reg); 5296 %} 5297 5298 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ 5299 effect(DEF dst, USE src); 5300 ins_cost(MEMORY_REF_COST*2); 5301 format %{ "STW $src,$dst.hi\t! long\n\t" 5302 "STW R_G0,$dst.lo" %} 5303 opcode(Assembler::stw_op3); 5304 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); 5305 ins_pipe(lstoreI_stk_reg); 5306 %} 5307 5308 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ 5309 // No match rule to avoid chain rule match. 5310 effect(DEF dst, USE src); 5311 ins_cost(MEMORY_REF_COST); 5312 format %{ "STX $src,$dst\t! regL to stkD" %} 5313 opcode(Assembler::stx_op3); 5314 ins_encode(simple_form3_mem_reg( dst, src ) ); 5315 ins_pipe(istore_stk_reg); 5316 %} 5317 5318 //---------- Chain stack slots between similar types -------- 5319 5320 // Load integer from stack slot 5321 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ 5322 match(Set dst src); 5323 ins_cost(MEMORY_REF_COST); 5324 5325 format %{ "LDUW $src,$dst\t!stk" %} 5326 opcode(Assembler::lduw_op3); 5327 ins_encode(simple_form3_mem_reg( src, dst ) ); 5328 ins_pipe(iload_mem); 5329 %} 5330 5331 // Store integer to stack slot 5332 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ 5333 match(Set dst src); 5334 ins_cost(MEMORY_REF_COST); 5335 5336 format %{ "STW $src,$dst\t!stk" %} 5337 opcode(Assembler::stw_op3); 5338 ins_encode(simple_form3_mem_reg( dst, src ) ); 5339 ins_pipe(istore_mem_reg); 5340 %} 5341 5342 // Load long from stack slot 5343 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ 5344 match(Set dst src); 5345 5346 ins_cost(MEMORY_REF_COST); 5347 format %{ "LDX $src,$dst\t! long" %} 5348 opcode(Assembler::ldx_op3); 5349 ins_encode(simple_form3_mem_reg( src, dst ) ); 5350 ins_pipe(iload_mem); 5351 %} 5352 5353 // Store long to stack slot 5354 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 5355 match(Set dst src); 5356 5357 ins_cost(MEMORY_REF_COST); 5358 format %{ "STX $src,$dst\t! long" %} 5359 opcode(Assembler::stx_op3); 5360 ins_encode(simple_form3_mem_reg( dst, src ) ); 5361 ins_pipe(istore_mem_reg); 5362 %} 5363 5364 #ifdef _LP64 5365 // Load pointer from stack slot, 64-bit encoding 5366 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5367 match(Set dst src); 5368 ins_cost(MEMORY_REF_COST); 5369 format %{ "LDX $src,$dst\t!ptr" %} 5370 opcode(Assembler::ldx_op3); 5371 ins_encode(simple_form3_mem_reg( src, dst ) ); 5372 ins_pipe(iload_mem); 5373 %} 5374 5375 // Store pointer to stack slot 5376 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5377 match(Set dst src); 5378 ins_cost(MEMORY_REF_COST); 5379 format %{ "STX $src,$dst\t!ptr" %} 5380 opcode(Assembler::stx_op3); 5381 ins_encode(simple_form3_mem_reg( dst, src ) ); 5382 ins_pipe(istore_mem_reg); 5383 %} 5384 #else // _LP64 5385 // Load pointer from stack slot, 32-bit encoding 5386 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5387 match(Set dst src); 5388 ins_cost(MEMORY_REF_COST); 5389 format %{ "LDUW $src,$dst\t!ptr" %} 5390 opcode(Assembler::lduw_op3, Assembler::ldst_op); 5391 ins_encode(simple_form3_mem_reg( src, dst ) ); 5392 ins_pipe(iload_mem); 5393 %} 5394 5395 // Store pointer to stack slot 5396 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5397 match(Set dst src); 5398 ins_cost(MEMORY_REF_COST); 5399 format %{ "STW $src,$dst\t!ptr" %} 5400 opcode(Assembler::stw_op3, Assembler::ldst_op); 5401 ins_encode(simple_form3_mem_reg( dst, src ) ); 5402 ins_pipe(istore_mem_reg); 5403 %} 5404 #endif // _LP64 5405 5406 //------------Special Nop instructions for bundling - no match rules----------- 5407 // Nop using the A0 functional unit 5408 instruct Nop_A0() %{ 5409 ins_cost(0); 5410 5411 format %{ "NOP ! Alu Pipeline" %} 5412 opcode(Assembler::or_op3, Assembler::arith_op); 5413 ins_encode( form2_nop() ); 5414 ins_pipe(ialu_nop_A0); 5415 %} 5416 5417 // Nop using the A1 functional unit 5418 instruct Nop_A1( ) %{ 5419 ins_cost(0); 5420 5421 format %{ "NOP ! Alu Pipeline" %} 5422 opcode(Assembler::or_op3, Assembler::arith_op); 5423 ins_encode( form2_nop() ); 5424 ins_pipe(ialu_nop_A1); 5425 %} 5426 5427 // Nop using the memory functional unit 5428 instruct Nop_MS( ) %{ 5429 ins_cost(0); 5430 5431 format %{ "NOP ! Memory Pipeline" %} 5432 ins_encode( emit_mem_nop ); 5433 ins_pipe(mem_nop); 5434 %} 5435 5436 // Nop using the floating add functional unit 5437 instruct Nop_FA( ) %{ 5438 ins_cost(0); 5439 5440 format %{ "NOP ! Floating Add Pipeline" %} 5441 ins_encode( emit_fadd_nop ); 5442 ins_pipe(fadd_nop); 5443 %} 5444 5445 // Nop using the branch functional unit 5446 instruct Nop_BR( ) %{ 5447 ins_cost(0); 5448 5449 format %{ "NOP ! Branch Pipeline" %} 5450 ins_encode( emit_br_nop ); 5451 ins_pipe(br_nop); 5452 %} 5453 5454 //----------Load/Store/Move Instructions--------------------------------------- 5455 //----------Load Instructions-------------------------------------------------- 5456 // Load Byte (8bit signed) 5457 instruct loadB(iRegI dst, memory mem) %{ 5458 match(Set dst (LoadB mem)); 5459 ins_cost(MEMORY_REF_COST); 5460 5461 size(4); 5462 format %{ "LDSB $mem,$dst\t! byte" %} 5463 ins_encode %{ 5464 __ ldsb($mem$$Address, $dst$$Register); 5465 %} 5466 ins_pipe(iload_mask_mem); 5467 %} 5468 5469 // Load Byte (8bit signed) into a Long Register 5470 instruct loadB2L(iRegL dst, memory mem) %{ 5471 match(Set dst (ConvI2L (LoadB mem))); 5472 ins_cost(MEMORY_REF_COST); 5473 5474 size(4); 5475 format %{ "LDSB $mem,$dst\t! byte -> long" %} 5476 ins_encode %{ 5477 __ ldsb($mem$$Address, $dst$$Register); 5478 %} 5479 ins_pipe(iload_mask_mem); 5480 %} 5481 5482 // Load Unsigned Byte (8bit UNsigned) into an int reg 5483 instruct loadUB(iRegI dst, memory mem) %{ 5484 match(Set dst (LoadUB mem)); 5485 ins_cost(MEMORY_REF_COST); 5486 5487 size(4); 5488 format %{ "LDUB $mem,$dst\t! ubyte" %} 5489 ins_encode %{ 5490 __ ldub($mem$$Address, $dst$$Register); 5491 %} 5492 ins_pipe(iload_mem); 5493 %} 5494 5495 // Load Unsigned Byte (8bit UNsigned) into a Long Register 5496 instruct loadUB2L(iRegL dst, memory mem) %{ 5497 match(Set dst (ConvI2L (LoadUB mem))); 5498 ins_cost(MEMORY_REF_COST); 5499 5500 size(4); 5501 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} 5502 ins_encode %{ 5503 __ ldub($mem$$Address, $dst$$Register); 5504 %} 5505 ins_pipe(iload_mem); 5506 %} 5507 5508 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register 5509 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{ 5510 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); 5511 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5512 5513 size(2*4); 5514 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t" 5515 "AND $dst,right_n_bits($mask, 8),$dst" %} 5516 ins_encode %{ 5517 __ ldub($mem$$Address, $dst$$Register); 5518 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register); 5519 %} 5520 ins_pipe(iload_mem); 5521 %} 5522 5523 // Load Short (16bit signed) 5524 instruct loadS(iRegI dst, memory mem) %{ 5525 match(Set dst (LoadS mem)); 5526 ins_cost(MEMORY_REF_COST); 5527 5528 size(4); 5529 format %{ "LDSH $mem,$dst\t! short" %} 5530 ins_encode %{ 5531 __ ldsh($mem$$Address, $dst$$Register); 5532 %} 5533 ins_pipe(iload_mask_mem); 5534 %} 5535 5536 // Load Short (16 bit signed) to Byte (8 bit signed) 5537 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5538 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 5539 ins_cost(MEMORY_REF_COST); 5540 5541 size(4); 5542 5543 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} 5544 ins_encode %{ 5545 __ ldsb($mem$$Address, $dst$$Register, 1); 5546 %} 5547 ins_pipe(iload_mask_mem); 5548 %} 5549 5550 // Load Short (16bit signed) into a Long Register 5551 instruct loadS2L(iRegL dst, memory mem) %{ 5552 match(Set dst (ConvI2L (LoadS mem))); 5553 ins_cost(MEMORY_REF_COST); 5554 5555 size(4); 5556 format %{ "LDSH $mem,$dst\t! short -> long" %} 5557 ins_encode %{ 5558 __ ldsh($mem$$Address, $dst$$Register); 5559 %} 5560 ins_pipe(iload_mask_mem); 5561 %} 5562 5563 // Load Unsigned Short/Char (16bit UNsigned) 5564 instruct loadUS(iRegI dst, memory mem) %{ 5565 match(Set dst (LoadUS mem)); 5566 ins_cost(MEMORY_REF_COST); 5567 5568 size(4); 5569 format %{ "LDUH $mem,$dst\t! ushort/char" %} 5570 ins_encode %{ 5571 __ lduh($mem$$Address, $dst$$Register); 5572 %} 5573 ins_pipe(iload_mem); 5574 %} 5575 5576 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 5577 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5578 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 5579 ins_cost(MEMORY_REF_COST); 5580 5581 size(4); 5582 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} 5583 ins_encode %{ 5584 __ ldsb($mem$$Address, $dst$$Register, 1); 5585 %} 5586 ins_pipe(iload_mask_mem); 5587 %} 5588 5589 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register 5590 instruct loadUS2L(iRegL dst, memory mem) %{ 5591 match(Set dst (ConvI2L (LoadUS mem))); 5592 ins_cost(MEMORY_REF_COST); 5593 5594 size(4); 5595 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} 5596 ins_encode %{ 5597 __ lduh($mem$$Address, $dst$$Register); 5598 %} 5599 ins_pipe(iload_mem); 5600 %} 5601 5602 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register 5603 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5604 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5605 ins_cost(MEMORY_REF_COST); 5606 5607 size(4); 5608 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} 5609 ins_encode %{ 5610 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE 5611 %} 5612 ins_pipe(iload_mem); 5613 %} 5614 5615 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register 5616 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5617 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5618 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5619 5620 size(2*4); 5621 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" 5622 "AND $dst,$mask,$dst" %} 5623 ins_encode %{ 5624 Register Rdst = $dst$$Register; 5625 __ lduh($mem$$Address, Rdst); 5626 __ and3(Rdst, $mask$$constant, Rdst); 5627 %} 5628 ins_pipe(iload_mem); 5629 %} 5630 5631 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register 5632 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ 5633 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5634 effect(TEMP dst, TEMP tmp); 5635 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5636 5637 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t" 5638 "SET right_n_bits($mask, 16),$tmp\n\t" 5639 "AND $dst,$tmp,$dst" %} 5640 ins_encode %{ 5641 Register Rdst = $dst$$Register; 5642 Register Rtmp = $tmp$$Register; 5643 __ lduh($mem$$Address, Rdst); 5644 __ set($mask$$constant & right_n_bits(16), Rtmp); 5645 __ and3(Rdst, Rtmp, Rdst); 5646 %} 5647 ins_pipe(iload_mem); 5648 %} 5649 5650 // Load Integer 5651 instruct loadI(iRegI dst, memory mem) %{ 5652 match(Set dst (LoadI mem)); 5653 ins_cost(MEMORY_REF_COST); 5654 5655 size(4); 5656 format %{ "LDUW $mem,$dst\t! int" %} 5657 ins_encode %{ 5658 __ lduw($mem$$Address, $dst$$Register); 5659 %} 5660 ins_pipe(iload_mem); 5661 %} 5662 5663 // Load Integer to Byte (8 bit signed) 5664 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5665 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 5666 ins_cost(MEMORY_REF_COST); 5667 5668 size(4); 5669 5670 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} 5671 ins_encode %{ 5672 __ ldsb($mem$$Address, $dst$$Register, 3); 5673 %} 5674 ins_pipe(iload_mask_mem); 5675 %} 5676 5677 // Load Integer to Unsigned Byte (8 bit UNsigned) 5678 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ 5679 match(Set dst (AndI (LoadI mem) mask)); 5680 ins_cost(MEMORY_REF_COST); 5681 5682 size(4); 5683 5684 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} 5685 ins_encode %{ 5686 __ ldub($mem$$Address, $dst$$Register, 3); 5687 %} 5688 ins_pipe(iload_mask_mem); 5689 %} 5690 5691 // Load Integer to Short (16 bit signed) 5692 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ 5693 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 5694 ins_cost(MEMORY_REF_COST); 5695 5696 size(4); 5697 5698 format %{ "LDSH $mem+2,$dst\t! int -> short" %} 5699 ins_encode %{ 5700 __ ldsh($mem$$Address, $dst$$Register, 2); 5701 %} 5702 ins_pipe(iload_mask_mem); 5703 %} 5704 5705 // Load Integer to Unsigned Short (16 bit UNsigned) 5706 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ 5707 match(Set dst (AndI (LoadI mem) mask)); 5708 ins_cost(MEMORY_REF_COST); 5709 5710 size(4); 5711 5712 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} 5713 ins_encode %{ 5714 __ lduh($mem$$Address, $dst$$Register, 2); 5715 %} 5716 ins_pipe(iload_mask_mem); 5717 %} 5718 5719 // Load Integer into a Long Register 5720 instruct loadI2L(iRegL dst, memory mem) %{ 5721 match(Set dst (ConvI2L (LoadI mem))); 5722 ins_cost(MEMORY_REF_COST); 5723 5724 size(4); 5725 format %{ "LDSW $mem,$dst\t! int -> long" %} 5726 ins_encode %{ 5727 __ ldsw($mem$$Address, $dst$$Register); 5728 %} 5729 ins_pipe(iload_mask_mem); 5730 %} 5731 5732 // Load Integer with mask 0xFF into a Long Register 5733 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5734 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5735 ins_cost(MEMORY_REF_COST); 5736 5737 size(4); 5738 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} 5739 ins_encode %{ 5740 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE 5741 %} 5742 ins_pipe(iload_mem); 5743 %} 5744 5745 // Load Integer with mask 0xFFFF into a Long Register 5746 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ 5747 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5748 ins_cost(MEMORY_REF_COST); 5749 5750 size(4); 5751 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} 5752 ins_encode %{ 5753 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE 5754 %} 5755 ins_pipe(iload_mem); 5756 %} 5757 5758 // Load Integer with a 12-bit mask into a Long Register 5759 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{ 5760 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5761 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5762 5763 size(2*4); 5764 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t" 5765 "AND $dst,$mask,$dst" %} 5766 ins_encode %{ 5767 Register Rdst = $dst$$Register; 5768 __ lduw($mem$$Address, Rdst); 5769 __ and3(Rdst, $mask$$constant, Rdst); 5770 %} 5771 ins_pipe(iload_mem); 5772 %} 5773 5774 // Load Integer with a 31-bit mask into a Long Register 5775 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{ 5776 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5777 effect(TEMP dst, TEMP tmp); 5778 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5779 5780 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t" 5781 "SET $mask,$tmp\n\t" 5782 "AND $dst,$tmp,$dst" %} 5783 ins_encode %{ 5784 Register Rdst = $dst$$Register; 5785 Register Rtmp = $tmp$$Register; 5786 __ lduw($mem$$Address, Rdst); 5787 __ set($mask$$constant, Rtmp); 5788 __ and3(Rdst, Rtmp, Rdst); 5789 %} 5790 ins_pipe(iload_mem); 5791 %} 5792 5793 // Load Unsigned Integer into a Long Register 5794 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{ 5795 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 5796 ins_cost(MEMORY_REF_COST); 5797 5798 size(4); 5799 format %{ "LDUW $mem,$dst\t! uint -> long" %} 5800 ins_encode %{ 5801 __ lduw($mem$$Address, $dst$$Register); 5802 %} 5803 ins_pipe(iload_mem); 5804 %} 5805 5806 // Load Long - aligned 5807 instruct loadL(iRegL dst, memory mem ) %{ 5808 match(Set dst (LoadL mem)); 5809 ins_cost(MEMORY_REF_COST); 5810 5811 size(4); 5812 format %{ "LDX $mem,$dst\t! long" %} 5813 ins_encode %{ 5814 __ ldx($mem$$Address, $dst$$Register); 5815 %} 5816 ins_pipe(iload_mem); 5817 %} 5818 5819 // Load Long - UNaligned 5820 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ 5821 match(Set dst (LoadL_unaligned mem)); 5822 effect(KILL tmp); 5823 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5824 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" 5825 "\tLDUW $mem ,$dst\n" 5826 "\tSLLX #32, $dst, $dst\n" 5827 "\tOR $dst, R_O7, $dst" %} 5828 opcode(Assembler::lduw_op3); 5829 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); 5830 ins_pipe(iload_mem); 5831 %} 5832 5833 // Load Range 5834 instruct loadRange(iRegI dst, memory mem) %{ 5835 match(Set dst (LoadRange mem)); 5836 ins_cost(MEMORY_REF_COST); 5837 5838 format %{ "LDUW $mem,$dst\t! range" %} 5839 opcode(Assembler::lduw_op3); 5840 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5841 ins_pipe(iload_mem); 5842 %} 5843 5844 // Load Integer into %f register (for fitos/fitod) 5845 instruct loadI_freg(regF dst, memory mem) %{ 5846 match(Set dst (LoadI mem)); 5847 ins_cost(MEMORY_REF_COST); 5848 5849 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} 5850 opcode(Assembler::ldf_op3); 5851 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5852 ins_pipe(floadF_mem); 5853 %} 5854 5855 // Load Pointer 5856 instruct loadP(iRegP dst, memory mem) %{ 5857 match(Set dst (LoadP mem)); 5858 ins_cost(MEMORY_REF_COST); 5859 size(4); 5860 5861 #ifndef _LP64 5862 format %{ "LDUW $mem,$dst\t! ptr" %} 5863 ins_encode %{ 5864 __ lduw($mem$$Address, $dst$$Register); 5865 %} 5866 #else 5867 format %{ "LDX $mem,$dst\t! ptr" %} 5868 ins_encode %{ 5869 __ ldx($mem$$Address, $dst$$Register); 5870 %} 5871 #endif 5872 ins_pipe(iload_mem); 5873 %} 5874 5875 // Load Compressed Pointer 5876 instruct loadN(iRegN dst, memory mem) %{ 5877 match(Set dst (LoadN mem)); 5878 ins_cost(MEMORY_REF_COST); 5879 size(4); 5880 5881 format %{ "LDUW $mem,$dst\t! compressed ptr" %} 5882 ins_encode %{ 5883 __ lduw($mem$$Address, $dst$$Register); 5884 %} 5885 ins_pipe(iload_mem); 5886 %} 5887 5888 // Load Klass Pointer 5889 instruct loadKlass(iRegP dst, memory mem) %{ 5890 match(Set dst (LoadKlass mem)); 5891 ins_cost(MEMORY_REF_COST); 5892 size(4); 5893 5894 #ifndef _LP64 5895 format %{ "LDUW $mem,$dst\t! klass ptr" %} 5896 ins_encode %{ 5897 __ lduw($mem$$Address, $dst$$Register); 5898 %} 5899 #else 5900 format %{ "LDX $mem,$dst\t! klass ptr" %} 5901 ins_encode %{ 5902 __ ldx($mem$$Address, $dst$$Register); 5903 %} 5904 #endif 5905 ins_pipe(iload_mem); 5906 %} 5907 5908 // Load narrow Klass Pointer 5909 instruct loadNKlass(iRegN dst, memory mem) %{ 5910 match(Set dst (LoadNKlass mem)); 5911 ins_cost(MEMORY_REF_COST); 5912 size(4); 5913 5914 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} 5915 ins_encode %{ 5916 __ lduw($mem$$Address, $dst$$Register); 5917 %} 5918 ins_pipe(iload_mem); 5919 %} 5920 5921 // Load Double 5922 instruct loadD(regD dst, memory mem) %{ 5923 match(Set dst (LoadD mem)); 5924 ins_cost(MEMORY_REF_COST); 5925 5926 format %{ "LDDF $mem,$dst" %} 5927 opcode(Assembler::lddf_op3); 5928 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5929 ins_pipe(floadD_mem); 5930 %} 5931 5932 // Load Double - UNaligned 5933 instruct loadD_unaligned(regD_low dst, memory mem ) %{ 5934 match(Set dst (LoadD_unaligned mem)); 5935 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5936 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" 5937 "\tLDF $mem+4,$dst.lo\t!" %} 5938 opcode(Assembler::ldf_op3); 5939 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); 5940 ins_pipe(iload_mem); 5941 %} 5942 5943 // Load Float 5944 instruct loadF(regF dst, memory mem) %{ 5945 match(Set dst (LoadF mem)); 5946 ins_cost(MEMORY_REF_COST); 5947 5948 format %{ "LDF $mem,$dst" %} 5949 opcode(Assembler::ldf_op3); 5950 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5951 ins_pipe(floadF_mem); 5952 %} 5953 5954 // Load Constant 5955 instruct loadConI( iRegI dst, immI src ) %{ 5956 match(Set dst src); 5957 ins_cost(DEFAULT_COST * 3/2); 5958 format %{ "SET $src,$dst" %} 5959 ins_encode( Set32(src, dst) ); 5960 ins_pipe(ialu_hi_lo_reg); 5961 %} 5962 5963 instruct loadConI13( iRegI dst, immI13 src ) %{ 5964 match(Set dst src); 5965 5966 size(4); 5967 format %{ "MOV $src,$dst" %} 5968 ins_encode( Set13( src, dst ) ); 5969 ins_pipe(ialu_imm); 5970 %} 5971 5972 #ifndef _LP64 5973 instruct loadConP(iRegP dst, immP con) %{ 5974 match(Set dst con); 5975 ins_cost(DEFAULT_COST * 3/2); 5976 format %{ "SET $con,$dst\t!ptr" %} 5977 ins_encode %{ 5978 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); 5979 intptr_t val = $con$$constant; 5980 if (constant_reloc == relocInfo::oop_type) { 5981 __ set_oop_constant((jobject) val, $dst$$Register); 5982 } else if (constant_reloc == relocInfo::metadata_type) { 5983 __ set_metadata_constant((Metadata*)val, $dst$$Register); 5984 } else { // non-oop pointers, e.g. card mark base, heap top 5985 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); 5986 __ set(val, $dst$$Register); 5987 } 5988 %} 5989 ins_pipe(loadConP); 5990 %} 5991 #else 5992 instruct loadConP_set(iRegP dst, immP_set con) %{ 5993 match(Set dst con); 5994 ins_cost(DEFAULT_COST * 3/2); 5995 format %{ "SET $con,$dst\t! ptr" %} 5996 ins_encode %{ 5997 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); 5998 intptr_t val = $con$$constant; 5999 if (constant_reloc == relocInfo::oop_type) { 6000 __ set_oop_constant((jobject) val, $dst$$Register); 6001 } else if (constant_reloc == relocInfo::metadata_type) { 6002 __ set_metadata_constant((Metadata*)val, $dst$$Register); 6003 } else { // non-oop pointers, e.g. card mark base, heap top 6004 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); 6005 __ set(val, $dst$$Register); 6006 } 6007 %} 6008 ins_pipe(loadConP); 6009 %} 6010 6011 instruct loadConP_load(iRegP dst, immP_load con) %{ 6012 match(Set dst con); 6013 ins_cost(MEMORY_REF_COST); 6014 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} 6015 ins_encode %{ 6016 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 6017 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); 6018 %} 6019 ins_pipe(loadConP); 6020 %} 6021 6022 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ 6023 match(Set dst con); 6024 ins_cost(DEFAULT_COST * 3/2); 6025 format %{ "SET $con,$dst\t! non-oop ptr" %} 6026 ins_encode %{ 6027 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) { 6028 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register); 6029 } else { 6030 __ set($con$$constant, $dst$$Register); 6031 } 6032 %} 6033 ins_pipe(loadConP); 6034 %} 6035 #endif // _LP64 6036 6037 instruct loadConP0(iRegP dst, immP0 src) %{ 6038 match(Set dst src); 6039 6040 size(4); 6041 format %{ "CLR $dst\t!ptr" %} 6042 ins_encode %{ 6043 __ clr($dst$$Register); 6044 %} 6045 ins_pipe(ialu_imm); 6046 %} 6047 6048 instruct loadConP_poll(iRegP dst, immP_poll src) %{ 6049 match(Set dst src); 6050 ins_cost(DEFAULT_COST); 6051 format %{ "SET $src,$dst\t!ptr" %} 6052 ins_encode %{ 6053 AddressLiteral polling_page(os::get_polling_page()); 6054 __ sethi(polling_page, reg_to_register_object($dst$$reg)); 6055 %} 6056 ins_pipe(loadConP_poll); 6057 %} 6058 6059 instruct loadConN0(iRegN dst, immN0 src) %{ 6060 match(Set dst src); 6061 6062 size(4); 6063 format %{ "CLR $dst\t! compressed NULL ptr" %} 6064 ins_encode %{ 6065 __ clr($dst$$Register); 6066 %} 6067 ins_pipe(ialu_imm); 6068 %} 6069 6070 instruct loadConN(iRegN dst, immN src) %{ 6071 match(Set dst src); 6072 ins_cost(DEFAULT_COST * 3/2); 6073 format %{ "SET $src,$dst\t! compressed ptr" %} 6074 ins_encode %{ 6075 Register dst = $dst$$Register; 6076 __ set_narrow_oop((jobject)$src$$constant, dst); 6077 %} 6078 ins_pipe(ialu_hi_lo_reg); 6079 %} 6080 6081 instruct loadConNKlass(iRegN dst, immNKlass src) %{ 6082 match(Set dst src); 6083 ins_cost(DEFAULT_COST * 3/2); 6084 format %{ "SET $src,$dst\t! compressed klass ptr" %} 6085 ins_encode %{ 6086 Register dst = $dst$$Register; 6087 __ set_narrow_klass((Klass*)$src$$constant, dst); 6088 %} 6089 ins_pipe(ialu_hi_lo_reg); 6090 %} 6091 6092 // Materialize long value (predicated by immL_cheap). 6093 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ 6094 match(Set dst con); 6095 effect(KILL tmp); 6096 ins_cost(DEFAULT_COST * 3); 6097 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} 6098 ins_encode %{ 6099 __ set64($con$$constant, $dst$$Register, $tmp$$Register); 6100 %} 6101 ins_pipe(loadConL); 6102 %} 6103 6104 // Load long value from constant table (predicated by immL_expensive). 6105 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ 6106 match(Set dst con); 6107 ins_cost(MEMORY_REF_COST); 6108 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} 6109 ins_encode %{ 6110 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 6111 __ ldx($constanttablebase, con_offset, $dst$$Register); 6112 %} 6113 ins_pipe(loadConL); 6114 %} 6115 6116 instruct loadConL0( iRegL dst, immL0 src ) %{ 6117 match(Set dst src); 6118 ins_cost(DEFAULT_COST); 6119 size(4); 6120 format %{ "CLR $dst\t! long" %} 6121 ins_encode( Set13( src, dst ) ); 6122 ins_pipe(ialu_imm); 6123 %} 6124 6125 instruct loadConL13( iRegL dst, immL13 src ) %{ 6126 match(Set dst src); 6127 ins_cost(DEFAULT_COST * 2); 6128 6129 size(4); 6130 format %{ "MOV $src,$dst\t! long" %} 6131 ins_encode( Set13( src, dst ) ); 6132 ins_pipe(ialu_imm); 6133 %} 6134 6135 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ 6136 match(Set dst con); 6137 effect(KILL tmp); 6138 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} 6139 ins_encode %{ 6140 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 6141 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); 6142 %} 6143 ins_pipe(loadConFD); 6144 %} 6145 6146 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ 6147 match(Set dst con); 6148 effect(KILL tmp); 6149 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} 6150 ins_encode %{ 6151 // XXX This is a quick fix for 6833573. 6152 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); 6153 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 6154 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 6155 %} 6156 ins_pipe(loadConFD); 6157 %} 6158 6159 // Prefetch instructions for allocation. 6160 // Must be safe to execute with invalid address (cannot fault). 6161 6162 instruct prefetchAlloc( memory mem ) %{ 6163 predicate(AllocatePrefetchInstr == 0); 6164 match( PrefetchAllocation mem ); 6165 ins_cost(MEMORY_REF_COST); 6166 6167 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} 6168 opcode(Assembler::prefetch_op3); 6169 ins_encode( form3_mem_prefetch_write( mem ) ); 6170 ins_pipe(iload_mem); 6171 %} 6172 6173 // Use BIS instruction to prefetch for allocation. 6174 // Could fault, need space at the end of TLAB. 6175 instruct prefetchAlloc_bis( iRegP dst ) %{ 6176 predicate(AllocatePrefetchInstr == 1); 6177 match( PrefetchAllocation dst ); 6178 ins_cost(MEMORY_REF_COST); 6179 size(4); 6180 6181 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} 6182 ins_encode %{ 6183 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); 6184 %} 6185 ins_pipe(istore_mem_reg); 6186 %} 6187 6188 // Next code is used for finding next cache line address to prefetch. 6189 #ifndef _LP64 6190 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{ 6191 match(Set dst (CastX2P (AndI (CastP2X src) mask))); 6192 ins_cost(DEFAULT_COST); 6193 size(4); 6194 6195 format %{ "AND $src,$mask,$dst\t! next cache line address" %} 6196 ins_encode %{ 6197 __ and3($src$$Register, $mask$$constant, $dst$$Register); 6198 %} 6199 ins_pipe(ialu_reg_imm); 6200 %} 6201 #else 6202 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ 6203 match(Set dst (CastX2P (AndL (CastP2X src) mask))); 6204 ins_cost(DEFAULT_COST); 6205 size(4); 6206 6207 format %{ "AND $src,$mask,$dst\t! next cache line address" %} 6208 ins_encode %{ 6209 __ and3($src$$Register, $mask$$constant, $dst$$Register); 6210 %} 6211 ins_pipe(ialu_reg_imm); 6212 %} 6213 #endif 6214 6215 //----------Store Instructions------------------------------------------------- 6216 // Store Byte 6217 instruct storeB(memory mem, iRegI src) %{ 6218 match(Set mem (StoreB mem src)); 6219 ins_cost(MEMORY_REF_COST); 6220 6221 format %{ "STB $src,$mem\t! byte" %} 6222 opcode(Assembler::stb_op3); 6223 ins_encode(simple_form3_mem_reg( mem, src ) ); 6224 ins_pipe(istore_mem_reg); 6225 %} 6226 6227 instruct storeB0(memory mem, immI0 src) %{ 6228 match(Set mem (StoreB mem src)); 6229 ins_cost(MEMORY_REF_COST); 6230 6231 format %{ "STB $src,$mem\t! byte" %} 6232 opcode(Assembler::stb_op3); 6233 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6234 ins_pipe(istore_mem_zero); 6235 %} 6236 6237 instruct storeCM0(memory mem, immI0 src) %{ 6238 match(Set mem (StoreCM mem src)); 6239 ins_cost(MEMORY_REF_COST); 6240 6241 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} 6242 opcode(Assembler::stb_op3); 6243 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6244 ins_pipe(istore_mem_zero); 6245 %} 6246 6247 // Store Char/Short 6248 instruct storeC(memory mem, iRegI src) %{ 6249 match(Set mem (StoreC mem src)); 6250 ins_cost(MEMORY_REF_COST); 6251 6252 format %{ "STH $src,$mem\t! short" %} 6253 opcode(Assembler::sth_op3); 6254 ins_encode(simple_form3_mem_reg( mem, src ) ); 6255 ins_pipe(istore_mem_reg); 6256 %} 6257 6258 instruct storeC0(memory mem, immI0 src) %{ 6259 match(Set mem (StoreC mem src)); 6260 ins_cost(MEMORY_REF_COST); 6261 6262 format %{ "STH $src,$mem\t! short" %} 6263 opcode(Assembler::sth_op3); 6264 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6265 ins_pipe(istore_mem_zero); 6266 %} 6267 6268 // Store Integer 6269 instruct storeI(memory mem, iRegI src) %{ 6270 match(Set mem (StoreI mem src)); 6271 ins_cost(MEMORY_REF_COST); 6272 6273 format %{ "STW $src,$mem" %} 6274 opcode(Assembler::stw_op3); 6275 ins_encode(simple_form3_mem_reg( mem, src ) ); 6276 ins_pipe(istore_mem_reg); 6277 %} 6278 6279 // Store Long 6280 instruct storeL(memory mem, iRegL src) %{ 6281 match(Set mem (StoreL mem src)); 6282 ins_cost(MEMORY_REF_COST); 6283 format %{ "STX $src,$mem\t! long" %} 6284 opcode(Assembler::stx_op3); 6285 ins_encode(simple_form3_mem_reg( mem, src ) ); 6286 ins_pipe(istore_mem_reg); 6287 %} 6288 6289 instruct storeI0(memory mem, immI0 src) %{ 6290 match(Set mem (StoreI mem src)); 6291 ins_cost(MEMORY_REF_COST); 6292 6293 format %{ "STW $src,$mem" %} 6294 opcode(Assembler::stw_op3); 6295 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6296 ins_pipe(istore_mem_zero); 6297 %} 6298 6299 instruct storeL0(memory mem, immL0 src) %{ 6300 match(Set mem (StoreL mem src)); 6301 ins_cost(MEMORY_REF_COST); 6302 6303 format %{ "STX $src,$mem" %} 6304 opcode(Assembler::stx_op3); 6305 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6306 ins_pipe(istore_mem_zero); 6307 %} 6308 6309 // Store Integer from float register (used after fstoi) 6310 instruct storeI_Freg(memory mem, regF src) %{ 6311 match(Set mem (StoreI mem src)); 6312 ins_cost(MEMORY_REF_COST); 6313 6314 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} 6315 opcode(Assembler::stf_op3); 6316 ins_encode(simple_form3_mem_reg( mem, src ) ); 6317 ins_pipe(fstoreF_mem_reg); 6318 %} 6319 6320 // Store Pointer 6321 instruct storeP(memory dst, sp_ptr_RegP src) %{ 6322 match(Set dst (StoreP dst src)); 6323 ins_cost(MEMORY_REF_COST); 6324 6325 #ifndef _LP64 6326 format %{ "STW $src,$dst\t! ptr" %} 6327 opcode(Assembler::stw_op3, 0, REGP_OP); 6328 #else 6329 format %{ "STX $src,$dst\t! ptr" %} 6330 opcode(Assembler::stx_op3, 0, REGP_OP); 6331 #endif 6332 ins_encode( form3_mem_reg( dst, src ) ); 6333 ins_pipe(istore_mem_spORreg); 6334 %} 6335 6336 instruct storeP0(memory dst, immP0 src) %{ 6337 match(Set dst (StoreP dst src)); 6338 ins_cost(MEMORY_REF_COST); 6339 6340 #ifndef _LP64 6341 format %{ "STW $src,$dst\t! ptr" %} 6342 opcode(Assembler::stw_op3, 0, REGP_OP); 6343 #else 6344 format %{ "STX $src,$dst\t! ptr" %} 6345 opcode(Assembler::stx_op3, 0, REGP_OP); 6346 #endif 6347 ins_encode( form3_mem_reg( dst, R_G0 ) ); 6348 ins_pipe(istore_mem_zero); 6349 %} 6350 6351 // Store Compressed Pointer 6352 instruct storeN(memory dst, iRegN src) %{ 6353 match(Set dst (StoreN dst src)); 6354 ins_cost(MEMORY_REF_COST); 6355 size(4); 6356 6357 format %{ "STW $src,$dst\t! compressed ptr" %} 6358 ins_encode %{ 6359 Register base = as_Register($dst$$base); 6360 Register index = as_Register($dst$$index); 6361 Register src = $src$$Register; 6362 if (index != G0) { 6363 __ stw(src, base, index); 6364 } else { 6365 __ stw(src, base, $dst$$disp); 6366 } 6367 %} 6368 ins_pipe(istore_mem_spORreg); 6369 %} 6370 6371 instruct storeNKlass(memory dst, iRegN src) %{ 6372 match(Set dst (StoreNKlass dst src)); 6373 ins_cost(MEMORY_REF_COST); 6374 size(4); 6375 6376 format %{ "STW $src,$dst\t! compressed klass ptr" %} 6377 ins_encode %{ 6378 Register base = as_Register($dst$$base); 6379 Register index = as_Register($dst$$index); 6380 Register src = $src$$Register; 6381 if (index != G0) { 6382 __ stw(src, base, index); 6383 } else { 6384 __ stw(src, base, $dst$$disp); 6385 } 6386 %} 6387 ins_pipe(istore_mem_spORreg); 6388 %} 6389 6390 instruct storeN0(memory dst, immN0 src) %{ 6391 match(Set dst (StoreN dst src)); 6392 ins_cost(MEMORY_REF_COST); 6393 size(4); 6394 6395 format %{ "STW $src,$dst\t! compressed ptr" %} 6396 ins_encode %{ 6397 Register base = as_Register($dst$$base); 6398 Register index = as_Register($dst$$index); 6399 if (index != G0) { 6400 __ stw(0, base, index); 6401 } else { 6402 __ stw(0, base, $dst$$disp); 6403 } 6404 %} 6405 ins_pipe(istore_mem_zero); 6406 %} 6407 6408 // Store Double 6409 instruct storeD( memory mem, regD src) %{ 6410 match(Set mem (StoreD mem src)); 6411 ins_cost(MEMORY_REF_COST); 6412 6413 format %{ "STDF $src,$mem" %} 6414 opcode(Assembler::stdf_op3); 6415 ins_encode(simple_form3_mem_reg( mem, src ) ); 6416 ins_pipe(fstoreD_mem_reg); 6417 %} 6418 6419 instruct storeD0( memory mem, immD0 src) %{ 6420 match(Set mem (StoreD mem src)); 6421 ins_cost(MEMORY_REF_COST); 6422 6423 format %{ "STX $src,$mem" %} 6424 opcode(Assembler::stx_op3); 6425 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6426 ins_pipe(fstoreD_mem_zero); 6427 %} 6428 6429 // Store Float 6430 instruct storeF( memory mem, regF src) %{ 6431 match(Set mem (StoreF mem src)); 6432 ins_cost(MEMORY_REF_COST); 6433 6434 format %{ "STF $src,$mem" %} 6435 opcode(Assembler::stf_op3); 6436 ins_encode(simple_form3_mem_reg( mem, src ) ); 6437 ins_pipe(fstoreF_mem_reg); 6438 %} 6439 6440 instruct storeF0( memory mem, immF0 src) %{ 6441 match(Set mem (StoreF mem src)); 6442 ins_cost(MEMORY_REF_COST); 6443 6444 format %{ "STW $src,$mem\t! storeF0" %} 6445 opcode(Assembler::stw_op3); 6446 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6447 ins_pipe(fstoreF_mem_zero); 6448 %} 6449 6450 // Convert oop pointer into compressed form 6451 instruct encodeHeapOop(iRegN dst, iRegP src) %{ 6452 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 6453 match(Set dst (EncodeP src)); 6454 format %{ "encode_heap_oop $src, $dst" %} 6455 ins_encode %{ 6456 __ encode_heap_oop($src$$Register, $dst$$Register); 6457 %} 6458 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE); 6459 ins_pipe(ialu_reg); 6460 %} 6461 6462 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ 6463 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); 6464 match(Set dst (EncodeP src)); 6465 format %{ "encode_heap_oop_not_null $src, $dst" %} 6466 ins_encode %{ 6467 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); 6468 %} 6469 ins_pipe(ialu_reg); 6470 %} 6471 6472 instruct decodeHeapOop(iRegP dst, iRegN src) %{ 6473 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6474 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); 6475 match(Set dst (DecodeN src)); 6476 format %{ "decode_heap_oop $src, $dst" %} 6477 ins_encode %{ 6478 __ decode_heap_oop($src$$Register, $dst$$Register); 6479 %} 6480 ins_pipe(ialu_reg); 6481 %} 6482 6483 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ 6484 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6485 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); 6486 match(Set dst (DecodeN src)); 6487 format %{ "decode_heap_oop_not_null $src, $dst" %} 6488 ins_encode %{ 6489 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); 6490 %} 6491 ins_pipe(ialu_reg); 6492 %} 6493 6494 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{ 6495 match(Set dst (EncodePKlass src)); 6496 format %{ "encode_klass_not_null $src, $dst" %} 6497 ins_encode %{ 6498 __ encode_klass_not_null($src$$Register, $dst$$Register); 6499 %} 6500 ins_pipe(ialu_reg); 6501 %} 6502 6503 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{ 6504 match(Set dst (DecodeNKlass src)); 6505 format %{ "decode_klass_not_null $src, $dst" %} 6506 ins_encode %{ 6507 __ decode_klass_not_null($src$$Register, $dst$$Register); 6508 %} 6509 ins_pipe(ialu_reg); 6510 %} 6511 6512 //----------MemBar Instructions----------------------------------------------- 6513 // Memory barrier flavors 6514 6515 instruct membar_acquire() %{ 6516 match(MemBarAcquire); 6517 match(LoadFence); 6518 ins_cost(4*MEMORY_REF_COST); 6519 6520 size(0); 6521 format %{ "MEMBAR-acquire" %} 6522 ins_encode( enc_membar_acquire ); 6523 ins_pipe(long_memory_op); 6524 %} 6525 6526 instruct membar_acquire_lock() %{ 6527 match(MemBarAcquireLock); 6528 ins_cost(0); 6529 6530 size(0); 6531 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 6532 ins_encode( ); 6533 ins_pipe(empty); 6534 %} 6535 6536 instruct membar_release() %{ 6537 match(MemBarRelease); 6538 match(StoreFence); 6539 ins_cost(4*MEMORY_REF_COST); 6540 6541 size(0); 6542 format %{ "MEMBAR-release" %} 6543 ins_encode( enc_membar_release ); 6544 ins_pipe(long_memory_op); 6545 %} 6546 6547 instruct membar_release_lock() %{ 6548 match(MemBarReleaseLock); 6549 ins_cost(0); 6550 6551 size(0); 6552 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 6553 ins_encode( ); 6554 ins_pipe(empty); 6555 %} 6556 6557 instruct membar_volatile() %{ 6558 match(MemBarVolatile); 6559 ins_cost(4*MEMORY_REF_COST); 6560 6561 size(4); 6562 format %{ "MEMBAR-volatile" %} 6563 ins_encode( enc_membar_volatile ); 6564 ins_pipe(long_memory_op); 6565 %} 6566 6567 instruct unnecessary_membar_volatile() %{ 6568 match(MemBarVolatile); 6569 predicate(Matcher::post_store_load_barrier(n)); 6570 ins_cost(0); 6571 6572 size(0); 6573 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} 6574 ins_encode( ); 6575 ins_pipe(empty); 6576 %} 6577 6578 instruct membar_storestore() %{ 6579 match(MemBarStoreStore); 6580 ins_cost(0); 6581 6582 size(0); 6583 format %{ "!MEMBAR-storestore (empty encoding)" %} 6584 ins_encode( ); 6585 ins_pipe(empty); 6586 %} 6587 6588 //----------Register Move Instructions----------------------------------------- 6589 instruct roundDouble_nop(regD dst) %{ 6590 match(Set dst (RoundDouble dst)); 6591 ins_cost(0); 6592 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6593 ins_encode( ); 6594 ins_pipe(empty); 6595 %} 6596 6597 6598 instruct roundFloat_nop(regF dst) %{ 6599 match(Set dst (RoundFloat dst)); 6600 ins_cost(0); 6601 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6602 ins_encode( ); 6603 ins_pipe(empty); 6604 %} 6605 6606 6607 // Cast Index to Pointer for unsafe natives 6608 instruct castX2P(iRegX src, iRegP dst) %{ 6609 match(Set dst (CastX2P src)); 6610 6611 format %{ "MOV $src,$dst\t! IntX->Ptr" %} 6612 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6613 ins_pipe(ialu_reg); 6614 %} 6615 6616 // Cast Pointer to Index for unsafe natives 6617 instruct castP2X(iRegP src, iRegX dst) %{ 6618 match(Set dst (CastP2X src)); 6619 6620 format %{ "MOV $src,$dst\t! Ptr->IntX" %} 6621 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6622 ins_pipe(ialu_reg); 6623 %} 6624 6625 instruct stfSSD(stackSlotD stkSlot, regD src) %{ 6626 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6627 match(Set stkSlot src); // chain rule 6628 ins_cost(MEMORY_REF_COST); 6629 format %{ "STDF $src,$stkSlot\t!stk" %} 6630 opcode(Assembler::stdf_op3); 6631 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6632 ins_pipe(fstoreD_stk_reg); 6633 %} 6634 6635 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ 6636 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6637 match(Set dst stkSlot); // chain rule 6638 ins_cost(MEMORY_REF_COST); 6639 format %{ "LDDF $stkSlot,$dst\t!stk" %} 6640 opcode(Assembler::lddf_op3); 6641 ins_encode(simple_form3_mem_reg(stkSlot, dst)); 6642 ins_pipe(floadD_stk); 6643 %} 6644 6645 instruct stfSSF(stackSlotF stkSlot, regF src) %{ 6646 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6647 match(Set stkSlot src); // chain rule 6648 ins_cost(MEMORY_REF_COST); 6649 format %{ "STF $src,$stkSlot\t!stk" %} 6650 opcode(Assembler::stf_op3); 6651 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6652 ins_pipe(fstoreF_stk_reg); 6653 %} 6654 6655 //----------Conditional Move--------------------------------------------------- 6656 // Conditional move 6657 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ 6658 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6659 ins_cost(150); 6660 format %{ "MOV$cmp $pcc,$src,$dst" %} 6661 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6662 ins_pipe(ialu_reg); 6663 %} 6664 6665 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ 6666 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6667 ins_cost(140); 6668 format %{ "MOV$cmp $pcc,$src,$dst" %} 6669 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6670 ins_pipe(ialu_imm); 6671 %} 6672 6673 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ 6674 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6675 ins_cost(150); 6676 size(4); 6677 format %{ "MOV$cmp $icc,$src,$dst" %} 6678 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6679 ins_pipe(ialu_reg); 6680 %} 6681 6682 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ 6683 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6684 ins_cost(140); 6685 size(4); 6686 format %{ "MOV$cmp $icc,$src,$dst" %} 6687 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6688 ins_pipe(ialu_imm); 6689 %} 6690 6691 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ 6692 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6693 ins_cost(150); 6694 size(4); 6695 format %{ "MOV$cmp $icc,$src,$dst" %} 6696 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6697 ins_pipe(ialu_reg); 6698 %} 6699 6700 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ 6701 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6702 ins_cost(140); 6703 size(4); 6704 format %{ "MOV$cmp $icc,$src,$dst" %} 6705 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6706 ins_pipe(ialu_imm); 6707 %} 6708 6709 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ 6710 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6711 ins_cost(150); 6712 size(4); 6713 format %{ "MOV$cmp $fcc,$src,$dst" %} 6714 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6715 ins_pipe(ialu_reg); 6716 %} 6717 6718 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ 6719 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6720 ins_cost(140); 6721 size(4); 6722 format %{ "MOV$cmp $fcc,$src,$dst" %} 6723 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6724 ins_pipe(ialu_imm); 6725 %} 6726 6727 // Conditional move for RegN. Only cmov(reg,reg). 6728 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ 6729 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); 6730 ins_cost(150); 6731 format %{ "MOV$cmp $pcc,$src,$dst" %} 6732 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6733 ins_pipe(ialu_reg); 6734 %} 6735 6736 // This instruction also works with CmpN so we don't need cmovNN_reg. 6737 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ 6738 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6739 ins_cost(150); 6740 size(4); 6741 format %{ "MOV$cmp $icc,$src,$dst" %} 6742 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6743 ins_pipe(ialu_reg); 6744 %} 6745 6746 // This instruction also works with CmpN so we don't need cmovNN_reg. 6747 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ 6748 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6749 ins_cost(150); 6750 size(4); 6751 format %{ "MOV$cmp $icc,$src,$dst" %} 6752 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6753 ins_pipe(ialu_reg); 6754 %} 6755 6756 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ 6757 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); 6758 ins_cost(150); 6759 size(4); 6760 format %{ "MOV$cmp $fcc,$src,$dst" %} 6761 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6762 ins_pipe(ialu_reg); 6763 %} 6764 6765 // Conditional move 6766 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ 6767 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6768 ins_cost(150); 6769 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6770 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6771 ins_pipe(ialu_reg); 6772 %} 6773 6774 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ 6775 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6776 ins_cost(140); 6777 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6778 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6779 ins_pipe(ialu_imm); 6780 %} 6781 6782 // This instruction also works with CmpN so we don't need cmovPN_reg. 6783 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ 6784 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6785 ins_cost(150); 6786 6787 size(4); 6788 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6789 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6790 ins_pipe(ialu_reg); 6791 %} 6792 6793 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ 6794 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6795 ins_cost(150); 6796 6797 size(4); 6798 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6799 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6800 ins_pipe(ialu_reg); 6801 %} 6802 6803 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ 6804 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6805 ins_cost(140); 6806 6807 size(4); 6808 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6809 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6810 ins_pipe(ialu_imm); 6811 %} 6812 6813 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ 6814 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6815 ins_cost(140); 6816 6817 size(4); 6818 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6819 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6820 ins_pipe(ialu_imm); 6821 %} 6822 6823 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ 6824 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6825 ins_cost(150); 6826 size(4); 6827 format %{ "MOV$cmp $fcc,$src,$dst" %} 6828 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6829 ins_pipe(ialu_imm); 6830 %} 6831 6832 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ 6833 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6834 ins_cost(140); 6835 size(4); 6836 format %{ "MOV$cmp $fcc,$src,$dst" %} 6837 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6838 ins_pipe(ialu_imm); 6839 %} 6840 6841 // Conditional move 6842 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ 6843 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); 6844 ins_cost(150); 6845 opcode(0x101); 6846 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6847 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6848 ins_pipe(int_conditional_float_move); 6849 %} 6850 6851 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ 6852 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6853 ins_cost(150); 6854 6855 size(4); 6856 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6857 opcode(0x101); 6858 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6859 ins_pipe(int_conditional_float_move); 6860 %} 6861 6862 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ 6863 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6864 ins_cost(150); 6865 6866 size(4); 6867 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6868 opcode(0x101); 6869 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6870 ins_pipe(int_conditional_float_move); 6871 %} 6872 6873 // Conditional move, 6874 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ 6875 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); 6876 ins_cost(150); 6877 size(4); 6878 format %{ "FMOVF$cmp $fcc,$src,$dst" %} 6879 opcode(0x1); 6880 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6881 ins_pipe(int_conditional_double_move); 6882 %} 6883 6884 // Conditional move 6885 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ 6886 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); 6887 ins_cost(150); 6888 size(4); 6889 opcode(0x102); 6890 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6891 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6892 ins_pipe(int_conditional_double_move); 6893 %} 6894 6895 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ 6896 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6897 ins_cost(150); 6898 6899 size(4); 6900 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6901 opcode(0x102); 6902 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6903 ins_pipe(int_conditional_double_move); 6904 %} 6905 6906 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ 6907 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6908 ins_cost(150); 6909 6910 size(4); 6911 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6912 opcode(0x102); 6913 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6914 ins_pipe(int_conditional_double_move); 6915 %} 6916 6917 // Conditional move, 6918 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ 6919 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); 6920 ins_cost(150); 6921 size(4); 6922 format %{ "FMOVD$cmp $fcc,$src,$dst" %} 6923 opcode(0x2); 6924 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6925 ins_pipe(int_conditional_double_move); 6926 %} 6927 6928 // Conditional move 6929 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ 6930 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6931 ins_cost(150); 6932 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6933 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6934 ins_pipe(ialu_reg); 6935 %} 6936 6937 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ 6938 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6939 ins_cost(140); 6940 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6941 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6942 ins_pipe(ialu_imm); 6943 %} 6944 6945 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ 6946 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6947 ins_cost(150); 6948 6949 size(4); 6950 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6951 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6952 ins_pipe(ialu_reg); 6953 %} 6954 6955 6956 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ 6957 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6958 ins_cost(150); 6959 6960 size(4); 6961 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6962 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6963 ins_pipe(ialu_reg); 6964 %} 6965 6966 6967 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ 6968 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); 6969 ins_cost(150); 6970 6971 size(4); 6972 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} 6973 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6974 ins_pipe(ialu_reg); 6975 %} 6976 6977 6978 6979 //----------OS and Locking Instructions---------------------------------------- 6980 6981 // This name is KNOWN by the ADLC and cannot be changed. 6982 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type 6983 // for this guy. 6984 instruct tlsLoadP(g2RegP dst) %{ 6985 match(Set dst (ThreadLocal)); 6986 6987 size(0); 6988 ins_cost(0); 6989 format %{ "# TLS is in G2" %} 6990 ins_encode( /*empty encoding*/ ); 6991 ins_pipe(ialu_none); 6992 %} 6993 6994 instruct checkCastPP( iRegP dst ) %{ 6995 match(Set dst (CheckCastPP dst)); 6996 6997 size(0); 6998 format %{ "# checkcastPP of $dst" %} 6999 ins_encode( /*empty encoding*/ ); 7000 ins_pipe(empty); 7001 %} 7002 7003 7004 instruct castPP( iRegP dst ) %{ 7005 match(Set dst (CastPP dst)); 7006 format %{ "# castPP of $dst" %} 7007 ins_encode( /*empty encoding*/ ); 7008 ins_pipe(empty); 7009 %} 7010 7011 instruct castII( iRegI dst ) %{ 7012 match(Set dst (CastII dst)); 7013 format %{ "# castII of $dst" %} 7014 ins_encode( /*empty encoding*/ ); 7015 ins_cost(0); 7016 ins_pipe(empty); 7017 %} 7018 7019 //----------Arithmetic Instructions-------------------------------------------- 7020 // Addition Instructions 7021 // Register Addition 7022 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7023 match(Set dst (AddI src1 src2)); 7024 7025 size(4); 7026 format %{ "ADD $src1,$src2,$dst" %} 7027 ins_encode %{ 7028 __ add($src1$$Register, $src2$$Register, $dst$$Register); 7029 %} 7030 ins_pipe(ialu_reg_reg); 7031 %} 7032 7033 // Immediate Addition 7034 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7035 match(Set dst (AddI src1 src2)); 7036 7037 size(4); 7038 format %{ "ADD $src1,$src2,$dst" %} 7039 opcode(Assembler::add_op3, Assembler::arith_op); 7040 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7041 ins_pipe(ialu_reg_imm); 7042 %} 7043 7044 // Pointer Register Addition 7045 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ 7046 match(Set dst (AddP src1 src2)); 7047 7048 size(4); 7049 format %{ "ADD $src1,$src2,$dst" %} 7050 opcode(Assembler::add_op3, Assembler::arith_op); 7051 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7052 ins_pipe(ialu_reg_reg); 7053 %} 7054 7055 // Pointer Immediate Addition 7056 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ 7057 match(Set dst (AddP src1 src2)); 7058 7059 size(4); 7060 format %{ "ADD $src1,$src2,$dst" %} 7061 opcode(Assembler::add_op3, Assembler::arith_op); 7062 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7063 ins_pipe(ialu_reg_imm); 7064 %} 7065 7066 // Long Addition 7067 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7068 match(Set dst (AddL src1 src2)); 7069 7070 size(4); 7071 format %{ "ADD $src1,$src2,$dst\t! long" %} 7072 opcode(Assembler::add_op3, Assembler::arith_op); 7073 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7074 ins_pipe(ialu_reg_reg); 7075 %} 7076 7077 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7078 match(Set dst (AddL src1 con)); 7079 7080 size(4); 7081 format %{ "ADD $src1,$con,$dst" %} 7082 opcode(Assembler::add_op3, Assembler::arith_op); 7083 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7084 ins_pipe(ialu_reg_imm); 7085 %} 7086 7087 //----------Conditional_store-------------------------------------------------- 7088 // Conditional-store of the updated heap-top. 7089 // Used during allocation of the shared heap. 7090 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 7091 7092 // LoadP-locked. Same as a regular pointer load when used with a compare-swap 7093 instruct loadPLocked(iRegP dst, memory mem) %{ 7094 match(Set dst (LoadPLocked mem)); 7095 ins_cost(MEMORY_REF_COST); 7096 7097 #ifndef _LP64 7098 format %{ "LDUW $mem,$dst\t! ptr" %} 7099 opcode(Assembler::lduw_op3, 0, REGP_OP); 7100 #else 7101 format %{ "LDX $mem,$dst\t! ptr" %} 7102 opcode(Assembler::ldx_op3, 0, REGP_OP); 7103 #endif 7104 ins_encode( form3_mem_reg( mem, dst ) ); 7105 ins_pipe(iload_mem); 7106 %} 7107 7108 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ 7109 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); 7110 effect( KILL newval ); 7111 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" 7112 "CMP R_G3,$oldval\t\t! See if we made progress" %} 7113 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); 7114 ins_pipe( long_memory_op ); 7115 %} 7116 7117 // Conditional-store of an int value. 7118 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ 7119 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); 7120 effect( KILL newval ); 7121 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7122 "CMP $oldval,$newval\t\t! See if we made progress" %} 7123 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7124 ins_pipe( long_memory_op ); 7125 %} 7126 7127 // Conditional-store of a long value. 7128 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ 7129 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); 7130 effect( KILL newval ); 7131 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7132 "CMP $oldval,$newval\t\t! See if we made progress" %} 7133 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7134 ins_pipe( long_memory_op ); 7135 %} 7136 7137 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 7138 7139 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7140 predicate(VM_Version::supports_cx8()); 7141 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 7142 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval))); 7143 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7144 format %{ 7145 "MOV $newval,O7\n\t" 7146 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7147 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7148 "MOV 1,$res\n\t" 7149 "MOVne xcc,R_G0,$res" 7150 %} 7151 ins_encode( enc_casx(mem_ptr, oldval, newval), 7152 enc_lflags_ne_to_boolean(res) ); 7153 ins_pipe( long_memory_op ); 7154 %} 7155 7156 7157 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7158 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 7159 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval))); 7160 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7161 format %{ 7162 "MOV $newval,O7\n\t" 7163 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7164 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7165 "MOV 1,$res\n\t" 7166 "MOVne icc,R_G0,$res" 7167 %} 7168 ins_encode( enc_casi(mem_ptr, oldval, newval), 7169 enc_iflags_ne_to_boolean(res) ); 7170 ins_pipe( long_memory_op ); 7171 %} 7172 7173 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7174 #ifdef _LP64 7175 predicate(VM_Version::supports_cx8()); 7176 #endif 7177 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 7178 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval))); 7179 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7180 format %{ 7181 "MOV $newval,O7\n\t" 7182 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7183 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7184 "MOV 1,$res\n\t" 7185 "MOVne xcc,R_G0,$res" 7186 %} 7187 #ifdef _LP64 7188 ins_encode( enc_casx(mem_ptr, oldval, newval), 7189 enc_lflags_ne_to_boolean(res) ); 7190 #else 7191 ins_encode( enc_casi(mem_ptr, oldval, newval), 7192 enc_iflags_ne_to_boolean(res) ); 7193 #endif 7194 ins_pipe( long_memory_op ); 7195 %} 7196 7197 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7198 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 7199 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval))); 7200 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7201 format %{ 7202 "MOV $newval,O7\n\t" 7203 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7204 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7205 "MOV 1,$res\n\t" 7206 "MOVne icc,R_G0,$res" 7207 %} 7208 ins_encode( enc_casi(mem_ptr, oldval, newval), 7209 enc_iflags_ne_to_boolean(res) ); 7210 ins_pipe( long_memory_op ); 7211 %} 7212 7213 instruct compareAndExchangeI(iRegP mem_ptr, iRegI oldval, iRegI newval) 7214 %{ 7215 match(Set newval (CompareAndExchangeI mem_ptr (Binary oldval newval))); 7216 effect( USE mem_ptr ); 7217 7218 format %{ 7219 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 7220 %} 7221 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) ); 7222 ins_pipe( long_memory_op ); 7223 %} 7224 7225 instruct compareAndExchangeL(iRegP mem_ptr, iRegL oldval, iRegL newval) 7226 %{ 7227 match(Set newval (CompareAndExchangeL mem_ptr (Binary oldval newval))); 7228 effect( USE mem_ptr ); 7229 7230 format %{ 7231 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 7232 %} 7233 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) ); 7234 ins_pipe( long_memory_op ); 7235 %} 7236 7237 instruct compareAndExchangeP(iRegP mem_ptr, iRegP oldval, iRegP newval) 7238 %{ 7239 match(Set newval (CompareAndExchangeP mem_ptr (Binary oldval newval))); 7240 effect( USE mem_ptr ); 7241 7242 format %{ 7243 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 7244 %} 7245 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) ); 7246 ins_pipe( long_memory_op ); 7247 %} 7248 7249 instruct compareAndExchangeN(iRegP mem_ptr, iRegN oldval, iRegN newval) 7250 %{ 7251 match(Set newval (CompareAndExchangeN mem_ptr (Binary oldval newval))); 7252 effect( USE mem_ptr ); 7253 7254 format %{ 7255 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 7256 %} 7257 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) ); 7258 ins_pipe( long_memory_op ); 7259 %} 7260 7261 instruct xchgI( memory mem, iRegI newval) %{ 7262 match(Set newval (GetAndSetI mem newval)); 7263 format %{ "SWAP [$mem],$newval" %} 7264 size(4); 7265 ins_encode %{ 7266 __ swap($mem$$Address, $newval$$Register); 7267 %} 7268 ins_pipe( long_memory_op ); 7269 %} 7270 7271 #ifndef _LP64 7272 instruct xchgP( memory mem, iRegP newval) %{ 7273 match(Set newval (GetAndSetP mem newval)); 7274 format %{ "SWAP [$mem],$newval" %} 7275 size(4); 7276 ins_encode %{ 7277 __ swap($mem$$Address, $newval$$Register); 7278 %} 7279 ins_pipe( long_memory_op ); 7280 %} 7281 #endif 7282 7283 instruct xchgN( memory mem, iRegN newval) %{ 7284 match(Set newval (GetAndSetN mem newval)); 7285 format %{ "SWAP [$mem],$newval" %} 7286 size(4); 7287 ins_encode %{ 7288 __ swap($mem$$Address, $newval$$Register); 7289 %} 7290 ins_pipe( long_memory_op ); 7291 %} 7292 7293 //--------------------- 7294 // Subtraction Instructions 7295 // Register Subtraction 7296 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7297 match(Set dst (SubI src1 src2)); 7298 7299 size(4); 7300 format %{ "SUB $src1,$src2,$dst" %} 7301 opcode(Assembler::sub_op3, Assembler::arith_op); 7302 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7303 ins_pipe(ialu_reg_reg); 7304 %} 7305 7306 // Immediate Subtraction 7307 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7308 match(Set dst (SubI src1 src2)); 7309 7310 size(4); 7311 format %{ "SUB $src1,$src2,$dst" %} 7312 opcode(Assembler::sub_op3, Assembler::arith_op); 7313 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7314 ins_pipe(ialu_reg_imm); 7315 %} 7316 7317 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 7318 match(Set dst (SubI zero src2)); 7319 7320 size(4); 7321 format %{ "NEG $src2,$dst" %} 7322 opcode(Assembler::sub_op3, Assembler::arith_op); 7323 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7324 ins_pipe(ialu_zero_reg); 7325 %} 7326 7327 // Long subtraction 7328 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7329 match(Set dst (SubL src1 src2)); 7330 7331 size(4); 7332 format %{ "SUB $src1,$src2,$dst\t! long" %} 7333 opcode(Assembler::sub_op3, Assembler::arith_op); 7334 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7335 ins_pipe(ialu_reg_reg); 7336 %} 7337 7338 // Immediate Subtraction 7339 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7340 match(Set dst (SubL src1 con)); 7341 7342 size(4); 7343 format %{ "SUB $src1,$con,$dst\t! long" %} 7344 opcode(Assembler::sub_op3, Assembler::arith_op); 7345 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7346 ins_pipe(ialu_reg_imm); 7347 %} 7348 7349 // Long negation 7350 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ 7351 match(Set dst (SubL zero src2)); 7352 7353 size(4); 7354 format %{ "NEG $src2,$dst\t! long" %} 7355 opcode(Assembler::sub_op3, Assembler::arith_op); 7356 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7357 ins_pipe(ialu_zero_reg); 7358 %} 7359 7360 // Multiplication Instructions 7361 // Integer Multiplication 7362 // Register Multiplication 7363 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7364 match(Set dst (MulI src1 src2)); 7365 7366 size(4); 7367 format %{ "MULX $src1,$src2,$dst" %} 7368 opcode(Assembler::mulx_op3, Assembler::arith_op); 7369 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7370 ins_pipe(imul_reg_reg); 7371 %} 7372 7373 // Immediate Multiplication 7374 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7375 match(Set dst (MulI src1 src2)); 7376 7377 size(4); 7378 format %{ "MULX $src1,$src2,$dst" %} 7379 opcode(Assembler::mulx_op3, Assembler::arith_op); 7380 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7381 ins_pipe(imul_reg_imm); 7382 %} 7383 7384 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7385 match(Set dst (MulL src1 src2)); 7386 ins_cost(DEFAULT_COST * 5); 7387 size(4); 7388 format %{ "MULX $src1,$src2,$dst\t! long" %} 7389 opcode(Assembler::mulx_op3, Assembler::arith_op); 7390 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7391 ins_pipe(mulL_reg_reg); 7392 %} 7393 7394 // Immediate Multiplication 7395 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7396 match(Set dst (MulL src1 src2)); 7397 ins_cost(DEFAULT_COST * 5); 7398 size(4); 7399 format %{ "MULX $src1,$src2,$dst" %} 7400 opcode(Assembler::mulx_op3, Assembler::arith_op); 7401 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7402 ins_pipe(mulL_reg_imm); 7403 %} 7404 7405 // Integer Division 7406 // Register Division 7407 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ 7408 match(Set dst (DivI src1 src2)); 7409 ins_cost((2+71)*DEFAULT_COST); 7410 7411 format %{ "SRA $src2,0,$src2\n\t" 7412 "SRA $src1,0,$src1\n\t" 7413 "SDIVX $src1,$src2,$dst" %} 7414 ins_encode( idiv_reg( src1, src2, dst ) ); 7415 ins_pipe(sdiv_reg_reg); 7416 %} 7417 7418 // Immediate Division 7419 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ 7420 match(Set dst (DivI src1 src2)); 7421 ins_cost((2+71)*DEFAULT_COST); 7422 7423 format %{ "SRA $src1,0,$src1\n\t" 7424 "SDIVX $src1,$src2,$dst" %} 7425 ins_encode( idiv_imm( src1, src2, dst ) ); 7426 ins_pipe(sdiv_reg_imm); 7427 %} 7428 7429 //----------Div-By-10-Expansion------------------------------------------------ 7430 // Extract hi bits of a 32x32->64 bit multiply. 7431 // Expand rule only, not matched 7432 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ 7433 effect( DEF dst, USE src1, USE src2 ); 7434 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" 7435 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} 7436 ins_encode( enc_mul_hi(dst,src1,src2)); 7437 ins_pipe(sdiv_reg_reg); 7438 %} 7439 7440 // Magic constant, reciprocal of 10 7441 instruct loadConI_x66666667(iRegIsafe dst) %{ 7442 effect( DEF dst ); 7443 7444 size(8); 7445 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} 7446 ins_encode( Set32(0x66666667, dst) ); 7447 ins_pipe(ialu_hi_lo_reg); 7448 %} 7449 7450 // Register Shift Right Arithmetic Long by 32-63 7451 instruct sra_31( iRegI dst, iRegI src ) %{ 7452 effect( DEF dst, USE src ); 7453 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} 7454 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); 7455 ins_pipe(ialu_reg_reg); 7456 %} 7457 7458 // Arithmetic Shift Right by 8-bit immediate 7459 instruct sra_reg_2( iRegI dst, iRegI src ) %{ 7460 effect( DEF dst, USE src ); 7461 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} 7462 opcode(Assembler::sra_op3, Assembler::arith_op); 7463 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); 7464 ins_pipe(ialu_reg_imm); 7465 %} 7466 7467 // Integer DIV with 10 7468 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ 7469 match(Set dst (DivI src div)); 7470 ins_cost((6+6)*DEFAULT_COST); 7471 expand %{ 7472 iRegIsafe tmp1; // Killed temps; 7473 iRegIsafe tmp2; // Killed temps; 7474 iRegI tmp3; // Killed temps; 7475 iRegI tmp4; // Killed temps; 7476 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 7477 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 7478 sra_31( tmp3, src ); // SRA src,31 -> tmp3 7479 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 7480 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst 7481 %} 7482 %} 7483 7484 // Register Long Division 7485 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7486 match(Set dst (DivL src1 src2)); 7487 ins_cost(DEFAULT_COST*71); 7488 size(4); 7489 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7490 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7491 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7492 ins_pipe(divL_reg_reg); 7493 %} 7494 7495 // Register Long Division 7496 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7497 match(Set dst (DivL src1 src2)); 7498 ins_cost(DEFAULT_COST*71); 7499 size(4); 7500 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7501 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7502 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7503 ins_pipe(divL_reg_imm); 7504 %} 7505 7506 // Integer Remainder 7507 // Register Remainder 7508 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ 7509 match(Set dst (ModI src1 src2)); 7510 effect( KILL ccr, KILL temp); 7511 7512 format %{ "SREM $src1,$src2,$dst" %} 7513 ins_encode( irem_reg(src1, src2, dst, temp) ); 7514 ins_pipe(sdiv_reg_reg); 7515 %} 7516 7517 // Immediate Remainder 7518 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ 7519 match(Set dst (ModI src1 src2)); 7520 effect( KILL ccr, KILL temp); 7521 7522 format %{ "SREM $src1,$src2,$dst" %} 7523 ins_encode( irem_imm(src1, src2, dst, temp) ); 7524 ins_pipe(sdiv_reg_imm); 7525 %} 7526 7527 // Register Long Remainder 7528 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7529 effect(DEF dst, USE src1, USE src2); 7530 size(4); 7531 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7532 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7533 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7534 ins_pipe(divL_reg_reg); 7535 %} 7536 7537 // Register Long Division 7538 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7539 effect(DEF dst, USE src1, USE src2); 7540 size(4); 7541 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7542 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7543 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7544 ins_pipe(divL_reg_imm); 7545 %} 7546 7547 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7548 effect(DEF dst, USE src1, USE src2); 7549 size(4); 7550 format %{ "MULX $src1,$src2,$dst\t! long" %} 7551 opcode(Assembler::mulx_op3, Assembler::arith_op); 7552 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7553 ins_pipe(mulL_reg_reg); 7554 %} 7555 7556 // Immediate Multiplication 7557 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7558 effect(DEF dst, USE src1, USE src2); 7559 size(4); 7560 format %{ "MULX $src1,$src2,$dst" %} 7561 opcode(Assembler::mulx_op3, Assembler::arith_op); 7562 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7563 ins_pipe(mulL_reg_imm); 7564 %} 7565 7566 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7567 effect(DEF dst, USE src1, USE src2); 7568 size(4); 7569 format %{ "SUB $src1,$src2,$dst\t! long" %} 7570 opcode(Assembler::sub_op3, Assembler::arith_op); 7571 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7572 ins_pipe(ialu_reg_reg); 7573 %} 7574 7575 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 7576 effect(DEF dst, USE src1, USE src2); 7577 size(4); 7578 format %{ "SUB $src1,$src2,$dst\t! long" %} 7579 opcode(Assembler::sub_op3, Assembler::arith_op); 7580 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7581 ins_pipe(ialu_reg_reg); 7582 %} 7583 7584 // Register Long Remainder 7585 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7586 match(Set dst (ModL src1 src2)); 7587 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7588 expand %{ 7589 iRegL tmp1; 7590 iRegL tmp2; 7591 divL_reg_reg_1(tmp1, src1, src2); 7592 mulL_reg_reg_1(tmp2, tmp1, src2); 7593 subL_reg_reg_1(dst, src1, tmp2); 7594 %} 7595 %} 7596 7597 // Register Long Remainder 7598 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7599 match(Set dst (ModL src1 src2)); 7600 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7601 expand %{ 7602 iRegL tmp1; 7603 iRegL tmp2; 7604 divL_reg_imm13_1(tmp1, src1, src2); 7605 mulL_reg_imm13_1(tmp2, tmp1, src2); 7606 subL_reg_reg_2 (dst, src1, tmp2); 7607 %} 7608 %} 7609 7610 // Integer Shift Instructions 7611 // Register Shift Left 7612 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7613 match(Set dst (LShiftI src1 src2)); 7614 7615 size(4); 7616 format %{ "SLL $src1,$src2,$dst" %} 7617 opcode(Assembler::sll_op3, Assembler::arith_op); 7618 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7619 ins_pipe(ialu_reg_reg); 7620 %} 7621 7622 // Register Shift Left Immediate 7623 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7624 match(Set dst (LShiftI src1 src2)); 7625 7626 size(4); 7627 format %{ "SLL $src1,$src2,$dst" %} 7628 opcode(Assembler::sll_op3, Assembler::arith_op); 7629 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7630 ins_pipe(ialu_reg_imm); 7631 %} 7632 7633 // Register Shift Left 7634 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7635 match(Set dst (LShiftL src1 src2)); 7636 7637 size(4); 7638 format %{ "SLLX $src1,$src2,$dst" %} 7639 opcode(Assembler::sllx_op3, Assembler::arith_op); 7640 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7641 ins_pipe(ialu_reg_reg); 7642 %} 7643 7644 // Register Shift Left Immediate 7645 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7646 match(Set dst (LShiftL src1 src2)); 7647 7648 size(4); 7649 format %{ "SLLX $src1,$src2,$dst" %} 7650 opcode(Assembler::sllx_op3, Assembler::arith_op); 7651 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7652 ins_pipe(ialu_reg_imm); 7653 %} 7654 7655 // Register Arithmetic Shift Right 7656 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7657 match(Set dst (RShiftI src1 src2)); 7658 size(4); 7659 format %{ "SRA $src1,$src2,$dst" %} 7660 opcode(Assembler::sra_op3, Assembler::arith_op); 7661 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7662 ins_pipe(ialu_reg_reg); 7663 %} 7664 7665 // Register Arithmetic Shift Right Immediate 7666 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7667 match(Set dst (RShiftI src1 src2)); 7668 7669 size(4); 7670 format %{ "SRA $src1,$src2,$dst" %} 7671 opcode(Assembler::sra_op3, Assembler::arith_op); 7672 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7673 ins_pipe(ialu_reg_imm); 7674 %} 7675 7676 // Register Shift Right Arithmatic Long 7677 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7678 match(Set dst (RShiftL src1 src2)); 7679 7680 size(4); 7681 format %{ "SRAX $src1,$src2,$dst" %} 7682 opcode(Assembler::srax_op3, Assembler::arith_op); 7683 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7684 ins_pipe(ialu_reg_reg); 7685 %} 7686 7687 // Register Shift Left Immediate 7688 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7689 match(Set dst (RShiftL src1 src2)); 7690 7691 size(4); 7692 format %{ "SRAX $src1,$src2,$dst" %} 7693 opcode(Assembler::srax_op3, Assembler::arith_op); 7694 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7695 ins_pipe(ialu_reg_imm); 7696 %} 7697 7698 // Register Shift Right 7699 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7700 match(Set dst (URShiftI src1 src2)); 7701 7702 size(4); 7703 format %{ "SRL $src1,$src2,$dst" %} 7704 opcode(Assembler::srl_op3, Assembler::arith_op); 7705 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7706 ins_pipe(ialu_reg_reg); 7707 %} 7708 7709 // Register Shift Right Immediate 7710 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7711 match(Set dst (URShiftI src1 src2)); 7712 7713 size(4); 7714 format %{ "SRL $src1,$src2,$dst" %} 7715 opcode(Assembler::srl_op3, Assembler::arith_op); 7716 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7717 ins_pipe(ialu_reg_imm); 7718 %} 7719 7720 // Register Shift Right 7721 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7722 match(Set dst (URShiftL src1 src2)); 7723 7724 size(4); 7725 format %{ "SRLX $src1,$src2,$dst" %} 7726 opcode(Assembler::srlx_op3, Assembler::arith_op); 7727 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7728 ins_pipe(ialu_reg_reg); 7729 %} 7730 7731 // Register Shift Right Immediate 7732 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7733 match(Set dst (URShiftL src1 src2)); 7734 7735 size(4); 7736 format %{ "SRLX $src1,$src2,$dst" %} 7737 opcode(Assembler::srlx_op3, Assembler::arith_op); 7738 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7739 ins_pipe(ialu_reg_imm); 7740 %} 7741 7742 // Register Shift Right Immediate with a CastP2X 7743 #ifdef _LP64 7744 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ 7745 match(Set dst (URShiftL (CastP2X src1) src2)); 7746 size(4); 7747 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} 7748 opcode(Assembler::srlx_op3, Assembler::arith_op); 7749 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7750 ins_pipe(ialu_reg_imm); 7751 %} 7752 #else 7753 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ 7754 match(Set dst (URShiftI (CastP2X src1) src2)); 7755 size(4); 7756 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} 7757 opcode(Assembler::srl_op3, Assembler::arith_op); 7758 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7759 ins_pipe(ialu_reg_imm); 7760 %} 7761 #endif 7762 7763 7764 //----------Floating Point Arithmetic Instructions----------------------------- 7765 7766 // Add float single precision 7767 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 7768 match(Set dst (AddF src1 src2)); 7769 7770 size(4); 7771 format %{ "FADDS $src1,$src2,$dst" %} 7772 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); 7773 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7774 ins_pipe(faddF_reg_reg); 7775 %} 7776 7777 // Add float double precision 7778 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 7779 match(Set dst (AddD src1 src2)); 7780 7781 size(4); 7782 format %{ "FADDD $src1,$src2,$dst" %} 7783 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 7784 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7785 ins_pipe(faddD_reg_reg); 7786 %} 7787 7788 // Sub float single precision 7789 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 7790 match(Set dst (SubF src1 src2)); 7791 7792 size(4); 7793 format %{ "FSUBS $src1,$src2,$dst" %} 7794 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); 7795 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7796 ins_pipe(faddF_reg_reg); 7797 %} 7798 7799 // Sub float double precision 7800 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 7801 match(Set dst (SubD src1 src2)); 7802 7803 size(4); 7804 format %{ "FSUBD $src1,$src2,$dst" %} 7805 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 7806 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7807 ins_pipe(faddD_reg_reg); 7808 %} 7809 7810 // Mul float single precision 7811 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 7812 match(Set dst (MulF src1 src2)); 7813 7814 size(4); 7815 format %{ "FMULS $src1,$src2,$dst" %} 7816 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); 7817 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7818 ins_pipe(fmulF_reg_reg); 7819 %} 7820 7821 // Mul float double precision 7822 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 7823 match(Set dst (MulD src1 src2)); 7824 7825 size(4); 7826 format %{ "FMULD $src1,$src2,$dst" %} 7827 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 7828 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7829 ins_pipe(fmulD_reg_reg); 7830 %} 7831 7832 // Div float single precision 7833 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 7834 match(Set dst (DivF src1 src2)); 7835 7836 size(4); 7837 format %{ "FDIVS $src1,$src2,$dst" %} 7838 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); 7839 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7840 ins_pipe(fdivF_reg_reg); 7841 %} 7842 7843 // Div float double precision 7844 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 7845 match(Set dst (DivD src1 src2)); 7846 7847 size(4); 7848 format %{ "FDIVD $src1,$src2,$dst" %} 7849 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); 7850 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7851 ins_pipe(fdivD_reg_reg); 7852 %} 7853 7854 // Absolute float double precision 7855 instruct absD_reg(regD dst, regD src) %{ 7856 match(Set dst (AbsD src)); 7857 7858 format %{ "FABSd $src,$dst" %} 7859 ins_encode(fabsd(dst, src)); 7860 ins_pipe(faddD_reg); 7861 %} 7862 7863 // Absolute float single precision 7864 instruct absF_reg(regF dst, regF src) %{ 7865 match(Set dst (AbsF src)); 7866 7867 format %{ "FABSs $src,$dst" %} 7868 ins_encode(fabss(dst, src)); 7869 ins_pipe(faddF_reg); 7870 %} 7871 7872 instruct negF_reg(regF dst, regF src) %{ 7873 match(Set dst (NegF src)); 7874 7875 size(4); 7876 format %{ "FNEGs $src,$dst" %} 7877 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); 7878 ins_encode(form3_opf_rs2F_rdF(src, dst)); 7879 ins_pipe(faddF_reg); 7880 %} 7881 7882 instruct negD_reg(regD dst, regD src) %{ 7883 match(Set dst (NegD src)); 7884 7885 format %{ "FNEGd $src,$dst" %} 7886 ins_encode(fnegd(dst, src)); 7887 ins_pipe(faddD_reg); 7888 %} 7889 7890 // Sqrt float double precision 7891 instruct sqrtF_reg_reg(regF dst, regF src) %{ 7892 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7893 7894 size(4); 7895 format %{ "FSQRTS $src,$dst" %} 7896 ins_encode(fsqrts(dst, src)); 7897 ins_pipe(fdivF_reg_reg); 7898 %} 7899 7900 // Sqrt float double precision 7901 instruct sqrtD_reg_reg(regD dst, regD src) %{ 7902 match(Set dst (SqrtD src)); 7903 7904 size(4); 7905 format %{ "FSQRTD $src,$dst" %} 7906 ins_encode(fsqrtd(dst, src)); 7907 ins_pipe(fdivD_reg_reg); 7908 %} 7909 7910 //----------Logical Instructions----------------------------------------------- 7911 // And Instructions 7912 // Register And 7913 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7914 match(Set dst (AndI src1 src2)); 7915 7916 size(4); 7917 format %{ "AND $src1,$src2,$dst" %} 7918 opcode(Assembler::and_op3, Assembler::arith_op); 7919 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7920 ins_pipe(ialu_reg_reg); 7921 %} 7922 7923 // Immediate And 7924 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7925 match(Set dst (AndI src1 src2)); 7926 7927 size(4); 7928 format %{ "AND $src1,$src2,$dst" %} 7929 opcode(Assembler::and_op3, Assembler::arith_op); 7930 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7931 ins_pipe(ialu_reg_imm); 7932 %} 7933 7934 // Register And Long 7935 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7936 match(Set dst (AndL src1 src2)); 7937 7938 ins_cost(DEFAULT_COST); 7939 size(4); 7940 format %{ "AND $src1,$src2,$dst\t! long" %} 7941 opcode(Assembler::and_op3, Assembler::arith_op); 7942 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7943 ins_pipe(ialu_reg_reg); 7944 %} 7945 7946 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7947 match(Set dst (AndL src1 con)); 7948 7949 ins_cost(DEFAULT_COST); 7950 size(4); 7951 format %{ "AND $src1,$con,$dst\t! long" %} 7952 opcode(Assembler::and_op3, Assembler::arith_op); 7953 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7954 ins_pipe(ialu_reg_imm); 7955 %} 7956 7957 // Or Instructions 7958 // Register Or 7959 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7960 match(Set dst (OrI src1 src2)); 7961 7962 size(4); 7963 format %{ "OR $src1,$src2,$dst" %} 7964 opcode(Assembler::or_op3, Assembler::arith_op); 7965 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7966 ins_pipe(ialu_reg_reg); 7967 %} 7968 7969 // Immediate Or 7970 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7971 match(Set dst (OrI src1 src2)); 7972 7973 size(4); 7974 format %{ "OR $src1,$src2,$dst" %} 7975 opcode(Assembler::or_op3, Assembler::arith_op); 7976 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7977 ins_pipe(ialu_reg_imm); 7978 %} 7979 7980 // Register Or Long 7981 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7982 match(Set dst (OrL src1 src2)); 7983 7984 ins_cost(DEFAULT_COST); 7985 size(4); 7986 format %{ "OR $src1,$src2,$dst\t! long" %} 7987 opcode(Assembler::or_op3, Assembler::arith_op); 7988 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7989 ins_pipe(ialu_reg_reg); 7990 %} 7991 7992 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7993 match(Set dst (OrL src1 con)); 7994 ins_cost(DEFAULT_COST*2); 7995 7996 ins_cost(DEFAULT_COST); 7997 size(4); 7998 format %{ "OR $src1,$con,$dst\t! long" %} 7999 opcode(Assembler::or_op3, Assembler::arith_op); 8000 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 8001 ins_pipe(ialu_reg_imm); 8002 %} 8003 8004 #ifndef _LP64 8005 8006 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. 8007 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ 8008 match(Set dst (OrI src1 (CastP2X src2))); 8009 8010 size(4); 8011 format %{ "OR $src1,$src2,$dst" %} 8012 opcode(Assembler::or_op3, Assembler::arith_op); 8013 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8014 ins_pipe(ialu_reg_reg); 8015 %} 8016 8017 #else 8018 8019 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ 8020 match(Set dst (OrL src1 (CastP2X src2))); 8021 8022 ins_cost(DEFAULT_COST); 8023 size(4); 8024 format %{ "OR $src1,$src2,$dst\t! long" %} 8025 opcode(Assembler::or_op3, Assembler::arith_op); 8026 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8027 ins_pipe(ialu_reg_reg); 8028 %} 8029 8030 #endif 8031 8032 // Xor Instructions 8033 // Register Xor 8034 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 8035 match(Set dst (XorI src1 src2)); 8036 8037 size(4); 8038 format %{ "XOR $src1,$src2,$dst" %} 8039 opcode(Assembler::xor_op3, Assembler::arith_op); 8040 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8041 ins_pipe(ialu_reg_reg); 8042 %} 8043 8044 // Immediate Xor 8045 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 8046 match(Set dst (XorI src1 src2)); 8047 8048 size(4); 8049 format %{ "XOR $src1,$src2,$dst" %} 8050 opcode(Assembler::xor_op3, Assembler::arith_op); 8051 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 8052 ins_pipe(ialu_reg_imm); 8053 %} 8054 8055 // Register Xor Long 8056 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 8057 match(Set dst (XorL src1 src2)); 8058 8059 ins_cost(DEFAULT_COST); 8060 size(4); 8061 format %{ "XOR $src1,$src2,$dst\t! long" %} 8062 opcode(Assembler::xor_op3, Assembler::arith_op); 8063 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8064 ins_pipe(ialu_reg_reg); 8065 %} 8066 8067 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 8068 match(Set dst (XorL src1 con)); 8069 8070 ins_cost(DEFAULT_COST); 8071 size(4); 8072 format %{ "XOR $src1,$con,$dst\t! long" %} 8073 opcode(Assembler::xor_op3, Assembler::arith_op); 8074 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 8075 ins_pipe(ialu_reg_imm); 8076 %} 8077 8078 //----------Convert to Boolean------------------------------------------------- 8079 // Nice hack for 32-bit tests but doesn't work for 8080 // 64-bit pointers. 8081 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ 8082 match(Set dst (Conv2B src)); 8083 effect( KILL ccr ); 8084 ins_cost(DEFAULT_COST*2); 8085 format %{ "CMP R_G0,$src\n\t" 8086 "ADDX R_G0,0,$dst" %} 8087 ins_encode( enc_to_bool( src, dst ) ); 8088 ins_pipe(ialu_reg_ialu); 8089 %} 8090 8091 #ifndef _LP64 8092 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ 8093 match(Set dst (Conv2B src)); 8094 effect( KILL ccr ); 8095 ins_cost(DEFAULT_COST*2); 8096 format %{ "CMP R_G0,$src\n\t" 8097 "ADDX R_G0,0,$dst" %} 8098 ins_encode( enc_to_bool( src, dst ) ); 8099 ins_pipe(ialu_reg_ialu); 8100 %} 8101 #else 8102 instruct convP2B( iRegI dst, iRegP src ) %{ 8103 match(Set dst (Conv2B src)); 8104 ins_cost(DEFAULT_COST*2); 8105 format %{ "MOV $src,$dst\n\t" 8106 "MOVRNZ $src,1,$dst" %} 8107 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); 8108 ins_pipe(ialu_clr_and_mover); 8109 %} 8110 #endif 8111 8112 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ 8113 match(Set dst (CmpLTMask src zero)); 8114 effect(KILL ccr); 8115 size(4); 8116 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} 8117 ins_encode %{ 8118 __ sra($src$$Register, 31, $dst$$Register); 8119 %} 8120 ins_pipe(ialu_reg_imm); 8121 %} 8122 8123 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ 8124 match(Set dst (CmpLTMask p q)); 8125 effect( KILL ccr ); 8126 ins_cost(DEFAULT_COST*4); 8127 format %{ "CMP $p,$q\n\t" 8128 "MOV #0,$dst\n\t" 8129 "BLT,a .+8\n\t" 8130 "MOV #-1,$dst" %} 8131 ins_encode( enc_ltmask(p,q,dst) ); 8132 ins_pipe(ialu_reg_reg_ialu); 8133 %} 8134 8135 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 8136 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 8137 effect(KILL ccr, TEMP tmp); 8138 ins_cost(DEFAULT_COST*3); 8139 8140 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 8141 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 8142 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} 8143 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp)); 8144 ins_pipe(cadd_cmpltmask); 8145 %} 8146 8147 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{ 8148 match(Set p (AndI (CmpLTMask p q) y)); 8149 effect(KILL ccr); 8150 ins_cost(DEFAULT_COST*3); 8151 8152 format %{ "CMP $p,$q\n\t" 8153 "MOV $y,$p\n\t" 8154 "MOVge G0,$p" %} 8155 ins_encode %{ 8156 __ cmp($p$$Register, $q$$Register); 8157 __ mov($y$$Register, $p$$Register); 8158 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register); 8159 %} 8160 ins_pipe(ialu_reg_reg_ialu); 8161 %} 8162 8163 //----------------------------------------------------------------- 8164 // Direct raw moves between float and general registers using VIS3. 8165 8166 // ins_pipe(faddF_reg); 8167 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ 8168 predicate(UseVIS >= 3); 8169 match(Set dst (MoveF2I src)); 8170 8171 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} 8172 ins_encode %{ 8173 __ movstouw($src$$FloatRegister, $dst$$Register); 8174 %} 8175 ins_pipe(ialu_reg_reg); 8176 %} 8177 8178 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ 8179 predicate(UseVIS >= 3); 8180 match(Set dst (MoveI2F src)); 8181 8182 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} 8183 ins_encode %{ 8184 __ movwtos($src$$Register, $dst$$FloatRegister); 8185 %} 8186 ins_pipe(ialu_reg_reg); 8187 %} 8188 8189 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ 8190 predicate(UseVIS >= 3); 8191 match(Set dst (MoveD2L src)); 8192 8193 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} 8194 ins_encode %{ 8195 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); 8196 %} 8197 ins_pipe(ialu_reg_reg); 8198 %} 8199 8200 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ 8201 predicate(UseVIS >= 3); 8202 match(Set dst (MoveL2D src)); 8203 8204 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} 8205 ins_encode %{ 8206 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); 8207 %} 8208 ins_pipe(ialu_reg_reg); 8209 %} 8210 8211 8212 // Raw moves between float and general registers using stack. 8213 8214 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 8215 match(Set dst (MoveF2I src)); 8216 effect(DEF dst, USE src); 8217 ins_cost(MEMORY_REF_COST); 8218 8219 format %{ "LDUW $src,$dst\t! MoveF2I" %} 8220 opcode(Assembler::lduw_op3); 8221 ins_encode(simple_form3_mem_reg( src, dst ) ); 8222 ins_pipe(iload_mem); 8223 %} 8224 8225 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 8226 match(Set dst (MoveI2F src)); 8227 effect(DEF dst, USE src); 8228 ins_cost(MEMORY_REF_COST); 8229 8230 format %{ "LDF $src,$dst\t! MoveI2F" %} 8231 opcode(Assembler::ldf_op3); 8232 ins_encode(simple_form3_mem_reg(src, dst)); 8233 ins_pipe(floadF_stk); 8234 %} 8235 8236 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 8237 match(Set dst (MoveD2L src)); 8238 effect(DEF dst, USE src); 8239 ins_cost(MEMORY_REF_COST); 8240 8241 format %{ "LDX $src,$dst\t! MoveD2L" %} 8242 opcode(Assembler::ldx_op3); 8243 ins_encode(simple_form3_mem_reg( src, dst ) ); 8244 ins_pipe(iload_mem); 8245 %} 8246 8247 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 8248 match(Set dst (MoveL2D src)); 8249 effect(DEF dst, USE src); 8250 ins_cost(MEMORY_REF_COST); 8251 8252 format %{ "LDDF $src,$dst\t! MoveL2D" %} 8253 opcode(Assembler::lddf_op3); 8254 ins_encode(simple_form3_mem_reg(src, dst)); 8255 ins_pipe(floadD_stk); 8256 %} 8257 8258 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 8259 match(Set dst (MoveF2I src)); 8260 effect(DEF dst, USE src); 8261 ins_cost(MEMORY_REF_COST); 8262 8263 format %{ "STF $src,$dst\t! MoveF2I" %} 8264 opcode(Assembler::stf_op3); 8265 ins_encode(simple_form3_mem_reg(dst, src)); 8266 ins_pipe(fstoreF_stk_reg); 8267 %} 8268 8269 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 8270 match(Set dst (MoveI2F src)); 8271 effect(DEF dst, USE src); 8272 ins_cost(MEMORY_REF_COST); 8273 8274 format %{ "STW $src,$dst\t! MoveI2F" %} 8275 opcode(Assembler::stw_op3); 8276 ins_encode(simple_form3_mem_reg( dst, src ) ); 8277 ins_pipe(istore_mem_reg); 8278 %} 8279 8280 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 8281 match(Set dst (MoveD2L src)); 8282 effect(DEF dst, USE src); 8283 ins_cost(MEMORY_REF_COST); 8284 8285 format %{ "STDF $src,$dst\t! MoveD2L" %} 8286 opcode(Assembler::stdf_op3); 8287 ins_encode(simple_form3_mem_reg(dst, src)); 8288 ins_pipe(fstoreD_stk_reg); 8289 %} 8290 8291 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 8292 match(Set dst (MoveL2D src)); 8293 effect(DEF dst, USE src); 8294 ins_cost(MEMORY_REF_COST); 8295 8296 format %{ "STX $src,$dst\t! MoveL2D" %} 8297 opcode(Assembler::stx_op3); 8298 ins_encode(simple_form3_mem_reg( dst, src ) ); 8299 ins_pipe(istore_mem_reg); 8300 %} 8301 8302 8303 //----------Arithmetic Conversion Instructions--------------------------------- 8304 // The conversions operations are all Alpha sorted. Please keep it that way! 8305 8306 instruct convD2F_reg(regF dst, regD src) %{ 8307 match(Set dst (ConvD2F src)); 8308 size(4); 8309 format %{ "FDTOS $src,$dst" %} 8310 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); 8311 ins_encode(form3_opf_rs2D_rdF(src, dst)); 8312 ins_pipe(fcvtD2F); 8313 %} 8314 8315 8316 // Convert a double to an int in a float register. 8317 // If the double is a NAN, stuff a zero in instead. 8318 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ 8319 effect(DEF dst, USE src, KILL fcc0); 8320 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8321 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8322 "FDTOI $src,$dst\t! convert in delay slot\n\t" 8323 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8324 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8325 "skip:" %} 8326 ins_encode(form_d2i_helper(src,dst)); 8327 ins_pipe(fcvtD2I); 8328 %} 8329 8330 instruct convD2I_stk(stackSlotI dst, regD src) %{ 8331 match(Set dst (ConvD2I src)); 8332 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8333 expand %{ 8334 regF tmp; 8335 convD2I_helper(tmp, src); 8336 regF_to_stkI(dst, tmp); 8337 %} 8338 %} 8339 8340 instruct convD2I_reg(iRegI dst, regD src) %{ 8341 predicate(UseVIS >= 3); 8342 match(Set dst (ConvD2I src)); 8343 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8344 expand %{ 8345 regF tmp; 8346 convD2I_helper(tmp, src); 8347 MoveF2I_reg_reg(dst, tmp); 8348 %} 8349 %} 8350 8351 8352 // Convert a double to a long in a double register. 8353 // If the double is a NAN, stuff a zero in instead. 8354 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ 8355 effect(DEF dst, USE src, KILL fcc0); 8356 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8357 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8358 "FDTOX $src,$dst\t! convert in delay slot\n\t" 8359 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8360 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8361 "skip:" %} 8362 ins_encode(form_d2l_helper(src,dst)); 8363 ins_pipe(fcvtD2L); 8364 %} 8365 8366 instruct convD2L_stk(stackSlotL dst, regD src) %{ 8367 match(Set dst (ConvD2L src)); 8368 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8369 expand %{ 8370 regD tmp; 8371 convD2L_helper(tmp, src); 8372 regD_to_stkL(dst, tmp); 8373 %} 8374 %} 8375 8376 instruct convD2L_reg(iRegL dst, regD src) %{ 8377 predicate(UseVIS >= 3); 8378 match(Set dst (ConvD2L src)); 8379 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8380 expand %{ 8381 regD tmp; 8382 convD2L_helper(tmp, src); 8383 MoveD2L_reg_reg(dst, tmp); 8384 %} 8385 %} 8386 8387 8388 instruct convF2D_reg(regD dst, regF src) %{ 8389 match(Set dst (ConvF2D src)); 8390 format %{ "FSTOD $src,$dst" %} 8391 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); 8392 ins_encode(form3_opf_rs2F_rdD(src, dst)); 8393 ins_pipe(fcvtF2D); 8394 %} 8395 8396 8397 // Convert a float to an int in a float register. 8398 // If the float is a NAN, stuff a zero in instead. 8399 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ 8400 effect(DEF dst, USE src, KILL fcc0); 8401 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8402 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8403 "FSTOI $src,$dst\t! convert in delay slot\n\t" 8404 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8405 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8406 "skip:" %} 8407 ins_encode(form_f2i_helper(src,dst)); 8408 ins_pipe(fcvtF2I); 8409 %} 8410 8411 instruct convF2I_stk(stackSlotI dst, regF src) %{ 8412 match(Set dst (ConvF2I src)); 8413 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8414 expand %{ 8415 regF tmp; 8416 convF2I_helper(tmp, src); 8417 regF_to_stkI(dst, tmp); 8418 %} 8419 %} 8420 8421 instruct convF2I_reg(iRegI dst, regF src) %{ 8422 predicate(UseVIS >= 3); 8423 match(Set dst (ConvF2I src)); 8424 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8425 expand %{ 8426 regF tmp; 8427 convF2I_helper(tmp, src); 8428 MoveF2I_reg_reg(dst, tmp); 8429 %} 8430 %} 8431 8432 8433 // Convert a float to a long in a float register. 8434 // If the float is a NAN, stuff a zero in instead. 8435 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ 8436 effect(DEF dst, USE src, KILL fcc0); 8437 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8438 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8439 "FSTOX $src,$dst\t! convert in delay slot\n\t" 8440 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8441 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8442 "skip:" %} 8443 ins_encode(form_f2l_helper(src,dst)); 8444 ins_pipe(fcvtF2L); 8445 %} 8446 8447 instruct convF2L_stk(stackSlotL dst, regF src) %{ 8448 match(Set dst (ConvF2L src)); 8449 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8450 expand %{ 8451 regD tmp; 8452 convF2L_helper(tmp, src); 8453 regD_to_stkL(dst, tmp); 8454 %} 8455 %} 8456 8457 instruct convF2L_reg(iRegL dst, regF src) %{ 8458 predicate(UseVIS >= 3); 8459 match(Set dst (ConvF2L src)); 8460 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8461 expand %{ 8462 regD tmp; 8463 convF2L_helper(tmp, src); 8464 MoveD2L_reg_reg(dst, tmp); 8465 %} 8466 %} 8467 8468 8469 instruct convI2D_helper(regD dst, regF tmp) %{ 8470 effect(USE tmp, DEF dst); 8471 format %{ "FITOD $tmp,$dst" %} 8472 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8473 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); 8474 ins_pipe(fcvtI2D); 8475 %} 8476 8477 instruct convI2D_stk(stackSlotI src, regD dst) %{ 8478 match(Set dst (ConvI2D src)); 8479 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8480 expand %{ 8481 regF tmp; 8482 stkI_to_regF(tmp, src); 8483 convI2D_helper(dst, tmp); 8484 %} 8485 %} 8486 8487 instruct convI2D_reg(regD_low dst, iRegI src) %{ 8488 predicate(UseVIS >= 3); 8489 match(Set dst (ConvI2D src)); 8490 expand %{ 8491 regF tmp; 8492 MoveI2F_reg_reg(tmp, src); 8493 convI2D_helper(dst, tmp); 8494 %} 8495 %} 8496 8497 instruct convI2D_mem(regD_low dst, memory mem) %{ 8498 match(Set dst (ConvI2D (LoadI mem))); 8499 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8500 format %{ "LDF $mem,$dst\n\t" 8501 "FITOD $dst,$dst" %} 8502 opcode(Assembler::ldf_op3, Assembler::fitod_opf); 8503 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8504 ins_pipe(floadF_mem); 8505 %} 8506 8507 8508 instruct convI2F_helper(regF dst, regF tmp) %{ 8509 effect(DEF dst, USE tmp); 8510 format %{ "FITOS $tmp,$dst" %} 8511 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); 8512 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); 8513 ins_pipe(fcvtI2F); 8514 %} 8515 8516 instruct convI2F_stk(regF dst, stackSlotI src) %{ 8517 match(Set dst (ConvI2F src)); 8518 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8519 expand %{ 8520 regF tmp; 8521 stkI_to_regF(tmp,src); 8522 convI2F_helper(dst, tmp); 8523 %} 8524 %} 8525 8526 instruct convI2F_reg(regF dst, iRegI src) %{ 8527 predicate(UseVIS >= 3); 8528 match(Set dst (ConvI2F src)); 8529 ins_cost(DEFAULT_COST); 8530 expand %{ 8531 regF tmp; 8532 MoveI2F_reg_reg(tmp, src); 8533 convI2F_helper(dst, tmp); 8534 %} 8535 %} 8536 8537 instruct convI2F_mem( regF dst, memory mem ) %{ 8538 match(Set dst (ConvI2F (LoadI mem))); 8539 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8540 format %{ "LDF $mem,$dst\n\t" 8541 "FITOS $dst,$dst" %} 8542 opcode(Assembler::ldf_op3, Assembler::fitos_opf); 8543 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8544 ins_pipe(floadF_mem); 8545 %} 8546 8547 8548 instruct convI2L_reg(iRegL dst, iRegI src) %{ 8549 match(Set dst (ConvI2L src)); 8550 size(4); 8551 format %{ "SRA $src,0,$dst\t! int->long" %} 8552 opcode(Assembler::sra_op3, Assembler::arith_op); 8553 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8554 ins_pipe(ialu_reg_reg); 8555 %} 8556 8557 // Zero-extend convert int to long 8558 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ 8559 match(Set dst (AndL (ConvI2L src) mask) ); 8560 size(4); 8561 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} 8562 opcode(Assembler::srl_op3, Assembler::arith_op); 8563 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8564 ins_pipe(ialu_reg_reg); 8565 %} 8566 8567 // Zero-extend long 8568 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ 8569 match(Set dst (AndL src mask) ); 8570 size(4); 8571 format %{ "SRL $src,0,$dst\t! zero-extend long" %} 8572 opcode(Assembler::srl_op3, Assembler::arith_op); 8573 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8574 ins_pipe(ialu_reg_reg); 8575 %} 8576 8577 8578 //----------- 8579 // Long to Double conversion using V8 opcodes. 8580 // Still useful because cheetah traps and becomes 8581 // amazingly slow for some common numbers. 8582 8583 // Magic constant, 0x43300000 8584 instruct loadConI_x43300000(iRegI dst) %{ 8585 effect(DEF dst); 8586 size(4); 8587 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} 8588 ins_encode(SetHi22(0x43300000, dst)); 8589 ins_pipe(ialu_none); 8590 %} 8591 8592 // Magic constant, 0x41f00000 8593 instruct loadConI_x41f00000(iRegI dst) %{ 8594 effect(DEF dst); 8595 size(4); 8596 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} 8597 ins_encode(SetHi22(0x41f00000, dst)); 8598 ins_pipe(ialu_none); 8599 %} 8600 8601 // Construct a double from two float halves 8602 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ 8603 effect(DEF dst, USE src1, USE src2); 8604 size(8); 8605 format %{ "FMOVS $src1.hi,$dst.hi\n\t" 8606 "FMOVS $src2.lo,$dst.lo" %} 8607 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); 8608 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); 8609 ins_pipe(faddD_reg_reg); 8610 %} 8611 8612 // Convert integer in high half of a double register (in the lower half of 8613 // the double register file) to double 8614 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ 8615 effect(DEF dst, USE src); 8616 size(4); 8617 format %{ "FITOD $src,$dst" %} 8618 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8619 ins_encode(form3_opf_rs2D_rdD(src, dst)); 8620 ins_pipe(fcvtLHi2D); 8621 %} 8622 8623 // Add float double precision 8624 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ 8625 effect(DEF dst, USE src1, USE src2); 8626 size(4); 8627 format %{ "FADDD $src1,$src2,$dst" %} 8628 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 8629 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8630 ins_pipe(faddD_reg_reg); 8631 %} 8632 8633 // Sub float double precision 8634 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ 8635 effect(DEF dst, USE src1, USE src2); 8636 size(4); 8637 format %{ "FSUBD $src1,$src2,$dst" %} 8638 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 8639 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8640 ins_pipe(faddD_reg_reg); 8641 %} 8642 8643 // Mul float double precision 8644 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ 8645 effect(DEF dst, USE src1, USE src2); 8646 size(4); 8647 format %{ "FMULD $src1,$src2,$dst" %} 8648 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 8649 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8650 ins_pipe(fmulD_reg_reg); 8651 %} 8652 8653 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ 8654 match(Set dst (ConvL2D src)); 8655 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); 8656 8657 expand %{ 8658 regD_low tmpsrc; 8659 iRegI ix43300000; 8660 iRegI ix41f00000; 8661 stackSlotL lx43300000; 8662 stackSlotL lx41f00000; 8663 regD_low dx43300000; 8664 regD dx41f00000; 8665 regD tmp1; 8666 regD_low tmp2; 8667 regD tmp3; 8668 regD tmp4; 8669 8670 stkL_to_regD(tmpsrc, src); 8671 8672 loadConI_x43300000(ix43300000); 8673 loadConI_x41f00000(ix41f00000); 8674 regI_to_stkLHi(lx43300000, ix43300000); 8675 regI_to_stkLHi(lx41f00000, ix41f00000); 8676 stkL_to_regD(dx43300000, lx43300000); 8677 stkL_to_regD(dx41f00000, lx41f00000); 8678 8679 convI2D_regDHi_regD(tmp1, tmpsrc); 8680 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); 8681 subD_regD_regD(tmp3, tmp2, dx43300000); 8682 mulD_regD_regD(tmp4, tmp1, dx41f00000); 8683 addD_regD_regD(dst, tmp3, tmp4); 8684 %} 8685 %} 8686 8687 // Long to Double conversion using fast fxtof 8688 instruct convL2D_helper(regD dst, regD tmp) %{ 8689 effect(DEF dst, USE tmp); 8690 size(4); 8691 format %{ "FXTOD $tmp,$dst" %} 8692 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); 8693 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); 8694 ins_pipe(fcvtL2D); 8695 %} 8696 8697 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ 8698 predicate(VM_Version::has_fast_fxtof()); 8699 match(Set dst (ConvL2D src)); 8700 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); 8701 expand %{ 8702 regD tmp; 8703 stkL_to_regD(tmp, src); 8704 convL2D_helper(dst, tmp); 8705 %} 8706 %} 8707 8708 instruct convL2D_reg(regD dst, iRegL src) %{ 8709 predicate(UseVIS >= 3); 8710 match(Set dst (ConvL2D src)); 8711 expand %{ 8712 regD tmp; 8713 MoveL2D_reg_reg(tmp, src); 8714 convL2D_helper(dst, tmp); 8715 %} 8716 %} 8717 8718 // Long to Float conversion using fast fxtof 8719 instruct convL2F_helper(regF dst, regD tmp) %{ 8720 effect(DEF dst, USE tmp); 8721 size(4); 8722 format %{ "FXTOS $tmp,$dst" %} 8723 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); 8724 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); 8725 ins_pipe(fcvtL2F); 8726 %} 8727 8728 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ 8729 match(Set dst (ConvL2F src)); 8730 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8731 expand %{ 8732 regD tmp; 8733 stkL_to_regD(tmp, src); 8734 convL2F_helper(dst, tmp); 8735 %} 8736 %} 8737 8738 instruct convL2F_reg(regF dst, iRegL src) %{ 8739 predicate(UseVIS >= 3); 8740 match(Set dst (ConvL2F src)); 8741 ins_cost(DEFAULT_COST); 8742 expand %{ 8743 regD tmp; 8744 MoveL2D_reg_reg(tmp, src); 8745 convL2F_helper(dst, tmp); 8746 %} 8747 %} 8748 8749 //----------- 8750 8751 instruct convL2I_reg(iRegI dst, iRegL src) %{ 8752 match(Set dst (ConvL2I src)); 8753 #ifndef _LP64 8754 format %{ "MOV $src.lo,$dst\t! long->int" %} 8755 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); 8756 ins_pipe(ialu_move_reg_I_to_L); 8757 #else 8758 size(4); 8759 format %{ "SRA $src,R_G0,$dst\t! long->int" %} 8760 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); 8761 ins_pipe(ialu_reg); 8762 #endif 8763 %} 8764 8765 // Register Shift Right Immediate 8766 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ 8767 match(Set dst (ConvL2I (RShiftL src cnt))); 8768 8769 size(4); 8770 format %{ "SRAX $src,$cnt,$dst" %} 8771 opcode(Assembler::srax_op3, Assembler::arith_op); 8772 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); 8773 ins_pipe(ialu_reg_imm); 8774 %} 8775 8776 //----------Control Flow Instructions------------------------------------------ 8777 // Compare Instructions 8778 // Compare Integers 8779 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ 8780 match(Set icc (CmpI op1 op2)); 8781 effect( DEF icc, USE op1, USE op2 ); 8782 8783 size(4); 8784 format %{ "CMP $op1,$op2" %} 8785 opcode(Assembler::subcc_op3, Assembler::arith_op); 8786 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8787 ins_pipe(ialu_cconly_reg_reg); 8788 %} 8789 8790 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ 8791 match(Set icc (CmpU op1 op2)); 8792 8793 size(4); 8794 format %{ "CMP $op1,$op2\t! unsigned" %} 8795 opcode(Assembler::subcc_op3, Assembler::arith_op); 8796 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8797 ins_pipe(ialu_cconly_reg_reg); 8798 %} 8799 8800 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ 8801 match(Set icc (CmpI op1 op2)); 8802 effect( DEF icc, USE op1 ); 8803 8804 size(4); 8805 format %{ "CMP $op1,$op2" %} 8806 opcode(Assembler::subcc_op3, Assembler::arith_op); 8807 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8808 ins_pipe(ialu_cconly_reg_imm); 8809 %} 8810 8811 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ 8812 match(Set icc (CmpI (AndI op1 op2) zero)); 8813 8814 size(4); 8815 format %{ "BTST $op2,$op1" %} 8816 opcode(Assembler::andcc_op3, Assembler::arith_op); 8817 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8818 ins_pipe(ialu_cconly_reg_reg_zero); 8819 %} 8820 8821 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ 8822 match(Set icc (CmpI (AndI op1 op2) zero)); 8823 8824 size(4); 8825 format %{ "BTST $op2,$op1" %} 8826 opcode(Assembler::andcc_op3, Assembler::arith_op); 8827 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8828 ins_pipe(ialu_cconly_reg_imm_zero); 8829 %} 8830 8831 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ 8832 match(Set xcc (CmpL op1 op2)); 8833 effect( DEF xcc, USE op1, USE op2 ); 8834 8835 size(4); 8836 format %{ "CMP $op1,$op2\t\t! long" %} 8837 opcode(Assembler::subcc_op3, Assembler::arith_op); 8838 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8839 ins_pipe(ialu_cconly_reg_reg); 8840 %} 8841 8842 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ 8843 match(Set xcc (CmpL op1 con)); 8844 effect( DEF xcc, USE op1, USE con ); 8845 8846 size(4); 8847 format %{ "CMP $op1,$con\t\t! long" %} 8848 opcode(Assembler::subcc_op3, Assembler::arith_op); 8849 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8850 ins_pipe(ialu_cconly_reg_reg); 8851 %} 8852 8853 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ 8854 match(Set xcc (CmpL (AndL op1 op2) zero)); 8855 effect( DEF xcc, USE op1, USE op2 ); 8856 8857 size(4); 8858 format %{ "BTST $op1,$op2\t\t! long" %} 8859 opcode(Assembler::andcc_op3, Assembler::arith_op); 8860 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8861 ins_pipe(ialu_cconly_reg_reg); 8862 %} 8863 8864 // useful for checking the alignment of a pointer: 8865 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ 8866 match(Set xcc (CmpL (AndL op1 con) zero)); 8867 effect( DEF xcc, USE op1, USE con ); 8868 8869 size(4); 8870 format %{ "BTST $op1,$con\t\t! long" %} 8871 opcode(Assembler::andcc_op3, Assembler::arith_op); 8872 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8873 ins_pipe(ialu_cconly_reg_reg); 8874 %} 8875 8876 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{ 8877 match(Set icc (CmpU op1 op2)); 8878 8879 size(4); 8880 format %{ "CMP $op1,$op2\t! unsigned" %} 8881 opcode(Assembler::subcc_op3, Assembler::arith_op); 8882 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8883 ins_pipe(ialu_cconly_reg_imm); 8884 %} 8885 8886 // Compare Pointers 8887 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ 8888 match(Set pcc (CmpP op1 op2)); 8889 8890 size(4); 8891 format %{ "CMP $op1,$op2\t! ptr" %} 8892 opcode(Assembler::subcc_op3, Assembler::arith_op); 8893 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8894 ins_pipe(ialu_cconly_reg_reg); 8895 %} 8896 8897 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ 8898 match(Set pcc (CmpP op1 op2)); 8899 8900 size(4); 8901 format %{ "CMP $op1,$op2\t! ptr" %} 8902 opcode(Assembler::subcc_op3, Assembler::arith_op); 8903 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8904 ins_pipe(ialu_cconly_reg_imm); 8905 %} 8906 8907 // Compare Narrow oops 8908 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ 8909 match(Set icc (CmpN op1 op2)); 8910 8911 size(4); 8912 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8913 opcode(Assembler::subcc_op3, Assembler::arith_op); 8914 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8915 ins_pipe(ialu_cconly_reg_reg); 8916 %} 8917 8918 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ 8919 match(Set icc (CmpN op1 op2)); 8920 8921 size(4); 8922 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8923 opcode(Assembler::subcc_op3, Assembler::arith_op); 8924 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8925 ins_pipe(ialu_cconly_reg_imm); 8926 %} 8927 8928 //----------Max and Min-------------------------------------------------------- 8929 // Min Instructions 8930 // Conditional move for min 8931 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8932 effect( USE_DEF op2, USE op1, USE icc ); 8933 8934 size(4); 8935 format %{ "MOVlt icc,$op1,$op2\t! min" %} 8936 opcode(Assembler::less); 8937 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8938 ins_pipe(ialu_reg_flags); 8939 %} 8940 8941 // Min Register with Register. 8942 instruct minI_eReg(iRegI op1, iRegI op2) %{ 8943 match(Set op2 (MinI op1 op2)); 8944 ins_cost(DEFAULT_COST*2); 8945 expand %{ 8946 flagsReg icc; 8947 compI_iReg(icc,op1,op2); 8948 cmovI_reg_lt(op2,op1,icc); 8949 %} 8950 %} 8951 8952 // Max Instructions 8953 // Conditional move for max 8954 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8955 effect( USE_DEF op2, USE op1, USE icc ); 8956 format %{ "MOVgt icc,$op1,$op2\t! max" %} 8957 opcode(Assembler::greater); 8958 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8959 ins_pipe(ialu_reg_flags); 8960 %} 8961 8962 // Max Register with Register 8963 instruct maxI_eReg(iRegI op1, iRegI op2) %{ 8964 match(Set op2 (MaxI op1 op2)); 8965 ins_cost(DEFAULT_COST*2); 8966 expand %{ 8967 flagsReg icc; 8968 compI_iReg(icc,op1,op2); 8969 cmovI_reg_gt(op2,op1,icc); 8970 %} 8971 %} 8972 8973 8974 //----------Float Compares---------------------------------------------------- 8975 // Compare floating, generate condition code 8976 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ 8977 match(Set fcc (CmpF src1 src2)); 8978 8979 size(4); 8980 format %{ "FCMPs $fcc,$src1,$src2" %} 8981 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); 8982 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); 8983 ins_pipe(faddF_fcc_reg_reg_zero); 8984 %} 8985 8986 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ 8987 match(Set fcc (CmpD src1 src2)); 8988 8989 size(4); 8990 format %{ "FCMPd $fcc,$src1,$src2" %} 8991 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); 8992 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); 8993 ins_pipe(faddD_fcc_reg_reg_zero); 8994 %} 8995 8996 8997 // Compare floating, generate -1,0,1 8998 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ 8999 match(Set dst (CmpF3 src1 src2)); 9000 effect(KILL fcc0); 9001 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 9002 format %{ "fcmpl $dst,$src1,$src2" %} 9003 // Primary = float 9004 opcode( true ); 9005 ins_encode( floating_cmp( dst, src1, src2 ) ); 9006 ins_pipe( floating_cmp ); 9007 %} 9008 9009 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ 9010 match(Set dst (CmpD3 src1 src2)); 9011 effect(KILL fcc0); 9012 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 9013 format %{ "dcmpl $dst,$src1,$src2" %} 9014 // Primary = double (not float) 9015 opcode( false ); 9016 ins_encode( floating_cmp( dst, src1, src2 ) ); 9017 ins_pipe( floating_cmp ); 9018 %} 9019 9020 //----------Branches--------------------------------------------------------- 9021 // Jump 9022 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) 9023 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ 9024 match(Jump switch_val); 9025 effect(TEMP table); 9026 9027 ins_cost(350); 9028 9029 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" 9030 "LD [O7 + $switch_val], O7\n\t" 9031 "JUMP O7" %} 9032 ins_encode %{ 9033 // Calculate table address into a register. 9034 Register table_reg; 9035 Register label_reg = O7; 9036 // If we are calculating the size of this instruction don't trust 9037 // zero offsets because they might change when 9038 // MachConstantBaseNode decides to optimize the constant table 9039 // base. 9040 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { 9041 table_reg = $constanttablebase; 9042 } else { 9043 table_reg = O7; 9044 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); 9045 __ add($constanttablebase, con_offset, table_reg); 9046 } 9047 9048 // Jump to base address + switch value 9049 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); 9050 __ jmp(label_reg, G0); 9051 __ delayed()->nop(); 9052 %} 9053 ins_pipe(ialu_reg_reg); 9054 %} 9055 9056 // Direct Branch. Use V8 version with longer range. 9057 instruct branch(label labl) %{ 9058 match(Goto); 9059 effect(USE labl); 9060 9061 size(8); 9062 ins_cost(BRANCH_COST); 9063 format %{ "BA $labl" %} 9064 ins_encode %{ 9065 Label* L = $labl$$label; 9066 __ ba(*L); 9067 __ delayed()->nop(); 9068 %} 9069 ins_avoid_back_to_back(AVOID_BEFORE); 9070 ins_pipe(br); 9071 %} 9072 9073 // Direct Branch, short with no delay slot 9074 instruct branch_short(label labl) %{ 9075 match(Goto); 9076 predicate(UseCBCond); 9077 effect(USE labl); 9078 9079 size(4); 9080 ins_cost(BRANCH_COST); 9081 format %{ "BA $labl\t! short branch" %} 9082 ins_encode %{ 9083 Label* L = $labl$$label; 9084 assert(__ use_cbcond(*L), "back to back cbcond"); 9085 __ ba_short(*L); 9086 %} 9087 ins_short_branch(1); 9088 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9089 ins_pipe(cbcond_reg_imm); 9090 %} 9091 9092 // Conditional Direct Branch 9093 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ 9094 match(If cmp icc); 9095 effect(USE labl); 9096 9097 size(8); 9098 ins_cost(BRANCH_COST); 9099 format %{ "BP$cmp $icc,$labl" %} 9100 // Prim = bits 24-22, Secnd = bits 31-30 9101 ins_encode( enc_bp( labl, cmp, icc ) ); 9102 ins_avoid_back_to_back(AVOID_BEFORE); 9103 ins_pipe(br_cc); 9104 %} 9105 9106 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9107 match(If cmp icc); 9108 effect(USE labl); 9109 9110 ins_cost(BRANCH_COST); 9111 format %{ "BP$cmp $icc,$labl" %} 9112 // Prim = bits 24-22, Secnd = bits 31-30 9113 ins_encode( enc_bp( labl, cmp, icc ) ); 9114 ins_avoid_back_to_back(AVOID_BEFORE); 9115 ins_pipe(br_cc); 9116 %} 9117 9118 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ 9119 match(If cmp pcc); 9120 effect(USE labl); 9121 9122 size(8); 9123 ins_cost(BRANCH_COST); 9124 format %{ "BP$cmp $pcc,$labl" %} 9125 ins_encode %{ 9126 Label* L = $labl$$label; 9127 Assembler::Predict predict_taken = 9128 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9129 9130 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9131 __ delayed()->nop(); 9132 %} 9133 ins_avoid_back_to_back(AVOID_BEFORE); 9134 ins_pipe(br_cc); 9135 %} 9136 9137 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ 9138 match(If cmp fcc); 9139 effect(USE labl); 9140 9141 size(8); 9142 ins_cost(BRANCH_COST); 9143 format %{ "FBP$cmp $fcc,$labl" %} 9144 ins_encode %{ 9145 Label* L = $labl$$label; 9146 Assembler::Predict predict_taken = 9147 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9148 9149 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); 9150 __ delayed()->nop(); 9151 %} 9152 ins_avoid_back_to_back(AVOID_BEFORE); 9153 ins_pipe(br_fcc); 9154 %} 9155 9156 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ 9157 match(CountedLoopEnd cmp icc); 9158 effect(USE labl); 9159 9160 size(8); 9161 ins_cost(BRANCH_COST); 9162 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9163 // Prim = bits 24-22, Secnd = bits 31-30 9164 ins_encode( enc_bp( labl, cmp, icc ) ); 9165 ins_avoid_back_to_back(AVOID_BEFORE); 9166 ins_pipe(br_cc); 9167 %} 9168 9169 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9170 match(CountedLoopEnd cmp icc); 9171 effect(USE labl); 9172 9173 size(8); 9174 ins_cost(BRANCH_COST); 9175 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9176 // Prim = bits 24-22, Secnd = bits 31-30 9177 ins_encode( enc_bp( labl, cmp, icc ) ); 9178 ins_avoid_back_to_back(AVOID_BEFORE); 9179 ins_pipe(br_cc); 9180 %} 9181 9182 // Compare and branch instructions 9183 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9184 match(If cmp (CmpI op1 op2)); 9185 effect(USE labl, KILL icc); 9186 9187 size(12); 9188 ins_cost(BRANCH_COST); 9189 format %{ "CMP $op1,$op2\t! int\n\t" 9190 "BP$cmp $labl" %} 9191 ins_encode %{ 9192 Label* L = $labl$$label; 9193 Assembler::Predict predict_taken = 9194 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9195 __ cmp($op1$$Register, $op2$$Register); 9196 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9197 __ delayed()->nop(); 9198 %} 9199 ins_pipe(cmp_br_reg_reg); 9200 %} 9201 9202 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9203 match(If cmp (CmpI op1 op2)); 9204 effect(USE labl, KILL icc); 9205 9206 size(12); 9207 ins_cost(BRANCH_COST); 9208 format %{ "CMP $op1,$op2\t! int\n\t" 9209 "BP$cmp $labl" %} 9210 ins_encode %{ 9211 Label* L = $labl$$label; 9212 Assembler::Predict predict_taken = 9213 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9214 __ cmp($op1$$Register, $op2$$constant); 9215 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9216 __ delayed()->nop(); 9217 %} 9218 ins_pipe(cmp_br_reg_imm); 9219 %} 9220 9221 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 9222 match(If cmp (CmpU op1 op2)); 9223 effect(USE labl, KILL icc); 9224 9225 size(12); 9226 ins_cost(BRANCH_COST); 9227 format %{ "CMP $op1,$op2\t! unsigned\n\t" 9228 "BP$cmp $labl" %} 9229 ins_encode %{ 9230 Label* L = $labl$$label; 9231 Assembler::Predict predict_taken = 9232 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9233 __ cmp($op1$$Register, $op2$$Register); 9234 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9235 __ delayed()->nop(); 9236 %} 9237 ins_pipe(cmp_br_reg_reg); 9238 %} 9239 9240 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 9241 match(If cmp (CmpU op1 op2)); 9242 effect(USE labl, KILL icc); 9243 9244 size(12); 9245 ins_cost(BRANCH_COST); 9246 format %{ "CMP $op1,$op2\t! unsigned\n\t" 9247 "BP$cmp $labl" %} 9248 ins_encode %{ 9249 Label* L = $labl$$label; 9250 Assembler::Predict predict_taken = 9251 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9252 __ cmp($op1$$Register, $op2$$constant); 9253 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9254 __ delayed()->nop(); 9255 %} 9256 ins_pipe(cmp_br_reg_imm); 9257 %} 9258 9259 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 9260 match(If cmp (CmpL op1 op2)); 9261 effect(USE labl, KILL xcc); 9262 9263 size(12); 9264 ins_cost(BRANCH_COST); 9265 format %{ "CMP $op1,$op2\t! long\n\t" 9266 "BP$cmp $labl" %} 9267 ins_encode %{ 9268 Label* L = $labl$$label; 9269 Assembler::Predict predict_taken = 9270 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9271 __ cmp($op1$$Register, $op2$$Register); 9272 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9273 __ delayed()->nop(); 9274 %} 9275 ins_pipe(cmp_br_reg_reg); 9276 %} 9277 9278 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 9279 match(If cmp (CmpL op1 op2)); 9280 effect(USE labl, KILL xcc); 9281 9282 size(12); 9283 ins_cost(BRANCH_COST); 9284 format %{ "CMP $op1,$op2\t! long\n\t" 9285 "BP$cmp $labl" %} 9286 ins_encode %{ 9287 Label* L = $labl$$label; 9288 Assembler::Predict predict_taken = 9289 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9290 __ cmp($op1$$Register, $op2$$constant); 9291 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9292 __ delayed()->nop(); 9293 %} 9294 ins_pipe(cmp_br_reg_imm); 9295 %} 9296 9297 // Compare Pointers and branch 9298 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 9299 match(If cmp (CmpP op1 op2)); 9300 effect(USE labl, KILL pcc); 9301 9302 size(12); 9303 ins_cost(BRANCH_COST); 9304 format %{ "CMP $op1,$op2\t! ptr\n\t" 9305 "B$cmp $labl" %} 9306 ins_encode %{ 9307 Label* L = $labl$$label; 9308 Assembler::Predict predict_taken = 9309 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9310 __ cmp($op1$$Register, $op2$$Register); 9311 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9312 __ delayed()->nop(); 9313 %} 9314 ins_pipe(cmp_br_reg_reg); 9315 %} 9316 9317 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 9318 match(If cmp (CmpP op1 null)); 9319 effect(USE labl, KILL pcc); 9320 9321 size(12); 9322 ins_cost(BRANCH_COST); 9323 format %{ "CMP $op1,0\t! ptr\n\t" 9324 "B$cmp $labl" %} 9325 ins_encode %{ 9326 Label* L = $labl$$label; 9327 Assembler::Predict predict_taken = 9328 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9329 __ cmp($op1$$Register, G0); 9330 // bpr() is not used here since it has shorter distance. 9331 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9332 __ delayed()->nop(); 9333 %} 9334 ins_pipe(cmp_br_reg_reg); 9335 %} 9336 9337 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 9338 match(If cmp (CmpN op1 op2)); 9339 effect(USE labl, KILL icc); 9340 9341 size(12); 9342 ins_cost(BRANCH_COST); 9343 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" 9344 "BP$cmp $labl" %} 9345 ins_encode %{ 9346 Label* L = $labl$$label; 9347 Assembler::Predict predict_taken = 9348 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9349 __ cmp($op1$$Register, $op2$$Register); 9350 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9351 __ delayed()->nop(); 9352 %} 9353 ins_pipe(cmp_br_reg_reg); 9354 %} 9355 9356 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 9357 match(If cmp (CmpN op1 null)); 9358 effect(USE labl, KILL icc); 9359 9360 size(12); 9361 ins_cost(BRANCH_COST); 9362 format %{ "CMP $op1,0\t! compressed ptr\n\t" 9363 "BP$cmp $labl" %} 9364 ins_encode %{ 9365 Label* L = $labl$$label; 9366 Assembler::Predict predict_taken = 9367 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9368 __ cmp($op1$$Register, G0); 9369 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9370 __ delayed()->nop(); 9371 %} 9372 ins_pipe(cmp_br_reg_reg); 9373 %} 9374 9375 // Loop back branch 9376 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9377 match(CountedLoopEnd cmp (CmpI op1 op2)); 9378 effect(USE labl, KILL icc); 9379 9380 size(12); 9381 ins_cost(BRANCH_COST); 9382 format %{ "CMP $op1,$op2\t! int\n\t" 9383 "BP$cmp $labl\t! Loop end" %} 9384 ins_encode %{ 9385 Label* L = $labl$$label; 9386 Assembler::Predict predict_taken = 9387 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9388 __ cmp($op1$$Register, $op2$$Register); 9389 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9390 __ delayed()->nop(); 9391 %} 9392 ins_pipe(cmp_br_reg_reg); 9393 %} 9394 9395 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9396 match(CountedLoopEnd cmp (CmpI op1 op2)); 9397 effect(USE labl, KILL icc); 9398 9399 size(12); 9400 ins_cost(BRANCH_COST); 9401 format %{ "CMP $op1,$op2\t! int\n\t" 9402 "BP$cmp $labl\t! Loop end" %} 9403 ins_encode %{ 9404 Label* L = $labl$$label; 9405 Assembler::Predict predict_taken = 9406 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9407 __ cmp($op1$$Register, $op2$$constant); 9408 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9409 __ delayed()->nop(); 9410 %} 9411 ins_pipe(cmp_br_reg_imm); 9412 %} 9413 9414 // Short compare and branch instructions 9415 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9416 match(If cmp (CmpI op1 op2)); 9417 predicate(UseCBCond); 9418 effect(USE labl, KILL icc); 9419 9420 size(4); 9421 ins_cost(BRANCH_COST); 9422 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 9423 ins_encode %{ 9424 Label* L = $labl$$label; 9425 assert(__ use_cbcond(*L), "back to back cbcond"); 9426 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9427 %} 9428 ins_short_branch(1); 9429 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9430 ins_pipe(cbcond_reg_reg); 9431 %} 9432 9433 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9434 match(If cmp (CmpI op1 op2)); 9435 predicate(UseCBCond); 9436 effect(USE labl, KILL icc); 9437 9438 size(4); 9439 ins_cost(BRANCH_COST); 9440 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 9441 ins_encode %{ 9442 Label* L = $labl$$label; 9443 assert(__ use_cbcond(*L), "back to back cbcond"); 9444 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9445 %} 9446 ins_short_branch(1); 9447 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9448 ins_pipe(cbcond_reg_imm); 9449 %} 9450 9451 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 9452 match(If cmp (CmpU op1 op2)); 9453 predicate(UseCBCond); 9454 effect(USE labl, KILL icc); 9455 9456 size(4); 9457 ins_cost(BRANCH_COST); 9458 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9459 ins_encode %{ 9460 Label* L = $labl$$label; 9461 assert(__ use_cbcond(*L), "back to back cbcond"); 9462 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9463 %} 9464 ins_short_branch(1); 9465 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9466 ins_pipe(cbcond_reg_reg); 9467 %} 9468 9469 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 9470 match(If cmp (CmpU op1 op2)); 9471 predicate(UseCBCond); 9472 effect(USE labl, KILL icc); 9473 9474 size(4); 9475 ins_cost(BRANCH_COST); 9476 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9477 ins_encode %{ 9478 Label* L = $labl$$label; 9479 assert(__ use_cbcond(*L), "back to back cbcond"); 9480 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9481 %} 9482 ins_short_branch(1); 9483 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9484 ins_pipe(cbcond_reg_imm); 9485 %} 9486 9487 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 9488 match(If cmp (CmpL op1 op2)); 9489 predicate(UseCBCond); 9490 effect(USE labl, KILL xcc); 9491 9492 size(4); 9493 ins_cost(BRANCH_COST); 9494 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9495 ins_encode %{ 9496 Label* L = $labl$$label; 9497 assert(__ use_cbcond(*L), "back to back cbcond"); 9498 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); 9499 %} 9500 ins_short_branch(1); 9501 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9502 ins_pipe(cbcond_reg_reg); 9503 %} 9504 9505 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 9506 match(If cmp (CmpL op1 op2)); 9507 predicate(UseCBCond); 9508 effect(USE labl, KILL xcc); 9509 9510 size(4); 9511 ins_cost(BRANCH_COST); 9512 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9513 ins_encode %{ 9514 Label* L = $labl$$label; 9515 assert(__ use_cbcond(*L), "back to back cbcond"); 9516 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); 9517 %} 9518 ins_short_branch(1); 9519 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9520 ins_pipe(cbcond_reg_imm); 9521 %} 9522 9523 // Compare Pointers and branch 9524 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 9525 match(If cmp (CmpP op1 op2)); 9526 predicate(UseCBCond); 9527 effect(USE labl, KILL pcc); 9528 9529 size(4); 9530 ins_cost(BRANCH_COST); 9531 #ifdef _LP64 9532 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} 9533 #else 9534 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %} 9535 #endif 9536 ins_encode %{ 9537 Label* L = $labl$$label; 9538 assert(__ use_cbcond(*L), "back to back cbcond"); 9539 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); 9540 %} 9541 ins_short_branch(1); 9542 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9543 ins_pipe(cbcond_reg_reg); 9544 %} 9545 9546 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 9547 match(If cmp (CmpP op1 null)); 9548 predicate(UseCBCond); 9549 effect(USE labl, KILL pcc); 9550 9551 size(4); 9552 ins_cost(BRANCH_COST); 9553 #ifdef _LP64 9554 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} 9555 #else 9556 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %} 9557 #endif 9558 ins_encode %{ 9559 Label* L = $labl$$label; 9560 assert(__ use_cbcond(*L), "back to back cbcond"); 9561 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); 9562 %} 9563 ins_short_branch(1); 9564 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9565 ins_pipe(cbcond_reg_reg); 9566 %} 9567 9568 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 9569 match(If cmp (CmpN op1 op2)); 9570 predicate(UseCBCond); 9571 effect(USE labl, KILL icc); 9572 9573 size(4); 9574 ins_cost(BRANCH_COST); 9575 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %} 9576 ins_encode %{ 9577 Label* L = $labl$$label; 9578 assert(__ use_cbcond(*L), "back to back cbcond"); 9579 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9580 %} 9581 ins_short_branch(1); 9582 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9583 ins_pipe(cbcond_reg_reg); 9584 %} 9585 9586 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 9587 match(If cmp (CmpN op1 null)); 9588 predicate(UseCBCond); 9589 effect(USE labl, KILL icc); 9590 9591 size(4); 9592 ins_cost(BRANCH_COST); 9593 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} 9594 ins_encode %{ 9595 Label* L = $labl$$label; 9596 assert(__ use_cbcond(*L), "back to back cbcond"); 9597 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); 9598 %} 9599 ins_short_branch(1); 9600 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9601 ins_pipe(cbcond_reg_reg); 9602 %} 9603 9604 // Loop back branch 9605 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9606 match(CountedLoopEnd cmp (CmpI op1 op2)); 9607 predicate(UseCBCond); 9608 effect(USE labl, KILL icc); 9609 9610 size(4); 9611 ins_cost(BRANCH_COST); 9612 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9613 ins_encode %{ 9614 Label* L = $labl$$label; 9615 assert(__ use_cbcond(*L), "back to back cbcond"); 9616 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9617 %} 9618 ins_short_branch(1); 9619 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9620 ins_pipe(cbcond_reg_reg); 9621 %} 9622 9623 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9624 match(CountedLoopEnd cmp (CmpI op1 op2)); 9625 predicate(UseCBCond); 9626 effect(USE labl, KILL icc); 9627 9628 size(4); 9629 ins_cost(BRANCH_COST); 9630 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9631 ins_encode %{ 9632 Label* L = $labl$$label; 9633 assert(__ use_cbcond(*L), "back to back cbcond"); 9634 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9635 %} 9636 ins_short_branch(1); 9637 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9638 ins_pipe(cbcond_reg_imm); 9639 %} 9640 9641 // Branch-on-register tests all 64 bits. We assume that values 9642 // in 64-bit registers always remains zero or sign extended 9643 // unless our code munges the high bits. Interrupts can chop 9644 // the high order bits to zero or sign at any time. 9645 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ 9646 match(If cmp (CmpI op1 zero)); 9647 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9648 effect(USE labl); 9649 9650 size(8); 9651 ins_cost(BRANCH_COST); 9652 format %{ "BR$cmp $op1,$labl" %} 9653 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9654 ins_avoid_back_to_back(AVOID_BEFORE); 9655 ins_pipe(br_reg); 9656 %} 9657 9658 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ 9659 match(If cmp (CmpP op1 null)); 9660 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9661 effect(USE labl); 9662 9663 size(8); 9664 ins_cost(BRANCH_COST); 9665 format %{ "BR$cmp $op1,$labl" %} 9666 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9667 ins_avoid_back_to_back(AVOID_BEFORE); 9668 ins_pipe(br_reg); 9669 %} 9670 9671 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ 9672 match(If cmp (CmpL op1 zero)); 9673 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9674 effect(USE labl); 9675 9676 size(8); 9677 ins_cost(BRANCH_COST); 9678 format %{ "BR$cmp $op1,$labl" %} 9679 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9680 ins_avoid_back_to_back(AVOID_BEFORE); 9681 ins_pipe(br_reg); 9682 %} 9683 9684 9685 // ============================================================================ 9686 // Long Compare 9687 // 9688 // Currently we hold longs in 2 registers. Comparing such values efficiently 9689 // is tricky. The flavor of compare used depends on whether we are testing 9690 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 9691 // The GE test is the negated LT test. The LE test can be had by commuting 9692 // the operands (yielding a GE test) and then negating; negate again for the 9693 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the 9694 // NE test is negated from that. 9695 9696 // Due to a shortcoming in the ADLC, it mixes up expressions like: 9697 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9698 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9699 // are collapsed internally in the ADLC's dfa-gen code. The match for 9700 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9701 // foo match ends up with the wrong leaf. One fix is to not match both 9702 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 9703 // both forms beat the trinary form of long-compare and both are very useful 9704 // on Intel which has so few registers. 9705 9706 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ 9707 match(If cmp xcc); 9708 effect(USE labl); 9709 9710 size(8); 9711 ins_cost(BRANCH_COST); 9712 format %{ "BP$cmp $xcc,$labl" %} 9713 ins_encode %{ 9714 Label* L = $labl$$label; 9715 Assembler::Predict predict_taken = 9716 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9717 9718 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9719 __ delayed()->nop(); 9720 %} 9721 ins_avoid_back_to_back(AVOID_BEFORE); 9722 ins_pipe(br_cc); 9723 %} 9724 9725 // Manifest a CmpL3 result in an integer register. Very painful. 9726 // This is the test to avoid. 9727 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ 9728 match(Set dst (CmpL3 src1 src2) ); 9729 effect( KILL ccr ); 9730 ins_cost(6*DEFAULT_COST); 9731 size(24); 9732 format %{ "CMP $src1,$src2\t\t! long\n" 9733 "\tBLT,a,pn done\n" 9734 "\tMOV -1,$dst\t! delay slot\n" 9735 "\tBGT,a,pn done\n" 9736 "\tMOV 1,$dst\t! delay slot\n" 9737 "\tCLR $dst\n" 9738 "done:" %} 9739 ins_encode( cmpl_flag(src1,src2,dst) ); 9740 ins_pipe(cmpL_reg); 9741 %} 9742 9743 // Conditional move 9744 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ 9745 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9746 ins_cost(150); 9747 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9748 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9749 ins_pipe(ialu_reg); 9750 %} 9751 9752 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ 9753 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9754 ins_cost(140); 9755 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9756 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9757 ins_pipe(ialu_imm); 9758 %} 9759 9760 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ 9761 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9762 ins_cost(150); 9763 format %{ "MOV$cmp $xcc,$src,$dst" %} 9764 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9765 ins_pipe(ialu_reg); 9766 %} 9767 9768 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ 9769 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9770 ins_cost(140); 9771 format %{ "MOV$cmp $xcc,$src,$dst" %} 9772 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9773 ins_pipe(ialu_imm); 9774 %} 9775 9776 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ 9777 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); 9778 ins_cost(150); 9779 format %{ "MOV$cmp $xcc,$src,$dst" %} 9780 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9781 ins_pipe(ialu_reg); 9782 %} 9783 9784 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ 9785 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9786 ins_cost(150); 9787 format %{ "MOV$cmp $xcc,$src,$dst" %} 9788 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9789 ins_pipe(ialu_reg); 9790 %} 9791 9792 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ 9793 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9794 ins_cost(140); 9795 format %{ "MOV$cmp $xcc,$src,$dst" %} 9796 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9797 ins_pipe(ialu_imm); 9798 %} 9799 9800 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ 9801 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); 9802 ins_cost(150); 9803 opcode(0x101); 9804 format %{ "FMOVS$cmp $xcc,$src,$dst" %} 9805 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9806 ins_pipe(int_conditional_float_move); 9807 %} 9808 9809 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ 9810 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); 9811 ins_cost(150); 9812 opcode(0x102); 9813 format %{ "FMOVD$cmp $xcc,$src,$dst" %} 9814 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9815 ins_pipe(int_conditional_float_move); 9816 %} 9817 9818 // ============================================================================ 9819 // Safepoint Instruction 9820 instruct safePoint_poll(iRegP poll) %{ 9821 match(SafePoint poll); 9822 effect(USE poll); 9823 9824 size(4); 9825 #ifdef _LP64 9826 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} 9827 #else 9828 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} 9829 #endif 9830 ins_encode %{ 9831 __ relocate(relocInfo::poll_type); 9832 __ ld_ptr($poll$$Register, 0, G0); 9833 %} 9834 ins_pipe(loadPollP); 9835 %} 9836 9837 // ============================================================================ 9838 // Call Instructions 9839 // Call Java Static Instruction 9840 instruct CallStaticJavaDirect( method meth ) %{ 9841 match(CallStaticJava); 9842 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9843 effect(USE meth); 9844 9845 size(8); 9846 ins_cost(CALL_COST); 9847 format %{ "CALL,static ; NOP ==> " %} 9848 ins_encode( Java_Static_Call( meth ), call_epilog ); 9849 ins_avoid_back_to_back(AVOID_BEFORE); 9850 ins_pipe(simple_call); 9851 %} 9852 9853 // Call Java Static Instruction (method handle version) 9854 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ 9855 match(CallStaticJava); 9856 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9857 effect(USE meth, KILL l7_mh_SP_save); 9858 9859 size(16); 9860 ins_cost(CALL_COST); 9861 format %{ "CALL,static/MethodHandle" %} 9862 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); 9863 ins_pipe(simple_call); 9864 %} 9865 9866 // Call Java Dynamic Instruction 9867 instruct CallDynamicJavaDirect( method meth ) %{ 9868 match(CallDynamicJava); 9869 effect(USE meth); 9870 9871 ins_cost(CALL_COST); 9872 format %{ "SET (empty),R_G5\n\t" 9873 "CALL,dynamic ; NOP ==> " %} 9874 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); 9875 ins_pipe(call); 9876 %} 9877 9878 // Call Runtime Instruction 9879 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ 9880 match(CallRuntime); 9881 effect(USE meth, KILL l7); 9882 ins_cost(CALL_COST); 9883 format %{ "CALL,runtime" %} 9884 ins_encode( Java_To_Runtime( meth ), 9885 call_epilog, adjust_long_from_native_call ); 9886 ins_avoid_back_to_back(AVOID_BEFORE); 9887 ins_pipe(simple_call); 9888 %} 9889 9890 // Call runtime without safepoint - same as CallRuntime 9891 instruct CallLeafDirect(method meth, l7RegP l7) %{ 9892 match(CallLeaf); 9893 effect(USE meth, KILL l7); 9894 ins_cost(CALL_COST); 9895 format %{ "CALL,runtime leaf" %} 9896 ins_encode( Java_To_Runtime( meth ), 9897 call_epilog, 9898 adjust_long_from_native_call ); 9899 ins_avoid_back_to_back(AVOID_BEFORE); 9900 ins_pipe(simple_call); 9901 %} 9902 9903 // Call runtime without safepoint - same as CallLeaf 9904 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ 9905 match(CallLeafNoFP); 9906 effect(USE meth, KILL l7); 9907 ins_cost(CALL_COST); 9908 format %{ "CALL,runtime leaf nofp" %} 9909 ins_encode( Java_To_Runtime( meth ), 9910 call_epilog, 9911 adjust_long_from_native_call ); 9912 ins_avoid_back_to_back(AVOID_BEFORE); 9913 ins_pipe(simple_call); 9914 %} 9915 9916 // Tail Call; Jump from runtime stub to Java code. 9917 // Also known as an 'interprocedural jump'. 9918 // Target of jump will eventually return to caller. 9919 // TailJump below removes the return address. 9920 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ 9921 match(TailCall jump_target method_oop ); 9922 9923 ins_cost(CALL_COST); 9924 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} 9925 ins_encode(form_jmpl(jump_target)); 9926 ins_avoid_back_to_back(AVOID_BEFORE); 9927 ins_pipe(tail_call); 9928 %} 9929 9930 9931 // Return Instruction 9932 instruct Ret() %{ 9933 match(Return); 9934 9935 // The epilogue node did the ret already. 9936 size(0); 9937 format %{ "! return" %} 9938 ins_encode(); 9939 ins_pipe(empty); 9940 %} 9941 9942 9943 // Tail Jump; remove the return address; jump to target. 9944 // TailCall above leaves the return address around. 9945 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 9946 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 9947 // "restore" before this instruction (in Epilogue), we need to materialize it 9948 // in %i0. 9949 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ 9950 match( TailJump jump_target ex_oop ); 9951 ins_cost(CALL_COST); 9952 format %{ "! discard R_O7\n\t" 9953 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} 9954 ins_encode(form_jmpl_set_exception_pc(jump_target)); 9955 // opcode(Assembler::jmpl_op3, Assembler::arith_op); 9956 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. 9957 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); 9958 ins_avoid_back_to_back(AVOID_BEFORE); 9959 ins_pipe(tail_call); 9960 %} 9961 9962 // Create exception oop: created by stack-crawling runtime code. 9963 // Created exception is now available to this handler, and is setup 9964 // just prior to jumping to this handler. No code emitted. 9965 instruct CreateException( o0RegP ex_oop ) 9966 %{ 9967 match(Set ex_oop (CreateEx)); 9968 ins_cost(0); 9969 9970 size(0); 9971 // use the following format syntax 9972 format %{ "! exception oop is in R_O0; no code emitted" %} 9973 ins_encode(); 9974 ins_pipe(empty); 9975 %} 9976 9977 9978 // Rethrow exception: 9979 // The exception oop will come in the first argument position. 9980 // Then JUMP (not call) to the rethrow stub code. 9981 instruct RethrowException() 9982 %{ 9983 match(Rethrow); 9984 ins_cost(CALL_COST); 9985 9986 // use the following format syntax 9987 format %{ "Jmp rethrow_stub" %} 9988 ins_encode(enc_rethrow); 9989 ins_avoid_back_to_back(AVOID_BEFORE); 9990 ins_pipe(tail_call); 9991 %} 9992 9993 9994 // Die now 9995 instruct ShouldNotReachHere( ) 9996 %{ 9997 match(Halt); 9998 ins_cost(CALL_COST); 9999 10000 size(4); 10001 // Use the following format syntax 10002 format %{ "ILLTRAP ; ShouldNotReachHere" %} 10003 ins_encode( form2_illtrap() ); 10004 ins_pipe(tail_call); 10005 %} 10006 10007 // ============================================================================ 10008 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 10009 // array for an instance of the superklass. Set a hidden internal cache on a 10010 // hit (cache is checked with exposed code in gen_subtype_check()). Return 10011 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 10012 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ 10013 match(Set index (PartialSubtypeCheck sub super)); 10014 effect( KILL pcc, KILL o7 ); 10015 ins_cost(DEFAULT_COST*10); 10016 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} 10017 ins_encode( enc_PartialSubtypeCheck() ); 10018 ins_avoid_back_to_back(AVOID_BEFORE); 10019 ins_pipe(partial_subtype_check_pipe); 10020 %} 10021 10022 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ 10023 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); 10024 effect( KILL idx, KILL o7 ); 10025 ins_cost(DEFAULT_COST*10); 10026 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} 10027 ins_encode( enc_PartialSubtypeCheck() ); 10028 ins_avoid_back_to_back(AVOID_BEFORE); 10029 ins_pipe(partial_subtype_check_pipe); 10030 %} 10031 10032 10033 // ============================================================================ 10034 // inlined locking and unlocking 10035 10036 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ 10037 match(Set pcc (FastLock object box)); 10038 10039 effect(TEMP scratch2, USE_KILL box, KILL scratch); 10040 ins_cost(100); 10041 10042 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} 10043 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); 10044 ins_pipe(long_memory_op); 10045 %} 10046 10047 10048 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ 10049 match(Set pcc (FastUnlock object box)); 10050 effect(TEMP scratch2, USE_KILL box, KILL scratch); 10051 ins_cost(100); 10052 10053 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} 10054 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); 10055 ins_pipe(long_memory_op); 10056 %} 10057 10058 // The encodings are generic. 10059 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ 10060 predicate(!use_block_zeroing(n->in(2)) ); 10061 match(Set dummy (ClearArray cnt base)); 10062 effect(TEMP temp, KILL ccr); 10063 ins_cost(300); 10064 format %{ "MOV $cnt,$temp\n" 10065 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" 10066 " BRge loop\t\t! Clearing loop\n" 10067 " STX G0,[$base+$temp]\t! delay slot" %} 10068 10069 ins_encode %{ 10070 // Compiler ensures base is doubleword aligned and cnt is count of doublewords 10071 Register nof_bytes_arg = $cnt$$Register; 10072 Register nof_bytes_tmp = $temp$$Register; 10073 Register base_pointer_arg = $base$$Register; 10074 10075 Label loop; 10076 __ mov(nof_bytes_arg, nof_bytes_tmp); 10077 10078 // Loop and clear, walking backwards through the array. 10079 // nof_bytes_tmp (if >0) is always the number of bytes to zero 10080 __ bind(loop); 10081 __ deccc(nof_bytes_tmp, 8); 10082 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); 10083 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); 10084 // %%%% this mini-loop must not cross a cache boundary! 10085 %} 10086 ins_pipe(long_memory_op); 10087 %} 10088 10089 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{ 10090 predicate(use_block_zeroing(n->in(2))); 10091 match(Set dummy (ClearArray cnt base)); 10092 effect(USE_KILL cnt, USE_KILL base, KILL ccr); 10093 ins_cost(300); 10094 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} 10095 10096 ins_encode %{ 10097 10098 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); 10099 Register to = $base$$Register; 10100 Register count = $cnt$$Register; 10101 10102 Label Ldone; 10103 __ nop(); // Separate short branches 10104 // Use BIS for zeroing (temp is not used). 10105 __ bis_zeroing(to, count, G0, Ldone); 10106 __ bind(Ldone); 10107 10108 %} 10109 ins_pipe(long_memory_op); 10110 %} 10111 10112 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{ 10113 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit)); 10114 match(Set dummy (ClearArray cnt base)); 10115 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr); 10116 ins_cost(300); 10117 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} 10118 10119 ins_encode %{ 10120 10121 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); 10122 Register to = $base$$Register; 10123 Register count = $cnt$$Register; 10124 Register temp = $tmp$$Register; 10125 10126 Label Ldone; 10127 __ nop(); // Separate short branches 10128 // Use BIS for zeroing 10129 __ bis_zeroing(to, count, temp, Ldone); 10130 __ bind(Ldone); 10131 10132 %} 10133 ins_pipe(long_memory_op); 10134 %} 10135 10136 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 10137 o7RegI tmp, flagsReg ccr) %{ 10138 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL); 10139 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10140 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 10141 ins_cost(300); 10142 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 10143 ins_encode %{ 10144 __ string_compare($str1$$Register, $str2$$Register, 10145 $cnt1$$Register, $cnt2$$Register, 10146 $tmp$$Register, $tmp$$Register, 10147 $result$$Register, StrIntrinsicNode::LL); 10148 %} 10149 ins_pipe(long_memory_op); 10150 %} 10151 10152 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 10153 o7RegI tmp, flagsReg ccr) %{ 10154 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU); 10155 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10156 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 10157 ins_cost(300); 10158 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 10159 ins_encode %{ 10160 __ string_compare($str1$$Register, $str2$$Register, 10161 $cnt1$$Register, $cnt2$$Register, 10162 $tmp$$Register, $tmp$$Register, 10163 $result$$Register, StrIntrinsicNode::UU); 10164 %} 10165 ins_pipe(long_memory_op); 10166 %} 10167 10168 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 10169 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{ 10170 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU); 10171 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10172 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2); 10173 ins_cost(300); 10174 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %} 10175 ins_encode %{ 10176 __ string_compare($str1$$Register, $str2$$Register, 10177 $cnt1$$Register, $cnt2$$Register, 10178 $tmp1$$Register, $tmp2$$Register, 10179 $result$$Register, StrIntrinsicNode::LU); 10180 %} 10181 ins_pipe(long_memory_op); 10182 %} 10183 10184 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 10185 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{ 10186 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL); 10187 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10188 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2); 10189 ins_cost(300); 10190 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %} 10191 ins_encode %{ 10192 __ string_compare($str2$$Register, $str1$$Register, 10193 $cnt2$$Register, $cnt1$$Register, 10194 $tmp1$$Register, $tmp2$$Register, 10195 $result$$Register, StrIntrinsicNode::UL); 10196 %} 10197 ins_pipe(long_memory_op); 10198 %} 10199 10200 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 10201 o7RegI tmp, flagsReg ccr) %{ 10202 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL); 10203 match(Set result (StrEquals (Binary str1 str2) cnt)); 10204 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 10205 ins_cost(300); 10206 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result // KILL $tmp" %} 10207 ins_encode %{ 10208 __ array_equals(false, $str1$$Register, $str2$$Register, 10209 $cnt$$Register, $tmp$$Register, 10210 $result$$Register, true /* byte */); 10211 %} 10212 ins_pipe(long_memory_op); 10213 %} 10214 10215 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 10216 o7RegI tmp, flagsReg ccr) %{ 10217 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU); 10218 match(Set result (StrEquals (Binary str1 str2) cnt)); 10219 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 10220 ins_cost(300); 10221 format %{ "String Equals char[] $str1,$str2,$cnt -> $result // KILL $tmp" %} 10222 ins_encode %{ 10223 __ array_equals(false, $str1$$Register, $str2$$Register, 10224 $cnt$$Register, $tmp$$Register, 10225 $result$$Register, false /* byte */); 10226 %} 10227 ins_pipe(long_memory_op); 10228 %} 10229 10230 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 10231 o7RegI tmp2, flagsReg ccr) %{ 10232 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL); 10233 match(Set result (AryEq ary1 ary2)); 10234 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 10235 ins_cost(300); 10236 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 10237 ins_encode %{ 10238 __ array_equals(true, $ary1$$Register, $ary2$$Register, 10239 $tmp1$$Register, $tmp2$$Register, 10240 $result$$Register, true /* byte */); 10241 %} 10242 ins_pipe(long_memory_op); 10243 %} 10244 10245 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 10246 o7RegI tmp2, flagsReg ccr) %{ 10247 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU); 10248 match(Set result (AryEq ary1 ary2)); 10249 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 10250 ins_cost(300); 10251 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 10252 ins_encode %{ 10253 __ array_equals(true, $ary1$$Register, $ary2$$Register, 10254 $tmp1$$Register, $tmp2$$Register, 10255 $result$$Register, false /* byte */); 10256 %} 10257 ins_pipe(long_memory_op); 10258 %} 10259 10260 instruct has_negatives(o0RegP pAryR, g3RegI iSizeR, notemp_iRegI resultR, 10261 iRegL tmp1L, iRegL tmp2L, iRegL tmp3L, iRegL tmp4L, 10262 flagsReg ccr) 10263 %{ 10264 match(Set resultR (HasNegatives pAryR iSizeR)); 10265 effect(TEMP resultR, TEMP tmp1L, TEMP tmp2L, TEMP tmp3L, TEMP tmp4L, USE pAryR, USE iSizeR, KILL ccr); 10266 format %{ "has negatives byte[] $pAryR,$iSizeR -> $resultR // KILL $tmp1L,$tmp2L,$tmp3L,$tmp4L" %} 10267 ins_encode %{ 10268 __ has_negatives($pAryR$$Register, $iSizeR$$Register, 10269 $resultR$$Register, 10270 $tmp1L$$Register, $tmp2L$$Register, 10271 $tmp3L$$Register, $tmp4L$$Register); 10272 %} 10273 ins_pipe(long_memory_op); 10274 %} 10275 10276 // char[] to byte[] compression 10277 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{ 10278 predicate(UseVIS < 3); 10279 match(Set result (StrCompressedCopy src (Binary dst len))); 10280 effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 10281 ins_cost(300); 10282 format %{ "String Compress $src,$dst,$len -> $result // KILL $tmp" %} 10283 ins_encode %{ 10284 Label Ldone; 10285 __ signx($len$$Register); 10286 __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn); 10287 __ delayed()->mov($len$$Register, $result$$Register); // copy count 10288 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone); 10289 __ bind(Ldone); 10290 %} 10291 ins_pipe(long_memory_op); 10292 %} 10293 10294 // fast char[] to byte[] compression using VIS instructions 10295 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, 10296 iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4, 10297 regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{ 10298 predicate(UseVIS >= 3); 10299 match(Set result (StrCompressedCopy src (Binary dst len))); 10300 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 10301 ins_cost(300); 10302 format %{ "String Compress Fast $src,$dst,$len -> $result // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %} 10303 ins_encode %{ 10304 Label Ldone; 10305 __ signx($len$$Register); 10306 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register, 10307 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, 10308 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone); 10309 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone); 10310 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone); 10311 __ bind(Ldone); 10312 %} 10313 ins_pipe(long_memory_op); 10314 %} 10315 10316 // byte[] to char[] inflation 10317 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len, 10318 iRegL tmp, flagsReg ccr) %{ 10319 match(Set dummy (StrInflatedCopy src (Binary dst len))); 10320 effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 10321 ins_cost(300); 10322 format %{ "String Inflate $src,$dst,$len // KILL $tmp" %} 10323 ins_encode %{ 10324 Label Ldone; 10325 __ signx($len$$Register); 10326 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone); 10327 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone); 10328 __ bind(Ldone); 10329 %} 10330 ins_pipe(long_memory_op); 10331 %} 10332 10333 // fast byte[] to char[] inflation using VIS instructions 10334 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len, 10335 iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{ 10336 predicate(UseVIS >= 3); 10337 match(Set dummy (StrInflatedCopy src (Binary dst len))); 10338 effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 10339 ins_cost(300); 10340 format %{ "String Inflate Fast $src,$dst,$len // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %} 10341 ins_encode %{ 10342 Label Ldone; 10343 __ signx($len$$Register); 10344 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, 10345 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone); 10346 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone); 10347 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone); 10348 __ bind(Ldone); 10349 %} 10350 ins_pipe(long_memory_op); 10351 %} 10352 10353 10354 //---------- Zeros Count Instructions ------------------------------------------ 10355 10356 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{ 10357 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10358 match(Set dst (CountLeadingZerosI src)); 10359 effect(TEMP dst, TEMP tmp, KILL cr); 10360 10361 // x |= (x >> 1); 10362 // x |= (x >> 2); 10363 // x |= (x >> 4); 10364 // x |= (x >> 8); 10365 // x |= (x >> 16); 10366 // return (WORDBITS - popc(x)); 10367 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" 10368 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" 10369 "OR $dst,$tmp,$dst\n\t" 10370 "SRL $dst,2,$tmp\n\t" 10371 "OR $dst,$tmp,$dst\n\t" 10372 "SRL $dst,4,$tmp\n\t" 10373 "OR $dst,$tmp,$dst\n\t" 10374 "SRL $dst,8,$tmp\n\t" 10375 "OR $dst,$tmp,$dst\n\t" 10376 "SRL $dst,16,$tmp\n\t" 10377 "OR $dst,$tmp,$dst\n\t" 10378 "POPC $dst,$dst\n\t" 10379 "MOV 32,$tmp\n\t" 10380 "SUB $tmp,$dst,$dst" %} 10381 ins_encode %{ 10382 Register Rdst = $dst$$Register; 10383 Register Rsrc = $src$$Register; 10384 Register Rtmp = $tmp$$Register; 10385 __ srl(Rsrc, 1, Rtmp); 10386 __ srl(Rsrc, 0, Rdst); 10387 __ or3(Rdst, Rtmp, Rdst); 10388 __ srl(Rdst, 2, Rtmp); 10389 __ or3(Rdst, Rtmp, Rdst); 10390 __ srl(Rdst, 4, Rtmp); 10391 __ or3(Rdst, Rtmp, Rdst); 10392 __ srl(Rdst, 8, Rtmp); 10393 __ or3(Rdst, Rtmp, Rdst); 10394 __ srl(Rdst, 16, Rtmp); 10395 __ or3(Rdst, Rtmp, Rdst); 10396 __ popc(Rdst, Rdst); 10397 __ mov(BitsPerInt, Rtmp); 10398 __ sub(Rtmp, Rdst, Rdst); 10399 %} 10400 ins_pipe(ialu_reg); 10401 %} 10402 10403 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ 10404 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10405 match(Set dst (CountLeadingZerosL src)); 10406 effect(TEMP dst, TEMP tmp, KILL cr); 10407 10408 // x |= (x >> 1); 10409 // x |= (x >> 2); 10410 // x |= (x >> 4); 10411 // x |= (x >> 8); 10412 // x |= (x >> 16); 10413 // x |= (x >> 32); 10414 // return (WORDBITS - popc(x)); 10415 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" 10416 "OR $src,$tmp,$dst\n\t" 10417 "SRLX $dst,2,$tmp\n\t" 10418 "OR $dst,$tmp,$dst\n\t" 10419 "SRLX $dst,4,$tmp\n\t" 10420 "OR $dst,$tmp,$dst\n\t" 10421 "SRLX $dst,8,$tmp\n\t" 10422 "OR $dst,$tmp,$dst\n\t" 10423 "SRLX $dst,16,$tmp\n\t" 10424 "OR $dst,$tmp,$dst\n\t" 10425 "SRLX $dst,32,$tmp\n\t" 10426 "OR $dst,$tmp,$dst\n\t" 10427 "POPC $dst,$dst\n\t" 10428 "MOV 64,$tmp\n\t" 10429 "SUB $tmp,$dst,$dst" %} 10430 ins_encode %{ 10431 Register Rdst = $dst$$Register; 10432 Register Rsrc = $src$$Register; 10433 Register Rtmp = $tmp$$Register; 10434 __ srlx(Rsrc, 1, Rtmp); 10435 __ or3( Rsrc, Rtmp, Rdst); 10436 __ srlx(Rdst, 2, Rtmp); 10437 __ or3( Rdst, Rtmp, Rdst); 10438 __ srlx(Rdst, 4, Rtmp); 10439 __ or3( Rdst, Rtmp, Rdst); 10440 __ srlx(Rdst, 8, Rtmp); 10441 __ or3( Rdst, Rtmp, Rdst); 10442 __ srlx(Rdst, 16, Rtmp); 10443 __ or3( Rdst, Rtmp, Rdst); 10444 __ srlx(Rdst, 32, Rtmp); 10445 __ or3( Rdst, Rtmp, Rdst); 10446 __ popc(Rdst, Rdst); 10447 __ mov(BitsPerLong, Rtmp); 10448 __ sub(Rtmp, Rdst, Rdst); 10449 %} 10450 ins_pipe(ialu_reg); 10451 %} 10452 10453 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{ 10454 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10455 match(Set dst (CountTrailingZerosI src)); 10456 effect(TEMP dst, KILL cr); 10457 10458 // return popc(~x & (x - 1)); 10459 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" 10460 "ANDN $dst,$src,$dst\n\t" 10461 "SRL $dst,R_G0,$dst\n\t" 10462 "POPC $dst,$dst" %} 10463 ins_encode %{ 10464 Register Rdst = $dst$$Register; 10465 Register Rsrc = $src$$Register; 10466 __ sub(Rsrc, 1, Rdst); 10467 __ andn(Rdst, Rsrc, Rdst); 10468 __ srl(Rdst, G0, Rdst); 10469 __ popc(Rdst, Rdst); 10470 %} 10471 ins_pipe(ialu_reg); 10472 %} 10473 10474 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{ 10475 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10476 match(Set dst (CountTrailingZerosL src)); 10477 effect(TEMP dst, KILL cr); 10478 10479 // return popc(~x & (x - 1)); 10480 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" 10481 "ANDN $dst,$src,$dst\n\t" 10482 "POPC $dst,$dst" %} 10483 ins_encode %{ 10484 Register Rdst = $dst$$Register; 10485 Register Rsrc = $src$$Register; 10486 __ sub(Rsrc, 1, Rdst); 10487 __ andn(Rdst, Rsrc, Rdst); 10488 __ popc(Rdst, Rdst); 10489 %} 10490 ins_pipe(ialu_reg); 10491 %} 10492 10493 10494 //---------- Population Count Instructions ------------------------------------- 10495 10496 instruct popCountI(iRegIsafe dst, iRegI src) %{ 10497 predicate(UsePopCountInstruction); 10498 match(Set dst (PopCountI src)); 10499 10500 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t" 10501 "POPC $dst, $dst" %} 10502 ins_encode %{ 10503 __ srl($src$$Register, G0, $dst$$Register); 10504 __ popc($dst$$Register, $dst$$Register); 10505 %} 10506 ins_pipe(ialu_reg); 10507 %} 10508 10509 // Note: Long.bitCount(long) returns an int. 10510 instruct popCountL(iRegIsafe dst, iRegL src) %{ 10511 predicate(UsePopCountInstruction); 10512 match(Set dst (PopCountL src)); 10513 10514 format %{ "POPC $src, $dst" %} 10515 ins_encode %{ 10516 __ popc($src$$Register, $dst$$Register); 10517 %} 10518 ins_pipe(ialu_reg); 10519 %} 10520 10521 10522 // ============================================================================ 10523 //------------Bytes reverse-------------------------------------------------- 10524 10525 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ 10526 match(Set dst (ReverseBytesI src)); 10527 10528 // Op cost is artificially doubled to make sure that load or store 10529 // instructions are preferred over this one which requires a spill 10530 // onto a stack slot. 10531 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10532 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10533 10534 ins_encode %{ 10535 __ set($src$$disp + STACK_BIAS, O7); 10536 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10537 %} 10538 ins_pipe( iload_mem ); 10539 %} 10540 10541 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ 10542 match(Set dst (ReverseBytesL src)); 10543 10544 // Op cost is artificially doubled to make sure that load or store 10545 // instructions are preferred over this one which requires a spill 10546 // onto a stack slot. 10547 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10548 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10549 10550 ins_encode %{ 10551 __ set($src$$disp + STACK_BIAS, O7); 10552 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10553 %} 10554 ins_pipe( iload_mem ); 10555 %} 10556 10557 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ 10558 match(Set dst (ReverseBytesUS src)); 10559 10560 // Op cost is artificially doubled to make sure that load or store 10561 // instructions are preferred over this one which requires a spill 10562 // onto a stack slot. 10563 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10564 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} 10565 10566 ins_encode %{ 10567 // the value was spilled as an int so bias the load 10568 __ set($src$$disp + STACK_BIAS + 2, O7); 10569 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10570 %} 10571 ins_pipe( iload_mem ); 10572 %} 10573 10574 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ 10575 match(Set dst (ReverseBytesS src)); 10576 10577 // Op cost is artificially doubled to make sure that load or store 10578 // instructions are preferred over this one which requires a spill 10579 // onto a stack slot. 10580 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10581 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} 10582 10583 ins_encode %{ 10584 // the value was spilled as an int so bias the load 10585 __ set($src$$disp + STACK_BIAS + 2, O7); 10586 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10587 %} 10588 ins_pipe( iload_mem ); 10589 %} 10590 10591 // Load Integer reversed byte order 10592 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ 10593 match(Set dst (ReverseBytesI (LoadI src))); 10594 10595 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 10596 size(4); 10597 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10598 10599 ins_encode %{ 10600 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10601 %} 10602 ins_pipe(iload_mem); 10603 %} 10604 10605 // Load Long - aligned and reversed 10606 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ 10607 match(Set dst (ReverseBytesL (LoadL src))); 10608 10609 ins_cost(MEMORY_REF_COST); 10610 size(4); 10611 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10612 10613 ins_encode %{ 10614 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10615 %} 10616 ins_pipe(iload_mem); 10617 %} 10618 10619 // Load unsigned short / char reversed byte order 10620 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ 10621 match(Set dst (ReverseBytesUS (LoadUS src))); 10622 10623 ins_cost(MEMORY_REF_COST); 10624 size(4); 10625 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} 10626 10627 ins_encode %{ 10628 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10629 %} 10630 ins_pipe(iload_mem); 10631 %} 10632 10633 // Load short reversed byte order 10634 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ 10635 match(Set dst (ReverseBytesS (LoadS src))); 10636 10637 ins_cost(MEMORY_REF_COST); 10638 size(4); 10639 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} 10640 10641 ins_encode %{ 10642 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10643 %} 10644 ins_pipe(iload_mem); 10645 %} 10646 10647 // Store Integer reversed byte order 10648 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ 10649 match(Set dst (StoreI dst (ReverseBytesI src))); 10650 10651 ins_cost(MEMORY_REF_COST); 10652 size(4); 10653 format %{ "STWA $src, $dst\t!asi=primary_little" %} 10654 10655 ins_encode %{ 10656 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10657 %} 10658 ins_pipe(istore_mem_reg); 10659 %} 10660 10661 // Store Long reversed byte order 10662 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ 10663 match(Set dst (StoreL dst (ReverseBytesL src))); 10664 10665 ins_cost(MEMORY_REF_COST); 10666 size(4); 10667 format %{ "STXA $src, $dst\t!asi=primary_little" %} 10668 10669 ins_encode %{ 10670 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10671 %} 10672 ins_pipe(istore_mem_reg); 10673 %} 10674 10675 // Store unsighed short/char reversed byte order 10676 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ 10677 match(Set dst (StoreC dst (ReverseBytesUS src))); 10678 10679 ins_cost(MEMORY_REF_COST); 10680 size(4); 10681 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10682 10683 ins_encode %{ 10684 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10685 %} 10686 ins_pipe(istore_mem_reg); 10687 %} 10688 10689 // Store short reversed byte order 10690 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ 10691 match(Set dst (StoreC dst (ReverseBytesS src))); 10692 10693 ins_cost(MEMORY_REF_COST); 10694 size(4); 10695 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10696 10697 ins_encode %{ 10698 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10699 %} 10700 ins_pipe(istore_mem_reg); 10701 %} 10702 10703 // ====================VECTOR INSTRUCTIONS===================================== 10704 10705 // Load Aligned Packed values into a Double Register 10706 instruct loadV8(regD dst, memory mem) %{ 10707 predicate(n->as_LoadVector()->memory_size() == 8); 10708 match(Set dst (LoadVector mem)); 10709 ins_cost(MEMORY_REF_COST); 10710 size(4); 10711 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %} 10712 ins_encode %{ 10713 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg)); 10714 %} 10715 ins_pipe(floadD_mem); 10716 %} 10717 10718 // Store Vector in Double register to memory 10719 instruct storeV8(memory mem, regD src) %{ 10720 predicate(n->as_StoreVector()->memory_size() == 8); 10721 match(Set mem (StoreVector mem src)); 10722 ins_cost(MEMORY_REF_COST); 10723 size(4); 10724 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %} 10725 ins_encode %{ 10726 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address); 10727 %} 10728 ins_pipe(fstoreD_mem_reg); 10729 %} 10730 10731 // Store Zero into vector in memory 10732 instruct storeV8B_zero(memory mem, immI0 zero) %{ 10733 predicate(n->as_StoreVector()->memory_size() == 8); 10734 match(Set mem (StoreVector mem (ReplicateB zero))); 10735 ins_cost(MEMORY_REF_COST); 10736 size(4); 10737 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %} 10738 ins_encode %{ 10739 __ stx(G0, $mem$$Address); 10740 %} 10741 ins_pipe(fstoreD_mem_zero); 10742 %} 10743 10744 instruct storeV4S_zero(memory mem, immI0 zero) %{ 10745 predicate(n->as_StoreVector()->memory_size() == 8); 10746 match(Set mem (StoreVector mem (ReplicateS zero))); 10747 ins_cost(MEMORY_REF_COST); 10748 size(4); 10749 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %} 10750 ins_encode %{ 10751 __ stx(G0, $mem$$Address); 10752 %} 10753 ins_pipe(fstoreD_mem_zero); 10754 %} 10755 10756 instruct storeV2I_zero(memory mem, immI0 zero) %{ 10757 predicate(n->as_StoreVector()->memory_size() == 8); 10758 match(Set mem (StoreVector mem (ReplicateI zero))); 10759 ins_cost(MEMORY_REF_COST); 10760 size(4); 10761 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %} 10762 ins_encode %{ 10763 __ stx(G0, $mem$$Address); 10764 %} 10765 ins_pipe(fstoreD_mem_zero); 10766 %} 10767 10768 instruct storeV2F_zero(memory mem, immF0 zero) %{ 10769 predicate(n->as_StoreVector()->memory_size() == 8); 10770 match(Set mem (StoreVector mem (ReplicateF zero))); 10771 ins_cost(MEMORY_REF_COST); 10772 size(4); 10773 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %} 10774 ins_encode %{ 10775 __ stx(G0, $mem$$Address); 10776 %} 10777 ins_pipe(fstoreD_mem_zero); 10778 %} 10779 10780 // Replicate scalar to packed byte values into Double register 10781 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10782 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3); 10783 match(Set dst (ReplicateB src)); 10784 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10785 format %{ "SLLX $src,56,$tmp\n\t" 10786 "SRLX $tmp, 8,$tmp2\n\t" 10787 "OR $tmp,$tmp2,$tmp\n\t" 10788 "SRLX $tmp,16,$tmp2\n\t" 10789 "OR $tmp,$tmp2,$tmp\n\t" 10790 "SRLX $tmp,32,$tmp2\n\t" 10791 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" 10792 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10793 ins_encode %{ 10794 Register Rsrc = $src$$Register; 10795 Register Rtmp = $tmp$$Register; 10796 Register Rtmp2 = $tmp2$$Register; 10797 __ sllx(Rsrc, 56, Rtmp); 10798 __ srlx(Rtmp, 8, Rtmp2); 10799 __ or3 (Rtmp, Rtmp2, Rtmp); 10800 __ srlx(Rtmp, 16, Rtmp2); 10801 __ or3 (Rtmp, Rtmp2, Rtmp); 10802 __ srlx(Rtmp, 32, Rtmp2); 10803 __ or3 (Rtmp, Rtmp2, Rtmp); 10804 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10805 %} 10806 ins_pipe(ialu_reg); 10807 %} 10808 10809 // Replicate scalar to packed byte values into Double stack 10810 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10811 predicate(n->as_Vector()->length() == 8 && UseVIS < 3); 10812 match(Set dst (ReplicateB src)); 10813 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10814 format %{ "SLLX $src,56,$tmp\n\t" 10815 "SRLX $tmp, 8,$tmp2\n\t" 10816 "OR $tmp,$tmp2,$tmp\n\t" 10817 "SRLX $tmp,16,$tmp2\n\t" 10818 "OR $tmp,$tmp2,$tmp\n\t" 10819 "SRLX $tmp,32,$tmp2\n\t" 10820 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" 10821 "STX $tmp,$dst\t! regL to stkD" %} 10822 ins_encode %{ 10823 Register Rsrc = $src$$Register; 10824 Register Rtmp = $tmp$$Register; 10825 Register Rtmp2 = $tmp2$$Register; 10826 __ sllx(Rsrc, 56, Rtmp); 10827 __ srlx(Rtmp, 8, Rtmp2); 10828 __ or3 (Rtmp, Rtmp2, Rtmp); 10829 __ srlx(Rtmp, 16, Rtmp2); 10830 __ or3 (Rtmp, Rtmp2, Rtmp); 10831 __ srlx(Rtmp, 32, Rtmp2); 10832 __ or3 (Rtmp, Rtmp2, Rtmp); 10833 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10834 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10835 %} 10836 ins_pipe(ialu_reg); 10837 %} 10838 10839 // Replicate scalar constant to packed byte values in Double register 10840 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ 10841 predicate(n->as_Vector()->length() == 8); 10842 match(Set dst (ReplicateB con)); 10843 effect(KILL tmp); 10844 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} 10845 ins_encode %{ 10846 // XXX This is a quick fix for 6833573. 10847 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); 10848 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); 10849 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10850 %} 10851 ins_pipe(loadConFD); 10852 %} 10853 10854 // Replicate scalar to packed char/short values into Double register 10855 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10856 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3); 10857 match(Set dst (ReplicateS src)); 10858 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10859 format %{ "SLLX $src,48,$tmp\n\t" 10860 "SRLX $tmp,16,$tmp2\n\t" 10861 "OR $tmp,$tmp2,$tmp\n\t" 10862 "SRLX $tmp,32,$tmp2\n\t" 10863 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" 10864 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10865 ins_encode %{ 10866 Register Rsrc = $src$$Register; 10867 Register Rtmp = $tmp$$Register; 10868 Register Rtmp2 = $tmp2$$Register; 10869 __ sllx(Rsrc, 48, Rtmp); 10870 __ srlx(Rtmp, 16, Rtmp2); 10871 __ or3 (Rtmp, Rtmp2, Rtmp); 10872 __ srlx(Rtmp, 32, Rtmp2); 10873 __ or3 (Rtmp, Rtmp2, Rtmp); 10874 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10875 %} 10876 ins_pipe(ialu_reg); 10877 %} 10878 10879 // Replicate scalar to packed char/short values into Double stack 10880 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10881 predicate(n->as_Vector()->length() == 4 && UseVIS < 3); 10882 match(Set dst (ReplicateS src)); 10883 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10884 format %{ "SLLX $src,48,$tmp\n\t" 10885 "SRLX $tmp,16,$tmp2\n\t" 10886 "OR $tmp,$tmp2,$tmp\n\t" 10887 "SRLX $tmp,32,$tmp2\n\t" 10888 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" 10889 "STX $tmp,$dst\t! regL to stkD" %} 10890 ins_encode %{ 10891 Register Rsrc = $src$$Register; 10892 Register Rtmp = $tmp$$Register; 10893 Register Rtmp2 = $tmp2$$Register; 10894 __ sllx(Rsrc, 48, Rtmp); 10895 __ srlx(Rtmp, 16, Rtmp2); 10896 __ or3 (Rtmp, Rtmp2, Rtmp); 10897 __ srlx(Rtmp, 32, Rtmp2); 10898 __ or3 (Rtmp, Rtmp2, Rtmp); 10899 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10900 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10901 %} 10902 ins_pipe(ialu_reg); 10903 %} 10904 10905 // Replicate scalar constant to packed char/short values in Double register 10906 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ 10907 predicate(n->as_Vector()->length() == 4); 10908 match(Set dst (ReplicateS con)); 10909 effect(KILL tmp); 10910 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} 10911 ins_encode %{ 10912 // XXX This is a quick fix for 6833573. 10913 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); 10914 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); 10915 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10916 %} 10917 ins_pipe(loadConFD); 10918 %} 10919 10920 // Replicate scalar to packed int values into Double register 10921 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10922 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3); 10923 match(Set dst (ReplicateI src)); 10924 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10925 format %{ "SLLX $src,32,$tmp\n\t" 10926 "SRLX $tmp,32,$tmp2\n\t" 10927 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" 10928 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10929 ins_encode %{ 10930 Register Rsrc = $src$$Register; 10931 Register Rtmp = $tmp$$Register; 10932 Register Rtmp2 = $tmp2$$Register; 10933 __ sllx(Rsrc, 32, Rtmp); 10934 __ srlx(Rtmp, 32, Rtmp2); 10935 __ or3 (Rtmp, Rtmp2, Rtmp); 10936 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10937 %} 10938 ins_pipe(ialu_reg); 10939 %} 10940 10941 // Replicate scalar to packed int values into Double stack 10942 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10943 predicate(n->as_Vector()->length() == 2 && UseVIS < 3); 10944 match(Set dst (ReplicateI src)); 10945 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10946 format %{ "SLLX $src,32,$tmp\n\t" 10947 "SRLX $tmp,32,$tmp2\n\t" 10948 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" 10949 "STX $tmp,$dst\t! regL to stkD" %} 10950 ins_encode %{ 10951 Register Rsrc = $src$$Register; 10952 Register Rtmp = $tmp$$Register; 10953 Register Rtmp2 = $tmp2$$Register; 10954 __ sllx(Rsrc, 32, Rtmp); 10955 __ srlx(Rtmp, 32, Rtmp2); 10956 __ or3 (Rtmp, Rtmp2, Rtmp); 10957 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10958 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10959 %} 10960 ins_pipe(ialu_reg); 10961 %} 10962 10963 // Replicate scalar zero constant to packed int values in Double register 10964 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ 10965 predicate(n->as_Vector()->length() == 2); 10966 match(Set dst (ReplicateI con)); 10967 effect(KILL tmp); 10968 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} 10969 ins_encode %{ 10970 // XXX This is a quick fix for 6833573. 10971 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); 10972 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); 10973 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10974 %} 10975 ins_pipe(loadConFD); 10976 %} 10977 10978 // Replicate scalar to packed float values into Double stack 10979 instruct Repl2F_stk(stackSlotD dst, regF src) %{ 10980 predicate(n->as_Vector()->length() == 2); 10981 match(Set dst (ReplicateF src)); 10982 ins_cost(MEMORY_REF_COST*2); 10983 format %{ "STF $src,$dst.hi\t! packed2F\n\t" 10984 "STF $src,$dst.lo" %} 10985 opcode(Assembler::stf_op3); 10986 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src)); 10987 ins_pipe(fstoreF_stk_reg); 10988 %} 10989 10990 // Replicate scalar zero constant to packed float values in Double register 10991 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{ 10992 predicate(n->as_Vector()->length() == 2); 10993 match(Set dst (ReplicateF con)); 10994 effect(KILL tmp); 10995 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %} 10996 ins_encode %{ 10997 // XXX This is a quick fix for 6833573. 10998 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister); 10999 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register); 11000 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 11001 %} 11002 ins_pipe(loadConFD); 11003 %} 11004 11005 //----------PEEPHOLE RULES----------------------------------------------------- 11006 // These must follow all instruction definitions as they use the names 11007 // defined in the instructions definitions. 11008 // 11009 // peepmatch ( root_instr_name [preceding_instruction]* ); 11010 // 11011 // peepconstraint %{ 11012 // (instruction_number.operand_name relational_op instruction_number.operand_name 11013 // [, ...] ); 11014 // // instruction numbers are zero-based using left to right order in peepmatch 11015 // 11016 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 11017 // // provide an instruction_number.operand_name for each operand that appears 11018 // // in the replacement instruction's match rule 11019 // 11020 // ---------VM FLAGS--------------------------------------------------------- 11021 // 11022 // All peephole optimizations can be turned off using -XX:-OptoPeephole 11023 // 11024 // Each peephole rule is given an identifying number starting with zero and 11025 // increasing by one in the order seen by the parser. An individual peephole 11026 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 11027 // on the command-line. 11028 // 11029 // ---------CURRENT LIMITATIONS---------------------------------------------- 11030 // 11031 // Only match adjacent instructions in same basic block 11032 // Only equality constraints 11033 // Only constraints between operands, not (0.dest_reg == EAX_enc) 11034 // Only one replacement instruction 11035 // 11036 // ---------EXAMPLE---------------------------------------------------------- 11037 // 11038 // // pertinent parts of existing instructions in architecture description 11039 // instruct movI(eRegI dst, eRegI src) %{ 11040 // match(Set dst (CopyI src)); 11041 // %} 11042 // 11043 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 11044 // match(Set dst (AddI dst src)); 11045 // effect(KILL cr); 11046 // %} 11047 // 11048 // // Change (inc mov) to lea 11049 // peephole %{ 11050 // // increment preceeded by register-register move 11051 // peepmatch ( incI_eReg movI ); 11052 // // require that the destination register of the increment 11053 // // match the destination register of the move 11054 // peepconstraint ( 0.dst == 1.dst ); 11055 // // construct a replacement instruction that sets 11056 // // the destination to ( move's source register + one ) 11057 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); 11058 // %} 11059 // 11060 11061 // // Change load of spilled value to only a spill 11062 // instruct storeI(memory mem, eRegI src) %{ 11063 // match(Set mem (StoreI mem src)); 11064 // %} 11065 // 11066 // instruct loadI(eRegI dst, memory mem) %{ 11067 // match(Set dst (LoadI mem)); 11068 // %} 11069 // 11070 // peephole %{ 11071 // peepmatch ( loadI storeI ); 11072 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 11073 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 11074 // %} 11075 11076 //----------SMARTSPILL RULES--------------------------------------------------- 11077 // These must follow all instruction definitions as they use the names 11078 // defined in the instructions definitions. 11079 // 11080 // SPARC will probably not have any of these rules due to RISC instruction set. 11081 11082 //----------PIPELINE----------------------------------------------------------- 11083 // Rules which define the behavior of the target architectures pipeline.