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src/cpu/sparc/vm/vm_version_sparc.cpp

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   1 /*
   2  * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *


  53     if (AllocatePrefetchInstr == 1) {
  54       warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
  55       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
  56     }
  57   }
  58 
  59   UseSSE = 0; // Only on x86 and x64
  60 
  61   _supports_cx8 = has_v9();
  62   _supports_atomic_getset4 = true; // swap instruction
  63 
  64   if (is_niagara()) {
  65     // Indirect branch is the same cost as direct
  66     if (FLAG_IS_DEFAULT(UseInlineCaches)) {
  67       FLAG_SET_DEFAULT(UseInlineCaches, false);
  68     }
  69     // Align loops on a single instruction boundary.
  70     if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
  71       FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
  72     }
  73 #ifdef _LP64
  74     // 32-bit oops don't make sense for the 64-bit VM on sparc
  75     // since the 32-bit VM has the same registers and smaller objects.
  76     Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
  77     Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
  78 #endif // _LP64
  79 #ifdef COMPILER2
  80     // Indirect branch is the same cost as direct
  81     if (FLAG_IS_DEFAULT(UseJumpTables)) {
  82       FLAG_SET_DEFAULT(UseJumpTables, true);
  83     }
  84     // Single-issue, so entry and loop tops are
  85     // aligned on a single instruction boundary
  86     if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
  87       FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
  88     }
  89     if (is_niagara_plus()) {
  90       if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
  91           FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
  92         if (!has_sparc5_instr()) {
  93           // Use BIS instruction for TLAB allocation prefetch
  94           // on Niagara plus processors other than those based on CoreS4
  95           FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
  96         } else {
  97           // On CoreS4 processors use prefetch instruction
  98           // to avoid partial RAW issue, also use prefetch style 3


   1 /*
   2  * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *


  53     if (AllocatePrefetchInstr == 1) {
  54       warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
  55       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
  56     }
  57   }
  58 
  59   UseSSE = 0; // Only on x86 and x64
  60 
  61   _supports_cx8 = has_v9();
  62   _supports_atomic_getset4 = true; // swap instruction
  63 
  64   if (is_niagara()) {
  65     // Indirect branch is the same cost as direct
  66     if (FLAG_IS_DEFAULT(UseInlineCaches)) {
  67       FLAG_SET_DEFAULT(UseInlineCaches, false);
  68     }
  69     // Align loops on a single instruction boundary.
  70     if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
  71       FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
  72     }

  73     // 32-bit oops don't make sense for the 64-bit VM on sparc
  74     // since the 32-bit VM has the same registers and smaller objects.
  75     Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
  76     Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);

  77 #ifdef COMPILER2
  78     // Indirect branch is the same cost as direct
  79     if (FLAG_IS_DEFAULT(UseJumpTables)) {
  80       FLAG_SET_DEFAULT(UseJumpTables, true);
  81     }
  82     // Single-issue, so entry and loop tops are
  83     // aligned on a single instruction boundary
  84     if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
  85       FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
  86     }
  87     if (is_niagara_plus()) {
  88       if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
  89           FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
  90         if (!has_sparc5_instr()) {
  91           // Use BIS instruction for TLAB allocation prefetch
  92           // on Niagara plus processors other than those based on CoreS4
  93           FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
  94         } else {
  95           // On CoreS4 processors use prefetch instruction
  96           // to avoid partial RAW issue, also use prefetch style 3


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