31   return FrameMap::nr2floatreg(fpu_regnr());
  32 }
  33 
  34 FloatRegister LIR_OprDesc::as_double_reg() const {
  35   return FrameMap::nr2floatreg(fpu_regnrHi());
  36 }
  37 
  38 LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
  39   assert(as_FloatRegister(reg2) != fnoreg, "Sparc holds double in two regs.");
  40   return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
  41                              (reg2 << LIR_OprDesc::reg2_shift) |
  42                              LIR_OprDesc::double_type          |
  43                              LIR_OprDesc::fpu_register         |
  44                              LIR_OprDesc::double_size);
  45 }
  46 
  47 #ifndef PRODUCT
  48 void LIR_Address::verify() const {
  49   assert(scale() == times_1, "Scaled addressing mode not available on SPARC and should not be used");
  50   assert(disp() == 0 || index()->is_illegal(), "can't have both");
  51 #ifdef _LP64
  52   assert(base()->is_cpu_register(), "wrong base operand");
  53   assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
  54   assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
  55          "wrong type for addresses");
  56 #else
  57   assert(base()->is_single_cpu(), "wrong base operand");
  58   assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
  59   assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
  60          "wrong type for addresses");
  61 #endif
  62 }
  63 #endif // PRODUCT

  31   return FrameMap::nr2floatreg(fpu_regnr());
  32 }
  33 
  34 FloatRegister LIR_OprDesc::as_double_reg() const {
  35   return FrameMap::nr2floatreg(fpu_regnrHi());
  36 }
  37 
  38 LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
  39   assert(as_FloatRegister(reg2) != fnoreg, "Sparc holds double in two regs.");
  40   return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
  41                              (reg2 << LIR_OprDesc::reg2_shift) |
  42                              LIR_OprDesc::double_type          |
  43                              LIR_OprDesc::fpu_register         |
  44                              LIR_OprDesc::double_size);
  45 }
  46 
  47 #ifndef PRODUCT
  48 void LIR_Address::verify() const {
  49   assert(scale() == times_1, "Scaled addressing mode not available on SPARC and should not be used");
  50   assert(disp() == 0 || index()->is_illegal(), "can't have both");

  51   assert(base()->is_cpu_register(), "wrong base operand");
  52   assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
  53   assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
  54          "wrong type for addresses");






  55 }
  56 #endif // PRODUCT