1 //
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3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
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10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 // 64-bit build means 64-bit pointers means hi/lo pairs
315 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
316 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
317 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
318 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
319 // Lock encodings use G3 and G4 internally
320 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
321 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
322 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
323 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
324 // Special class for storeP instructions, which can store SP or RPC to TLS.
325 // It is also used for memory addressing, allowing direct TLS addressing.
326 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
327 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
328 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
329 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
330 // R_L7 is the lowest-priority callee-save (i.e., NS) register
331 // We use it to save R_G2 across calls out of Java.
332 reg_class l7_regP(R_L7H,R_L7);
333
334 // Other special pointer regs
335 reg_class g1_regP(R_G1H,R_G1);
336 reg_class g2_regP(R_G2H,R_G2);
337 reg_class g3_regP(R_G3H,R_G3);
338 reg_class g4_regP(R_G4H,R_G4);
339 reg_class g5_regP(R_G5H,R_G5);
340 reg_class i0_regP(R_I0H,R_I0);
341 reg_class o0_regP(R_O0H,R_O0);
342 reg_class o1_regP(R_O1H,R_O1);
343 reg_class o2_regP(R_O2H,R_O2);
344 reg_class o7_regP(R_O7H,R_O7);
345
346
347 // ----------------------------
348 // Long Register Classes
349 // ----------------------------
350 // Longs in 1 register. Aligned adjacent hi/lo pairs.
351 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
352 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
353 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
354 // 64-bit, longs in 1 register: use all 64-bit integer registers
355 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
356 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
357 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
358 );
359
360 reg_class g1_regL(R_G1H,R_G1);
361 reg_class g3_regL(R_G3H,R_G3);
362 reg_class o2_regL(R_O2H,R_O2);
363 reg_class o7_regL(R_O7H,R_O7);
364
365 // ----------------------------
366 // Special Class for Condition Code Flags Register
367 reg_class int_flags(CCR);
368 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
369 reg_class float_flag0(FCC0);
370
371
372 // ----------------------------
373 // Float Point Register Classes
374 // ----------------------------
375 // Skip F30/F31, they are reserved for mem-mem copies
376 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
377
378 // Paired floating point registers--they show up in the same order as the floats,
379 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
380 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
381 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
382 /* Use extra V9 double registers; this AD file does not support V8 */
383 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
384 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
385 );
386
387 // Paired floating point registers--they show up in the same order as the floats,
388 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
389 // This class is usable for mis-aligned loads as happen in I2C adapters.
390 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
391 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
392 %}
393
394 //----------DEFINITION BLOCK---------------------------------------------------
395 // Define name --> value mappings to inform the ADLC of an integer valued name
396 // Current support includes integer values in the range [0, 0x7FFFFFFF]
397 // Format:
398 // int_def <name> ( <int_value>, <expression>);
399 // Generated Code in ad_<arch>.hpp
400 // #define <name> (<expression>)
401 // // value == <int_value>
402 // Generated code in ad_<arch>.cpp adlc_verification()
403 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
404 //
405 definitions %{
406 // The default cost (of an ALU instruction).
407 int_def DEFAULT_COST ( 100, 100);
408 int_def HUGE_COST (1000000, 1000000);
409
410 // Memory refs are twice as expensive as run-of-the-mill.
411 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
412
413 // Branches are even more expensive.
414 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
415 int_def CALL_COST ( 300, DEFAULT_COST * 3);
416 %}
417
418
419 //----------SOURCE BLOCK-------------------------------------------------------
420 // This is a block of C++ code which provides values, functions, and
421 // definitions necessary in the rest of the architecture description
422 source_hpp %{
423 // Header information of the source block.
424 // Method declarations/definitions which are used outside
425 // the ad-scope can conveniently be defined here.
426 //
427 // To keep related declarations/definitions/uses close together,
428 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
429
430 // Must be visible to the DFA in dfa_sparc.cpp
431 extern bool can_branch_register( Node *bol, Node *cmp );
432
433 extern bool use_block_zeroing(Node* count);
434
435 // Macros to extract hi & lo halves from a long pair.
436 // G0 is not part of any long pair, so assert on that.
437 // Prevents accidentally using G1 instead of G0.
438 #define LONG_HI_REG(x) (x)
439 #define LONG_LO_REG(x) (x)
440
441 class CallStubImpl {
442
443 //--------------------------------------------------------------
444 //---< Used for optimization in Compile::Shorten_branches >---
445 //--------------------------------------------------------------
446
447 public:
448 // Size of call trampoline stub.
449 static uint size_call_trampoline() {
450 return 0; // no call trampolines on this platform
451 }
452
453 // number of relocations needed by a call trampoline stub
454 static uint reloc_call_trampoline() {
455 return 0; // no call trampolines on this platform
456 }
457 };
458
459 class HandlerImpl {
460
461 public:
462
463 static int emit_exception_handler(CodeBuffer &cbuf);
464 static int emit_deopt_handler(CodeBuffer& cbuf);
465
466 static uint size_exception_handler() {
467 return ( NativeJump::instruction_size ); // sethi;jmp;nop
468 }
469
470 static uint size_deopt_handler() {
471 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
472 }
473 };
474
475 %}
476
477 source %{
478 #define __ _masm.
479
480 // tertiary op of a LoadP or StoreP encoding
481 #define REGP_OP true
482
483 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
484 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
485 static Register reg_to_register_object(int register_encoding);
486
487 // Used by the DFA in dfa_sparc.cpp.
488 // Check for being able to use a V9 branch-on-register. Requires a
489 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
490 // extended. Doesn't work following an integer ADD, for example, because of
491 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
492 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
493 // replace them with zero, which could become sign-extension in a different OS
494 // release. There's no obvious reason why an interrupt will ever fill these
495 // bits with non-zero junk (the registers are reloaded with standard LD
496 // instructions which either zero-fill or sign-fill).
497 bool can_branch_register( Node *bol, Node *cmp ) {
498 if( !BranchOnRegister ) return false;
499 if( cmp->Opcode() == Op_CmpP )
500 return true; // No problems with pointer compares
501 if( cmp->Opcode() == Op_CmpL )
502 return true; // No problems with long compares
503
504 if( !SparcV9RegsHiBitsZero ) return false;
505 if( bol->as_Bool()->_test._test != BoolTest::ne &&
506 bol->as_Bool()->_test._test != BoolTest::eq )
507 return false;
508
509 // Check for comparing against a 'safe' value. Any operation which
510 // clears out the high word is safe. Thus, loads and certain shifts
511 // are safe, as are non-negative constants. Any operation which
512 // preserves zero bits in the high word is safe as long as each of its
513 // inputs are safe. Thus, phis and bitwise booleans are safe if their
514 // inputs are safe. At present, the only important case to recognize
515 // seems to be loads. Constants should fold away, and shifts &
516 // logicals can use the 'cc' forms.
517 Node *x = cmp->in(1);
518 if( x->is_Load() ) return true;
519 if( x->is_Phi() ) {
520 for( uint i = 1; i < x->req(); i++ )
521 if( !x->in(i)->is_Load() )
522 return false;
523 return true;
524 }
525 return false;
526 }
527
528 bool use_block_zeroing(Node* count) {
529 // Use BIS for zeroing if count is not constant
530 // or it is >= BlockZeroingLowLimit.
531 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
532 }
533
534 // ****************************************************************************
535
536 // REQUIRED FUNCTIONALITY
537
538 // !!!!! Special hack to get all type of calls to specify the byte offset
539 // from the start of the call to the point where the return address
540 // will point.
541 // The "return address" is the address of the call instruction, plus 8.
542
543 int MachCallStaticJavaNode::ret_addr_offset() {
544 int offset = NativeCall::instruction_size; // call; delay slot
545 if (_method_handle_invoke)
546 offset += 4; // restore SP
547 return offset;
548 }
549
550 int MachCallDynamicJavaNode::ret_addr_offset() {
551 int vtable_index = this->_vtable_index;
552 if (vtable_index < 0) {
553 // must be invalid_vtable_index, not nonvirtual_vtable_index
554 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
555 return (NativeMovConstReg::instruction_size +
556 NativeCall::instruction_size); // sethi; setlo; call; delay slot
557 } else {
558 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
559 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
560 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
561 int klass_load_size;
562 if (UseCompressedClassPointers) {
563 assert(Universe::heap() != NULL, "java heap should be initialized");
564 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
565 } else {
566 klass_load_size = 1*BytesPerInstWord;
567 }
568 if (Assembler::is_simm13(v_off)) {
569 return klass_load_size +
570 (2*BytesPerInstWord + // ld_ptr, ld_ptr
571 NativeCall::instruction_size); // call; delay slot
572 } else {
573 return klass_load_size +
574 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
575 NativeCall::instruction_size); // call; delay slot
576 }
577 }
578 }
579
580 int MachCallRuntimeNode::ret_addr_offset() {
581 if (MacroAssembler::is_far_target(entry_point())) {
582 return NativeFarCall::instruction_size;
583 } else {
584 return NativeCall::instruction_size;
585 }
586 }
587
588 // Indicate if the safepoint node needs the polling page as an input.
589 // Since Sparc does not have absolute addressing, it does.
590 bool SafePointNode::needs_polling_address_input() {
591 return true;
592 }
593
594 // emit an interrupt that is caught by the debugger (for debugging compiler)
595 void emit_break(CodeBuffer &cbuf) {
596 MacroAssembler _masm(&cbuf);
597 __ breakpoint_trap();
598 }
599
600 #ifndef PRODUCT
601 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
602 st->print("TA");
603 }
604 #endif
605
606 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
607 emit_break(cbuf);
608 }
609
610 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
611 return MachNode::size(ra_);
612 }
613
614 // Traceable jump
615 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
616 MacroAssembler _masm(&cbuf);
617 Register rdest = reg_to_register_object(jump_target);
618 __ JMP(rdest, 0);
619 __ delayed()->nop();
620 }
621
622 // Traceable jump and set exception pc
623 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
624 MacroAssembler _masm(&cbuf);
625 Register rdest = reg_to_register_object(jump_target);
626 __ JMP(rdest, 0);
627 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
628 }
629
630 void emit_nop(CodeBuffer &cbuf) {
631 MacroAssembler _masm(&cbuf);
632 __ nop();
633 }
634
635 void emit_illtrap(CodeBuffer &cbuf) {
636 MacroAssembler _masm(&cbuf);
637 __ illtrap(0);
638 }
639
640
641 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
642 assert(n->rule() != loadUB_rule, "");
643
644 intptr_t offset = 0;
645 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
646 const Node* addr = n->get_base_and_disp(offset, adr_type);
647 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
648 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
649 assert(addr->bottom_type()->isa_oopptr() == atype, "");
650 atype = atype->add_offset(offset);
651 assert(disp32 == offset, "wrong disp32");
652 return atype->_offset;
653 }
654
655
656 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
657 assert(n->rule() != loadUB_rule, "");
658
659 intptr_t offset = 0;
660 Node* addr = n->in(2);
661 assert(addr->bottom_type()->isa_oopptr() == atype, "");
662 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
663 Node* a = addr->in(2/*AddPNode::Address*/);
664 Node* o = addr->in(3/*AddPNode::Offset*/);
665 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
666 atype = a->bottom_type()->is_ptr()->add_offset(offset);
667 assert(atype->isa_oop_ptr(), "still an oop");
668 }
669 offset = atype->is_ptr()->_offset;
670 if (offset != Type::OffsetBot) offset += disp32;
671 return offset;
672 }
673
674 static inline jlong replicate_immI(int con, int count, int width) {
675 // Load a constant replicated "count" times with width "width"
676 assert(count*width == 8 && width <= 4, "sanity");
677 int bit_width = width * 8;
678 jlong val = con;
679 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
680 for (int i = 0; i < count - 1; i++) {
681 val |= (val << bit_width);
682 }
683 return val;
684 }
685
686 static inline jlong replicate_immF(float con) {
687 // Replicate float con 2 times and pack into vector.
688 int val = *((int*)&con);
689 jlong lval = val;
690 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
691 return lval;
692 }
693
694 // Standard Sparc opcode form2 field breakdown
695 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
696 f0 &= (1<<19)-1; // Mask displacement to 19 bits
697 int op = (f30 << 30) |
698 (f29 << 29) |
699 (f25 << 25) |
700 (f22 << 22) |
701 (f20 << 20) |
702 (f19 << 19) |
703 (f0 << 0);
704 cbuf.insts()->emit_int32(op);
705 }
706
707 // Standard Sparc opcode form2 field breakdown
708 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
709 f0 >>= 10; // Drop 10 bits
710 f0 &= (1<<22)-1; // Mask displacement to 22 bits
711 int op = (f30 << 30) |
712 (f25 << 25) |
713 (f22 << 22) |
714 (f0 << 0);
715 cbuf.insts()->emit_int32(op);
716 }
717
718 // Standard Sparc opcode form3 field breakdown
719 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
720 int op = (f30 << 30) |
721 (f25 << 25) |
722 (f19 << 19) |
723 (f14 << 14) |
724 (f5 << 5) |
725 (f0 << 0);
726 cbuf.insts()->emit_int32(op);
727 }
728
729 // Standard Sparc opcode form3 field breakdown
730 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
731 simm13 &= (1<<13)-1; // Mask to 13 bits
732 int op = (f30 << 30) |
733 (f25 << 25) |
734 (f19 << 19) |
735 (f14 << 14) |
736 (1 << 13) | // bit to indicate immediate-mode
737 (simm13<<0);
738 cbuf.insts()->emit_int32(op);
739 }
740
741 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
742 simm10 &= (1<<10)-1; // Mask to 10 bits
743 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
744 }
745
746 #ifdef ASSERT
747 // Helper function for VerifyOops in emit_form3_mem_reg
748 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
749 warning("VerifyOops encountered unexpected instruction:");
750 n->dump(2);
751 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
752 }
753 #endif
754
755
756 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
757 int src1_enc, int disp32, int src2_enc, int dst_enc) {
758
759 #ifdef ASSERT
760 // The following code implements the +VerifyOops feature.
761 // It verifies oop values which are loaded into or stored out of
762 // the current method activation. +VerifyOops complements techniques
763 // like ScavengeALot, because it eagerly inspects oops in transit,
764 // as they enter or leave the stack, as opposed to ScavengeALot,
765 // which inspects oops "at rest", in the stack or heap, at safepoints.
766 // For this reason, +VerifyOops can sometimes detect bugs very close
767 // to their point of creation. It can also serve as a cross-check
768 // on the validity of oop maps, when used toegether with ScavengeALot.
769
770 // It would be good to verify oops at other points, especially
771 // when an oop is used as a base pointer for a load or store.
772 // This is presently difficult, because it is hard to know when
773 // a base address is biased or not. (If we had such information,
774 // it would be easy and useful to make a two-argument version of
775 // verify_oop which unbiases the base, and performs verification.)
776
777 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
778 bool is_verified_oop_base = false;
779 bool is_verified_oop_load = false;
780 bool is_verified_oop_store = false;
781 int tmp_enc = -1;
782 if (VerifyOops && src1_enc != R_SP_enc) {
783 // classify the op, mainly for an assert check
784 int st_op = 0, ld_op = 0;
785 switch (primary) {
786 case Assembler::stb_op3: st_op = Op_StoreB; break;
787 case Assembler::sth_op3: st_op = Op_StoreC; break;
788 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
789 case Assembler::stw_op3: st_op = Op_StoreI; break;
790 case Assembler::std_op3: st_op = Op_StoreL; break;
791 case Assembler::stf_op3: st_op = Op_StoreF; break;
792 case Assembler::stdf_op3: st_op = Op_StoreD; break;
793
794 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
795 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
796 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
797 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
798 case Assembler::ldx_op3: // may become LoadP or stay LoadI
799 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
800 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
801 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
802 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
803 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
804 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
805
806 default: ShouldNotReachHere();
807 }
808 if (tertiary == REGP_OP) {
809 if (st_op == Op_StoreI) st_op = Op_StoreP;
810 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
811 else ShouldNotReachHere();
812 if (st_op) {
813 // a store
814 // inputs are (0:control, 1:memory, 2:address, 3:value)
815 Node* n2 = n->in(3);
816 if (n2 != NULL) {
817 const Type* t = n2->bottom_type();
818 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
819 }
820 } else {
821 // a load
822 const Type* t = n->bottom_type();
823 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
824 }
825 }
826
827 if (ld_op) {
828 // a Load
829 // inputs are (0:control, 1:memory, 2:address)
830 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
831 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
832 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
833 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
834 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
835 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
836 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
837 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
839 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
840 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
841 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
843 !(n->rule() == loadUB_rule)) {
844 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
845 }
846 } else if (st_op) {
847 // a Store
848 // inputs are (0:control, 1:memory, 2:address, 3:value)
849 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
850 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
851 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
852 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
853 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
854 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
855 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
856 verify_oops_warning(n, n->ideal_Opcode(), st_op);
857 }
858 }
859
860 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
861 Node* addr = n->in(2);
862 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
863 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
864 if (atype != NULL) {
865 intptr_t offset = get_offset_from_base(n, atype, disp32);
866 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
867 if (offset != offset_2) {
868 get_offset_from_base(n, atype, disp32);
869 get_offset_from_base_2(n, atype, disp32);
870 }
871 assert(offset == offset_2, "different offsets");
872 if (offset == disp32) {
873 // we now know that src1 is a true oop pointer
874 is_verified_oop_base = true;
875 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
876 if( primary == Assembler::ldd_op3 ) {
877 is_verified_oop_base = false; // Cannot 'ldd' into O7
878 } else {
879 tmp_enc = dst_enc;
880 dst_enc = R_O7_enc; // Load into O7; preserve source oop
881 assert(src1_enc != dst_enc, "");
882 }
883 }
884 }
885 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
886 || offset == oopDesc::mark_offset_in_bytes())) {
887 // loading the mark should not be allowed either, but
888 // we don't check this since it conflicts with InlineObjectHash
889 // usage of LoadINode to get the mark. We could keep the
890 // check if we create a new LoadMarkNode
891 // but do not verify the object before its header is initialized
892 ShouldNotReachHere();
893 }
894 }
895 }
896 }
897 }
898 #endif
899
900 uint instr = (Assembler::ldst_op << 30)
901 | (dst_enc << 25)
902 | (primary << 19)
903 | (src1_enc << 14);
904
905 uint index = src2_enc;
906 int disp = disp32;
907
908 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
909 disp += STACK_BIAS;
910 // Check that stack offset fits, load into O7 if not
911 if (!Assembler::is_simm13(disp)) {
912 MacroAssembler _masm(&cbuf);
913 __ set(disp, O7);
914 if (index != R_G0_enc) {
915 __ add(O7, reg_to_register_object(index), O7);
916 }
917 index = R_O7_enc;
918 disp = 0;
919 }
920 }
921
922 if( disp == 0 ) {
923 // use reg-reg form
924 // bit 13 is already zero
925 instr |= index;
926 } else {
927 // use reg-imm form
928 instr |= 0x00002000; // set bit 13 to one
929 instr |= disp & 0x1FFF;
930 }
931
932 cbuf.insts()->emit_int32(instr);
933
934 #ifdef ASSERT
935 if (VerifyOops) {
936 MacroAssembler _masm(&cbuf);
937 if (is_verified_oop_base) {
938 __ verify_oop(reg_to_register_object(src1_enc));
939 }
940 if (is_verified_oop_store) {
941 __ verify_oop(reg_to_register_object(dst_enc));
942 }
943 if (tmp_enc != -1) {
944 __ mov(O7, reg_to_register_object(tmp_enc));
945 }
946 if (is_verified_oop_load) {
947 __ verify_oop(reg_to_register_object(dst_enc));
948 }
949 }
950 #endif
951 }
952
953 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) {
954 // The method which records debug information at every safepoint
955 // expects the call to be the first instruction in the snippet as
956 // it creates a PcDesc structure which tracks the offset of a call
957 // from the start of the codeBlob. This offset is computed as
958 // code_end() - code_begin() of the code which has been emitted
959 // so far.
960 // In this particular case we have skirted around the problem by
961 // putting the "mov" instruction in the delay slot but the problem
962 // may bite us again at some other point and a cleaner/generic
963 // solution using relocations would be needed.
964 MacroAssembler _masm(&cbuf);
965 __ set_inst_mark();
966
967 // We flush the current window just so that there is a valid stack copy
968 // the fact that the current window becomes active again instantly is
969 // not a problem there is nothing live in it.
970
971 #ifdef ASSERT
972 int startpos = __ offset();
973 #endif /* ASSERT */
974
975 __ call((address)entry_point, rspec);
976
977 if (preserve_g2) __ delayed()->mov(G2, L7);
978 else __ delayed()->nop();
979
980 if (preserve_g2) __ mov(L7, G2);
981
982 #ifdef ASSERT
983 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
984 // Trash argument dump slots.
985 __ set(0xb0b8ac0db0b8ac0d, G1);
986 __ mov(G1, G5);
987 __ stx(G1, SP, STACK_BIAS + 0x80);
988 __ stx(G1, SP, STACK_BIAS + 0x88);
989 __ stx(G1, SP, STACK_BIAS + 0x90);
990 __ stx(G1, SP, STACK_BIAS + 0x98);
991 __ stx(G1, SP, STACK_BIAS + 0xA0);
992 __ stx(G1, SP, STACK_BIAS + 0xA8);
993 }
994 #endif /*ASSERT*/
995 }
996
997 //=============================================================================
998 // REQUIRED FUNCTIONALITY for encoding
999 void emit_lo(CodeBuffer &cbuf, int val) { }
1000 void emit_hi(CodeBuffer &cbuf, int val) { }
1001
1002
1003 //=============================================================================
1004 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1005
1006 int Compile::ConstantTable::calculate_table_base_offset() const {
1007 if (UseRDPCForConstantTableBase) {
1008 // The table base offset might be less but then it fits into
1009 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1010 return Assembler::min_simm13();
1011 } else {
1012 int offset = -(size() / 2);
1013 if (!Assembler::is_simm13(offset)) {
1014 offset = Assembler::min_simm13();
1015 }
1016 return offset;
1017 }
1018 }
1019
1020 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1021 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1022 ShouldNotReachHere();
1023 }
1024
1025 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1026 Compile* C = ra_->C;
1027 Compile::ConstantTable& constant_table = C->constant_table();
1028 MacroAssembler _masm(&cbuf);
1029
1030 Register r = as_Register(ra_->get_encode(this));
1031 CodeSection* consts_section = __ code()->consts();
1032 int consts_size = consts_section->align_at_start(consts_section->size());
1033 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size);
1034
1035 if (UseRDPCForConstantTableBase) {
1036 // For the following RDPC logic to work correctly the consts
1037 // section must be allocated right before the insts section. This
1038 // assert checks for that. The layout and the SECT_* constants
1039 // are defined in src/share/vm/asm/codeBuffer.hpp.
1040 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1041 int insts_offset = __ offset();
1042
1043 // Layout:
1044 //
1045 // |----------- consts section ------------|----------- insts section -----------...
1046 // |------ constant table -----|- padding -|------------------x----
1047 // \ current PC (RDPC instruction)
1048 // |<------------- consts_size ----------->|<- insts_offset ->|
1049 // \ table base
1050 // The table base offset is later added to the load displacement
1051 // so it has to be negative.
1052 int table_base_offset = -(consts_size + insts_offset);
1053 int disp;
1054
1055 // If the displacement from the current PC to the constant table
1056 // base fits into simm13 we set the constant table base to the
1057 // current PC.
1058 if (Assembler::is_simm13(table_base_offset)) {
1059 constant_table.set_table_base_offset(table_base_offset);
1060 disp = 0;
1061 } else {
1062 // Otherwise we set the constant table base offset to the
1063 // maximum negative displacement of load instructions to keep
1064 // the disp as small as possible:
1065 //
1066 // |<------------- consts_size ----------->|<- insts_offset ->|
1067 // |<--------- min_simm13 --------->|<-------- disp --------->|
1068 // \ table base
1069 table_base_offset = Assembler::min_simm13();
1070 constant_table.set_table_base_offset(table_base_offset);
1071 disp = (consts_size + insts_offset) + table_base_offset;
1072 }
1073
1074 __ rdpc(r);
1075
1076 if (disp != 0) {
1077 assert(r != O7, "need temporary");
1078 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1079 }
1080 }
1081 else {
1082 // Materialize the constant table base.
1083 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1084 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1085 AddressLiteral base(baseaddr, rspec);
1086 __ set(base, r);
1087 }
1088 }
1089
1090 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1091 if (UseRDPCForConstantTableBase) {
1092 // This is really the worst case but generally it's only 1 instruction.
1093 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1094 } else {
1095 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1096 }
1097 }
1098
1099 #ifndef PRODUCT
1100 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1101 char reg[128];
1102 ra_->dump_register(this, reg);
1103 if (UseRDPCForConstantTableBase) {
1104 st->print("RDPC %s\t! constant table base", reg);
1105 } else {
1106 st->print("SET &constanttable,%s\t! constant table base", reg);
1107 }
1108 }
1109 #endif
1110
1111
1112 //=============================================================================
1113
1114 #ifndef PRODUCT
1115 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1116 Compile* C = ra_->C;
1117
1118 for (int i = 0; i < OptoPrologueNops; i++) {
1119 st->print_cr("NOP"); st->print("\t");
1120 }
1121
1122 if( VerifyThread ) {
1123 st->print_cr("Verify_Thread"); st->print("\t");
1124 }
1125
1126 size_t framesize = C->frame_size_in_bytes();
1127 int bangsize = C->bang_size_in_bytes();
1128
1129 // Calls to C2R adapters often do not accept exceptional returns.
1130 // We require that their callers must bang for them. But be careful, because
1131 // some VM calls (such as call site linkage) can use several kilobytes of
1132 // stack. But the stack safety zone should account for that.
1133 // See bugs 4446381, 4468289, 4497237.
1134 if (C->need_stack_bang(bangsize)) {
1135 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1136 }
1137
1138 if (Assembler::is_simm13(-framesize)) {
1139 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1140 } else {
1141 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1142 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1143 st->print ("SAVE R_SP,R_G3,R_SP");
1144 }
1145
1146 }
1147 #endif
1148
1149 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1150 Compile* C = ra_->C;
1151 MacroAssembler _masm(&cbuf);
1152
1153 for (int i = 0; i < OptoPrologueNops; i++) {
1154 __ nop();
1155 }
1156
1157 __ verify_thread();
1158
1159 size_t framesize = C->frame_size_in_bytes();
1160 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1161 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1162 int bangsize = C->bang_size_in_bytes();
1163
1164 // Calls to C2R adapters often do not accept exceptional returns.
1165 // We require that their callers must bang for them. But be careful, because
1166 // some VM calls (such as call site linkage) can use several kilobytes of
1167 // stack. But the stack safety zone should account for that.
1168 // See bugs 4446381, 4468289, 4497237.
1169 if (C->need_stack_bang(bangsize)) {
1170 __ generate_stack_overflow_check(bangsize);
1171 }
1172
1173 if (Assembler::is_simm13(-framesize)) {
1174 __ save(SP, -framesize, SP);
1175 } else {
1176 __ sethi(-framesize & ~0x3ff, G3);
1177 __ add(G3, -framesize & 0x3ff, G3);
1178 __ save(SP, G3, SP);
1179 }
1180 C->set_frame_complete( __ offset() );
1181
1182 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1183 // NOTE: We set the table base offset here because users might be
1184 // emitted before MachConstantBaseNode.
1185 Compile::ConstantTable& constant_table = C->constant_table();
1186 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1187 }
1188 }
1189
1190 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1191 return MachNode::size(ra_);
1192 }
1193
1194 int MachPrologNode::reloc() const {
1195 return 10; // a large enough number
1196 }
1197
1198 //=============================================================================
1199 #ifndef PRODUCT
1200 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1201 Compile* C = ra_->C;
1202
1203 if(do_polling() && ra_->C->is_method_compilation()) {
1204 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1205 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1206 }
1207
1208 if(do_polling()) {
1209 if (UseCBCond && !ra_->C->is_method_compilation()) {
1210 st->print("NOP\n\t");
1211 }
1212 st->print("RET\n\t");
1213 }
1214
1215 st->print("RESTORE");
1216 }
1217 #endif
1218
1219 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1220 MacroAssembler _masm(&cbuf);
1221 Compile* C = ra_->C;
1222
1223 __ verify_thread();
1224
1225 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1226 __ reserved_stack_check();
1227 }
1228
1229 // If this does safepoint polling, then do it here
1230 if(do_polling() && ra_->C->is_method_compilation()) {
1231 AddressLiteral polling_page(os::get_polling_page());
1232 __ sethi(polling_page, L0);
1233 __ relocate(relocInfo::poll_return_type);
1234 __ ld_ptr(L0, 0, G0);
1235 }
1236
1237 // If this is a return, then stuff the restore in the delay slot
1238 if(do_polling()) {
1239 if (UseCBCond && !ra_->C->is_method_compilation()) {
1240 // Insert extra padding for the case when the epilogue is preceded by
1241 // a cbcond jump, which can't be followed by a CTI instruction
1242 __ nop();
1243 }
1244 __ ret();
1245 __ delayed()->restore();
1246 } else {
1247 __ restore();
1248 }
1249 }
1250
1251 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1252 return MachNode::size(ra_);
1253 }
1254
1255 int MachEpilogNode::reloc() const {
1256 return 16; // a large enough number
1257 }
1258
1259 const Pipeline * MachEpilogNode::pipeline() const {
1260 return MachNode::pipeline_class();
1261 }
1262
1263 int MachEpilogNode::safepoint_offset() const {
1264 assert( do_polling(), "no return for this epilog node");
1265 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1266 }
1267
1268 //=============================================================================
1269
1270 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1271 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1272 static enum RC rc_class( OptoReg::Name reg ) {
1273 if (!OptoReg::is_valid(reg)) return rc_bad;
1274 if (OptoReg::is_stack(reg)) return rc_stack;
1275 VMReg r = OptoReg::as_VMReg(reg);
1276 if (r->is_Register()) return rc_int;
1277 assert(r->is_FloatRegister(), "must be");
1278 return rc_float;
1279 }
1280
1281 #ifndef PRODUCT
1282 ATTRIBUTE_PRINTF(2, 3)
1283 static void print_helper(outputStream* st, const char* format, ...) {
1284 if (st->position() > 0) {
1285 st->cr();
1286 st->sp();
1287 }
1288 va_list ap;
1289 va_start(ap, format);
1290 st->vprint(format, ap);
1291 va_end(ap);
1292 }
1293 #endif // !PRODUCT
1294
1295 static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) {
1296 if (cbuf) {
1297 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1298 }
1299 #ifndef PRODUCT
1300 else {
1301 if (is_load) {
1302 print_helper(st, "%s [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg));
1303 } else {
1304 print_helper(st, "%s R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset);
1305 }
1306 }
1307 #endif
1308 }
1309
1310 static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) {
1311 if (cbuf) {
1312 emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]);
1313 }
1314 #ifndef PRODUCT
1315 else {
1316 print_helper(st, "%s R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst));
1317 }
1318 #endif
1319 }
1320
1321 static void mach_spill_copy_implementation_helper(const MachNode* mach,
1322 CodeBuffer *cbuf,
1323 PhaseRegAlloc *ra_,
1324 outputStream* st) {
1325 // Get registers to move
1326 OptoReg::Name src_second = ra_->get_reg_second(mach->in(1));
1327 OptoReg::Name src_first = ra_->get_reg_first(mach->in(1));
1328 OptoReg::Name dst_second = ra_->get_reg_second(mach);
1329 OptoReg::Name dst_first = ra_->get_reg_first(mach);
1330
1331 enum RC src_second_rc = rc_class(src_second);
1332 enum RC src_first_rc = rc_class(src_first);
1333 enum RC dst_second_rc = rc_class(dst_second);
1334 enum RC dst_first_rc = rc_class(dst_first);
1335
1336 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register");
1337
1338 if (src_first == dst_first && src_second == dst_second) {
1339 return; // Self copy, no move
1340 }
1341
1342 // --------------------------------------
1343 // Check for mem-mem move. Load into unused float registers and fall into
1344 // the float-store case.
1345 if (src_first_rc == rc_stack && dst_first_rc == rc_stack) {
1346 int offset = ra_->reg2offset(src_first);
1347 // Further check for aligned-adjacent pair, so we can use a double load
1348 if ((src_first&1) == 0 && src_first+1 == src_second) {
1349 src_second = OptoReg::Name(R_F31_num);
1350 src_second_rc = rc_float;
1351 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st);
1352 } else {
1353 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st);
1354 }
1355 src_first = OptoReg::Name(R_F30_num);
1356 src_first_rc = rc_float;
1357 }
1358
1359 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1360 int offset = ra_->reg2offset(src_second);
1361 impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st);
1362 src_second = OptoReg::Name(R_F31_num);
1363 src_second_rc = rc_float;
1364 }
1365
1366 // --------------------------------------
1367 // Check for float->int copy; requires a trip through memory
1368 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1369 int offset = frame::register_save_words*wordSize;
1370 if (cbuf) {
1371 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16);
1372 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1373 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1374 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16);
1375 }
1376 #ifndef PRODUCT
1377 else {
1378 print_helper(st, "SUB R_SP,16,R_SP");
1379 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1380 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1381 print_helper(st, "ADD R_SP,16,R_SP");
1382 }
1383 #endif
1384 }
1385
1386 // Check for float->int copy on T4
1387 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1388 // Further check for aligned-adjacent pair, so we can use a double move
1389 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1390 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st);
1391 return;
1392 }
1393 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st);
1394 }
1395 // Check for int->float copy on T4
1396 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1397 // Further check for aligned-adjacent pair, so we can use a double move
1398 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1399 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st);
1400 return;
1401 }
1402 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st);
1403 }
1404
1405 // --------------------------------------
1406 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1407 // In such cases, I have to do the big-endian swap. For aligned targets, the
1408 // hardware does the flop for me. Doubles are always aligned, so no problem
1409 // there. Misaligned sources only come from native-long-returns (handled
1410 // special below).
1411
1412 // --------------------------------------
1413 // Check for integer reg-reg copy
1414 if (src_first_rc == rc_int && dst_first_rc == rc_int) {
1415 // Else normal reg-reg copy
1416 assert(src_second != dst_first, "smashed second before evacuating it");
1417 impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV ", st);
1418 assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers");
1419 // This moves an aligned adjacent pair.
1420 // See if we are done.
1421 if (src_first + 1 == src_second && dst_first + 1 == dst_second) {
1422 return;
1423 }
1424 }
1425
1426 // Check for integer store
1427 if (src_first_rc == rc_int && dst_first_rc == rc_stack) {
1428 int offset = ra_->reg2offset(dst_first);
1429 // Further check for aligned-adjacent pair, so we can use a double store
1430 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1431 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st);
1432 return;
1433 }
1434 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st);
1435 }
1436
1437 // Check for integer load
1438 if (dst_first_rc == rc_int && src_first_rc == rc_stack) {
1439 int offset = ra_->reg2offset(src_first);
1440 // Further check for aligned-adjacent pair, so we can use a double load
1441 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1442 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st);
1443 return;
1444 }
1445 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1446 }
1447
1448 // Check for float reg-reg copy
1449 if (src_first_rc == rc_float && dst_first_rc == rc_float) {
1450 // Further check for aligned-adjacent pair, so we can use a double move
1451 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1452 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st);
1453 return;
1454 }
1455 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st);
1456 }
1457
1458 // Check for float store
1459 if (src_first_rc == rc_float && dst_first_rc == rc_stack) {
1460 int offset = ra_->reg2offset(dst_first);
1461 // Further check for aligned-adjacent pair, so we can use a double store
1462 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1463 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st);
1464 return;
1465 }
1466 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1467 }
1468
1469 // Check for float load
1470 if (dst_first_rc == rc_float && src_first_rc == rc_stack) {
1471 int offset = ra_->reg2offset(src_first);
1472 // Further check for aligned-adjacent pair, so we can use a double load
1473 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1474 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st);
1475 return;
1476 }
1477 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st);
1478 }
1479
1480 // --------------------------------------------------------------------
1481 // Check for hi bits still needing moving. Only happens for misaligned
1482 // arguments to native calls.
1483 if (src_second == dst_second) {
1484 return; // Self copy; no move
1485 }
1486 assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad");
1487
1488 Unimplemented();
1489 }
1490
1491 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf,
1492 PhaseRegAlloc *ra_,
1493 bool do_size,
1494 outputStream* st) const {
1495 assert(!do_size, "not supported");
1496 mach_spill_copy_implementation_helper(this, cbuf, ra_, st);
1497 return 0;
1498 }
1499
1500 #ifndef PRODUCT
1501 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1502 implementation( NULL, ra_, false, st );
1503 }
1504 #endif
1505
1506 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1507 implementation( &cbuf, ra_, false, NULL );
1508 }
1509
1510 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1511 return MachNode::size(ra_);
1512 }
1513
1514 //=============================================================================
1515 #ifndef PRODUCT
1516 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const {
1517 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1518 }
1519 #endif
1520
1521 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1522 MacroAssembler _masm(&cbuf);
1523 for (int i = 0; i < _count; i += 1) {
1524 __ nop();
1525 }
1526 }
1527
1528 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1529 return 4 * _count;
1530 }
1531
1532
1533 //=============================================================================
1534 #ifndef PRODUCT
1535 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1536 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1537 int reg = ra_->get_reg_first(this);
1538 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1539 }
1540 #endif
1541
1542 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1543 MacroAssembler _masm(&cbuf);
1544 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1545 int reg = ra_->get_encode(this);
1546
1547 if (Assembler::is_simm13(offset)) {
1548 __ add(SP, offset, reg_to_register_object(reg));
1549 } else {
1550 __ set(offset, O7);
1551 __ add(SP, O7, reg_to_register_object(reg));
1552 }
1553 }
1554
1555 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1556 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1557 assert(ra_ == ra_->C->regalloc(), "sanity");
1558 return ra_->C->scratch_emit_size(this);
1559 }
1560
1561 //=============================================================================
1562 #ifndef PRODUCT
1563 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1564 st->print_cr("\nUEP:");
1565 if (UseCompressedClassPointers) {
1566 assert(Universe::heap() != NULL, "java heap should be initialized");
1567 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1568 if (Universe::narrow_klass_base() != 0) {
1569 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1570 if (Universe::narrow_klass_shift() != 0) {
1571 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1572 }
1573 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1574 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1575 } else {
1576 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1577 }
1578 } else {
1579 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1580 }
1581 st->print_cr("\tCMP R_G5,R_G3" );
1582 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1583 }
1584 #endif
1585
1586 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1587 MacroAssembler _masm(&cbuf);
1588 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1589 Register temp_reg = G3;
1590 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1591
1592 // Load klass from receiver
1593 __ load_klass(O0, temp_reg);
1594 // Compare against expected klass
1595 __ cmp(temp_reg, G5_ic_reg);
1596 // Branch to miss code, checks xcc or icc depending
1597 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1598 }
1599
1600 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1601 return MachNode::size(ra_);
1602 }
1603
1604
1605 //=============================================================================
1606
1607
1608 // Emit exception handler code.
1609 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1610 Register temp_reg = G3;
1611 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1612 MacroAssembler _masm(&cbuf);
1613
1614 address base = __ start_a_stub(size_exception_handler());
1615 if (base == NULL) {
1616 ciEnv::current()->record_failure("CodeCache is full");
1617 return 0; // CodeBuffer::expand failed
1618 }
1619
1620 int offset = __ offset();
1621
1622 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1623 __ delayed()->nop();
1624
1625 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1626
1627 __ end_a_stub();
1628
1629 return offset;
1630 }
1631
1632 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1633 // Can't use any of the current frame's registers as we may have deopted
1634 // at a poll and everything (including G3) can be live.
1635 Register temp_reg = L0;
1636 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1637 MacroAssembler _masm(&cbuf);
1638
1639 address base = __ start_a_stub(size_deopt_handler());
1640 if (base == NULL) {
1641 ciEnv::current()->record_failure("CodeCache is full");
1642 return 0; // CodeBuffer::expand failed
1643 }
1644
1645 int offset = __ offset();
1646 __ save_frame(0);
1647 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1648 __ delayed()->restore();
1649
1650 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1651
1652 __ end_a_stub();
1653 return offset;
1654
1655 }
1656
1657 // Given a register encoding, produce a Integer Register object
1658 static Register reg_to_register_object(int register_encoding) {
1659 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1660 return as_Register(register_encoding);
1661 }
1662
1663 // Given a register encoding, produce a single-precision Float Register object
1664 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1665 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1666 return as_SingleFloatRegister(register_encoding);
1667 }
1668
1669 // Given a register encoding, produce a double-precision Float Register object
1670 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1671 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1672 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1673 return as_DoubleFloatRegister(register_encoding);
1674 }
1675
1676 const bool Matcher::match_rule_supported(int opcode) {
1677 if (!has_match_rule(opcode))
1678 return false;
1679
1680 switch (opcode) {
1681 case Op_CountLeadingZerosI:
1682 case Op_CountLeadingZerosL:
1683 case Op_CountTrailingZerosI:
1684 case Op_CountTrailingZerosL:
1685 case Op_PopCountI:
1686 case Op_PopCountL:
1687 if (!UsePopCountInstruction)
1688 return false;
1689 case Op_CompareAndSwapL:
1690 case Op_CompareAndSwapP:
1691 if (!VM_Version::supports_cx8())
1692 return false;
1693 break;
1694 }
1695
1696 return true; // Per default match rules are supported.
1697 }
1698
1699 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1700
1701 // TODO
1702 // identify extra cases that we might want to provide match rules for
1703 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1704 bool ret_value = match_rule_supported(opcode);
1705 // Add rules here.
1706
1707 return ret_value; // Per default match rules are supported.
1708 }
1709
1710 const bool Matcher::has_predicated_vectors(void) {
1711 return false;
1712 }
1713
1714 const int Matcher::float_pressure(int default_pressure_threshold) {
1715 return default_pressure_threshold;
1716 }
1717
1718 int Matcher::regnum_to_fpu_offset(int regnum) {
1719 return regnum - 32; // The FP registers are in the second chunk
1720 }
1721
1722 #ifdef ASSERT
1723 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1724 #endif
1725
1726 // Vector width in bytes
1727 const int Matcher::vector_width_in_bytes(BasicType bt) {
1728 assert(MaxVectorSize == 8, "");
1729 return 8;
1730 }
1731
1732 // Vector ideal reg
1733 const int Matcher::vector_ideal_reg(int size) {
1734 assert(MaxVectorSize == 8, "");
1735 return Op_RegD;
1736 }
1737
1738 const int Matcher::vector_shift_count_ideal_reg(int size) {
1739 fatal("vector shift is not supported");
1740 return Node::NotAMachineReg;
1741 }
1742
1743 // Limits on vector size (number of elements) loaded into vector.
1744 const int Matcher::max_vector_size(const BasicType bt) {
1745 assert(is_java_primitive(bt), "only primitive type vectors");
1746 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1747 }
1748
1749 const int Matcher::min_vector_size(const BasicType bt) {
1750 return max_vector_size(bt); // Same as max.
1751 }
1752
1753 // SPARC doesn't support misaligned vectors store/load.
1754 const bool Matcher::misaligned_vectors_ok() {
1755 return false;
1756 }
1757
1758 // Current (2013) SPARC platforms need to read original key
1759 // to construct decryption expanded key
1760 const bool Matcher::pass_original_key_for_aes() {
1761 return true;
1762 }
1763
1764 // USII supports fxtof through the whole range of number, USIII doesn't
1765 const bool Matcher::convL2FSupported(void) {
1766 return VM_Version::has_fast_fxtof();
1767 }
1768
1769 // Is this branch offset short enough that a short branch can be used?
1770 //
1771 // NOTE: If the platform does not provide any short branch variants, then
1772 // this method should return false for offset 0.
1773 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1774 // The passed offset is relative to address of the branch.
1775 // Don't need to adjust the offset.
1776 return UseCBCond && Assembler::is_simm12(offset);
1777 }
1778
1779 const bool Matcher::isSimpleConstant64(jlong value) {
1780 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1781 // Depends on optimizations in MacroAssembler::setx.
1782 int hi = (int)(value >> 32);
1783 int lo = (int)(value & ~0);
1784 return (hi == 0) || (hi == -1) || (lo == 0);
1785 }
1786
1787 // No scaling for the parameter the ClearArray node.
1788 const bool Matcher::init_array_count_is_in_bytes = true;
1789
1790 // No additional cost for CMOVL.
1791 const int Matcher::long_cmove_cost() { return 0; }
1792
1793 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1794 const int Matcher::float_cmove_cost() {
1795 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1796 }
1797
1798 // Does the CPU require late expand (see block.cpp for description of late expand)?
1799 const bool Matcher::require_postalloc_expand = false;
1800
1801 // Do we need to mask the count passed to shift instructions or does
1802 // the cpu only look at the lower 5/6 bits anyway?
1803 const bool Matcher::need_masked_shift_count = false;
1804
1805 bool Matcher::narrow_oop_use_complex_address() {
1806 assert(UseCompressedOops, "only for compressed oops code");
1807 return false;
1808 }
1809
1810 bool Matcher::narrow_klass_use_complex_address() {
1811 assert(UseCompressedClassPointers, "only for compressed klass code");
1812 return false;
1813 }
1814
1815 bool Matcher::const_oop_prefer_decode() {
1816 // TODO: Check if loading ConP from TOC in heap-based mode is better:
1817 // Prefer ConN+DecodeN over ConP in simple compressed oops mode.
1818 // return Universe::narrow_oop_base() == NULL;
1819 return true;
1820 }
1821
1822 bool Matcher::const_klass_prefer_decode() {
1823 // TODO: Check if loading ConP from TOC in heap-based mode is better:
1824 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1825 // return Universe::narrow_klass_base() == NULL;
1826 return true;
1827 }
1828
1829 // Is it better to copy float constants, or load them directly from memory?
1830 // Intel can load a float constant from a direct address, requiring no
1831 // extra registers. Most RISCs will have to materialize an address into a
1832 // register first, so they would do better to copy the constant from stack.
1833 const bool Matcher::rematerialize_float_constants = false;
1834
1835 // If CPU can load and store mis-aligned doubles directly then no fixup is
1836 // needed. Else we split the double into 2 integer pieces and move it
1837 // piece-by-piece. Only happens when passing doubles into C code as the
1838 // Java calling convention forces doubles to be aligned.
1839 const bool Matcher::misaligned_doubles_ok = true;
1840
1841 // No-op on SPARC.
1842 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1843 }
1844
1845 // Advertise here if the CPU requires explicit rounding operations
1846 // to implement the UseStrictFP mode.
1847 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1848
1849 // Are floats converted to double when stored to stack during deoptimization?
1850 // Sparc does not handle callee-save floats.
1851 bool Matcher::float_in_double() { return false; }
1852
1853 // Do ints take an entire long register or just half?
1854 // Note that we if-def off of _LP64.
1855 // The relevant question is how the int is callee-saved. In _LP64
1856 // the whole long is written but de-opt'ing will have to extract
1857 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1858 const bool Matcher::int_in_long = true;
1859
1860 // Return whether or not this register is ever used as an argument. This
1861 // function is used on startup to build the trampoline stubs in generateOptoStub.
1862 // Registers not mentioned will be killed by the VM call in the trampoline, and
1863 // arguments in those registers not be available to the callee.
1864 bool Matcher::can_be_java_arg( int reg ) {
1865 // Standard sparc 6 args in registers
1866 if( reg == R_I0_num ||
1867 reg == R_I1_num ||
1868 reg == R_I2_num ||
1869 reg == R_I3_num ||
1870 reg == R_I4_num ||
1871 reg == R_I5_num ) return true;
1872 // 64-bit builds can pass 64-bit pointers and longs in
1873 // the high I registers
1874 if( reg == R_I0H_num ||
1875 reg == R_I1H_num ||
1876 reg == R_I2H_num ||
1877 reg == R_I3H_num ||
1878 reg == R_I4H_num ||
1879 reg == R_I5H_num ) return true;
1880
1881 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1882 return true;
1883 }
1884
1885 // A few float args in registers
1886 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1887
1888 return false;
1889 }
1890
1891 bool Matcher::is_spillable_arg( int reg ) {
1892 return can_be_java_arg(reg);
1893 }
1894
1895 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1896 // Use hardware SDIVX instruction when it is
1897 // faster than a code which use multiply.
1898 return VM_Version::has_fast_idiv();
1899 }
1900
1901 // Register for DIVI projection of divmodI
1902 RegMask Matcher::divI_proj_mask() {
1903 ShouldNotReachHere();
1904 return RegMask();
1905 }
1906
1907 // Register for MODI projection of divmodI
1908 RegMask Matcher::modI_proj_mask() {
1909 ShouldNotReachHere();
1910 return RegMask();
1911 }
1912
1913 // Register for DIVL projection of divmodL
1914 RegMask Matcher::divL_proj_mask() {
1915 ShouldNotReachHere();
1916 return RegMask();
1917 }
1918
1919 // Register for MODL projection of divmodL
1920 RegMask Matcher::modL_proj_mask() {
1921 ShouldNotReachHere();
1922 return RegMask();
1923 }
1924
1925 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1926 return L7_REGP_mask();
1927 }
1928
1929
1930 const bool Matcher::convi2l_type_required = true;
1931
1932 // Should the Matcher clone shifts on addressing modes, expecting them
1933 // to be subsumed into complex addressing expressions or compute them
1934 // into registers?
1935 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
1936 return clone_base_plus_offset_address(m, mstack, address_visited);
1937 }
1938
1939 void Compile::reshape_address(AddPNode* addp) {
1940 }
1941
1942 %}
1943
1944
1945 // The intptr_t operand types, defined by textual substitution.
1946 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1947 #define immX immL
1948 #define immX13 immL13
1949 #define immX13m7 immL13m7
1950 #define iRegX iRegL
1951 #define g1RegX g1RegL
1952
1953 //----------ENCODING BLOCK-----------------------------------------------------
1954 // This block specifies the encoding classes used by the compiler to output
1955 // byte streams. Encoding classes are parameterized macros used by
1956 // Machine Instruction Nodes in order to generate the bit encoding of the
1957 // instruction. Operands specify their base encoding interface with the
1958 // interface keyword. There are currently supported four interfaces,
1959 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1960 // operand to generate a function which returns its register number when
1961 // queried. CONST_INTER causes an operand to generate a function which
1962 // returns the value of the constant when queried. MEMORY_INTER causes an
1963 // operand to generate four functions which return the Base Register, the
1964 // Index Register, the Scale Value, and the Offset Value of the operand when
1965 // queried. COND_INTER causes an operand to generate six functions which
1966 // return the encoding code (ie - encoding bits for the instruction)
1967 // associated with each basic boolean condition for a conditional instruction.
1968 //
1969 // Instructions specify two basic values for encoding. Again, a function
1970 // is available to check if the constant displacement is an oop. They use the
1971 // ins_encode keyword to specify their encoding classes (which must be
1972 // a sequence of enc_class names, and their parameters, specified in
1973 // the encoding block), and they use the
1974 // opcode keyword to specify, in order, their primary, secondary, and
1975 // tertiary opcode. Only the opcode sections which a particular instruction
1976 // needs for encoding need to be specified.
1977 encode %{
1978 enc_class enc_untested %{
1979 #ifdef ASSERT
1980 MacroAssembler _masm(&cbuf);
1981 __ untested("encoding");
1982 #endif
1983 %}
1984
1985 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
1986 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
1987 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1988 %}
1989
1990 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
1991 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
1992 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1993 %}
1994
1995 enc_class form3_mem_prefetch_read( memory mem ) %{
1996 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
1997 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
1998 %}
1999
2000 enc_class form3_mem_prefetch_write( memory mem ) %{
2001 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2002 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2003 %}
2004
2005 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2006 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2007 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2008 guarantee($mem$$index == R_G0_enc, "double index?");
2009 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2010 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2011 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2012 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2013 %}
2014
2015 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2016 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2017 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2018 guarantee($mem$$index == R_G0_enc, "double index?");
2019 // Load long with 2 instructions
2020 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2021 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2022 %}
2023
2024 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2025 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2026 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2027 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2028 %}
2029
2030 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2031 // Encode a reg-reg copy. If it is useless, then empty encoding.
2032 if( $rs2$$reg != $rd$$reg )
2033 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2034 %}
2035
2036 // Target lo half of long
2037 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2038 // Encode a reg-reg copy. If it is useless, then empty encoding.
2039 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2040 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2041 %}
2042
2043 // Source lo half of long
2044 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2045 // Encode a reg-reg copy. If it is useless, then empty encoding.
2046 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2047 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2048 %}
2049
2050 // Target hi half of long
2051 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2052 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2053 %}
2054
2055 // Source lo half of long, and leave it sign extended.
2056 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2057 // Sign extend low half
2058 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2059 %}
2060
2061 // Source hi half of long, and leave it sign extended.
2062 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2063 // Shift high half to low half
2064 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2065 %}
2066
2067 // Source hi half of long
2068 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2069 // Encode a reg-reg copy. If it is useless, then empty encoding.
2070 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2071 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2072 %}
2073
2074 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2075 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2076 %}
2077
2078 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2079 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2080 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2081 %}
2082
2083 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2084 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2085 // clear if nothing else is happening
2086 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2087 // blt,a,pn done
2088 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2089 // mov dst,-1 in delay slot
2090 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2091 %}
2092
2093 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2094 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2095 %}
2096
2097 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2098 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2099 %}
2100
2101 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2102 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2103 %}
2104
2105 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2106 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2107 %}
2108
2109 enc_class move_return_pc_to_o1() %{
2110 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2111 %}
2112
2113 /* %%% merge with enc_to_bool */
2114 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2115 MacroAssembler _masm(&cbuf);
2116
2117 Register src_reg = reg_to_register_object($src$$reg);
2118 Register dst_reg = reg_to_register_object($dst$$reg);
2119 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2120 %}
2121
2122 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2123 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2124 MacroAssembler _masm(&cbuf);
2125
2126 Register p_reg = reg_to_register_object($p$$reg);
2127 Register q_reg = reg_to_register_object($q$$reg);
2128 Register y_reg = reg_to_register_object($y$$reg);
2129 Register tmp_reg = reg_to_register_object($tmp$$reg);
2130
2131 __ subcc( p_reg, q_reg, p_reg );
2132 __ add ( p_reg, y_reg, tmp_reg );
2133 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2134 %}
2135
2136 enc_class form_d2i_helper(regD src, regF dst) %{
2137 // fcmp %fcc0,$src,$src
2138 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2139 // branch %fcc0 not-nan, predict taken
2140 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2141 // fdtoi $src,$dst
2142 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2143 // fitos $dst,$dst (if nan)
2144 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2145 // clear $dst (if nan)
2146 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2147 // carry on here...
2148 %}
2149
2150 enc_class form_d2l_helper(regD src, regD dst) %{
2151 // fcmp %fcc0,$src,$src check for NAN
2152 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2153 // branch %fcc0 not-nan, predict taken
2154 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2155 // fdtox $src,$dst convert in delay slot
2156 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2157 // fxtod $dst,$dst (if nan)
2158 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2159 // clear $dst (if nan)
2160 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2161 // carry on here...
2162 %}
2163
2164 enc_class form_f2i_helper(regF src, regF dst) %{
2165 // fcmps %fcc0,$src,$src
2166 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2167 // branch %fcc0 not-nan, predict taken
2168 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2169 // fstoi $src,$dst
2170 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2171 // fitos $dst,$dst (if nan)
2172 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2173 // clear $dst (if nan)
2174 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2175 // carry on here...
2176 %}
2177
2178 enc_class form_f2l_helper(regF src, regD dst) %{
2179 // fcmps %fcc0,$src,$src
2180 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2181 // branch %fcc0 not-nan, predict taken
2182 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2183 // fstox $src,$dst
2184 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2185 // fxtod $dst,$dst (if nan)
2186 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2187 // clear $dst (if nan)
2188 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2189 // carry on here...
2190 %}
2191
2192 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2193 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2194 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2195 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2196
2197 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2198
2199 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2200 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2201
2202 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2203 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2204 %}
2205
2206 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2207 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2208 %}
2209
2210 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2211 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2212 %}
2213
2214 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2215 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2216 %}
2217
2218 enc_class form3_convI2F(regF rs2, regF rd) %{
2219 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2220 %}
2221
2222 // Encloding class for traceable jumps
2223 enc_class form_jmpl(g3RegP dest) %{
2224 emit_jmpl(cbuf, $dest$$reg);
2225 %}
2226
2227 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2228 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2229 %}
2230
2231 enc_class form2_nop() %{
2232 emit_nop(cbuf);
2233 %}
2234
2235 enc_class form2_illtrap() %{
2236 emit_illtrap(cbuf);
2237 %}
2238
2239
2240 // Compare longs and convert into -1, 0, 1.
2241 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2242 // CMP $src1,$src2
2243 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2244 // blt,a,pn done
2245 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2246 // mov dst,-1 in delay slot
2247 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2248 // bgt,a,pn done
2249 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2250 // mov dst,1 in delay slot
2251 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2252 // CLR $dst
2253 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2254 %}
2255
2256 enc_class enc_PartialSubtypeCheck() %{
2257 MacroAssembler _masm(&cbuf);
2258 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2259 __ delayed()->nop();
2260 %}
2261
2262 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2263 MacroAssembler _masm(&cbuf);
2264 Label* L = $labl$$label;
2265 Assembler::Predict predict_taken =
2266 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2267
2268 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2269 __ delayed()->nop();
2270 %}
2271
2272 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2273 MacroAssembler _masm(&cbuf);
2274 Label* L = $labl$$label;
2275 Assembler::Predict predict_taken =
2276 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2277
2278 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2279 __ delayed()->nop();
2280 %}
2281
2282 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2283 int op = (Assembler::arith_op << 30) |
2284 ($dst$$reg << 25) |
2285 (Assembler::movcc_op3 << 19) |
2286 (1 << 18) | // cc2 bit for 'icc'
2287 ($cmp$$cmpcode << 14) |
2288 (0 << 13) | // select register move
2289 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2290 ($src$$reg << 0);
2291 cbuf.insts()->emit_int32(op);
2292 %}
2293
2294 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2295 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2296 int op = (Assembler::arith_op << 30) |
2297 ($dst$$reg << 25) |
2298 (Assembler::movcc_op3 << 19) |
2299 (1 << 18) | // cc2 bit for 'icc'
2300 ($cmp$$cmpcode << 14) |
2301 (1 << 13) | // select immediate move
2302 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2303 (simm11 << 0);
2304 cbuf.insts()->emit_int32(op);
2305 %}
2306
2307 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2308 int op = (Assembler::arith_op << 30) |
2309 ($dst$$reg << 25) |
2310 (Assembler::movcc_op3 << 19) |
2311 (0 << 18) | // cc2 bit for 'fccX'
2312 ($cmp$$cmpcode << 14) |
2313 (0 << 13) | // select register move
2314 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2315 ($src$$reg << 0);
2316 cbuf.insts()->emit_int32(op);
2317 %}
2318
2319 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2320 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2321 int op = (Assembler::arith_op << 30) |
2322 ($dst$$reg << 25) |
2323 (Assembler::movcc_op3 << 19) |
2324 (0 << 18) | // cc2 bit for 'fccX'
2325 ($cmp$$cmpcode << 14) |
2326 (1 << 13) | // select immediate move
2327 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2328 (simm11 << 0);
2329 cbuf.insts()->emit_int32(op);
2330 %}
2331
2332 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2333 int op = (Assembler::arith_op << 30) |
2334 ($dst$$reg << 25) |
2335 (Assembler::fpop2_op3 << 19) |
2336 (0 << 18) |
2337 ($cmp$$cmpcode << 14) |
2338 (1 << 13) | // select register move
2339 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2340 ($primary << 5) | // select single, double or quad
2341 ($src$$reg << 0);
2342 cbuf.insts()->emit_int32(op);
2343 %}
2344
2345 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2346 int op = (Assembler::arith_op << 30) |
2347 ($dst$$reg << 25) |
2348 (Assembler::fpop2_op3 << 19) |
2349 (0 << 18) |
2350 ($cmp$$cmpcode << 14) |
2351 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2352 ($primary << 5) | // select single, double or quad
2353 ($src$$reg << 0);
2354 cbuf.insts()->emit_int32(op);
2355 %}
2356
2357 // Used by the MIN/MAX encodings. Same as a CMOV, but
2358 // the condition comes from opcode-field instead of an argument.
2359 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2360 int op = (Assembler::arith_op << 30) |
2361 ($dst$$reg << 25) |
2362 (Assembler::movcc_op3 << 19) |
2363 (1 << 18) | // cc2 bit for 'icc'
2364 ($primary << 14) |
2365 (0 << 13) | // select register move
2366 (0 << 11) | // cc1, cc0 bits for 'icc'
2367 ($src$$reg << 0);
2368 cbuf.insts()->emit_int32(op);
2369 %}
2370
2371 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2372 int op = (Assembler::arith_op << 30) |
2373 ($dst$$reg << 25) |
2374 (Assembler::movcc_op3 << 19) |
2375 (6 << 16) | // cc2 bit for 'xcc'
2376 ($primary << 14) |
2377 (0 << 13) | // select register move
2378 (0 << 11) | // cc1, cc0 bits for 'icc'
2379 ($src$$reg << 0);
2380 cbuf.insts()->emit_int32(op);
2381 %}
2382
2383 enc_class Set13( immI13 src, iRegI rd ) %{
2384 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2385 %}
2386
2387 enc_class SetHi22( immI src, iRegI rd ) %{
2388 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2389 %}
2390
2391 enc_class Set32( immI src, iRegI rd ) %{
2392 MacroAssembler _masm(&cbuf);
2393 __ set($src$$constant, reg_to_register_object($rd$$reg));
2394 %}
2395
2396 enc_class call_epilog %{
2397 if( VerifyStackAtCalls ) {
2398 MacroAssembler _masm(&cbuf);
2399 int framesize = ra_->C->frame_size_in_bytes();
2400 Register temp_reg = G3;
2401 __ add(SP, framesize, temp_reg);
2402 __ cmp(temp_reg, FP);
2403 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2404 }
2405 %}
2406
2407 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2408 // to G1 so the register allocator will not have to deal with the misaligned register
2409 // pair.
2410 enc_class adjust_long_from_native_call %{
2411 %}
2412
2413 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2414 // CALL directly to the runtime
2415 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2416 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true);
2417 %}
2418
2419 enc_class preserve_SP %{
2420 MacroAssembler _masm(&cbuf);
2421 __ mov(SP, L7_mh_SP_save);
2422 %}
2423
2424 enc_class restore_SP %{
2425 MacroAssembler _masm(&cbuf);
2426 __ mov(L7_mh_SP_save, SP);
2427 %}
2428
2429 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2430 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2431 // who we intended to call.
2432 if (!_method) {
2433 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec());
2434 } else {
2435 int method_index = resolved_method_index(cbuf);
2436 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2437 : static_call_Relocation::spec(method_index);
2438 emit_call_reloc(cbuf, $meth$$method, rspec);
2439
2440 // Emit stub for static call.
2441 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2442 if (stub == NULL) {
2443 ciEnv::current()->record_failure("CodeCache is full");
2444 return;
2445 }
2446 }
2447 %}
2448
2449 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2450 MacroAssembler _masm(&cbuf);
2451 __ set_inst_mark();
2452 int vtable_index = this->_vtable_index;
2453 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2454 if (vtable_index < 0) {
2455 // must be invalid_vtable_index, not nonvirtual_vtable_index
2456 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2457 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2458 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2459 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2460 __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf));
2461 } else {
2462 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2463 // Just go thru the vtable
2464 // get receiver klass (receiver already checked for non-null)
2465 // If we end up going thru a c2i adapter interpreter expects method in G5
2466 int off = __ offset();
2467 __ load_klass(O0, G3_scratch);
2468 int klass_load_size;
2469 if (UseCompressedClassPointers) {
2470 assert(Universe::heap() != NULL, "java heap should be initialized");
2471 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2472 } else {
2473 klass_load_size = 1*BytesPerInstWord;
2474 }
2475 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
2476 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
2477 if (Assembler::is_simm13(v_off)) {
2478 __ ld_ptr(G3, v_off, G5_method);
2479 } else {
2480 // Generate 2 instructions
2481 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2482 __ or3(G5_method, v_off & 0x3ff, G5_method);
2483 // ld_ptr, set_hi, set
2484 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2485 "Unexpected instruction size(s)");
2486 __ ld_ptr(G3, G5_method, G5_method);
2487 }
2488 // NOTE: for vtable dispatches, the vtable entry will never be null.
2489 // However it may very well end up in handle_wrong_method if the
2490 // method is abstract for the particular class.
2491 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2492 // jump to target (either compiled code or c2iadapter)
2493 __ jmpl(G3_scratch, G0, O7);
2494 __ delayed()->nop();
2495 }
2496 %}
2497
2498 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2499 MacroAssembler _masm(&cbuf);
2500
2501 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2502 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2503 // we might be calling a C2I adapter which needs it.
2504
2505 assert(temp_reg != G5_ic_reg, "conflicting registers");
2506 // Load nmethod
2507 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2508
2509 // CALL to compiled java, indirect the contents of G3
2510 __ set_inst_mark();
2511 __ callr(temp_reg, G0);
2512 __ delayed()->nop();
2513 %}
2514
2515 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2516 MacroAssembler _masm(&cbuf);
2517 Register Rdividend = reg_to_register_object($src1$$reg);
2518 Register Rdivisor = reg_to_register_object($src2$$reg);
2519 Register Rresult = reg_to_register_object($dst$$reg);
2520
2521 __ sra(Rdivisor, 0, Rdivisor);
2522 __ sra(Rdividend, 0, Rdividend);
2523 __ sdivx(Rdividend, Rdivisor, Rresult);
2524 %}
2525
2526 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2527 MacroAssembler _masm(&cbuf);
2528
2529 Register Rdividend = reg_to_register_object($src1$$reg);
2530 int divisor = $imm$$constant;
2531 Register Rresult = reg_to_register_object($dst$$reg);
2532
2533 __ sra(Rdividend, 0, Rdividend);
2534 __ sdivx(Rdividend, divisor, Rresult);
2535 %}
2536
2537 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2538 MacroAssembler _masm(&cbuf);
2539 Register Rsrc1 = reg_to_register_object($src1$$reg);
2540 Register Rsrc2 = reg_to_register_object($src2$$reg);
2541 Register Rdst = reg_to_register_object($dst$$reg);
2542
2543 __ sra( Rsrc1, 0, Rsrc1 );
2544 __ sra( Rsrc2, 0, Rsrc2 );
2545 __ mulx( Rsrc1, Rsrc2, Rdst );
2546 __ srlx( Rdst, 32, Rdst );
2547 %}
2548
2549 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2550 MacroAssembler _masm(&cbuf);
2551 Register Rdividend = reg_to_register_object($src1$$reg);
2552 Register Rdivisor = reg_to_register_object($src2$$reg);
2553 Register Rresult = reg_to_register_object($dst$$reg);
2554 Register Rscratch = reg_to_register_object($scratch$$reg);
2555
2556 assert(Rdividend != Rscratch, "");
2557 assert(Rdivisor != Rscratch, "");
2558
2559 __ sra(Rdividend, 0, Rdividend);
2560 __ sra(Rdivisor, 0, Rdivisor);
2561 __ sdivx(Rdividend, Rdivisor, Rscratch);
2562 __ mulx(Rscratch, Rdivisor, Rscratch);
2563 __ sub(Rdividend, Rscratch, Rresult);
2564 %}
2565
2566 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2567 MacroAssembler _masm(&cbuf);
2568
2569 Register Rdividend = reg_to_register_object($src1$$reg);
2570 int divisor = $imm$$constant;
2571 Register Rresult = reg_to_register_object($dst$$reg);
2572 Register Rscratch = reg_to_register_object($scratch$$reg);
2573
2574 assert(Rdividend != Rscratch, "");
2575
2576 __ sra(Rdividend, 0, Rdividend);
2577 __ sdivx(Rdividend, divisor, Rscratch);
2578 __ mulx(Rscratch, divisor, Rscratch);
2579 __ sub(Rdividend, Rscratch, Rresult);
2580 %}
2581
2582 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2583 MacroAssembler _masm(&cbuf);
2584
2585 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2586 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2587
2588 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2589 %}
2590
2591 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2592 MacroAssembler _masm(&cbuf);
2593
2594 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2595 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2596
2597 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2598 %}
2599
2600 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2601 MacroAssembler _masm(&cbuf);
2602
2603 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2604 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2605
2606 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2607 %}
2608
2609 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2610 MacroAssembler _masm(&cbuf);
2611
2612 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2613 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2614
2615 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2616 %}
2617
2618 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2619 MacroAssembler _masm(&cbuf);
2620
2621 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2622 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2623
2624 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2625 %}
2626
2627 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2628 MacroAssembler _masm(&cbuf);
2629
2630 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2631 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2632
2633 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2634 %}
2635
2636 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2637 MacroAssembler _masm(&cbuf);
2638
2639 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2640 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2641
2642 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2643 %}
2644
2645 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2646 MacroAssembler _masm(&cbuf);
2647
2648 Register Roop = reg_to_register_object($oop$$reg);
2649 Register Rbox = reg_to_register_object($box$$reg);
2650 Register Rscratch = reg_to_register_object($scratch$$reg);
2651 Register Rmark = reg_to_register_object($scratch2$$reg);
2652
2653 assert(Roop != Rscratch, "");
2654 assert(Roop != Rmark, "");
2655 assert(Rbox != Rscratch, "");
2656 assert(Rbox != Rmark, "");
2657
2658 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2659 %}
2660
2661 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2662 MacroAssembler _masm(&cbuf);
2663
2664 Register Roop = reg_to_register_object($oop$$reg);
2665 Register Rbox = reg_to_register_object($box$$reg);
2666 Register Rscratch = reg_to_register_object($scratch$$reg);
2667 Register Rmark = reg_to_register_object($scratch2$$reg);
2668
2669 assert(Roop != Rscratch, "");
2670 assert(Roop != Rmark, "");
2671 assert(Rbox != Rscratch, "");
2672 assert(Rbox != Rmark, "");
2673
2674 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2675 %}
2676
2677 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2678 MacroAssembler _masm(&cbuf);
2679 Register Rmem = reg_to_register_object($mem$$reg);
2680 Register Rold = reg_to_register_object($old$$reg);
2681 Register Rnew = reg_to_register_object($new$$reg);
2682
2683 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2684 __ cmp( Rold, Rnew );
2685 %}
2686
2687 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2688 Register Rmem = reg_to_register_object($mem$$reg);
2689 Register Rold = reg_to_register_object($old$$reg);
2690 Register Rnew = reg_to_register_object($new$$reg);
2691
2692 MacroAssembler _masm(&cbuf);
2693 __ mov(Rnew, O7);
2694 __ casx(Rmem, Rold, O7);
2695 __ cmp( Rold, O7 );
2696 %}
2697
2698 // raw int cas, used for compareAndSwap
2699 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2700 Register Rmem = reg_to_register_object($mem$$reg);
2701 Register Rold = reg_to_register_object($old$$reg);
2702 Register Rnew = reg_to_register_object($new$$reg);
2703
2704 MacroAssembler _masm(&cbuf);
2705 __ mov(Rnew, O7);
2706 __ cas(Rmem, Rold, O7);
2707 __ cmp( Rold, O7 );
2708 %}
2709
2710 // raw int cas without using tmp register for compareAndExchange
2711 enc_class enc_casi_exch( iRegP mem, iRegL old, iRegL new) %{
2712 Register Rmem = reg_to_register_object($mem$$reg);
2713 Register Rold = reg_to_register_object($old$$reg);
2714 Register Rnew = reg_to_register_object($new$$reg);
2715
2716 MacroAssembler _masm(&cbuf);
2717 __ cas(Rmem, Rold, Rnew);
2718 %}
2719
2720 // 64-bit cas without using tmp register for compareAndExchange
2721 enc_class enc_casx_exch( iRegP mem, iRegL old, iRegL new) %{
2722 Register Rmem = reg_to_register_object($mem$$reg);
2723 Register Rold = reg_to_register_object($old$$reg);
2724 Register Rnew = reg_to_register_object($new$$reg);
2725
2726 MacroAssembler _masm(&cbuf);
2727 __ casx(Rmem, Rold, Rnew);
2728 %}
2729
2730 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2731 Register Rres = reg_to_register_object($res$$reg);
2732
2733 MacroAssembler _masm(&cbuf);
2734 __ mov(1, Rres);
2735 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2736 %}
2737
2738 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2739 Register Rres = reg_to_register_object($res$$reg);
2740
2741 MacroAssembler _masm(&cbuf);
2742 __ mov(1, Rres);
2743 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2744 %}
2745
2746 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2747 MacroAssembler _masm(&cbuf);
2748 Register Rdst = reg_to_register_object($dst$$reg);
2749 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2750 : reg_to_DoubleFloatRegister_object($src1$$reg);
2751 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2752 : reg_to_DoubleFloatRegister_object($src2$$reg);
2753
2754 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2755 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2756 %}
2757
2758 enc_class enc_rethrow() %{
2759 cbuf.set_insts_mark();
2760 Register temp_reg = G3;
2761 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
2762 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
2763 MacroAssembler _masm(&cbuf);
2764 #ifdef ASSERT
2765 __ save_frame(0);
2766 AddressLiteral last_rethrow_addrlit(&last_rethrow);
2767 __ sethi(last_rethrow_addrlit, L1);
2768 Address addr(L1, last_rethrow_addrlit.low10());
2769 __ rdpc(L2);
2770 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
2771 __ st_ptr(L2, addr);
2772 __ restore();
2773 #endif
2774 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
2775 __ delayed()->nop();
2776 %}
2777
2778 enc_class emit_mem_nop() %{
2779 // Generates the instruction LDUXA [o6,g0],#0x82,g0
2780 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
2781 %}
2782
2783 enc_class emit_fadd_nop() %{
2784 // Generates the instruction FMOVS f31,f31
2785 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
2786 %}
2787
2788 enc_class emit_br_nop() %{
2789 // Generates the instruction BPN,PN .
2790 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
2791 %}
2792
2793 enc_class enc_membar_acquire %{
2794 MacroAssembler _masm(&cbuf);
2795 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
2796 %}
2797
2798 enc_class enc_membar_release %{
2799 MacroAssembler _masm(&cbuf);
2800 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
2801 %}
2802
2803 enc_class enc_membar_volatile %{
2804 MacroAssembler _masm(&cbuf);
2805 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
2806 %}
2807
2808 %}
2809
2810 //----------FRAME--------------------------------------------------------------
2811 // Definition of frame structure and management information.
2812 //
2813 // S T A C K L A Y O U T Allocators stack-slot number
2814 // | (to get allocators register number
2815 // G Owned by | | v add VMRegImpl::stack0)
2816 // r CALLER | |
2817 // o | +--------+ pad to even-align allocators stack-slot
2818 // w V | pad0 | numbers; owned by CALLER
2819 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2820 // h ^ | in | 5
2821 // | | args | 4 Holes in incoming args owned by SELF
2822 // | | | | 3
2823 // | | +--------+
2824 // V | | old out| Empty on Intel, window on Sparc
2825 // | old |preserve| Must be even aligned.
2826 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
2827 // | | in | 3 area for Intel ret address
2828 // Owned by |preserve| Empty on Sparc.
2829 // SELF +--------+
2830 // | | pad2 | 2 pad to align old SP
2831 // | +--------+ 1
2832 // | | locks | 0
2833 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
2834 // | | pad1 | 11 pad to align new SP
2835 // | +--------+
2836 // | | | 10
2837 // | | spills | 9 spills
2838 // V | | 8 (pad0 slot for callee)
2839 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2840 // ^ | out | 7
2841 // | | args | 6 Holes in outgoing args owned by CALLEE
2842 // Owned by +--------+
2843 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2844 // | new |preserve| Must be even-aligned.
2845 // | SP-+--------+----> Matcher::_new_SP, even aligned
2846 // | | |
2847 //
2848 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2849 // known from SELF's arguments and the Java calling convention.
2850 // Region 6-7 is determined per call site.
2851 // Note 2: If the calling convention leaves holes in the incoming argument
2852 // area, those holes are owned by SELF. Holes in the outgoing area
2853 // are owned by the CALLEE. Holes should not be nessecary in the
2854 // incoming area, as the Java calling convention is completely under
2855 // the control of the AD file. Doubles can be sorted and packed to
2856 // avoid holes. Holes in the outgoing arguments may be necessary for
2857 // varargs C calling conventions.
2858 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2859 // even aligned with pad0 as needed.
2860 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2861 // region 6-11 is even aligned; it may be padded out more so that
2862 // the region from SP to FP meets the minimum stack alignment.
2863
2864 frame %{
2865 // What direction does stack grow in (assumed to be same for native & Java)
2866 stack_direction(TOWARDS_LOW);
2867
2868 // These two registers define part of the calling convention
2869 // between compiled code and the interpreter.
2870 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
2871 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
2872
2873 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2874 cisc_spilling_operand_name(indOffset);
2875
2876 // Number of stack slots consumed by a Monitor enter
2877 sync_stack_slots(2);
2878
2879 // Compiled code's Frame Pointer
2880 frame_pointer(R_SP);
2881
2882 // Stack alignment requirement
2883 stack_alignment(StackAlignmentInBytes);
2884 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
2885 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
2886
2887 // Number of stack slots between incoming argument block and the start of
2888 // a new frame. The PROLOG must add this many slots to the stack. The
2889 // EPILOG must remove this many slots.
2890 in_preserve_stack_slots(0);
2891
2892 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2893 // for calls to C. Supports the var-args backing area for register parms.
2894 // ADLC doesn't support parsing expressions, so I folded the math by hand.
2895 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
2896 varargs_C_out_slots_killed(12);
2897
2898 // The after-PROLOG location of the return address. Location of
2899 // return address specifies a type (REG or STACK) and a number
2900 // representing the register number (i.e. - use a register name) or
2901 // stack slot.
2902 return_addr(REG R_I7); // Ret Addr is in register I7
2903
2904 // Body of function which returns an OptoRegs array locating
2905 // arguments either in registers or in stack slots for calling
2906 // java
2907 calling_convention %{
2908 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
2909
2910 %}
2911
2912 // Body of function which returns an OptoRegs array locating
2913 // arguments either in registers or in stack slots for calling
2914 // C.
2915 c_calling_convention %{
2916 // This is obviously always outgoing
2917 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2918 %}
2919
2920 // Location of native (C/C++) and interpreter return values. This is specified to
2921 // be the same as Java. In the 32-bit VM, long values are actually returned from
2922 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
2923 // to and from the register pairs is done by the appropriate call and epilog
2924 // opcodes. This simplifies the register allocator.
2925 c_return_value %{
2926 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
2927 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
2928 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
2929 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
2930 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
2931 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
2932 (is_outgoing?lo_out:lo_in)[ideal_reg] );
2933 %}
2934
2935 // Location of compiled Java return values. Same as C
2936 return_value %{
2937 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
2938 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
2939 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
2940 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
2941 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
2942 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
2943 (is_outgoing?lo_out:lo_in)[ideal_reg] );
2944 %}
2945
2946 %}
2947
2948
2949 //----------ATTRIBUTES---------------------------------------------------------
2950 //----------Operand Attributes-------------------------------------------------
2951 op_attrib op_cost(1); // Required cost attribute
2952
2953 //----------Instruction Attributes---------------------------------------------
2954 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2955 ins_attrib ins_size(32); // Required size attribute (in bits)
2956
2957 // avoid_back_to_back attribute is an expression that must return
2958 // one of the following values defined in MachNode:
2959 // AVOID_NONE - instruction can be placed anywhere
2960 // AVOID_BEFORE - instruction cannot be placed after an
2961 // instruction with MachNode::AVOID_AFTER
2962 // AVOID_AFTER - the next instruction cannot be the one
2963 // with MachNode::AVOID_BEFORE
2964 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
2965 // the same time
2966 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
2967
2968 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
2969 // non-matching short branch variant of some
2970 // long branch?
2971
2972 //----------OPERANDS-----------------------------------------------------------
2973 // Operand definitions must precede instruction definitions for correct parsing
2974 // in the ADLC because operands constitute user defined types which are used in
2975 // instruction definitions.
2976
2977 //----------Simple Operands----------------------------------------------------
2978 // Immediate Operands
2979 // Integer Immediate: 32-bit
2980 operand immI() %{
2981 match(ConI);
2982
2983 op_cost(0);
2984 // formats are generated automatically for constants and base registers
2985 format %{ %}
2986 interface(CONST_INTER);
2987 %}
2988
2989 // Integer Immediate: 0-bit
2990 operand immI0() %{
2991 predicate(n->get_int() == 0);
2992 match(ConI);
2993 op_cost(0);
2994
2995 format %{ %}
2996 interface(CONST_INTER);
2997 %}
2998
2999 // Integer Immediate: 5-bit
3000 operand immI5() %{
3001 predicate(Assembler::is_simm5(n->get_int()));
3002 match(ConI);
3003 op_cost(0);
3004 format %{ %}
3005 interface(CONST_INTER);
3006 %}
3007
3008 // Integer Immediate: 8-bit
3009 operand immI8() %{
3010 predicate(Assembler::is_simm8(n->get_int()));
3011 match(ConI);
3012 op_cost(0);
3013 format %{ %}
3014 interface(CONST_INTER);
3015 %}
3016
3017 // Integer Immediate: the value 10
3018 operand immI10() %{
3019 predicate(n->get_int() == 10);
3020 match(ConI);
3021 op_cost(0);
3022
3023 format %{ %}
3024 interface(CONST_INTER);
3025 %}
3026
3027 // Integer Immediate: 11-bit
3028 operand immI11() %{
3029 predicate(Assembler::is_simm11(n->get_int()));
3030 match(ConI);
3031 op_cost(0);
3032 format %{ %}
3033 interface(CONST_INTER);
3034 %}
3035
3036 // Integer Immediate: 13-bit
3037 operand immI13() %{
3038 predicate(Assembler::is_simm13(n->get_int()));
3039 match(ConI);
3040 op_cost(0);
3041
3042 format %{ %}
3043 interface(CONST_INTER);
3044 %}
3045
3046 // Integer Immediate: 13-bit minus 7
3047 operand immI13m7() %{
3048 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3049 match(ConI);
3050 op_cost(0);
3051
3052 format %{ %}
3053 interface(CONST_INTER);
3054 %}
3055
3056 // Integer Immediate: 16-bit
3057 operand immI16() %{
3058 predicate(Assembler::is_simm16(n->get_int()));
3059 match(ConI);
3060 op_cost(0);
3061 format %{ %}
3062 interface(CONST_INTER);
3063 %}
3064
3065 // Integer Immediate: the values 1-31
3066 operand immI_1_31() %{
3067 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3068 match(ConI);
3069 op_cost(0);
3070
3071 format %{ %}
3072 interface(CONST_INTER);
3073 %}
3074
3075 // Integer Immediate: the values 32-63
3076 operand immI_32_63() %{
3077 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3078 match(ConI);
3079 op_cost(0);
3080
3081 format %{ %}
3082 interface(CONST_INTER);
3083 %}
3084
3085 // Immediates for special shifts (sign extend)
3086
3087 // Integer Immediate: the value 16
3088 operand immI_16() %{
3089 predicate(n->get_int() == 16);
3090 match(ConI);
3091 op_cost(0);
3092
3093 format %{ %}
3094 interface(CONST_INTER);
3095 %}
3096
3097 // Integer Immediate: the value 24
3098 operand immI_24() %{
3099 predicate(n->get_int() == 24);
3100 match(ConI);
3101 op_cost(0);
3102
3103 format %{ %}
3104 interface(CONST_INTER);
3105 %}
3106 // Integer Immediate: the value 255
3107 operand immI_255() %{
3108 predicate( n->get_int() == 255 );
3109 match(ConI);
3110 op_cost(0);
3111
3112 format %{ %}
3113 interface(CONST_INTER);
3114 %}
3115
3116 // Integer Immediate: the value 65535
3117 operand immI_65535() %{
3118 predicate(n->get_int() == 65535);
3119 match(ConI);
3120 op_cost(0);
3121
3122 format %{ %}
3123 interface(CONST_INTER);
3124 %}
3125
3126 // Integer Immediate: the values 0-31
3127 operand immU5() %{
3128 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3129 match(ConI);
3130 op_cost(0);
3131
3132 format %{ %}
3133 interface(CONST_INTER);
3134 %}
3135
3136 // Integer Immediate: 6-bit
3137 operand immU6() %{
3138 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3139 match(ConI);
3140 op_cost(0);
3141 format %{ %}
3142 interface(CONST_INTER);
3143 %}
3144
3145 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3146 operand immU12() %{
3147 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3148 match(ConI);
3149 op_cost(0);
3150
3151 format %{ %}
3152 interface(CONST_INTER);
3153 %}
3154
3155 // Integer Immediate non-negative
3156 operand immU31()
3157 %{
3158 predicate(n->get_int() >= 0);
3159 match(ConI);
3160
3161 op_cost(0);
3162 format %{ %}
3163 interface(CONST_INTER);
3164 %}
3165
3166 // Long Immediate: the value FF
3167 operand immL_FF() %{
3168 predicate( n->get_long() == 0xFFL );
3169 match(ConL);
3170 op_cost(0);
3171
3172 format %{ %}
3173 interface(CONST_INTER);
3174 %}
3175
3176 // Long Immediate: the value FFFF
3177 operand immL_FFFF() %{
3178 predicate( n->get_long() == 0xFFFFL );
3179 match(ConL);
3180 op_cost(0);
3181
3182 format %{ %}
3183 interface(CONST_INTER);
3184 %}
3185
3186 // Pointer Immediate: 32 or 64-bit
3187 operand immP() %{
3188 match(ConP);
3189
3190 op_cost(5);
3191 // formats are generated automatically for constants and base registers
3192 format %{ %}
3193 interface(CONST_INTER);
3194 %}
3195
3196 // Pointer Immediate: 64-bit
3197 operand immP_set() %{
3198 predicate(!VM_Version::is_niagara_plus());
3199 match(ConP);
3200
3201 op_cost(5);
3202 // formats are generated automatically for constants and base registers
3203 format %{ %}
3204 interface(CONST_INTER);
3205 %}
3206
3207 // Pointer Immediate: 64-bit
3208 // From Niagara2 processors on a load should be better than materializing.
3209 operand immP_load() %{
3210 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3211 match(ConP);
3212
3213 op_cost(5);
3214 // formats are generated automatically for constants and base registers
3215 format %{ %}
3216 interface(CONST_INTER);
3217 %}
3218
3219 // Pointer Immediate: 64-bit
3220 operand immP_no_oop_cheap() %{
3221 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3222 match(ConP);
3223
3224 op_cost(5);
3225 // formats are generated automatically for constants and base registers
3226 format %{ %}
3227 interface(CONST_INTER);
3228 %}
3229
3230 operand immP13() %{
3231 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3232 match(ConP);
3233 op_cost(0);
3234
3235 format %{ %}
3236 interface(CONST_INTER);
3237 %}
3238
3239 operand immP0() %{
3240 predicate(n->get_ptr() == 0);
3241 match(ConP);
3242 op_cost(0);
3243
3244 format %{ %}
3245 interface(CONST_INTER);
3246 %}
3247
3248 operand immP_poll() %{
3249 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3250 match(ConP);
3251
3252 // formats are generated automatically for constants and base registers
3253 format %{ %}
3254 interface(CONST_INTER);
3255 %}
3256
3257 // Pointer Immediate
3258 operand immN()
3259 %{
3260 match(ConN);
3261
3262 op_cost(10);
3263 format %{ %}
3264 interface(CONST_INTER);
3265 %}
3266
3267 operand immNKlass()
3268 %{
3269 match(ConNKlass);
3270
3271 op_cost(10);
3272 format %{ %}
3273 interface(CONST_INTER);
3274 %}
3275
3276 // NULL Pointer Immediate
3277 operand immN0()
3278 %{
3279 predicate(n->get_narrowcon() == 0);
3280 match(ConN);
3281
3282 op_cost(0);
3283 format %{ %}
3284 interface(CONST_INTER);
3285 %}
3286
3287 operand immL() %{
3288 match(ConL);
3289 op_cost(40);
3290 // formats are generated automatically for constants and base registers
3291 format %{ %}
3292 interface(CONST_INTER);
3293 %}
3294
3295 operand immL0() %{
3296 predicate(n->get_long() == 0L);
3297 match(ConL);
3298 op_cost(0);
3299 // formats are generated automatically for constants and base registers
3300 format %{ %}
3301 interface(CONST_INTER);
3302 %}
3303
3304 // Integer Immediate: 5-bit
3305 operand immL5() %{
3306 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3307 match(ConL);
3308 op_cost(0);
3309 format %{ %}
3310 interface(CONST_INTER);
3311 %}
3312
3313 // Long Immediate: 13-bit
3314 operand immL13() %{
3315 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3316 match(ConL);
3317 op_cost(0);
3318
3319 format %{ %}
3320 interface(CONST_INTER);
3321 %}
3322
3323 // Long Immediate: 13-bit minus 7
3324 operand immL13m7() %{
3325 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3326 match(ConL);
3327 op_cost(0);
3328
3329 format %{ %}
3330 interface(CONST_INTER);
3331 %}
3332
3333 // Long Immediate: low 32-bit mask
3334 operand immL_32bits() %{
3335 predicate(n->get_long() == 0xFFFFFFFFL);
3336 match(ConL);
3337 op_cost(0);
3338
3339 format %{ %}
3340 interface(CONST_INTER);
3341 %}
3342
3343 // Long Immediate: cheap (materialize in <= 3 instructions)
3344 operand immL_cheap() %{
3345 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3346 match(ConL);
3347 op_cost(0);
3348
3349 format %{ %}
3350 interface(CONST_INTER);
3351 %}
3352
3353 // Long Immediate: expensive (materialize in > 3 instructions)
3354 operand immL_expensive() %{
3355 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3356 match(ConL);
3357 op_cost(0);
3358
3359 format %{ %}
3360 interface(CONST_INTER);
3361 %}
3362
3363 // Double Immediate
3364 operand immD() %{
3365 match(ConD);
3366
3367 op_cost(40);
3368 format %{ %}
3369 interface(CONST_INTER);
3370 %}
3371
3372 // Double Immediate: +0.0d
3373 operand immD0() %{
3374 predicate(jlong_cast(n->getd()) == 0);
3375 match(ConD);
3376
3377 op_cost(0);
3378 format %{ %}
3379 interface(CONST_INTER);
3380 %}
3381
3382 // Float Immediate
3383 operand immF() %{
3384 match(ConF);
3385
3386 op_cost(20);
3387 format %{ %}
3388 interface(CONST_INTER);
3389 %}
3390
3391 // Float Immediate: +0.0f
3392 operand immF0() %{
3393 predicate(jint_cast(n->getf()) == 0);
3394 match(ConF);
3395
3396 op_cost(0);
3397 format %{ %}
3398 interface(CONST_INTER);
3399 %}
3400
3401 // Integer Register Operands
3402 // Integer Register
3403 operand iRegI() %{
3404 constraint(ALLOC_IN_RC(int_reg));
3405 match(RegI);
3406
3407 match(notemp_iRegI);
3408 match(g1RegI);
3409 match(o0RegI);
3410 match(iRegIsafe);
3411
3412 format %{ %}
3413 interface(REG_INTER);
3414 %}
3415
3416 operand notemp_iRegI() %{
3417 constraint(ALLOC_IN_RC(notemp_int_reg));
3418 match(RegI);
3419
3420 match(o0RegI);
3421
3422 format %{ %}
3423 interface(REG_INTER);
3424 %}
3425
3426 operand o0RegI() %{
3427 constraint(ALLOC_IN_RC(o0_regI));
3428 match(iRegI);
3429
3430 format %{ %}
3431 interface(REG_INTER);
3432 %}
3433
3434 // Pointer Register
3435 operand iRegP() %{
3436 constraint(ALLOC_IN_RC(ptr_reg));
3437 match(RegP);
3438
3439 match(lock_ptr_RegP);
3440 match(g1RegP);
3441 match(g2RegP);
3442 match(g3RegP);
3443 match(g4RegP);
3444 match(i0RegP);
3445 match(o0RegP);
3446 match(o1RegP);
3447 match(l7RegP);
3448
3449 format %{ %}
3450 interface(REG_INTER);
3451 %}
3452
3453 operand sp_ptr_RegP() %{
3454 constraint(ALLOC_IN_RC(sp_ptr_reg));
3455 match(RegP);
3456 match(iRegP);
3457
3458 format %{ %}
3459 interface(REG_INTER);
3460 %}
3461
3462 operand lock_ptr_RegP() %{
3463 constraint(ALLOC_IN_RC(lock_ptr_reg));
3464 match(RegP);
3465 match(i0RegP);
3466 match(o0RegP);
3467 match(o1RegP);
3468 match(l7RegP);
3469
3470 format %{ %}
3471 interface(REG_INTER);
3472 %}
3473
3474 operand g1RegP() %{
3475 constraint(ALLOC_IN_RC(g1_regP));
3476 match(iRegP);
3477
3478 format %{ %}
3479 interface(REG_INTER);
3480 %}
3481
3482 operand g2RegP() %{
3483 constraint(ALLOC_IN_RC(g2_regP));
3484 match(iRegP);
3485
3486 format %{ %}
3487 interface(REG_INTER);
3488 %}
3489
3490 operand g3RegP() %{
3491 constraint(ALLOC_IN_RC(g3_regP));
3492 match(iRegP);
3493
3494 format %{ %}
3495 interface(REG_INTER);
3496 %}
3497
3498 operand g1RegI() %{
3499 constraint(ALLOC_IN_RC(g1_regI));
3500 match(iRegI);
3501
3502 format %{ %}
3503 interface(REG_INTER);
3504 %}
3505
3506 operand g3RegI() %{
3507 constraint(ALLOC_IN_RC(g3_regI));
3508 match(iRegI);
3509
3510 format %{ %}
3511 interface(REG_INTER);
3512 %}
3513
3514 operand g4RegI() %{
3515 constraint(ALLOC_IN_RC(g4_regI));
3516 match(iRegI);
3517
3518 format %{ %}
3519 interface(REG_INTER);
3520 %}
3521
3522 operand g4RegP() %{
3523 constraint(ALLOC_IN_RC(g4_regP));
3524 match(iRegP);
3525
3526 format %{ %}
3527 interface(REG_INTER);
3528 %}
3529
3530 operand i0RegP() %{
3531 constraint(ALLOC_IN_RC(i0_regP));
3532 match(iRegP);
3533
3534 format %{ %}
3535 interface(REG_INTER);
3536 %}
3537
3538 operand o0RegP() %{
3539 constraint(ALLOC_IN_RC(o0_regP));
3540 match(iRegP);
3541
3542 format %{ %}
3543 interface(REG_INTER);
3544 %}
3545
3546 operand o1RegP() %{
3547 constraint(ALLOC_IN_RC(o1_regP));
3548 match(iRegP);
3549
3550 format %{ %}
3551 interface(REG_INTER);
3552 %}
3553
3554 operand o2RegP() %{
3555 constraint(ALLOC_IN_RC(o2_regP));
3556 match(iRegP);
3557
3558 format %{ %}
3559 interface(REG_INTER);
3560 %}
3561
3562 operand o7RegP() %{
3563 constraint(ALLOC_IN_RC(o7_regP));
3564 match(iRegP);
3565
3566 format %{ %}
3567 interface(REG_INTER);
3568 %}
3569
3570 operand l7RegP() %{
3571 constraint(ALLOC_IN_RC(l7_regP));
3572 match(iRegP);
3573
3574 format %{ %}
3575 interface(REG_INTER);
3576 %}
3577
3578 operand o7RegI() %{
3579 constraint(ALLOC_IN_RC(o7_regI));
3580 match(iRegI);
3581
3582 format %{ %}
3583 interface(REG_INTER);
3584 %}
3585
3586 operand iRegN() %{
3587 constraint(ALLOC_IN_RC(int_reg));
3588 match(RegN);
3589
3590 format %{ %}
3591 interface(REG_INTER);
3592 %}
3593
3594 // Long Register
3595 operand iRegL() %{
3596 constraint(ALLOC_IN_RC(long_reg));
3597 match(RegL);
3598
3599 format %{ %}
3600 interface(REG_INTER);
3601 %}
3602
3603 operand o2RegL() %{
3604 constraint(ALLOC_IN_RC(o2_regL));
3605 match(iRegL);
3606
3607 format %{ %}
3608 interface(REG_INTER);
3609 %}
3610
3611 operand o7RegL() %{
3612 constraint(ALLOC_IN_RC(o7_regL));
3613 match(iRegL);
3614
3615 format %{ %}
3616 interface(REG_INTER);
3617 %}
3618
3619 operand g1RegL() %{
3620 constraint(ALLOC_IN_RC(g1_regL));
3621 match(iRegL);
3622
3623 format %{ %}
3624 interface(REG_INTER);
3625 %}
3626
3627 operand g3RegL() %{
3628 constraint(ALLOC_IN_RC(g3_regL));
3629 match(iRegL);
3630
3631 format %{ %}
3632 interface(REG_INTER);
3633 %}
3634
3635 // Int Register safe
3636 // This is 64bit safe
3637 operand iRegIsafe() %{
3638 constraint(ALLOC_IN_RC(long_reg));
3639
3640 match(iRegI);
3641
3642 format %{ %}
3643 interface(REG_INTER);
3644 %}
3645
3646 // Condition Code Flag Register
3647 operand flagsReg() %{
3648 constraint(ALLOC_IN_RC(int_flags));
3649 match(RegFlags);
3650
3651 format %{ "ccr" %} // both ICC and XCC
3652 interface(REG_INTER);
3653 %}
3654
3655 // Condition Code Register, unsigned comparisons.
3656 operand flagsRegU() %{
3657 constraint(ALLOC_IN_RC(int_flags));
3658 match(RegFlags);
3659
3660 format %{ "icc_U" %}
3661 interface(REG_INTER);
3662 %}
3663
3664 // Condition Code Register, pointer comparisons.
3665 operand flagsRegP() %{
3666 constraint(ALLOC_IN_RC(int_flags));
3667 match(RegFlags);
3668
3669 format %{ "xcc_P" %}
3670 interface(REG_INTER);
3671 %}
3672
3673 // Condition Code Register, long comparisons.
3674 operand flagsRegL() %{
3675 constraint(ALLOC_IN_RC(int_flags));
3676 match(RegFlags);
3677
3678 format %{ "xcc_L" %}
3679 interface(REG_INTER);
3680 %}
3681
3682 // Condition Code Register, floating comparisons, unordered same as "less".
3683 operand flagsRegF() %{
3684 constraint(ALLOC_IN_RC(float_flags));
3685 match(RegFlags);
3686 match(flagsRegF0);
3687
3688 format %{ %}
3689 interface(REG_INTER);
3690 %}
3691
3692 operand flagsRegF0() %{
3693 constraint(ALLOC_IN_RC(float_flag0));
3694 match(RegFlags);
3695
3696 format %{ %}
3697 interface(REG_INTER);
3698 %}
3699
3700
3701 // Condition Code Flag Register used by long compare
3702 operand flagsReg_long_LTGE() %{
3703 constraint(ALLOC_IN_RC(int_flags));
3704 match(RegFlags);
3705 format %{ "icc_LTGE" %}
3706 interface(REG_INTER);
3707 %}
3708 operand flagsReg_long_EQNE() %{
3709 constraint(ALLOC_IN_RC(int_flags));
3710 match(RegFlags);
3711 format %{ "icc_EQNE" %}
3712 interface(REG_INTER);
3713 %}
3714 operand flagsReg_long_LEGT() %{
3715 constraint(ALLOC_IN_RC(int_flags));
3716 match(RegFlags);
3717 format %{ "icc_LEGT" %}
3718 interface(REG_INTER);
3719 %}
3720
3721
3722 operand regD() %{
3723 constraint(ALLOC_IN_RC(dflt_reg));
3724 match(RegD);
3725
3726 match(regD_low);
3727
3728 format %{ %}
3729 interface(REG_INTER);
3730 %}
3731
3732 operand regF() %{
3733 constraint(ALLOC_IN_RC(sflt_reg));
3734 match(RegF);
3735
3736 format %{ %}
3737 interface(REG_INTER);
3738 %}
3739
3740 operand regD_low() %{
3741 constraint(ALLOC_IN_RC(dflt_low_reg));
3742 match(regD);
3743
3744 format %{ %}
3745 interface(REG_INTER);
3746 %}
3747
3748 // Special Registers
3749
3750 // Method Register
3751 operand inline_cache_regP(iRegP reg) %{
3752 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
3753 match(reg);
3754 format %{ %}
3755 interface(REG_INTER);
3756 %}
3757
3758 operand interpreter_method_oop_regP(iRegP reg) %{
3759 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
3760 match(reg);
3761 format %{ %}
3762 interface(REG_INTER);
3763 %}
3764
3765
3766 //----------Complex Operands---------------------------------------------------
3767 // Indirect Memory Reference
3768 operand indirect(sp_ptr_RegP reg) %{
3769 constraint(ALLOC_IN_RC(sp_ptr_reg));
3770 match(reg);
3771
3772 op_cost(100);
3773 format %{ "[$reg]" %}
3774 interface(MEMORY_INTER) %{
3775 base($reg);
3776 index(0x0);
3777 scale(0x0);
3778 disp(0x0);
3779 %}
3780 %}
3781
3782 // Indirect with simm13 Offset
3783 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
3784 constraint(ALLOC_IN_RC(sp_ptr_reg));
3785 match(AddP reg offset);
3786
3787 op_cost(100);
3788 format %{ "[$reg + $offset]" %}
3789 interface(MEMORY_INTER) %{
3790 base($reg);
3791 index(0x0);
3792 scale(0x0);
3793 disp($offset);
3794 %}
3795 %}
3796
3797 // Indirect with simm13 Offset minus 7
3798 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
3799 constraint(ALLOC_IN_RC(sp_ptr_reg));
3800 match(AddP reg offset);
3801
3802 op_cost(100);
3803 format %{ "[$reg + $offset]" %}
3804 interface(MEMORY_INTER) %{
3805 base($reg);
3806 index(0x0);
3807 scale(0x0);
3808 disp($offset);
3809 %}
3810 %}
3811
3812 // Note: Intel has a swapped version also, like this:
3813 //operand indOffsetX(iRegI reg, immP offset) %{
3814 // constraint(ALLOC_IN_RC(int_reg));
3815 // match(AddP offset reg);
3816 //
3817 // op_cost(100);
3818 // format %{ "[$reg + $offset]" %}
3819 // interface(MEMORY_INTER) %{
3820 // base($reg);
3821 // index(0x0);
3822 // scale(0x0);
3823 // disp($offset);
3824 // %}
3825 //%}
3826 //// However, it doesn't make sense for SPARC, since
3827 // we have no particularly good way to embed oops in
3828 // single instructions.
3829
3830 // Indirect with Register Index
3831 operand indIndex(iRegP addr, iRegX index) %{
3832 constraint(ALLOC_IN_RC(ptr_reg));
3833 match(AddP addr index);
3834
3835 op_cost(100);
3836 format %{ "[$addr + $index]" %}
3837 interface(MEMORY_INTER) %{
3838 base($addr);
3839 index($index);
3840 scale(0x0);
3841 disp(0x0);
3842 %}
3843 %}
3844
3845 //----------Special Memory Operands--------------------------------------------
3846 // Stack Slot Operand - This operand is used for loading and storing temporary
3847 // values on the stack where a match requires a value to
3848 // flow through memory.
3849 operand stackSlotI(sRegI reg) %{
3850 constraint(ALLOC_IN_RC(stack_slots));
3851 op_cost(100);
3852 //match(RegI);
3853 format %{ "[$reg]" %}
3854 interface(MEMORY_INTER) %{
3855 base(0xE); // R_SP
3856 index(0x0);
3857 scale(0x0);
3858 disp($reg); // Stack Offset
3859 %}
3860 %}
3861
3862 operand stackSlotP(sRegP reg) %{
3863 constraint(ALLOC_IN_RC(stack_slots));
3864 op_cost(100);
3865 //match(RegP);
3866 format %{ "[$reg]" %}
3867 interface(MEMORY_INTER) %{
3868 base(0xE); // R_SP
3869 index(0x0);
3870 scale(0x0);
3871 disp($reg); // Stack Offset
3872 %}
3873 %}
3874
3875 operand stackSlotF(sRegF reg) %{
3876 constraint(ALLOC_IN_RC(stack_slots));
3877 op_cost(100);
3878 //match(RegF);
3879 format %{ "[$reg]" %}
3880 interface(MEMORY_INTER) %{
3881 base(0xE); // R_SP
3882 index(0x0);
3883 scale(0x0);
3884 disp($reg); // Stack Offset
3885 %}
3886 %}
3887 operand stackSlotD(sRegD reg) %{
3888 constraint(ALLOC_IN_RC(stack_slots));
3889 op_cost(100);
3890 //match(RegD);
3891 format %{ "[$reg]" %}
3892 interface(MEMORY_INTER) %{
3893 base(0xE); // R_SP
3894 index(0x0);
3895 scale(0x0);
3896 disp($reg); // Stack Offset
3897 %}
3898 %}
3899 operand stackSlotL(sRegL reg) %{
3900 constraint(ALLOC_IN_RC(stack_slots));
3901 op_cost(100);
3902 //match(RegL);
3903 format %{ "[$reg]" %}
3904 interface(MEMORY_INTER) %{
3905 base(0xE); // R_SP
3906 index(0x0);
3907 scale(0x0);
3908 disp($reg); // Stack Offset
3909 %}
3910 %}
3911
3912 // Operands for expressing Control Flow
3913 // NOTE: Label is a predefined operand which should not be redefined in
3914 // the AD file. It is generically handled within the ADLC.
3915
3916 //----------Conditional Branch Operands----------------------------------------
3917 // Comparison Op - This is the operation of the comparison, and is limited to
3918 // the following set of codes:
3919 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3920 //
3921 // Other attributes of the comparison, such as unsignedness, are specified
3922 // by the comparison instruction that sets a condition code flags register.
3923 // That result is represented by a flags operand whose subtype is appropriate
3924 // to the unsignedness (etc.) of the comparison.
3925 //
3926 // Later, the instruction which matches both the Comparison Op (a Bool) and
3927 // the flags (produced by the Cmp) specifies the coding of the comparison op
3928 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3929
3930 operand cmpOp() %{
3931 match(Bool);
3932
3933 format %{ "" %}
3934 interface(COND_INTER) %{
3935 equal(0x1);
3936 not_equal(0x9);
3937 less(0x3);
3938 greater_equal(0xB);
3939 less_equal(0x2);
3940 greater(0xA);
3941 overflow(0x7);
3942 no_overflow(0xF);
3943 %}
3944 %}
3945
3946 // Comparison Op, unsigned
3947 operand cmpOpU() %{
3948 match(Bool);
3949 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
3950 n->as_Bool()->_test._test != BoolTest::no_overflow);
3951
3952 format %{ "u" %}
3953 interface(COND_INTER) %{
3954 equal(0x1);
3955 not_equal(0x9);
3956 less(0x5);
3957 greater_equal(0xD);
3958 less_equal(0x4);
3959 greater(0xC);
3960 overflow(0x7);
3961 no_overflow(0xF);
3962 %}
3963 %}
3964
3965 // Comparison Op, pointer (same as unsigned)
3966 operand cmpOpP() %{
3967 match(Bool);
3968 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
3969 n->as_Bool()->_test._test != BoolTest::no_overflow);
3970
3971 format %{ "p" %}
3972 interface(COND_INTER) %{
3973 equal(0x1);
3974 not_equal(0x9);
3975 less(0x5);
3976 greater_equal(0xD);
3977 less_equal(0x4);
3978 greater(0xC);
3979 overflow(0x7);
3980 no_overflow(0xF);
3981 %}
3982 %}
3983
3984 // Comparison Op, branch-register encoding
3985 operand cmpOp_reg() %{
3986 match(Bool);
3987 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
3988 n->as_Bool()->_test._test != BoolTest::no_overflow);
3989
3990 format %{ "" %}
3991 interface(COND_INTER) %{
3992 equal (0x1);
3993 not_equal (0x5);
3994 less (0x3);
3995 greater_equal(0x7);
3996 less_equal (0x2);
3997 greater (0x6);
3998 overflow(0x7); // not supported
3999 no_overflow(0xF); // not supported
4000 %}
4001 %}
4002
4003 // Comparison Code, floating, unordered same as less
4004 operand cmpOpF() %{
4005 match(Bool);
4006 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4007 n->as_Bool()->_test._test != BoolTest::no_overflow);
4008
4009 format %{ "fl" %}
4010 interface(COND_INTER) %{
4011 equal(0x9);
4012 not_equal(0x1);
4013 less(0x3);
4014 greater_equal(0xB);
4015 less_equal(0xE);
4016 greater(0x6);
4017
4018 overflow(0x7); // not supported
4019 no_overflow(0xF); // not supported
4020 %}
4021 %}
4022
4023 // Used by long compare
4024 operand cmpOp_commute() %{
4025 match(Bool);
4026 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4027 n->as_Bool()->_test._test != BoolTest::no_overflow);
4028
4029 format %{ "" %}
4030 interface(COND_INTER) %{
4031 equal(0x1);
4032 not_equal(0x9);
4033 less(0xA);
4034 greater_equal(0x2);
4035 less_equal(0xB);
4036 greater(0x3);
4037 overflow(0x7);
4038 no_overflow(0xF);
4039 %}
4040 %}
4041
4042 //----------OPERAND CLASSES----------------------------------------------------
4043 // Operand Classes are groups of operands that are used to simplify
4044 // instruction definitions by not requiring the AD writer to specify separate
4045 // instructions for every form of operand when the instruction accepts
4046 // multiple operand types with the same basic encoding and format. The classic
4047 // case of this is memory operands.
4048 opclass memory( indirect, indOffset13, indIndex );
4049 opclass indIndexMemory( indIndex );
4050
4051 //----------PIPELINE-----------------------------------------------------------
4052 pipeline %{
4053
4054 //----------ATTRIBUTES---------------------------------------------------------
4055 attributes %{
4056 fixed_size_instructions; // Fixed size instructions
4057 branch_has_delay_slot; // Branch has delay slot following
4058 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4059 instruction_unit_size = 4; // An instruction is 4 bytes long
4060 instruction_fetch_unit_size = 16; // The processor fetches one line
4061 instruction_fetch_units = 1; // of 16 bytes
4062
4063 // List of nop instructions
4064 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4065 %}
4066
4067 //----------RESOURCES----------------------------------------------------------
4068 // Resources are the functional units available to the machine
4069 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4070
4071 //----------PIPELINE DESCRIPTION-----------------------------------------------
4072 // Pipeline Description specifies the stages in the machine's pipeline
4073
4074 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4075
4076 //----------PIPELINE CLASSES---------------------------------------------------
4077 // Pipeline Classes describe the stages in which input and output are
4078 // referenced by the hardware pipeline.
4079
4080 // Integer ALU reg-reg operation
4081 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4082 single_instruction;
4083 dst : E(write);
4084 src1 : R(read);
4085 src2 : R(read);
4086 IALU : R;
4087 %}
4088
4089 // Integer ALU reg-reg long operation
4090 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4091 instruction_count(2);
4092 dst : E(write);
4093 src1 : R(read);
4094 src2 : R(read);
4095 IALU : R;
4096 IALU : R;
4097 %}
4098
4099 // Integer ALU reg-reg long dependent operation
4100 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4101 instruction_count(1); multiple_bundles;
4102 dst : E(write);
4103 src1 : R(read);
4104 src2 : R(read);
4105 cr : E(write);
4106 IALU : R(2);
4107 %}
4108
4109 // Integer ALU reg-imm operaion
4110 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4111 single_instruction;
4112 dst : E(write);
4113 src1 : R(read);
4114 IALU : R;
4115 %}
4116
4117 // Integer ALU reg-reg operation with condition code
4118 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4119 single_instruction;
4120 dst : E(write);
4121 cr : E(write);
4122 src1 : R(read);
4123 src2 : R(read);
4124 IALU : R;
4125 %}
4126
4127 // Integer ALU reg-imm operation with condition code
4128 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4129 single_instruction;
4130 dst : E(write);
4131 cr : E(write);
4132 src1 : R(read);
4133 IALU : R;
4134 %}
4135
4136 // Integer ALU zero-reg operation
4137 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4138 single_instruction;
4139 dst : E(write);
4140 src2 : R(read);
4141 IALU : R;
4142 %}
4143
4144 // Integer ALU zero-reg operation with condition code only
4145 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4146 single_instruction;
4147 cr : E(write);
4148 src : R(read);
4149 IALU : R;
4150 %}
4151
4152 // Integer ALU reg-reg operation with condition code only
4153 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4154 single_instruction;
4155 cr : E(write);
4156 src1 : R(read);
4157 src2 : R(read);
4158 IALU : R;
4159 %}
4160
4161 // Integer ALU reg-imm operation with condition code only
4162 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4163 single_instruction;
4164 cr : E(write);
4165 src1 : R(read);
4166 IALU : R;
4167 %}
4168
4169 // Integer ALU reg-reg-zero operation with condition code only
4170 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4171 single_instruction;
4172 cr : E(write);
4173 src1 : R(read);
4174 src2 : R(read);
4175 IALU : R;
4176 %}
4177
4178 // Integer ALU reg-imm-zero operation with condition code only
4179 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4180 single_instruction;
4181 cr : E(write);
4182 src1 : R(read);
4183 IALU : R;
4184 %}
4185
4186 // Integer ALU reg-reg operation with condition code, src1 modified
4187 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4188 single_instruction;
4189 cr : E(write);
4190 src1 : E(write);
4191 src1 : R(read);
4192 src2 : R(read);
4193 IALU : R;
4194 %}
4195
4196 // Integer ALU reg-imm operation with condition code, src1 modified
4197 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4198 single_instruction;
4199 cr : E(write);
4200 src1 : E(write);
4201 src1 : R(read);
4202 IALU : R;
4203 %}
4204
4205 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4206 multiple_bundles;
4207 dst : E(write)+4;
4208 cr : E(write);
4209 src1 : R(read);
4210 src2 : R(read);
4211 IALU : R(3);
4212 BR : R(2);
4213 %}
4214
4215 // Integer ALU operation
4216 pipe_class ialu_none(iRegI dst) %{
4217 single_instruction;
4218 dst : E(write);
4219 IALU : R;
4220 %}
4221
4222 // Integer ALU reg operation
4223 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4224 single_instruction; may_have_no_code;
4225 dst : E(write);
4226 src : R(read);
4227 IALU : R;
4228 %}
4229
4230 // Integer ALU reg conditional operation
4231 // This instruction has a 1 cycle stall, and cannot execute
4232 // in the same cycle as the instruction setting the condition
4233 // code. We kludge this by pretending to read the condition code
4234 // 1 cycle earlier, and by marking the functional units as busy
4235 // for 2 cycles with the result available 1 cycle later than
4236 // is really the case.
4237 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4238 single_instruction;
4239 op2_out : C(write);
4240 op1 : R(read);
4241 cr : R(read); // This is really E, with a 1 cycle stall
4242 BR : R(2);
4243 MS : R(2);
4244 %}
4245
4246 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4247 instruction_count(1); multiple_bundles;
4248 dst : C(write)+1;
4249 src : R(read)+1;
4250 IALU : R(1);
4251 BR : E(2);
4252 MS : E(2);
4253 %}
4254
4255 // Integer ALU reg operation
4256 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4257 single_instruction; may_have_no_code;
4258 dst : E(write);
4259 src : R(read);
4260 IALU : R;
4261 %}
4262 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4263 single_instruction; may_have_no_code;
4264 dst : E(write);
4265 src : R(read);
4266 IALU : R;
4267 %}
4268
4269 // Two integer ALU reg operations
4270 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4271 instruction_count(2);
4272 dst : E(write);
4273 src : R(read);
4274 A0 : R;
4275 A1 : R;
4276 %}
4277
4278 // Two integer ALU reg operations
4279 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4280 instruction_count(2); may_have_no_code;
4281 dst : E(write);
4282 src : R(read);
4283 A0 : R;
4284 A1 : R;
4285 %}
4286
4287 // Integer ALU imm operation
4288 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4289 single_instruction;
4290 dst : E(write);
4291 IALU : R;
4292 %}
4293
4294 // Integer ALU reg-reg with carry operation
4295 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4296 single_instruction;
4297 dst : E(write);
4298 src1 : R(read);
4299 src2 : R(read);
4300 IALU : R;
4301 %}
4302
4303 // Integer ALU cc operation
4304 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4305 single_instruction;
4306 dst : E(write);
4307 cc : R(read);
4308 IALU : R;
4309 %}
4310
4311 // Integer ALU cc / second IALU operation
4312 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4313 instruction_count(1); multiple_bundles;
4314 dst : E(write)+1;
4315 src : R(read);
4316 IALU : R;
4317 %}
4318
4319 // Integer ALU cc / second IALU operation
4320 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4321 instruction_count(1); multiple_bundles;
4322 dst : E(write)+1;
4323 p : R(read);
4324 q : R(read);
4325 IALU : R;
4326 %}
4327
4328 // Integer ALU hi-lo-reg operation
4329 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4330 instruction_count(1); multiple_bundles;
4331 dst : E(write)+1;
4332 IALU : R(2);
4333 %}
4334
4335 // Float ALU hi-lo-reg operation (with temp)
4336 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4337 instruction_count(1); multiple_bundles;
4338 dst : E(write)+1;
4339 IALU : R(2);
4340 %}
4341
4342 // Long Constant
4343 pipe_class loadConL( iRegL dst, immL src ) %{
4344 instruction_count(2); multiple_bundles;
4345 dst : E(write)+1;
4346 IALU : R(2);
4347 IALU : R(2);
4348 %}
4349
4350 // Pointer Constant
4351 pipe_class loadConP( iRegP dst, immP src ) %{
4352 instruction_count(0); multiple_bundles;
4353 fixed_latency(6);
4354 %}
4355
4356 // Polling Address
4357 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4358 instruction_count(0); multiple_bundles;
4359 fixed_latency(6);
4360 %}
4361
4362 // Long Constant small
4363 pipe_class loadConLlo( iRegL dst, immL src ) %{
4364 instruction_count(2);
4365 dst : E(write);
4366 IALU : R;
4367 IALU : R;
4368 %}
4369
4370 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4371 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4372 instruction_count(1); multiple_bundles;
4373 src : R(read);
4374 dst : M(write)+1;
4375 IALU : R;
4376 MS : E;
4377 %}
4378
4379 // Integer ALU nop operation
4380 pipe_class ialu_nop() %{
4381 single_instruction;
4382 IALU : R;
4383 %}
4384
4385 // Integer ALU nop operation
4386 pipe_class ialu_nop_A0() %{
4387 single_instruction;
4388 A0 : R;
4389 %}
4390
4391 // Integer ALU nop operation
4392 pipe_class ialu_nop_A1() %{
4393 single_instruction;
4394 A1 : R;
4395 %}
4396
4397 // Integer Multiply reg-reg operation
4398 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4399 single_instruction;
4400 dst : E(write);
4401 src1 : R(read);
4402 src2 : R(read);
4403 MS : R(5);
4404 %}
4405
4406 // Integer Multiply reg-imm operation
4407 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4408 single_instruction;
4409 dst : E(write);
4410 src1 : R(read);
4411 MS : R(5);
4412 %}
4413
4414 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4415 single_instruction;
4416 dst : E(write)+4;
4417 src1 : R(read);
4418 src2 : R(read);
4419 MS : R(6);
4420 %}
4421
4422 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4423 single_instruction;
4424 dst : E(write)+4;
4425 src1 : R(read);
4426 MS : R(6);
4427 %}
4428
4429 // Integer Divide reg-reg
4430 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4431 instruction_count(1); multiple_bundles;
4432 dst : E(write);
4433 temp : E(write);
4434 src1 : R(read);
4435 src2 : R(read);
4436 temp : R(read);
4437 MS : R(38);
4438 %}
4439
4440 // Integer Divide reg-imm
4441 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4442 instruction_count(1); multiple_bundles;
4443 dst : E(write);
4444 temp : E(write);
4445 src1 : R(read);
4446 temp : R(read);
4447 MS : R(38);
4448 %}
4449
4450 // Long Divide
4451 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4452 dst : E(write)+71;
4453 src1 : R(read);
4454 src2 : R(read)+1;
4455 MS : R(70);
4456 %}
4457
4458 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4459 dst : E(write)+71;
4460 src1 : R(read);
4461 MS : R(70);
4462 %}
4463
4464 // Floating Point Add Float
4465 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4466 single_instruction;
4467 dst : X(write);
4468 src1 : E(read);
4469 src2 : E(read);
4470 FA : R;
4471 %}
4472
4473 // Floating Point Add Double
4474 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4475 single_instruction;
4476 dst : X(write);
4477 src1 : E(read);
4478 src2 : E(read);
4479 FA : R;
4480 %}
4481
4482 // Floating Point Conditional Move based on integer flags
4483 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4484 single_instruction;
4485 dst : X(write);
4486 src : E(read);
4487 cr : R(read);
4488 FA : R(2);
4489 BR : R(2);
4490 %}
4491
4492 // Floating Point Conditional Move based on integer flags
4493 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4494 single_instruction;
4495 dst : X(write);
4496 src : E(read);
4497 cr : R(read);
4498 FA : R(2);
4499 BR : R(2);
4500 %}
4501
4502 // Floating Point Multiply Float
4503 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4504 single_instruction;
4505 dst : X(write);
4506 src1 : E(read);
4507 src2 : E(read);
4508 FM : R;
4509 %}
4510
4511 // Floating Point Multiply Double
4512 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4513 single_instruction;
4514 dst : X(write);
4515 src1 : E(read);
4516 src2 : E(read);
4517 FM : R;
4518 %}
4519
4520 // Floating Point Divide Float
4521 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4522 single_instruction;
4523 dst : X(write);
4524 src1 : E(read);
4525 src2 : E(read);
4526 FM : R;
4527 FDIV : C(14);
4528 %}
4529
4530 // Floating Point Divide Double
4531 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4532 single_instruction;
4533 dst : X(write);
4534 src1 : E(read);
4535 src2 : E(read);
4536 FM : R;
4537 FDIV : C(17);
4538 %}
4539
4540 // Floating Point Move/Negate/Abs Float
4541 pipe_class faddF_reg(regF dst, regF src) %{
4542 single_instruction;
4543 dst : W(write);
4544 src : E(read);
4545 FA : R(1);
4546 %}
4547
4548 // Floating Point Move/Negate/Abs Double
4549 pipe_class faddD_reg(regD dst, regD src) %{
4550 single_instruction;
4551 dst : W(write);
4552 src : E(read);
4553 FA : R;
4554 %}
4555
4556 // Floating Point Convert F->D
4557 pipe_class fcvtF2D(regD dst, regF src) %{
4558 single_instruction;
4559 dst : X(write);
4560 src : E(read);
4561 FA : R;
4562 %}
4563
4564 // Floating Point Convert I->D
4565 pipe_class fcvtI2D(regD dst, regF src) %{
4566 single_instruction;
4567 dst : X(write);
4568 src : E(read);
4569 FA : R;
4570 %}
4571
4572 // Floating Point Convert LHi->D
4573 pipe_class fcvtLHi2D(regD dst, regD src) %{
4574 single_instruction;
4575 dst : X(write);
4576 src : E(read);
4577 FA : R;
4578 %}
4579
4580 // Floating Point Convert L->D
4581 pipe_class fcvtL2D(regD dst, regF src) %{
4582 single_instruction;
4583 dst : X(write);
4584 src : E(read);
4585 FA : R;
4586 %}
4587
4588 // Floating Point Convert L->F
4589 pipe_class fcvtL2F(regD dst, regF src) %{
4590 single_instruction;
4591 dst : X(write);
4592 src : E(read);
4593 FA : R;
4594 %}
4595
4596 // Floating Point Convert D->F
4597 pipe_class fcvtD2F(regD dst, regF src) %{
4598 single_instruction;
4599 dst : X(write);
4600 src : E(read);
4601 FA : R;
4602 %}
4603
4604 // Floating Point Convert I->L
4605 pipe_class fcvtI2L(regD dst, regF src) %{
4606 single_instruction;
4607 dst : X(write);
4608 src : E(read);
4609 FA : R;
4610 %}
4611
4612 // Floating Point Convert D->F
4613 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4614 instruction_count(1); multiple_bundles;
4615 dst : X(write)+6;
4616 src : E(read);
4617 FA : R;
4618 %}
4619
4620 // Floating Point Convert D->L
4621 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4622 instruction_count(1); multiple_bundles;
4623 dst : X(write)+6;
4624 src : E(read);
4625 FA : R;
4626 %}
4627
4628 // Floating Point Convert F->I
4629 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4630 instruction_count(1); multiple_bundles;
4631 dst : X(write)+6;
4632 src : E(read);
4633 FA : R;
4634 %}
4635
4636 // Floating Point Convert F->L
4637 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4638 instruction_count(1); multiple_bundles;
4639 dst : X(write)+6;
4640 src : E(read);
4641 FA : R;
4642 %}
4643
4644 // Floating Point Convert I->F
4645 pipe_class fcvtI2F(regF dst, regF src) %{
4646 single_instruction;
4647 dst : X(write);
4648 src : E(read);
4649 FA : R;
4650 %}
4651
4652 // Floating Point Compare
4653 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4654 single_instruction;
4655 cr : X(write);
4656 src1 : E(read);
4657 src2 : E(read);
4658 FA : R;
4659 %}
4660
4661 // Floating Point Compare
4662 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4663 single_instruction;
4664 cr : X(write);
4665 src1 : E(read);
4666 src2 : E(read);
4667 FA : R;
4668 %}
4669
4670 // Floating Add Nop
4671 pipe_class fadd_nop() %{
4672 single_instruction;
4673 FA : R;
4674 %}
4675
4676 // Integer Store to Memory
4677 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4678 single_instruction;
4679 mem : R(read);
4680 src : C(read);
4681 MS : R;
4682 %}
4683
4684 // Integer Store to Memory
4685 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4686 single_instruction;
4687 mem : R(read);
4688 src : C(read);
4689 MS : R;
4690 %}
4691
4692 // Integer Store Zero to Memory
4693 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4694 single_instruction;
4695 mem : R(read);
4696 MS : R;
4697 %}
4698
4699 // Special Stack Slot Store
4700 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4701 single_instruction;
4702 stkSlot : R(read);
4703 src : C(read);
4704 MS : R;
4705 %}
4706
4707 // Special Stack Slot Store
4708 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4709 instruction_count(2); multiple_bundles;
4710 stkSlot : R(read);
4711 src : C(read);
4712 MS : R(2);
4713 %}
4714
4715 // Float Store
4716 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4717 single_instruction;
4718 mem : R(read);
4719 src : C(read);
4720 MS : R;
4721 %}
4722
4723 // Float Store
4724 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4725 single_instruction;
4726 mem : R(read);
4727 MS : R;
4728 %}
4729
4730 // Double Store
4731 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4732 instruction_count(1);
4733 mem : R(read);
4734 src : C(read);
4735 MS : R;
4736 %}
4737
4738 // Double Store
4739 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4740 single_instruction;
4741 mem : R(read);
4742 MS : R;
4743 %}
4744
4745 // Special Stack Slot Float Store
4746 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4747 single_instruction;
4748 stkSlot : R(read);
4749 src : C(read);
4750 MS : R;
4751 %}
4752
4753 // Special Stack Slot Double Store
4754 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4755 single_instruction;
4756 stkSlot : R(read);
4757 src : C(read);
4758 MS : R;
4759 %}
4760
4761 // Integer Load (when sign bit propagation not needed)
4762 pipe_class iload_mem(iRegI dst, memory mem) %{
4763 single_instruction;
4764 mem : R(read);
4765 dst : C(write);
4766 MS : R;
4767 %}
4768
4769 // Integer Load from stack operand
4770 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
4771 single_instruction;
4772 mem : R(read);
4773 dst : C(write);
4774 MS : R;
4775 %}
4776
4777 // Integer Load (when sign bit propagation or masking is needed)
4778 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
4779 single_instruction;
4780 mem : R(read);
4781 dst : M(write);
4782 MS : R;
4783 %}
4784
4785 // Float Load
4786 pipe_class floadF_mem(regF dst, memory mem) %{
4787 single_instruction;
4788 mem : R(read);
4789 dst : M(write);
4790 MS : R;
4791 %}
4792
4793 // Float Load
4794 pipe_class floadD_mem(regD dst, memory mem) %{
4795 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
4796 mem : R(read);
4797 dst : M(write);
4798 MS : R;
4799 %}
4800
4801 // Float Load
4802 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
4803 single_instruction;
4804 stkSlot : R(read);
4805 dst : M(write);
4806 MS : R;
4807 %}
4808
4809 // Float Load
4810 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
4811 single_instruction;
4812 stkSlot : R(read);
4813 dst : M(write);
4814 MS : R;
4815 %}
4816
4817 // Memory Nop
4818 pipe_class mem_nop() %{
4819 single_instruction;
4820 MS : R;
4821 %}
4822
4823 pipe_class sethi(iRegP dst, immI src) %{
4824 single_instruction;
4825 dst : E(write);
4826 IALU : R;
4827 %}
4828
4829 pipe_class loadPollP(iRegP poll) %{
4830 single_instruction;
4831 poll : R(read);
4832 MS : R;
4833 %}
4834
4835 pipe_class br(Universe br, label labl) %{
4836 single_instruction_with_delay_slot;
4837 BR : R;
4838 %}
4839
4840 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
4841 single_instruction_with_delay_slot;
4842 cr : E(read);
4843 BR : R;
4844 %}
4845
4846 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
4847 single_instruction_with_delay_slot;
4848 op1 : E(read);
4849 BR : R;
4850 MS : R;
4851 %}
4852
4853 // Compare and branch
4854 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
4855 instruction_count(2); has_delay_slot;
4856 cr : E(write);
4857 src1 : R(read);
4858 src2 : R(read);
4859 IALU : R;
4860 BR : R;
4861 %}
4862
4863 // Compare and branch
4864 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
4865 instruction_count(2); has_delay_slot;
4866 cr : E(write);
4867 src1 : R(read);
4868 IALU : R;
4869 BR : R;
4870 %}
4871
4872 // Compare and branch using cbcond
4873 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
4874 single_instruction;
4875 src1 : E(read);
4876 src2 : E(read);
4877 IALU : R;
4878 BR : R;
4879 %}
4880
4881 // Compare and branch using cbcond
4882 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
4883 single_instruction;
4884 src1 : E(read);
4885 IALU : R;
4886 BR : R;
4887 %}
4888
4889 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
4890 single_instruction_with_delay_slot;
4891 cr : E(read);
4892 BR : R;
4893 %}
4894
4895 pipe_class br_nop() %{
4896 single_instruction;
4897 BR : R;
4898 %}
4899
4900 pipe_class simple_call(method meth) %{
4901 instruction_count(2); multiple_bundles; force_serialization;
4902 fixed_latency(100);
4903 BR : R(1);
4904 MS : R(1);
4905 A0 : R(1);
4906 %}
4907
4908 pipe_class compiled_call(method meth) %{
4909 instruction_count(1); multiple_bundles; force_serialization;
4910 fixed_latency(100);
4911 MS : R(1);
4912 %}
4913
4914 pipe_class call(method meth) %{
4915 instruction_count(0); multiple_bundles; force_serialization;
4916 fixed_latency(100);
4917 %}
4918
4919 pipe_class tail_call(Universe ignore, label labl) %{
4920 single_instruction; has_delay_slot;
4921 fixed_latency(100);
4922 BR : R(1);
4923 MS : R(1);
4924 %}
4925
4926 pipe_class ret(Universe ignore) %{
4927 single_instruction; has_delay_slot;
4928 BR : R(1);
4929 MS : R(1);
4930 %}
4931
4932 pipe_class ret_poll(g3RegP poll) %{
4933 instruction_count(3); has_delay_slot;
4934 poll : E(read);
4935 MS : R;
4936 %}
4937
4938 // The real do-nothing guy
4939 pipe_class empty( ) %{
4940 instruction_count(0);
4941 %}
4942
4943 pipe_class long_memory_op() %{
4944 instruction_count(0); multiple_bundles; force_serialization;
4945 fixed_latency(25);
4946 MS : R(1);
4947 %}
4948
4949 // Check-cast
4950 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
4951 array : R(read);
4952 match : R(read);
4953 IALU : R(2);
4954 BR : R(2);
4955 MS : R;
4956 %}
4957
4958 // Convert FPU flags into +1,0,-1
4959 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
4960 src1 : E(read);
4961 src2 : E(read);
4962 dst : E(write);
4963 FA : R;
4964 MS : R(2);
4965 BR : R(2);
4966 %}
4967
4968 // Compare for p < q, and conditionally add y
4969 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
4970 p : E(read);
4971 q : E(read);
4972 y : E(read);
4973 IALU : R(3)
4974 %}
4975
4976 // Perform a compare, then move conditionally in a branch delay slot.
4977 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
4978 src2 : E(read);
4979 srcdst : E(read);
4980 IALU : R;
4981 BR : R;
4982 %}
4983
4984 // Define the class for the Nop node
4985 define %{
4986 MachNop = ialu_nop;
4987 %}
4988
4989 %}
4990
4991 //----------INSTRUCTIONS-------------------------------------------------------
4992
4993 //------------Special Stack Slot instructions - no match rules-----------------
4994 instruct stkI_to_regF(regF dst, stackSlotI src) %{
4995 // No match rule to avoid chain rule match.
4996 effect(DEF dst, USE src);
4997 ins_cost(MEMORY_REF_COST);
4998 format %{ "LDF $src,$dst\t! stkI to regF" %}
4999 opcode(Assembler::ldf_op3);
5000 ins_encode(simple_form3_mem_reg(src, dst));
5001 ins_pipe(floadF_stk);
5002 %}
5003
5004 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5005 // No match rule to avoid chain rule match.
5006 effect(DEF dst, USE src);
5007 ins_cost(MEMORY_REF_COST);
5008 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5009 opcode(Assembler::lddf_op3);
5010 ins_encode(simple_form3_mem_reg(src, dst));
5011 ins_pipe(floadD_stk);
5012 %}
5013
5014 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5015 // No match rule to avoid chain rule match.
5016 effect(DEF dst, USE src);
5017 ins_cost(MEMORY_REF_COST);
5018 format %{ "STF $src,$dst\t! regF to stkI" %}
5019 opcode(Assembler::stf_op3);
5020 ins_encode(simple_form3_mem_reg(dst, src));
5021 ins_pipe(fstoreF_stk_reg);
5022 %}
5023
5024 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5025 // No match rule to avoid chain rule match.
5026 effect(DEF dst, USE src);
5027 ins_cost(MEMORY_REF_COST);
5028 format %{ "STDF $src,$dst\t! regD to stkL" %}
5029 opcode(Assembler::stdf_op3);
5030 ins_encode(simple_form3_mem_reg(dst, src));
5031 ins_pipe(fstoreD_stk_reg);
5032 %}
5033
5034 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5035 effect(DEF dst, USE src);
5036 ins_cost(MEMORY_REF_COST*2);
5037 format %{ "STW $src,$dst.hi\t! long\n\t"
5038 "STW R_G0,$dst.lo" %}
5039 opcode(Assembler::stw_op3);
5040 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5041 ins_pipe(lstoreI_stk_reg);
5042 %}
5043
5044 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5045 // No match rule to avoid chain rule match.
5046 effect(DEF dst, USE src);
5047 ins_cost(MEMORY_REF_COST);
5048 format %{ "STX $src,$dst\t! regL to stkD" %}
5049 opcode(Assembler::stx_op3);
5050 ins_encode(simple_form3_mem_reg( dst, src ) );
5051 ins_pipe(istore_stk_reg);
5052 %}
5053
5054 //---------- Chain stack slots between similar types --------
5055
5056 // Load integer from stack slot
5057 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5058 match(Set dst src);
5059 ins_cost(MEMORY_REF_COST);
5060
5061 format %{ "LDUW $src,$dst\t!stk" %}
5062 opcode(Assembler::lduw_op3);
5063 ins_encode(simple_form3_mem_reg( src, dst ) );
5064 ins_pipe(iload_mem);
5065 %}
5066
5067 // Store integer to stack slot
5068 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5069 match(Set dst src);
5070 ins_cost(MEMORY_REF_COST);
5071
5072 format %{ "STW $src,$dst\t!stk" %}
5073 opcode(Assembler::stw_op3);
5074 ins_encode(simple_form3_mem_reg( dst, src ) );
5075 ins_pipe(istore_mem_reg);
5076 %}
5077
5078 // Load long from stack slot
5079 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5080 match(Set dst src);
5081
5082 ins_cost(MEMORY_REF_COST);
5083 format %{ "LDX $src,$dst\t! long" %}
5084 opcode(Assembler::ldx_op3);
5085 ins_encode(simple_form3_mem_reg( src, dst ) );
5086 ins_pipe(iload_mem);
5087 %}
5088
5089 // Store long to stack slot
5090 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5091 match(Set dst src);
5092
5093 ins_cost(MEMORY_REF_COST);
5094 format %{ "STX $src,$dst\t! long" %}
5095 opcode(Assembler::stx_op3);
5096 ins_encode(simple_form3_mem_reg( dst, src ) );
5097 ins_pipe(istore_mem_reg);
5098 %}
5099
5100 // Load pointer from stack slot, 64-bit encoding
5101 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5102 match(Set dst src);
5103 ins_cost(MEMORY_REF_COST);
5104 format %{ "LDX $src,$dst\t!ptr" %}
5105 opcode(Assembler::ldx_op3);
5106 ins_encode(simple_form3_mem_reg( src, dst ) );
5107 ins_pipe(iload_mem);
5108 %}
5109
5110 // Store pointer to stack slot
5111 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5112 match(Set dst src);
5113 ins_cost(MEMORY_REF_COST);
5114 format %{ "STX $src,$dst\t!ptr" %}
5115 opcode(Assembler::stx_op3);
5116 ins_encode(simple_form3_mem_reg( dst, src ) );
5117 ins_pipe(istore_mem_reg);
5118 %}
5119
5120 //------------Special Nop instructions for bundling - no match rules-----------
5121 // Nop using the A0 functional unit
5122 instruct Nop_A0() %{
5123 ins_cost(0);
5124
5125 format %{ "NOP ! Alu Pipeline" %}
5126 opcode(Assembler::or_op3, Assembler::arith_op);
5127 ins_encode( form2_nop() );
5128 ins_pipe(ialu_nop_A0);
5129 %}
5130
5131 // Nop using the A1 functional unit
5132 instruct Nop_A1( ) %{
5133 ins_cost(0);
5134
5135 format %{ "NOP ! Alu Pipeline" %}
5136 opcode(Assembler::or_op3, Assembler::arith_op);
5137 ins_encode( form2_nop() );
5138 ins_pipe(ialu_nop_A1);
5139 %}
5140
5141 // Nop using the memory functional unit
5142 instruct Nop_MS( ) %{
5143 ins_cost(0);
5144
5145 format %{ "NOP ! Memory Pipeline" %}
5146 ins_encode( emit_mem_nop );
5147 ins_pipe(mem_nop);
5148 %}
5149
5150 // Nop using the floating add functional unit
5151 instruct Nop_FA( ) %{
5152 ins_cost(0);
5153
5154 format %{ "NOP ! Floating Add Pipeline" %}
5155 ins_encode( emit_fadd_nop );
5156 ins_pipe(fadd_nop);
5157 %}
5158
5159 // Nop using the branch functional unit
5160 instruct Nop_BR( ) %{
5161 ins_cost(0);
5162
5163 format %{ "NOP ! Branch Pipeline" %}
5164 ins_encode( emit_br_nop );
5165 ins_pipe(br_nop);
5166 %}
5167
5168 //----------Load/Store/Move Instructions---------------------------------------
5169 //----------Load Instructions--------------------------------------------------
5170 // Load Byte (8bit signed)
5171 instruct loadB(iRegI dst, memory mem) %{
5172 match(Set dst (LoadB mem));
5173 ins_cost(MEMORY_REF_COST);
5174
5175 size(4);
5176 format %{ "LDSB $mem,$dst\t! byte" %}
5177 ins_encode %{
5178 __ ldsb($mem$$Address, $dst$$Register);
5179 %}
5180 ins_pipe(iload_mask_mem);
5181 %}
5182
5183 // Load Byte (8bit signed) into a Long Register
5184 instruct loadB2L(iRegL dst, memory mem) %{
5185 match(Set dst (ConvI2L (LoadB mem)));
5186 ins_cost(MEMORY_REF_COST);
5187
5188 size(4);
5189 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5190 ins_encode %{
5191 __ ldsb($mem$$Address, $dst$$Register);
5192 %}
5193 ins_pipe(iload_mask_mem);
5194 %}
5195
5196 // Load Unsigned Byte (8bit UNsigned) into an int reg
5197 instruct loadUB(iRegI dst, memory mem) %{
5198 match(Set dst (LoadUB mem));
5199 ins_cost(MEMORY_REF_COST);
5200
5201 size(4);
5202 format %{ "LDUB $mem,$dst\t! ubyte" %}
5203 ins_encode %{
5204 __ ldub($mem$$Address, $dst$$Register);
5205 %}
5206 ins_pipe(iload_mem);
5207 %}
5208
5209 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5210 instruct loadUB2L(iRegL dst, memory mem) %{
5211 match(Set dst (ConvI2L (LoadUB mem)));
5212 ins_cost(MEMORY_REF_COST);
5213
5214 size(4);
5215 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5216 ins_encode %{
5217 __ ldub($mem$$Address, $dst$$Register);
5218 %}
5219 ins_pipe(iload_mem);
5220 %}
5221
5222 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5223 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{
5224 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5225 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5226
5227 size(2*4);
5228 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t"
5229 "AND $dst,right_n_bits($mask, 8),$dst" %}
5230 ins_encode %{
5231 __ ldub($mem$$Address, $dst$$Register);
5232 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register);
5233 %}
5234 ins_pipe(iload_mem);
5235 %}
5236
5237 // Load Short (16bit signed)
5238 instruct loadS(iRegI dst, memory mem) %{
5239 match(Set dst (LoadS mem));
5240 ins_cost(MEMORY_REF_COST);
5241
5242 size(4);
5243 format %{ "LDSH $mem,$dst\t! short" %}
5244 ins_encode %{
5245 __ ldsh($mem$$Address, $dst$$Register);
5246 %}
5247 ins_pipe(iload_mask_mem);
5248 %}
5249
5250 // Load Short (16 bit signed) to Byte (8 bit signed)
5251 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5252 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5253 ins_cost(MEMORY_REF_COST);
5254
5255 size(4);
5256
5257 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5258 ins_encode %{
5259 __ ldsb($mem$$Address, $dst$$Register, 1);
5260 %}
5261 ins_pipe(iload_mask_mem);
5262 %}
5263
5264 // Load Short (16bit signed) into a Long Register
5265 instruct loadS2L(iRegL dst, memory mem) %{
5266 match(Set dst (ConvI2L (LoadS mem)));
5267 ins_cost(MEMORY_REF_COST);
5268
5269 size(4);
5270 format %{ "LDSH $mem,$dst\t! short -> long" %}
5271 ins_encode %{
5272 __ ldsh($mem$$Address, $dst$$Register);
5273 %}
5274 ins_pipe(iload_mask_mem);
5275 %}
5276
5277 // Load Unsigned Short/Char (16bit UNsigned)
5278 instruct loadUS(iRegI dst, memory mem) %{
5279 match(Set dst (LoadUS mem));
5280 ins_cost(MEMORY_REF_COST);
5281
5282 size(4);
5283 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5284 ins_encode %{
5285 __ lduh($mem$$Address, $dst$$Register);
5286 %}
5287 ins_pipe(iload_mem);
5288 %}
5289
5290 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5291 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5292 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5293 ins_cost(MEMORY_REF_COST);
5294
5295 size(4);
5296 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5297 ins_encode %{
5298 __ ldsb($mem$$Address, $dst$$Register, 1);
5299 %}
5300 ins_pipe(iload_mask_mem);
5301 %}
5302
5303 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5304 instruct loadUS2L(iRegL dst, memory mem) %{
5305 match(Set dst (ConvI2L (LoadUS mem)));
5306 ins_cost(MEMORY_REF_COST);
5307
5308 size(4);
5309 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5310 ins_encode %{
5311 __ lduh($mem$$Address, $dst$$Register);
5312 %}
5313 ins_pipe(iload_mem);
5314 %}
5315
5316 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5317 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5318 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5319 ins_cost(MEMORY_REF_COST);
5320
5321 size(4);
5322 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5323 ins_encode %{
5324 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5325 %}
5326 ins_pipe(iload_mem);
5327 %}
5328
5329 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5330 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5331 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5332 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5333
5334 size(2*4);
5335 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5336 "AND $dst,$mask,$dst" %}
5337 ins_encode %{
5338 Register Rdst = $dst$$Register;
5339 __ lduh($mem$$Address, Rdst);
5340 __ and3(Rdst, $mask$$constant, Rdst);
5341 %}
5342 ins_pipe(iload_mem);
5343 %}
5344
5345 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register
5346 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5347 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5348 effect(TEMP dst, TEMP tmp);
5349 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5350
5351 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t"
5352 "SET right_n_bits($mask, 16),$tmp\n\t"
5353 "AND $dst,$tmp,$dst" %}
5354 ins_encode %{
5355 Register Rdst = $dst$$Register;
5356 Register Rtmp = $tmp$$Register;
5357 __ lduh($mem$$Address, Rdst);
5358 __ set($mask$$constant & right_n_bits(16), Rtmp);
5359 __ and3(Rdst, Rtmp, Rdst);
5360 %}
5361 ins_pipe(iload_mem);
5362 %}
5363
5364 // Load Integer
5365 instruct loadI(iRegI dst, memory mem) %{
5366 match(Set dst (LoadI mem));
5367 ins_cost(MEMORY_REF_COST);
5368
5369 size(4);
5370 format %{ "LDUW $mem,$dst\t! int" %}
5371 ins_encode %{
5372 __ lduw($mem$$Address, $dst$$Register);
5373 %}
5374 ins_pipe(iload_mem);
5375 %}
5376
5377 // Load Integer to Byte (8 bit signed)
5378 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5379 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5380 ins_cost(MEMORY_REF_COST);
5381
5382 size(4);
5383
5384 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5385 ins_encode %{
5386 __ ldsb($mem$$Address, $dst$$Register, 3);
5387 %}
5388 ins_pipe(iload_mask_mem);
5389 %}
5390
5391 // Load Integer to Unsigned Byte (8 bit UNsigned)
5392 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5393 match(Set dst (AndI (LoadI mem) mask));
5394 ins_cost(MEMORY_REF_COST);
5395
5396 size(4);
5397
5398 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5399 ins_encode %{
5400 __ ldub($mem$$Address, $dst$$Register, 3);
5401 %}
5402 ins_pipe(iload_mask_mem);
5403 %}
5404
5405 // Load Integer to Short (16 bit signed)
5406 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5407 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5408 ins_cost(MEMORY_REF_COST);
5409
5410 size(4);
5411
5412 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5413 ins_encode %{
5414 __ ldsh($mem$$Address, $dst$$Register, 2);
5415 %}
5416 ins_pipe(iload_mask_mem);
5417 %}
5418
5419 // Load Integer to Unsigned Short (16 bit UNsigned)
5420 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5421 match(Set dst (AndI (LoadI mem) mask));
5422 ins_cost(MEMORY_REF_COST);
5423
5424 size(4);
5425
5426 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5427 ins_encode %{
5428 __ lduh($mem$$Address, $dst$$Register, 2);
5429 %}
5430 ins_pipe(iload_mask_mem);
5431 %}
5432
5433 // Load Integer into a Long Register
5434 instruct loadI2L(iRegL dst, memory mem) %{
5435 match(Set dst (ConvI2L (LoadI mem)));
5436 ins_cost(MEMORY_REF_COST);
5437
5438 size(4);
5439 format %{ "LDSW $mem,$dst\t! int -> long" %}
5440 ins_encode %{
5441 __ ldsw($mem$$Address, $dst$$Register);
5442 %}
5443 ins_pipe(iload_mask_mem);
5444 %}
5445
5446 // Load Integer with mask 0xFF into a Long Register
5447 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5448 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5449 ins_cost(MEMORY_REF_COST);
5450
5451 size(4);
5452 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5453 ins_encode %{
5454 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5455 %}
5456 ins_pipe(iload_mem);
5457 %}
5458
5459 // Load Integer with mask 0xFFFF into a Long Register
5460 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5461 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5462 ins_cost(MEMORY_REF_COST);
5463
5464 size(4);
5465 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5466 ins_encode %{
5467 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5468 %}
5469 ins_pipe(iload_mem);
5470 %}
5471
5472 // Load Integer with a 12-bit mask into a Long Register
5473 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5474 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5475 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5476
5477 size(2*4);
5478 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5479 "AND $dst,$mask,$dst" %}
5480 ins_encode %{
5481 Register Rdst = $dst$$Register;
5482 __ lduw($mem$$Address, Rdst);
5483 __ and3(Rdst, $mask$$constant, Rdst);
5484 %}
5485 ins_pipe(iload_mem);
5486 %}
5487
5488 // Load Integer with a 31-bit mask into a Long Register
5489 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5490 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5491 effect(TEMP dst, TEMP tmp);
5492 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5493
5494 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5495 "SET $mask,$tmp\n\t"
5496 "AND $dst,$tmp,$dst" %}
5497 ins_encode %{
5498 Register Rdst = $dst$$Register;
5499 Register Rtmp = $tmp$$Register;
5500 __ lduw($mem$$Address, Rdst);
5501 __ set($mask$$constant, Rtmp);
5502 __ and3(Rdst, Rtmp, Rdst);
5503 %}
5504 ins_pipe(iload_mem);
5505 %}
5506
5507 // Load Unsigned Integer into a Long Register
5508 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5509 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5510 ins_cost(MEMORY_REF_COST);
5511
5512 size(4);
5513 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5514 ins_encode %{
5515 __ lduw($mem$$Address, $dst$$Register);
5516 %}
5517 ins_pipe(iload_mem);
5518 %}
5519
5520 // Load Long - aligned
5521 instruct loadL(iRegL dst, memory mem ) %{
5522 match(Set dst (LoadL mem));
5523 ins_cost(MEMORY_REF_COST);
5524
5525 size(4);
5526 format %{ "LDX $mem,$dst\t! long" %}
5527 ins_encode %{
5528 __ ldx($mem$$Address, $dst$$Register);
5529 %}
5530 ins_pipe(iload_mem);
5531 %}
5532
5533 // Load Long - UNaligned
5534 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5535 match(Set dst (LoadL_unaligned mem));
5536 effect(KILL tmp);
5537 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5538 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5539 "\tLDUW $mem ,$dst\n"
5540 "\tSLLX #32, $dst, $dst\n"
5541 "\tOR $dst, R_O7, $dst" %}
5542 opcode(Assembler::lduw_op3);
5543 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5544 ins_pipe(iload_mem);
5545 %}
5546
5547 // Load Range
5548 instruct loadRange(iRegI dst, memory mem) %{
5549 match(Set dst (LoadRange mem));
5550 ins_cost(MEMORY_REF_COST);
5551
5552 format %{ "LDUW $mem,$dst\t! range" %}
5553 opcode(Assembler::lduw_op3);
5554 ins_encode(simple_form3_mem_reg( mem, dst ) );
5555 ins_pipe(iload_mem);
5556 %}
5557
5558 // Load Integer into %f register (for fitos/fitod)
5559 instruct loadI_freg(regF dst, memory mem) %{
5560 match(Set dst (LoadI mem));
5561 ins_cost(MEMORY_REF_COST);
5562
5563 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5564 opcode(Assembler::ldf_op3);
5565 ins_encode(simple_form3_mem_reg( mem, dst ) );
5566 ins_pipe(floadF_mem);
5567 %}
5568
5569 // Load Pointer
5570 instruct loadP(iRegP dst, memory mem) %{
5571 match(Set dst (LoadP mem));
5572 ins_cost(MEMORY_REF_COST);
5573 size(4);
5574
5575 format %{ "LDX $mem,$dst\t! ptr" %}
5576 ins_encode %{
5577 __ ldx($mem$$Address, $dst$$Register);
5578 %}
5579 ins_pipe(iload_mem);
5580 %}
5581
5582 // Load Compressed Pointer
5583 instruct loadN(iRegN dst, memory mem) %{
5584 match(Set dst (LoadN mem));
5585 ins_cost(MEMORY_REF_COST);
5586 size(4);
5587
5588 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5589 ins_encode %{
5590 __ lduw($mem$$Address, $dst$$Register);
5591 %}
5592 ins_pipe(iload_mem);
5593 %}
5594
5595 // Load Klass Pointer
5596 instruct loadKlass(iRegP dst, memory mem) %{
5597 match(Set dst (LoadKlass mem));
5598 ins_cost(MEMORY_REF_COST);
5599 size(4);
5600
5601 format %{ "LDX $mem,$dst\t! klass ptr" %}
5602 ins_encode %{
5603 __ ldx($mem$$Address, $dst$$Register);
5604 %}
5605 ins_pipe(iload_mem);
5606 %}
5607
5608 // Load narrow Klass Pointer
5609 instruct loadNKlass(iRegN dst, memory mem) %{
5610 match(Set dst (LoadNKlass mem));
5611 ins_cost(MEMORY_REF_COST);
5612 size(4);
5613
5614 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5615 ins_encode %{
5616 __ lduw($mem$$Address, $dst$$Register);
5617 %}
5618 ins_pipe(iload_mem);
5619 %}
5620
5621 // Load Double
5622 instruct loadD(regD dst, memory mem) %{
5623 match(Set dst (LoadD mem));
5624 ins_cost(MEMORY_REF_COST);
5625
5626 format %{ "LDDF $mem,$dst" %}
5627 opcode(Assembler::lddf_op3);
5628 ins_encode(simple_form3_mem_reg( mem, dst ) );
5629 ins_pipe(floadD_mem);
5630 %}
5631
5632 // Load Double - UNaligned
5633 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5634 match(Set dst (LoadD_unaligned mem));
5635 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5636 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5637 "\tLDF $mem+4,$dst.lo\t!" %}
5638 opcode(Assembler::ldf_op3);
5639 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5640 ins_pipe(iload_mem);
5641 %}
5642
5643 // Load Float
5644 instruct loadF(regF dst, memory mem) %{
5645 match(Set dst (LoadF mem));
5646 ins_cost(MEMORY_REF_COST);
5647
5648 format %{ "LDF $mem,$dst" %}
5649 opcode(Assembler::ldf_op3);
5650 ins_encode(simple_form3_mem_reg( mem, dst ) );
5651 ins_pipe(floadF_mem);
5652 %}
5653
5654 // Load Constant
5655 instruct loadConI( iRegI dst, immI src ) %{
5656 match(Set dst src);
5657 ins_cost(DEFAULT_COST * 3/2);
5658 format %{ "SET $src,$dst" %}
5659 ins_encode( Set32(src, dst) );
5660 ins_pipe(ialu_hi_lo_reg);
5661 %}
5662
5663 instruct loadConI13( iRegI dst, immI13 src ) %{
5664 match(Set dst src);
5665
5666 size(4);
5667 format %{ "MOV $src,$dst" %}
5668 ins_encode( Set13( src, dst ) );
5669 ins_pipe(ialu_imm);
5670 %}
5671
5672 instruct loadConP_set(iRegP dst, immP_set con) %{
5673 match(Set dst con);
5674 ins_cost(DEFAULT_COST * 3/2);
5675 format %{ "SET $con,$dst\t! ptr" %}
5676 ins_encode %{
5677 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5678 intptr_t val = $con$$constant;
5679 if (constant_reloc == relocInfo::oop_type) {
5680 __ set_oop_constant((jobject) val, $dst$$Register);
5681 } else if (constant_reloc == relocInfo::metadata_type) {
5682 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5683 } else { // non-oop pointers, e.g. card mark base, heap top
5684 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5685 __ set(val, $dst$$Register);
5686 }
5687 %}
5688 ins_pipe(loadConP);
5689 %}
5690
5691 instruct loadConP_load(iRegP dst, immP_load con) %{
5692 match(Set dst con);
5693 ins_cost(MEMORY_REF_COST);
5694 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
5695 ins_encode %{
5696 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
5697 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
5698 %}
5699 ins_pipe(loadConP);
5700 %}
5701
5702 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
5703 match(Set dst con);
5704 ins_cost(DEFAULT_COST * 3/2);
5705 format %{ "SET $con,$dst\t! non-oop ptr" %}
5706 ins_encode %{
5707 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
5708 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
5709 } else {
5710 __ set($con$$constant, $dst$$Register);
5711 }
5712 %}
5713 ins_pipe(loadConP);
5714 %}
5715
5716 instruct loadConP0(iRegP dst, immP0 src) %{
5717 match(Set dst src);
5718
5719 size(4);
5720 format %{ "CLR $dst\t!ptr" %}
5721 ins_encode %{
5722 __ clr($dst$$Register);
5723 %}
5724 ins_pipe(ialu_imm);
5725 %}
5726
5727 instruct loadConP_poll(iRegP dst, immP_poll src) %{
5728 match(Set dst src);
5729 ins_cost(DEFAULT_COST);
5730 format %{ "SET $src,$dst\t!ptr" %}
5731 ins_encode %{
5732 AddressLiteral polling_page(os::get_polling_page());
5733 __ sethi(polling_page, reg_to_register_object($dst$$reg));
5734 %}
5735 ins_pipe(loadConP_poll);
5736 %}
5737
5738 instruct loadConN0(iRegN dst, immN0 src) %{
5739 match(Set dst src);
5740
5741 size(4);
5742 format %{ "CLR $dst\t! compressed NULL ptr" %}
5743 ins_encode %{
5744 __ clr($dst$$Register);
5745 %}
5746 ins_pipe(ialu_imm);
5747 %}
5748
5749 instruct loadConN(iRegN dst, immN src) %{
5750 match(Set dst src);
5751 ins_cost(DEFAULT_COST * 3/2);
5752 format %{ "SET $src,$dst\t! compressed ptr" %}
5753 ins_encode %{
5754 Register dst = $dst$$Register;
5755 __ set_narrow_oop((jobject)$src$$constant, dst);
5756 %}
5757 ins_pipe(ialu_hi_lo_reg);
5758 %}
5759
5760 instruct loadConNKlass(iRegN dst, immNKlass src) %{
5761 match(Set dst src);
5762 ins_cost(DEFAULT_COST * 3/2);
5763 format %{ "SET $src,$dst\t! compressed klass ptr" %}
5764 ins_encode %{
5765 Register dst = $dst$$Register;
5766 __ set_narrow_klass((Klass*)$src$$constant, dst);
5767 %}
5768 ins_pipe(ialu_hi_lo_reg);
5769 %}
5770
5771 // Materialize long value (predicated by immL_cheap).
5772 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
5773 match(Set dst con);
5774 effect(KILL tmp);
5775 ins_cost(DEFAULT_COST * 3);
5776 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
5777 ins_encode %{
5778 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
5779 %}
5780 ins_pipe(loadConL);
5781 %}
5782
5783 // Load long value from constant table (predicated by immL_expensive).
5784 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
5785 match(Set dst con);
5786 ins_cost(MEMORY_REF_COST);
5787 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
5788 ins_encode %{
5789 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
5790 __ ldx($constanttablebase, con_offset, $dst$$Register);
5791 %}
5792 ins_pipe(loadConL);
5793 %}
5794
5795 instruct loadConL0( iRegL dst, immL0 src ) %{
5796 match(Set dst src);
5797 ins_cost(DEFAULT_COST);
5798 size(4);
5799 format %{ "CLR $dst\t! long" %}
5800 ins_encode( Set13( src, dst ) );
5801 ins_pipe(ialu_imm);
5802 %}
5803
5804 instruct loadConL13( iRegL dst, immL13 src ) %{
5805 match(Set dst src);
5806 ins_cost(DEFAULT_COST * 2);
5807
5808 size(4);
5809 format %{ "MOV $src,$dst\t! long" %}
5810 ins_encode( Set13( src, dst ) );
5811 ins_pipe(ialu_imm);
5812 %}
5813
5814 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
5815 match(Set dst con);
5816 effect(KILL tmp);
5817 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
5818 ins_encode %{
5819 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
5820 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
5821 %}
5822 ins_pipe(loadConFD);
5823 %}
5824
5825 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
5826 match(Set dst con);
5827 effect(KILL tmp);
5828 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
5829 ins_encode %{
5830 // XXX This is a quick fix for 6833573.
5831 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
5832 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
5833 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
5834 %}
5835 ins_pipe(loadConFD);
5836 %}
5837
5838 // Prefetch instructions for allocation.
5839 // Must be safe to execute with invalid address (cannot fault).
5840
5841 instruct prefetchAlloc( memory mem ) %{
5842 predicate(AllocatePrefetchInstr == 0);
5843 match( PrefetchAllocation mem );
5844 ins_cost(MEMORY_REF_COST);
5845
5846 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
5847 opcode(Assembler::prefetch_op3);
5848 ins_encode( form3_mem_prefetch_write( mem ) );
5849 ins_pipe(iload_mem);
5850 %}
5851
5852 // Use BIS instruction to prefetch for allocation.
5853 // Could fault, need space at the end of TLAB.
5854 instruct prefetchAlloc_bis( iRegP dst ) %{
5855 predicate(AllocatePrefetchInstr == 1);
5856 match( PrefetchAllocation dst );
5857 ins_cost(MEMORY_REF_COST);
5858 size(4);
5859
5860 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
5861 ins_encode %{
5862 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
5863 %}
5864 ins_pipe(istore_mem_reg);
5865 %}
5866
5867 // Next code is used for finding next cache line address to prefetch.
5868 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
5869 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
5870 ins_cost(DEFAULT_COST);
5871 size(4);
5872
5873 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
5874 ins_encode %{
5875 __ and3($src$$Register, $mask$$constant, $dst$$Register);
5876 %}
5877 ins_pipe(ialu_reg_imm);
5878 %}
5879
5880 //----------Store Instructions-------------------------------------------------
5881 // Store Byte
5882 instruct storeB(memory mem, iRegI src) %{
5883 match(Set mem (StoreB mem src));
5884 ins_cost(MEMORY_REF_COST);
5885
5886 format %{ "STB $src,$mem\t! byte" %}
5887 opcode(Assembler::stb_op3);
5888 ins_encode(simple_form3_mem_reg( mem, src ) );
5889 ins_pipe(istore_mem_reg);
5890 %}
5891
5892 instruct storeB0(memory mem, immI0 src) %{
5893 match(Set mem (StoreB mem src));
5894 ins_cost(MEMORY_REF_COST);
5895
5896 format %{ "STB $src,$mem\t! byte" %}
5897 opcode(Assembler::stb_op3);
5898 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5899 ins_pipe(istore_mem_zero);
5900 %}
5901
5902 instruct storeCM0(memory mem, immI0 src) %{
5903 match(Set mem (StoreCM mem src));
5904 ins_cost(MEMORY_REF_COST);
5905
5906 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
5907 opcode(Assembler::stb_op3);
5908 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5909 ins_pipe(istore_mem_zero);
5910 %}
5911
5912 // Store Char/Short
5913 instruct storeC(memory mem, iRegI src) %{
5914 match(Set mem (StoreC mem src));
5915 ins_cost(MEMORY_REF_COST);
5916
5917 format %{ "STH $src,$mem\t! short" %}
5918 opcode(Assembler::sth_op3);
5919 ins_encode(simple_form3_mem_reg( mem, src ) );
5920 ins_pipe(istore_mem_reg);
5921 %}
5922
5923 instruct storeC0(memory mem, immI0 src) %{
5924 match(Set mem (StoreC mem src));
5925 ins_cost(MEMORY_REF_COST);
5926
5927 format %{ "STH $src,$mem\t! short" %}
5928 opcode(Assembler::sth_op3);
5929 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5930 ins_pipe(istore_mem_zero);
5931 %}
5932
5933 // Store Integer
5934 instruct storeI(memory mem, iRegI src) %{
5935 match(Set mem (StoreI mem src));
5936 ins_cost(MEMORY_REF_COST);
5937
5938 format %{ "STW $src,$mem" %}
5939 opcode(Assembler::stw_op3);
5940 ins_encode(simple_form3_mem_reg( mem, src ) );
5941 ins_pipe(istore_mem_reg);
5942 %}
5943
5944 // Store Long
5945 instruct storeL(memory mem, iRegL src) %{
5946 match(Set mem (StoreL mem src));
5947 ins_cost(MEMORY_REF_COST);
5948 format %{ "STX $src,$mem\t! long" %}
5949 opcode(Assembler::stx_op3);
5950 ins_encode(simple_form3_mem_reg( mem, src ) );
5951 ins_pipe(istore_mem_reg);
5952 %}
5953
5954 instruct storeI0(memory mem, immI0 src) %{
5955 match(Set mem (StoreI mem src));
5956 ins_cost(MEMORY_REF_COST);
5957
5958 format %{ "STW $src,$mem" %}
5959 opcode(Assembler::stw_op3);
5960 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5961 ins_pipe(istore_mem_zero);
5962 %}
5963
5964 instruct storeL0(memory mem, immL0 src) %{
5965 match(Set mem (StoreL mem src));
5966 ins_cost(MEMORY_REF_COST);
5967
5968 format %{ "STX $src,$mem" %}
5969 opcode(Assembler::stx_op3);
5970 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5971 ins_pipe(istore_mem_zero);
5972 %}
5973
5974 // Store Integer from float register (used after fstoi)
5975 instruct storeI_Freg(memory mem, regF src) %{
5976 match(Set mem (StoreI mem src));
5977 ins_cost(MEMORY_REF_COST);
5978
5979 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
5980 opcode(Assembler::stf_op3);
5981 ins_encode(simple_form3_mem_reg( mem, src ) );
5982 ins_pipe(fstoreF_mem_reg);
5983 %}
5984
5985 // Store Pointer
5986 instruct storeP(memory dst, sp_ptr_RegP src) %{
5987 match(Set dst (StoreP dst src));
5988 ins_cost(MEMORY_REF_COST);
5989
5990 format %{ "STX $src,$dst\t! ptr" %}
5991 opcode(Assembler::stx_op3, 0, REGP_OP);
5992 ins_encode( form3_mem_reg( dst, src ) );
5993 ins_pipe(istore_mem_spORreg);
5994 %}
5995
5996 instruct storeP0(memory dst, immP0 src) %{
5997 match(Set dst (StoreP dst src));
5998 ins_cost(MEMORY_REF_COST);
5999
6000 format %{ "STX $src,$dst\t! ptr" %}
6001 opcode(Assembler::stx_op3, 0, REGP_OP);
6002 ins_encode( form3_mem_reg( dst, R_G0 ) );
6003 ins_pipe(istore_mem_zero);
6004 %}
6005
6006 // Store Compressed Pointer
6007 instruct storeN(memory dst, iRegN src) %{
6008 match(Set dst (StoreN dst src));
6009 ins_cost(MEMORY_REF_COST);
6010 size(4);
6011
6012 format %{ "STW $src,$dst\t! compressed ptr" %}
6013 ins_encode %{
6014 Register base = as_Register($dst$$base);
6015 Register index = as_Register($dst$$index);
6016 Register src = $src$$Register;
6017 if (index != G0) {
6018 __ stw(src, base, index);
6019 } else {
6020 __ stw(src, base, $dst$$disp);
6021 }
6022 %}
6023 ins_pipe(istore_mem_spORreg);
6024 %}
6025
6026 instruct storeNKlass(memory dst, iRegN src) %{
6027 match(Set dst (StoreNKlass dst src));
6028 ins_cost(MEMORY_REF_COST);
6029 size(4);
6030
6031 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6032 ins_encode %{
6033 Register base = as_Register($dst$$base);
6034 Register index = as_Register($dst$$index);
6035 Register src = $src$$Register;
6036 if (index != G0) {
6037 __ stw(src, base, index);
6038 } else {
6039 __ stw(src, base, $dst$$disp);
6040 }
6041 %}
6042 ins_pipe(istore_mem_spORreg);
6043 %}
6044
6045 instruct storeN0(memory dst, immN0 src) %{
6046 match(Set dst (StoreN dst src));
6047 ins_cost(MEMORY_REF_COST);
6048 size(4);
6049
6050 format %{ "STW $src,$dst\t! compressed ptr" %}
6051 ins_encode %{
6052 Register base = as_Register($dst$$base);
6053 Register index = as_Register($dst$$index);
6054 if (index != G0) {
6055 __ stw(0, base, index);
6056 } else {
6057 __ stw(0, base, $dst$$disp);
6058 }
6059 %}
6060 ins_pipe(istore_mem_zero);
6061 %}
6062
6063 // Store Double
6064 instruct storeD( memory mem, regD src) %{
6065 match(Set mem (StoreD mem src));
6066 ins_cost(MEMORY_REF_COST);
6067
6068 format %{ "STDF $src,$mem" %}
6069 opcode(Assembler::stdf_op3);
6070 ins_encode(simple_form3_mem_reg( mem, src ) );
6071 ins_pipe(fstoreD_mem_reg);
6072 %}
6073
6074 instruct storeD0( memory mem, immD0 src) %{
6075 match(Set mem (StoreD mem src));
6076 ins_cost(MEMORY_REF_COST);
6077
6078 format %{ "STX $src,$mem" %}
6079 opcode(Assembler::stx_op3);
6080 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6081 ins_pipe(fstoreD_mem_zero);
6082 %}
6083
6084 // Store Float
6085 instruct storeF( memory mem, regF src) %{
6086 match(Set mem (StoreF mem src));
6087 ins_cost(MEMORY_REF_COST);
6088
6089 format %{ "STF $src,$mem" %}
6090 opcode(Assembler::stf_op3);
6091 ins_encode(simple_form3_mem_reg( mem, src ) );
6092 ins_pipe(fstoreF_mem_reg);
6093 %}
6094
6095 instruct storeF0( memory mem, immF0 src) %{
6096 match(Set mem (StoreF mem src));
6097 ins_cost(MEMORY_REF_COST);
6098
6099 format %{ "STW $src,$mem\t! storeF0" %}
6100 opcode(Assembler::stw_op3);
6101 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6102 ins_pipe(fstoreF_mem_zero);
6103 %}
6104
6105 // Convert oop pointer into compressed form
6106 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6107 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6108 match(Set dst (EncodeP src));
6109 format %{ "encode_heap_oop $src, $dst" %}
6110 ins_encode %{
6111 __ encode_heap_oop($src$$Register, $dst$$Register);
6112 %}
6113 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6114 ins_pipe(ialu_reg);
6115 %}
6116
6117 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6118 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6119 match(Set dst (EncodeP src));
6120 format %{ "encode_heap_oop_not_null $src, $dst" %}
6121 ins_encode %{
6122 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6123 %}
6124 ins_pipe(ialu_reg);
6125 %}
6126
6127 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6128 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6129 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6130 match(Set dst (DecodeN src));
6131 format %{ "decode_heap_oop $src, $dst" %}
6132 ins_encode %{
6133 __ decode_heap_oop($src$$Register, $dst$$Register);
6134 %}
6135 ins_pipe(ialu_reg);
6136 %}
6137
6138 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6139 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6140 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6141 match(Set dst (DecodeN src));
6142 format %{ "decode_heap_oop_not_null $src, $dst" %}
6143 ins_encode %{
6144 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6145 %}
6146 ins_pipe(ialu_reg);
6147 %}
6148
6149 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6150 match(Set dst (EncodePKlass src));
6151 format %{ "encode_klass_not_null $src, $dst" %}
6152 ins_encode %{
6153 __ encode_klass_not_null($src$$Register, $dst$$Register);
6154 %}
6155 ins_pipe(ialu_reg);
6156 %}
6157
6158 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6159 match(Set dst (DecodeNKlass src));
6160 format %{ "decode_klass_not_null $src, $dst" %}
6161 ins_encode %{
6162 __ decode_klass_not_null($src$$Register, $dst$$Register);
6163 %}
6164 ins_pipe(ialu_reg);
6165 %}
6166
6167 //----------MemBar Instructions-----------------------------------------------
6168 // Memory barrier flavors
6169
6170 instruct membar_acquire() %{
6171 match(MemBarAcquire);
6172 match(LoadFence);
6173 ins_cost(4*MEMORY_REF_COST);
6174
6175 size(0);
6176 format %{ "MEMBAR-acquire" %}
6177 ins_encode( enc_membar_acquire );
6178 ins_pipe(long_memory_op);
6179 %}
6180
6181 instruct membar_acquire_lock() %{
6182 match(MemBarAcquireLock);
6183 ins_cost(0);
6184
6185 size(0);
6186 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6187 ins_encode( );
6188 ins_pipe(empty);
6189 %}
6190
6191 instruct membar_release() %{
6192 match(MemBarRelease);
6193 match(StoreFence);
6194 ins_cost(4*MEMORY_REF_COST);
6195
6196 size(0);
6197 format %{ "MEMBAR-release" %}
6198 ins_encode( enc_membar_release );
6199 ins_pipe(long_memory_op);
6200 %}
6201
6202 instruct membar_release_lock() %{
6203 match(MemBarReleaseLock);
6204 ins_cost(0);
6205
6206 size(0);
6207 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6208 ins_encode( );
6209 ins_pipe(empty);
6210 %}
6211
6212 instruct membar_volatile() %{
6213 match(MemBarVolatile);
6214 ins_cost(4*MEMORY_REF_COST);
6215
6216 size(4);
6217 format %{ "MEMBAR-volatile" %}
6218 ins_encode( enc_membar_volatile );
6219 ins_pipe(long_memory_op);
6220 %}
6221
6222 instruct unnecessary_membar_volatile() %{
6223 match(MemBarVolatile);
6224 predicate(Matcher::post_store_load_barrier(n));
6225 ins_cost(0);
6226
6227 size(0);
6228 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6229 ins_encode( );
6230 ins_pipe(empty);
6231 %}
6232
6233 instruct membar_storestore() %{
6234 match(MemBarStoreStore);
6235 ins_cost(0);
6236
6237 size(0);
6238 format %{ "!MEMBAR-storestore (empty encoding)" %}
6239 ins_encode( );
6240 ins_pipe(empty);
6241 %}
6242
6243 //----------Register Move Instructions-----------------------------------------
6244 instruct roundDouble_nop(regD dst) %{
6245 match(Set dst (RoundDouble dst));
6246 ins_cost(0);
6247 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6248 ins_encode( );
6249 ins_pipe(empty);
6250 %}
6251
6252
6253 instruct roundFloat_nop(regF dst) %{
6254 match(Set dst (RoundFloat dst));
6255 ins_cost(0);
6256 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6257 ins_encode( );
6258 ins_pipe(empty);
6259 %}
6260
6261
6262 // Cast Index to Pointer for unsafe natives
6263 instruct castX2P(iRegX src, iRegP dst) %{
6264 match(Set dst (CastX2P src));
6265
6266 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6267 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6268 ins_pipe(ialu_reg);
6269 %}
6270
6271 // Cast Pointer to Index for unsafe natives
6272 instruct castP2X(iRegP src, iRegX dst) %{
6273 match(Set dst (CastP2X src));
6274
6275 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6276 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6277 ins_pipe(ialu_reg);
6278 %}
6279
6280 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6281 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6282 match(Set stkSlot src); // chain rule
6283 ins_cost(MEMORY_REF_COST);
6284 format %{ "STDF $src,$stkSlot\t!stk" %}
6285 opcode(Assembler::stdf_op3);
6286 ins_encode(simple_form3_mem_reg(stkSlot, src));
6287 ins_pipe(fstoreD_stk_reg);
6288 %}
6289
6290 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6291 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6292 match(Set dst stkSlot); // chain rule
6293 ins_cost(MEMORY_REF_COST);
6294 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6295 opcode(Assembler::lddf_op3);
6296 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6297 ins_pipe(floadD_stk);
6298 %}
6299
6300 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6301 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6302 match(Set stkSlot src); // chain rule
6303 ins_cost(MEMORY_REF_COST);
6304 format %{ "STF $src,$stkSlot\t!stk" %}
6305 opcode(Assembler::stf_op3);
6306 ins_encode(simple_form3_mem_reg(stkSlot, src));
6307 ins_pipe(fstoreF_stk_reg);
6308 %}
6309
6310 //----------Conditional Move---------------------------------------------------
6311 // Conditional move
6312 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6313 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6314 ins_cost(150);
6315 format %{ "MOV$cmp $pcc,$src,$dst" %}
6316 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6317 ins_pipe(ialu_reg);
6318 %}
6319
6320 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6321 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6322 ins_cost(140);
6323 format %{ "MOV$cmp $pcc,$src,$dst" %}
6324 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6325 ins_pipe(ialu_imm);
6326 %}
6327
6328 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6329 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6330 ins_cost(150);
6331 size(4);
6332 format %{ "MOV$cmp $icc,$src,$dst" %}
6333 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6334 ins_pipe(ialu_reg);
6335 %}
6336
6337 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6338 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6339 ins_cost(140);
6340 size(4);
6341 format %{ "MOV$cmp $icc,$src,$dst" %}
6342 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6343 ins_pipe(ialu_imm);
6344 %}
6345
6346 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6347 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6348 ins_cost(150);
6349 size(4);
6350 format %{ "MOV$cmp $icc,$src,$dst" %}
6351 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6352 ins_pipe(ialu_reg);
6353 %}
6354
6355 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6356 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6357 ins_cost(140);
6358 size(4);
6359 format %{ "MOV$cmp $icc,$src,$dst" %}
6360 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6361 ins_pipe(ialu_imm);
6362 %}
6363
6364 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6365 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6366 ins_cost(150);
6367 size(4);
6368 format %{ "MOV$cmp $fcc,$src,$dst" %}
6369 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6370 ins_pipe(ialu_reg);
6371 %}
6372
6373 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6374 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6375 ins_cost(140);
6376 size(4);
6377 format %{ "MOV$cmp $fcc,$src,$dst" %}
6378 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6379 ins_pipe(ialu_imm);
6380 %}
6381
6382 // Conditional move for RegN. Only cmov(reg,reg).
6383 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6384 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6385 ins_cost(150);
6386 format %{ "MOV$cmp $pcc,$src,$dst" %}
6387 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6388 ins_pipe(ialu_reg);
6389 %}
6390
6391 // This instruction also works with CmpN so we don't need cmovNN_reg.
6392 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6393 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6394 ins_cost(150);
6395 size(4);
6396 format %{ "MOV$cmp $icc,$src,$dst" %}
6397 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6398 ins_pipe(ialu_reg);
6399 %}
6400
6401 // This instruction also works with CmpN so we don't need cmovNN_reg.
6402 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6403 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6404 ins_cost(150);
6405 size(4);
6406 format %{ "MOV$cmp $icc,$src,$dst" %}
6407 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6408 ins_pipe(ialu_reg);
6409 %}
6410
6411 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6412 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6413 ins_cost(150);
6414 size(4);
6415 format %{ "MOV$cmp $fcc,$src,$dst" %}
6416 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6417 ins_pipe(ialu_reg);
6418 %}
6419
6420 // Conditional move
6421 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6422 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6423 ins_cost(150);
6424 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6425 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6426 ins_pipe(ialu_reg);
6427 %}
6428
6429 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6430 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6431 ins_cost(140);
6432 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6433 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6434 ins_pipe(ialu_imm);
6435 %}
6436
6437 // This instruction also works with CmpN so we don't need cmovPN_reg.
6438 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6439 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6440 ins_cost(150);
6441
6442 size(4);
6443 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6444 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6445 ins_pipe(ialu_reg);
6446 %}
6447
6448 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6449 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6450 ins_cost(150);
6451
6452 size(4);
6453 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6454 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6455 ins_pipe(ialu_reg);
6456 %}
6457
6458 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6459 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6460 ins_cost(140);
6461
6462 size(4);
6463 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6464 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6465 ins_pipe(ialu_imm);
6466 %}
6467
6468 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6469 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6470 ins_cost(140);
6471
6472 size(4);
6473 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6474 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6475 ins_pipe(ialu_imm);
6476 %}
6477
6478 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6479 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6480 ins_cost(150);
6481 size(4);
6482 format %{ "MOV$cmp $fcc,$src,$dst" %}
6483 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6484 ins_pipe(ialu_imm);
6485 %}
6486
6487 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6488 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6489 ins_cost(140);
6490 size(4);
6491 format %{ "MOV$cmp $fcc,$src,$dst" %}
6492 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6493 ins_pipe(ialu_imm);
6494 %}
6495
6496 // Conditional move
6497 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6498 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6499 ins_cost(150);
6500 opcode(0x101);
6501 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6502 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6503 ins_pipe(int_conditional_float_move);
6504 %}
6505
6506 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6507 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6508 ins_cost(150);
6509
6510 size(4);
6511 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6512 opcode(0x101);
6513 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6514 ins_pipe(int_conditional_float_move);
6515 %}
6516
6517 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6518 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6519 ins_cost(150);
6520
6521 size(4);
6522 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6523 opcode(0x101);
6524 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6525 ins_pipe(int_conditional_float_move);
6526 %}
6527
6528 // Conditional move,
6529 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6530 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6531 ins_cost(150);
6532 size(4);
6533 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6534 opcode(0x1);
6535 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6536 ins_pipe(int_conditional_double_move);
6537 %}
6538
6539 // Conditional move
6540 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6541 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6542 ins_cost(150);
6543 size(4);
6544 opcode(0x102);
6545 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6546 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6547 ins_pipe(int_conditional_double_move);
6548 %}
6549
6550 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6551 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6552 ins_cost(150);
6553
6554 size(4);
6555 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6556 opcode(0x102);
6557 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6558 ins_pipe(int_conditional_double_move);
6559 %}
6560
6561 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6562 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6563 ins_cost(150);
6564
6565 size(4);
6566 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6567 opcode(0x102);
6568 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6569 ins_pipe(int_conditional_double_move);
6570 %}
6571
6572 // Conditional move,
6573 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6574 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6575 ins_cost(150);
6576 size(4);
6577 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6578 opcode(0x2);
6579 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6580 ins_pipe(int_conditional_double_move);
6581 %}
6582
6583 // Conditional move
6584 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6585 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6586 ins_cost(150);
6587 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6588 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6589 ins_pipe(ialu_reg);
6590 %}
6591
6592 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6593 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6594 ins_cost(140);
6595 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6596 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6597 ins_pipe(ialu_imm);
6598 %}
6599
6600 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6601 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6602 ins_cost(150);
6603
6604 size(4);
6605 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6606 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6607 ins_pipe(ialu_reg);
6608 %}
6609
6610
6611 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6612 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6613 ins_cost(150);
6614
6615 size(4);
6616 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6617 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6618 ins_pipe(ialu_reg);
6619 %}
6620
6621
6622 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6623 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6624 ins_cost(150);
6625
6626 size(4);
6627 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6628 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6629 ins_pipe(ialu_reg);
6630 %}
6631
6632
6633
6634 //----------OS and Locking Instructions----------------------------------------
6635
6636 // This name is KNOWN by the ADLC and cannot be changed.
6637 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6638 // for this guy.
6639 instruct tlsLoadP(g2RegP dst) %{
6640 match(Set dst (ThreadLocal));
6641
6642 size(0);
6643 ins_cost(0);
6644 format %{ "# TLS is in G2" %}
6645 ins_encode( /*empty encoding*/ );
6646 ins_pipe(ialu_none);
6647 %}
6648
6649 instruct checkCastPP( iRegP dst ) %{
6650 match(Set dst (CheckCastPP dst));
6651
6652 size(0);
6653 format %{ "# checkcastPP of $dst" %}
6654 ins_encode( /*empty encoding*/ );
6655 ins_pipe(empty);
6656 %}
6657
6658
6659 instruct castPP( iRegP dst ) %{
6660 match(Set dst (CastPP dst));
6661 format %{ "# castPP of $dst" %}
6662 ins_encode( /*empty encoding*/ );
6663 ins_pipe(empty);
6664 %}
6665
6666 instruct castII( iRegI dst ) %{
6667 match(Set dst (CastII dst));
6668 format %{ "# castII of $dst" %}
6669 ins_encode( /*empty encoding*/ );
6670 ins_cost(0);
6671 ins_pipe(empty);
6672 %}
6673
6674 //----------Arithmetic Instructions--------------------------------------------
6675 // Addition Instructions
6676 // Register Addition
6677 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6678 match(Set dst (AddI src1 src2));
6679
6680 size(4);
6681 format %{ "ADD $src1,$src2,$dst" %}
6682 ins_encode %{
6683 __ add($src1$$Register, $src2$$Register, $dst$$Register);
6684 %}
6685 ins_pipe(ialu_reg_reg);
6686 %}
6687
6688 // Immediate Addition
6689 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6690 match(Set dst (AddI src1 src2));
6691
6692 size(4);
6693 format %{ "ADD $src1,$src2,$dst" %}
6694 opcode(Assembler::add_op3, Assembler::arith_op);
6695 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6696 ins_pipe(ialu_reg_imm);
6697 %}
6698
6699 // Pointer Register Addition
6700 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
6701 match(Set dst (AddP src1 src2));
6702
6703 size(4);
6704 format %{ "ADD $src1,$src2,$dst" %}
6705 opcode(Assembler::add_op3, Assembler::arith_op);
6706 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6707 ins_pipe(ialu_reg_reg);
6708 %}
6709
6710 // Pointer Immediate Addition
6711 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
6712 match(Set dst (AddP src1 src2));
6713
6714 size(4);
6715 format %{ "ADD $src1,$src2,$dst" %}
6716 opcode(Assembler::add_op3, Assembler::arith_op);
6717 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6718 ins_pipe(ialu_reg_imm);
6719 %}
6720
6721 // Long Addition
6722 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6723 match(Set dst (AddL src1 src2));
6724
6725 size(4);
6726 format %{ "ADD $src1,$src2,$dst\t! long" %}
6727 opcode(Assembler::add_op3, Assembler::arith_op);
6728 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6729 ins_pipe(ialu_reg_reg);
6730 %}
6731
6732 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6733 match(Set dst (AddL src1 con));
6734
6735 size(4);
6736 format %{ "ADD $src1,$con,$dst" %}
6737 opcode(Assembler::add_op3, Assembler::arith_op);
6738 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6739 ins_pipe(ialu_reg_imm);
6740 %}
6741
6742 //----------Conditional_store--------------------------------------------------
6743 // Conditional-store of the updated heap-top.
6744 // Used during allocation of the shared heap.
6745 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
6746
6747 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
6748 instruct loadPLocked(iRegP dst, memory mem) %{
6749 match(Set dst (LoadPLocked mem));
6750 ins_cost(MEMORY_REF_COST);
6751
6752 format %{ "LDX $mem,$dst\t! ptr" %}
6753 opcode(Assembler::ldx_op3, 0, REGP_OP);
6754 ins_encode( form3_mem_reg( mem, dst ) );
6755 ins_pipe(iload_mem);
6756 %}
6757
6758 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
6759 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
6760 effect( KILL newval );
6761 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
6762 "CMP R_G3,$oldval\t\t! See if we made progress" %}
6763 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
6764 ins_pipe( long_memory_op );
6765 %}
6766
6767 // Conditional-store of an int value.
6768 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
6769 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
6770 effect( KILL newval );
6771 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6772 "CMP $oldval,$newval\t\t! See if we made progress" %}
6773 ins_encode( enc_cas(mem_ptr,oldval,newval) );
6774 ins_pipe( long_memory_op );
6775 %}
6776
6777 // Conditional-store of a long value.
6778 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
6779 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
6780 effect( KILL newval );
6781 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6782 "CMP $oldval,$newval\t\t! See if we made progress" %}
6783 ins_encode( enc_cas(mem_ptr,oldval,newval) );
6784 ins_pipe( long_memory_op );
6785 %}
6786
6787 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
6788
6789 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6790 predicate(VM_Version::supports_cx8());
6791 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
6792 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
6793 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6794 format %{
6795 "MOV $newval,O7\n\t"
6796 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6797 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6798 "MOV 1,$res\n\t"
6799 "MOVne xcc,R_G0,$res"
6800 %}
6801 ins_encode( enc_casx(mem_ptr, oldval, newval),
6802 enc_lflags_ne_to_boolean(res) );
6803 ins_pipe( long_memory_op );
6804 %}
6805
6806
6807 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6808 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
6809 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
6810 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6811 format %{
6812 "MOV $newval,O7\n\t"
6813 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6814 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6815 "MOV 1,$res\n\t"
6816 "MOVne icc,R_G0,$res"
6817 %}
6818 ins_encode( enc_casi(mem_ptr, oldval, newval),
6819 enc_iflags_ne_to_boolean(res) );
6820 ins_pipe( long_memory_op );
6821 %}
6822
6823 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6824 predicate(VM_Version::supports_cx8());
6825 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
6826 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
6827 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6828 format %{
6829 "MOV $newval,O7\n\t"
6830 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6831 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6832 "MOV 1,$res\n\t"
6833 "MOVne xcc,R_G0,$res"
6834 %}
6835 ins_encode( enc_casx(mem_ptr, oldval, newval),
6836 enc_lflags_ne_to_boolean(res) );
6837 ins_pipe( long_memory_op );
6838 %}
6839
6840 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6841 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
6842 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
6843 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6844 format %{
6845 "MOV $newval,O7\n\t"
6846 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6847 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6848 "MOV 1,$res\n\t"
6849 "MOVne icc,R_G0,$res"
6850 %}
6851 ins_encode( enc_casi(mem_ptr, oldval, newval),
6852 enc_iflags_ne_to_boolean(res) );
6853 ins_pipe( long_memory_op );
6854 %}
6855
6856 instruct compareAndExchangeI(iRegP mem_ptr, iRegI oldval, iRegI newval)
6857 %{
6858 match(Set newval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
6859 effect( USE mem_ptr );
6860
6861 format %{
6862 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t"
6863 %}
6864 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) );
6865 ins_pipe( long_memory_op );
6866 %}
6867
6868 instruct compareAndExchangeL(iRegP mem_ptr, iRegL oldval, iRegL newval)
6869 %{
6870 match(Set newval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
6871 effect( USE mem_ptr );
6872
6873 format %{
6874 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t"
6875 %}
6876 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) );
6877 ins_pipe( long_memory_op );
6878 %}
6879
6880 instruct compareAndExchangeP(iRegP mem_ptr, iRegP oldval, iRegP newval)
6881 %{
6882 match(Set newval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
6883 effect( USE mem_ptr );
6884
6885 format %{
6886 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t"
6887 %}
6888 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) );
6889 ins_pipe( long_memory_op );
6890 %}
6891
6892 instruct compareAndExchangeN(iRegP mem_ptr, iRegN oldval, iRegN newval)
6893 %{
6894 match(Set newval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
6895 effect( USE mem_ptr );
6896
6897 format %{
6898 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t"
6899 %}
6900 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) );
6901 ins_pipe( long_memory_op );
6902 %}
6903
6904 instruct xchgI( memory mem, iRegI newval) %{
6905 match(Set newval (GetAndSetI mem newval));
6906 format %{ "SWAP [$mem],$newval" %}
6907 size(4);
6908 ins_encode %{
6909 __ swap($mem$$Address, $newval$$Register);
6910 %}
6911 ins_pipe( long_memory_op );
6912 %}
6913
6914
6915 instruct xchgN( memory mem, iRegN newval) %{
6916 match(Set newval (GetAndSetN mem newval));
6917 format %{ "SWAP [$mem],$newval" %}
6918 size(4);
6919 ins_encode %{
6920 __ swap($mem$$Address, $newval$$Register);
6921 %}
6922 ins_pipe( long_memory_op );
6923 %}
6924
6925 //---------------------
6926 // Subtraction Instructions
6927 // Register Subtraction
6928 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6929 match(Set dst (SubI src1 src2));
6930
6931 size(4);
6932 format %{ "SUB $src1,$src2,$dst" %}
6933 opcode(Assembler::sub_op3, Assembler::arith_op);
6934 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6935 ins_pipe(ialu_reg_reg);
6936 %}
6937
6938 // Immediate Subtraction
6939 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6940 match(Set dst (SubI src1 src2));
6941
6942 size(4);
6943 format %{ "SUB $src1,$src2,$dst" %}
6944 opcode(Assembler::sub_op3, Assembler::arith_op);
6945 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6946 ins_pipe(ialu_reg_imm);
6947 %}
6948
6949 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
6950 match(Set dst (SubI zero src2));
6951
6952 size(4);
6953 format %{ "NEG $src2,$dst" %}
6954 opcode(Assembler::sub_op3, Assembler::arith_op);
6955 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
6956 ins_pipe(ialu_zero_reg);
6957 %}
6958
6959 // Long subtraction
6960 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6961 match(Set dst (SubL src1 src2));
6962
6963 size(4);
6964 format %{ "SUB $src1,$src2,$dst\t! long" %}
6965 opcode(Assembler::sub_op3, Assembler::arith_op);
6966 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6967 ins_pipe(ialu_reg_reg);
6968 %}
6969
6970 // Immediate Subtraction
6971 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6972 match(Set dst (SubL src1 con));
6973
6974 size(4);
6975 format %{ "SUB $src1,$con,$dst\t! long" %}
6976 opcode(Assembler::sub_op3, Assembler::arith_op);
6977 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6978 ins_pipe(ialu_reg_imm);
6979 %}
6980
6981 // Long negation
6982 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
6983 match(Set dst (SubL zero src2));
6984
6985 size(4);
6986 format %{ "NEG $src2,$dst\t! long" %}
6987 opcode(Assembler::sub_op3, Assembler::arith_op);
6988 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
6989 ins_pipe(ialu_zero_reg);
6990 %}
6991
6992 // Multiplication Instructions
6993 // Integer Multiplication
6994 // Register Multiplication
6995 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6996 match(Set dst (MulI src1 src2));
6997
6998 size(4);
6999 format %{ "MULX $src1,$src2,$dst" %}
7000 opcode(Assembler::mulx_op3, Assembler::arith_op);
7001 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7002 ins_pipe(imul_reg_reg);
7003 %}
7004
7005 // Immediate Multiplication
7006 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7007 match(Set dst (MulI src1 src2));
7008
7009 size(4);
7010 format %{ "MULX $src1,$src2,$dst" %}
7011 opcode(Assembler::mulx_op3, Assembler::arith_op);
7012 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7013 ins_pipe(imul_reg_imm);
7014 %}
7015
7016 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7017 match(Set dst (MulL src1 src2));
7018 ins_cost(DEFAULT_COST * 5);
7019 size(4);
7020 format %{ "MULX $src1,$src2,$dst\t! long" %}
7021 opcode(Assembler::mulx_op3, Assembler::arith_op);
7022 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7023 ins_pipe(mulL_reg_reg);
7024 %}
7025
7026 // Immediate Multiplication
7027 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7028 match(Set dst (MulL src1 src2));
7029 ins_cost(DEFAULT_COST * 5);
7030 size(4);
7031 format %{ "MULX $src1,$src2,$dst" %}
7032 opcode(Assembler::mulx_op3, Assembler::arith_op);
7033 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7034 ins_pipe(mulL_reg_imm);
7035 %}
7036
7037 // Integer Division
7038 // Register Division
7039 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7040 match(Set dst (DivI src1 src2));
7041 ins_cost((2+71)*DEFAULT_COST);
7042
7043 format %{ "SRA $src2,0,$src2\n\t"
7044 "SRA $src1,0,$src1\n\t"
7045 "SDIVX $src1,$src2,$dst" %}
7046 ins_encode( idiv_reg( src1, src2, dst ) );
7047 ins_pipe(sdiv_reg_reg);
7048 %}
7049
7050 // Immediate Division
7051 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7052 match(Set dst (DivI src1 src2));
7053 ins_cost((2+71)*DEFAULT_COST);
7054
7055 format %{ "SRA $src1,0,$src1\n\t"
7056 "SDIVX $src1,$src2,$dst" %}
7057 ins_encode( idiv_imm( src1, src2, dst ) );
7058 ins_pipe(sdiv_reg_imm);
7059 %}
7060
7061 //----------Div-By-10-Expansion------------------------------------------------
7062 // Extract hi bits of a 32x32->64 bit multiply.
7063 // Expand rule only, not matched
7064 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7065 effect( DEF dst, USE src1, USE src2 );
7066 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7067 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7068 ins_encode( enc_mul_hi(dst,src1,src2));
7069 ins_pipe(sdiv_reg_reg);
7070 %}
7071
7072 // Magic constant, reciprocal of 10
7073 instruct loadConI_x66666667(iRegIsafe dst) %{
7074 effect( DEF dst );
7075
7076 size(8);
7077 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7078 ins_encode( Set32(0x66666667, dst) );
7079 ins_pipe(ialu_hi_lo_reg);
7080 %}
7081
7082 // Register Shift Right Arithmetic Long by 32-63
7083 instruct sra_31( iRegI dst, iRegI src ) %{
7084 effect( DEF dst, USE src );
7085 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7086 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7087 ins_pipe(ialu_reg_reg);
7088 %}
7089
7090 // Arithmetic Shift Right by 8-bit immediate
7091 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7092 effect( DEF dst, USE src );
7093 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7094 opcode(Assembler::sra_op3, Assembler::arith_op);
7095 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7096 ins_pipe(ialu_reg_imm);
7097 %}
7098
7099 // Integer DIV with 10
7100 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7101 match(Set dst (DivI src div));
7102 ins_cost((6+6)*DEFAULT_COST);
7103 expand %{
7104 iRegIsafe tmp1; // Killed temps;
7105 iRegIsafe tmp2; // Killed temps;
7106 iRegI tmp3; // Killed temps;
7107 iRegI tmp4; // Killed temps;
7108 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7109 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7110 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7111 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7112 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7113 %}
7114 %}
7115
7116 // Register Long Division
7117 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7118 match(Set dst (DivL src1 src2));
7119 ins_cost(DEFAULT_COST*71);
7120 size(4);
7121 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7122 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7123 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7124 ins_pipe(divL_reg_reg);
7125 %}
7126
7127 // Register Long Division
7128 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7129 match(Set dst (DivL src1 src2));
7130 ins_cost(DEFAULT_COST*71);
7131 size(4);
7132 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7133 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7134 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7135 ins_pipe(divL_reg_imm);
7136 %}
7137
7138 // Integer Remainder
7139 // Register Remainder
7140 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7141 match(Set dst (ModI src1 src2));
7142 effect( KILL ccr, KILL temp);
7143
7144 format %{ "SREM $src1,$src2,$dst" %}
7145 ins_encode( irem_reg(src1, src2, dst, temp) );
7146 ins_pipe(sdiv_reg_reg);
7147 %}
7148
7149 // Immediate Remainder
7150 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7151 match(Set dst (ModI src1 src2));
7152 effect( KILL ccr, KILL temp);
7153
7154 format %{ "SREM $src1,$src2,$dst" %}
7155 ins_encode( irem_imm(src1, src2, dst, temp) );
7156 ins_pipe(sdiv_reg_imm);
7157 %}
7158
7159 // Register Long Remainder
7160 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7161 effect(DEF dst, USE src1, USE src2);
7162 size(4);
7163 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7164 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7165 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7166 ins_pipe(divL_reg_reg);
7167 %}
7168
7169 // Register Long Division
7170 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7171 effect(DEF dst, USE src1, USE src2);
7172 size(4);
7173 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7174 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7175 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7176 ins_pipe(divL_reg_imm);
7177 %}
7178
7179 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7180 effect(DEF dst, USE src1, USE src2);
7181 size(4);
7182 format %{ "MULX $src1,$src2,$dst\t! long" %}
7183 opcode(Assembler::mulx_op3, Assembler::arith_op);
7184 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7185 ins_pipe(mulL_reg_reg);
7186 %}
7187
7188 // Immediate Multiplication
7189 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7190 effect(DEF dst, USE src1, USE src2);
7191 size(4);
7192 format %{ "MULX $src1,$src2,$dst" %}
7193 opcode(Assembler::mulx_op3, Assembler::arith_op);
7194 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7195 ins_pipe(mulL_reg_imm);
7196 %}
7197
7198 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7199 effect(DEF dst, USE src1, USE src2);
7200 size(4);
7201 format %{ "SUB $src1,$src2,$dst\t! long" %}
7202 opcode(Assembler::sub_op3, Assembler::arith_op);
7203 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7204 ins_pipe(ialu_reg_reg);
7205 %}
7206
7207 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7208 effect(DEF dst, USE src1, USE src2);
7209 size(4);
7210 format %{ "SUB $src1,$src2,$dst\t! long" %}
7211 opcode(Assembler::sub_op3, Assembler::arith_op);
7212 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7213 ins_pipe(ialu_reg_reg);
7214 %}
7215
7216 // Register Long Remainder
7217 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7218 match(Set dst (ModL src1 src2));
7219 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7220 expand %{
7221 iRegL tmp1;
7222 iRegL tmp2;
7223 divL_reg_reg_1(tmp1, src1, src2);
7224 mulL_reg_reg_1(tmp2, tmp1, src2);
7225 subL_reg_reg_1(dst, src1, tmp2);
7226 %}
7227 %}
7228
7229 // Register Long Remainder
7230 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7231 match(Set dst (ModL src1 src2));
7232 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7233 expand %{
7234 iRegL tmp1;
7235 iRegL tmp2;
7236 divL_reg_imm13_1(tmp1, src1, src2);
7237 mulL_reg_imm13_1(tmp2, tmp1, src2);
7238 subL_reg_reg_2 (dst, src1, tmp2);
7239 %}
7240 %}
7241
7242 // Integer Shift Instructions
7243 // Register Shift Left
7244 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7245 match(Set dst (LShiftI src1 src2));
7246
7247 size(4);
7248 format %{ "SLL $src1,$src2,$dst" %}
7249 opcode(Assembler::sll_op3, Assembler::arith_op);
7250 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7251 ins_pipe(ialu_reg_reg);
7252 %}
7253
7254 // Register Shift Left Immediate
7255 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7256 match(Set dst (LShiftI src1 src2));
7257
7258 size(4);
7259 format %{ "SLL $src1,$src2,$dst" %}
7260 opcode(Assembler::sll_op3, Assembler::arith_op);
7261 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7262 ins_pipe(ialu_reg_imm);
7263 %}
7264
7265 // Register Shift Left
7266 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7267 match(Set dst (LShiftL src1 src2));
7268
7269 size(4);
7270 format %{ "SLLX $src1,$src2,$dst" %}
7271 opcode(Assembler::sllx_op3, Assembler::arith_op);
7272 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7273 ins_pipe(ialu_reg_reg);
7274 %}
7275
7276 // Register Shift Left Immediate
7277 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7278 match(Set dst (LShiftL src1 src2));
7279
7280 size(4);
7281 format %{ "SLLX $src1,$src2,$dst" %}
7282 opcode(Assembler::sllx_op3, Assembler::arith_op);
7283 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7284 ins_pipe(ialu_reg_imm);
7285 %}
7286
7287 // Register Arithmetic Shift Right
7288 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7289 match(Set dst (RShiftI src1 src2));
7290 size(4);
7291 format %{ "SRA $src1,$src2,$dst" %}
7292 opcode(Assembler::sra_op3, Assembler::arith_op);
7293 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7294 ins_pipe(ialu_reg_reg);
7295 %}
7296
7297 // Register Arithmetic Shift Right Immediate
7298 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7299 match(Set dst (RShiftI src1 src2));
7300
7301 size(4);
7302 format %{ "SRA $src1,$src2,$dst" %}
7303 opcode(Assembler::sra_op3, Assembler::arith_op);
7304 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7305 ins_pipe(ialu_reg_imm);
7306 %}
7307
7308 // Register Shift Right Arithmatic Long
7309 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7310 match(Set dst (RShiftL src1 src2));
7311
7312 size(4);
7313 format %{ "SRAX $src1,$src2,$dst" %}
7314 opcode(Assembler::srax_op3, Assembler::arith_op);
7315 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7316 ins_pipe(ialu_reg_reg);
7317 %}
7318
7319 // Register Shift Left Immediate
7320 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7321 match(Set dst (RShiftL src1 src2));
7322
7323 size(4);
7324 format %{ "SRAX $src1,$src2,$dst" %}
7325 opcode(Assembler::srax_op3, Assembler::arith_op);
7326 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7327 ins_pipe(ialu_reg_imm);
7328 %}
7329
7330 // Register Shift Right
7331 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7332 match(Set dst (URShiftI src1 src2));
7333
7334 size(4);
7335 format %{ "SRL $src1,$src2,$dst" %}
7336 opcode(Assembler::srl_op3, Assembler::arith_op);
7337 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7338 ins_pipe(ialu_reg_reg);
7339 %}
7340
7341 // Register Shift Right Immediate
7342 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7343 match(Set dst (URShiftI src1 src2));
7344
7345 size(4);
7346 format %{ "SRL $src1,$src2,$dst" %}
7347 opcode(Assembler::srl_op3, Assembler::arith_op);
7348 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7349 ins_pipe(ialu_reg_imm);
7350 %}
7351
7352 // Register Shift Right
7353 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7354 match(Set dst (URShiftL src1 src2));
7355
7356 size(4);
7357 format %{ "SRLX $src1,$src2,$dst" %}
7358 opcode(Assembler::srlx_op3, Assembler::arith_op);
7359 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7360 ins_pipe(ialu_reg_reg);
7361 %}
7362
7363 // Register Shift Right Immediate
7364 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7365 match(Set dst (URShiftL src1 src2));
7366
7367 size(4);
7368 format %{ "SRLX $src1,$src2,$dst" %}
7369 opcode(Assembler::srlx_op3, Assembler::arith_op);
7370 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7371 ins_pipe(ialu_reg_imm);
7372 %}
7373
7374 // Register Shift Right Immediate with a CastP2X
7375 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7376 match(Set dst (URShiftL (CastP2X src1) src2));
7377 size(4);
7378 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7379 opcode(Assembler::srlx_op3, Assembler::arith_op);
7380 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7381 ins_pipe(ialu_reg_imm);
7382 %}
7383
7384
7385 //----------Floating Point Arithmetic Instructions-----------------------------
7386
7387 // Add float single precision
7388 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7389 match(Set dst (AddF src1 src2));
7390
7391 size(4);
7392 format %{ "FADDS $src1,$src2,$dst" %}
7393 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7394 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7395 ins_pipe(faddF_reg_reg);
7396 %}
7397
7398 // Add float double precision
7399 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7400 match(Set dst (AddD src1 src2));
7401
7402 size(4);
7403 format %{ "FADDD $src1,$src2,$dst" %}
7404 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7405 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7406 ins_pipe(faddD_reg_reg);
7407 %}
7408
7409 // Sub float single precision
7410 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7411 match(Set dst (SubF src1 src2));
7412
7413 size(4);
7414 format %{ "FSUBS $src1,$src2,$dst" %}
7415 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7416 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7417 ins_pipe(faddF_reg_reg);
7418 %}
7419
7420 // Sub float double precision
7421 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7422 match(Set dst (SubD src1 src2));
7423
7424 size(4);
7425 format %{ "FSUBD $src1,$src2,$dst" %}
7426 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7427 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7428 ins_pipe(faddD_reg_reg);
7429 %}
7430
7431 // Mul float single precision
7432 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7433 match(Set dst (MulF src1 src2));
7434
7435 size(4);
7436 format %{ "FMULS $src1,$src2,$dst" %}
7437 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7438 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7439 ins_pipe(fmulF_reg_reg);
7440 %}
7441
7442 // Mul float double precision
7443 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7444 match(Set dst (MulD src1 src2));
7445
7446 size(4);
7447 format %{ "FMULD $src1,$src2,$dst" %}
7448 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7449 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7450 ins_pipe(fmulD_reg_reg);
7451 %}
7452
7453 // Div float single precision
7454 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7455 match(Set dst (DivF src1 src2));
7456
7457 size(4);
7458 format %{ "FDIVS $src1,$src2,$dst" %}
7459 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7460 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7461 ins_pipe(fdivF_reg_reg);
7462 %}
7463
7464 // Div float double precision
7465 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7466 match(Set dst (DivD src1 src2));
7467
7468 size(4);
7469 format %{ "FDIVD $src1,$src2,$dst" %}
7470 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7471 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7472 ins_pipe(fdivD_reg_reg);
7473 %}
7474
7475 // Absolute float double precision
7476 instruct absD_reg(regD dst, regD src) %{
7477 match(Set dst (AbsD src));
7478
7479 format %{ "FABSd $src,$dst" %}
7480 ins_encode(fabsd(dst, src));
7481 ins_pipe(faddD_reg);
7482 %}
7483
7484 // Absolute float single precision
7485 instruct absF_reg(regF dst, regF src) %{
7486 match(Set dst (AbsF src));
7487
7488 format %{ "FABSs $src,$dst" %}
7489 ins_encode(fabss(dst, src));
7490 ins_pipe(faddF_reg);
7491 %}
7492
7493 instruct negF_reg(regF dst, regF src) %{
7494 match(Set dst (NegF src));
7495
7496 size(4);
7497 format %{ "FNEGs $src,$dst" %}
7498 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7499 ins_encode(form3_opf_rs2F_rdF(src, dst));
7500 ins_pipe(faddF_reg);
7501 %}
7502
7503 instruct negD_reg(regD dst, regD src) %{
7504 match(Set dst (NegD src));
7505
7506 format %{ "FNEGd $src,$dst" %}
7507 ins_encode(fnegd(dst, src));
7508 ins_pipe(faddD_reg);
7509 %}
7510
7511 // Sqrt float double precision
7512 instruct sqrtF_reg_reg(regF dst, regF src) %{
7513 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7514
7515 size(4);
7516 format %{ "FSQRTS $src,$dst" %}
7517 ins_encode(fsqrts(dst, src));
7518 ins_pipe(fdivF_reg_reg);
7519 %}
7520
7521 // Sqrt float double precision
7522 instruct sqrtD_reg_reg(regD dst, regD src) %{
7523 match(Set dst (SqrtD src));
7524
7525 size(4);
7526 format %{ "FSQRTD $src,$dst" %}
7527 ins_encode(fsqrtd(dst, src));
7528 ins_pipe(fdivD_reg_reg);
7529 %}
7530
7531 //----------Logical Instructions-----------------------------------------------
7532 // And Instructions
7533 // Register And
7534 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7535 match(Set dst (AndI src1 src2));
7536
7537 size(4);
7538 format %{ "AND $src1,$src2,$dst" %}
7539 opcode(Assembler::and_op3, Assembler::arith_op);
7540 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7541 ins_pipe(ialu_reg_reg);
7542 %}
7543
7544 // Immediate And
7545 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7546 match(Set dst (AndI src1 src2));
7547
7548 size(4);
7549 format %{ "AND $src1,$src2,$dst" %}
7550 opcode(Assembler::and_op3, Assembler::arith_op);
7551 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7552 ins_pipe(ialu_reg_imm);
7553 %}
7554
7555 // Register And Long
7556 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7557 match(Set dst (AndL src1 src2));
7558
7559 ins_cost(DEFAULT_COST);
7560 size(4);
7561 format %{ "AND $src1,$src2,$dst\t! long" %}
7562 opcode(Assembler::and_op3, Assembler::arith_op);
7563 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7564 ins_pipe(ialu_reg_reg);
7565 %}
7566
7567 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7568 match(Set dst (AndL src1 con));
7569
7570 ins_cost(DEFAULT_COST);
7571 size(4);
7572 format %{ "AND $src1,$con,$dst\t! long" %}
7573 opcode(Assembler::and_op3, Assembler::arith_op);
7574 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7575 ins_pipe(ialu_reg_imm);
7576 %}
7577
7578 // Or Instructions
7579 // Register Or
7580 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7581 match(Set dst (OrI src1 src2));
7582
7583 size(4);
7584 format %{ "OR $src1,$src2,$dst" %}
7585 opcode(Assembler::or_op3, Assembler::arith_op);
7586 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7587 ins_pipe(ialu_reg_reg);
7588 %}
7589
7590 // Immediate Or
7591 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7592 match(Set dst (OrI src1 src2));
7593
7594 size(4);
7595 format %{ "OR $src1,$src2,$dst" %}
7596 opcode(Assembler::or_op3, Assembler::arith_op);
7597 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7598 ins_pipe(ialu_reg_imm);
7599 %}
7600
7601 // Register Or Long
7602 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7603 match(Set dst (OrL src1 src2));
7604
7605 ins_cost(DEFAULT_COST);
7606 size(4);
7607 format %{ "OR $src1,$src2,$dst\t! long" %}
7608 opcode(Assembler::or_op3, Assembler::arith_op);
7609 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7610 ins_pipe(ialu_reg_reg);
7611 %}
7612
7613 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7614 match(Set dst (OrL src1 con));
7615 ins_cost(DEFAULT_COST*2);
7616
7617 ins_cost(DEFAULT_COST);
7618 size(4);
7619 format %{ "OR $src1,$con,$dst\t! long" %}
7620 opcode(Assembler::or_op3, Assembler::arith_op);
7621 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7622 ins_pipe(ialu_reg_imm);
7623 %}
7624
7625 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7626 match(Set dst (OrL src1 (CastP2X src2)));
7627
7628 ins_cost(DEFAULT_COST);
7629 size(4);
7630 format %{ "OR $src1,$src2,$dst\t! long" %}
7631 opcode(Assembler::or_op3, Assembler::arith_op);
7632 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7633 ins_pipe(ialu_reg_reg);
7634 %}
7635
7636 // Xor Instructions
7637 // Register Xor
7638 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7639 match(Set dst (XorI src1 src2));
7640
7641 size(4);
7642 format %{ "XOR $src1,$src2,$dst" %}
7643 opcode(Assembler::xor_op3, Assembler::arith_op);
7644 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7645 ins_pipe(ialu_reg_reg);
7646 %}
7647
7648 // Immediate Xor
7649 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7650 match(Set dst (XorI src1 src2));
7651
7652 size(4);
7653 format %{ "XOR $src1,$src2,$dst" %}
7654 opcode(Assembler::xor_op3, Assembler::arith_op);
7655 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7656 ins_pipe(ialu_reg_imm);
7657 %}
7658
7659 // Register Xor Long
7660 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7661 match(Set dst (XorL src1 src2));
7662
7663 ins_cost(DEFAULT_COST);
7664 size(4);
7665 format %{ "XOR $src1,$src2,$dst\t! long" %}
7666 opcode(Assembler::xor_op3, Assembler::arith_op);
7667 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7668 ins_pipe(ialu_reg_reg);
7669 %}
7670
7671 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7672 match(Set dst (XorL src1 con));
7673
7674 ins_cost(DEFAULT_COST);
7675 size(4);
7676 format %{ "XOR $src1,$con,$dst\t! long" %}
7677 opcode(Assembler::xor_op3, Assembler::arith_op);
7678 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7679 ins_pipe(ialu_reg_imm);
7680 %}
7681
7682 //----------Convert to Boolean-------------------------------------------------
7683 // Nice hack for 32-bit tests but doesn't work for
7684 // 64-bit pointers.
7685 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7686 match(Set dst (Conv2B src));
7687 effect( KILL ccr );
7688 ins_cost(DEFAULT_COST*2);
7689 format %{ "CMP R_G0,$src\n\t"
7690 "ADDX R_G0,0,$dst" %}
7691 ins_encode( enc_to_bool( src, dst ) );
7692 ins_pipe(ialu_reg_ialu);
7693 %}
7694
7695 instruct convP2B( iRegI dst, iRegP src ) %{
7696 match(Set dst (Conv2B src));
7697 ins_cost(DEFAULT_COST*2);
7698 format %{ "MOV $src,$dst\n\t"
7699 "MOVRNZ $src,1,$dst" %}
7700 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
7701 ins_pipe(ialu_clr_and_mover);
7702 %}
7703
7704 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
7705 match(Set dst (CmpLTMask src zero));
7706 effect(KILL ccr);
7707 size(4);
7708 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
7709 ins_encode %{
7710 __ sra($src$$Register, 31, $dst$$Register);
7711 %}
7712 ins_pipe(ialu_reg_imm);
7713 %}
7714
7715 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
7716 match(Set dst (CmpLTMask p q));
7717 effect( KILL ccr );
7718 ins_cost(DEFAULT_COST*4);
7719 format %{ "CMP $p,$q\n\t"
7720 "MOV #0,$dst\n\t"
7721 "BLT,a .+8\n\t"
7722 "MOV #-1,$dst" %}
7723 ins_encode( enc_ltmask(p,q,dst) );
7724 ins_pipe(ialu_reg_reg_ialu);
7725 %}
7726
7727 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7728 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
7729 effect(KILL ccr, TEMP tmp);
7730 ins_cost(DEFAULT_COST*3);
7731
7732 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7733 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7734 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7735 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
7736 ins_pipe(cadd_cmpltmask);
7737 %}
7738
7739 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
7740 match(Set p (AndI (CmpLTMask p q) y));
7741 effect(KILL ccr);
7742 ins_cost(DEFAULT_COST*3);
7743
7744 format %{ "CMP $p,$q\n\t"
7745 "MOV $y,$p\n\t"
7746 "MOVge G0,$p" %}
7747 ins_encode %{
7748 __ cmp($p$$Register, $q$$Register);
7749 __ mov($y$$Register, $p$$Register);
7750 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
7751 %}
7752 ins_pipe(ialu_reg_reg_ialu);
7753 %}
7754
7755 //-----------------------------------------------------------------
7756 // Direct raw moves between float and general registers using VIS3.
7757
7758 // ins_pipe(faddF_reg);
7759 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
7760 predicate(UseVIS >= 3);
7761 match(Set dst (MoveF2I src));
7762
7763 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
7764 ins_encode %{
7765 __ movstouw($src$$FloatRegister, $dst$$Register);
7766 %}
7767 ins_pipe(ialu_reg_reg);
7768 %}
7769
7770 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
7771 predicate(UseVIS >= 3);
7772 match(Set dst (MoveI2F src));
7773
7774 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
7775 ins_encode %{
7776 __ movwtos($src$$Register, $dst$$FloatRegister);
7777 %}
7778 ins_pipe(ialu_reg_reg);
7779 %}
7780
7781 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
7782 predicate(UseVIS >= 3);
7783 match(Set dst (MoveD2L src));
7784
7785 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
7786 ins_encode %{
7787 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
7788 %}
7789 ins_pipe(ialu_reg_reg);
7790 %}
7791
7792 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
7793 predicate(UseVIS >= 3);
7794 match(Set dst (MoveL2D src));
7795
7796 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
7797 ins_encode %{
7798 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
7799 %}
7800 ins_pipe(ialu_reg_reg);
7801 %}
7802
7803
7804 // Raw moves between float and general registers using stack.
7805
7806 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
7807 match(Set dst (MoveF2I src));
7808 effect(DEF dst, USE src);
7809 ins_cost(MEMORY_REF_COST);
7810
7811 format %{ "LDUW $src,$dst\t! MoveF2I" %}
7812 opcode(Assembler::lduw_op3);
7813 ins_encode(simple_form3_mem_reg( src, dst ) );
7814 ins_pipe(iload_mem);
7815 %}
7816
7817 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
7818 match(Set dst (MoveI2F src));
7819 effect(DEF dst, USE src);
7820 ins_cost(MEMORY_REF_COST);
7821
7822 format %{ "LDF $src,$dst\t! MoveI2F" %}
7823 opcode(Assembler::ldf_op3);
7824 ins_encode(simple_form3_mem_reg(src, dst));
7825 ins_pipe(floadF_stk);
7826 %}
7827
7828 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
7829 match(Set dst (MoveD2L src));
7830 effect(DEF dst, USE src);
7831 ins_cost(MEMORY_REF_COST);
7832
7833 format %{ "LDX $src,$dst\t! MoveD2L" %}
7834 opcode(Assembler::ldx_op3);
7835 ins_encode(simple_form3_mem_reg( src, dst ) );
7836 ins_pipe(iload_mem);
7837 %}
7838
7839 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
7840 match(Set dst (MoveL2D src));
7841 effect(DEF dst, USE src);
7842 ins_cost(MEMORY_REF_COST);
7843
7844 format %{ "LDDF $src,$dst\t! MoveL2D" %}
7845 opcode(Assembler::lddf_op3);
7846 ins_encode(simple_form3_mem_reg(src, dst));
7847 ins_pipe(floadD_stk);
7848 %}
7849
7850 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
7851 match(Set dst (MoveF2I src));
7852 effect(DEF dst, USE src);
7853 ins_cost(MEMORY_REF_COST);
7854
7855 format %{ "STF $src,$dst\t! MoveF2I" %}
7856 opcode(Assembler::stf_op3);
7857 ins_encode(simple_form3_mem_reg(dst, src));
7858 ins_pipe(fstoreF_stk_reg);
7859 %}
7860
7861 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
7862 match(Set dst (MoveI2F src));
7863 effect(DEF dst, USE src);
7864 ins_cost(MEMORY_REF_COST);
7865
7866 format %{ "STW $src,$dst\t! MoveI2F" %}
7867 opcode(Assembler::stw_op3);
7868 ins_encode(simple_form3_mem_reg( dst, src ) );
7869 ins_pipe(istore_mem_reg);
7870 %}
7871
7872 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
7873 match(Set dst (MoveD2L src));
7874 effect(DEF dst, USE src);
7875 ins_cost(MEMORY_REF_COST);
7876
7877 format %{ "STDF $src,$dst\t! MoveD2L" %}
7878 opcode(Assembler::stdf_op3);
7879 ins_encode(simple_form3_mem_reg(dst, src));
7880 ins_pipe(fstoreD_stk_reg);
7881 %}
7882
7883 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
7884 match(Set dst (MoveL2D src));
7885 effect(DEF dst, USE src);
7886 ins_cost(MEMORY_REF_COST);
7887
7888 format %{ "STX $src,$dst\t! MoveL2D" %}
7889 opcode(Assembler::stx_op3);
7890 ins_encode(simple_form3_mem_reg( dst, src ) );
7891 ins_pipe(istore_mem_reg);
7892 %}
7893
7894
7895 //----------Arithmetic Conversion Instructions---------------------------------
7896 // The conversions operations are all Alpha sorted. Please keep it that way!
7897
7898 instruct convD2F_reg(regF dst, regD src) %{
7899 match(Set dst (ConvD2F src));
7900 size(4);
7901 format %{ "FDTOS $src,$dst" %}
7902 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
7903 ins_encode(form3_opf_rs2D_rdF(src, dst));
7904 ins_pipe(fcvtD2F);
7905 %}
7906
7907
7908 // Convert a double to an int in a float register.
7909 // If the double is a NAN, stuff a zero in instead.
7910 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
7911 effect(DEF dst, USE src, KILL fcc0);
7912 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7913 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7914 "FDTOI $src,$dst\t! convert in delay slot\n\t"
7915 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7916 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
7917 "skip:" %}
7918 ins_encode(form_d2i_helper(src,dst));
7919 ins_pipe(fcvtD2I);
7920 %}
7921
7922 instruct convD2I_stk(stackSlotI dst, regD src) %{
7923 match(Set dst (ConvD2I src));
7924 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7925 expand %{
7926 regF tmp;
7927 convD2I_helper(tmp, src);
7928 regF_to_stkI(dst, tmp);
7929 %}
7930 %}
7931
7932 instruct convD2I_reg(iRegI dst, regD src) %{
7933 predicate(UseVIS >= 3);
7934 match(Set dst (ConvD2I src));
7935 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
7936 expand %{
7937 regF tmp;
7938 convD2I_helper(tmp, src);
7939 MoveF2I_reg_reg(dst, tmp);
7940 %}
7941 %}
7942
7943
7944 // Convert a double to a long in a double register.
7945 // If the double is a NAN, stuff a zero in instead.
7946 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
7947 effect(DEF dst, USE src, KILL fcc0);
7948 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7949 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7950 "FDTOX $src,$dst\t! convert in delay slot\n\t"
7951 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
7952 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
7953 "skip:" %}
7954 ins_encode(form_d2l_helper(src,dst));
7955 ins_pipe(fcvtD2L);
7956 %}
7957
7958 instruct convD2L_stk(stackSlotL dst, regD src) %{
7959 match(Set dst (ConvD2L src));
7960 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7961 expand %{
7962 regD tmp;
7963 convD2L_helper(tmp, src);
7964 regD_to_stkL(dst, tmp);
7965 %}
7966 %}
7967
7968 instruct convD2L_reg(iRegL dst, regD src) %{
7969 predicate(UseVIS >= 3);
7970 match(Set dst (ConvD2L src));
7971 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
7972 expand %{
7973 regD tmp;
7974 convD2L_helper(tmp, src);
7975 MoveD2L_reg_reg(dst, tmp);
7976 %}
7977 %}
7978
7979
7980 instruct convF2D_reg(regD dst, regF src) %{
7981 match(Set dst (ConvF2D src));
7982 format %{ "FSTOD $src,$dst" %}
7983 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
7984 ins_encode(form3_opf_rs2F_rdD(src, dst));
7985 ins_pipe(fcvtF2D);
7986 %}
7987
7988
7989 // Convert a float to an int in a float register.
7990 // If the float is a NAN, stuff a zero in instead.
7991 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
7992 effect(DEF dst, USE src, KILL fcc0);
7993 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
7994 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7995 "FSTOI $src,$dst\t! convert in delay slot\n\t"
7996 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7997 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
7998 "skip:" %}
7999 ins_encode(form_f2i_helper(src,dst));
8000 ins_pipe(fcvtF2I);
8001 %}
8002
8003 instruct convF2I_stk(stackSlotI dst, regF src) %{
8004 match(Set dst (ConvF2I src));
8005 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8006 expand %{
8007 regF tmp;
8008 convF2I_helper(tmp, src);
8009 regF_to_stkI(dst, tmp);
8010 %}
8011 %}
8012
8013 instruct convF2I_reg(iRegI dst, regF src) %{
8014 predicate(UseVIS >= 3);
8015 match(Set dst (ConvF2I src));
8016 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8017 expand %{
8018 regF tmp;
8019 convF2I_helper(tmp, src);
8020 MoveF2I_reg_reg(dst, tmp);
8021 %}
8022 %}
8023
8024
8025 // Convert a float to a long in a float register.
8026 // If the float is a NAN, stuff a zero in instead.
8027 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8028 effect(DEF dst, USE src, KILL fcc0);
8029 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8030 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8031 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8032 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8033 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8034 "skip:" %}
8035 ins_encode(form_f2l_helper(src,dst));
8036 ins_pipe(fcvtF2L);
8037 %}
8038
8039 instruct convF2L_stk(stackSlotL dst, regF src) %{
8040 match(Set dst (ConvF2L src));
8041 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8042 expand %{
8043 regD tmp;
8044 convF2L_helper(tmp, src);
8045 regD_to_stkL(dst, tmp);
8046 %}
8047 %}
8048
8049 instruct convF2L_reg(iRegL dst, regF src) %{
8050 predicate(UseVIS >= 3);
8051 match(Set dst (ConvF2L src));
8052 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8053 expand %{
8054 regD tmp;
8055 convF2L_helper(tmp, src);
8056 MoveD2L_reg_reg(dst, tmp);
8057 %}
8058 %}
8059
8060
8061 instruct convI2D_helper(regD dst, regF tmp) %{
8062 effect(USE tmp, DEF dst);
8063 format %{ "FITOD $tmp,$dst" %}
8064 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8065 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8066 ins_pipe(fcvtI2D);
8067 %}
8068
8069 instruct convI2D_stk(stackSlotI src, regD dst) %{
8070 match(Set dst (ConvI2D src));
8071 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8072 expand %{
8073 regF tmp;
8074 stkI_to_regF(tmp, src);
8075 convI2D_helper(dst, tmp);
8076 %}
8077 %}
8078
8079 instruct convI2D_reg(regD_low dst, iRegI src) %{
8080 predicate(UseVIS >= 3);
8081 match(Set dst (ConvI2D src));
8082 expand %{
8083 regF tmp;
8084 MoveI2F_reg_reg(tmp, src);
8085 convI2D_helper(dst, tmp);
8086 %}
8087 %}
8088
8089 instruct convI2D_mem(regD_low dst, memory mem) %{
8090 match(Set dst (ConvI2D (LoadI mem)));
8091 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8092 format %{ "LDF $mem,$dst\n\t"
8093 "FITOD $dst,$dst" %}
8094 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8095 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8096 ins_pipe(floadF_mem);
8097 %}
8098
8099
8100 instruct convI2F_helper(regF dst, regF tmp) %{
8101 effect(DEF dst, USE tmp);
8102 format %{ "FITOS $tmp,$dst" %}
8103 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8104 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8105 ins_pipe(fcvtI2F);
8106 %}
8107
8108 instruct convI2F_stk(regF dst, stackSlotI src) %{
8109 match(Set dst (ConvI2F src));
8110 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8111 expand %{
8112 regF tmp;
8113 stkI_to_regF(tmp,src);
8114 convI2F_helper(dst, tmp);
8115 %}
8116 %}
8117
8118 instruct convI2F_reg(regF dst, iRegI src) %{
8119 predicate(UseVIS >= 3);
8120 match(Set dst (ConvI2F src));
8121 ins_cost(DEFAULT_COST);
8122 expand %{
8123 regF tmp;
8124 MoveI2F_reg_reg(tmp, src);
8125 convI2F_helper(dst, tmp);
8126 %}
8127 %}
8128
8129 instruct convI2F_mem( regF dst, memory mem ) %{
8130 match(Set dst (ConvI2F (LoadI mem)));
8131 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8132 format %{ "LDF $mem,$dst\n\t"
8133 "FITOS $dst,$dst" %}
8134 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8135 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8136 ins_pipe(floadF_mem);
8137 %}
8138
8139
8140 instruct convI2L_reg(iRegL dst, iRegI src) %{
8141 match(Set dst (ConvI2L src));
8142 size(4);
8143 format %{ "SRA $src,0,$dst\t! int->long" %}
8144 opcode(Assembler::sra_op3, Assembler::arith_op);
8145 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8146 ins_pipe(ialu_reg_reg);
8147 %}
8148
8149 // Zero-extend convert int to long
8150 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8151 match(Set dst (AndL (ConvI2L src) mask) );
8152 size(4);
8153 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8154 opcode(Assembler::srl_op3, Assembler::arith_op);
8155 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8156 ins_pipe(ialu_reg_reg);
8157 %}
8158
8159 // Zero-extend long
8160 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8161 match(Set dst (AndL src mask) );
8162 size(4);
8163 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8164 opcode(Assembler::srl_op3, Assembler::arith_op);
8165 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8166 ins_pipe(ialu_reg_reg);
8167 %}
8168
8169
8170 //-----------
8171 // Long to Double conversion using V8 opcodes.
8172 // Still useful because cheetah traps and becomes
8173 // amazingly slow for some common numbers.
8174
8175 // Magic constant, 0x43300000
8176 instruct loadConI_x43300000(iRegI dst) %{
8177 effect(DEF dst);
8178 size(4);
8179 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8180 ins_encode(SetHi22(0x43300000, dst));
8181 ins_pipe(ialu_none);
8182 %}
8183
8184 // Magic constant, 0x41f00000
8185 instruct loadConI_x41f00000(iRegI dst) %{
8186 effect(DEF dst);
8187 size(4);
8188 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8189 ins_encode(SetHi22(0x41f00000, dst));
8190 ins_pipe(ialu_none);
8191 %}
8192
8193 // Construct a double from two float halves
8194 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8195 effect(DEF dst, USE src1, USE src2);
8196 size(8);
8197 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8198 "FMOVS $src2.lo,$dst.lo" %}
8199 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8200 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8201 ins_pipe(faddD_reg_reg);
8202 %}
8203
8204 // Convert integer in high half of a double register (in the lower half of
8205 // the double register file) to double
8206 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8207 effect(DEF dst, USE src);
8208 size(4);
8209 format %{ "FITOD $src,$dst" %}
8210 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8211 ins_encode(form3_opf_rs2D_rdD(src, dst));
8212 ins_pipe(fcvtLHi2D);
8213 %}
8214
8215 // Add float double precision
8216 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8217 effect(DEF dst, USE src1, USE src2);
8218 size(4);
8219 format %{ "FADDD $src1,$src2,$dst" %}
8220 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8221 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8222 ins_pipe(faddD_reg_reg);
8223 %}
8224
8225 // Sub float double precision
8226 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8227 effect(DEF dst, USE src1, USE src2);
8228 size(4);
8229 format %{ "FSUBD $src1,$src2,$dst" %}
8230 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8231 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8232 ins_pipe(faddD_reg_reg);
8233 %}
8234
8235 // Mul float double precision
8236 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8237 effect(DEF dst, USE src1, USE src2);
8238 size(4);
8239 format %{ "FMULD $src1,$src2,$dst" %}
8240 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8241 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8242 ins_pipe(fmulD_reg_reg);
8243 %}
8244
8245 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8246 match(Set dst (ConvL2D src));
8247 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8248
8249 expand %{
8250 regD_low tmpsrc;
8251 iRegI ix43300000;
8252 iRegI ix41f00000;
8253 stackSlotL lx43300000;
8254 stackSlotL lx41f00000;
8255 regD_low dx43300000;
8256 regD dx41f00000;
8257 regD tmp1;
8258 regD_low tmp2;
8259 regD tmp3;
8260 regD tmp4;
8261
8262 stkL_to_regD(tmpsrc, src);
8263
8264 loadConI_x43300000(ix43300000);
8265 loadConI_x41f00000(ix41f00000);
8266 regI_to_stkLHi(lx43300000, ix43300000);
8267 regI_to_stkLHi(lx41f00000, ix41f00000);
8268 stkL_to_regD(dx43300000, lx43300000);
8269 stkL_to_regD(dx41f00000, lx41f00000);
8270
8271 convI2D_regDHi_regD(tmp1, tmpsrc);
8272 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8273 subD_regD_regD(tmp3, tmp2, dx43300000);
8274 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8275 addD_regD_regD(dst, tmp3, tmp4);
8276 %}
8277 %}
8278
8279 // Long to Double conversion using fast fxtof
8280 instruct convL2D_helper(regD dst, regD tmp) %{
8281 effect(DEF dst, USE tmp);
8282 size(4);
8283 format %{ "FXTOD $tmp,$dst" %}
8284 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8285 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8286 ins_pipe(fcvtL2D);
8287 %}
8288
8289 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8290 predicate(VM_Version::has_fast_fxtof());
8291 match(Set dst (ConvL2D src));
8292 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8293 expand %{
8294 regD tmp;
8295 stkL_to_regD(tmp, src);
8296 convL2D_helper(dst, tmp);
8297 %}
8298 %}
8299
8300 instruct convL2D_reg(regD dst, iRegL src) %{
8301 predicate(UseVIS >= 3);
8302 match(Set dst (ConvL2D src));
8303 expand %{
8304 regD tmp;
8305 MoveL2D_reg_reg(tmp, src);
8306 convL2D_helper(dst, tmp);
8307 %}
8308 %}
8309
8310 // Long to Float conversion using fast fxtof
8311 instruct convL2F_helper(regF dst, regD tmp) %{
8312 effect(DEF dst, USE tmp);
8313 size(4);
8314 format %{ "FXTOS $tmp,$dst" %}
8315 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8316 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8317 ins_pipe(fcvtL2F);
8318 %}
8319
8320 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8321 match(Set dst (ConvL2F src));
8322 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8323 expand %{
8324 regD tmp;
8325 stkL_to_regD(tmp, src);
8326 convL2F_helper(dst, tmp);
8327 %}
8328 %}
8329
8330 instruct convL2F_reg(regF dst, iRegL src) %{
8331 predicate(UseVIS >= 3);
8332 match(Set dst (ConvL2F src));
8333 ins_cost(DEFAULT_COST);
8334 expand %{
8335 regD tmp;
8336 MoveL2D_reg_reg(tmp, src);
8337 convL2F_helper(dst, tmp);
8338 %}
8339 %}
8340
8341 //-----------
8342
8343 instruct convL2I_reg(iRegI dst, iRegL src) %{
8344 match(Set dst (ConvL2I src));
8345 size(4);
8346 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8347 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8348 ins_pipe(ialu_reg);
8349 %}
8350
8351 // Register Shift Right Immediate
8352 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8353 match(Set dst (ConvL2I (RShiftL src cnt)));
8354
8355 size(4);
8356 format %{ "SRAX $src,$cnt,$dst" %}
8357 opcode(Assembler::srax_op3, Assembler::arith_op);
8358 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8359 ins_pipe(ialu_reg_imm);
8360 %}
8361
8362 //----------Control Flow Instructions------------------------------------------
8363 // Compare Instructions
8364 // Compare Integers
8365 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8366 match(Set icc (CmpI op1 op2));
8367 effect( DEF icc, USE op1, USE op2 );
8368
8369 size(4);
8370 format %{ "CMP $op1,$op2" %}
8371 opcode(Assembler::subcc_op3, Assembler::arith_op);
8372 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8373 ins_pipe(ialu_cconly_reg_reg);
8374 %}
8375
8376 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8377 match(Set icc (CmpU op1 op2));
8378
8379 size(4);
8380 format %{ "CMP $op1,$op2\t! unsigned" %}
8381 opcode(Assembler::subcc_op3, Assembler::arith_op);
8382 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8383 ins_pipe(ialu_cconly_reg_reg);
8384 %}
8385
8386 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8387 match(Set icc (CmpI op1 op2));
8388 effect( DEF icc, USE op1 );
8389
8390 size(4);
8391 format %{ "CMP $op1,$op2" %}
8392 opcode(Assembler::subcc_op3, Assembler::arith_op);
8393 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8394 ins_pipe(ialu_cconly_reg_imm);
8395 %}
8396
8397 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8398 match(Set icc (CmpI (AndI op1 op2) zero));
8399
8400 size(4);
8401 format %{ "BTST $op2,$op1" %}
8402 opcode(Assembler::andcc_op3, Assembler::arith_op);
8403 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8404 ins_pipe(ialu_cconly_reg_reg_zero);
8405 %}
8406
8407 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8408 match(Set icc (CmpI (AndI op1 op2) zero));
8409
8410 size(4);
8411 format %{ "BTST $op2,$op1" %}
8412 opcode(Assembler::andcc_op3, Assembler::arith_op);
8413 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8414 ins_pipe(ialu_cconly_reg_imm_zero);
8415 %}
8416
8417 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8418 match(Set xcc (CmpL op1 op2));
8419 effect( DEF xcc, USE op1, USE op2 );
8420
8421 size(4);
8422 format %{ "CMP $op1,$op2\t\t! long" %}
8423 opcode(Assembler::subcc_op3, Assembler::arith_op);
8424 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8425 ins_pipe(ialu_cconly_reg_reg);
8426 %}
8427
8428 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8429 match(Set xcc (CmpL op1 con));
8430 effect( DEF xcc, USE op1, USE con );
8431
8432 size(4);
8433 format %{ "CMP $op1,$con\t\t! long" %}
8434 opcode(Assembler::subcc_op3, Assembler::arith_op);
8435 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8436 ins_pipe(ialu_cconly_reg_reg);
8437 %}
8438
8439 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8440 match(Set xcc (CmpL (AndL op1 op2) zero));
8441 effect( DEF xcc, USE op1, USE op2 );
8442
8443 size(4);
8444 format %{ "BTST $op1,$op2\t\t! long" %}
8445 opcode(Assembler::andcc_op3, Assembler::arith_op);
8446 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8447 ins_pipe(ialu_cconly_reg_reg);
8448 %}
8449
8450 // useful for checking the alignment of a pointer:
8451 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8452 match(Set xcc (CmpL (AndL op1 con) zero));
8453 effect( DEF xcc, USE op1, USE con );
8454
8455 size(4);
8456 format %{ "BTST $op1,$con\t\t! long" %}
8457 opcode(Assembler::andcc_op3, Assembler::arith_op);
8458 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8459 ins_pipe(ialu_cconly_reg_reg);
8460 %}
8461
8462 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8463 match(Set icc (CmpU op1 op2));
8464
8465 size(4);
8466 format %{ "CMP $op1,$op2\t! unsigned" %}
8467 opcode(Assembler::subcc_op3, Assembler::arith_op);
8468 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8469 ins_pipe(ialu_cconly_reg_imm);
8470 %}
8471
8472 // Compare Pointers
8473 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8474 match(Set pcc (CmpP op1 op2));
8475
8476 size(4);
8477 format %{ "CMP $op1,$op2\t! ptr" %}
8478 opcode(Assembler::subcc_op3, Assembler::arith_op);
8479 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8480 ins_pipe(ialu_cconly_reg_reg);
8481 %}
8482
8483 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8484 match(Set pcc (CmpP op1 op2));
8485
8486 size(4);
8487 format %{ "CMP $op1,$op2\t! ptr" %}
8488 opcode(Assembler::subcc_op3, Assembler::arith_op);
8489 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8490 ins_pipe(ialu_cconly_reg_imm);
8491 %}
8492
8493 // Compare Narrow oops
8494 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8495 match(Set icc (CmpN op1 op2));
8496
8497 size(4);
8498 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8499 opcode(Assembler::subcc_op3, Assembler::arith_op);
8500 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8501 ins_pipe(ialu_cconly_reg_reg);
8502 %}
8503
8504 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8505 match(Set icc (CmpN op1 op2));
8506
8507 size(4);
8508 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8509 opcode(Assembler::subcc_op3, Assembler::arith_op);
8510 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8511 ins_pipe(ialu_cconly_reg_imm);
8512 %}
8513
8514 //----------Max and Min--------------------------------------------------------
8515 // Min Instructions
8516 // Conditional move for min
8517 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8518 effect( USE_DEF op2, USE op1, USE icc );
8519
8520 size(4);
8521 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8522 opcode(Assembler::less);
8523 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8524 ins_pipe(ialu_reg_flags);
8525 %}
8526
8527 // Min Register with Register.
8528 instruct minI_eReg(iRegI op1, iRegI op2) %{
8529 match(Set op2 (MinI op1 op2));
8530 ins_cost(DEFAULT_COST*2);
8531 expand %{
8532 flagsReg icc;
8533 compI_iReg(icc,op1,op2);
8534 cmovI_reg_lt(op2,op1,icc);
8535 %}
8536 %}
8537
8538 // Max Instructions
8539 // Conditional move for max
8540 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8541 effect( USE_DEF op2, USE op1, USE icc );
8542 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8543 opcode(Assembler::greater);
8544 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8545 ins_pipe(ialu_reg_flags);
8546 %}
8547
8548 // Max Register with Register
8549 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8550 match(Set op2 (MaxI op1 op2));
8551 ins_cost(DEFAULT_COST*2);
8552 expand %{
8553 flagsReg icc;
8554 compI_iReg(icc,op1,op2);
8555 cmovI_reg_gt(op2,op1,icc);
8556 %}
8557 %}
8558
8559
8560 //----------Float Compares----------------------------------------------------
8561 // Compare floating, generate condition code
8562 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8563 match(Set fcc (CmpF src1 src2));
8564
8565 size(4);
8566 format %{ "FCMPs $fcc,$src1,$src2" %}
8567 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8568 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8569 ins_pipe(faddF_fcc_reg_reg_zero);
8570 %}
8571
8572 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8573 match(Set fcc (CmpD src1 src2));
8574
8575 size(4);
8576 format %{ "FCMPd $fcc,$src1,$src2" %}
8577 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8578 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8579 ins_pipe(faddD_fcc_reg_reg_zero);
8580 %}
8581
8582
8583 // Compare floating, generate -1,0,1
8584 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8585 match(Set dst (CmpF3 src1 src2));
8586 effect(KILL fcc0);
8587 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8588 format %{ "fcmpl $dst,$src1,$src2" %}
8589 // Primary = float
8590 opcode( true );
8591 ins_encode( floating_cmp( dst, src1, src2 ) );
8592 ins_pipe( floating_cmp );
8593 %}
8594
8595 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8596 match(Set dst (CmpD3 src1 src2));
8597 effect(KILL fcc0);
8598 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8599 format %{ "dcmpl $dst,$src1,$src2" %}
8600 // Primary = double (not float)
8601 opcode( false );
8602 ins_encode( floating_cmp( dst, src1, src2 ) );
8603 ins_pipe( floating_cmp );
8604 %}
8605
8606 //----------Branches---------------------------------------------------------
8607 // Jump
8608 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8609 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8610 match(Jump switch_val);
8611 effect(TEMP table);
8612
8613 ins_cost(350);
8614
8615 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
8616 "LD [O7 + $switch_val], O7\n\t"
8617 "JUMP O7" %}
8618 ins_encode %{
8619 // Calculate table address into a register.
8620 Register table_reg;
8621 Register label_reg = O7;
8622 // If we are calculating the size of this instruction don't trust
8623 // zero offsets because they might change when
8624 // MachConstantBaseNode decides to optimize the constant table
8625 // base.
8626 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
8627 table_reg = $constanttablebase;
8628 } else {
8629 table_reg = O7;
8630 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
8631 __ add($constanttablebase, con_offset, table_reg);
8632 }
8633
8634 // Jump to base address + switch value
8635 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
8636 __ jmp(label_reg, G0);
8637 __ delayed()->nop();
8638 %}
8639 ins_pipe(ialu_reg_reg);
8640 %}
8641
8642 // Direct Branch. Use V8 version with longer range.
8643 instruct branch(label labl) %{
8644 match(Goto);
8645 effect(USE labl);
8646
8647 size(8);
8648 ins_cost(BRANCH_COST);
8649 format %{ "BA $labl" %}
8650 ins_encode %{
8651 Label* L = $labl$$label;
8652 __ ba(*L);
8653 __ delayed()->nop();
8654 %}
8655 ins_avoid_back_to_back(AVOID_BEFORE);
8656 ins_pipe(br);
8657 %}
8658
8659 // Direct Branch, short with no delay slot
8660 instruct branch_short(label labl) %{
8661 match(Goto);
8662 predicate(UseCBCond);
8663 effect(USE labl);
8664
8665 size(4);
8666 ins_cost(BRANCH_COST);
8667 format %{ "BA $labl\t! short branch" %}
8668 ins_encode %{
8669 Label* L = $labl$$label;
8670 assert(__ use_cbcond(*L), "back to back cbcond");
8671 __ ba_short(*L);
8672 %}
8673 ins_short_branch(1);
8674 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
8675 ins_pipe(cbcond_reg_imm);
8676 %}
8677
8678 // Conditional Direct Branch
8679 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
8680 match(If cmp icc);
8681 effect(USE labl);
8682
8683 size(8);
8684 ins_cost(BRANCH_COST);
8685 format %{ "BP$cmp $icc,$labl" %}
8686 // Prim = bits 24-22, Secnd = bits 31-30
8687 ins_encode( enc_bp( labl, cmp, icc ) );
8688 ins_avoid_back_to_back(AVOID_BEFORE);
8689 ins_pipe(br_cc);
8690 %}
8691
8692 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
8693 match(If cmp icc);
8694 effect(USE labl);
8695
8696 ins_cost(BRANCH_COST);
8697 format %{ "BP$cmp $icc,$labl" %}
8698 // Prim = bits 24-22, Secnd = bits 31-30
8699 ins_encode( enc_bp( labl, cmp, icc ) );
8700 ins_avoid_back_to_back(AVOID_BEFORE);
8701 ins_pipe(br_cc);
8702 %}
8703
8704 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
8705 match(If cmp pcc);
8706 effect(USE labl);
8707
8708 size(8);
8709 ins_cost(BRANCH_COST);
8710 format %{ "BP$cmp $pcc,$labl" %}
8711 ins_encode %{
8712 Label* L = $labl$$label;
8713 Assembler::Predict predict_taken =
8714 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8715
8716 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
8717 __ delayed()->nop();
8718 %}
8719 ins_avoid_back_to_back(AVOID_BEFORE);
8720 ins_pipe(br_cc);
8721 %}
8722
8723 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
8724 match(If cmp fcc);
8725 effect(USE labl);
8726
8727 size(8);
8728 ins_cost(BRANCH_COST);
8729 format %{ "FBP$cmp $fcc,$labl" %}
8730 ins_encode %{
8731 Label* L = $labl$$label;
8732 Assembler::Predict predict_taken =
8733 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8734
8735 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
8736 __ delayed()->nop();
8737 %}
8738 ins_avoid_back_to_back(AVOID_BEFORE);
8739 ins_pipe(br_fcc);
8740 %}
8741
8742 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
8743 match(CountedLoopEnd cmp icc);
8744 effect(USE labl);
8745
8746 size(8);
8747 ins_cost(BRANCH_COST);
8748 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8749 // Prim = bits 24-22, Secnd = bits 31-30
8750 ins_encode( enc_bp( labl, cmp, icc ) );
8751 ins_avoid_back_to_back(AVOID_BEFORE);
8752 ins_pipe(br_cc);
8753 %}
8754
8755 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
8756 match(CountedLoopEnd cmp icc);
8757 effect(USE labl);
8758
8759 size(8);
8760 ins_cost(BRANCH_COST);
8761 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8762 // Prim = bits 24-22, Secnd = bits 31-30
8763 ins_encode( enc_bp( labl, cmp, icc ) );
8764 ins_avoid_back_to_back(AVOID_BEFORE);
8765 ins_pipe(br_cc);
8766 %}
8767
8768 // Compare and branch instructions
8769 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
8770 match(If cmp (CmpI op1 op2));
8771 effect(USE labl, KILL icc);
8772
8773 size(12);
8774 ins_cost(BRANCH_COST);
8775 format %{ "CMP $op1,$op2\t! int\n\t"
8776 "BP$cmp $labl" %}
8777 ins_encode %{
8778 Label* L = $labl$$label;
8779 Assembler::Predict predict_taken =
8780 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8781 __ cmp($op1$$Register, $op2$$Register);
8782 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8783 __ delayed()->nop();
8784 %}
8785 ins_pipe(cmp_br_reg_reg);
8786 %}
8787
8788 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
8789 match(If cmp (CmpI op1 op2));
8790 effect(USE labl, KILL icc);
8791
8792 size(12);
8793 ins_cost(BRANCH_COST);
8794 format %{ "CMP $op1,$op2\t! int\n\t"
8795 "BP$cmp $labl" %}
8796 ins_encode %{
8797 Label* L = $labl$$label;
8798 Assembler::Predict predict_taken =
8799 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8800 __ cmp($op1$$Register, $op2$$constant);
8801 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8802 __ delayed()->nop();
8803 %}
8804 ins_pipe(cmp_br_reg_imm);
8805 %}
8806
8807 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
8808 match(If cmp (CmpU op1 op2));
8809 effect(USE labl, KILL icc);
8810
8811 size(12);
8812 ins_cost(BRANCH_COST);
8813 format %{ "CMP $op1,$op2\t! unsigned\n\t"
8814 "BP$cmp $labl" %}
8815 ins_encode %{
8816 Label* L = $labl$$label;
8817 Assembler::Predict predict_taken =
8818 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8819 __ cmp($op1$$Register, $op2$$Register);
8820 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8821 __ delayed()->nop();
8822 %}
8823 ins_pipe(cmp_br_reg_reg);
8824 %}
8825
8826 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
8827 match(If cmp (CmpU op1 op2));
8828 effect(USE labl, KILL icc);
8829
8830 size(12);
8831 ins_cost(BRANCH_COST);
8832 format %{ "CMP $op1,$op2\t! unsigned\n\t"
8833 "BP$cmp $labl" %}
8834 ins_encode %{
8835 Label* L = $labl$$label;
8836 Assembler::Predict predict_taken =
8837 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8838 __ cmp($op1$$Register, $op2$$constant);
8839 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8840 __ delayed()->nop();
8841 %}
8842 ins_pipe(cmp_br_reg_imm);
8843 %}
8844
8845 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
8846 match(If cmp (CmpL op1 op2));
8847 effect(USE labl, KILL xcc);
8848
8849 size(12);
8850 ins_cost(BRANCH_COST);
8851 format %{ "CMP $op1,$op2\t! long\n\t"
8852 "BP$cmp $labl" %}
8853 ins_encode %{
8854 Label* L = $labl$$label;
8855 Assembler::Predict predict_taken =
8856 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8857 __ cmp($op1$$Register, $op2$$Register);
8858 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
8859 __ delayed()->nop();
8860 %}
8861 ins_pipe(cmp_br_reg_reg);
8862 %}
8863
8864 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
8865 match(If cmp (CmpL op1 op2));
8866 effect(USE labl, KILL xcc);
8867
8868 size(12);
8869 ins_cost(BRANCH_COST);
8870 format %{ "CMP $op1,$op2\t! long\n\t"
8871 "BP$cmp $labl" %}
8872 ins_encode %{
8873 Label* L = $labl$$label;
8874 Assembler::Predict predict_taken =
8875 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8876 __ cmp($op1$$Register, $op2$$constant);
8877 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
8878 __ delayed()->nop();
8879 %}
8880 ins_pipe(cmp_br_reg_imm);
8881 %}
8882
8883 // Compare Pointers and branch
8884 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
8885 match(If cmp (CmpP op1 op2));
8886 effect(USE labl, KILL pcc);
8887
8888 size(12);
8889 ins_cost(BRANCH_COST);
8890 format %{ "CMP $op1,$op2\t! ptr\n\t"
8891 "B$cmp $labl" %}
8892 ins_encode %{
8893 Label* L = $labl$$label;
8894 Assembler::Predict predict_taken =
8895 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8896 __ cmp($op1$$Register, $op2$$Register);
8897 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
8898 __ delayed()->nop();
8899 %}
8900 ins_pipe(cmp_br_reg_reg);
8901 %}
8902
8903 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
8904 match(If cmp (CmpP op1 null));
8905 effect(USE labl, KILL pcc);
8906
8907 size(12);
8908 ins_cost(BRANCH_COST);
8909 format %{ "CMP $op1,0\t! ptr\n\t"
8910 "B$cmp $labl" %}
8911 ins_encode %{
8912 Label* L = $labl$$label;
8913 Assembler::Predict predict_taken =
8914 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8915 __ cmp($op1$$Register, G0);
8916 // bpr() is not used here since it has shorter distance.
8917 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
8918 __ delayed()->nop();
8919 %}
8920 ins_pipe(cmp_br_reg_reg);
8921 %}
8922
8923 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
8924 match(If cmp (CmpN op1 op2));
8925 effect(USE labl, KILL icc);
8926
8927 size(12);
8928 ins_cost(BRANCH_COST);
8929 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
8930 "BP$cmp $labl" %}
8931 ins_encode %{
8932 Label* L = $labl$$label;
8933 Assembler::Predict predict_taken =
8934 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8935 __ cmp($op1$$Register, $op2$$Register);
8936 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8937 __ delayed()->nop();
8938 %}
8939 ins_pipe(cmp_br_reg_reg);
8940 %}
8941
8942 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
8943 match(If cmp (CmpN op1 null));
8944 effect(USE labl, KILL icc);
8945
8946 size(12);
8947 ins_cost(BRANCH_COST);
8948 format %{ "CMP $op1,0\t! compressed ptr\n\t"
8949 "BP$cmp $labl" %}
8950 ins_encode %{
8951 Label* L = $labl$$label;
8952 Assembler::Predict predict_taken =
8953 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8954 __ cmp($op1$$Register, G0);
8955 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8956 __ delayed()->nop();
8957 %}
8958 ins_pipe(cmp_br_reg_reg);
8959 %}
8960
8961 // Loop back branch
8962 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
8963 match(CountedLoopEnd cmp (CmpI op1 op2));
8964 effect(USE labl, KILL icc);
8965
8966 size(12);
8967 ins_cost(BRANCH_COST);
8968 format %{ "CMP $op1,$op2\t! int\n\t"
8969 "BP$cmp $labl\t! Loop end" %}
8970 ins_encode %{
8971 Label* L = $labl$$label;
8972 Assembler::Predict predict_taken =
8973 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8974 __ cmp($op1$$Register, $op2$$Register);
8975 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8976 __ delayed()->nop();
8977 %}
8978 ins_pipe(cmp_br_reg_reg);
8979 %}
8980
8981 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
8982 match(CountedLoopEnd cmp (CmpI op1 op2));
8983 effect(USE labl, KILL icc);
8984
8985 size(12);
8986 ins_cost(BRANCH_COST);
8987 format %{ "CMP $op1,$op2\t! int\n\t"
8988 "BP$cmp $labl\t! Loop end" %}
8989 ins_encode %{
8990 Label* L = $labl$$label;
8991 Assembler::Predict predict_taken =
8992 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8993 __ cmp($op1$$Register, $op2$$constant);
8994 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8995 __ delayed()->nop();
8996 %}
8997 ins_pipe(cmp_br_reg_imm);
8998 %}
8999
9000 // Short compare and branch instructions
9001 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9002 match(If cmp (CmpI op1 op2));
9003 predicate(UseCBCond);
9004 effect(USE labl, KILL icc);
9005
9006 size(4);
9007 ins_cost(BRANCH_COST);
9008 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9009 ins_encode %{
9010 Label* L = $labl$$label;
9011 assert(__ use_cbcond(*L), "back to back cbcond");
9012 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9013 %}
9014 ins_short_branch(1);
9015 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9016 ins_pipe(cbcond_reg_reg);
9017 %}
9018
9019 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9020 match(If cmp (CmpI op1 op2));
9021 predicate(UseCBCond);
9022 effect(USE labl, KILL icc);
9023
9024 size(4);
9025 ins_cost(BRANCH_COST);
9026 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9027 ins_encode %{
9028 Label* L = $labl$$label;
9029 assert(__ use_cbcond(*L), "back to back cbcond");
9030 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9031 %}
9032 ins_short_branch(1);
9033 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9034 ins_pipe(cbcond_reg_imm);
9035 %}
9036
9037 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9038 match(If cmp (CmpU op1 op2));
9039 predicate(UseCBCond);
9040 effect(USE labl, KILL icc);
9041
9042 size(4);
9043 ins_cost(BRANCH_COST);
9044 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9045 ins_encode %{
9046 Label* L = $labl$$label;
9047 assert(__ use_cbcond(*L), "back to back cbcond");
9048 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9049 %}
9050 ins_short_branch(1);
9051 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9052 ins_pipe(cbcond_reg_reg);
9053 %}
9054
9055 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9056 match(If cmp (CmpU op1 op2));
9057 predicate(UseCBCond);
9058 effect(USE labl, KILL icc);
9059
9060 size(4);
9061 ins_cost(BRANCH_COST);
9062 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9063 ins_encode %{
9064 Label* L = $labl$$label;
9065 assert(__ use_cbcond(*L), "back to back cbcond");
9066 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9067 %}
9068 ins_short_branch(1);
9069 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9070 ins_pipe(cbcond_reg_imm);
9071 %}
9072
9073 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9074 match(If cmp (CmpL op1 op2));
9075 predicate(UseCBCond);
9076 effect(USE labl, KILL xcc);
9077
9078 size(4);
9079 ins_cost(BRANCH_COST);
9080 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9081 ins_encode %{
9082 Label* L = $labl$$label;
9083 assert(__ use_cbcond(*L), "back to back cbcond");
9084 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9085 %}
9086 ins_short_branch(1);
9087 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9088 ins_pipe(cbcond_reg_reg);
9089 %}
9090
9091 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9092 match(If cmp (CmpL op1 op2));
9093 predicate(UseCBCond);
9094 effect(USE labl, KILL xcc);
9095
9096 size(4);
9097 ins_cost(BRANCH_COST);
9098 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9099 ins_encode %{
9100 Label* L = $labl$$label;
9101 assert(__ use_cbcond(*L), "back to back cbcond");
9102 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9103 %}
9104 ins_short_branch(1);
9105 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9106 ins_pipe(cbcond_reg_imm);
9107 %}
9108
9109 // Compare Pointers and branch
9110 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9111 match(If cmp (CmpP op1 op2));
9112 predicate(UseCBCond);
9113 effect(USE labl, KILL pcc);
9114
9115 size(4);
9116 ins_cost(BRANCH_COST);
9117 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9118 ins_encode %{
9119 Label* L = $labl$$label;
9120 assert(__ use_cbcond(*L), "back to back cbcond");
9121 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9122 %}
9123 ins_short_branch(1);
9124 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9125 ins_pipe(cbcond_reg_reg);
9126 %}
9127
9128 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9129 match(If cmp (CmpP op1 null));
9130 predicate(UseCBCond);
9131 effect(USE labl, KILL pcc);
9132
9133 size(4);
9134 ins_cost(BRANCH_COST);
9135 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9136 ins_encode %{
9137 Label* L = $labl$$label;
9138 assert(__ use_cbcond(*L), "back to back cbcond");
9139 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9140 %}
9141 ins_short_branch(1);
9142 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9143 ins_pipe(cbcond_reg_reg);
9144 %}
9145
9146 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9147 match(If cmp (CmpN op1 op2));
9148 predicate(UseCBCond);
9149 effect(USE labl, KILL icc);
9150
9151 size(4);
9152 ins_cost(BRANCH_COST);
9153 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %}
9154 ins_encode %{
9155 Label* L = $labl$$label;
9156 assert(__ use_cbcond(*L), "back to back cbcond");
9157 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9158 %}
9159 ins_short_branch(1);
9160 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9161 ins_pipe(cbcond_reg_reg);
9162 %}
9163
9164 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9165 match(If cmp (CmpN op1 null));
9166 predicate(UseCBCond);
9167 effect(USE labl, KILL icc);
9168
9169 size(4);
9170 ins_cost(BRANCH_COST);
9171 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9172 ins_encode %{
9173 Label* L = $labl$$label;
9174 assert(__ use_cbcond(*L), "back to back cbcond");
9175 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9176 %}
9177 ins_short_branch(1);
9178 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9179 ins_pipe(cbcond_reg_reg);
9180 %}
9181
9182 // Loop back branch
9183 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9184 match(CountedLoopEnd cmp (CmpI op1 op2));
9185 predicate(UseCBCond);
9186 effect(USE labl, KILL icc);
9187
9188 size(4);
9189 ins_cost(BRANCH_COST);
9190 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9191 ins_encode %{
9192 Label* L = $labl$$label;
9193 assert(__ use_cbcond(*L), "back to back cbcond");
9194 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9195 %}
9196 ins_short_branch(1);
9197 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9198 ins_pipe(cbcond_reg_reg);
9199 %}
9200
9201 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9202 match(CountedLoopEnd cmp (CmpI op1 op2));
9203 predicate(UseCBCond);
9204 effect(USE labl, KILL icc);
9205
9206 size(4);
9207 ins_cost(BRANCH_COST);
9208 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9209 ins_encode %{
9210 Label* L = $labl$$label;
9211 assert(__ use_cbcond(*L), "back to back cbcond");
9212 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9213 %}
9214 ins_short_branch(1);
9215 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9216 ins_pipe(cbcond_reg_imm);
9217 %}
9218
9219 // Branch-on-register tests all 64 bits. We assume that values
9220 // in 64-bit registers always remains zero or sign extended
9221 // unless our code munges the high bits. Interrupts can chop
9222 // the high order bits to zero or sign at any time.
9223 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9224 match(If cmp (CmpI op1 zero));
9225 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9226 effect(USE labl);
9227
9228 size(8);
9229 ins_cost(BRANCH_COST);
9230 format %{ "BR$cmp $op1,$labl" %}
9231 ins_encode( enc_bpr( labl, cmp, op1 ) );
9232 ins_avoid_back_to_back(AVOID_BEFORE);
9233 ins_pipe(br_reg);
9234 %}
9235
9236 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9237 match(If cmp (CmpP op1 null));
9238 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9239 effect(USE labl);
9240
9241 size(8);
9242 ins_cost(BRANCH_COST);
9243 format %{ "BR$cmp $op1,$labl" %}
9244 ins_encode( enc_bpr( labl, cmp, op1 ) );
9245 ins_avoid_back_to_back(AVOID_BEFORE);
9246 ins_pipe(br_reg);
9247 %}
9248
9249 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9250 match(If cmp (CmpL op1 zero));
9251 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9252 effect(USE labl);
9253
9254 size(8);
9255 ins_cost(BRANCH_COST);
9256 format %{ "BR$cmp $op1,$labl" %}
9257 ins_encode( enc_bpr( labl, cmp, op1 ) );
9258 ins_avoid_back_to_back(AVOID_BEFORE);
9259 ins_pipe(br_reg);
9260 %}
9261
9262
9263 // ============================================================================
9264 // Long Compare
9265 //
9266 // Currently we hold longs in 2 registers. Comparing such values efficiently
9267 // is tricky. The flavor of compare used depends on whether we are testing
9268 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9269 // The GE test is the negated LT test. The LE test can be had by commuting
9270 // the operands (yielding a GE test) and then negating; negate again for the
9271 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9272 // NE test is negated from that.
9273
9274 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9275 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9276 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9277 // are collapsed internally in the ADLC's dfa-gen code. The match for
9278 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9279 // foo match ends up with the wrong leaf. One fix is to not match both
9280 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9281 // both forms beat the trinary form of long-compare and both are very useful
9282 // on Intel which has so few registers.
9283
9284 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9285 match(If cmp xcc);
9286 effect(USE labl);
9287
9288 size(8);
9289 ins_cost(BRANCH_COST);
9290 format %{ "BP$cmp $xcc,$labl" %}
9291 ins_encode %{
9292 Label* L = $labl$$label;
9293 Assembler::Predict predict_taken =
9294 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9295
9296 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9297 __ delayed()->nop();
9298 %}
9299 ins_avoid_back_to_back(AVOID_BEFORE);
9300 ins_pipe(br_cc);
9301 %}
9302
9303 // Manifest a CmpL3 result in an integer register. Very painful.
9304 // This is the test to avoid.
9305 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9306 match(Set dst (CmpL3 src1 src2) );
9307 effect( KILL ccr );
9308 ins_cost(6*DEFAULT_COST);
9309 size(24);
9310 format %{ "CMP $src1,$src2\t\t! long\n"
9311 "\tBLT,a,pn done\n"
9312 "\tMOV -1,$dst\t! delay slot\n"
9313 "\tBGT,a,pn done\n"
9314 "\tMOV 1,$dst\t! delay slot\n"
9315 "\tCLR $dst\n"
9316 "done:" %}
9317 ins_encode( cmpl_flag(src1,src2,dst) );
9318 ins_pipe(cmpL_reg);
9319 %}
9320
9321 // Conditional move
9322 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9323 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9324 ins_cost(150);
9325 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9326 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9327 ins_pipe(ialu_reg);
9328 %}
9329
9330 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9331 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9332 ins_cost(140);
9333 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9334 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9335 ins_pipe(ialu_imm);
9336 %}
9337
9338 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9339 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9340 ins_cost(150);
9341 format %{ "MOV$cmp $xcc,$src,$dst" %}
9342 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9343 ins_pipe(ialu_reg);
9344 %}
9345
9346 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9347 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9348 ins_cost(140);
9349 format %{ "MOV$cmp $xcc,$src,$dst" %}
9350 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9351 ins_pipe(ialu_imm);
9352 %}
9353
9354 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9355 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9356 ins_cost(150);
9357 format %{ "MOV$cmp $xcc,$src,$dst" %}
9358 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9359 ins_pipe(ialu_reg);
9360 %}
9361
9362 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9363 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9364 ins_cost(150);
9365 format %{ "MOV$cmp $xcc,$src,$dst" %}
9366 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9367 ins_pipe(ialu_reg);
9368 %}
9369
9370 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9371 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9372 ins_cost(140);
9373 format %{ "MOV$cmp $xcc,$src,$dst" %}
9374 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9375 ins_pipe(ialu_imm);
9376 %}
9377
9378 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9379 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9380 ins_cost(150);
9381 opcode(0x101);
9382 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9383 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9384 ins_pipe(int_conditional_float_move);
9385 %}
9386
9387 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9388 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9389 ins_cost(150);
9390 opcode(0x102);
9391 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9392 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9393 ins_pipe(int_conditional_float_move);
9394 %}
9395
9396 // ============================================================================
9397 // Safepoint Instruction
9398 instruct safePoint_poll(iRegP poll) %{
9399 match(SafePoint poll);
9400 effect(USE poll);
9401
9402 size(4);
9403 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9404 ins_encode %{
9405 __ relocate(relocInfo::poll_type);
9406 __ ld_ptr($poll$$Register, 0, G0);
9407 %}
9408 ins_pipe(loadPollP);
9409 %}
9410
9411 // ============================================================================
9412 // Call Instructions
9413 // Call Java Static Instruction
9414 instruct CallStaticJavaDirect( method meth ) %{
9415 match(CallStaticJava);
9416 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9417 effect(USE meth);
9418
9419 size(8);
9420 ins_cost(CALL_COST);
9421 format %{ "CALL,static ; NOP ==> " %}
9422 ins_encode( Java_Static_Call( meth ), call_epilog );
9423 ins_avoid_back_to_back(AVOID_BEFORE);
9424 ins_pipe(simple_call);
9425 %}
9426
9427 // Call Java Static Instruction (method handle version)
9428 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9429 match(CallStaticJava);
9430 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9431 effect(USE meth, KILL l7_mh_SP_save);
9432
9433 size(16);
9434 ins_cost(CALL_COST);
9435 format %{ "CALL,static/MethodHandle" %}
9436 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9437 ins_pipe(simple_call);
9438 %}
9439
9440 // Call Java Dynamic Instruction
9441 instruct CallDynamicJavaDirect( method meth ) %{
9442 match(CallDynamicJava);
9443 effect(USE meth);
9444
9445 ins_cost(CALL_COST);
9446 format %{ "SET (empty),R_G5\n\t"
9447 "CALL,dynamic ; NOP ==> " %}
9448 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9449 ins_pipe(call);
9450 %}
9451
9452 // Call Runtime Instruction
9453 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9454 match(CallRuntime);
9455 effect(USE meth, KILL l7);
9456 ins_cost(CALL_COST);
9457 format %{ "CALL,runtime" %}
9458 ins_encode( Java_To_Runtime( meth ),
9459 call_epilog, adjust_long_from_native_call );
9460 ins_avoid_back_to_back(AVOID_BEFORE);
9461 ins_pipe(simple_call);
9462 %}
9463
9464 // Call runtime without safepoint - same as CallRuntime
9465 instruct CallLeafDirect(method meth, l7RegP l7) %{
9466 match(CallLeaf);
9467 effect(USE meth, KILL l7);
9468 ins_cost(CALL_COST);
9469 format %{ "CALL,runtime leaf" %}
9470 ins_encode( Java_To_Runtime( meth ),
9471 call_epilog,
9472 adjust_long_from_native_call );
9473 ins_avoid_back_to_back(AVOID_BEFORE);
9474 ins_pipe(simple_call);
9475 %}
9476
9477 // Call runtime without safepoint - same as CallLeaf
9478 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9479 match(CallLeafNoFP);
9480 effect(USE meth, KILL l7);
9481 ins_cost(CALL_COST);
9482 format %{ "CALL,runtime leaf nofp" %}
9483 ins_encode( Java_To_Runtime( meth ),
9484 call_epilog,
9485 adjust_long_from_native_call );
9486 ins_avoid_back_to_back(AVOID_BEFORE);
9487 ins_pipe(simple_call);
9488 %}
9489
9490 // Tail Call; Jump from runtime stub to Java code.
9491 // Also known as an 'interprocedural jump'.
9492 // Target of jump will eventually return to caller.
9493 // TailJump below removes the return address.
9494 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9495 match(TailCall jump_target method_oop );
9496
9497 ins_cost(CALL_COST);
9498 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9499 ins_encode(form_jmpl(jump_target));
9500 ins_avoid_back_to_back(AVOID_BEFORE);
9501 ins_pipe(tail_call);
9502 %}
9503
9504
9505 // Return Instruction
9506 instruct Ret() %{
9507 match(Return);
9508
9509 // The epilogue node did the ret already.
9510 size(0);
9511 format %{ "! return" %}
9512 ins_encode();
9513 ins_pipe(empty);
9514 %}
9515
9516
9517 // Tail Jump; remove the return address; jump to target.
9518 // TailCall above leaves the return address around.
9519 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9520 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9521 // "restore" before this instruction (in Epilogue), we need to materialize it
9522 // in %i0.
9523 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9524 match( TailJump jump_target ex_oop );
9525 ins_cost(CALL_COST);
9526 format %{ "! discard R_O7\n\t"
9527 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9528 ins_encode(form_jmpl_set_exception_pc(jump_target));
9529 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9530 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9531 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9532 ins_avoid_back_to_back(AVOID_BEFORE);
9533 ins_pipe(tail_call);
9534 %}
9535
9536 // Create exception oop: created by stack-crawling runtime code.
9537 // Created exception is now available to this handler, and is setup
9538 // just prior to jumping to this handler. No code emitted.
9539 instruct CreateException( o0RegP ex_oop )
9540 %{
9541 match(Set ex_oop (CreateEx));
9542 ins_cost(0);
9543
9544 size(0);
9545 // use the following format syntax
9546 format %{ "! exception oop is in R_O0; no code emitted" %}
9547 ins_encode();
9548 ins_pipe(empty);
9549 %}
9550
9551
9552 // Rethrow exception:
9553 // The exception oop will come in the first argument position.
9554 // Then JUMP (not call) to the rethrow stub code.
9555 instruct RethrowException()
9556 %{
9557 match(Rethrow);
9558 ins_cost(CALL_COST);
9559
9560 // use the following format syntax
9561 format %{ "Jmp rethrow_stub" %}
9562 ins_encode(enc_rethrow);
9563 ins_avoid_back_to_back(AVOID_BEFORE);
9564 ins_pipe(tail_call);
9565 %}
9566
9567
9568 // Die now
9569 instruct ShouldNotReachHere( )
9570 %{
9571 match(Halt);
9572 ins_cost(CALL_COST);
9573
9574 size(4);
9575 // Use the following format syntax
9576 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9577 ins_encode( form2_illtrap() );
9578 ins_pipe(tail_call);
9579 %}
9580
9581 // ============================================================================
9582 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9583 // array for an instance of the superklass. Set a hidden internal cache on a
9584 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9585 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9586 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9587 match(Set index (PartialSubtypeCheck sub super));
9588 effect( KILL pcc, KILL o7 );
9589 ins_cost(DEFAULT_COST*10);
9590 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9591 ins_encode( enc_PartialSubtypeCheck() );
9592 ins_avoid_back_to_back(AVOID_BEFORE);
9593 ins_pipe(partial_subtype_check_pipe);
9594 %}
9595
9596 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9597 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9598 effect( KILL idx, KILL o7 );
9599 ins_cost(DEFAULT_COST*10);
9600 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9601 ins_encode( enc_PartialSubtypeCheck() );
9602 ins_avoid_back_to_back(AVOID_BEFORE);
9603 ins_pipe(partial_subtype_check_pipe);
9604 %}
9605
9606
9607 // ============================================================================
9608 // inlined locking and unlocking
9609
9610 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9611 match(Set pcc (FastLock object box));
9612
9613 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9614 ins_cost(100);
9615
9616 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9617 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9618 ins_pipe(long_memory_op);
9619 %}
9620
9621
9622 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9623 match(Set pcc (FastUnlock object box));
9624 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9625 ins_cost(100);
9626
9627 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9628 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9629 ins_pipe(long_memory_op);
9630 %}
9631
9632 // The encodings are generic.
9633 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9634 predicate(!use_block_zeroing(n->in(2)) );
9635 match(Set dummy (ClearArray cnt base));
9636 effect(TEMP temp, KILL ccr);
9637 ins_cost(300);
9638 format %{ "MOV $cnt,$temp\n"
9639 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9640 " BRge loop\t\t! Clearing loop\n"
9641 " STX G0,[$base+$temp]\t! delay slot" %}
9642
9643 ins_encode %{
9644 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
9645 Register nof_bytes_arg = $cnt$$Register;
9646 Register nof_bytes_tmp = $temp$$Register;
9647 Register base_pointer_arg = $base$$Register;
9648
9649 Label loop;
9650 __ mov(nof_bytes_arg, nof_bytes_tmp);
9651
9652 // Loop and clear, walking backwards through the array.
9653 // nof_bytes_tmp (if >0) is always the number of bytes to zero
9654 __ bind(loop);
9655 __ deccc(nof_bytes_tmp, 8);
9656 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
9657 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
9658 // %%%% this mini-loop must not cross a cache boundary!
9659 %}
9660 ins_pipe(long_memory_op);
9661 %}
9662
9663 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
9664 predicate(use_block_zeroing(n->in(2)));
9665 match(Set dummy (ClearArray cnt base));
9666 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
9667 ins_cost(300);
9668 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
9669
9670 ins_encode %{
9671
9672 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
9673 Register to = $base$$Register;
9674 Register count = $cnt$$Register;
9675
9676 Label Ldone;
9677 __ nop(); // Separate short branches
9678 // Use BIS for zeroing (temp is not used).
9679 __ bis_zeroing(to, count, G0, Ldone);
9680 __ bind(Ldone);
9681
9682 %}
9683 ins_pipe(long_memory_op);
9684 %}
9685
9686 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
9687 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
9688 match(Set dummy (ClearArray cnt base));
9689 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
9690 ins_cost(300);
9691 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
9692
9693 ins_encode %{
9694
9695 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
9696 Register to = $base$$Register;
9697 Register count = $cnt$$Register;
9698 Register temp = $tmp$$Register;
9699
9700 Label Ldone;
9701 __ nop(); // Separate short branches
9702 // Use BIS for zeroing
9703 __ bis_zeroing(to, count, temp, Ldone);
9704 __ bind(Ldone);
9705
9706 %}
9707 ins_pipe(long_memory_op);
9708 %}
9709
9710 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9711 o7RegI tmp, flagsReg ccr) %{
9712 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
9713 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9714 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
9715 ins_cost(300);
9716 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
9717 ins_encode %{
9718 __ string_compare($str1$$Register, $str2$$Register,
9719 $cnt1$$Register, $cnt2$$Register,
9720 $tmp$$Register, $tmp$$Register,
9721 $result$$Register, StrIntrinsicNode::LL);
9722 %}
9723 ins_pipe(long_memory_op);
9724 %}
9725
9726 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9727 o7RegI tmp, flagsReg ccr) %{
9728 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
9729 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9730 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
9731 ins_cost(300);
9732 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
9733 ins_encode %{
9734 __ string_compare($str1$$Register, $str2$$Register,
9735 $cnt1$$Register, $cnt2$$Register,
9736 $tmp$$Register, $tmp$$Register,
9737 $result$$Register, StrIntrinsicNode::UU);
9738 %}
9739 ins_pipe(long_memory_op);
9740 %}
9741
9742 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9743 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
9744 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
9745 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9746 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
9747 ins_cost(300);
9748 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
9749 ins_encode %{
9750 __ string_compare($str1$$Register, $str2$$Register,
9751 $cnt1$$Register, $cnt2$$Register,
9752 $tmp1$$Register, $tmp2$$Register,
9753 $result$$Register, StrIntrinsicNode::LU);
9754 %}
9755 ins_pipe(long_memory_op);
9756 %}
9757
9758 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9759 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
9760 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
9761 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9762 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
9763 ins_cost(300);
9764 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
9765 ins_encode %{
9766 __ string_compare($str2$$Register, $str1$$Register,
9767 $cnt2$$Register, $cnt1$$Register,
9768 $tmp1$$Register, $tmp2$$Register,
9769 $result$$Register, StrIntrinsicNode::UL);
9770 %}
9771 ins_pipe(long_memory_op);
9772 %}
9773
9774 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
9775 o7RegI tmp, flagsReg ccr) %{
9776 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
9777 match(Set result (StrEquals (Binary str1 str2) cnt));
9778 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
9779 ins_cost(300);
9780 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
9781 ins_encode %{
9782 __ array_equals(false, $str1$$Register, $str2$$Register,
9783 $cnt$$Register, $tmp$$Register,
9784 $result$$Register, true /* byte */);
9785 %}
9786 ins_pipe(long_memory_op);
9787 %}
9788
9789 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
9790 o7RegI tmp, flagsReg ccr) %{
9791 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
9792 match(Set result (StrEquals (Binary str1 str2) cnt));
9793 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
9794 ins_cost(300);
9795 format %{ "String Equals char[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
9796 ins_encode %{
9797 __ array_equals(false, $str1$$Register, $str2$$Register,
9798 $cnt$$Register, $tmp$$Register,
9799 $result$$Register, false /* byte */);
9800 %}
9801 ins_pipe(long_memory_op);
9802 %}
9803
9804 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
9805 o7RegI tmp2, flagsReg ccr) %{
9806 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
9807 match(Set result (AryEq ary1 ary2));
9808 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9809 ins_cost(300);
9810 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
9811 ins_encode %{
9812 __ array_equals(true, $ary1$$Register, $ary2$$Register,
9813 $tmp1$$Register, $tmp2$$Register,
9814 $result$$Register, true /* byte */);
9815 %}
9816 ins_pipe(long_memory_op);
9817 %}
9818
9819 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
9820 o7RegI tmp2, flagsReg ccr) %{
9821 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
9822 match(Set result (AryEq ary1 ary2));
9823 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9824 ins_cost(300);
9825 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
9826 ins_encode %{
9827 __ array_equals(true, $ary1$$Register, $ary2$$Register,
9828 $tmp1$$Register, $tmp2$$Register,
9829 $result$$Register, false /* byte */);
9830 %}
9831 ins_pipe(long_memory_op);
9832 %}
9833
9834 instruct has_negatives(o0RegP pAryR, g3RegI iSizeR, notemp_iRegI resultR,
9835 iRegL tmp1L, iRegL tmp2L, iRegL tmp3L, iRegL tmp4L,
9836 flagsReg ccr)
9837 %{
9838 match(Set resultR (HasNegatives pAryR iSizeR));
9839 effect(TEMP resultR, TEMP tmp1L, TEMP tmp2L, TEMP tmp3L, TEMP tmp4L, USE pAryR, USE iSizeR, KILL ccr);
9840 format %{ "has negatives byte[] $pAryR,$iSizeR -> $resultR // KILL $tmp1L,$tmp2L,$tmp3L,$tmp4L" %}
9841 ins_encode %{
9842 __ has_negatives($pAryR$$Register, $iSizeR$$Register,
9843 $resultR$$Register,
9844 $tmp1L$$Register, $tmp2L$$Register,
9845 $tmp3L$$Register, $tmp4L$$Register);
9846 %}
9847 ins_pipe(long_memory_op);
9848 %}
9849
9850 // char[] to byte[] compression
9851 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{
9852 predicate(UseVIS < 3);
9853 match(Set result (StrCompressedCopy src (Binary dst len)));
9854 effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
9855 ins_cost(300);
9856 format %{ "String Compress $src,$dst,$len -> $result // KILL $tmp" %}
9857 ins_encode %{
9858 Label Ldone;
9859 __ signx($len$$Register);
9860 __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn);
9861 __ delayed()->mov($len$$Register, $result$$Register); // copy count
9862 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone);
9863 __ bind(Ldone);
9864 %}
9865 ins_pipe(long_memory_op);
9866 %}
9867
9868 // fast char[] to byte[] compression using VIS instructions
9869 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result,
9870 iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4,
9871 regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{
9872 predicate(UseVIS >= 3);
9873 match(Set result (StrCompressedCopy src (Binary dst len)));
9874 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
9875 ins_cost(300);
9876 format %{ "String Compress Fast $src,$dst,$len -> $result // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %}
9877 ins_encode %{
9878 Label Ldone;
9879 __ signx($len$$Register);
9880 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register,
9881 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
9882 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone);
9883 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
9884 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone);
9885 __ bind(Ldone);
9886 %}
9887 ins_pipe(long_memory_op);
9888 %}
9889
9890 // byte[] to char[] inflation
9891 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
9892 iRegL tmp, flagsReg ccr) %{
9893 match(Set dummy (StrInflatedCopy src (Binary dst len)));
9894 effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
9895 ins_cost(300);
9896 format %{ "String Inflate $src,$dst,$len // KILL $tmp" %}
9897 ins_encode %{
9898 Label Ldone;
9899 __ signx($len$$Register);
9900 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
9901 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
9902 __ bind(Ldone);
9903 %}
9904 ins_pipe(long_memory_op);
9905 %}
9906
9907 // fast byte[] to char[] inflation using VIS instructions
9908 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
9909 iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{
9910 predicate(UseVIS >= 3);
9911 match(Set dummy (StrInflatedCopy src (Binary dst len)));
9912 effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
9913 ins_cost(300);
9914 format %{ "String Inflate Fast $src,$dst,$len // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %}
9915 ins_encode %{
9916 Label Ldone;
9917 __ signx($len$$Register);
9918 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register,
9919 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone);
9920 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
9921 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
9922 __ bind(Ldone);
9923 %}
9924 ins_pipe(long_memory_op);
9925 %}
9926
9927
9928 //---------- Zeros Count Instructions ------------------------------------------
9929
9930 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
9931 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9932 match(Set dst (CountLeadingZerosI src));
9933 effect(TEMP dst, TEMP tmp, KILL cr);
9934
9935 // x |= (x >> 1);
9936 // x |= (x >> 2);
9937 // x |= (x >> 4);
9938 // x |= (x >> 8);
9939 // x |= (x >> 16);
9940 // return (WORDBITS - popc(x));
9941 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
9942 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
9943 "OR $dst,$tmp,$dst\n\t"
9944 "SRL $dst,2,$tmp\n\t"
9945 "OR $dst,$tmp,$dst\n\t"
9946 "SRL $dst,4,$tmp\n\t"
9947 "OR $dst,$tmp,$dst\n\t"
9948 "SRL $dst,8,$tmp\n\t"
9949 "OR $dst,$tmp,$dst\n\t"
9950 "SRL $dst,16,$tmp\n\t"
9951 "OR $dst,$tmp,$dst\n\t"
9952 "POPC $dst,$dst\n\t"
9953 "MOV 32,$tmp\n\t"
9954 "SUB $tmp,$dst,$dst" %}
9955 ins_encode %{
9956 Register Rdst = $dst$$Register;
9957 Register Rsrc = $src$$Register;
9958 Register Rtmp = $tmp$$Register;
9959 __ srl(Rsrc, 1, Rtmp);
9960 __ srl(Rsrc, 0, Rdst);
9961 __ or3(Rdst, Rtmp, Rdst);
9962 __ srl(Rdst, 2, Rtmp);
9963 __ or3(Rdst, Rtmp, Rdst);
9964 __ srl(Rdst, 4, Rtmp);
9965 __ or3(Rdst, Rtmp, Rdst);
9966 __ srl(Rdst, 8, Rtmp);
9967 __ or3(Rdst, Rtmp, Rdst);
9968 __ srl(Rdst, 16, Rtmp);
9969 __ or3(Rdst, Rtmp, Rdst);
9970 __ popc(Rdst, Rdst);
9971 __ mov(BitsPerInt, Rtmp);
9972 __ sub(Rtmp, Rdst, Rdst);
9973 %}
9974 ins_pipe(ialu_reg);
9975 %}
9976
9977 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
9978 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9979 match(Set dst (CountLeadingZerosL src));
9980 effect(TEMP dst, TEMP tmp, KILL cr);
9981
9982 // x |= (x >> 1);
9983 // x |= (x >> 2);
9984 // x |= (x >> 4);
9985 // x |= (x >> 8);
9986 // x |= (x >> 16);
9987 // x |= (x >> 32);
9988 // return (WORDBITS - popc(x));
9989 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
9990 "OR $src,$tmp,$dst\n\t"
9991 "SRLX $dst,2,$tmp\n\t"
9992 "OR $dst,$tmp,$dst\n\t"
9993 "SRLX $dst,4,$tmp\n\t"
9994 "OR $dst,$tmp,$dst\n\t"
9995 "SRLX $dst,8,$tmp\n\t"
9996 "OR $dst,$tmp,$dst\n\t"
9997 "SRLX $dst,16,$tmp\n\t"
9998 "OR $dst,$tmp,$dst\n\t"
9999 "SRLX $dst,32,$tmp\n\t"
10000 "OR $dst,$tmp,$dst\n\t"
10001 "POPC $dst,$dst\n\t"
10002 "MOV 64,$tmp\n\t"
10003 "SUB $tmp,$dst,$dst" %}
10004 ins_encode %{
10005 Register Rdst = $dst$$Register;
10006 Register Rsrc = $src$$Register;
10007 Register Rtmp = $tmp$$Register;
10008 __ srlx(Rsrc, 1, Rtmp);
10009 __ or3( Rsrc, Rtmp, Rdst);
10010 __ srlx(Rdst, 2, Rtmp);
10011 __ or3( Rdst, Rtmp, Rdst);
10012 __ srlx(Rdst, 4, Rtmp);
10013 __ or3( Rdst, Rtmp, Rdst);
10014 __ srlx(Rdst, 8, Rtmp);
10015 __ or3( Rdst, Rtmp, Rdst);
10016 __ srlx(Rdst, 16, Rtmp);
10017 __ or3( Rdst, Rtmp, Rdst);
10018 __ srlx(Rdst, 32, Rtmp);
10019 __ or3( Rdst, Rtmp, Rdst);
10020 __ popc(Rdst, Rdst);
10021 __ mov(BitsPerLong, Rtmp);
10022 __ sub(Rtmp, Rdst, Rdst);
10023 %}
10024 ins_pipe(ialu_reg);
10025 %}
10026
10027 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10028 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10029 match(Set dst (CountTrailingZerosI src));
10030 effect(TEMP dst, KILL cr);
10031
10032 // return popc(~x & (x - 1));
10033 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10034 "ANDN $dst,$src,$dst\n\t"
10035 "SRL $dst,R_G0,$dst\n\t"
10036 "POPC $dst,$dst" %}
10037 ins_encode %{
10038 Register Rdst = $dst$$Register;
10039 Register Rsrc = $src$$Register;
10040 __ sub(Rsrc, 1, Rdst);
10041 __ andn(Rdst, Rsrc, Rdst);
10042 __ srl(Rdst, G0, Rdst);
10043 __ popc(Rdst, Rdst);
10044 %}
10045 ins_pipe(ialu_reg);
10046 %}
10047
10048 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10049 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10050 match(Set dst (CountTrailingZerosL src));
10051 effect(TEMP dst, KILL cr);
10052
10053 // return popc(~x & (x - 1));
10054 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10055 "ANDN $dst,$src,$dst\n\t"
10056 "POPC $dst,$dst" %}
10057 ins_encode %{
10058 Register Rdst = $dst$$Register;
10059 Register Rsrc = $src$$Register;
10060 __ sub(Rsrc, 1, Rdst);
10061 __ andn(Rdst, Rsrc, Rdst);
10062 __ popc(Rdst, Rdst);
10063 %}
10064 ins_pipe(ialu_reg);
10065 %}
10066
10067
10068 //---------- Population Count Instructions -------------------------------------
10069
10070 instruct popCountI(iRegIsafe dst, iRegI src) %{
10071 predicate(UsePopCountInstruction);
10072 match(Set dst (PopCountI src));
10073
10074 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10075 "POPC $dst, $dst" %}
10076 ins_encode %{
10077 __ srl($src$$Register, G0, $dst$$Register);
10078 __ popc($dst$$Register, $dst$$Register);
10079 %}
10080 ins_pipe(ialu_reg);
10081 %}
10082
10083 // Note: Long.bitCount(long) returns an int.
10084 instruct popCountL(iRegIsafe dst, iRegL src) %{
10085 predicate(UsePopCountInstruction);
10086 match(Set dst (PopCountL src));
10087
10088 format %{ "POPC $src, $dst" %}
10089 ins_encode %{
10090 __ popc($src$$Register, $dst$$Register);
10091 %}
10092 ins_pipe(ialu_reg);
10093 %}
10094
10095
10096 // ============================================================================
10097 //------------Bytes reverse--------------------------------------------------
10098
10099 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10100 match(Set dst (ReverseBytesI src));
10101
10102 // Op cost is artificially doubled to make sure that load or store
10103 // instructions are preferred over this one which requires a spill
10104 // onto a stack slot.
10105 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10106 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10107
10108 ins_encode %{
10109 __ set($src$$disp + STACK_BIAS, O7);
10110 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10111 %}
10112 ins_pipe( iload_mem );
10113 %}
10114
10115 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10116 match(Set dst (ReverseBytesL src));
10117
10118 // Op cost is artificially doubled to make sure that load or store
10119 // instructions are preferred over this one which requires a spill
10120 // onto a stack slot.
10121 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10122 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10123
10124 ins_encode %{
10125 __ set($src$$disp + STACK_BIAS, O7);
10126 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10127 %}
10128 ins_pipe( iload_mem );
10129 %}
10130
10131 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10132 match(Set dst (ReverseBytesUS src));
10133
10134 // Op cost is artificially doubled to make sure that load or store
10135 // instructions are preferred over this one which requires a spill
10136 // onto a stack slot.
10137 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10138 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10139
10140 ins_encode %{
10141 // the value was spilled as an int so bias the load
10142 __ set($src$$disp + STACK_BIAS + 2, O7);
10143 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10144 %}
10145 ins_pipe( iload_mem );
10146 %}
10147
10148 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10149 match(Set dst (ReverseBytesS src));
10150
10151 // Op cost is artificially doubled to make sure that load or store
10152 // instructions are preferred over this one which requires a spill
10153 // onto a stack slot.
10154 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10155 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10156
10157 ins_encode %{
10158 // the value was spilled as an int so bias the load
10159 __ set($src$$disp + STACK_BIAS + 2, O7);
10160 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10161 %}
10162 ins_pipe( iload_mem );
10163 %}
10164
10165 // Load Integer reversed byte order
10166 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10167 match(Set dst (ReverseBytesI (LoadI src)));
10168
10169 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10170 size(4);
10171 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10172
10173 ins_encode %{
10174 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10175 %}
10176 ins_pipe(iload_mem);
10177 %}
10178
10179 // Load Long - aligned and reversed
10180 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10181 match(Set dst (ReverseBytesL (LoadL src)));
10182
10183 ins_cost(MEMORY_REF_COST);
10184 size(4);
10185 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10186
10187 ins_encode %{
10188 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10189 %}
10190 ins_pipe(iload_mem);
10191 %}
10192
10193 // Load unsigned short / char reversed byte order
10194 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10195 match(Set dst (ReverseBytesUS (LoadUS src)));
10196
10197 ins_cost(MEMORY_REF_COST);
10198 size(4);
10199 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10200
10201 ins_encode %{
10202 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10203 %}
10204 ins_pipe(iload_mem);
10205 %}
10206
10207 // Load short reversed byte order
10208 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10209 match(Set dst (ReverseBytesS (LoadS src)));
10210
10211 ins_cost(MEMORY_REF_COST);
10212 size(4);
10213 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10214
10215 ins_encode %{
10216 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10217 %}
10218 ins_pipe(iload_mem);
10219 %}
10220
10221 // Store Integer reversed byte order
10222 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10223 match(Set dst (StoreI dst (ReverseBytesI src)));
10224
10225 ins_cost(MEMORY_REF_COST);
10226 size(4);
10227 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10228
10229 ins_encode %{
10230 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10231 %}
10232 ins_pipe(istore_mem_reg);
10233 %}
10234
10235 // Store Long reversed byte order
10236 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10237 match(Set dst (StoreL dst (ReverseBytesL src)));
10238
10239 ins_cost(MEMORY_REF_COST);
10240 size(4);
10241 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10242
10243 ins_encode %{
10244 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10245 %}
10246 ins_pipe(istore_mem_reg);
10247 %}
10248
10249 // Store unsighed short/char reversed byte order
10250 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10251 match(Set dst (StoreC dst (ReverseBytesUS src)));
10252
10253 ins_cost(MEMORY_REF_COST);
10254 size(4);
10255 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10256
10257 ins_encode %{
10258 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10259 %}
10260 ins_pipe(istore_mem_reg);
10261 %}
10262
10263 // Store short reversed byte order
10264 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10265 match(Set dst (StoreC dst (ReverseBytesS src)));
10266
10267 ins_cost(MEMORY_REF_COST);
10268 size(4);
10269 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10270
10271 ins_encode %{
10272 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10273 %}
10274 ins_pipe(istore_mem_reg);
10275 %}
10276
10277 // ====================VECTOR INSTRUCTIONS=====================================
10278
10279 // Load Aligned Packed values into a Double Register
10280 instruct loadV8(regD dst, memory mem) %{
10281 predicate(n->as_LoadVector()->memory_size() == 8);
10282 match(Set dst (LoadVector mem));
10283 ins_cost(MEMORY_REF_COST);
10284 size(4);
10285 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10286 ins_encode %{
10287 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10288 %}
10289 ins_pipe(floadD_mem);
10290 %}
10291
10292 // Store Vector in Double register to memory
10293 instruct storeV8(memory mem, regD src) %{
10294 predicate(n->as_StoreVector()->memory_size() == 8);
10295 match(Set mem (StoreVector mem src));
10296 ins_cost(MEMORY_REF_COST);
10297 size(4);
10298 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10299 ins_encode %{
10300 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10301 %}
10302 ins_pipe(fstoreD_mem_reg);
10303 %}
10304
10305 // Store Zero into vector in memory
10306 instruct storeV8B_zero(memory mem, immI0 zero) %{
10307 predicate(n->as_StoreVector()->memory_size() == 8);
10308 match(Set mem (StoreVector mem (ReplicateB zero)));
10309 ins_cost(MEMORY_REF_COST);
10310 size(4);
10311 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10312 ins_encode %{
10313 __ stx(G0, $mem$$Address);
10314 %}
10315 ins_pipe(fstoreD_mem_zero);
10316 %}
10317
10318 instruct storeV4S_zero(memory mem, immI0 zero) %{
10319 predicate(n->as_StoreVector()->memory_size() == 8);
10320 match(Set mem (StoreVector mem (ReplicateS zero)));
10321 ins_cost(MEMORY_REF_COST);
10322 size(4);
10323 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10324 ins_encode %{
10325 __ stx(G0, $mem$$Address);
10326 %}
10327 ins_pipe(fstoreD_mem_zero);
10328 %}
10329
10330 instruct storeV2I_zero(memory mem, immI0 zero) %{
10331 predicate(n->as_StoreVector()->memory_size() == 8);
10332 match(Set mem (StoreVector mem (ReplicateI zero)));
10333 ins_cost(MEMORY_REF_COST);
10334 size(4);
10335 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10336 ins_encode %{
10337 __ stx(G0, $mem$$Address);
10338 %}
10339 ins_pipe(fstoreD_mem_zero);
10340 %}
10341
10342 instruct storeV2F_zero(memory mem, immF0 zero) %{
10343 predicate(n->as_StoreVector()->memory_size() == 8);
10344 match(Set mem (StoreVector mem (ReplicateF zero)));
10345 ins_cost(MEMORY_REF_COST);
10346 size(4);
10347 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10348 ins_encode %{
10349 __ stx(G0, $mem$$Address);
10350 %}
10351 ins_pipe(fstoreD_mem_zero);
10352 %}
10353
10354 // Replicate scalar to packed byte values into Double register
10355 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10356 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10357 match(Set dst (ReplicateB src));
10358 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10359 format %{ "SLLX $src,56,$tmp\n\t"
10360 "SRLX $tmp, 8,$tmp2\n\t"
10361 "OR $tmp,$tmp2,$tmp\n\t"
10362 "SRLX $tmp,16,$tmp2\n\t"
10363 "OR $tmp,$tmp2,$tmp\n\t"
10364 "SRLX $tmp,32,$tmp2\n\t"
10365 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10366 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10367 ins_encode %{
10368 Register Rsrc = $src$$Register;
10369 Register Rtmp = $tmp$$Register;
10370 Register Rtmp2 = $tmp2$$Register;
10371 __ sllx(Rsrc, 56, Rtmp);
10372 __ srlx(Rtmp, 8, Rtmp2);
10373 __ or3 (Rtmp, Rtmp2, Rtmp);
10374 __ srlx(Rtmp, 16, Rtmp2);
10375 __ or3 (Rtmp, Rtmp2, Rtmp);
10376 __ srlx(Rtmp, 32, Rtmp2);
10377 __ or3 (Rtmp, Rtmp2, Rtmp);
10378 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10379 %}
10380 ins_pipe(ialu_reg);
10381 %}
10382
10383 // Replicate scalar to packed byte values into Double stack
10384 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10385 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10386 match(Set dst (ReplicateB src));
10387 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10388 format %{ "SLLX $src,56,$tmp\n\t"
10389 "SRLX $tmp, 8,$tmp2\n\t"
10390 "OR $tmp,$tmp2,$tmp\n\t"
10391 "SRLX $tmp,16,$tmp2\n\t"
10392 "OR $tmp,$tmp2,$tmp\n\t"
10393 "SRLX $tmp,32,$tmp2\n\t"
10394 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10395 "STX $tmp,$dst\t! regL to stkD" %}
10396 ins_encode %{
10397 Register Rsrc = $src$$Register;
10398 Register Rtmp = $tmp$$Register;
10399 Register Rtmp2 = $tmp2$$Register;
10400 __ sllx(Rsrc, 56, Rtmp);
10401 __ srlx(Rtmp, 8, Rtmp2);
10402 __ or3 (Rtmp, Rtmp2, Rtmp);
10403 __ srlx(Rtmp, 16, Rtmp2);
10404 __ or3 (Rtmp, Rtmp2, Rtmp);
10405 __ srlx(Rtmp, 32, Rtmp2);
10406 __ or3 (Rtmp, Rtmp2, Rtmp);
10407 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10408 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10409 %}
10410 ins_pipe(ialu_reg);
10411 %}
10412
10413 // Replicate scalar constant to packed byte values in Double register
10414 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10415 predicate(n->as_Vector()->length() == 8);
10416 match(Set dst (ReplicateB con));
10417 effect(KILL tmp);
10418 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10419 ins_encode %{
10420 // XXX This is a quick fix for 6833573.
10421 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10422 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10423 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10424 %}
10425 ins_pipe(loadConFD);
10426 %}
10427
10428 // Replicate scalar to packed char/short values into Double register
10429 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10430 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10431 match(Set dst (ReplicateS src));
10432 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10433 format %{ "SLLX $src,48,$tmp\n\t"
10434 "SRLX $tmp,16,$tmp2\n\t"
10435 "OR $tmp,$tmp2,$tmp\n\t"
10436 "SRLX $tmp,32,$tmp2\n\t"
10437 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10438 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10439 ins_encode %{
10440 Register Rsrc = $src$$Register;
10441 Register Rtmp = $tmp$$Register;
10442 Register Rtmp2 = $tmp2$$Register;
10443 __ sllx(Rsrc, 48, Rtmp);
10444 __ srlx(Rtmp, 16, Rtmp2);
10445 __ or3 (Rtmp, Rtmp2, Rtmp);
10446 __ srlx(Rtmp, 32, Rtmp2);
10447 __ or3 (Rtmp, Rtmp2, Rtmp);
10448 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10449 %}
10450 ins_pipe(ialu_reg);
10451 %}
10452
10453 // Replicate scalar to packed char/short values into Double stack
10454 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10455 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10456 match(Set dst (ReplicateS src));
10457 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10458 format %{ "SLLX $src,48,$tmp\n\t"
10459 "SRLX $tmp,16,$tmp2\n\t"
10460 "OR $tmp,$tmp2,$tmp\n\t"
10461 "SRLX $tmp,32,$tmp2\n\t"
10462 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10463 "STX $tmp,$dst\t! regL to stkD" %}
10464 ins_encode %{
10465 Register Rsrc = $src$$Register;
10466 Register Rtmp = $tmp$$Register;
10467 Register Rtmp2 = $tmp2$$Register;
10468 __ sllx(Rsrc, 48, Rtmp);
10469 __ srlx(Rtmp, 16, Rtmp2);
10470 __ or3 (Rtmp, Rtmp2, Rtmp);
10471 __ srlx(Rtmp, 32, Rtmp2);
10472 __ or3 (Rtmp, Rtmp2, Rtmp);
10473 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10474 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10475 %}
10476 ins_pipe(ialu_reg);
10477 %}
10478
10479 // Replicate scalar constant to packed char/short values in Double register
10480 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10481 predicate(n->as_Vector()->length() == 4);
10482 match(Set dst (ReplicateS con));
10483 effect(KILL tmp);
10484 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10485 ins_encode %{
10486 // XXX This is a quick fix for 6833573.
10487 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10488 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10489 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10490 %}
10491 ins_pipe(loadConFD);
10492 %}
10493
10494 // Replicate scalar to packed int values into Double register
10495 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10496 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10497 match(Set dst (ReplicateI src));
10498 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10499 format %{ "SLLX $src,32,$tmp\n\t"
10500 "SRLX $tmp,32,$tmp2\n\t"
10501 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10502 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10503 ins_encode %{
10504 Register Rsrc = $src$$Register;
10505 Register Rtmp = $tmp$$Register;
10506 Register Rtmp2 = $tmp2$$Register;
10507 __ sllx(Rsrc, 32, Rtmp);
10508 __ srlx(Rtmp, 32, Rtmp2);
10509 __ or3 (Rtmp, Rtmp2, Rtmp);
10510 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10511 %}
10512 ins_pipe(ialu_reg);
10513 %}
10514
10515 // Replicate scalar to packed int values into Double stack
10516 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10517 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10518 match(Set dst (ReplicateI src));
10519 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10520 format %{ "SLLX $src,32,$tmp\n\t"
10521 "SRLX $tmp,32,$tmp2\n\t"
10522 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10523 "STX $tmp,$dst\t! regL to stkD" %}
10524 ins_encode %{
10525 Register Rsrc = $src$$Register;
10526 Register Rtmp = $tmp$$Register;
10527 Register Rtmp2 = $tmp2$$Register;
10528 __ sllx(Rsrc, 32, Rtmp);
10529 __ srlx(Rtmp, 32, Rtmp2);
10530 __ or3 (Rtmp, Rtmp2, Rtmp);
10531 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10532 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10533 %}
10534 ins_pipe(ialu_reg);
10535 %}
10536
10537 // Replicate scalar zero constant to packed int values in Double register
10538 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10539 predicate(n->as_Vector()->length() == 2);
10540 match(Set dst (ReplicateI con));
10541 effect(KILL tmp);
10542 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10543 ins_encode %{
10544 // XXX This is a quick fix for 6833573.
10545 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10546 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10547 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10548 %}
10549 ins_pipe(loadConFD);
10550 %}
10551
10552 // Replicate scalar to packed float values into Double stack
10553 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10554 predicate(n->as_Vector()->length() == 2);
10555 match(Set dst (ReplicateF src));
10556 ins_cost(MEMORY_REF_COST*2);
10557 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10558 "STF $src,$dst.lo" %}
10559 opcode(Assembler::stf_op3);
10560 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10561 ins_pipe(fstoreF_stk_reg);
10562 %}
10563
10564 // Replicate scalar zero constant to packed float values in Double register
10565 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10566 predicate(n->as_Vector()->length() == 2);
10567 match(Set dst (ReplicateF con));
10568 effect(KILL tmp);
10569 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10570 ins_encode %{
10571 // XXX This is a quick fix for 6833573.
10572 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10573 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10574 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10575 %}
10576 ins_pipe(loadConFD);
10577 %}
10578
10579 //----------PEEPHOLE RULES-----------------------------------------------------
10580 // These must follow all instruction definitions as they use the names
10581 // defined in the instructions definitions.
10582 //
10583 // peepmatch ( root_instr_name [preceding_instruction]* );
10584 //
10585 // peepconstraint %{
10586 // (instruction_number.operand_name relational_op instruction_number.operand_name
10587 // [, ...] );
10588 // // instruction numbers are zero-based using left to right order in peepmatch
10589 //
10590 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10591 // // provide an instruction_number.operand_name for each operand that appears
10592 // // in the replacement instruction's match rule
10593 //
10594 // ---------VM FLAGS---------------------------------------------------------
10595 //
10596 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10597 //
10598 // Each peephole rule is given an identifying number starting with zero and
10599 // increasing by one in the order seen by the parser. An individual peephole
10600 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10601 // on the command-line.
10602 //
10603 // ---------CURRENT LIMITATIONS----------------------------------------------
10604 //
10605 // Only match adjacent instructions in same basic block
10606 // Only equality constraints
10607 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10608 // Only one replacement instruction
10609 //
10610 // ---------EXAMPLE----------------------------------------------------------
10611 //
10612 // // pertinent parts of existing instructions in architecture description
10613 // instruct movI(eRegI dst, eRegI src) %{
10614 // match(Set dst (CopyI src));
10615 // %}
10616 //
10617 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10618 // match(Set dst (AddI dst src));
10619 // effect(KILL cr);
10620 // %}
10621 //
10622 // // Change (inc mov) to lea
10623 // peephole %{
10624 // // increment preceeded by register-register move
10625 // peepmatch ( incI_eReg movI );
10626 // // require that the destination register of the increment
10627 // // match the destination register of the move
10628 // peepconstraint ( 0.dst == 1.dst );
10629 // // construct a replacement instruction that sets
10630 // // the destination to ( move's source register + one )
10631 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10632 // %}
10633 //
10634
10635 // // Change load of spilled value to only a spill
10636 // instruct storeI(memory mem, eRegI src) %{
10637 // match(Set mem (StoreI mem src));
10638 // %}
10639 //
10640 // instruct loadI(eRegI dst, memory mem) %{
10641 // match(Set dst (LoadI mem));
10642 // %}
10643 //
10644 // peephole %{
10645 // peepmatch ( loadI storeI );
10646 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10647 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10648 // %}
10649
10650 //----------SMARTSPILL RULES---------------------------------------------------
10651 // These must follow all instruction definitions as they use the names
10652 // defined in the instructions definitions.
10653 //
10654 // SPARC will probably not have any of these rules due to RISC instruction set.
10655
10656 //----------PIPELINE-----------------------------------------------------------
10657 // Rules which define the behavior of the target architectures pipeline.