539 assert (op->code() == lir_branch, "just checking");
540
541 Assembler::Condition acond;
542 switch (op->cond()) {
543 case lir_cond_equal: acond = Assembler::equal; break;
544 case lir_cond_notEqual: acond = Assembler::notEqual; break;
545 case lir_cond_less: acond = Assembler::less; break;
546 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
547 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
548 case lir_cond_greater: acond = Assembler::greater; break;
549 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
550 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
551 default: ShouldNotReachHere();
552 };
553
554 // sparc has different condition codes for testing 32-bit
555 // vs. 64-bit values. We could always test xcc is we could
556 // guarantee that 32-bit loads always sign extended but that isn't
557 // true and since sign extension isn't free, it would impose a
558 // slight cost.
559 #ifdef _LP64
560 if (op->type() == T_INT) {
561 __ br(acond, false, Assembler::pn, *(op->label()));
562 } else
563 #endif
564 __ brx(acond, false, Assembler::pn, *(op->label()));
565 }
566 // The peephole pass fills the delay slot
567 }
568
569
570 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
571 Bytecodes::Code code = op->bytecode();
572 LIR_Opr dst = op->result_opr();
573
574 switch(code) {
575 case Bytecodes::_i2l: {
576 Register rlo = dst->as_register_lo();
577 Register rhi = dst->as_register_hi();
578 Register rval = op->in_opr()->as_register();
579 #ifdef _LP64
580 __ sra(rval, 0, rlo);
581 #else
582 __ mov(rval, rlo);
583 __ sra(rval, BitsPerInt-1, rhi);
584 #endif
585 break;
586 }
587 case Bytecodes::_i2d:
588 case Bytecodes::_i2f: {
589 bool is_double = (code == Bytecodes::_i2d);
590 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
591 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
592 FloatRegister rsrc = op->in_opr()->as_float_reg();
593 if (rsrc != rdst) {
594 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
595 }
596 __ fitof(w, rdst, rdst);
597 break;
598 }
599 case Bytecodes::_f2i:{
600 FloatRegister rsrc = op->in_opr()->as_float_reg();
601 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
602 Label L;
603 // result must be 0 if value is NaN; test by comparing value to itself
604 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
605 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
606 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
607 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
608 // move integer result from float register to int register
609 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
610 __ bind (L);
611 break;
612 }
613 case Bytecodes::_l2i: {
614 Register rlo = op->in_opr()->as_register_lo();
615 Register rhi = op->in_opr()->as_register_hi();
616 Register rdst = dst->as_register();
617 #ifdef _LP64
618 __ sra(rlo, 0, rdst);
619 #else
620 __ mov(rlo, rdst);
621 #endif
622 break;
623 }
624 case Bytecodes::_d2f:
625 case Bytecodes::_f2d: {
626 bool is_double = (code == Bytecodes::_f2d);
627 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
628 LIR_Opr val = op->in_opr();
629 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
630 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
631 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
632 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
633 __ ftof(vw, dw, rval, rdst);
634 break;
635 }
636 case Bytecodes::_i2s:
637 case Bytecodes::_i2b: {
638 Register rval = op->in_opr()->as_register();
639 Register rdst = dst->as_register();
640 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
641 __ sll (rval, shift, rdst);
694 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
695 int store_offset;
696 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
697 assert(base != O7, "destroying register");
698 assert(!unaligned, "can't handle this");
699 // for offsets larger than a simm13 we setup the offset in O7
700 __ set(offset, O7);
701 store_offset = store(from_reg, base, O7, type, wide);
702 } else {
703 if (type == T_ARRAY || type == T_OBJECT) {
704 __ verify_oop(from_reg->as_register());
705 }
706 store_offset = code_offset();
707 switch (type) {
708 case T_BOOLEAN: // fall through
709 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
710 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
711 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
712 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
713 case T_LONG :
714 #ifdef _LP64
715 if (unaligned || PatchALot) {
716 // Don't use O7 here because it may be equal to 'base' (see LIR_Assembler::reg2mem)
717 assert(G3_scratch != base, "can't handle this");
718 assert(G3_scratch != from_reg->as_register_lo(), "can't handle this");
719 __ srax(from_reg->as_register_lo(), 32, G3_scratch);
720 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
721 __ stw(G3_scratch, base, offset + hi_word_offset_in_bytes);
722 } else {
723 __ stx(from_reg->as_register_lo(), base, offset);
724 }
725 #else
726 assert(Assembler::is_simm13(offset + 4), "must be");
727 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
728 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
729 #endif
730 break;
731 case T_ADDRESS:
732 case T_METADATA:
733 __ st_ptr(from_reg->as_register(), base, offset);
734 break;
735 case T_ARRAY : // fall through
736 case T_OBJECT:
737 {
738 if (UseCompressedOops && !wide) {
739 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
740 store_offset = code_offset();
741 __ stw(G3_scratch, base, offset);
742 } else {
743 __ st_ptr(from_reg->as_register(), base, offset);
744 }
745 break;
746 }
747
748 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
749 case T_DOUBLE:
761 }
762 default : ShouldNotReachHere();
763 }
764 }
765 return store_offset;
766 }
767
768
769 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
770 if (type == T_ARRAY || type == T_OBJECT) {
771 __ verify_oop(from_reg->as_register());
772 }
773 int store_offset = code_offset();
774 switch (type) {
775 case T_BOOLEAN: // fall through
776 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
777 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
778 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
779 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
780 case T_LONG :
781 #ifdef _LP64
782 __ stx(from_reg->as_register_lo(), base, disp);
783 #else
784 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
785 __ std(from_reg->as_register_hi(), base, disp);
786 #endif
787 break;
788 case T_ADDRESS:
789 __ st_ptr(from_reg->as_register(), base, disp);
790 break;
791 case T_ARRAY : // fall through
792 case T_OBJECT:
793 {
794 if (UseCompressedOops && !wide) {
795 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
796 store_offset = code_offset();
797 __ stw(G3_scratch, base, disp);
798 } else {
799 __ st_ptr(from_reg->as_register(), base, disp);
800 }
801 break;
802 }
803 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
804 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
805 default : ShouldNotReachHere();
806 }
809
810
811 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
812 int load_offset;
813 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
814 assert(base != O7, "destroying register");
815 assert(!unaligned, "can't handle this");
816 // for offsets larger than a simm13 we setup the offset in O7
817 __ set(offset, O7);
818 load_offset = load(base, O7, to_reg, type, wide);
819 } else {
820 load_offset = code_offset();
821 switch(type) {
822 case T_BOOLEAN: // fall through
823 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
824 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
825 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
826 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
827 case T_LONG :
828 if (!unaligned && !PatchALot) {
829 #ifdef _LP64
830 __ ldx(base, offset, to_reg->as_register_lo());
831 #else
832 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
833 "must be sequential");
834 __ ldd(base, offset, to_reg->as_register_hi());
835 #endif
836 } else {
837 #ifdef _LP64
838 assert(base != to_reg->as_register_lo(), "can't handle this");
839 assert(O7 != to_reg->as_register_lo(), "can't handle this");
840 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
841 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
842 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
843 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
844 #else
845 if (base == to_reg->as_register_lo()) {
846 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
847 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
848 } else {
849 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
850 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
851 }
852 #endif
853 }
854 break;
855 case T_METADATA: __ ld_ptr(base, offset, to_reg->as_register()); break;
856 case T_ADDRESS:
857 #ifdef _LP64
858 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
859 __ lduw(base, offset, to_reg->as_register());
860 __ decode_klass_not_null(to_reg->as_register());
861 } else
862 #endif
863 {
864 __ ld_ptr(base, offset, to_reg->as_register());
865 }
866 break;
867 case T_ARRAY : // fall through
868 case T_OBJECT:
869 {
870 if (UseCompressedOops && !wide) {
871 __ lduw(base, offset, to_reg->as_register());
872 __ decode_heap_oop(to_reg->as_register());
873 } else {
874 __ ld_ptr(base, offset, to_reg->as_register());
875 }
876 break;
877 }
878 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
879 case T_DOUBLE:
880 {
881 FloatRegister reg = to_reg->as_double_reg();
882 // split unaligned loads
904 case T_BOOLEAN: // fall through
905 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
906 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
907 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
908 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
909 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
910 case T_ARRAY : // fall through
911 case T_OBJECT:
912 {
913 if (UseCompressedOops && !wide) {
914 __ lduw(base, disp, to_reg->as_register());
915 __ decode_heap_oop(to_reg->as_register());
916 } else {
917 __ ld_ptr(base, disp, to_reg->as_register());
918 }
919 break;
920 }
921 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
922 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
923 case T_LONG :
924 #ifdef _LP64
925 __ ldx(base, disp, to_reg->as_register_lo());
926 #else
927 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
928 "must be sequential");
929 __ ldd(base, disp, to_reg->as_register_hi());
930 #endif
931 break;
932 default : ShouldNotReachHere();
933 }
934 if (type == T_ARRAY || type == T_OBJECT) {
935 __ verify_oop(to_reg->as_register());
936 }
937 return load_offset;
938 }
939
940 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
941 LIR_Const* c = src->as_constant_ptr();
942 switch (c->type()) {
943 case T_INT:
944 case T_FLOAT: {
945 Register src_reg = O7;
946 int value = c->as_jint_bits();
947 if (value == 0) {
948 src_reg = G0;
949 } else {
950 __ set(value, O7);
1090 if (to_reg->is_single_cpu()) {
1091 assert(patch_code == lir_patch_none, "no patching handled here");
1092 __ set(con, to_reg->as_register());
1093 } else {
1094 ShouldNotReachHere();
1095 assert(to_reg->is_single_fpu(), "wrong register kind");
1096
1097 __ set(con, O7);
1098 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1099 __ st(O7, temp_slot);
1100 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1101 }
1102 }
1103 break;
1104
1105 case T_LONG:
1106 {
1107 jlong con = c->as_jlong();
1108
1109 if (to_reg->is_double_cpu()) {
1110 #ifdef _LP64
1111 __ set(con, to_reg->as_register_lo());
1112 #else
1113 __ set(low(con), to_reg->as_register_lo());
1114 __ set(high(con), to_reg->as_register_hi());
1115 #endif
1116 #ifdef _LP64
1117 } else if (to_reg->is_single_cpu()) {
1118 __ set(con, to_reg->as_register());
1119 #endif
1120 } else {
1121 ShouldNotReachHere();
1122 assert(to_reg->is_double_fpu(), "wrong register kind");
1123 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1124 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1125 __ set(low(con), O7);
1126 __ st(O7, temp_slot_lo);
1127 __ set(high(con), O7);
1128 __ st(O7, temp_slot_hi);
1129 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1130 }
1131 }
1132 break;
1133
1134 case T_OBJECT:
1135 {
1136 if (patch_code == lir_patch_none) {
1137 jobject2reg(c->as_jobject(), to_reg->as_register());
1138 } else {
1139 jobject2reg_with_patching(to_reg->as_register(), info);
1173 }
1174 }
1175 break;
1176
1177 case T_DOUBLE:
1178 {
1179 address const_addr = __ double_constant(c->as_jdouble());
1180 if (const_addr == NULL) {
1181 bailout("const section overflow");
1182 break;
1183 }
1184 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1185
1186 if (to_reg->is_double_fpu()) {
1187 AddressLiteral const_addrlit(const_addr, rspec);
1188 __ patchable_sethi(const_addrlit, O7);
1189 __ relocate(rspec);
1190 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1191 } else {
1192 assert(to_reg->is_double_cpu(), "Must be a long register.");
1193 #ifdef _LP64
1194 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1195 #else
1196 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
1197 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
1198 #endif
1199 }
1200
1201 }
1202 break;
1203
1204 default:
1205 ShouldNotReachHere();
1206 }
1207 }
1208
1209 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1210 Register reg = addr->base()->as_pointer_register();
1211 LIR_Opr index = addr->index();
1212 if (index->is_illegal()) {
1213 return Address(reg, addr->disp());
1214 } else {
1215 assert (addr->disp() == 0, "unsupported address mode");
1216 return Address(reg, index->as_pointer_register());
1217 }
1218 }
1349 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1350 }
1351 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1352 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1353 }
1354
1355
1356 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1357 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1358 if (from_reg->is_double_fpu()) {
1359 // double to double moves
1360 assert(to_reg->is_double_fpu(), "should match");
1361 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1362 } else {
1363 // float to float moves
1364 assert(to_reg->is_single_fpu(), "should match");
1365 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1366 }
1367 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1368 if (from_reg->is_double_cpu()) {
1369 #ifdef _LP64
1370 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1371 #else
1372 assert(to_reg->is_double_cpu() &&
1373 from_reg->as_register_hi() != to_reg->as_register_lo() &&
1374 from_reg->as_register_lo() != to_reg->as_register_hi(),
1375 "should both be long and not overlap");
1376 // long to long moves
1377 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
1378 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
1379 #endif
1380 #ifdef _LP64
1381 } else if (to_reg->is_double_cpu()) {
1382 // int to int moves
1383 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1384 #endif
1385 } else {
1386 // int to int moves
1387 __ mov(from_reg->as_register(), to_reg->as_register());
1388 }
1389 } else {
1390 ShouldNotReachHere();
1391 }
1392 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1393 __ verify_oop(to_reg->as_register());
1394 }
1395 }
1396
1397
1398 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1399 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1400 bool wide, bool unaligned) {
1401 assert(type != T_METADATA, "store of metadata ptr not supported");
1402 LIR_Address* addr = dest->as_address_ptr();
1403
1404 Register src = addr->base()->as_pointer_register();
1444 if (disp_reg == noreg) {
1445 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1446 } else {
1447 assert(!unaligned, "can't handle this");
1448 offset = store(from_reg, src, disp_reg, type, wide);
1449 }
1450
1451 if (patch != NULL) {
1452 patching_epilog(patch, patch_code, src, info);
1453 }
1454
1455 if (info != NULL) add_debug_info_for_null_check(offset, info);
1456 }
1457
1458
1459 void LIR_Assembler::return_op(LIR_Opr result) {
1460 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1461 __ reserved_stack_check();
1462 }
1463 // the poll may need a register so just pick one that isn't the return register
1464 #if defined(TIERED) && !defined(_LP64)
1465 if (result->type_field() == LIR_OprDesc::long_type) {
1466 // Must move the result to G1
1467 // Must leave proper result in O0,O1 and G1 (TIERED only)
1468 __ sllx(I0, 32, G1); // Shift bits into high G1
1469 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
1470 __ or3 (I1, G1, G1); // OR 64 bits into G1
1471 #ifdef ASSERT
1472 // mangle it so any problems will show up
1473 __ set(0xdeadbeef, I0);
1474 __ set(0xdeadbeef, I1);
1475 #endif
1476 }
1477 #endif // TIERED
1478 __ set((intptr_t)os::get_polling_page(), L0);
1479 __ relocate(relocInfo::poll_return_type);
1480 __ ld_ptr(L0, 0, G0);
1481 __ ret();
1482 __ delayed()->restore();
1483 }
1484
1485
1486 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1487 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1488 if (info != NULL) {
1489 add_debug_info_for_branch(info);
1490 }
1491 int offset = __ offset();
1492 __ relocate(relocInfo::poll_type);
1493 __ ld_ptr(tmp->as_register(), 0, G0);
1494 return offset;
1495 }
1496
1497
1551 default:
1552 ShouldNotReachHere();
1553 break;
1554 }
1555 } else {
1556 if (opr2->is_address()) {
1557 LIR_Address * addr = opr2->as_address_ptr();
1558 BasicType type = addr->type();
1559 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1560 else __ ld(as_Address(addr), O7);
1561 __ cmp(opr1->as_register(), O7);
1562 } else {
1563 __ cmp(opr1->as_register(), opr2->as_register());
1564 }
1565 }
1566 } else if (opr1->is_double_cpu()) {
1567 Register xlo = opr1->as_register_lo();
1568 Register xhi = opr1->as_register_hi();
1569 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1570 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1571 #ifdef _LP64
1572 __ orcc(xhi, G0, G0);
1573 #else
1574 __ orcc(xhi, xlo, G0);
1575 #endif
1576 } else if (opr2->is_register()) {
1577 Register ylo = opr2->as_register_lo();
1578 Register yhi = opr2->as_register_hi();
1579 #ifdef _LP64
1580 __ cmp(xlo, ylo);
1581 #else
1582 __ subcc(xlo, ylo, xlo);
1583 __ subccc(xhi, yhi, xhi);
1584 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1585 __ orcc(xhi, xlo, G0);
1586 }
1587 #endif
1588 } else {
1589 ShouldNotReachHere();
1590 }
1591 } else if (opr1->is_address()) {
1592 LIR_Address * addr = opr1->as_address_ptr();
1593 BasicType type = addr->type();
1594 assert (opr2->is_constant(), "Checking");
1595 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1596 else __ ld(as_Address(addr), O7);
1597 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1598 } else {
1599 ShouldNotReachHere();
1600 }
1601 }
1602
1603
1604 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1605 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1606 bool is_unordered_less = (code == lir_ucmp_fd2i);
1607 if (left->is_single_fpu()) {
1608 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1609 } else if (left->is_double_fpu()) {
1610 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1611 } else {
1612 ShouldNotReachHere();
1613 }
1614 } else if (code == lir_cmp_l2i) {
1615 #ifdef _LP64
1616 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1617 #else
1618 __ lcmp(left->as_register_hi(), left->as_register_lo(),
1619 right->as_register_hi(), right->as_register_lo(),
1620 dst->as_register());
1621 #endif
1622 } else {
1623 ShouldNotReachHere();
1624 }
1625 }
1626
1627
1628 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1629 Assembler::Condition acond;
1630 switch (condition) {
1631 case lir_cond_equal: acond = Assembler::equal; break;
1632 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1633 case lir_cond_less: acond = Assembler::less; break;
1634 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1635 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1636 case lir_cond_greater: acond = Assembler::greater; break;
1637 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1638 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1639 default: ShouldNotReachHere();
1640 };
1641
1642 if (opr1->is_constant() && opr1->type() == T_INT) {
1643 Register dest = result->as_register();
1644 // load up first part of constant before branch
1645 // and do the rest in the delay slot.
1646 if (!Assembler::is_simm13(opr1->as_jint())) {
1647 __ sethi(opr1->as_jint(), dest);
1648 }
1649 } else if (opr1->is_constant()) {
1650 const2reg(opr1, result, lir_patch_none, NULL);
1651 } else if (opr1->is_register()) {
1652 reg2reg(opr1, result);
1653 } else if (opr1->is_stack()) {
1654 stack2reg(opr1, result, result->type());
1655 } else {
1656 ShouldNotReachHere();
1657 }
1658 Label skip;
1659 #ifdef _LP64
1660 if (type == T_INT) {
1661 __ br(acond, false, Assembler::pt, skip);
1662 } else
1663 #endif
1664 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
1665 if (opr1->is_constant() && opr1->type() == T_INT) {
1666 Register dest = result->as_register();
1667 if (Assembler::is_simm13(opr1->as_jint())) {
1668 __ delayed()->or3(G0, opr1->as_jint(), dest);
1669 } else {
1670 // the sethi has been done above, so just put in the low 10 bits
1671 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1672 }
1673 } else {
1674 // can't do anything useful in the delay slot
1675 __ delayed()->nop();
1676 }
1677 if (opr2->is_constant()) {
1678 const2reg(opr2, result, lir_patch_none, NULL);
1679 } else if (opr2->is_register()) {
1680 reg2reg(opr2, result);
1681 } else if (opr2->is_stack()) {
1682 stack2reg(opr2, result, result->type());
1683 } else {
1703 rreg = right->as_float_reg();
1704 res = dest->as_float_reg();
1705 } else {
1706 w = FloatRegisterImpl::D;
1707 lreg = left->as_double_reg();
1708 rreg = right->as_double_reg();
1709 res = dest->as_double_reg();
1710 }
1711
1712 switch (code) {
1713 case lir_add: __ fadd(w, lreg, rreg, res); break;
1714 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1715 case lir_mul: // fall through
1716 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1717 case lir_div: // fall through
1718 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1719 default: ShouldNotReachHere();
1720 }
1721
1722 } else if (dest->is_double_cpu()) {
1723 #ifdef _LP64
1724 Register dst_lo = dest->as_register_lo();
1725 Register op1_lo = left->as_pointer_register();
1726 Register op2_lo = right->as_pointer_register();
1727
1728 switch (code) {
1729 case lir_add:
1730 __ add(op1_lo, op2_lo, dst_lo);
1731 break;
1732
1733 case lir_sub:
1734 __ sub(op1_lo, op2_lo, dst_lo);
1735 break;
1736
1737 default: ShouldNotReachHere();
1738 }
1739 #else
1740 Register op1_lo = left->as_register_lo();
1741 Register op1_hi = left->as_register_hi();
1742 Register op2_lo = right->as_register_lo();
1743 Register op2_hi = right->as_register_hi();
1744 Register dst_lo = dest->as_register_lo();
1745 Register dst_hi = dest->as_register_hi();
1746
1747 switch (code) {
1748 case lir_add:
1749 __ addcc(op1_lo, op2_lo, dst_lo);
1750 __ addc (op1_hi, op2_hi, dst_hi);
1751 break;
1752
1753 case lir_sub:
1754 __ subcc(op1_lo, op2_lo, dst_lo);
1755 __ subc (op1_hi, op2_hi, dst_hi);
1756 break;
1757
1758 default: ShouldNotReachHere();
1759 }
1760 #endif
1761 } else {
1762 assert (right->is_single_cpu(), "Just Checking");
1763
1764 Register lreg = left->as_register();
1765 Register res = dest->as_register();
1766 Register rreg = right->as_register();
1767 switch (code) {
1768 case lir_add: __ add (lreg, rreg, res); break;
1769 case lir_sub: __ sub (lreg, rreg, res); break;
1770 case lir_mul: __ mulx (lreg, rreg, res); break;
1771 default: ShouldNotReachHere();
1772 }
1773 }
1774 } else {
1775 assert (right->is_constant(), "must be constant");
1776
1777 if (dest->is_single_cpu()) {
1778 Register lreg = left->as_register();
1779 Register res = dest->as_register();
1780 int simm13 = right->as_constant_ptr()->as_jint();
1835 }
1836 }
1837
1838
1839 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1840 if (right->is_constant()) {
1841 if (dest->is_single_cpu()) {
1842 int simm13 = right->as_constant_ptr()->as_jint();
1843 switch (code) {
1844 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1845 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1846 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1847 default: ShouldNotReachHere();
1848 }
1849 } else {
1850 long c = right->as_constant_ptr()->as_jlong();
1851 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1852 int simm13 = (int)c;
1853 switch (code) {
1854 case lir_logic_and:
1855 #ifndef _LP64
1856 __ and3 (left->as_register_hi(), 0, dest->as_register_hi());
1857 #endif
1858 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1859 break;
1860
1861 case lir_logic_or:
1862 #ifndef _LP64
1863 __ or3 (left->as_register_hi(), 0, dest->as_register_hi());
1864 #endif
1865 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1866 break;
1867
1868 case lir_logic_xor:
1869 #ifndef _LP64
1870 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi());
1871 #endif
1872 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1873 break;
1874
1875 default: ShouldNotReachHere();
1876 }
1877 }
1878 } else {
1879 assert(right->is_register(), "right should be in register");
1880
1881 if (dest->is_single_cpu()) {
1882 switch (code) {
1883 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1884 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1885 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1886 default: ShouldNotReachHere();
1887 }
1888 } else {
1889 #ifdef _LP64
1890 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1891 left->as_register_lo();
1892 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1893 right->as_register_lo();
1894
1895 switch (code) {
1896 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
1897 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
1898 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
1899 default: ShouldNotReachHere();
1900 }
1901 #else
1902 switch (code) {
1903 case lir_logic_and:
1904 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
1905 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
1906 break;
1907
1908 case lir_logic_or:
1909 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
1910 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
1911 break;
1912
1913 case lir_logic_xor:
1914 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
1915 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
1916 break;
1917
1918 default: ShouldNotReachHere();
1919 }
1920 #endif
1921 }
1922 }
1923 }
1924
1925
1926 int LIR_Assembler::shift_amount(BasicType t) {
1927 int elem_size = type2aelembytes(t);
1928 switch (elem_size) {
1929 case 1 : return 0;
1930 case 2 : return 1;
1931 case 4 : return 2;
1932 case 8 : return 3;
1933 }
1934 ShouldNotReachHere();
1935 return -1;
1936 }
1937
1938
1939 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1940 assert(exceptionOop->as_register() == Oexception, "should match");
1958 assert(exceptionOop->as_register() == Oexception, "should match");
1959
1960 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
1961 __ delayed()->nop();
1962 }
1963
1964 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1965 Register src = op->src()->as_register();
1966 Register dst = op->dst()->as_register();
1967 Register src_pos = op->src_pos()->as_register();
1968 Register dst_pos = op->dst_pos()->as_register();
1969 Register length = op->length()->as_register();
1970 Register tmp = op->tmp()->as_register();
1971 Register tmp2 = O7;
1972
1973 int flags = op->flags();
1974 ciArrayKlass* default_type = op->expected_type();
1975 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1976 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1977
1978 #ifdef _LP64
1979 // higher 32bits must be null
1980 __ sra(dst_pos, 0, dst_pos);
1981 __ sra(src_pos, 0, src_pos);
1982 __ sra(length, 0, length);
1983 #endif
1984
1985 // set up the arraycopy stub information
1986 ArrayCopyStub* stub = op->stub();
1987
1988 // always do stub if no type information is available. it's ok if
1989 // the known type isn't loaded since the code sanity checks
1990 // in debug mode and the type isn't required when we know the exact type
1991 // also check that the type is an array type.
1992 if (op->expected_type() == NULL) {
1993 __ mov(src, O0);
1994 __ mov(src_pos, O1);
1995 __ mov(dst, O2);
1996 __ mov(dst_pos, O3);
1997 __ mov(length, O4);
1998 address copyfunc_addr = StubRoutines::generic_arraycopy();
1999
2000 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
2001 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
2002 } else {
2003 #ifndef PRODUCT
2299 } else {
2300 __ sll(dst_pos, shift, tmp);
2301 __ add(dst_ptr, tmp, dst_ptr);
2302 }
2303
2304 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2305 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2306 const char *name;
2307 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2308
2309 // arraycopy stubs takes a length in number of elements, so don't scale it.
2310 __ mov(length, len);
2311 __ call_VM_leaf(tmp, entry);
2312
2313 __ bind(*stub->continuation());
2314 }
2315
2316
2317 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2318 if (dest->is_single_cpu()) {
2319 #ifdef _LP64
2320 if (left->type() == T_OBJECT) {
2321 switch (code) {
2322 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2323 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2324 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2325 default: ShouldNotReachHere();
2326 }
2327 } else
2328 #endif
2329 switch (code) {
2330 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2331 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2332 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2333 default: ShouldNotReachHere();
2334 }
2335 } else {
2336 #ifdef _LP64
2337 switch (code) {
2338 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2339 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2340 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2341 default: ShouldNotReachHere();
2342 }
2343 #else
2344 switch (code) {
2345 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2346 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2347 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2348 default: ShouldNotReachHere();
2349 }
2350 #endif
2351 }
2352 }
2353
2354
2355 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2356 #ifdef _LP64
2357 if (left->type() == T_OBJECT) {
2358 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2359 Register l = left->as_register();
2360 Register d = dest->as_register_lo();
2361 switch (code) {
2362 case lir_shl: __ sllx (l, count, d); break;
2363 case lir_shr: __ srax (l, count, d); break;
2364 case lir_ushr: __ srlx (l, count, d); break;
2365 default: ShouldNotReachHere();
2366 }
2367 return;
2368 }
2369 #endif
2370
2371 if (dest->is_single_cpu()) {
2372 count = count & 0x1F; // Java spec
2373 switch (code) {
2374 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2375 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2376 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2377 default: ShouldNotReachHere();
2378 }
2379 } else if (dest->is_double_cpu()) {
2380 count = count & 63; // Java spec
2381 switch (code) {
2382 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2383 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2384 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2385 default: ShouldNotReachHere();
2386 }
2387 } else {
2388 ShouldNotReachHere();
2389 }
2731 __ bind(success);
2732 __ set(1, dst);
2733 __ bind(done);
2734 } else {
2735 ShouldNotReachHere();
2736 }
2737
2738 }
2739
2740
2741 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2742 if (op->code() == lir_cas_long) {
2743 assert(VM_Version::supports_cx8(), "wrong machine");
2744 Register addr = op->addr()->as_pointer_register();
2745 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2746 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2747 Register new_value_lo = op->new_value()->as_register_lo();
2748 Register new_value_hi = op->new_value()->as_register_hi();
2749 Register t1 = op->tmp1()->as_register();
2750 Register t2 = op->tmp2()->as_register();
2751 #ifdef _LP64
2752 __ mov(cmp_value_lo, t1);
2753 __ mov(new_value_lo, t2);
2754 // perform the compare and swap operation
2755 __ casx(addr, t1, t2);
2756 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2757 // overwritten with the original value in "addr" and will be equal to t1.
2758 __ cmp(t1, t2);
2759 #else
2760 // move high and low halves of long values into single registers
2761 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg
2762 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
2763 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
2764 __ sllx(new_value_hi, 32, t2);
2765 __ srl(new_value_lo, 0, new_value_lo);
2766 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
2767 // perform the compare and swap operation
2768 __ casx(addr, t1, t2);
2769 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2770 // overwritten with the original value in "addr" and will be equal to t1.
2771 // Produce icc flag for 32bit.
2772 __ sub(t1, t2, t2);
2773 __ srlx(t2, 32, t1);
2774 __ orcc(t2, t1, G0);
2775 #endif
2776 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2777 Register addr = op->addr()->as_pointer_register();
2778 Register cmp_value = op->cmp_value()->as_register();
2779 Register new_value = op->new_value()->as_register();
2780 Register t1 = op->tmp1()->as_register();
2781 Register t2 = op->tmp2()->as_register();
2782 __ mov(cmp_value, t1);
2783 __ mov(new_value, t2);
2784 if (op->code() == lir_cas_obj) {
2785 if (UseCompressedOops) {
2786 __ encode_heap_oop(t1);
2787 __ encode_heap_oop(t2);
2788 __ cas(addr, t1, t2);
2789 } else {
2790 __ cas_ptr(addr, t1, t2);
2791 }
2792 } else {
2793 __ cas(addr, t1, t2);
2794 }
2795 __ cmp(t1, t2);
2897 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2898 __ delayed()->nop();
2899 }
2900 }
2901 __ bind(*op->stub()->continuation());
2902 }
2903
2904
2905 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2906 ciMethod* method = op->profiled_method();
2907 int bci = op->profiled_bci();
2908 ciMethod* callee = op->profiled_callee();
2909
2910 // Update counter for all call types
2911 ciMethodData* md = method->method_data_or_null();
2912 assert(md != NULL, "Sanity");
2913 ciProfileData* data = md->bci_to_data(bci);
2914 assert(data->is_CounterData(), "need CounterData for calls");
2915 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2916 Register mdo = op->mdo()->as_register();
2917 #ifdef _LP64
2918 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2919 Register tmp1 = op->tmp1()->as_register_lo();
2920 #else
2921 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2922 Register tmp1 = op->tmp1()->as_register();
2923 #endif
2924 metadata2reg(md->constant_encoding(), mdo);
2925 int mdo_offset_bias = 0;
2926 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2927 data->size_in_bytes())) {
2928 // The offset is large so bias the mdo by the base of the slot so
2929 // that the ld can use simm13s to reference the slots of the data
2930 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2931 __ set(mdo_offset_bias, O7);
2932 __ add(mdo, O7, mdo);
2933 }
2934
2935 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2936 Bytecodes::Code bc = method->java_code_at_bci(bci);
2937 const bool callee_is_static = callee->is_loaded() && callee->is_static();
2938 // Perform additional virtual call profiling for invokevirtual and
2939 // invokeinterface bytecodes
2940 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2941 !callee_is_static && // required for optimized MH invokes
2942 C1ProfileVirtualCalls) {
2943 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3183 _masm->sub(FP, SP, O7);
3184 _masm->cmp(O7, initial_frame_size_in_bytes());
3185 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
3186 }
3187 }
3188
3189
3190 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3191 assert(left->is_register(), "can only handle registers");
3192
3193 if (left->is_single_cpu()) {
3194 __ neg(left->as_register(), dest->as_register());
3195 } else if (left->is_single_fpu()) {
3196 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
3197 } else if (left->is_double_fpu()) {
3198 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
3199 } else {
3200 assert (left->is_double_cpu(), "Must be a long");
3201 Register Rlow = left->as_register_lo();
3202 Register Rhi = left->as_register_hi();
3203 #ifdef _LP64
3204 __ sub(G0, Rlow, dest->as_register_lo());
3205 #else
3206 __ subcc(G0, Rlow, dest->as_register_lo());
3207 __ subc (G0, Rhi, dest->as_register_hi());
3208 #endif
3209 }
3210 }
3211
3212
3213 void LIR_Assembler::fxch(int i) {
3214 Unimplemented();
3215 }
3216
3217 void LIR_Assembler::fld(int i) {
3218 Unimplemented();
3219 }
3220
3221 void LIR_Assembler::ffree(int i) {
3222 Unimplemented();
3223 }
3224
3225 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
3226 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3227
3228 // if tmp is invalid, then the function being called doesn't destroy the thread
3229 if (tmp->is_valid()) {
3230 __ save_thread(tmp->as_pointer_register());
3231 }
3232 __ call(dest, relocInfo::runtime_call_type);
3233 __ delayed()->nop();
3234 if (info != NULL) {
3235 add_call_info_here(info);
3236 }
3237 if (tmp->is_valid()) {
3238 __ restore_thread(tmp->as_pointer_register());
3239 }
3240
3241 #ifdef ASSERT
3242 __ verify_thread();
3243 #endif // ASSERT
3244 }
3245
3246
3247 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3248 #ifdef _LP64
3249 ShouldNotReachHere();
3250 #endif
3251
3252 NEEDS_CLEANUP;
3253 if (type == T_LONG) {
3254 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3255
3256 // (extended to allow indexed as well as constant displaced for JSR-166)
3257 Register idx = noreg; // contains either constant offset or index
3258
3259 int disp = mem_addr->disp();
3260 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
3261 if (!Assembler::is_simm13(disp)) {
3262 idx = O7;
3263 __ set(disp, idx);
3264 }
3265 } else {
3266 assert(disp == 0, "not both indexed and disp");
3267 idx = mem_addr->index()->as_register();
3268 }
3269
3270 int null_check_offset = -1;
3474 prev->result_opr()->as_register() != O0) &&
3475 LIR_Assembler::is_single_instruction(prev)) {
3476 // Only moves without info can be put into the delay slot.
3477 // Also don't allow the setup of the receiver in the delay
3478 // slot for vtable calls.
3479 inst->at_put(i - 1, op);
3480 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3481 #ifndef PRODUCT
3482 if (LIRTracePeephole) {
3483 tty->print_cr("delayed");
3484 inst->at(i - 1)->print();
3485 inst->at(i)->print();
3486 tty->cr();
3487 }
3488 #endif
3489 } else {
3490 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3491 inst->insert_before(i + 1, delay_op);
3492 i++;
3493 }
3494
3495 #if defined(TIERED) && !defined(_LP64)
3496 // fixup the return value from G1 to O0/O1 for long returns.
3497 // It's done here instead of in LIRGenerator because there's
3498 // such a mismatch between the single reg and double reg
3499 // calling convention.
3500 LIR_OpJavaCall* callop = op->as_OpJavaCall();
3501 if (callop->result_opr() == FrameMap::out_long_opr) {
3502 LIR_OpJavaCall* call;
3503 LIR_OprList* arguments = new LIR_OprList(callop->arguments()->length());
3504 for (int a = 0; a < arguments->length(); a++) {
3505 arguments[a] = callop->arguments()[a];
3506 }
3507 if (op->code() == lir_virtual_call) {
3508 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3509 callop->vtable_offset(), arguments, callop->info());
3510 } else {
3511 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3512 callop->addr(), arguments, callop->info());
3513 }
3514 inst->at_put(i - 1, call);
3515 inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(),
3516 T_LONG, lir_patch_none, NULL));
3517 }
3518 #endif
3519 break;
3520 }
3521 }
3522 }
3523 }
3524
3525 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3526 LIR_Address* addr = src->as_address_ptr();
3527
3528 assert(data == dest, "swap uses only 2 operands");
3529 assert (code == lir_xchg, "no xadd on sparc");
3530
3531 if (data->type() == T_INT) {
3532 __ swap(as_Address(addr), data->as_register());
3533 } else if (data->is_oop()) {
3534 Register obj = data->as_register();
3535 Register narrow = tmp->as_register();
3536 #ifdef _LP64
3537 assert(UseCompressedOops, "swap is 32bit only");
3538 __ encode_heap_oop(obj, narrow);
3539 __ swap(as_Address(addr), narrow);
3540 __ decode_heap_oop(narrow, obj);
3541 #else
3542 __ swap(as_Address(addr), obj);
3543 #endif
3544 } else {
3545 ShouldNotReachHere();
3546 }
3547 }
3548
3549 #undef __
|
539 assert (op->code() == lir_branch, "just checking");
540
541 Assembler::Condition acond;
542 switch (op->cond()) {
543 case lir_cond_equal: acond = Assembler::equal; break;
544 case lir_cond_notEqual: acond = Assembler::notEqual; break;
545 case lir_cond_less: acond = Assembler::less; break;
546 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
547 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
548 case lir_cond_greater: acond = Assembler::greater; break;
549 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
550 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
551 default: ShouldNotReachHere();
552 };
553
554 // sparc has different condition codes for testing 32-bit
555 // vs. 64-bit values. We could always test xcc is we could
556 // guarantee that 32-bit loads always sign extended but that isn't
557 // true and since sign extension isn't free, it would impose a
558 // slight cost.
559 if (op->type() == T_INT) {
560 __ br(acond, false, Assembler::pn, *(op->label()));
561 } else
562 __ brx(acond, false, Assembler::pn, *(op->label()));
563 }
564 // The peephole pass fills the delay slot
565 }
566
567
568 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
569 Bytecodes::Code code = op->bytecode();
570 LIR_Opr dst = op->result_opr();
571
572 switch(code) {
573 case Bytecodes::_i2l: {
574 Register rlo = dst->as_register_lo();
575 Register rhi = dst->as_register_hi();
576 Register rval = op->in_opr()->as_register();
577 __ sra(rval, 0, rlo);
578 break;
579 }
580 case Bytecodes::_i2d:
581 case Bytecodes::_i2f: {
582 bool is_double = (code == Bytecodes::_i2d);
583 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
584 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
585 FloatRegister rsrc = op->in_opr()->as_float_reg();
586 if (rsrc != rdst) {
587 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
588 }
589 __ fitof(w, rdst, rdst);
590 break;
591 }
592 case Bytecodes::_f2i:{
593 FloatRegister rsrc = op->in_opr()->as_float_reg();
594 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
595 Label L;
596 // result must be 0 if value is NaN; test by comparing value to itself
597 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
598 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
599 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
600 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
601 // move integer result from float register to int register
602 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
603 __ bind (L);
604 break;
605 }
606 case Bytecodes::_l2i: {
607 Register rlo = op->in_opr()->as_register_lo();
608 Register rhi = op->in_opr()->as_register_hi();
609 Register rdst = dst->as_register();
610 __ sra(rlo, 0, rdst);
611 break;
612 }
613 case Bytecodes::_d2f:
614 case Bytecodes::_f2d: {
615 bool is_double = (code == Bytecodes::_f2d);
616 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
617 LIR_Opr val = op->in_opr();
618 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
619 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
620 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
621 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
622 __ ftof(vw, dw, rval, rdst);
623 break;
624 }
625 case Bytecodes::_i2s:
626 case Bytecodes::_i2b: {
627 Register rval = op->in_opr()->as_register();
628 Register rdst = dst->as_register();
629 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
630 __ sll (rval, shift, rdst);
683 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
684 int store_offset;
685 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
686 assert(base != O7, "destroying register");
687 assert(!unaligned, "can't handle this");
688 // for offsets larger than a simm13 we setup the offset in O7
689 __ set(offset, O7);
690 store_offset = store(from_reg, base, O7, type, wide);
691 } else {
692 if (type == T_ARRAY || type == T_OBJECT) {
693 __ verify_oop(from_reg->as_register());
694 }
695 store_offset = code_offset();
696 switch (type) {
697 case T_BOOLEAN: // fall through
698 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
699 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
700 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
701 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
702 case T_LONG :
703 if (unaligned || PatchALot) {
704 // Don't use O7 here because it may be equal to 'base' (see LIR_Assembler::reg2mem)
705 assert(G3_scratch != base, "can't handle this");
706 assert(G3_scratch != from_reg->as_register_lo(), "can't handle this");
707 __ srax(from_reg->as_register_lo(), 32, G3_scratch);
708 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
709 __ stw(G3_scratch, base, offset + hi_word_offset_in_bytes);
710 } else {
711 __ stx(from_reg->as_register_lo(), base, offset);
712 }
713 break;
714 case T_ADDRESS:
715 case T_METADATA:
716 __ st_ptr(from_reg->as_register(), base, offset);
717 break;
718 case T_ARRAY : // fall through
719 case T_OBJECT:
720 {
721 if (UseCompressedOops && !wide) {
722 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
723 store_offset = code_offset();
724 __ stw(G3_scratch, base, offset);
725 } else {
726 __ st_ptr(from_reg->as_register(), base, offset);
727 }
728 break;
729 }
730
731 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
732 case T_DOUBLE:
744 }
745 default : ShouldNotReachHere();
746 }
747 }
748 return store_offset;
749 }
750
751
752 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
753 if (type == T_ARRAY || type == T_OBJECT) {
754 __ verify_oop(from_reg->as_register());
755 }
756 int store_offset = code_offset();
757 switch (type) {
758 case T_BOOLEAN: // fall through
759 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
760 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
761 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
762 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
763 case T_LONG :
764 __ stx(from_reg->as_register_lo(), base, disp);
765 break;
766 case T_ADDRESS:
767 __ st_ptr(from_reg->as_register(), base, disp);
768 break;
769 case T_ARRAY : // fall through
770 case T_OBJECT:
771 {
772 if (UseCompressedOops && !wide) {
773 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
774 store_offset = code_offset();
775 __ stw(G3_scratch, base, disp);
776 } else {
777 __ st_ptr(from_reg->as_register(), base, disp);
778 }
779 break;
780 }
781 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
782 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
783 default : ShouldNotReachHere();
784 }
787
788
789 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
790 int load_offset;
791 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
792 assert(base != O7, "destroying register");
793 assert(!unaligned, "can't handle this");
794 // for offsets larger than a simm13 we setup the offset in O7
795 __ set(offset, O7);
796 load_offset = load(base, O7, to_reg, type, wide);
797 } else {
798 load_offset = code_offset();
799 switch(type) {
800 case T_BOOLEAN: // fall through
801 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
802 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
803 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
804 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
805 case T_LONG :
806 if (!unaligned && !PatchALot) {
807 __ ldx(base, offset, to_reg->as_register_lo());
808 } else {
809 assert(base != to_reg->as_register_lo(), "can't handle this");
810 assert(O7 != to_reg->as_register_lo(), "can't handle this");
811 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
812 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
813 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
814 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
815 }
816 break;
817 case T_METADATA: __ ld_ptr(base, offset, to_reg->as_register()); break;
818 case T_ADDRESS:
819 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
820 __ lduw(base, offset, to_reg->as_register());
821 __ decode_klass_not_null(to_reg->as_register());
822 } else
823 {
824 __ ld_ptr(base, offset, to_reg->as_register());
825 }
826 break;
827 case T_ARRAY : // fall through
828 case T_OBJECT:
829 {
830 if (UseCompressedOops && !wide) {
831 __ lduw(base, offset, to_reg->as_register());
832 __ decode_heap_oop(to_reg->as_register());
833 } else {
834 __ ld_ptr(base, offset, to_reg->as_register());
835 }
836 break;
837 }
838 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
839 case T_DOUBLE:
840 {
841 FloatRegister reg = to_reg->as_double_reg();
842 // split unaligned loads
864 case T_BOOLEAN: // fall through
865 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
866 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
867 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
868 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
869 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
870 case T_ARRAY : // fall through
871 case T_OBJECT:
872 {
873 if (UseCompressedOops && !wide) {
874 __ lduw(base, disp, to_reg->as_register());
875 __ decode_heap_oop(to_reg->as_register());
876 } else {
877 __ ld_ptr(base, disp, to_reg->as_register());
878 }
879 break;
880 }
881 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
882 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
883 case T_LONG :
884 __ ldx(base, disp, to_reg->as_register_lo());
885 break;
886 default : ShouldNotReachHere();
887 }
888 if (type == T_ARRAY || type == T_OBJECT) {
889 __ verify_oop(to_reg->as_register());
890 }
891 return load_offset;
892 }
893
894 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
895 LIR_Const* c = src->as_constant_ptr();
896 switch (c->type()) {
897 case T_INT:
898 case T_FLOAT: {
899 Register src_reg = O7;
900 int value = c->as_jint_bits();
901 if (value == 0) {
902 src_reg = G0;
903 } else {
904 __ set(value, O7);
1044 if (to_reg->is_single_cpu()) {
1045 assert(patch_code == lir_patch_none, "no patching handled here");
1046 __ set(con, to_reg->as_register());
1047 } else {
1048 ShouldNotReachHere();
1049 assert(to_reg->is_single_fpu(), "wrong register kind");
1050
1051 __ set(con, O7);
1052 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1053 __ st(O7, temp_slot);
1054 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1055 }
1056 }
1057 break;
1058
1059 case T_LONG:
1060 {
1061 jlong con = c->as_jlong();
1062
1063 if (to_reg->is_double_cpu()) {
1064 __ set(con, to_reg->as_register_lo());
1065 } else if (to_reg->is_single_cpu()) {
1066 __ set(con, to_reg->as_register());
1067 } else {
1068 ShouldNotReachHere();
1069 assert(to_reg->is_double_fpu(), "wrong register kind");
1070 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1071 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1072 __ set(low(con), O7);
1073 __ st(O7, temp_slot_lo);
1074 __ set(high(con), O7);
1075 __ st(O7, temp_slot_hi);
1076 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1077 }
1078 }
1079 break;
1080
1081 case T_OBJECT:
1082 {
1083 if (patch_code == lir_patch_none) {
1084 jobject2reg(c->as_jobject(), to_reg->as_register());
1085 } else {
1086 jobject2reg_with_patching(to_reg->as_register(), info);
1120 }
1121 }
1122 break;
1123
1124 case T_DOUBLE:
1125 {
1126 address const_addr = __ double_constant(c->as_jdouble());
1127 if (const_addr == NULL) {
1128 bailout("const section overflow");
1129 break;
1130 }
1131 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1132
1133 if (to_reg->is_double_fpu()) {
1134 AddressLiteral const_addrlit(const_addr, rspec);
1135 __ patchable_sethi(const_addrlit, O7);
1136 __ relocate(rspec);
1137 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1138 } else {
1139 assert(to_reg->is_double_cpu(), "Must be a long register.");
1140 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1141 }
1142
1143 }
1144 break;
1145
1146 default:
1147 ShouldNotReachHere();
1148 }
1149 }
1150
1151 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1152 Register reg = addr->base()->as_pointer_register();
1153 LIR_Opr index = addr->index();
1154 if (index->is_illegal()) {
1155 return Address(reg, addr->disp());
1156 } else {
1157 assert (addr->disp() == 0, "unsupported address mode");
1158 return Address(reg, index->as_pointer_register());
1159 }
1160 }
1291 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1292 }
1293 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1294 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1295 }
1296
1297
1298 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1299 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1300 if (from_reg->is_double_fpu()) {
1301 // double to double moves
1302 assert(to_reg->is_double_fpu(), "should match");
1303 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1304 } else {
1305 // float to float moves
1306 assert(to_reg->is_single_fpu(), "should match");
1307 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1308 }
1309 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1310 if (from_reg->is_double_cpu()) {
1311 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1312 } else if (to_reg->is_double_cpu()) {
1313 // int to int moves
1314 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1315 } else {
1316 // int to int moves
1317 __ mov(from_reg->as_register(), to_reg->as_register());
1318 }
1319 } else {
1320 ShouldNotReachHere();
1321 }
1322 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1323 __ verify_oop(to_reg->as_register());
1324 }
1325 }
1326
1327
1328 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1329 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1330 bool wide, bool unaligned) {
1331 assert(type != T_METADATA, "store of metadata ptr not supported");
1332 LIR_Address* addr = dest->as_address_ptr();
1333
1334 Register src = addr->base()->as_pointer_register();
1374 if (disp_reg == noreg) {
1375 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1376 } else {
1377 assert(!unaligned, "can't handle this");
1378 offset = store(from_reg, src, disp_reg, type, wide);
1379 }
1380
1381 if (patch != NULL) {
1382 patching_epilog(patch, patch_code, src, info);
1383 }
1384
1385 if (info != NULL) add_debug_info_for_null_check(offset, info);
1386 }
1387
1388
1389 void LIR_Assembler::return_op(LIR_Opr result) {
1390 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1391 __ reserved_stack_check();
1392 }
1393 // the poll may need a register so just pick one that isn't the return register
1394 __ set((intptr_t)os::get_polling_page(), L0);
1395 __ relocate(relocInfo::poll_return_type);
1396 __ ld_ptr(L0, 0, G0);
1397 __ ret();
1398 __ delayed()->restore();
1399 }
1400
1401
1402 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1403 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1404 if (info != NULL) {
1405 add_debug_info_for_branch(info);
1406 }
1407 int offset = __ offset();
1408 __ relocate(relocInfo::poll_type);
1409 __ ld_ptr(tmp->as_register(), 0, G0);
1410 return offset;
1411 }
1412
1413
1467 default:
1468 ShouldNotReachHere();
1469 break;
1470 }
1471 } else {
1472 if (opr2->is_address()) {
1473 LIR_Address * addr = opr2->as_address_ptr();
1474 BasicType type = addr->type();
1475 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1476 else __ ld(as_Address(addr), O7);
1477 __ cmp(opr1->as_register(), O7);
1478 } else {
1479 __ cmp(opr1->as_register(), opr2->as_register());
1480 }
1481 }
1482 } else if (opr1->is_double_cpu()) {
1483 Register xlo = opr1->as_register_lo();
1484 Register xhi = opr1->as_register_hi();
1485 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1486 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1487 __ orcc(xhi, G0, G0);
1488 } else if (opr2->is_register()) {
1489 Register ylo = opr2->as_register_lo();
1490 Register yhi = opr2->as_register_hi();
1491 __ cmp(xlo, ylo);
1492 } else {
1493 ShouldNotReachHere();
1494 }
1495 } else if (opr1->is_address()) {
1496 LIR_Address * addr = opr1->as_address_ptr();
1497 BasicType type = addr->type();
1498 assert (opr2->is_constant(), "Checking");
1499 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1500 else __ ld(as_Address(addr), O7);
1501 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1502 } else {
1503 ShouldNotReachHere();
1504 }
1505 }
1506
1507
1508 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1509 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1510 bool is_unordered_less = (code == lir_ucmp_fd2i);
1511 if (left->is_single_fpu()) {
1512 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1513 } else if (left->is_double_fpu()) {
1514 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1515 } else {
1516 ShouldNotReachHere();
1517 }
1518 } else if (code == lir_cmp_l2i) {
1519 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1520 } else {
1521 ShouldNotReachHere();
1522 }
1523 }
1524
1525
1526 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1527 Assembler::Condition acond;
1528 switch (condition) {
1529 case lir_cond_equal: acond = Assembler::equal; break;
1530 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1531 case lir_cond_less: acond = Assembler::less; break;
1532 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1533 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1534 case lir_cond_greater: acond = Assembler::greater; break;
1535 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1536 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1537 default: ShouldNotReachHere();
1538 };
1539
1540 if (opr1->is_constant() && opr1->type() == T_INT) {
1541 Register dest = result->as_register();
1542 // load up first part of constant before branch
1543 // and do the rest in the delay slot.
1544 if (!Assembler::is_simm13(opr1->as_jint())) {
1545 __ sethi(opr1->as_jint(), dest);
1546 }
1547 } else if (opr1->is_constant()) {
1548 const2reg(opr1, result, lir_patch_none, NULL);
1549 } else if (opr1->is_register()) {
1550 reg2reg(opr1, result);
1551 } else if (opr1->is_stack()) {
1552 stack2reg(opr1, result, result->type());
1553 } else {
1554 ShouldNotReachHere();
1555 }
1556 Label skip;
1557 if (type == T_INT) {
1558 __ br(acond, false, Assembler::pt, skip);
1559 } else
1560 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
1561 if (opr1->is_constant() && opr1->type() == T_INT) {
1562 Register dest = result->as_register();
1563 if (Assembler::is_simm13(opr1->as_jint())) {
1564 __ delayed()->or3(G0, opr1->as_jint(), dest);
1565 } else {
1566 // the sethi has been done above, so just put in the low 10 bits
1567 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1568 }
1569 } else {
1570 // can't do anything useful in the delay slot
1571 __ delayed()->nop();
1572 }
1573 if (opr2->is_constant()) {
1574 const2reg(opr2, result, lir_patch_none, NULL);
1575 } else if (opr2->is_register()) {
1576 reg2reg(opr2, result);
1577 } else if (opr2->is_stack()) {
1578 stack2reg(opr2, result, result->type());
1579 } else {
1599 rreg = right->as_float_reg();
1600 res = dest->as_float_reg();
1601 } else {
1602 w = FloatRegisterImpl::D;
1603 lreg = left->as_double_reg();
1604 rreg = right->as_double_reg();
1605 res = dest->as_double_reg();
1606 }
1607
1608 switch (code) {
1609 case lir_add: __ fadd(w, lreg, rreg, res); break;
1610 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1611 case lir_mul: // fall through
1612 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1613 case lir_div: // fall through
1614 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1615 default: ShouldNotReachHere();
1616 }
1617
1618 } else if (dest->is_double_cpu()) {
1619 Register dst_lo = dest->as_register_lo();
1620 Register op1_lo = left->as_pointer_register();
1621 Register op2_lo = right->as_pointer_register();
1622
1623 switch (code) {
1624 case lir_add:
1625 __ add(op1_lo, op2_lo, dst_lo);
1626 break;
1627
1628 case lir_sub:
1629 __ sub(op1_lo, op2_lo, dst_lo);
1630 break;
1631
1632 default: ShouldNotReachHere();
1633 }
1634 } else {
1635 assert (right->is_single_cpu(), "Just Checking");
1636
1637 Register lreg = left->as_register();
1638 Register res = dest->as_register();
1639 Register rreg = right->as_register();
1640 switch (code) {
1641 case lir_add: __ add (lreg, rreg, res); break;
1642 case lir_sub: __ sub (lreg, rreg, res); break;
1643 case lir_mul: __ mulx (lreg, rreg, res); break;
1644 default: ShouldNotReachHere();
1645 }
1646 }
1647 } else {
1648 assert (right->is_constant(), "must be constant");
1649
1650 if (dest->is_single_cpu()) {
1651 Register lreg = left->as_register();
1652 Register res = dest->as_register();
1653 int simm13 = right->as_constant_ptr()->as_jint();
1708 }
1709 }
1710
1711
1712 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1713 if (right->is_constant()) {
1714 if (dest->is_single_cpu()) {
1715 int simm13 = right->as_constant_ptr()->as_jint();
1716 switch (code) {
1717 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1718 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1719 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1720 default: ShouldNotReachHere();
1721 }
1722 } else {
1723 long c = right->as_constant_ptr()->as_jlong();
1724 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1725 int simm13 = (int)c;
1726 switch (code) {
1727 case lir_logic_and:
1728 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1729 break;
1730
1731 case lir_logic_or:
1732 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1733 break;
1734
1735 case lir_logic_xor:
1736 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1737 break;
1738
1739 default: ShouldNotReachHere();
1740 }
1741 }
1742 } else {
1743 assert(right->is_register(), "right should be in register");
1744
1745 if (dest->is_single_cpu()) {
1746 switch (code) {
1747 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1748 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1749 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1750 default: ShouldNotReachHere();
1751 }
1752 } else {
1753 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1754 left->as_register_lo();
1755 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1756 right->as_register_lo();
1757
1758 switch (code) {
1759 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
1760 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
1761 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
1762 default: ShouldNotReachHere();
1763 }
1764 }
1765 }
1766 }
1767
1768
1769 int LIR_Assembler::shift_amount(BasicType t) {
1770 int elem_size = type2aelembytes(t);
1771 switch (elem_size) {
1772 case 1 : return 0;
1773 case 2 : return 1;
1774 case 4 : return 2;
1775 case 8 : return 3;
1776 }
1777 ShouldNotReachHere();
1778 return -1;
1779 }
1780
1781
1782 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1783 assert(exceptionOop->as_register() == Oexception, "should match");
1801 assert(exceptionOop->as_register() == Oexception, "should match");
1802
1803 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
1804 __ delayed()->nop();
1805 }
1806
1807 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1808 Register src = op->src()->as_register();
1809 Register dst = op->dst()->as_register();
1810 Register src_pos = op->src_pos()->as_register();
1811 Register dst_pos = op->dst_pos()->as_register();
1812 Register length = op->length()->as_register();
1813 Register tmp = op->tmp()->as_register();
1814 Register tmp2 = O7;
1815
1816 int flags = op->flags();
1817 ciArrayKlass* default_type = op->expected_type();
1818 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1819 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1820
1821 // higher 32bits must be null
1822 __ sra(dst_pos, 0, dst_pos);
1823 __ sra(src_pos, 0, src_pos);
1824 __ sra(length, 0, length);
1825
1826 // set up the arraycopy stub information
1827 ArrayCopyStub* stub = op->stub();
1828
1829 // always do stub if no type information is available. it's ok if
1830 // the known type isn't loaded since the code sanity checks
1831 // in debug mode and the type isn't required when we know the exact type
1832 // also check that the type is an array type.
1833 if (op->expected_type() == NULL) {
1834 __ mov(src, O0);
1835 __ mov(src_pos, O1);
1836 __ mov(dst, O2);
1837 __ mov(dst_pos, O3);
1838 __ mov(length, O4);
1839 address copyfunc_addr = StubRoutines::generic_arraycopy();
1840
1841 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
1842 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
1843 } else {
1844 #ifndef PRODUCT
2140 } else {
2141 __ sll(dst_pos, shift, tmp);
2142 __ add(dst_ptr, tmp, dst_ptr);
2143 }
2144
2145 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2146 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2147 const char *name;
2148 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2149
2150 // arraycopy stubs takes a length in number of elements, so don't scale it.
2151 __ mov(length, len);
2152 __ call_VM_leaf(tmp, entry);
2153
2154 __ bind(*stub->continuation());
2155 }
2156
2157
2158 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2159 if (dest->is_single_cpu()) {
2160 if (left->type() == T_OBJECT) {
2161 switch (code) {
2162 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2163 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2164 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2165 default: ShouldNotReachHere();
2166 }
2167 } else
2168 switch (code) {
2169 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2170 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2171 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2172 default: ShouldNotReachHere();
2173 }
2174 } else {
2175 switch (code) {
2176 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2177 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2178 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2179 default: ShouldNotReachHere();
2180 }
2181 }
2182 }
2183
2184
2185 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2186 if (left->type() == T_OBJECT) {
2187 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2188 Register l = left->as_register();
2189 Register d = dest->as_register_lo();
2190 switch (code) {
2191 case lir_shl: __ sllx (l, count, d); break;
2192 case lir_shr: __ srax (l, count, d); break;
2193 case lir_ushr: __ srlx (l, count, d); break;
2194 default: ShouldNotReachHere();
2195 }
2196 return;
2197 }
2198
2199 if (dest->is_single_cpu()) {
2200 count = count & 0x1F; // Java spec
2201 switch (code) {
2202 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2203 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2204 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2205 default: ShouldNotReachHere();
2206 }
2207 } else if (dest->is_double_cpu()) {
2208 count = count & 63; // Java spec
2209 switch (code) {
2210 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2211 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2212 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2213 default: ShouldNotReachHere();
2214 }
2215 } else {
2216 ShouldNotReachHere();
2217 }
2559 __ bind(success);
2560 __ set(1, dst);
2561 __ bind(done);
2562 } else {
2563 ShouldNotReachHere();
2564 }
2565
2566 }
2567
2568
2569 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2570 if (op->code() == lir_cas_long) {
2571 assert(VM_Version::supports_cx8(), "wrong machine");
2572 Register addr = op->addr()->as_pointer_register();
2573 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2574 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2575 Register new_value_lo = op->new_value()->as_register_lo();
2576 Register new_value_hi = op->new_value()->as_register_hi();
2577 Register t1 = op->tmp1()->as_register();
2578 Register t2 = op->tmp2()->as_register();
2579 __ mov(cmp_value_lo, t1);
2580 __ mov(new_value_lo, t2);
2581 // perform the compare and swap operation
2582 __ casx(addr, t1, t2);
2583 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2584 // overwritten with the original value in "addr" and will be equal to t1.
2585 __ cmp(t1, t2);
2586 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2587 Register addr = op->addr()->as_pointer_register();
2588 Register cmp_value = op->cmp_value()->as_register();
2589 Register new_value = op->new_value()->as_register();
2590 Register t1 = op->tmp1()->as_register();
2591 Register t2 = op->tmp2()->as_register();
2592 __ mov(cmp_value, t1);
2593 __ mov(new_value, t2);
2594 if (op->code() == lir_cas_obj) {
2595 if (UseCompressedOops) {
2596 __ encode_heap_oop(t1);
2597 __ encode_heap_oop(t2);
2598 __ cas(addr, t1, t2);
2599 } else {
2600 __ cas_ptr(addr, t1, t2);
2601 }
2602 } else {
2603 __ cas(addr, t1, t2);
2604 }
2605 __ cmp(t1, t2);
2707 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2708 __ delayed()->nop();
2709 }
2710 }
2711 __ bind(*op->stub()->continuation());
2712 }
2713
2714
2715 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2716 ciMethod* method = op->profiled_method();
2717 int bci = op->profiled_bci();
2718 ciMethod* callee = op->profiled_callee();
2719
2720 // Update counter for all call types
2721 ciMethodData* md = method->method_data_or_null();
2722 assert(md != NULL, "Sanity");
2723 ciProfileData* data = md->bci_to_data(bci);
2724 assert(data->is_CounterData(), "need CounterData for calls");
2725 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2726 Register mdo = op->mdo()->as_register();
2727 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2728 Register tmp1 = op->tmp1()->as_register_lo();
2729 metadata2reg(md->constant_encoding(), mdo);
2730 int mdo_offset_bias = 0;
2731 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2732 data->size_in_bytes())) {
2733 // The offset is large so bias the mdo by the base of the slot so
2734 // that the ld can use simm13s to reference the slots of the data
2735 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2736 __ set(mdo_offset_bias, O7);
2737 __ add(mdo, O7, mdo);
2738 }
2739
2740 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2741 Bytecodes::Code bc = method->java_code_at_bci(bci);
2742 const bool callee_is_static = callee->is_loaded() && callee->is_static();
2743 // Perform additional virtual call profiling for invokevirtual and
2744 // invokeinterface bytecodes
2745 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2746 !callee_is_static && // required for optimized MH invokes
2747 C1ProfileVirtualCalls) {
2748 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2988 _masm->sub(FP, SP, O7);
2989 _masm->cmp(O7, initial_frame_size_in_bytes());
2990 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
2991 }
2992 }
2993
2994
2995 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
2996 assert(left->is_register(), "can only handle registers");
2997
2998 if (left->is_single_cpu()) {
2999 __ neg(left->as_register(), dest->as_register());
3000 } else if (left->is_single_fpu()) {
3001 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
3002 } else if (left->is_double_fpu()) {
3003 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
3004 } else {
3005 assert (left->is_double_cpu(), "Must be a long");
3006 Register Rlow = left->as_register_lo();
3007 Register Rhi = left->as_register_hi();
3008 __ sub(G0, Rlow, dest->as_register_lo());
3009 }
3010 }
3011
3012
3013 void LIR_Assembler::fxch(int i) {
3014 Unimplemented();
3015 }
3016
3017 void LIR_Assembler::fld(int i) {
3018 Unimplemented();
3019 }
3020
3021 void LIR_Assembler::ffree(int i) {
3022 Unimplemented();
3023 }
3024
3025 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
3026 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3027
3028 // if tmp is invalid, then the function being called doesn't destroy the thread
3029 if (tmp->is_valid()) {
3030 __ save_thread(tmp->as_pointer_register());
3031 }
3032 __ call(dest, relocInfo::runtime_call_type);
3033 __ delayed()->nop();
3034 if (info != NULL) {
3035 add_call_info_here(info);
3036 }
3037 if (tmp->is_valid()) {
3038 __ restore_thread(tmp->as_pointer_register());
3039 }
3040
3041 #ifdef ASSERT
3042 __ verify_thread();
3043 #endif // ASSERT
3044 }
3045
3046
3047 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3048 ShouldNotReachHere();
3049
3050 NEEDS_CLEANUP;
3051 if (type == T_LONG) {
3052 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3053
3054 // (extended to allow indexed as well as constant displaced for JSR-166)
3055 Register idx = noreg; // contains either constant offset or index
3056
3057 int disp = mem_addr->disp();
3058 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
3059 if (!Assembler::is_simm13(disp)) {
3060 idx = O7;
3061 __ set(disp, idx);
3062 }
3063 } else {
3064 assert(disp == 0, "not both indexed and disp");
3065 idx = mem_addr->index()->as_register();
3066 }
3067
3068 int null_check_offset = -1;
3272 prev->result_opr()->as_register() != O0) &&
3273 LIR_Assembler::is_single_instruction(prev)) {
3274 // Only moves without info can be put into the delay slot.
3275 // Also don't allow the setup of the receiver in the delay
3276 // slot for vtable calls.
3277 inst->at_put(i - 1, op);
3278 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3279 #ifndef PRODUCT
3280 if (LIRTracePeephole) {
3281 tty->print_cr("delayed");
3282 inst->at(i - 1)->print();
3283 inst->at(i)->print();
3284 tty->cr();
3285 }
3286 #endif
3287 } else {
3288 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3289 inst->insert_before(i + 1, delay_op);
3290 i++;
3291 }
3292 break;
3293 }
3294 }
3295 }
3296 }
3297
3298 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3299 LIR_Address* addr = src->as_address_ptr();
3300
3301 assert(data == dest, "swap uses only 2 operands");
3302 assert (code == lir_xchg, "no xadd on sparc");
3303
3304 if (data->type() == T_INT) {
3305 __ swap(as_Address(addr), data->as_register());
3306 } else if (data->is_oop()) {
3307 Register obj = data->as_register();
3308 Register narrow = tmp->as_register();
3309 assert(UseCompressedOops, "swap is 32bit only");
3310 __ encode_heap_oop(obj, narrow);
3311 __ swap(as_Address(addr), narrow);
3312 __ decode_heap_oop(narrow, obj);
3313 } else {
3314 ShouldNotReachHere();
3315 }
3316 }
3317
3318 #undef __
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