1 //
2 // Copyright (c) 1998, 2016, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
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10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 // 64-bit build means 64-bit pointers means hi/lo pairs
315 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
316 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
317 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
318 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
319 // Lock encodings use G3 and G4 internally
320 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
321 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
322 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
323 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
324 // Special class for storeP instructions, which can store SP or RPC to TLS.
325 // It is also used for memory addressing, allowing direct TLS addressing.
326 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
327 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
328 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
329 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
330 // R_L7 is the lowest-priority callee-save (i.e., NS) register
331 // We use it to save R_G2 across calls out of Java.
332 reg_class l7_regP(R_L7H,R_L7);
333
334 // Other special pointer regs
335 reg_class g1_regP(R_G1H,R_G1);
336 reg_class g2_regP(R_G2H,R_G2);
337 reg_class g3_regP(R_G3H,R_G3);
338 reg_class g4_regP(R_G4H,R_G4);
339 reg_class g5_regP(R_G5H,R_G5);
340 reg_class i0_regP(R_I0H,R_I0);
341 reg_class o0_regP(R_O0H,R_O0);
342 reg_class o1_regP(R_O1H,R_O1);
343 reg_class o2_regP(R_O2H,R_O2);
344 reg_class o7_regP(R_O7H,R_O7);
345
346
347 // ----------------------------
348 // Long Register Classes
349 // ----------------------------
350 // Longs in 1 register. Aligned adjacent hi/lo pairs.
351 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
352 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
353 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
354 // 64-bit, longs in 1 register: use all 64-bit integer registers
355 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
356 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
357 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
358 );
359
360 reg_class g1_regL(R_G1H,R_G1);
361 reg_class g3_regL(R_G3H,R_G3);
362 reg_class o2_regL(R_O2H,R_O2);
363 reg_class o7_regL(R_O7H,R_O7);
364
365 // ----------------------------
366 // Special Class for Condition Code Flags Register
367 reg_class int_flags(CCR);
368 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
369 reg_class float_flag0(FCC0);
370
371
372 // ----------------------------
373 // Float Point Register Classes
374 // ----------------------------
375 // Skip F30/F31, they are reserved for mem-mem copies
376 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
377
378 // Paired floating point registers--they show up in the same order as the floats,
379 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
380 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
381 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
382 /* Use extra V9 double registers; this AD file does not support V8 */
383 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
384 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
385 );
386
387 // Paired floating point registers--they show up in the same order as the floats,
388 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
389 // This class is usable for mis-aligned loads as happen in I2C adapters.
390 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
391 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
392 %}
393
394 //----------DEFINITION BLOCK---------------------------------------------------
395 // Define name --> value mappings to inform the ADLC of an integer valued name
396 // Current support includes integer values in the range [0, 0x7FFFFFFF]
397 // Format:
398 // int_def <name> ( <int_value>, <expression>);
399 // Generated Code in ad_<arch>.hpp
400 // #define <name> (<expression>)
401 // // value == <int_value>
402 // Generated code in ad_<arch>.cpp adlc_verification()
403 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
404 //
405 definitions %{
406 // The default cost (of an ALU instruction).
407 int_def DEFAULT_COST ( 100, 100);
408 int_def HUGE_COST (1000000, 1000000);
409
410 // Memory refs are twice as expensive as run-of-the-mill.
411 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
412
413 // Branches are even more expensive.
414 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
415 int_def CALL_COST ( 300, DEFAULT_COST * 3);
416 %}
417
418
419 //----------SOURCE BLOCK-------------------------------------------------------
420 // This is a block of C++ code which provides values, functions, and
421 // definitions necessary in the rest of the architecture description
422 source_hpp %{
423 // Header information of the source block.
424 // Method declarations/definitions which are used outside
425 // the ad-scope can conveniently be defined here.
426 //
427 // To keep related declarations/definitions/uses close together,
428 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
429
430 // Must be visible to the DFA in dfa_sparc.cpp
431 extern bool can_branch_register( Node *bol, Node *cmp );
432
433 extern bool use_block_zeroing(Node* count);
434
435 // Macros to extract hi & lo halves from a long pair.
436 // G0 is not part of any long pair, so assert on that.
437 // Prevents accidentally using G1 instead of G0.
438 #define LONG_HI_REG(x) (x)
439 #define LONG_LO_REG(x) (x)
440
441 class CallStubImpl {
442
443 //--------------------------------------------------------------
444 //---< Used for optimization in Compile::Shorten_branches >---
445 //--------------------------------------------------------------
446
447 public:
448 // Size of call trampoline stub.
449 static uint size_call_trampoline() {
450 return 0; // no call trampolines on this platform
451 }
452
453 // number of relocations needed by a call trampoline stub
454 static uint reloc_call_trampoline() {
455 return 0; // no call trampolines on this platform
456 }
457 };
458
459 class HandlerImpl {
460
461 public:
462
463 static int emit_exception_handler(CodeBuffer &cbuf);
464 static int emit_deopt_handler(CodeBuffer& cbuf);
465
466 static uint size_exception_handler() {
467 return ( NativeJump::instruction_size ); // sethi;jmp;nop
468 }
469
470 static uint size_deopt_handler() {
471 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
472 }
473 };
474
475 %}
476
477 source %{
478 #define __ _masm.
479
480 // tertiary op of a LoadP or StoreP encoding
481 #define REGP_OP true
482
483 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
484 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
485 static Register reg_to_register_object(int register_encoding);
486
487 // Used by the DFA in dfa_sparc.cpp.
488 // Check for being able to use a V9 branch-on-register. Requires a
489 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
490 // extended. Doesn't work following an integer ADD, for example, because of
491 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
492 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
493 // replace them with zero, which could become sign-extension in a different OS
494 // release. There's no obvious reason why an interrupt will ever fill these
495 // bits with non-zero junk (the registers are reloaded with standard LD
496 // instructions which either zero-fill or sign-fill).
497 bool can_branch_register( Node *bol, Node *cmp ) {
498 if( !BranchOnRegister ) return false;
499 if( cmp->Opcode() == Op_CmpP )
500 return true; // No problems with pointer compares
501 if( cmp->Opcode() == Op_CmpL )
502 return true; // No problems with long compares
503
504 if( !SparcV9RegsHiBitsZero ) return false;
505 if( bol->as_Bool()->_test._test != BoolTest::ne &&
506 bol->as_Bool()->_test._test != BoolTest::eq )
507 return false;
508
509 // Check for comparing against a 'safe' value. Any operation which
510 // clears out the high word is safe. Thus, loads and certain shifts
511 // are safe, as are non-negative constants. Any operation which
512 // preserves zero bits in the high word is safe as long as each of its
513 // inputs are safe. Thus, phis and bitwise booleans are safe if their
514 // inputs are safe. At present, the only important case to recognize
515 // seems to be loads. Constants should fold away, and shifts &
516 // logicals can use the 'cc' forms.
517 Node *x = cmp->in(1);
518 if( x->is_Load() ) return true;
519 if( x->is_Phi() ) {
520 for( uint i = 1; i < x->req(); i++ )
521 if( !x->in(i)->is_Load() )
522 return false;
523 return true;
524 }
525 return false;
526 }
527
528 bool use_block_zeroing(Node* count) {
529 // Use BIS for zeroing if count is not constant
530 // or it is >= BlockZeroingLowLimit.
531 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
532 }
533
534 // ****************************************************************************
535
536 // REQUIRED FUNCTIONALITY
537
538 // !!!!! Special hack to get all type of calls to specify the byte offset
539 // from the start of the call to the point where the return address
540 // will point.
541 // The "return address" is the address of the call instruction, plus 8.
542
543 int MachCallStaticJavaNode::ret_addr_offset() {
544 int offset = NativeCall::instruction_size; // call; delay slot
545 if (_method_handle_invoke)
546 offset += 4; // restore SP
547 return offset;
548 }
549
550 int MachCallDynamicJavaNode::ret_addr_offset() {
551 int vtable_index = this->_vtable_index;
552 if (vtable_index < 0) {
553 // must be invalid_vtable_index, not nonvirtual_vtable_index
554 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
555 return (NativeMovConstReg::instruction_size +
556 NativeCall::instruction_size); // sethi; setlo; call; delay slot
557 } else {
558 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
559 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
560 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
561 int klass_load_size;
562 if (UseCompressedClassPointers) {
563 assert(Universe::heap() != NULL, "java heap should be initialized");
564 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
565 } else {
566 klass_load_size = 1*BytesPerInstWord;
567 }
568 if (Assembler::is_simm13(v_off)) {
569 return klass_load_size +
570 (2*BytesPerInstWord + // ld_ptr, ld_ptr
571 NativeCall::instruction_size); // call; delay slot
572 } else {
573 return klass_load_size +
574 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
575 NativeCall::instruction_size); // call; delay slot
576 }
577 }
578 }
579
580 int MachCallRuntimeNode::ret_addr_offset() {
581 if (MacroAssembler::is_far_target(entry_point())) {
582 return NativeFarCall::instruction_size;
583 } else {
584 return NativeCall::instruction_size;
585 }
586 }
587
588 // Indicate if the safepoint node needs the polling page as an input.
589 // Since Sparc does not have absolute addressing, it does.
590 bool SafePointNode::needs_polling_address_input() {
591 return true;
592 }
593
594 // emit an interrupt that is caught by the debugger (for debugging compiler)
595 void emit_break(CodeBuffer &cbuf) {
596 MacroAssembler _masm(&cbuf);
597 __ breakpoint_trap();
598 }
599
600 #ifndef PRODUCT
601 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
602 st->print("TA");
603 }
604 #endif
605
606 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
607 emit_break(cbuf);
608 }
609
610 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
611 return MachNode::size(ra_);
612 }
613
614 // Traceable jump
615 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
616 MacroAssembler _masm(&cbuf);
617 Register rdest = reg_to_register_object(jump_target);
618 __ JMP(rdest, 0);
619 __ delayed()->nop();
620 }
621
622 // Traceable jump and set exception pc
623 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
624 MacroAssembler _masm(&cbuf);
625 Register rdest = reg_to_register_object(jump_target);
626 __ JMP(rdest, 0);
627 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
628 }
629
630 void emit_nop(CodeBuffer &cbuf) {
631 MacroAssembler _masm(&cbuf);
632 __ nop();
633 }
634
635 void emit_illtrap(CodeBuffer &cbuf) {
636 MacroAssembler _masm(&cbuf);
637 __ illtrap(0);
638 }
639
640
641 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
642 assert(n->rule() != loadUB_rule, "");
643
644 intptr_t offset = 0;
645 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
646 const Node* addr = n->get_base_and_disp(offset, adr_type);
647 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
648 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
649 assert(addr->bottom_type()->isa_oopptr() == atype, "");
650 atype = atype->add_offset(offset);
651 assert(disp32 == offset, "wrong disp32");
652 return atype->_offset;
653 }
654
655
656 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
657 assert(n->rule() != loadUB_rule, "");
658
659 intptr_t offset = 0;
660 Node* addr = n->in(2);
661 assert(addr->bottom_type()->isa_oopptr() == atype, "");
662 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
663 Node* a = addr->in(2/*AddPNode::Address*/);
664 Node* o = addr->in(3/*AddPNode::Offset*/);
665 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
666 atype = a->bottom_type()->is_ptr()->add_offset(offset);
667 assert(atype->isa_oop_ptr(), "still an oop");
668 }
669 offset = atype->is_ptr()->_offset;
670 if (offset != Type::OffsetBot) offset += disp32;
671 return offset;
672 }
673
674 static inline jlong replicate_immI(int con, int count, int width) {
675 // Load a constant replicated "count" times with width "width"
676 assert(count*width == 8 && width <= 4, "sanity");
677 int bit_width = width * 8;
678 jlong val = con;
679 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
680 for (int i = 0; i < count - 1; i++) {
681 val |= (val << bit_width);
682 }
683 return val;
684 }
685
686 static inline jlong replicate_immF(float con) {
687 // Replicate float con 2 times and pack into vector.
688 int val = *((int*)&con);
689 jlong lval = val;
690 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
691 return lval;
692 }
693
694 // Standard Sparc opcode form2 field breakdown
695 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
696 f0 &= (1<<19)-1; // Mask displacement to 19 bits
697 int op = (f30 << 30) |
698 (f29 << 29) |
699 (f25 << 25) |
700 (f22 << 22) |
701 (f20 << 20) |
702 (f19 << 19) |
703 (f0 << 0);
704 cbuf.insts()->emit_int32(op);
705 }
706
707 // Standard Sparc opcode form2 field breakdown
708 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
709 f0 >>= 10; // Drop 10 bits
710 f0 &= (1<<22)-1; // Mask displacement to 22 bits
711 int op = (f30 << 30) |
712 (f25 << 25) |
713 (f22 << 22) |
714 (f0 << 0);
715 cbuf.insts()->emit_int32(op);
716 }
717
718 // Standard Sparc opcode form3 field breakdown
719 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
720 int op = (f30 << 30) |
721 (f25 << 25) |
722 (f19 << 19) |
723 (f14 << 14) |
724 (f5 << 5) |
725 (f0 << 0);
726 cbuf.insts()->emit_int32(op);
727 }
728
729 // Standard Sparc opcode form3 field breakdown
730 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
731 simm13 &= (1<<13)-1; // Mask to 13 bits
732 int op = (f30 << 30) |
733 (f25 << 25) |
734 (f19 << 19) |
735 (f14 << 14) |
736 (1 << 13) | // bit to indicate immediate-mode
737 (simm13<<0);
738 cbuf.insts()->emit_int32(op);
739 }
740
741 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
742 simm10 &= (1<<10)-1; // Mask to 10 bits
743 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
744 }
745
746 #ifdef ASSERT
747 // Helper function for VerifyOops in emit_form3_mem_reg
748 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
749 warning("VerifyOops encountered unexpected instruction:");
750 n->dump(2);
751 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
752 }
753 #endif
754
755
756 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
757 int src1_enc, int disp32, int src2_enc, int dst_enc) {
758
759 #ifdef ASSERT
760 // The following code implements the +VerifyOops feature.
761 // It verifies oop values which are loaded into or stored out of
762 // the current method activation. +VerifyOops complements techniques
763 // like ScavengeALot, because it eagerly inspects oops in transit,
764 // as they enter or leave the stack, as opposed to ScavengeALot,
765 // which inspects oops "at rest", in the stack or heap, at safepoints.
766 // For this reason, +VerifyOops can sometimes detect bugs very close
767 // to their point of creation. It can also serve as a cross-check
768 // on the validity of oop maps, when used toegether with ScavengeALot.
769
770 // It would be good to verify oops at other points, especially
771 // when an oop is used as a base pointer for a load or store.
772 // This is presently difficult, because it is hard to know when
773 // a base address is biased or not. (If we had such information,
774 // it would be easy and useful to make a two-argument version of
775 // verify_oop which unbiases the base, and performs verification.)
776
777 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
778 bool is_verified_oop_base = false;
779 bool is_verified_oop_load = false;
780 bool is_verified_oop_store = false;
781 int tmp_enc = -1;
782 if (VerifyOops && src1_enc != R_SP_enc) {
783 // classify the op, mainly for an assert check
784 int st_op = 0, ld_op = 0;
785 switch (primary) {
786 case Assembler::stb_op3: st_op = Op_StoreB; break;
787 case Assembler::sth_op3: st_op = Op_StoreC; break;
788 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
789 case Assembler::stw_op3: st_op = Op_StoreI; break;
790 case Assembler::std_op3: st_op = Op_StoreL; break;
791 case Assembler::stf_op3: st_op = Op_StoreF; break;
792 case Assembler::stdf_op3: st_op = Op_StoreD; break;
793
794 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
795 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
796 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
797 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
798 case Assembler::ldx_op3: // may become LoadP or stay LoadI
799 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
800 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
801 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
802 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
803 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
804 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
805
806 default: ShouldNotReachHere();
807 }
808 if (tertiary == REGP_OP) {
809 if (st_op == Op_StoreI) st_op = Op_StoreP;
810 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
811 else ShouldNotReachHere();
812 if (st_op) {
813 // a store
814 // inputs are (0:control, 1:memory, 2:address, 3:value)
815 Node* n2 = n->in(3);
816 if (n2 != NULL) {
817 const Type* t = n2->bottom_type();
818 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
819 }
820 } else {
821 // a load
822 const Type* t = n->bottom_type();
823 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
824 }
825 }
826
827 if (ld_op) {
828 // a Load
829 // inputs are (0:control, 1:memory, 2:address)
830 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
831 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
832 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
833 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
834 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
835 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
836 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
837 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
839 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
840 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
841 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
843 !(n->rule() == loadUB_rule)) {
844 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
845 }
846 } else if (st_op) {
847 // a Store
848 // inputs are (0:control, 1:memory, 2:address, 3:value)
849 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
850 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
851 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
852 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
853 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
854 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
855 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
856 verify_oops_warning(n, n->ideal_Opcode(), st_op);
857 }
858 }
859
860 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
861 Node* addr = n->in(2);
862 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
863 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
864 if (atype != NULL) {
865 intptr_t offset = get_offset_from_base(n, atype, disp32);
866 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
867 if (offset != offset_2) {
868 get_offset_from_base(n, atype, disp32);
869 get_offset_from_base_2(n, atype, disp32);
870 }
871 assert(offset == offset_2, "different offsets");
872 if (offset == disp32) {
873 // we now know that src1 is a true oop pointer
874 is_verified_oop_base = true;
875 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
876 if( primary == Assembler::ldd_op3 ) {
877 is_verified_oop_base = false; // Cannot 'ldd' into O7
878 } else {
879 tmp_enc = dst_enc;
880 dst_enc = R_O7_enc; // Load into O7; preserve source oop
881 assert(src1_enc != dst_enc, "");
882 }
883 }
884 }
885 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
886 || offset == oopDesc::mark_offset_in_bytes())) {
887 // loading the mark should not be allowed either, but
888 // we don't check this since it conflicts with InlineObjectHash
889 // usage of LoadINode to get the mark. We could keep the
890 // check if we create a new LoadMarkNode
891 // but do not verify the object before its header is initialized
892 ShouldNotReachHere();
893 }
894 }
895 }
896 }
897 }
898 #endif
899
900 uint instr = (Assembler::ldst_op << 30)
901 | (dst_enc << 25)
902 | (primary << 19)
903 | (src1_enc << 14);
904
905 uint index = src2_enc;
906 int disp = disp32;
907
908 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
909 disp += STACK_BIAS;
910 // Check that stack offset fits, load into O7 if not
911 if (!Assembler::is_simm13(disp)) {
912 MacroAssembler _masm(&cbuf);
913 __ set(disp, O7);
914 if (index != R_G0_enc) {
915 __ add(O7, reg_to_register_object(index), O7);
916 }
917 index = R_O7_enc;
918 disp = 0;
919 }
920 }
921
922 if( disp == 0 ) {
923 // use reg-reg form
924 // bit 13 is already zero
925 instr |= index;
926 } else {
927 // use reg-imm form
928 instr |= 0x00002000; // set bit 13 to one
929 instr |= disp & 0x1FFF;
930 }
931
932 cbuf.insts()->emit_int32(instr);
933
934 #ifdef ASSERT
935 if (VerifyOops) {
936 MacroAssembler _masm(&cbuf);
937 if (is_verified_oop_base) {
938 __ verify_oop(reg_to_register_object(src1_enc));
939 }
940 if (is_verified_oop_store) {
941 __ verify_oop(reg_to_register_object(dst_enc));
942 }
943 if (tmp_enc != -1) {
944 __ mov(O7, reg_to_register_object(tmp_enc));
945 }
946 if (is_verified_oop_load) {
947 __ verify_oop(reg_to_register_object(dst_enc));
948 }
949 }
950 #endif
951 }
952
953 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) {
954 // The method which records debug information at every safepoint
955 // expects the call to be the first instruction in the snippet as
956 // it creates a PcDesc structure which tracks the offset of a call
957 // from the start of the codeBlob. This offset is computed as
958 // code_end() - code_begin() of the code which has been emitted
959 // so far.
960 // In this particular case we have skirted around the problem by
961 // putting the "mov" instruction in the delay slot but the problem
962 // may bite us again at some other point and a cleaner/generic
963 // solution using relocations would be needed.
964 MacroAssembler _masm(&cbuf);
965 __ set_inst_mark();
966
967 // We flush the current window just so that there is a valid stack copy
968 // the fact that the current window becomes active again instantly is
969 // not a problem there is nothing live in it.
970
971 #ifdef ASSERT
972 int startpos = __ offset();
973 #endif /* ASSERT */
974
975 __ call((address)entry_point, rspec);
976
977 if (preserve_g2) __ delayed()->mov(G2, L7);
978 else __ delayed()->nop();
979
980 if (preserve_g2) __ mov(L7, G2);
981
982 #ifdef ASSERT
983 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
984 // Trash argument dump slots.
985 __ set(0xb0b8ac0db0b8ac0d, G1);
986 __ mov(G1, G5);
987 __ stx(G1, SP, STACK_BIAS + 0x80);
988 __ stx(G1, SP, STACK_BIAS + 0x88);
989 __ stx(G1, SP, STACK_BIAS + 0x90);
990 __ stx(G1, SP, STACK_BIAS + 0x98);
991 __ stx(G1, SP, STACK_BIAS + 0xA0);
992 __ stx(G1, SP, STACK_BIAS + 0xA8);
993 }
994 #endif /*ASSERT*/
995 }
996
997 //=============================================================================
998 // REQUIRED FUNCTIONALITY for encoding
999 void emit_lo(CodeBuffer &cbuf, int val) { }
1000 void emit_hi(CodeBuffer &cbuf, int val) { }
1001
1002
1003 //=============================================================================
1004 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1005
1006 int Compile::ConstantTable::calculate_table_base_offset() const {
1007 if (UseRDPCForConstantTableBase) {
1008 // The table base offset might be less but then it fits into
1009 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1010 return Assembler::min_simm13();
1011 } else {
1012 int offset = -(size() / 2);
1013 if (!Assembler::is_simm13(offset)) {
1014 offset = Assembler::min_simm13();
1015 }
1016 return offset;
1017 }
1018 }
1019
1020 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1021 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1022 ShouldNotReachHere();
1023 }
1024
1025 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1026 Compile* C = ra_->C;
1027 Compile::ConstantTable& constant_table = C->constant_table();
1028 MacroAssembler _masm(&cbuf);
1029
1030 Register r = as_Register(ra_->get_encode(this));
1031 CodeSection* consts_section = __ code()->consts();
1032 int consts_size = consts_section->align_at_start(consts_section->size());
1033 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size);
1034
1035 if (UseRDPCForConstantTableBase) {
1036 // For the following RDPC logic to work correctly the consts
1037 // section must be allocated right before the insts section. This
1038 // assert checks for that. The layout and the SECT_* constants
1039 // are defined in src/share/vm/asm/codeBuffer.hpp.
1040 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1041 int insts_offset = __ offset();
1042
1043 // Layout:
1044 //
1045 // |----------- consts section ------------|----------- insts section -----------...
1046 // |------ constant table -----|- padding -|------------------x----
1047 // \ current PC (RDPC instruction)
1048 // |<------------- consts_size ----------->|<- insts_offset ->|
1049 // \ table base
1050 // The table base offset is later added to the load displacement
1051 // so it has to be negative.
1052 int table_base_offset = -(consts_size + insts_offset);
1053 int disp;
1054
1055 // If the displacement from the current PC to the constant table
1056 // base fits into simm13 we set the constant table base to the
1057 // current PC.
1058 if (Assembler::is_simm13(table_base_offset)) {
1059 constant_table.set_table_base_offset(table_base_offset);
1060 disp = 0;
1061 } else {
1062 // Otherwise we set the constant table base offset to the
1063 // maximum negative displacement of load instructions to keep
1064 // the disp as small as possible:
1065 //
1066 // |<------------- consts_size ----------->|<- insts_offset ->|
1067 // |<--------- min_simm13 --------->|<-------- disp --------->|
1068 // \ table base
1069 table_base_offset = Assembler::min_simm13();
1070 constant_table.set_table_base_offset(table_base_offset);
1071 disp = (consts_size + insts_offset) + table_base_offset;
1072 }
1073
1074 __ rdpc(r);
1075
1076 if (disp != 0) {
1077 assert(r != O7, "need temporary");
1078 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1079 }
1080 }
1081 else {
1082 // Materialize the constant table base.
1083 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1084 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1085 AddressLiteral base(baseaddr, rspec);
1086 __ set(base, r);
1087 }
1088 }
1089
1090 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1091 if (UseRDPCForConstantTableBase) {
1092 // This is really the worst case but generally it's only 1 instruction.
1093 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1094 } else {
1095 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1096 }
1097 }
1098
1099 #ifndef PRODUCT
1100 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1101 char reg[128];
1102 ra_->dump_register(this, reg);
1103 if (UseRDPCForConstantTableBase) {
1104 st->print("RDPC %s\t! constant table base", reg);
1105 } else {
1106 st->print("SET &constanttable,%s\t! constant table base", reg);
1107 }
1108 }
1109 #endif
1110
1111
1112 //=============================================================================
1113
1114 #ifndef PRODUCT
1115 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1116 Compile* C = ra_->C;
1117
1118 for (int i = 0; i < OptoPrologueNops; i++) {
1119 st->print_cr("NOP"); st->print("\t");
1120 }
1121
1122 if( VerifyThread ) {
1123 st->print_cr("Verify_Thread"); st->print("\t");
1124 }
1125
1126 size_t framesize = C->frame_size_in_bytes();
1127 int bangsize = C->bang_size_in_bytes();
1128
1129 // Calls to C2R adapters often do not accept exceptional returns.
1130 // We require that their callers must bang for them. But be careful, because
1131 // some VM calls (such as call site linkage) can use several kilobytes of
1132 // stack. But the stack safety zone should account for that.
1133 // See bugs 4446381, 4468289, 4497237.
1134 if (C->need_stack_bang(bangsize)) {
1135 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1136 }
1137
1138 if (Assembler::is_simm13(-framesize)) {
1139 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1140 } else {
1141 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1142 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1143 st->print ("SAVE R_SP,R_G3,R_SP");
1144 }
1145
1146 }
1147 #endif
1148
1149 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1150 Compile* C = ra_->C;
1151 MacroAssembler _masm(&cbuf);
1152
1153 for (int i = 0; i < OptoPrologueNops; i++) {
1154 __ nop();
1155 }
1156
1157 __ verify_thread();
1158
1159 size_t framesize = C->frame_size_in_bytes();
1160 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1161 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1162 int bangsize = C->bang_size_in_bytes();
1163
1164 // Calls to C2R adapters often do not accept exceptional returns.
1165 // We require that their callers must bang for them. But be careful, because
1166 // some VM calls (such as call site linkage) can use several kilobytes of
1167 // stack. But the stack safety zone should account for that.
1168 // See bugs 4446381, 4468289, 4497237.
1169 if (C->need_stack_bang(bangsize)) {
1170 __ generate_stack_overflow_check(bangsize);
1171 }
1172
1173 if (Assembler::is_simm13(-framesize)) {
1174 __ save(SP, -framesize, SP);
1175 } else {
1176 __ sethi(-framesize & ~0x3ff, G3);
1177 __ add(G3, -framesize & 0x3ff, G3);
1178 __ save(SP, G3, SP);
1179 }
1180 C->set_frame_complete( __ offset() );
1181
1182 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1183 // NOTE: We set the table base offset here because users might be
1184 // emitted before MachConstantBaseNode.
1185 Compile::ConstantTable& constant_table = C->constant_table();
1186 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1187 }
1188 }
1189
1190 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1191 return MachNode::size(ra_);
1192 }
1193
1194 int MachPrologNode::reloc() const {
1195 return 10; // a large enough number
1196 }
1197
1198 //=============================================================================
1199 #ifndef PRODUCT
1200 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1201 Compile* C = ra_->C;
1202
1203 if(do_polling() && ra_->C->is_method_compilation()) {
1204 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1205 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1206 }
1207
1208 if(do_polling()) {
1209 if (UseCBCond && !ra_->C->is_method_compilation()) {
1210 st->print("NOP\n\t");
1211 }
1212 st->print("RET\n\t");
1213 }
1214
1215 st->print("RESTORE");
1216 }
1217 #endif
1218
1219 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1220 MacroAssembler _masm(&cbuf);
1221 Compile* C = ra_->C;
1222
1223 __ verify_thread();
1224
1225 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1226 __ reserved_stack_check();
1227 }
1228
1229 // If this does safepoint polling, then do it here
1230 if(do_polling() && ra_->C->is_method_compilation()) {
1231 AddressLiteral polling_page(os::get_polling_page());
1232 __ sethi(polling_page, L0);
1233 __ relocate(relocInfo::poll_return_type);
1234 __ ld_ptr(L0, 0, G0);
1235 }
1236
1237 // If this is a return, then stuff the restore in the delay slot
1238 if(do_polling()) {
1239 if (UseCBCond && !ra_->C->is_method_compilation()) {
1240 // Insert extra padding for the case when the epilogue is preceded by
1241 // a cbcond jump, which can't be followed by a CTI instruction
1242 __ nop();
1243 }
1244 __ ret();
1245 __ delayed()->restore();
1246 } else {
1247 __ restore();
1248 }
1249 }
1250
1251 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1252 return MachNode::size(ra_);
1253 }
1254
1255 int MachEpilogNode::reloc() const {
1256 return 16; // a large enough number
1257 }
1258
1259 const Pipeline * MachEpilogNode::pipeline() const {
1260 return MachNode::pipeline_class();
1261 }
1262
1263 int MachEpilogNode::safepoint_offset() const {
1264 assert( do_polling(), "no return for this epilog node");
1265 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1266 }
1267
1268 //=============================================================================
1269
1270 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1271 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1272 static enum RC rc_class( OptoReg::Name reg ) {
1273 if (!OptoReg::is_valid(reg)) return rc_bad;
1274 if (OptoReg::is_stack(reg)) return rc_stack;
1275 VMReg r = OptoReg::as_VMReg(reg);
1276 if (r->is_Register()) return rc_int;
1277 assert(r->is_FloatRegister(), "must be");
1278 return rc_float;
1279 }
1280
1281 #ifndef PRODUCT
1282 ATTRIBUTE_PRINTF(2, 3)
1283 static void print_helper(outputStream* st, const char* format, ...) {
1284 if (st->position() > 0) {
1285 st->cr();
1286 st->sp();
1287 }
1288 va_list ap;
1289 va_start(ap, format);
1290 st->vprint(format, ap);
1291 va_end(ap);
1292 }
1293 #endif // !PRODUCT
1294
1295 static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) {
1296 if (cbuf) {
1297 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1298 }
1299 #ifndef PRODUCT
1300 else {
1301 if (is_load) {
1302 print_helper(st, "%s [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg));
1303 } else {
1304 print_helper(st, "%s R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset);
1305 }
1306 }
1307 #endif
1308 }
1309
1310 static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) {
1311 if (cbuf) {
1312 emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]);
1313 }
1314 #ifndef PRODUCT
1315 else {
1316 print_helper(st, "%s R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst));
1317 }
1318 #endif
1319 }
1320
1321 static void mach_spill_copy_implementation_helper(const MachNode* mach,
1322 CodeBuffer *cbuf,
1323 PhaseRegAlloc *ra_,
1324 outputStream* st) {
1325 // Get registers to move
1326 OptoReg::Name src_second = ra_->get_reg_second(mach->in(1));
1327 OptoReg::Name src_first = ra_->get_reg_first(mach->in(1));
1328 OptoReg::Name dst_second = ra_->get_reg_second(mach);
1329 OptoReg::Name dst_first = ra_->get_reg_first(mach);
1330
1331 enum RC src_second_rc = rc_class(src_second);
1332 enum RC src_first_rc = rc_class(src_first);
1333 enum RC dst_second_rc = rc_class(dst_second);
1334 enum RC dst_first_rc = rc_class(dst_first);
1335
1336 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register");
1337
1338 if (src_first == dst_first && src_second == dst_second) {
1339 return; // Self copy, no move
1340 }
1341
1342 // --------------------------------------
1343 // Check for mem-mem move. Load into unused float registers and fall into
1344 // the float-store case.
1345 if (src_first_rc == rc_stack && dst_first_rc == rc_stack) {
1346 int offset = ra_->reg2offset(src_first);
1347 // Further check for aligned-adjacent pair, so we can use a double load
1348 if ((src_first&1) == 0 && src_first+1 == src_second) {
1349 src_second = OptoReg::Name(R_F31_num);
1350 src_second_rc = rc_float;
1351 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st);
1352 } else {
1353 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st);
1354 }
1355 src_first = OptoReg::Name(R_F30_num);
1356 src_first_rc = rc_float;
1357 }
1358
1359 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1360 int offset = ra_->reg2offset(src_second);
1361 impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st);
1362 src_second = OptoReg::Name(R_F31_num);
1363 src_second_rc = rc_float;
1364 }
1365
1366 // --------------------------------------
1367 // Check for float->int copy; requires a trip through memory
1368 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1369 int offset = frame::register_save_words*wordSize;
1370 if (cbuf) {
1371 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16);
1372 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1373 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1374 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16);
1375 }
1376 #ifndef PRODUCT
1377 else {
1378 print_helper(st, "SUB R_SP,16,R_SP");
1379 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1380 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1381 print_helper(st, "ADD R_SP,16,R_SP");
1382 }
1383 #endif
1384 }
1385
1386 // Check for float->int copy on T4
1387 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1388 // Further check for aligned-adjacent pair, so we can use a double move
1389 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1390 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st);
1391 return;
1392 }
1393 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st);
1394 }
1395 // Check for int->float copy on T4
1396 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1397 // Further check for aligned-adjacent pair, so we can use a double move
1398 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1399 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st);
1400 return;
1401 }
1402 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st);
1403 }
1404
1405 // --------------------------------------
1406 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1407 // In such cases, I have to do the big-endian swap. For aligned targets, the
1408 // hardware does the flop for me. Doubles are always aligned, so no problem
1409 // there. Misaligned sources only come from native-long-returns (handled
1410 // special below).
1411
1412 // --------------------------------------
1413 // Check for integer reg-reg copy
1414 if (src_first_rc == rc_int && dst_first_rc == rc_int) {
1415 // Else normal reg-reg copy
1416 assert(src_second != dst_first, "smashed second before evacuating it");
1417 impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV ", st);
1418 assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers");
1419 // This moves an aligned adjacent pair.
1420 // See if we are done.
1421 if (src_first + 1 == src_second && dst_first + 1 == dst_second) {
1422 return;
1423 }
1424 }
1425
1426 // Check for integer store
1427 if (src_first_rc == rc_int && dst_first_rc == rc_stack) {
1428 int offset = ra_->reg2offset(dst_first);
1429 // Further check for aligned-adjacent pair, so we can use a double store
1430 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1431 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st);
1432 return;
1433 }
1434 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st);
1435 }
1436
1437 // Check for integer load
1438 if (dst_first_rc == rc_int && src_first_rc == rc_stack) {
1439 int offset = ra_->reg2offset(src_first);
1440 // Further check for aligned-adjacent pair, so we can use a double load
1441 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1442 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st);
1443 return;
1444 }
1445 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1446 }
1447
1448 // Check for float reg-reg copy
1449 if (src_first_rc == rc_float && dst_first_rc == rc_float) {
1450 // Further check for aligned-adjacent pair, so we can use a double move
1451 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1452 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st);
1453 return;
1454 }
1455 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st);
1456 }
1457
1458 // Check for float store
1459 if (src_first_rc == rc_float && dst_first_rc == rc_stack) {
1460 int offset = ra_->reg2offset(dst_first);
1461 // Further check for aligned-adjacent pair, so we can use a double store
1462 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1463 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st);
1464 return;
1465 }
1466 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1467 }
1468
1469 // Check for float load
1470 if (dst_first_rc == rc_float && src_first_rc == rc_stack) {
1471 int offset = ra_->reg2offset(src_first);
1472 // Further check for aligned-adjacent pair, so we can use a double load
1473 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1474 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st);
1475 return;
1476 }
1477 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st);
1478 }
1479
1480 // --------------------------------------------------------------------
1481 // Check for hi bits still needing moving. Only happens for misaligned
1482 // arguments to native calls.
1483 if (src_second == dst_second) {
1484 return; // Self copy; no move
1485 }
1486 assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad");
1487
1488 Unimplemented();
1489 }
1490
1491 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf,
1492 PhaseRegAlloc *ra_,
1493 bool do_size,
1494 outputStream* st) const {
1495 assert(!do_size, "not supported");
1496 mach_spill_copy_implementation_helper(this, cbuf, ra_, st);
1497 return 0;
1498 }
1499
1500 #ifndef PRODUCT
1501 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1502 implementation( NULL, ra_, false, st );
1503 }
1504 #endif
1505
1506 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1507 implementation( &cbuf, ra_, false, NULL );
1508 }
1509
1510 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1511 return MachNode::size(ra_);
1512 }
1513
1514 //=============================================================================
1515 #ifndef PRODUCT
1516 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const {
1517 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1518 }
1519 #endif
1520
1521 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1522 MacroAssembler _masm(&cbuf);
1523 for (int i = 0; i < _count; i += 1) {
1524 __ nop();
1525 }
1526 }
1527
1528 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1529 return 4 * _count;
1530 }
1531
1532
1533 //=============================================================================
1534 #ifndef PRODUCT
1535 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1536 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1537 int reg = ra_->get_reg_first(this);
1538 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1539 }
1540 #endif
1541
1542 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1543 MacroAssembler _masm(&cbuf);
1544 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1545 int reg = ra_->get_encode(this);
1546
1547 if (Assembler::is_simm13(offset)) {
1548 __ add(SP, offset, reg_to_register_object(reg));
1549 } else {
1550 __ set(offset, O7);
1551 __ add(SP, O7, reg_to_register_object(reg));
1552 }
1553 }
1554
1555 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1556 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1557 assert(ra_ == ra_->C->regalloc(), "sanity");
1558 return ra_->C->scratch_emit_size(this);
1559 }
1560
1561 //=============================================================================
1562 #ifndef PRODUCT
1563 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1564 st->print_cr("\nUEP:");
1565 if (UseCompressedClassPointers) {
1566 assert(Universe::heap() != NULL, "java heap should be initialized");
1567 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1568 if (Universe::narrow_klass_base() != 0) {
1569 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1570 if (Universe::narrow_klass_shift() != 0) {
1571 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1572 }
1573 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1574 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1575 } else {
1576 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1577 }
1578 } else {
1579 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1580 }
1581 st->print_cr("\tCMP R_G5,R_G3" );
1582 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1583 }
1584 #endif
1585
1586 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1587 MacroAssembler _masm(&cbuf);
1588 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1589 Register temp_reg = G3;
1590 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1591
1592 // Load klass from receiver
1593 __ load_klass(O0, temp_reg);
1594 // Compare against expected klass
1595 __ cmp(temp_reg, G5_ic_reg);
1596 // Branch to miss code, checks xcc or icc depending
1597 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1598 }
1599
1600 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1601 return MachNode::size(ra_);
1602 }
1603
1604
1605 //=============================================================================
1606
1607
1608 // Emit exception handler code.
1609 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1610 Register temp_reg = G3;
1611 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1612 MacroAssembler _masm(&cbuf);
1613
1614 address base = __ start_a_stub(size_exception_handler());
1615 if (base == NULL) {
1616 ciEnv::current()->record_failure("CodeCache is full");
1617 return 0; // CodeBuffer::expand failed
1618 }
1619
1620 int offset = __ offset();
1621
1622 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1623 __ delayed()->nop();
1624
1625 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1626
1627 __ end_a_stub();
1628
1629 return offset;
1630 }
1631
1632 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1633 // Can't use any of the current frame's registers as we may have deopted
1634 // at a poll and everything (including G3) can be live.
1635 Register temp_reg = L0;
1636 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1637 MacroAssembler _masm(&cbuf);
1638
1639 address base = __ start_a_stub(size_deopt_handler());
1640 if (base == NULL) {
1641 ciEnv::current()->record_failure("CodeCache is full");
1642 return 0; // CodeBuffer::expand failed
1643 }
1644
1645 int offset = __ offset();
1646 __ save_frame(0);
1647 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1648 __ delayed()->restore();
1649
1650 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1651
1652 __ end_a_stub();
1653 return offset;
1654
1655 }
1656
1657 // Given a register encoding, produce a Integer Register object
1658 static Register reg_to_register_object(int register_encoding) {
1659 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1660 return as_Register(register_encoding);
1661 }
1662
1663 // Given a register encoding, produce a single-precision Float Register object
1664 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1665 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1666 return as_SingleFloatRegister(register_encoding);
1667 }
1668
1669 // Given a register encoding, produce a double-precision Float Register object
1670 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1671 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1672 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1673 return as_DoubleFloatRegister(register_encoding);
1674 }
1675
1676 const bool Matcher::match_rule_supported(int opcode) {
1677 if (!has_match_rule(opcode))
1678 return false;
1679
1680 switch (opcode) {
1681 case Op_CountLeadingZerosI:
1682 case Op_CountLeadingZerosL:
1683 case Op_CountTrailingZerosI:
1684 case Op_CountTrailingZerosL:
1685 case Op_PopCountI:
1686 case Op_PopCountL:
1687 if (!UsePopCountInstruction)
1688 return false;
1689 case Op_CompareAndSwapL:
1690 case Op_CompareAndSwapP:
1691 if (!VM_Version::supports_cx8())
1692 return false;
1693 break;
1694 }
1695
1696 return true; // Per default match rules are supported.
1697 }
1698
1699 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1700
1701 // TODO
1702 // identify extra cases that we might want to provide match rules for
1703 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1704 bool ret_value = match_rule_supported(opcode);
1705 // Add rules here.
1706
1707 return ret_value; // Per default match rules are supported.
1708 }
1709
1710 const bool Matcher::has_predicated_vectors(void) {
1711 return false;
1712 }
1713
1714 const int Matcher::float_pressure(int default_pressure_threshold) {
1715 return default_pressure_threshold;
1716 }
1717
1718 int Matcher::regnum_to_fpu_offset(int regnum) {
1719 return regnum - 32; // The FP registers are in the second chunk
1720 }
1721
1722 #ifdef ASSERT
1723 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1724 #endif
1725
1726 // Vector width in bytes
1727 const int Matcher::vector_width_in_bytes(BasicType bt) {
1728 assert(MaxVectorSize == 8, "");
1729 return 8;
1730 }
1731
1732 // Vector ideal reg
1733 const int Matcher::vector_ideal_reg(int size) {
1734 assert(MaxVectorSize == 8, "");
1735 return Op_RegD;
1736 }
1737
1738 const int Matcher::vector_shift_count_ideal_reg(int size) {
1739 fatal("vector shift is not supported");
1740 return Node::NotAMachineReg;
1741 }
1742
1743 // Limits on vector size (number of elements) loaded into vector.
1744 const int Matcher::max_vector_size(const BasicType bt) {
1745 assert(is_java_primitive(bt), "only primitive type vectors");
1746 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1747 }
1748
1749 const int Matcher::min_vector_size(const BasicType bt) {
1750 return max_vector_size(bt); // Same as max.
1751 }
1752
1753 // SPARC doesn't support misaligned vectors store/load.
1754 const bool Matcher::misaligned_vectors_ok() {
1755 return false;
1756 }
1757
1758 // Current (2013) SPARC platforms need to read original key
1759 // to construct decryption expanded key
1760 const bool Matcher::pass_original_key_for_aes() {
1761 return true;
1762 }
1763
1764 // USII supports fxtof through the whole range of number, USIII doesn't
1765 const bool Matcher::convL2FSupported(void) {
1766 return VM_Version::has_fast_fxtof();
1767 }
1768
1769 // Is this branch offset short enough that a short branch can be used?
1770 //
1771 // NOTE: If the platform does not provide any short branch variants, then
1772 // this method should return false for offset 0.
1773 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1774 // The passed offset is relative to address of the branch.
1775 // Don't need to adjust the offset.
1776 return UseCBCond && Assembler::is_simm12(offset);
1777 }
1778
1779 const bool Matcher::isSimpleConstant64(jlong value) {
1780 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1781 // Depends on optimizations in MacroAssembler::setx.
1782 int hi = (int)(value >> 32);
1783 int lo = (int)(value & ~0);
1784 return (hi == 0) || (hi == -1) || (lo == 0);
1785 }
1786
1787 // No scaling for the parameter the ClearArray node.
1788 const bool Matcher::init_array_count_is_in_bytes = true;
1789
1790 // No additional cost for CMOVL.
1791 const int Matcher::long_cmove_cost() { return 0; }
1792
1793 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1794 const int Matcher::float_cmove_cost() {
1795 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1796 }
1797
1798 // Does the CPU require late expand (see block.cpp for description of late expand)?
1799 const bool Matcher::require_postalloc_expand = false;
1800
1801 // Do we need to mask the count passed to shift instructions or does
1802 // the cpu only look at the lower 5/6 bits anyway?
1803 const bool Matcher::need_masked_shift_count = false;
1804
1805 bool Matcher::narrow_oop_use_complex_address() {
1806 NOT_LP64(ShouldNotCallThis());
1807 assert(UseCompressedOops, "only for compressed oops code");
1808 return false;
1809 }
1810
1811 bool Matcher::narrow_klass_use_complex_address() {
1812 NOT_LP64(ShouldNotCallThis());
1813 assert(UseCompressedClassPointers, "only for compressed klass code");
1814 return false;
1815 }
1816
1817 bool Matcher::const_oop_prefer_decode() {
1818 // TODO: Check if loading ConP from TOC in heap-based mode is better:
1819 // Prefer ConN+DecodeN over ConP in simple compressed oops mode.
1820 // return Universe::narrow_oop_base() == NULL;
1821 return true;
1822 }
1823
1824 bool Matcher::const_klass_prefer_decode() {
1825 // TODO: Check if loading ConP from TOC in heap-based mode is better:
1826 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1827 // return Universe::narrow_klass_base() == NULL;
1828 return true;
1829 }
1830
1831 // Is it better to copy float constants, or load them directly from memory?
1832 // Intel can load a float constant from a direct address, requiring no
1833 // extra registers. Most RISCs will have to materialize an address into a
1834 // register first, so they would do better to copy the constant from stack.
1835 const bool Matcher::rematerialize_float_constants = false;
1836
1837 // If CPU can load and store mis-aligned doubles directly then no fixup is
1838 // needed. Else we split the double into 2 integer pieces and move it
1839 // piece-by-piece. Only happens when passing doubles into C code as the
1840 // Java calling convention forces doubles to be aligned.
1841 const bool Matcher::misaligned_doubles_ok = true;
1842
1843 // No-op on SPARC.
1844 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1845 }
1846
1847 // Advertise here if the CPU requires explicit rounding operations
1848 // to implement the UseStrictFP mode.
1849 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1850
1851 // Are floats converted to double when stored to stack during deoptimization?
1852 // Sparc does not handle callee-save floats.
1853 bool Matcher::float_in_double() { return false; }
1854
1855 // Do ints take an entire long register or just half?
1856 // Note that we if-def off of _LP64.
1857 // The relevant question is how the int is callee-saved. In _LP64
1858 // the whole long is written but de-opt'ing will have to extract
1859 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1860 const bool Matcher::int_in_long = true;
1861
1862 // Return whether or not this register is ever used as an argument. This
1863 // function is used on startup to build the trampoline stubs in generateOptoStub.
1864 // Registers not mentioned will be killed by the VM call in the trampoline, and
1865 // arguments in those registers not be available to the callee.
1866 bool Matcher::can_be_java_arg( int reg ) {
1867 // Standard sparc 6 args in registers
1868 if( reg == R_I0_num ||
1869 reg == R_I1_num ||
1870 reg == R_I2_num ||
1871 reg == R_I3_num ||
1872 reg == R_I4_num ||
1873 reg == R_I5_num ) return true;
1874 // 64-bit builds can pass 64-bit pointers and longs in
1875 // the high I registers
1876 if( reg == R_I0H_num ||
1877 reg == R_I1H_num ||
1878 reg == R_I2H_num ||
1879 reg == R_I3H_num ||
1880 reg == R_I4H_num ||
1881 reg == R_I5H_num ) return true;
1882
1883 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1884 return true;
1885 }
1886
1887 // A few float args in registers
1888 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1889
1890 return false;
1891 }
1892
1893 bool Matcher::is_spillable_arg( int reg ) {
1894 return can_be_java_arg(reg);
1895 }
1896
1897 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1898 // Use hardware SDIVX instruction when it is
1899 // faster than a code which use multiply.
1900 return VM_Version::has_fast_idiv();
1901 }
1902
1903 // Register for DIVI projection of divmodI
1904 RegMask Matcher::divI_proj_mask() {
1905 ShouldNotReachHere();
1906 return RegMask();
1907 }
1908
1909 // Register for MODI projection of divmodI
1910 RegMask Matcher::modI_proj_mask() {
1911 ShouldNotReachHere();
1912 return RegMask();
1913 }
1914
1915 // Register for DIVL projection of divmodL
1916 RegMask Matcher::divL_proj_mask() {
1917 ShouldNotReachHere();
1918 return RegMask();
1919 }
1920
1921 // Register for MODL projection of divmodL
1922 RegMask Matcher::modL_proj_mask() {
1923 ShouldNotReachHere();
1924 return RegMask();
1925 }
1926
1927 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1928 return L7_REGP_mask();
1929 }
1930
1931
1932 const bool Matcher::convi2l_type_required = true;
1933
1934 // Should the Matcher clone shifts on addressing modes, expecting them
1935 // to be subsumed into complex addressing expressions or compute them
1936 // into registers?
1937 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
1938 return clone_base_plus_offset_address(m, mstack, address_visited);
1939 }
1940
1941 void Compile::reshape_address(AddPNode* addp) {
1942 }
1943
1944 %}
1945
1946
1947 // The intptr_t operand types, defined by textual substitution.
1948 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1949 #define immX immL
1950 #define immX13 immL13
1951 #define immX13m7 immL13m7
1952 #define iRegX iRegL
1953 #define g1RegX g1RegL
1954
1955 //----------ENCODING BLOCK-----------------------------------------------------
1956 // This block specifies the encoding classes used by the compiler to output
1957 // byte streams. Encoding classes are parameterized macros used by
1958 // Machine Instruction Nodes in order to generate the bit encoding of the
1959 // instruction. Operands specify their base encoding interface with the
1960 // interface keyword. There are currently supported four interfaces,
1961 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1962 // operand to generate a function which returns its register number when
1963 // queried. CONST_INTER causes an operand to generate a function which
1964 // returns the value of the constant when queried. MEMORY_INTER causes an
1965 // operand to generate four functions which return the Base Register, the
1966 // Index Register, the Scale Value, and the Offset Value of the operand when
1967 // queried. COND_INTER causes an operand to generate six functions which
1968 // return the encoding code (ie - encoding bits for the instruction)
1969 // associated with each basic boolean condition for a conditional instruction.
1970 //
1971 // Instructions specify two basic values for encoding. Again, a function
1972 // is available to check if the constant displacement is an oop. They use the
1973 // ins_encode keyword to specify their encoding classes (which must be
1974 // a sequence of enc_class names, and their parameters, specified in
1975 // the encoding block), and they use the
1976 // opcode keyword to specify, in order, their primary, secondary, and
1977 // tertiary opcode. Only the opcode sections which a particular instruction
1978 // needs for encoding need to be specified.
1979 encode %{
1980 enc_class enc_untested %{
1981 #ifdef ASSERT
1982 MacroAssembler _masm(&cbuf);
1983 __ untested("encoding");
1984 #endif
1985 %}
1986
1987 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
1988 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
1989 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1990 %}
1991
1992 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
1993 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
1994 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1995 %}
1996
1997 enc_class form3_mem_prefetch_read( memory mem ) %{
1998 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
1999 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2000 %}
2001
2002 enc_class form3_mem_prefetch_write( memory mem ) %{
2003 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2004 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2005 %}
2006
2007 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2008 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2009 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2010 guarantee($mem$$index == R_G0_enc, "double index?");
2011 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2012 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2013 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2014 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2015 %}
2016
2017 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2018 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2019 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2020 guarantee($mem$$index == R_G0_enc, "double index?");
2021 // Load long with 2 instructions
2022 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2023 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2024 %}
2025
2026 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2027 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2028 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2029 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2030 %}
2031
2032 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2033 // Encode a reg-reg copy. If it is useless, then empty encoding.
2034 if( $rs2$$reg != $rd$$reg )
2035 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2036 %}
2037
2038 // Target lo half of long
2039 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2040 // Encode a reg-reg copy. If it is useless, then empty encoding.
2041 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2042 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2043 %}
2044
2045 // Source lo half of long
2046 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2047 // Encode a reg-reg copy. If it is useless, then empty encoding.
2048 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2049 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2050 %}
2051
2052 // Target hi half of long
2053 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2054 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2055 %}
2056
2057 // Source lo half of long, and leave it sign extended.
2058 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2059 // Sign extend low half
2060 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2061 %}
2062
2063 // Source hi half of long, and leave it sign extended.
2064 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2065 // Shift high half to low half
2066 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2067 %}
2068
2069 // Source hi half of long
2070 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2071 // Encode a reg-reg copy. If it is useless, then empty encoding.
2072 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2073 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2074 %}
2075
2076 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2077 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2078 %}
2079
2080 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2081 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2082 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2083 %}
2084
2085 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2086 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2087 // clear if nothing else is happening
2088 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2089 // blt,a,pn done
2090 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2091 // mov dst,-1 in delay slot
2092 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2093 %}
2094
2095 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2096 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2097 %}
2098
2099 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2100 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2101 %}
2102
2103 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2104 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2105 %}
2106
2107 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2108 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2109 %}
2110
2111 enc_class move_return_pc_to_o1() %{
2112 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2113 %}
2114
2115 /* %%% merge with enc_to_bool */
2116 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2117 MacroAssembler _masm(&cbuf);
2118
2119 Register src_reg = reg_to_register_object($src$$reg);
2120 Register dst_reg = reg_to_register_object($dst$$reg);
2121 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2122 %}
2123
2124 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2125 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2126 MacroAssembler _masm(&cbuf);
2127
2128 Register p_reg = reg_to_register_object($p$$reg);
2129 Register q_reg = reg_to_register_object($q$$reg);
2130 Register y_reg = reg_to_register_object($y$$reg);
2131 Register tmp_reg = reg_to_register_object($tmp$$reg);
2132
2133 __ subcc( p_reg, q_reg, p_reg );
2134 __ add ( p_reg, y_reg, tmp_reg );
2135 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2136 %}
2137
2138 enc_class form_d2i_helper(regD src, regF dst) %{
2139 // fcmp %fcc0,$src,$src
2140 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2141 // branch %fcc0 not-nan, predict taken
2142 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2143 // fdtoi $src,$dst
2144 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2145 // fitos $dst,$dst (if nan)
2146 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2147 // clear $dst (if nan)
2148 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2149 // carry on here...
2150 %}
2151
2152 enc_class form_d2l_helper(regD src, regD dst) %{
2153 // fcmp %fcc0,$src,$src check for NAN
2154 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2155 // branch %fcc0 not-nan, predict taken
2156 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2157 // fdtox $src,$dst convert in delay slot
2158 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2159 // fxtod $dst,$dst (if nan)
2160 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2161 // clear $dst (if nan)
2162 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2163 // carry on here...
2164 %}
2165
2166 enc_class form_f2i_helper(regF src, regF dst) %{
2167 // fcmps %fcc0,$src,$src
2168 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2169 // branch %fcc0 not-nan, predict taken
2170 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2171 // fstoi $src,$dst
2172 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2173 // fitos $dst,$dst (if nan)
2174 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2175 // clear $dst (if nan)
2176 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2177 // carry on here...
2178 %}
2179
2180 enc_class form_f2l_helper(regF src, regD dst) %{
2181 // fcmps %fcc0,$src,$src
2182 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2183 // branch %fcc0 not-nan, predict taken
2184 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2185 // fstox $src,$dst
2186 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2187 // fxtod $dst,$dst (if nan)
2188 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2189 // clear $dst (if nan)
2190 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2191 // carry on here...
2192 %}
2193
2194 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2195 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2196 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2197 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2198
2199 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2200
2201 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2202 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2203
2204 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2205 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2206 %}
2207
2208 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2209 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2210 %}
2211
2212 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2213 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2214 %}
2215
2216 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2217 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2218 %}
2219
2220 enc_class form3_convI2F(regF rs2, regF rd) %{
2221 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2222 %}
2223
2224 // Encloding class for traceable jumps
2225 enc_class form_jmpl(g3RegP dest) %{
2226 emit_jmpl(cbuf, $dest$$reg);
2227 %}
2228
2229 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2230 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2231 %}
2232
2233 enc_class form2_nop() %{
2234 emit_nop(cbuf);
2235 %}
2236
2237 enc_class form2_illtrap() %{
2238 emit_illtrap(cbuf);
2239 %}
2240
2241
2242 // Compare longs and convert into -1, 0, 1.
2243 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2244 // CMP $src1,$src2
2245 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2246 // blt,a,pn done
2247 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2248 // mov dst,-1 in delay slot
2249 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2250 // bgt,a,pn done
2251 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2252 // mov dst,1 in delay slot
2253 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2254 // CLR $dst
2255 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2256 %}
2257
2258 enc_class enc_PartialSubtypeCheck() %{
2259 MacroAssembler _masm(&cbuf);
2260 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2261 __ delayed()->nop();
2262 %}
2263
2264 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2265 MacroAssembler _masm(&cbuf);
2266 Label* L = $labl$$label;
2267 Assembler::Predict predict_taken =
2268 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2269
2270 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2271 __ delayed()->nop();
2272 %}
2273
2274 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2275 MacroAssembler _masm(&cbuf);
2276 Label* L = $labl$$label;
2277 Assembler::Predict predict_taken =
2278 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2279
2280 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2281 __ delayed()->nop();
2282 %}
2283
2284 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2285 int op = (Assembler::arith_op << 30) |
2286 ($dst$$reg << 25) |
2287 (Assembler::movcc_op3 << 19) |
2288 (1 << 18) | // cc2 bit for 'icc'
2289 ($cmp$$cmpcode << 14) |
2290 (0 << 13) | // select register move
2291 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2292 ($src$$reg << 0);
2293 cbuf.insts()->emit_int32(op);
2294 %}
2295
2296 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2297 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2298 int op = (Assembler::arith_op << 30) |
2299 ($dst$$reg << 25) |
2300 (Assembler::movcc_op3 << 19) |
2301 (1 << 18) | // cc2 bit for 'icc'
2302 ($cmp$$cmpcode << 14) |
2303 (1 << 13) | // select immediate move
2304 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2305 (simm11 << 0);
2306 cbuf.insts()->emit_int32(op);
2307 %}
2308
2309 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2310 int op = (Assembler::arith_op << 30) |
2311 ($dst$$reg << 25) |
2312 (Assembler::movcc_op3 << 19) |
2313 (0 << 18) | // cc2 bit for 'fccX'
2314 ($cmp$$cmpcode << 14) |
2315 (0 << 13) | // select register move
2316 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2317 ($src$$reg << 0);
2318 cbuf.insts()->emit_int32(op);
2319 %}
2320
2321 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2322 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2323 int op = (Assembler::arith_op << 30) |
2324 ($dst$$reg << 25) |
2325 (Assembler::movcc_op3 << 19) |
2326 (0 << 18) | // cc2 bit for 'fccX'
2327 ($cmp$$cmpcode << 14) |
2328 (1 << 13) | // select immediate move
2329 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2330 (simm11 << 0);
2331 cbuf.insts()->emit_int32(op);
2332 %}
2333
2334 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2335 int op = (Assembler::arith_op << 30) |
2336 ($dst$$reg << 25) |
2337 (Assembler::fpop2_op3 << 19) |
2338 (0 << 18) |
2339 ($cmp$$cmpcode << 14) |
2340 (1 << 13) | // select register move
2341 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2342 ($primary << 5) | // select single, double or quad
2343 ($src$$reg << 0);
2344 cbuf.insts()->emit_int32(op);
2345 %}
2346
2347 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2348 int op = (Assembler::arith_op << 30) |
2349 ($dst$$reg << 25) |
2350 (Assembler::fpop2_op3 << 19) |
2351 (0 << 18) |
2352 ($cmp$$cmpcode << 14) |
2353 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2354 ($primary << 5) | // select single, double or quad
2355 ($src$$reg << 0);
2356 cbuf.insts()->emit_int32(op);
2357 %}
2358
2359 // Used by the MIN/MAX encodings. Same as a CMOV, but
2360 // the condition comes from opcode-field instead of an argument.
2361 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2362 int op = (Assembler::arith_op << 30) |
2363 ($dst$$reg << 25) |
2364 (Assembler::movcc_op3 << 19) |
2365 (1 << 18) | // cc2 bit for 'icc'
2366 ($primary << 14) |
2367 (0 << 13) | // select register move
2368 (0 << 11) | // cc1, cc0 bits for 'icc'
2369 ($src$$reg << 0);
2370 cbuf.insts()->emit_int32(op);
2371 %}
2372
2373 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2374 int op = (Assembler::arith_op << 30) |
2375 ($dst$$reg << 25) |
2376 (Assembler::movcc_op3 << 19) |
2377 (6 << 16) | // cc2 bit for 'xcc'
2378 ($primary << 14) |
2379 (0 << 13) | // select register move
2380 (0 << 11) | // cc1, cc0 bits for 'icc'
2381 ($src$$reg << 0);
2382 cbuf.insts()->emit_int32(op);
2383 %}
2384
2385 enc_class Set13( immI13 src, iRegI rd ) %{
2386 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2387 %}
2388
2389 enc_class SetHi22( immI src, iRegI rd ) %{
2390 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2391 %}
2392
2393 enc_class Set32( immI src, iRegI rd ) %{
2394 MacroAssembler _masm(&cbuf);
2395 __ set($src$$constant, reg_to_register_object($rd$$reg));
2396 %}
2397
2398 enc_class call_epilog %{
2399 if( VerifyStackAtCalls ) {
2400 MacroAssembler _masm(&cbuf);
2401 int framesize = ra_->C->frame_size_in_bytes();
2402 Register temp_reg = G3;
2403 __ add(SP, framesize, temp_reg);
2404 __ cmp(temp_reg, FP);
2405 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2406 }
2407 %}
2408
2409 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2410 // to G1 so the register allocator will not have to deal with the misaligned register
2411 // pair.
2412 enc_class adjust_long_from_native_call %{
2413 %}
2414
2415 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2416 // CALL directly to the runtime
2417 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2418 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true);
2419 %}
2420
2421 enc_class preserve_SP %{
2422 MacroAssembler _masm(&cbuf);
2423 __ mov(SP, L7_mh_SP_save);
2424 %}
2425
2426 enc_class restore_SP %{
2427 MacroAssembler _masm(&cbuf);
2428 __ mov(L7_mh_SP_save, SP);
2429 %}
2430
2431 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2432 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2433 // who we intended to call.
2434 if (!_method) {
2435 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec());
2436 } else {
2437 int method_index = resolved_method_index(cbuf);
2438 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2439 : static_call_Relocation::spec(method_index);
2440 emit_call_reloc(cbuf, $meth$$method, rspec);
2441
2442 // Emit stub for static call.
2443 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2444 if (stub == NULL) {
2445 ciEnv::current()->record_failure("CodeCache is full");
2446 return;
2447 }
2448 }
2449 %}
2450
2451 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2452 MacroAssembler _masm(&cbuf);
2453 __ set_inst_mark();
2454 int vtable_index = this->_vtable_index;
2455 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2456 if (vtable_index < 0) {
2457 // must be invalid_vtable_index, not nonvirtual_vtable_index
2458 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2459 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2460 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2461 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2462 __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf));
2463 } else {
2464 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2465 // Just go thru the vtable
2466 // get receiver klass (receiver already checked for non-null)
2467 // If we end up going thru a c2i adapter interpreter expects method in G5
2468 int off = __ offset();
2469 __ load_klass(O0, G3_scratch);
2470 int klass_load_size;
2471 if (UseCompressedClassPointers) {
2472 assert(Universe::heap() != NULL, "java heap should be initialized");
2473 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2474 } else {
2475 klass_load_size = 1*BytesPerInstWord;
2476 }
2477 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
2478 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
2479 if (Assembler::is_simm13(v_off)) {
2480 __ ld_ptr(G3, v_off, G5_method);
2481 } else {
2482 // Generate 2 instructions
2483 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2484 __ or3(G5_method, v_off & 0x3ff, G5_method);
2485 // ld_ptr, set_hi, set
2486 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2487 "Unexpected instruction size(s)");
2488 __ ld_ptr(G3, G5_method, G5_method);
2489 }
2490 // NOTE: for vtable dispatches, the vtable entry will never be null.
2491 // However it may very well end up in handle_wrong_method if the
2492 // method is abstract for the particular class.
2493 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2494 // jump to target (either compiled code or c2iadapter)
2495 __ jmpl(G3_scratch, G0, O7);
2496 __ delayed()->nop();
2497 }
2498 %}
2499
2500 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2501 MacroAssembler _masm(&cbuf);
2502
2503 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2504 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2505 // we might be calling a C2I adapter which needs it.
2506
2507 assert(temp_reg != G5_ic_reg, "conflicting registers");
2508 // Load nmethod
2509 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2510
2511 // CALL to compiled java, indirect the contents of G3
2512 __ set_inst_mark();
2513 __ callr(temp_reg, G0);
2514 __ delayed()->nop();
2515 %}
2516
2517 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2518 MacroAssembler _masm(&cbuf);
2519 Register Rdividend = reg_to_register_object($src1$$reg);
2520 Register Rdivisor = reg_to_register_object($src2$$reg);
2521 Register Rresult = reg_to_register_object($dst$$reg);
2522
2523 __ sra(Rdivisor, 0, Rdivisor);
2524 __ sra(Rdividend, 0, Rdividend);
2525 __ sdivx(Rdividend, Rdivisor, Rresult);
2526 %}
2527
2528 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2529 MacroAssembler _masm(&cbuf);
2530
2531 Register Rdividend = reg_to_register_object($src1$$reg);
2532 int divisor = $imm$$constant;
2533 Register Rresult = reg_to_register_object($dst$$reg);
2534
2535 __ sra(Rdividend, 0, Rdividend);
2536 __ sdivx(Rdividend, divisor, Rresult);
2537 %}
2538
2539 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2540 MacroAssembler _masm(&cbuf);
2541 Register Rsrc1 = reg_to_register_object($src1$$reg);
2542 Register Rsrc2 = reg_to_register_object($src2$$reg);
2543 Register Rdst = reg_to_register_object($dst$$reg);
2544
2545 __ sra( Rsrc1, 0, Rsrc1 );
2546 __ sra( Rsrc2, 0, Rsrc2 );
2547 __ mulx( Rsrc1, Rsrc2, Rdst );
2548 __ srlx( Rdst, 32, Rdst );
2549 %}
2550
2551 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2552 MacroAssembler _masm(&cbuf);
2553 Register Rdividend = reg_to_register_object($src1$$reg);
2554 Register Rdivisor = reg_to_register_object($src2$$reg);
2555 Register Rresult = reg_to_register_object($dst$$reg);
2556 Register Rscratch = reg_to_register_object($scratch$$reg);
2557
2558 assert(Rdividend != Rscratch, "");
2559 assert(Rdivisor != Rscratch, "");
2560
2561 __ sra(Rdividend, 0, Rdividend);
2562 __ sra(Rdivisor, 0, Rdivisor);
2563 __ sdivx(Rdividend, Rdivisor, Rscratch);
2564 __ mulx(Rscratch, Rdivisor, Rscratch);
2565 __ sub(Rdividend, Rscratch, Rresult);
2566 %}
2567
2568 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2569 MacroAssembler _masm(&cbuf);
2570
2571 Register Rdividend = reg_to_register_object($src1$$reg);
2572 int divisor = $imm$$constant;
2573 Register Rresult = reg_to_register_object($dst$$reg);
2574 Register Rscratch = reg_to_register_object($scratch$$reg);
2575
2576 assert(Rdividend != Rscratch, "");
2577
2578 __ sra(Rdividend, 0, Rdividend);
2579 __ sdivx(Rdividend, divisor, Rscratch);
2580 __ mulx(Rscratch, divisor, Rscratch);
2581 __ sub(Rdividend, Rscratch, Rresult);
2582 %}
2583
2584 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2585 MacroAssembler _masm(&cbuf);
2586
2587 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2588 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2589
2590 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2591 %}
2592
2593 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2594 MacroAssembler _masm(&cbuf);
2595
2596 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2597 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2598
2599 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2600 %}
2601
2602 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2603 MacroAssembler _masm(&cbuf);
2604
2605 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2606 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2607
2608 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2609 %}
2610
2611 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2612 MacroAssembler _masm(&cbuf);
2613
2614 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2615 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2616
2617 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2618 %}
2619
2620 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2621 MacroAssembler _masm(&cbuf);
2622
2623 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2624 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2625
2626 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2627 %}
2628
2629 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2630 MacroAssembler _masm(&cbuf);
2631
2632 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2633 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2634
2635 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2636 %}
2637
2638 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2639 MacroAssembler _masm(&cbuf);
2640
2641 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2642 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2643
2644 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2645 %}
2646
2647 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2648 MacroAssembler _masm(&cbuf);
2649
2650 Register Roop = reg_to_register_object($oop$$reg);
2651 Register Rbox = reg_to_register_object($box$$reg);
2652 Register Rscratch = reg_to_register_object($scratch$$reg);
2653 Register Rmark = reg_to_register_object($scratch2$$reg);
2654
2655 assert(Roop != Rscratch, "");
2656 assert(Roop != Rmark, "");
2657 assert(Rbox != Rscratch, "");
2658 assert(Rbox != Rmark, "");
2659
2660 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2661 %}
2662
2663 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2664 MacroAssembler _masm(&cbuf);
2665
2666 Register Roop = reg_to_register_object($oop$$reg);
2667 Register Rbox = reg_to_register_object($box$$reg);
2668 Register Rscratch = reg_to_register_object($scratch$$reg);
2669 Register Rmark = reg_to_register_object($scratch2$$reg);
2670
2671 assert(Roop != Rscratch, "");
2672 assert(Roop != Rmark, "");
2673 assert(Rbox != Rscratch, "");
2674 assert(Rbox != Rmark, "");
2675
2676 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2677 %}
2678
2679 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2680 MacroAssembler _masm(&cbuf);
2681 Register Rmem = reg_to_register_object($mem$$reg);
2682 Register Rold = reg_to_register_object($old$$reg);
2683 Register Rnew = reg_to_register_object($new$$reg);
2684
2685 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2686 __ cmp( Rold, Rnew );
2687 %}
2688
2689 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2690 Register Rmem = reg_to_register_object($mem$$reg);
2691 Register Rold = reg_to_register_object($old$$reg);
2692 Register Rnew = reg_to_register_object($new$$reg);
2693
2694 MacroAssembler _masm(&cbuf);
2695 __ mov(Rnew, O7);
2696 __ casx(Rmem, Rold, O7);
2697 __ cmp( Rold, O7 );
2698 %}
2699
2700 // raw int cas, used for compareAndSwap
2701 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2702 Register Rmem = reg_to_register_object($mem$$reg);
2703 Register Rold = reg_to_register_object($old$$reg);
2704 Register Rnew = reg_to_register_object($new$$reg);
2705
2706 MacroAssembler _masm(&cbuf);
2707 __ mov(Rnew, O7);
2708 __ cas(Rmem, Rold, O7);
2709 __ cmp( Rold, O7 );
2710 %}
2711
2712 // raw int cas without using tmp register for compareAndExchange
2713 enc_class enc_casi_exch( iRegP mem, iRegL old, iRegL new) %{
2714 Register Rmem = reg_to_register_object($mem$$reg);
2715 Register Rold = reg_to_register_object($old$$reg);
2716 Register Rnew = reg_to_register_object($new$$reg);
2717
2718 MacroAssembler _masm(&cbuf);
2719 __ cas(Rmem, Rold, Rnew);
2720 %}
2721
2722 // 64-bit cas without using tmp register for compareAndExchange
2723 enc_class enc_casx_exch( iRegP mem, iRegL old, iRegL new) %{
2724 Register Rmem = reg_to_register_object($mem$$reg);
2725 Register Rold = reg_to_register_object($old$$reg);
2726 Register Rnew = reg_to_register_object($new$$reg);
2727
2728 MacroAssembler _masm(&cbuf);
2729 __ casx(Rmem, Rold, Rnew);
2730 %}
2731
2732 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2733 Register Rres = reg_to_register_object($res$$reg);
2734
2735 MacroAssembler _masm(&cbuf);
2736 __ mov(1, Rres);
2737 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2738 %}
2739
2740 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2741 Register Rres = reg_to_register_object($res$$reg);
2742
2743 MacroAssembler _masm(&cbuf);
2744 __ mov(1, Rres);
2745 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2746 %}
2747
2748 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2749 MacroAssembler _masm(&cbuf);
2750 Register Rdst = reg_to_register_object($dst$$reg);
2751 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2752 : reg_to_DoubleFloatRegister_object($src1$$reg);
2753 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2754 : reg_to_DoubleFloatRegister_object($src2$$reg);
2755
2756 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2757 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2758 %}
2759
2760 enc_class enc_rethrow() %{
2761 cbuf.set_insts_mark();
2762 Register temp_reg = G3;
2763 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
2764 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
2765 MacroAssembler _masm(&cbuf);
2766 #ifdef ASSERT
2767 __ save_frame(0);
2768 AddressLiteral last_rethrow_addrlit(&last_rethrow);
2769 __ sethi(last_rethrow_addrlit, L1);
2770 Address addr(L1, last_rethrow_addrlit.low10());
2771 __ rdpc(L2);
2772 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
2773 __ st_ptr(L2, addr);
2774 __ restore();
2775 #endif
2776 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
2777 __ delayed()->nop();
2778 %}
2779
2780 enc_class emit_mem_nop() %{
2781 // Generates the instruction LDUXA [o6,g0],#0x82,g0
2782 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
2783 %}
2784
2785 enc_class emit_fadd_nop() %{
2786 // Generates the instruction FMOVS f31,f31
2787 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
2788 %}
2789
2790 enc_class emit_br_nop() %{
2791 // Generates the instruction BPN,PN .
2792 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
2793 %}
2794
2795 enc_class enc_membar_acquire %{
2796 MacroAssembler _masm(&cbuf);
2797 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
2798 %}
2799
2800 enc_class enc_membar_release %{
2801 MacroAssembler _masm(&cbuf);
2802 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
2803 %}
2804
2805 enc_class enc_membar_volatile %{
2806 MacroAssembler _masm(&cbuf);
2807 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
2808 %}
2809
2810 %}
2811
2812 //----------FRAME--------------------------------------------------------------
2813 // Definition of frame structure and management information.
2814 //
2815 // S T A C K L A Y O U T Allocators stack-slot number
2816 // | (to get allocators register number
2817 // G Owned by | | v add VMRegImpl::stack0)
2818 // r CALLER | |
2819 // o | +--------+ pad to even-align allocators stack-slot
2820 // w V | pad0 | numbers; owned by CALLER
2821 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2822 // h ^ | in | 5
2823 // | | args | 4 Holes in incoming args owned by SELF
2824 // | | | | 3
2825 // | | +--------+
2826 // V | | old out| Empty on Intel, window on Sparc
2827 // | old |preserve| Must be even aligned.
2828 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
2829 // | | in | 3 area for Intel ret address
2830 // Owned by |preserve| Empty on Sparc.
2831 // SELF +--------+
2832 // | | pad2 | 2 pad to align old SP
2833 // | +--------+ 1
2834 // | | locks | 0
2835 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
2836 // | | pad1 | 11 pad to align new SP
2837 // | +--------+
2838 // | | | 10
2839 // | | spills | 9 spills
2840 // V | | 8 (pad0 slot for callee)
2841 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2842 // ^ | out | 7
2843 // | | args | 6 Holes in outgoing args owned by CALLEE
2844 // Owned by +--------+
2845 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2846 // | new |preserve| Must be even-aligned.
2847 // | SP-+--------+----> Matcher::_new_SP, even aligned
2848 // | | |
2849 //
2850 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2851 // known from SELF's arguments and the Java calling convention.
2852 // Region 6-7 is determined per call site.
2853 // Note 2: If the calling convention leaves holes in the incoming argument
2854 // area, those holes are owned by SELF. Holes in the outgoing area
2855 // are owned by the CALLEE. Holes should not be nessecary in the
2856 // incoming area, as the Java calling convention is completely under
2857 // the control of the AD file. Doubles can be sorted and packed to
2858 // avoid holes. Holes in the outgoing arguments may be necessary for
2859 // varargs C calling conventions.
2860 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2861 // even aligned with pad0 as needed.
2862 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2863 // region 6-11 is even aligned; it may be padded out more so that
2864 // the region from SP to FP meets the minimum stack alignment.
2865
2866 frame %{
2867 // What direction does stack grow in (assumed to be same for native & Java)
2868 stack_direction(TOWARDS_LOW);
2869
2870 // These two registers define part of the calling convention
2871 // between compiled code and the interpreter.
2872 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
2873 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
2874
2875 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2876 cisc_spilling_operand_name(indOffset);
2877
2878 // Number of stack slots consumed by a Monitor enter
2879 sync_stack_slots(2);
2880
2881 // Compiled code's Frame Pointer
2882 frame_pointer(R_SP);
2883
2884 // Stack alignment requirement
2885 stack_alignment(StackAlignmentInBytes);
2886 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
2887 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
2888
2889 // Number of stack slots between incoming argument block and the start of
2890 // a new frame. The PROLOG must add this many slots to the stack. The
2891 // EPILOG must remove this many slots.
2892 in_preserve_stack_slots(0);
2893
2894 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2895 // for calls to C. Supports the var-args backing area for register parms.
2896 // ADLC doesn't support parsing expressions, so I folded the math by hand.
2897 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
2898 varargs_C_out_slots_killed(12);
2899
2900 // The after-PROLOG location of the return address. Location of
2901 // return address specifies a type (REG or STACK) and a number
2902 // representing the register number (i.e. - use a register name) or
2903 // stack slot.
2904 return_addr(REG R_I7); // Ret Addr is in register I7
2905
2906 // Body of function which returns an OptoRegs array locating
2907 // arguments either in registers or in stack slots for calling
2908 // java
2909 calling_convention %{
2910 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
2911
2912 %}
2913
2914 // Body of function which returns an OptoRegs array locating
2915 // arguments either in registers or in stack slots for calling
2916 // C.
2917 c_calling_convention %{
2918 // This is obviously always outgoing
2919 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2920 %}
2921
2922 // Location of native (C/C++) and interpreter return values. This is specified to
2923 // be the same as Java. In the 32-bit VM, long values are actually returned from
2924 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
2925 // to and from the register pairs is done by the appropriate call and epilog
2926 // opcodes. This simplifies the register allocator.
2927 c_return_value %{
2928 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
2929 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
2930 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
2931 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
2932 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
2933 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
2934 (is_outgoing?lo_out:lo_in)[ideal_reg] );
2935 %}
2936
2937 // Location of compiled Java return values. Same as C
2938 return_value %{
2939 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
2940 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
2941 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
2942 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
2943 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
2944 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
2945 (is_outgoing?lo_out:lo_in)[ideal_reg] );
2946 %}
2947
2948 %}
2949
2950
2951 //----------ATTRIBUTES---------------------------------------------------------
2952 //----------Operand Attributes-------------------------------------------------
2953 op_attrib op_cost(1); // Required cost attribute
2954
2955 //----------Instruction Attributes---------------------------------------------
2956 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2957 ins_attrib ins_size(32); // Required size attribute (in bits)
2958
2959 // avoid_back_to_back attribute is an expression that must return
2960 // one of the following values defined in MachNode:
2961 // AVOID_NONE - instruction can be placed anywhere
2962 // AVOID_BEFORE - instruction cannot be placed after an
2963 // instruction with MachNode::AVOID_AFTER
2964 // AVOID_AFTER - the next instruction cannot be the one
2965 // with MachNode::AVOID_BEFORE
2966 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
2967 // the same time
2968 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
2969
2970 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
2971 // non-matching short branch variant of some
2972 // long branch?
2973
2974 //----------OPERANDS-----------------------------------------------------------
2975 // Operand definitions must precede instruction definitions for correct parsing
2976 // in the ADLC because operands constitute user defined types which are used in
2977 // instruction definitions.
2978
2979 //----------Simple Operands----------------------------------------------------
2980 // Immediate Operands
2981 // Integer Immediate: 32-bit
2982 operand immI() %{
2983 match(ConI);
2984
2985 op_cost(0);
2986 // formats are generated automatically for constants and base registers
2987 format %{ %}
2988 interface(CONST_INTER);
2989 %}
2990
2991 // Integer Immediate: 0-bit
2992 operand immI0() %{
2993 predicate(n->get_int() == 0);
2994 match(ConI);
2995 op_cost(0);
2996
2997 format %{ %}
2998 interface(CONST_INTER);
2999 %}
3000
3001 // Integer Immediate: 5-bit
3002 operand immI5() %{
3003 predicate(Assembler::is_simm5(n->get_int()));
3004 match(ConI);
3005 op_cost(0);
3006 format %{ %}
3007 interface(CONST_INTER);
3008 %}
3009
3010 // Integer Immediate: 8-bit
3011 operand immI8() %{
3012 predicate(Assembler::is_simm8(n->get_int()));
3013 match(ConI);
3014 op_cost(0);
3015 format %{ %}
3016 interface(CONST_INTER);
3017 %}
3018
3019 // Integer Immediate: the value 10
3020 operand immI10() %{
3021 predicate(n->get_int() == 10);
3022 match(ConI);
3023 op_cost(0);
3024
3025 format %{ %}
3026 interface(CONST_INTER);
3027 %}
3028
3029 // Integer Immediate: 11-bit
3030 operand immI11() %{
3031 predicate(Assembler::is_simm11(n->get_int()));
3032 match(ConI);
3033 op_cost(0);
3034 format %{ %}
3035 interface(CONST_INTER);
3036 %}
3037
3038 // Integer Immediate: 13-bit
3039 operand immI13() %{
3040 predicate(Assembler::is_simm13(n->get_int()));
3041 match(ConI);
3042 op_cost(0);
3043
3044 format %{ %}
3045 interface(CONST_INTER);
3046 %}
3047
3048 // Integer Immediate: 13-bit minus 7
3049 operand immI13m7() %{
3050 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3051 match(ConI);
3052 op_cost(0);
3053
3054 format %{ %}
3055 interface(CONST_INTER);
3056 %}
3057
3058 // Integer Immediate: 16-bit
3059 operand immI16() %{
3060 predicate(Assembler::is_simm16(n->get_int()));
3061 match(ConI);
3062 op_cost(0);
3063 format %{ %}
3064 interface(CONST_INTER);
3065 %}
3066
3067 // Integer Immediate: the values 1-31
3068 operand immI_1_31() %{
3069 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3070 match(ConI);
3071 op_cost(0);
3072
3073 format %{ %}
3074 interface(CONST_INTER);
3075 %}
3076
3077 // Integer Immediate: the values 32-63
3078 operand immI_32_63() %{
3079 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3080 match(ConI);
3081 op_cost(0);
3082
3083 format %{ %}
3084 interface(CONST_INTER);
3085 %}
3086
3087 // Immediates for special shifts (sign extend)
3088
3089 // Integer Immediate: the value 16
3090 operand immI_16() %{
3091 predicate(n->get_int() == 16);
3092 match(ConI);
3093 op_cost(0);
3094
3095 format %{ %}
3096 interface(CONST_INTER);
3097 %}
3098
3099 // Integer Immediate: the value 24
3100 operand immI_24() %{
3101 predicate(n->get_int() == 24);
3102 match(ConI);
3103 op_cost(0);
3104
3105 format %{ %}
3106 interface(CONST_INTER);
3107 %}
3108 // Integer Immediate: the value 255
3109 operand immI_255() %{
3110 predicate( n->get_int() == 255 );
3111 match(ConI);
3112 op_cost(0);
3113
3114 format %{ %}
3115 interface(CONST_INTER);
3116 %}
3117
3118 // Integer Immediate: the value 65535
3119 operand immI_65535() %{
3120 predicate(n->get_int() == 65535);
3121 match(ConI);
3122 op_cost(0);
3123
3124 format %{ %}
3125 interface(CONST_INTER);
3126 %}
3127
3128 // Integer Immediate: the values 0-31
3129 operand immU5() %{
3130 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3131 match(ConI);
3132 op_cost(0);
3133
3134 format %{ %}
3135 interface(CONST_INTER);
3136 %}
3137
3138 // Integer Immediate: 6-bit
3139 operand immU6() %{
3140 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3141 match(ConI);
3142 op_cost(0);
3143 format %{ %}
3144 interface(CONST_INTER);
3145 %}
3146
3147 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3148 operand immU12() %{
3149 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3150 match(ConI);
3151 op_cost(0);
3152
3153 format %{ %}
3154 interface(CONST_INTER);
3155 %}
3156
3157 // Integer Immediate non-negative
3158 operand immU31()
3159 %{
3160 predicate(n->get_int() >= 0);
3161 match(ConI);
3162
3163 op_cost(0);
3164 format %{ %}
3165 interface(CONST_INTER);
3166 %}
3167
3168 // Long Immediate: the value FF
3169 operand immL_FF() %{
3170 predicate( n->get_long() == 0xFFL );
3171 match(ConL);
3172 op_cost(0);
3173
3174 format %{ %}
3175 interface(CONST_INTER);
3176 %}
3177
3178 // Long Immediate: the value FFFF
3179 operand immL_FFFF() %{
3180 predicate( n->get_long() == 0xFFFFL );
3181 match(ConL);
3182 op_cost(0);
3183
3184 format %{ %}
3185 interface(CONST_INTER);
3186 %}
3187
3188 // Pointer Immediate: 32 or 64-bit
3189 operand immP() %{
3190 match(ConP);
3191
3192 op_cost(5);
3193 // formats are generated automatically for constants and base registers
3194 format %{ %}
3195 interface(CONST_INTER);
3196 %}
3197
3198 // Pointer Immediate: 64-bit
3199 operand immP_set() %{
3200 predicate(!VM_Version::is_niagara_plus());
3201 match(ConP);
3202
3203 op_cost(5);
3204 // formats are generated automatically for constants and base registers
3205 format %{ %}
3206 interface(CONST_INTER);
3207 %}
3208
3209 // Pointer Immediate: 64-bit
3210 // From Niagara2 processors on a load should be better than materializing.
3211 operand immP_load() %{
3212 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3213 match(ConP);
3214
3215 op_cost(5);
3216 // formats are generated automatically for constants and base registers
3217 format %{ %}
3218 interface(CONST_INTER);
3219 %}
3220
3221 // Pointer Immediate: 64-bit
3222 operand immP_no_oop_cheap() %{
3223 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3224 match(ConP);
3225
3226 op_cost(5);
3227 // formats are generated automatically for constants and base registers
3228 format %{ %}
3229 interface(CONST_INTER);
3230 %}
3231
3232 operand immP13() %{
3233 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3234 match(ConP);
3235 op_cost(0);
3236
3237 format %{ %}
3238 interface(CONST_INTER);
3239 %}
3240
3241 operand immP0() %{
3242 predicate(n->get_ptr() == 0);
3243 match(ConP);
3244 op_cost(0);
3245
3246 format %{ %}
3247 interface(CONST_INTER);
3248 %}
3249
3250 operand immP_poll() %{
3251 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3252 match(ConP);
3253
3254 // formats are generated automatically for constants and base registers
3255 format %{ %}
3256 interface(CONST_INTER);
3257 %}
3258
3259 // Pointer Immediate
3260 operand immN()
3261 %{
3262 match(ConN);
3263
3264 op_cost(10);
3265 format %{ %}
3266 interface(CONST_INTER);
3267 %}
3268
3269 operand immNKlass()
3270 %{
3271 match(ConNKlass);
3272
3273 op_cost(10);
3274 format %{ %}
3275 interface(CONST_INTER);
3276 %}
3277
3278 // NULL Pointer Immediate
3279 operand immN0()
3280 %{
3281 predicate(n->get_narrowcon() == 0);
3282 match(ConN);
3283
3284 op_cost(0);
3285 format %{ %}
3286 interface(CONST_INTER);
3287 %}
3288
3289 operand immL() %{
3290 match(ConL);
3291 op_cost(40);
3292 // formats are generated automatically for constants and base registers
3293 format %{ %}
3294 interface(CONST_INTER);
3295 %}
3296
3297 operand immL0() %{
3298 predicate(n->get_long() == 0L);
3299 match(ConL);
3300 op_cost(0);
3301 // formats are generated automatically for constants and base registers
3302 format %{ %}
3303 interface(CONST_INTER);
3304 %}
3305
3306 // Integer Immediate: 5-bit
3307 operand immL5() %{
3308 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3309 match(ConL);
3310 op_cost(0);
3311 format %{ %}
3312 interface(CONST_INTER);
3313 %}
3314
3315 // Long Immediate: 13-bit
3316 operand immL13() %{
3317 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3318 match(ConL);
3319 op_cost(0);
3320
3321 format %{ %}
3322 interface(CONST_INTER);
3323 %}
3324
3325 // Long Immediate: 13-bit minus 7
3326 operand immL13m7() %{
3327 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3328 match(ConL);
3329 op_cost(0);
3330
3331 format %{ %}
3332 interface(CONST_INTER);
3333 %}
3334
3335 // Long Immediate: low 32-bit mask
3336 operand immL_32bits() %{
3337 predicate(n->get_long() == 0xFFFFFFFFL);
3338 match(ConL);
3339 op_cost(0);
3340
3341 format %{ %}
3342 interface(CONST_INTER);
3343 %}
3344
3345 // Long Immediate: cheap (materialize in <= 3 instructions)
3346 operand immL_cheap() %{
3347 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3348 match(ConL);
3349 op_cost(0);
3350
3351 format %{ %}
3352 interface(CONST_INTER);
3353 %}
3354
3355 // Long Immediate: expensive (materialize in > 3 instructions)
3356 operand immL_expensive() %{
3357 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3358 match(ConL);
3359 op_cost(0);
3360
3361 format %{ %}
3362 interface(CONST_INTER);
3363 %}
3364
3365 // Double Immediate
3366 operand immD() %{
3367 match(ConD);
3368
3369 op_cost(40);
3370 format %{ %}
3371 interface(CONST_INTER);
3372 %}
3373
3374 // Double Immediate: +0.0d
3375 operand immD0() %{
3376 predicate(jlong_cast(n->getd()) == 0);
3377 match(ConD);
3378
3379 op_cost(0);
3380 format %{ %}
3381 interface(CONST_INTER);
3382 %}
3383
3384 // Float Immediate
3385 operand immF() %{
3386 match(ConF);
3387
3388 op_cost(20);
3389 format %{ %}
3390 interface(CONST_INTER);
3391 %}
3392
3393 // Float Immediate: +0.0f
3394 operand immF0() %{
3395 predicate(jint_cast(n->getf()) == 0);
3396 match(ConF);
3397
3398 op_cost(0);
3399 format %{ %}
3400 interface(CONST_INTER);
3401 %}
3402
3403 // Integer Register Operands
3404 // Integer Register
3405 operand iRegI() %{
3406 constraint(ALLOC_IN_RC(int_reg));
3407 match(RegI);
3408
3409 match(notemp_iRegI);
3410 match(g1RegI);
3411 match(o0RegI);
3412 match(iRegIsafe);
3413
3414 format %{ %}
3415 interface(REG_INTER);
3416 %}
3417
3418 operand notemp_iRegI() %{
3419 constraint(ALLOC_IN_RC(notemp_int_reg));
3420 match(RegI);
3421
3422 match(o0RegI);
3423
3424 format %{ %}
3425 interface(REG_INTER);
3426 %}
3427
3428 operand o0RegI() %{
3429 constraint(ALLOC_IN_RC(o0_regI));
3430 match(iRegI);
3431
3432 format %{ %}
3433 interface(REG_INTER);
3434 %}
3435
3436 // Pointer Register
3437 operand iRegP() %{
3438 constraint(ALLOC_IN_RC(ptr_reg));
3439 match(RegP);
3440
3441 match(lock_ptr_RegP);
3442 match(g1RegP);
3443 match(g2RegP);
3444 match(g3RegP);
3445 match(g4RegP);
3446 match(i0RegP);
3447 match(o0RegP);
3448 match(o1RegP);
3449 match(l7RegP);
3450
3451 format %{ %}
3452 interface(REG_INTER);
3453 %}
3454
3455 operand sp_ptr_RegP() %{
3456 constraint(ALLOC_IN_RC(sp_ptr_reg));
3457 match(RegP);
3458 match(iRegP);
3459
3460 format %{ %}
3461 interface(REG_INTER);
3462 %}
3463
3464 operand lock_ptr_RegP() %{
3465 constraint(ALLOC_IN_RC(lock_ptr_reg));
3466 match(RegP);
3467 match(i0RegP);
3468 match(o0RegP);
3469 match(o1RegP);
3470 match(l7RegP);
3471
3472 format %{ %}
3473 interface(REG_INTER);
3474 %}
3475
3476 operand g1RegP() %{
3477 constraint(ALLOC_IN_RC(g1_regP));
3478 match(iRegP);
3479
3480 format %{ %}
3481 interface(REG_INTER);
3482 %}
3483
3484 operand g2RegP() %{
3485 constraint(ALLOC_IN_RC(g2_regP));
3486 match(iRegP);
3487
3488 format %{ %}
3489 interface(REG_INTER);
3490 %}
3491
3492 operand g3RegP() %{
3493 constraint(ALLOC_IN_RC(g3_regP));
3494 match(iRegP);
3495
3496 format %{ %}
3497 interface(REG_INTER);
3498 %}
3499
3500 operand g1RegI() %{
3501 constraint(ALLOC_IN_RC(g1_regI));
3502 match(iRegI);
3503
3504 format %{ %}
3505 interface(REG_INTER);
3506 %}
3507
3508 operand g3RegI() %{
3509 constraint(ALLOC_IN_RC(g3_regI));
3510 match(iRegI);
3511
3512 format %{ %}
3513 interface(REG_INTER);
3514 %}
3515
3516 operand g4RegI() %{
3517 constraint(ALLOC_IN_RC(g4_regI));
3518 match(iRegI);
3519
3520 format %{ %}
3521 interface(REG_INTER);
3522 %}
3523
3524 operand g4RegP() %{
3525 constraint(ALLOC_IN_RC(g4_regP));
3526 match(iRegP);
3527
3528 format %{ %}
3529 interface(REG_INTER);
3530 %}
3531
3532 operand i0RegP() %{
3533 constraint(ALLOC_IN_RC(i0_regP));
3534 match(iRegP);
3535
3536 format %{ %}
3537 interface(REG_INTER);
3538 %}
3539
3540 operand o0RegP() %{
3541 constraint(ALLOC_IN_RC(o0_regP));
3542 match(iRegP);
3543
3544 format %{ %}
3545 interface(REG_INTER);
3546 %}
3547
3548 operand o1RegP() %{
3549 constraint(ALLOC_IN_RC(o1_regP));
3550 match(iRegP);
3551
3552 format %{ %}
3553 interface(REG_INTER);
3554 %}
3555
3556 operand o2RegP() %{
3557 constraint(ALLOC_IN_RC(o2_regP));
3558 match(iRegP);
3559
3560 format %{ %}
3561 interface(REG_INTER);
3562 %}
3563
3564 operand o7RegP() %{
3565 constraint(ALLOC_IN_RC(o7_regP));
3566 match(iRegP);
3567
3568 format %{ %}
3569 interface(REG_INTER);
3570 %}
3571
3572 operand l7RegP() %{
3573 constraint(ALLOC_IN_RC(l7_regP));
3574 match(iRegP);
3575
3576 format %{ %}
3577 interface(REG_INTER);
3578 %}
3579
3580 operand o7RegI() %{
3581 constraint(ALLOC_IN_RC(o7_regI));
3582 match(iRegI);
3583
3584 format %{ %}
3585 interface(REG_INTER);
3586 %}
3587
3588 operand iRegN() %{
3589 constraint(ALLOC_IN_RC(int_reg));
3590 match(RegN);
3591
3592 format %{ %}
3593 interface(REG_INTER);
3594 %}
3595
3596 // Long Register
3597 operand iRegL() %{
3598 constraint(ALLOC_IN_RC(long_reg));
3599 match(RegL);
3600
3601 format %{ %}
3602 interface(REG_INTER);
3603 %}
3604
3605 operand o2RegL() %{
3606 constraint(ALLOC_IN_RC(o2_regL));
3607 match(iRegL);
3608
3609 format %{ %}
3610 interface(REG_INTER);
3611 %}
3612
3613 operand o7RegL() %{
3614 constraint(ALLOC_IN_RC(o7_regL));
3615 match(iRegL);
3616
3617 format %{ %}
3618 interface(REG_INTER);
3619 %}
3620
3621 operand g1RegL() %{
3622 constraint(ALLOC_IN_RC(g1_regL));
3623 match(iRegL);
3624
3625 format %{ %}
3626 interface(REG_INTER);
3627 %}
3628
3629 operand g3RegL() %{
3630 constraint(ALLOC_IN_RC(g3_regL));
3631 match(iRegL);
3632
3633 format %{ %}
3634 interface(REG_INTER);
3635 %}
3636
3637 // Int Register safe
3638 // This is 64bit safe
3639 operand iRegIsafe() %{
3640 constraint(ALLOC_IN_RC(long_reg));
3641
3642 match(iRegI);
3643
3644 format %{ %}
3645 interface(REG_INTER);
3646 %}
3647
3648 // Condition Code Flag Register
3649 operand flagsReg() %{
3650 constraint(ALLOC_IN_RC(int_flags));
3651 match(RegFlags);
3652
3653 format %{ "ccr" %} // both ICC and XCC
3654 interface(REG_INTER);
3655 %}
3656
3657 // Condition Code Register, unsigned comparisons.
3658 operand flagsRegU() %{
3659 constraint(ALLOC_IN_RC(int_flags));
3660 match(RegFlags);
3661
3662 format %{ "icc_U" %}
3663 interface(REG_INTER);
3664 %}
3665
3666 // Condition Code Register, pointer comparisons.
3667 operand flagsRegP() %{
3668 constraint(ALLOC_IN_RC(int_flags));
3669 match(RegFlags);
3670
3671 format %{ "xcc_P" %}
3672 interface(REG_INTER);
3673 %}
3674
3675 // Condition Code Register, long comparisons.
3676 operand flagsRegL() %{
3677 constraint(ALLOC_IN_RC(int_flags));
3678 match(RegFlags);
3679
3680 format %{ "xcc_L" %}
3681 interface(REG_INTER);
3682 %}
3683
3684 // Condition Code Register, floating comparisons, unordered same as "less".
3685 operand flagsRegF() %{
3686 constraint(ALLOC_IN_RC(float_flags));
3687 match(RegFlags);
3688 match(flagsRegF0);
3689
3690 format %{ %}
3691 interface(REG_INTER);
3692 %}
3693
3694 operand flagsRegF0() %{
3695 constraint(ALLOC_IN_RC(float_flag0));
3696 match(RegFlags);
3697
3698 format %{ %}
3699 interface(REG_INTER);
3700 %}
3701
3702
3703 // Condition Code Flag Register used by long compare
3704 operand flagsReg_long_LTGE() %{
3705 constraint(ALLOC_IN_RC(int_flags));
3706 match(RegFlags);
3707 format %{ "icc_LTGE" %}
3708 interface(REG_INTER);
3709 %}
3710 operand flagsReg_long_EQNE() %{
3711 constraint(ALLOC_IN_RC(int_flags));
3712 match(RegFlags);
3713 format %{ "icc_EQNE" %}
3714 interface(REG_INTER);
3715 %}
3716 operand flagsReg_long_LEGT() %{
3717 constraint(ALLOC_IN_RC(int_flags));
3718 match(RegFlags);
3719 format %{ "icc_LEGT" %}
3720 interface(REG_INTER);
3721 %}
3722
3723
3724 operand regD() %{
3725 constraint(ALLOC_IN_RC(dflt_reg));
3726 match(RegD);
3727
3728 match(regD_low);
3729
3730 format %{ %}
3731 interface(REG_INTER);
3732 %}
3733
3734 operand regF() %{
3735 constraint(ALLOC_IN_RC(sflt_reg));
3736 match(RegF);
3737
3738 format %{ %}
3739 interface(REG_INTER);
3740 %}
3741
3742 operand regD_low() %{
3743 constraint(ALLOC_IN_RC(dflt_low_reg));
3744 match(regD);
3745
3746 format %{ %}
3747 interface(REG_INTER);
3748 %}
3749
3750 // Special Registers
3751
3752 // Method Register
3753 operand inline_cache_regP(iRegP reg) %{
3754 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
3755 match(reg);
3756 format %{ %}
3757 interface(REG_INTER);
3758 %}
3759
3760 operand interpreter_method_oop_regP(iRegP reg) %{
3761 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
3762 match(reg);
3763 format %{ %}
3764 interface(REG_INTER);
3765 %}
3766
3767
3768 //----------Complex Operands---------------------------------------------------
3769 // Indirect Memory Reference
3770 operand indirect(sp_ptr_RegP reg) %{
3771 constraint(ALLOC_IN_RC(sp_ptr_reg));
3772 match(reg);
3773
3774 op_cost(100);
3775 format %{ "[$reg]" %}
3776 interface(MEMORY_INTER) %{
3777 base($reg);
3778 index(0x0);
3779 scale(0x0);
3780 disp(0x0);
3781 %}
3782 %}
3783
3784 // Indirect with simm13 Offset
3785 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
3786 constraint(ALLOC_IN_RC(sp_ptr_reg));
3787 match(AddP reg offset);
3788
3789 op_cost(100);
3790 format %{ "[$reg + $offset]" %}
3791 interface(MEMORY_INTER) %{
3792 base($reg);
3793 index(0x0);
3794 scale(0x0);
3795 disp($offset);
3796 %}
3797 %}
3798
3799 // Indirect with simm13 Offset minus 7
3800 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
3801 constraint(ALLOC_IN_RC(sp_ptr_reg));
3802 match(AddP reg offset);
3803
3804 op_cost(100);
3805 format %{ "[$reg + $offset]" %}
3806 interface(MEMORY_INTER) %{
3807 base($reg);
3808 index(0x0);
3809 scale(0x0);
3810 disp($offset);
3811 %}
3812 %}
3813
3814 // Note: Intel has a swapped version also, like this:
3815 //operand indOffsetX(iRegI reg, immP offset) %{
3816 // constraint(ALLOC_IN_RC(int_reg));
3817 // match(AddP offset reg);
3818 //
3819 // op_cost(100);
3820 // format %{ "[$reg + $offset]" %}
3821 // interface(MEMORY_INTER) %{
3822 // base($reg);
3823 // index(0x0);
3824 // scale(0x0);
3825 // disp($offset);
3826 // %}
3827 //%}
3828 //// However, it doesn't make sense for SPARC, since
3829 // we have no particularly good way to embed oops in
3830 // single instructions.
3831
3832 // Indirect with Register Index
3833 operand indIndex(iRegP addr, iRegX index) %{
3834 constraint(ALLOC_IN_RC(ptr_reg));
3835 match(AddP addr index);
3836
3837 op_cost(100);
3838 format %{ "[$addr + $index]" %}
3839 interface(MEMORY_INTER) %{
3840 base($addr);
3841 index($index);
3842 scale(0x0);
3843 disp(0x0);
3844 %}
3845 %}
3846
3847 //----------Special Memory Operands--------------------------------------------
3848 // Stack Slot Operand - This operand is used for loading and storing temporary
3849 // values on the stack where a match requires a value to
3850 // flow through memory.
3851 operand stackSlotI(sRegI reg) %{
3852 constraint(ALLOC_IN_RC(stack_slots));
3853 op_cost(100);
3854 //match(RegI);
3855 format %{ "[$reg]" %}
3856 interface(MEMORY_INTER) %{
3857 base(0xE); // R_SP
3858 index(0x0);
3859 scale(0x0);
3860 disp($reg); // Stack Offset
3861 %}
3862 %}
3863
3864 operand stackSlotP(sRegP reg) %{
3865 constraint(ALLOC_IN_RC(stack_slots));
3866 op_cost(100);
3867 //match(RegP);
3868 format %{ "[$reg]" %}
3869 interface(MEMORY_INTER) %{
3870 base(0xE); // R_SP
3871 index(0x0);
3872 scale(0x0);
3873 disp($reg); // Stack Offset
3874 %}
3875 %}
3876
3877 operand stackSlotF(sRegF reg) %{
3878 constraint(ALLOC_IN_RC(stack_slots));
3879 op_cost(100);
3880 //match(RegF);
3881 format %{ "[$reg]" %}
3882 interface(MEMORY_INTER) %{
3883 base(0xE); // R_SP
3884 index(0x0);
3885 scale(0x0);
3886 disp($reg); // Stack Offset
3887 %}
3888 %}
3889 operand stackSlotD(sRegD reg) %{
3890 constraint(ALLOC_IN_RC(stack_slots));
3891 op_cost(100);
3892 //match(RegD);
3893 format %{ "[$reg]" %}
3894 interface(MEMORY_INTER) %{
3895 base(0xE); // R_SP
3896 index(0x0);
3897 scale(0x0);
3898 disp($reg); // Stack Offset
3899 %}
3900 %}
3901 operand stackSlotL(sRegL reg) %{
3902 constraint(ALLOC_IN_RC(stack_slots));
3903 op_cost(100);
3904 //match(RegL);
3905 format %{ "[$reg]" %}
3906 interface(MEMORY_INTER) %{
3907 base(0xE); // R_SP
3908 index(0x0);
3909 scale(0x0);
3910 disp($reg); // Stack Offset
3911 %}
3912 %}
3913
3914 // Operands for expressing Control Flow
3915 // NOTE: Label is a predefined operand which should not be redefined in
3916 // the AD file. It is generically handled within the ADLC.
3917
3918 //----------Conditional Branch Operands----------------------------------------
3919 // Comparison Op - This is the operation of the comparison, and is limited to
3920 // the following set of codes:
3921 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3922 //
3923 // Other attributes of the comparison, such as unsignedness, are specified
3924 // by the comparison instruction that sets a condition code flags register.
3925 // That result is represented by a flags operand whose subtype is appropriate
3926 // to the unsignedness (etc.) of the comparison.
3927 //
3928 // Later, the instruction which matches both the Comparison Op (a Bool) and
3929 // the flags (produced by the Cmp) specifies the coding of the comparison op
3930 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3931
3932 operand cmpOp() %{
3933 match(Bool);
3934
3935 format %{ "" %}
3936 interface(COND_INTER) %{
3937 equal(0x1);
3938 not_equal(0x9);
3939 less(0x3);
3940 greater_equal(0xB);
3941 less_equal(0x2);
3942 greater(0xA);
3943 overflow(0x7);
3944 no_overflow(0xF);
3945 %}
3946 %}
3947
3948 // Comparison Op, unsigned
3949 operand cmpOpU() %{
3950 match(Bool);
3951 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
3952 n->as_Bool()->_test._test != BoolTest::no_overflow);
3953
3954 format %{ "u" %}
3955 interface(COND_INTER) %{
3956 equal(0x1);
3957 not_equal(0x9);
3958 less(0x5);
3959 greater_equal(0xD);
3960 less_equal(0x4);
3961 greater(0xC);
3962 overflow(0x7);
3963 no_overflow(0xF);
3964 %}
3965 %}
3966
3967 // Comparison Op, pointer (same as unsigned)
3968 operand cmpOpP() %{
3969 match(Bool);
3970 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
3971 n->as_Bool()->_test._test != BoolTest::no_overflow);
3972
3973 format %{ "p" %}
3974 interface(COND_INTER) %{
3975 equal(0x1);
3976 not_equal(0x9);
3977 less(0x5);
3978 greater_equal(0xD);
3979 less_equal(0x4);
3980 greater(0xC);
3981 overflow(0x7);
3982 no_overflow(0xF);
3983 %}
3984 %}
3985
3986 // Comparison Op, branch-register encoding
3987 operand cmpOp_reg() %{
3988 match(Bool);
3989 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
3990 n->as_Bool()->_test._test != BoolTest::no_overflow);
3991
3992 format %{ "" %}
3993 interface(COND_INTER) %{
3994 equal (0x1);
3995 not_equal (0x5);
3996 less (0x3);
3997 greater_equal(0x7);
3998 less_equal (0x2);
3999 greater (0x6);
4000 overflow(0x7); // not supported
4001 no_overflow(0xF); // not supported
4002 %}
4003 %}
4004
4005 // Comparison Code, floating, unordered same as less
4006 operand cmpOpF() %{
4007 match(Bool);
4008 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4009 n->as_Bool()->_test._test != BoolTest::no_overflow);
4010
4011 format %{ "fl" %}
4012 interface(COND_INTER) %{
4013 equal(0x9);
4014 not_equal(0x1);
4015 less(0x3);
4016 greater_equal(0xB);
4017 less_equal(0xE);
4018 greater(0x6);
4019
4020 overflow(0x7); // not supported
4021 no_overflow(0xF); // not supported
4022 %}
4023 %}
4024
4025 // Used by long compare
4026 operand cmpOp_commute() %{
4027 match(Bool);
4028 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4029 n->as_Bool()->_test._test != BoolTest::no_overflow);
4030
4031 format %{ "" %}
4032 interface(COND_INTER) %{
4033 equal(0x1);
4034 not_equal(0x9);
4035 less(0xA);
4036 greater_equal(0x2);
4037 less_equal(0xB);
4038 greater(0x3);
4039 overflow(0x7);
4040 no_overflow(0xF);
4041 %}
4042 %}
4043
4044 //----------OPERAND CLASSES----------------------------------------------------
4045 // Operand Classes are groups of operands that are used to simplify
4046 // instruction definitions by not requiring the AD writer to specify separate
4047 // instructions for every form of operand when the instruction accepts
4048 // multiple operand types with the same basic encoding and format. The classic
4049 // case of this is memory operands.
4050 opclass memory( indirect, indOffset13, indIndex );
4051 opclass indIndexMemory( indIndex );
4052
4053 //----------PIPELINE-----------------------------------------------------------
4054 pipeline %{
4055
4056 //----------ATTRIBUTES---------------------------------------------------------
4057 attributes %{
4058 fixed_size_instructions; // Fixed size instructions
4059 branch_has_delay_slot; // Branch has delay slot following
4060 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4061 instruction_unit_size = 4; // An instruction is 4 bytes long
4062 instruction_fetch_unit_size = 16; // The processor fetches one line
4063 instruction_fetch_units = 1; // of 16 bytes
4064
4065 // List of nop instructions
4066 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4067 %}
4068
4069 //----------RESOURCES----------------------------------------------------------
4070 // Resources are the functional units available to the machine
4071 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4072
4073 //----------PIPELINE DESCRIPTION-----------------------------------------------
4074 // Pipeline Description specifies the stages in the machine's pipeline
4075
4076 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4077
4078 //----------PIPELINE CLASSES---------------------------------------------------
4079 // Pipeline Classes describe the stages in which input and output are
4080 // referenced by the hardware pipeline.
4081
4082 // Integer ALU reg-reg operation
4083 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4084 single_instruction;
4085 dst : E(write);
4086 src1 : R(read);
4087 src2 : R(read);
4088 IALU : R;
4089 %}
4090
4091 // Integer ALU reg-reg long operation
4092 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4093 instruction_count(2);
4094 dst : E(write);
4095 src1 : R(read);
4096 src2 : R(read);
4097 IALU : R;
4098 IALU : R;
4099 %}
4100
4101 // Integer ALU reg-reg long dependent operation
4102 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4103 instruction_count(1); multiple_bundles;
4104 dst : E(write);
4105 src1 : R(read);
4106 src2 : R(read);
4107 cr : E(write);
4108 IALU : R(2);
4109 %}
4110
4111 // Integer ALU reg-imm operaion
4112 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4113 single_instruction;
4114 dst : E(write);
4115 src1 : R(read);
4116 IALU : R;
4117 %}
4118
4119 // Integer ALU reg-reg operation with condition code
4120 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4121 single_instruction;
4122 dst : E(write);
4123 cr : E(write);
4124 src1 : R(read);
4125 src2 : R(read);
4126 IALU : R;
4127 %}
4128
4129 // Integer ALU reg-imm operation with condition code
4130 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4131 single_instruction;
4132 dst : E(write);
4133 cr : E(write);
4134 src1 : R(read);
4135 IALU : R;
4136 %}
4137
4138 // Integer ALU zero-reg operation
4139 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4140 single_instruction;
4141 dst : E(write);
4142 src2 : R(read);
4143 IALU : R;
4144 %}
4145
4146 // Integer ALU zero-reg operation with condition code only
4147 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4148 single_instruction;
4149 cr : E(write);
4150 src : R(read);
4151 IALU : R;
4152 %}
4153
4154 // Integer ALU reg-reg operation with condition code only
4155 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4156 single_instruction;
4157 cr : E(write);
4158 src1 : R(read);
4159 src2 : R(read);
4160 IALU : R;
4161 %}
4162
4163 // Integer ALU reg-imm operation with condition code only
4164 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4165 single_instruction;
4166 cr : E(write);
4167 src1 : R(read);
4168 IALU : R;
4169 %}
4170
4171 // Integer ALU reg-reg-zero operation with condition code only
4172 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4173 single_instruction;
4174 cr : E(write);
4175 src1 : R(read);
4176 src2 : R(read);
4177 IALU : R;
4178 %}
4179
4180 // Integer ALU reg-imm-zero operation with condition code only
4181 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4182 single_instruction;
4183 cr : E(write);
4184 src1 : R(read);
4185 IALU : R;
4186 %}
4187
4188 // Integer ALU reg-reg operation with condition code, src1 modified
4189 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4190 single_instruction;
4191 cr : E(write);
4192 src1 : E(write);
4193 src1 : R(read);
4194 src2 : R(read);
4195 IALU : R;
4196 %}
4197
4198 // Integer ALU reg-imm operation with condition code, src1 modified
4199 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4200 single_instruction;
4201 cr : E(write);
4202 src1 : E(write);
4203 src1 : R(read);
4204 IALU : R;
4205 %}
4206
4207 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4208 multiple_bundles;
4209 dst : E(write)+4;
4210 cr : E(write);
4211 src1 : R(read);
4212 src2 : R(read);
4213 IALU : R(3);
4214 BR : R(2);
4215 %}
4216
4217 // Integer ALU operation
4218 pipe_class ialu_none(iRegI dst) %{
4219 single_instruction;
4220 dst : E(write);
4221 IALU : R;
4222 %}
4223
4224 // Integer ALU reg operation
4225 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4226 single_instruction; may_have_no_code;
4227 dst : E(write);
4228 src : R(read);
4229 IALU : R;
4230 %}
4231
4232 // Integer ALU reg conditional operation
4233 // This instruction has a 1 cycle stall, and cannot execute
4234 // in the same cycle as the instruction setting the condition
4235 // code. We kludge this by pretending to read the condition code
4236 // 1 cycle earlier, and by marking the functional units as busy
4237 // for 2 cycles with the result available 1 cycle later than
4238 // is really the case.
4239 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4240 single_instruction;
4241 op2_out : C(write);
4242 op1 : R(read);
4243 cr : R(read); // This is really E, with a 1 cycle stall
4244 BR : R(2);
4245 MS : R(2);
4246 %}
4247
4248 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4249 instruction_count(1); multiple_bundles;
4250 dst : C(write)+1;
4251 src : R(read)+1;
4252 IALU : R(1);
4253 BR : E(2);
4254 MS : E(2);
4255 %}
4256
4257 // Integer ALU reg operation
4258 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4259 single_instruction; may_have_no_code;
4260 dst : E(write);
4261 src : R(read);
4262 IALU : R;
4263 %}
4264 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4265 single_instruction; may_have_no_code;
4266 dst : E(write);
4267 src : R(read);
4268 IALU : R;
4269 %}
4270
4271 // Two integer ALU reg operations
4272 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4273 instruction_count(2);
4274 dst : E(write);
4275 src : R(read);
4276 A0 : R;
4277 A1 : R;
4278 %}
4279
4280 // Two integer ALU reg operations
4281 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4282 instruction_count(2); may_have_no_code;
4283 dst : E(write);
4284 src : R(read);
4285 A0 : R;
4286 A1 : R;
4287 %}
4288
4289 // Integer ALU imm operation
4290 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4291 single_instruction;
4292 dst : E(write);
4293 IALU : R;
4294 %}
4295
4296 // Integer ALU reg-reg with carry operation
4297 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4298 single_instruction;
4299 dst : E(write);
4300 src1 : R(read);
4301 src2 : R(read);
4302 IALU : R;
4303 %}
4304
4305 // Integer ALU cc operation
4306 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4307 single_instruction;
4308 dst : E(write);
4309 cc : R(read);
4310 IALU : R;
4311 %}
4312
4313 // Integer ALU cc / second IALU operation
4314 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4315 instruction_count(1); multiple_bundles;
4316 dst : E(write)+1;
4317 src : R(read);
4318 IALU : R;
4319 %}
4320
4321 // Integer ALU cc / second IALU operation
4322 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4323 instruction_count(1); multiple_bundles;
4324 dst : E(write)+1;
4325 p : R(read);
4326 q : R(read);
4327 IALU : R;
4328 %}
4329
4330 // Integer ALU hi-lo-reg operation
4331 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4332 instruction_count(1); multiple_bundles;
4333 dst : E(write)+1;
4334 IALU : R(2);
4335 %}
4336
4337 // Float ALU hi-lo-reg operation (with temp)
4338 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4339 instruction_count(1); multiple_bundles;
4340 dst : E(write)+1;
4341 IALU : R(2);
4342 %}
4343
4344 // Long Constant
4345 pipe_class loadConL( iRegL dst, immL src ) %{
4346 instruction_count(2); multiple_bundles;
4347 dst : E(write)+1;
4348 IALU : R(2);
4349 IALU : R(2);
4350 %}
4351
4352 // Pointer Constant
4353 pipe_class loadConP( iRegP dst, immP src ) %{
4354 instruction_count(0); multiple_bundles;
4355 fixed_latency(6);
4356 %}
4357
4358 // Polling Address
4359 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4360 instruction_count(0); multiple_bundles;
4361 fixed_latency(6);
4362 %}
4363
4364 // Long Constant small
4365 pipe_class loadConLlo( iRegL dst, immL src ) %{
4366 instruction_count(2);
4367 dst : E(write);
4368 IALU : R;
4369 IALU : R;
4370 %}
4371
4372 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4373 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4374 instruction_count(1); multiple_bundles;
4375 src : R(read);
4376 dst : M(write)+1;
4377 IALU : R;
4378 MS : E;
4379 %}
4380
4381 // Integer ALU nop operation
4382 pipe_class ialu_nop() %{
4383 single_instruction;
4384 IALU : R;
4385 %}
4386
4387 // Integer ALU nop operation
4388 pipe_class ialu_nop_A0() %{
4389 single_instruction;
4390 A0 : R;
4391 %}
4392
4393 // Integer ALU nop operation
4394 pipe_class ialu_nop_A1() %{
4395 single_instruction;
4396 A1 : R;
4397 %}
4398
4399 // Integer Multiply reg-reg operation
4400 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4401 single_instruction;
4402 dst : E(write);
4403 src1 : R(read);
4404 src2 : R(read);
4405 MS : R(5);
4406 %}
4407
4408 // Integer Multiply reg-imm operation
4409 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4410 single_instruction;
4411 dst : E(write);
4412 src1 : R(read);
4413 MS : R(5);
4414 %}
4415
4416 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4417 single_instruction;
4418 dst : E(write)+4;
4419 src1 : R(read);
4420 src2 : R(read);
4421 MS : R(6);
4422 %}
4423
4424 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4425 single_instruction;
4426 dst : E(write)+4;
4427 src1 : R(read);
4428 MS : R(6);
4429 %}
4430
4431 // Integer Divide reg-reg
4432 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4433 instruction_count(1); multiple_bundles;
4434 dst : E(write);
4435 temp : E(write);
4436 src1 : R(read);
4437 src2 : R(read);
4438 temp : R(read);
4439 MS : R(38);
4440 %}
4441
4442 // Integer Divide reg-imm
4443 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4444 instruction_count(1); multiple_bundles;
4445 dst : E(write);
4446 temp : E(write);
4447 src1 : R(read);
4448 temp : R(read);
4449 MS : R(38);
4450 %}
4451
4452 // Long Divide
4453 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4454 dst : E(write)+71;
4455 src1 : R(read);
4456 src2 : R(read)+1;
4457 MS : R(70);
4458 %}
4459
4460 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4461 dst : E(write)+71;
4462 src1 : R(read);
4463 MS : R(70);
4464 %}
4465
4466 // Floating Point Add Float
4467 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4468 single_instruction;
4469 dst : X(write);
4470 src1 : E(read);
4471 src2 : E(read);
4472 FA : R;
4473 %}
4474
4475 // Floating Point Add Double
4476 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4477 single_instruction;
4478 dst : X(write);
4479 src1 : E(read);
4480 src2 : E(read);
4481 FA : R;
4482 %}
4483
4484 // Floating Point Conditional Move based on integer flags
4485 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4486 single_instruction;
4487 dst : X(write);
4488 src : E(read);
4489 cr : R(read);
4490 FA : R(2);
4491 BR : R(2);
4492 %}
4493
4494 // Floating Point Conditional Move based on integer flags
4495 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4496 single_instruction;
4497 dst : X(write);
4498 src : E(read);
4499 cr : R(read);
4500 FA : R(2);
4501 BR : R(2);
4502 %}
4503
4504 // Floating Point Multiply Float
4505 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4506 single_instruction;
4507 dst : X(write);
4508 src1 : E(read);
4509 src2 : E(read);
4510 FM : R;
4511 %}
4512
4513 // Floating Point Multiply Double
4514 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4515 single_instruction;
4516 dst : X(write);
4517 src1 : E(read);
4518 src2 : E(read);
4519 FM : R;
4520 %}
4521
4522 // Floating Point Divide Float
4523 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4524 single_instruction;
4525 dst : X(write);
4526 src1 : E(read);
4527 src2 : E(read);
4528 FM : R;
4529 FDIV : C(14);
4530 %}
4531
4532 // Floating Point Divide Double
4533 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4534 single_instruction;
4535 dst : X(write);
4536 src1 : E(read);
4537 src2 : E(read);
4538 FM : R;
4539 FDIV : C(17);
4540 %}
4541
4542 // Floating Point Move/Negate/Abs Float
4543 pipe_class faddF_reg(regF dst, regF src) %{
4544 single_instruction;
4545 dst : W(write);
4546 src : E(read);
4547 FA : R(1);
4548 %}
4549
4550 // Floating Point Move/Negate/Abs Double
4551 pipe_class faddD_reg(regD dst, regD src) %{
4552 single_instruction;
4553 dst : W(write);
4554 src : E(read);
4555 FA : R;
4556 %}
4557
4558 // Floating Point Convert F->D
4559 pipe_class fcvtF2D(regD dst, regF src) %{
4560 single_instruction;
4561 dst : X(write);
4562 src : E(read);
4563 FA : R;
4564 %}
4565
4566 // Floating Point Convert I->D
4567 pipe_class fcvtI2D(regD dst, regF src) %{
4568 single_instruction;
4569 dst : X(write);
4570 src : E(read);
4571 FA : R;
4572 %}
4573
4574 // Floating Point Convert LHi->D
4575 pipe_class fcvtLHi2D(regD dst, regD src) %{
4576 single_instruction;
4577 dst : X(write);
4578 src : E(read);
4579 FA : R;
4580 %}
4581
4582 // Floating Point Convert L->D
4583 pipe_class fcvtL2D(regD dst, regF src) %{
4584 single_instruction;
4585 dst : X(write);
4586 src : E(read);
4587 FA : R;
4588 %}
4589
4590 // Floating Point Convert L->F
4591 pipe_class fcvtL2F(regD dst, regF src) %{
4592 single_instruction;
4593 dst : X(write);
4594 src : E(read);
4595 FA : R;
4596 %}
4597
4598 // Floating Point Convert D->F
4599 pipe_class fcvtD2F(regD dst, regF src) %{
4600 single_instruction;
4601 dst : X(write);
4602 src : E(read);
4603 FA : R;
4604 %}
4605
4606 // Floating Point Convert I->L
4607 pipe_class fcvtI2L(regD dst, regF src) %{
4608 single_instruction;
4609 dst : X(write);
4610 src : E(read);
4611 FA : R;
4612 %}
4613
4614 // Floating Point Convert D->F
4615 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4616 instruction_count(1); multiple_bundles;
4617 dst : X(write)+6;
4618 src : E(read);
4619 FA : R;
4620 %}
4621
4622 // Floating Point Convert D->L
4623 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4624 instruction_count(1); multiple_bundles;
4625 dst : X(write)+6;
4626 src : E(read);
4627 FA : R;
4628 %}
4629
4630 // Floating Point Convert F->I
4631 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4632 instruction_count(1); multiple_bundles;
4633 dst : X(write)+6;
4634 src : E(read);
4635 FA : R;
4636 %}
4637
4638 // Floating Point Convert F->L
4639 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4640 instruction_count(1); multiple_bundles;
4641 dst : X(write)+6;
4642 src : E(read);
4643 FA : R;
4644 %}
4645
4646 // Floating Point Convert I->F
4647 pipe_class fcvtI2F(regF dst, regF src) %{
4648 single_instruction;
4649 dst : X(write);
4650 src : E(read);
4651 FA : R;
4652 %}
4653
4654 // Floating Point Compare
4655 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4656 single_instruction;
4657 cr : X(write);
4658 src1 : E(read);
4659 src2 : E(read);
4660 FA : R;
4661 %}
4662
4663 // Floating Point Compare
4664 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4665 single_instruction;
4666 cr : X(write);
4667 src1 : E(read);
4668 src2 : E(read);
4669 FA : R;
4670 %}
4671
4672 // Floating Add Nop
4673 pipe_class fadd_nop() %{
4674 single_instruction;
4675 FA : R;
4676 %}
4677
4678 // Integer Store to Memory
4679 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4680 single_instruction;
4681 mem : R(read);
4682 src : C(read);
4683 MS : R;
4684 %}
4685
4686 // Integer Store to Memory
4687 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4688 single_instruction;
4689 mem : R(read);
4690 src : C(read);
4691 MS : R;
4692 %}
4693
4694 // Integer Store Zero to Memory
4695 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4696 single_instruction;
4697 mem : R(read);
4698 MS : R;
4699 %}
4700
4701 // Special Stack Slot Store
4702 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4703 single_instruction;
4704 stkSlot : R(read);
4705 src : C(read);
4706 MS : R;
4707 %}
4708
4709 // Special Stack Slot Store
4710 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4711 instruction_count(2); multiple_bundles;
4712 stkSlot : R(read);
4713 src : C(read);
4714 MS : R(2);
4715 %}
4716
4717 // Float Store
4718 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4719 single_instruction;
4720 mem : R(read);
4721 src : C(read);
4722 MS : R;
4723 %}
4724
4725 // Float Store
4726 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4727 single_instruction;
4728 mem : R(read);
4729 MS : R;
4730 %}
4731
4732 // Double Store
4733 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4734 instruction_count(1);
4735 mem : R(read);
4736 src : C(read);
4737 MS : R;
4738 %}
4739
4740 // Double Store
4741 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4742 single_instruction;
4743 mem : R(read);
4744 MS : R;
4745 %}
4746
4747 // Special Stack Slot Float Store
4748 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4749 single_instruction;
4750 stkSlot : R(read);
4751 src : C(read);
4752 MS : R;
4753 %}
4754
4755 // Special Stack Slot Double Store
4756 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4757 single_instruction;
4758 stkSlot : R(read);
4759 src : C(read);
4760 MS : R;
4761 %}
4762
4763 // Integer Load (when sign bit propagation not needed)
4764 pipe_class iload_mem(iRegI dst, memory mem) %{
4765 single_instruction;
4766 mem : R(read);
4767 dst : C(write);
4768 MS : R;
4769 %}
4770
4771 // Integer Load from stack operand
4772 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
4773 single_instruction;
4774 mem : R(read);
4775 dst : C(write);
4776 MS : R;
4777 %}
4778
4779 // Integer Load (when sign bit propagation or masking is needed)
4780 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
4781 single_instruction;
4782 mem : R(read);
4783 dst : M(write);
4784 MS : R;
4785 %}
4786
4787 // Float Load
4788 pipe_class floadF_mem(regF dst, memory mem) %{
4789 single_instruction;
4790 mem : R(read);
4791 dst : M(write);
4792 MS : R;
4793 %}
4794
4795 // Float Load
4796 pipe_class floadD_mem(regD dst, memory mem) %{
4797 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
4798 mem : R(read);
4799 dst : M(write);
4800 MS : R;
4801 %}
4802
4803 // Float Load
4804 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
4805 single_instruction;
4806 stkSlot : R(read);
4807 dst : M(write);
4808 MS : R;
4809 %}
4810
4811 // Float Load
4812 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
4813 single_instruction;
4814 stkSlot : R(read);
4815 dst : M(write);
4816 MS : R;
4817 %}
4818
4819 // Memory Nop
4820 pipe_class mem_nop() %{
4821 single_instruction;
4822 MS : R;
4823 %}
4824
4825 pipe_class sethi(iRegP dst, immI src) %{
4826 single_instruction;
4827 dst : E(write);
4828 IALU : R;
4829 %}
4830
4831 pipe_class loadPollP(iRegP poll) %{
4832 single_instruction;
4833 poll : R(read);
4834 MS : R;
4835 %}
4836
4837 pipe_class br(Universe br, label labl) %{
4838 single_instruction_with_delay_slot;
4839 BR : R;
4840 %}
4841
4842 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
4843 single_instruction_with_delay_slot;
4844 cr : E(read);
4845 BR : R;
4846 %}
4847
4848 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
4849 single_instruction_with_delay_slot;
4850 op1 : E(read);
4851 BR : R;
4852 MS : R;
4853 %}
4854
4855 // Compare and branch
4856 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
4857 instruction_count(2); has_delay_slot;
4858 cr : E(write);
4859 src1 : R(read);
4860 src2 : R(read);
4861 IALU : R;
4862 BR : R;
4863 %}
4864
4865 // Compare and branch
4866 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
4867 instruction_count(2); has_delay_slot;
4868 cr : E(write);
4869 src1 : R(read);
4870 IALU : R;
4871 BR : R;
4872 %}
4873
4874 // Compare and branch using cbcond
4875 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
4876 single_instruction;
4877 src1 : E(read);
4878 src2 : E(read);
4879 IALU : R;
4880 BR : R;
4881 %}
4882
4883 // Compare and branch using cbcond
4884 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
4885 single_instruction;
4886 src1 : E(read);
4887 IALU : R;
4888 BR : R;
4889 %}
4890
4891 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
4892 single_instruction_with_delay_slot;
4893 cr : E(read);
4894 BR : R;
4895 %}
4896
4897 pipe_class br_nop() %{
4898 single_instruction;
4899 BR : R;
4900 %}
4901
4902 pipe_class simple_call(method meth) %{
4903 instruction_count(2); multiple_bundles; force_serialization;
4904 fixed_latency(100);
4905 BR : R(1);
4906 MS : R(1);
4907 A0 : R(1);
4908 %}
4909
4910 pipe_class compiled_call(method meth) %{
4911 instruction_count(1); multiple_bundles; force_serialization;
4912 fixed_latency(100);
4913 MS : R(1);
4914 %}
4915
4916 pipe_class call(method meth) %{
4917 instruction_count(0); multiple_bundles; force_serialization;
4918 fixed_latency(100);
4919 %}
4920
4921 pipe_class tail_call(Universe ignore, label labl) %{
4922 single_instruction; has_delay_slot;
4923 fixed_latency(100);
4924 BR : R(1);
4925 MS : R(1);
4926 %}
4927
4928 pipe_class ret(Universe ignore) %{
4929 single_instruction; has_delay_slot;
4930 BR : R(1);
4931 MS : R(1);
4932 %}
4933
4934 pipe_class ret_poll(g3RegP poll) %{
4935 instruction_count(3); has_delay_slot;
4936 poll : E(read);
4937 MS : R;
4938 %}
4939
4940 // The real do-nothing guy
4941 pipe_class empty( ) %{
4942 instruction_count(0);
4943 %}
4944
4945 pipe_class long_memory_op() %{
4946 instruction_count(0); multiple_bundles; force_serialization;
4947 fixed_latency(25);
4948 MS : R(1);
4949 %}
4950
4951 // Check-cast
4952 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
4953 array : R(read);
4954 match : R(read);
4955 IALU : R(2);
4956 BR : R(2);
4957 MS : R;
4958 %}
4959
4960 // Convert FPU flags into +1,0,-1
4961 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
4962 src1 : E(read);
4963 src2 : E(read);
4964 dst : E(write);
4965 FA : R;
4966 MS : R(2);
4967 BR : R(2);
4968 %}
4969
4970 // Compare for p < q, and conditionally add y
4971 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
4972 p : E(read);
4973 q : E(read);
4974 y : E(read);
4975 IALU : R(3)
4976 %}
4977
4978 // Perform a compare, then move conditionally in a branch delay slot.
4979 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
4980 src2 : E(read);
4981 srcdst : E(read);
4982 IALU : R;
4983 BR : R;
4984 %}
4985
4986 // Define the class for the Nop node
4987 define %{
4988 MachNop = ialu_nop;
4989 %}
4990
4991 %}
4992
4993 //----------INSTRUCTIONS-------------------------------------------------------
4994
4995 //------------Special Stack Slot instructions - no match rules-----------------
4996 instruct stkI_to_regF(regF dst, stackSlotI src) %{
4997 // No match rule to avoid chain rule match.
4998 effect(DEF dst, USE src);
4999 ins_cost(MEMORY_REF_COST);
5000 format %{ "LDF $src,$dst\t! stkI to regF" %}
5001 opcode(Assembler::ldf_op3);
5002 ins_encode(simple_form3_mem_reg(src, dst));
5003 ins_pipe(floadF_stk);
5004 %}
5005
5006 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5007 // No match rule to avoid chain rule match.
5008 effect(DEF dst, USE src);
5009 ins_cost(MEMORY_REF_COST);
5010 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5011 opcode(Assembler::lddf_op3);
5012 ins_encode(simple_form3_mem_reg(src, dst));
5013 ins_pipe(floadD_stk);
5014 %}
5015
5016 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5017 // No match rule to avoid chain rule match.
5018 effect(DEF dst, USE src);
5019 ins_cost(MEMORY_REF_COST);
5020 format %{ "STF $src,$dst\t! regF to stkI" %}
5021 opcode(Assembler::stf_op3);
5022 ins_encode(simple_form3_mem_reg(dst, src));
5023 ins_pipe(fstoreF_stk_reg);
5024 %}
5025
5026 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5027 // No match rule to avoid chain rule match.
5028 effect(DEF dst, USE src);
5029 ins_cost(MEMORY_REF_COST);
5030 format %{ "STDF $src,$dst\t! regD to stkL" %}
5031 opcode(Assembler::stdf_op3);
5032 ins_encode(simple_form3_mem_reg(dst, src));
5033 ins_pipe(fstoreD_stk_reg);
5034 %}
5035
5036 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5037 effect(DEF dst, USE src);
5038 ins_cost(MEMORY_REF_COST*2);
5039 format %{ "STW $src,$dst.hi\t! long\n\t"
5040 "STW R_G0,$dst.lo" %}
5041 opcode(Assembler::stw_op3);
5042 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5043 ins_pipe(lstoreI_stk_reg);
5044 %}
5045
5046 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5047 // No match rule to avoid chain rule match.
5048 effect(DEF dst, USE src);
5049 ins_cost(MEMORY_REF_COST);
5050 format %{ "STX $src,$dst\t! regL to stkD" %}
5051 opcode(Assembler::stx_op3);
5052 ins_encode(simple_form3_mem_reg( dst, src ) );
5053 ins_pipe(istore_stk_reg);
5054 %}
5055
5056 //---------- Chain stack slots between similar types --------
5057
5058 // Load integer from stack slot
5059 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5060 match(Set dst src);
5061 ins_cost(MEMORY_REF_COST);
5062
5063 format %{ "LDUW $src,$dst\t!stk" %}
5064 opcode(Assembler::lduw_op3);
5065 ins_encode(simple_form3_mem_reg( src, dst ) );
5066 ins_pipe(iload_mem);
5067 %}
5068
5069 // Store integer to stack slot
5070 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5071 match(Set dst src);
5072 ins_cost(MEMORY_REF_COST);
5073
5074 format %{ "STW $src,$dst\t!stk" %}
5075 opcode(Assembler::stw_op3);
5076 ins_encode(simple_form3_mem_reg( dst, src ) );
5077 ins_pipe(istore_mem_reg);
5078 %}
5079
5080 // Load long from stack slot
5081 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5082 match(Set dst src);
5083
5084 ins_cost(MEMORY_REF_COST);
5085 format %{ "LDX $src,$dst\t! long" %}
5086 opcode(Assembler::ldx_op3);
5087 ins_encode(simple_form3_mem_reg( src, dst ) );
5088 ins_pipe(iload_mem);
5089 %}
5090
5091 // Store long to stack slot
5092 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5093 match(Set dst src);
5094
5095 ins_cost(MEMORY_REF_COST);
5096 format %{ "STX $src,$dst\t! long" %}
5097 opcode(Assembler::stx_op3);
5098 ins_encode(simple_form3_mem_reg( dst, src ) );
5099 ins_pipe(istore_mem_reg);
5100 %}
5101
5102 // Load pointer from stack slot, 64-bit encoding
5103 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5104 match(Set dst src);
5105 ins_cost(MEMORY_REF_COST);
5106 format %{ "LDX $src,$dst\t!ptr" %}
5107 opcode(Assembler::ldx_op3);
5108 ins_encode(simple_form3_mem_reg( src, dst ) );
5109 ins_pipe(iload_mem);
5110 %}
5111
5112 // Store pointer to stack slot
5113 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5114 match(Set dst src);
5115 ins_cost(MEMORY_REF_COST);
5116 format %{ "STX $src,$dst\t!ptr" %}
5117 opcode(Assembler::stx_op3);
5118 ins_encode(simple_form3_mem_reg( dst, src ) );
5119 ins_pipe(istore_mem_reg);
5120 %}
5121
5122 //------------Special Nop instructions for bundling - no match rules-----------
5123 // Nop using the A0 functional unit
5124 instruct Nop_A0() %{
5125 ins_cost(0);
5126
5127 format %{ "NOP ! Alu Pipeline" %}
5128 opcode(Assembler::or_op3, Assembler::arith_op);
5129 ins_encode( form2_nop() );
5130 ins_pipe(ialu_nop_A0);
5131 %}
5132
5133 // Nop using the A1 functional unit
5134 instruct Nop_A1( ) %{
5135 ins_cost(0);
5136
5137 format %{ "NOP ! Alu Pipeline" %}
5138 opcode(Assembler::or_op3, Assembler::arith_op);
5139 ins_encode( form2_nop() );
5140 ins_pipe(ialu_nop_A1);
5141 %}
5142
5143 // Nop using the memory functional unit
5144 instruct Nop_MS( ) %{
5145 ins_cost(0);
5146
5147 format %{ "NOP ! Memory Pipeline" %}
5148 ins_encode( emit_mem_nop );
5149 ins_pipe(mem_nop);
5150 %}
5151
5152 // Nop using the floating add functional unit
5153 instruct Nop_FA( ) %{
5154 ins_cost(0);
5155
5156 format %{ "NOP ! Floating Add Pipeline" %}
5157 ins_encode( emit_fadd_nop );
5158 ins_pipe(fadd_nop);
5159 %}
5160
5161 // Nop using the branch functional unit
5162 instruct Nop_BR( ) %{
5163 ins_cost(0);
5164
5165 format %{ "NOP ! Branch Pipeline" %}
5166 ins_encode( emit_br_nop );
5167 ins_pipe(br_nop);
5168 %}
5169
5170 //----------Load/Store/Move Instructions---------------------------------------
5171 //----------Load Instructions--------------------------------------------------
5172 // Load Byte (8bit signed)
5173 instruct loadB(iRegI dst, memory mem) %{
5174 match(Set dst (LoadB mem));
5175 ins_cost(MEMORY_REF_COST);
5176
5177 size(4);
5178 format %{ "LDSB $mem,$dst\t! byte" %}
5179 ins_encode %{
5180 __ ldsb($mem$$Address, $dst$$Register);
5181 %}
5182 ins_pipe(iload_mask_mem);
5183 %}
5184
5185 // Load Byte (8bit signed) into a Long Register
5186 instruct loadB2L(iRegL dst, memory mem) %{
5187 match(Set dst (ConvI2L (LoadB mem)));
5188 ins_cost(MEMORY_REF_COST);
5189
5190 size(4);
5191 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5192 ins_encode %{
5193 __ ldsb($mem$$Address, $dst$$Register);
5194 %}
5195 ins_pipe(iload_mask_mem);
5196 %}
5197
5198 // Load Unsigned Byte (8bit UNsigned) into an int reg
5199 instruct loadUB(iRegI dst, memory mem) %{
5200 match(Set dst (LoadUB mem));
5201 ins_cost(MEMORY_REF_COST);
5202
5203 size(4);
5204 format %{ "LDUB $mem,$dst\t! ubyte" %}
5205 ins_encode %{
5206 __ ldub($mem$$Address, $dst$$Register);
5207 %}
5208 ins_pipe(iload_mem);
5209 %}
5210
5211 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5212 instruct loadUB2L(iRegL dst, memory mem) %{
5213 match(Set dst (ConvI2L (LoadUB mem)));
5214 ins_cost(MEMORY_REF_COST);
5215
5216 size(4);
5217 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5218 ins_encode %{
5219 __ ldub($mem$$Address, $dst$$Register);
5220 %}
5221 ins_pipe(iload_mem);
5222 %}
5223
5224 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5225 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{
5226 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5227 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5228
5229 size(2*4);
5230 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t"
5231 "AND $dst,right_n_bits($mask, 8),$dst" %}
5232 ins_encode %{
5233 __ ldub($mem$$Address, $dst$$Register);
5234 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register);
5235 %}
5236 ins_pipe(iload_mem);
5237 %}
5238
5239 // Load Short (16bit signed)
5240 instruct loadS(iRegI dst, memory mem) %{
5241 match(Set dst (LoadS mem));
5242 ins_cost(MEMORY_REF_COST);
5243
5244 size(4);
5245 format %{ "LDSH $mem,$dst\t! short" %}
5246 ins_encode %{
5247 __ ldsh($mem$$Address, $dst$$Register);
5248 %}
5249 ins_pipe(iload_mask_mem);
5250 %}
5251
5252 // Load Short (16 bit signed) to Byte (8 bit signed)
5253 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5254 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5255 ins_cost(MEMORY_REF_COST);
5256
5257 size(4);
5258
5259 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5260 ins_encode %{
5261 __ ldsb($mem$$Address, $dst$$Register, 1);
5262 %}
5263 ins_pipe(iload_mask_mem);
5264 %}
5265
5266 // Load Short (16bit signed) into a Long Register
5267 instruct loadS2L(iRegL dst, memory mem) %{
5268 match(Set dst (ConvI2L (LoadS mem)));
5269 ins_cost(MEMORY_REF_COST);
5270
5271 size(4);
5272 format %{ "LDSH $mem,$dst\t! short -> long" %}
5273 ins_encode %{
5274 __ ldsh($mem$$Address, $dst$$Register);
5275 %}
5276 ins_pipe(iload_mask_mem);
5277 %}
5278
5279 // Load Unsigned Short/Char (16bit UNsigned)
5280 instruct loadUS(iRegI dst, memory mem) %{
5281 match(Set dst (LoadUS mem));
5282 ins_cost(MEMORY_REF_COST);
5283
5284 size(4);
5285 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5286 ins_encode %{
5287 __ lduh($mem$$Address, $dst$$Register);
5288 %}
5289 ins_pipe(iload_mem);
5290 %}
5291
5292 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5293 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5294 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5295 ins_cost(MEMORY_REF_COST);
5296
5297 size(4);
5298 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5299 ins_encode %{
5300 __ ldsb($mem$$Address, $dst$$Register, 1);
5301 %}
5302 ins_pipe(iload_mask_mem);
5303 %}
5304
5305 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5306 instruct loadUS2L(iRegL dst, memory mem) %{
5307 match(Set dst (ConvI2L (LoadUS mem)));
5308 ins_cost(MEMORY_REF_COST);
5309
5310 size(4);
5311 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5312 ins_encode %{
5313 __ lduh($mem$$Address, $dst$$Register);
5314 %}
5315 ins_pipe(iload_mem);
5316 %}
5317
5318 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5319 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5320 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5321 ins_cost(MEMORY_REF_COST);
5322
5323 size(4);
5324 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5325 ins_encode %{
5326 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5327 %}
5328 ins_pipe(iload_mem);
5329 %}
5330
5331 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5332 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5333 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5334 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5335
5336 size(2*4);
5337 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5338 "AND $dst,$mask,$dst" %}
5339 ins_encode %{
5340 Register Rdst = $dst$$Register;
5341 __ lduh($mem$$Address, Rdst);
5342 __ and3(Rdst, $mask$$constant, Rdst);
5343 %}
5344 ins_pipe(iload_mem);
5345 %}
5346
5347 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register
5348 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5349 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5350 effect(TEMP dst, TEMP tmp);
5351 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5352
5353 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t"
5354 "SET right_n_bits($mask, 16),$tmp\n\t"
5355 "AND $dst,$tmp,$dst" %}
5356 ins_encode %{
5357 Register Rdst = $dst$$Register;
5358 Register Rtmp = $tmp$$Register;
5359 __ lduh($mem$$Address, Rdst);
5360 __ set($mask$$constant & right_n_bits(16), Rtmp);
5361 __ and3(Rdst, Rtmp, Rdst);
5362 %}
5363 ins_pipe(iload_mem);
5364 %}
5365
5366 // Load Integer
5367 instruct loadI(iRegI dst, memory mem) %{
5368 match(Set dst (LoadI mem));
5369 ins_cost(MEMORY_REF_COST);
5370
5371 size(4);
5372 format %{ "LDUW $mem,$dst\t! int" %}
5373 ins_encode %{
5374 __ lduw($mem$$Address, $dst$$Register);
5375 %}
5376 ins_pipe(iload_mem);
5377 %}
5378
5379 // Load Integer to Byte (8 bit signed)
5380 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5381 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5382 ins_cost(MEMORY_REF_COST);
5383
5384 size(4);
5385
5386 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5387 ins_encode %{
5388 __ ldsb($mem$$Address, $dst$$Register, 3);
5389 %}
5390 ins_pipe(iload_mask_mem);
5391 %}
5392
5393 // Load Integer to Unsigned Byte (8 bit UNsigned)
5394 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5395 match(Set dst (AndI (LoadI mem) mask));
5396 ins_cost(MEMORY_REF_COST);
5397
5398 size(4);
5399
5400 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5401 ins_encode %{
5402 __ ldub($mem$$Address, $dst$$Register, 3);
5403 %}
5404 ins_pipe(iload_mask_mem);
5405 %}
5406
5407 // Load Integer to Short (16 bit signed)
5408 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5409 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5410 ins_cost(MEMORY_REF_COST);
5411
5412 size(4);
5413
5414 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5415 ins_encode %{
5416 __ ldsh($mem$$Address, $dst$$Register, 2);
5417 %}
5418 ins_pipe(iload_mask_mem);
5419 %}
5420
5421 // Load Integer to Unsigned Short (16 bit UNsigned)
5422 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5423 match(Set dst (AndI (LoadI mem) mask));
5424 ins_cost(MEMORY_REF_COST);
5425
5426 size(4);
5427
5428 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5429 ins_encode %{
5430 __ lduh($mem$$Address, $dst$$Register, 2);
5431 %}
5432 ins_pipe(iload_mask_mem);
5433 %}
5434
5435 // Load Integer into a Long Register
5436 instruct loadI2L(iRegL dst, memory mem) %{
5437 match(Set dst (ConvI2L (LoadI mem)));
5438 ins_cost(MEMORY_REF_COST);
5439
5440 size(4);
5441 format %{ "LDSW $mem,$dst\t! int -> long" %}
5442 ins_encode %{
5443 __ ldsw($mem$$Address, $dst$$Register);
5444 %}
5445 ins_pipe(iload_mask_mem);
5446 %}
5447
5448 // Load Integer with mask 0xFF into a Long Register
5449 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5450 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5451 ins_cost(MEMORY_REF_COST);
5452
5453 size(4);
5454 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5455 ins_encode %{
5456 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5457 %}
5458 ins_pipe(iload_mem);
5459 %}
5460
5461 // Load Integer with mask 0xFFFF into a Long Register
5462 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5463 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5464 ins_cost(MEMORY_REF_COST);
5465
5466 size(4);
5467 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5468 ins_encode %{
5469 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5470 %}
5471 ins_pipe(iload_mem);
5472 %}
5473
5474 // Load Integer with a 12-bit mask into a Long Register
5475 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5476 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5477 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5478
5479 size(2*4);
5480 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5481 "AND $dst,$mask,$dst" %}
5482 ins_encode %{
5483 Register Rdst = $dst$$Register;
5484 __ lduw($mem$$Address, Rdst);
5485 __ and3(Rdst, $mask$$constant, Rdst);
5486 %}
5487 ins_pipe(iload_mem);
5488 %}
5489
5490 // Load Integer with a 31-bit mask into a Long Register
5491 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5492 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5493 effect(TEMP dst, TEMP tmp);
5494 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5495
5496 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5497 "SET $mask,$tmp\n\t"
5498 "AND $dst,$tmp,$dst" %}
5499 ins_encode %{
5500 Register Rdst = $dst$$Register;
5501 Register Rtmp = $tmp$$Register;
5502 __ lduw($mem$$Address, Rdst);
5503 __ set($mask$$constant, Rtmp);
5504 __ and3(Rdst, Rtmp, Rdst);
5505 %}
5506 ins_pipe(iload_mem);
5507 %}
5508
5509 // Load Unsigned Integer into a Long Register
5510 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5511 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5512 ins_cost(MEMORY_REF_COST);
5513
5514 size(4);
5515 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5516 ins_encode %{
5517 __ lduw($mem$$Address, $dst$$Register);
5518 %}
5519 ins_pipe(iload_mem);
5520 %}
5521
5522 // Load Long - aligned
5523 instruct loadL(iRegL dst, memory mem ) %{
5524 match(Set dst (LoadL mem));
5525 ins_cost(MEMORY_REF_COST);
5526
5527 size(4);
5528 format %{ "LDX $mem,$dst\t! long" %}
5529 ins_encode %{
5530 __ ldx($mem$$Address, $dst$$Register);
5531 %}
5532 ins_pipe(iload_mem);
5533 %}
5534
5535 // Load Long - UNaligned
5536 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5537 match(Set dst (LoadL_unaligned mem));
5538 effect(KILL tmp);
5539 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5540 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5541 "\tLDUW $mem ,$dst\n"
5542 "\tSLLX #32, $dst, $dst\n"
5543 "\tOR $dst, R_O7, $dst" %}
5544 opcode(Assembler::lduw_op3);
5545 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5546 ins_pipe(iload_mem);
5547 %}
5548
5549 // Load Range
5550 instruct loadRange(iRegI dst, memory mem) %{
5551 match(Set dst (LoadRange mem));
5552 ins_cost(MEMORY_REF_COST);
5553
5554 format %{ "LDUW $mem,$dst\t! range" %}
5555 opcode(Assembler::lduw_op3);
5556 ins_encode(simple_form3_mem_reg( mem, dst ) );
5557 ins_pipe(iload_mem);
5558 %}
5559
5560 // Load Integer into %f register (for fitos/fitod)
5561 instruct loadI_freg(regF dst, memory mem) %{
5562 match(Set dst (LoadI mem));
5563 ins_cost(MEMORY_REF_COST);
5564
5565 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5566 opcode(Assembler::ldf_op3);
5567 ins_encode(simple_form3_mem_reg( mem, dst ) );
5568 ins_pipe(floadF_mem);
5569 %}
5570
5571 // Load Pointer
5572 instruct loadP(iRegP dst, memory mem) %{
5573 match(Set dst (LoadP mem));
5574 ins_cost(MEMORY_REF_COST);
5575 size(4);
5576
5577 format %{ "LDX $mem,$dst\t! ptr" %}
5578 ins_encode %{
5579 __ ldx($mem$$Address, $dst$$Register);
5580 %}
5581 ins_pipe(iload_mem);
5582 %}
5583
5584 // Load Compressed Pointer
5585 instruct loadN(iRegN dst, memory mem) %{
5586 match(Set dst (LoadN mem));
5587 ins_cost(MEMORY_REF_COST);
5588 size(4);
5589
5590 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5591 ins_encode %{
5592 __ lduw($mem$$Address, $dst$$Register);
5593 %}
5594 ins_pipe(iload_mem);
5595 %}
5596
5597 // Load Klass Pointer
5598 instruct loadKlass(iRegP dst, memory mem) %{
5599 match(Set dst (LoadKlass mem));
5600 ins_cost(MEMORY_REF_COST);
5601 size(4);
5602
5603 format %{ "LDX $mem,$dst\t! klass ptr" %}
5604 ins_encode %{
5605 __ ldx($mem$$Address, $dst$$Register);
5606 %}
5607 ins_pipe(iload_mem);
5608 %}
5609
5610 // Load narrow Klass Pointer
5611 instruct loadNKlass(iRegN dst, memory mem) %{
5612 match(Set dst (LoadNKlass mem));
5613 ins_cost(MEMORY_REF_COST);
5614 size(4);
5615
5616 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5617 ins_encode %{
5618 __ lduw($mem$$Address, $dst$$Register);
5619 %}
5620 ins_pipe(iload_mem);
5621 %}
5622
5623 // Load Double
5624 instruct loadD(regD dst, memory mem) %{
5625 match(Set dst (LoadD mem));
5626 ins_cost(MEMORY_REF_COST);
5627
5628 format %{ "LDDF $mem,$dst" %}
5629 opcode(Assembler::lddf_op3);
5630 ins_encode(simple_form3_mem_reg( mem, dst ) );
5631 ins_pipe(floadD_mem);
5632 %}
5633
5634 // Load Double - UNaligned
5635 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5636 match(Set dst (LoadD_unaligned mem));
5637 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5638 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5639 "\tLDF $mem+4,$dst.lo\t!" %}
5640 opcode(Assembler::ldf_op3);
5641 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5642 ins_pipe(iload_mem);
5643 %}
5644
5645 // Load Float
5646 instruct loadF(regF dst, memory mem) %{
5647 match(Set dst (LoadF mem));
5648 ins_cost(MEMORY_REF_COST);
5649
5650 format %{ "LDF $mem,$dst" %}
5651 opcode(Assembler::ldf_op3);
5652 ins_encode(simple_form3_mem_reg( mem, dst ) );
5653 ins_pipe(floadF_mem);
5654 %}
5655
5656 // Load Constant
5657 instruct loadConI( iRegI dst, immI src ) %{
5658 match(Set dst src);
5659 ins_cost(DEFAULT_COST * 3/2);
5660 format %{ "SET $src,$dst" %}
5661 ins_encode( Set32(src, dst) );
5662 ins_pipe(ialu_hi_lo_reg);
5663 %}
5664
5665 instruct loadConI13( iRegI dst, immI13 src ) %{
5666 match(Set dst src);
5667
5668 size(4);
5669 format %{ "MOV $src,$dst" %}
5670 ins_encode( Set13( src, dst ) );
5671 ins_pipe(ialu_imm);
5672 %}
5673
5674 instruct loadConP_set(iRegP dst, immP_set con) %{
5675 match(Set dst con);
5676 ins_cost(DEFAULT_COST * 3/2);
5677 format %{ "SET $con,$dst\t! ptr" %}
5678 ins_encode %{
5679 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5680 intptr_t val = $con$$constant;
5681 if (constant_reloc == relocInfo::oop_type) {
5682 __ set_oop_constant((jobject) val, $dst$$Register);
5683 } else if (constant_reloc == relocInfo::metadata_type) {
5684 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5685 } else { // non-oop pointers, e.g. card mark base, heap top
5686 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5687 __ set(val, $dst$$Register);
5688 }
5689 %}
5690 ins_pipe(loadConP);
5691 %}
5692
5693 instruct loadConP_load(iRegP dst, immP_load con) %{
5694 match(Set dst con);
5695 ins_cost(MEMORY_REF_COST);
5696 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
5697 ins_encode %{
5698 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
5699 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
5700 %}
5701 ins_pipe(loadConP);
5702 %}
5703
5704 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
5705 match(Set dst con);
5706 ins_cost(DEFAULT_COST * 3/2);
5707 format %{ "SET $con,$dst\t! non-oop ptr" %}
5708 ins_encode %{
5709 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
5710 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
5711 } else {
5712 __ set($con$$constant, $dst$$Register);
5713 }
5714 %}
5715 ins_pipe(loadConP);
5716 %}
5717
5718 instruct loadConP0(iRegP dst, immP0 src) %{
5719 match(Set dst src);
5720
5721 size(4);
5722 format %{ "CLR $dst\t!ptr" %}
5723 ins_encode %{
5724 __ clr($dst$$Register);
5725 %}
5726 ins_pipe(ialu_imm);
5727 %}
5728
5729 instruct loadConP_poll(iRegP dst, immP_poll src) %{
5730 match(Set dst src);
5731 ins_cost(DEFAULT_COST);
5732 format %{ "SET $src,$dst\t!ptr" %}
5733 ins_encode %{
5734 AddressLiteral polling_page(os::get_polling_page());
5735 __ sethi(polling_page, reg_to_register_object($dst$$reg));
5736 %}
5737 ins_pipe(loadConP_poll);
5738 %}
5739
5740 instruct loadConN0(iRegN dst, immN0 src) %{
5741 match(Set dst src);
5742
5743 size(4);
5744 format %{ "CLR $dst\t! compressed NULL ptr" %}
5745 ins_encode %{
5746 __ clr($dst$$Register);
5747 %}
5748 ins_pipe(ialu_imm);
5749 %}
5750
5751 instruct loadConN(iRegN dst, immN src) %{
5752 match(Set dst src);
5753 ins_cost(DEFAULT_COST * 3/2);
5754 format %{ "SET $src,$dst\t! compressed ptr" %}
5755 ins_encode %{
5756 Register dst = $dst$$Register;
5757 __ set_narrow_oop((jobject)$src$$constant, dst);
5758 %}
5759 ins_pipe(ialu_hi_lo_reg);
5760 %}
5761
5762 instruct loadConNKlass(iRegN dst, immNKlass src) %{
5763 match(Set dst src);
5764 ins_cost(DEFAULT_COST * 3/2);
5765 format %{ "SET $src,$dst\t! compressed klass ptr" %}
5766 ins_encode %{
5767 Register dst = $dst$$Register;
5768 __ set_narrow_klass((Klass*)$src$$constant, dst);
5769 %}
5770 ins_pipe(ialu_hi_lo_reg);
5771 %}
5772
5773 // Materialize long value (predicated by immL_cheap).
5774 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
5775 match(Set dst con);
5776 effect(KILL tmp);
5777 ins_cost(DEFAULT_COST * 3);
5778 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
5779 ins_encode %{
5780 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
5781 %}
5782 ins_pipe(loadConL);
5783 %}
5784
5785 // Load long value from constant table (predicated by immL_expensive).
5786 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
5787 match(Set dst con);
5788 ins_cost(MEMORY_REF_COST);
5789 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
5790 ins_encode %{
5791 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
5792 __ ldx($constanttablebase, con_offset, $dst$$Register);
5793 %}
5794 ins_pipe(loadConL);
5795 %}
5796
5797 instruct loadConL0( iRegL dst, immL0 src ) %{
5798 match(Set dst src);
5799 ins_cost(DEFAULT_COST);
5800 size(4);
5801 format %{ "CLR $dst\t! long" %}
5802 ins_encode( Set13( src, dst ) );
5803 ins_pipe(ialu_imm);
5804 %}
5805
5806 instruct loadConL13( iRegL dst, immL13 src ) %{
5807 match(Set dst src);
5808 ins_cost(DEFAULT_COST * 2);
5809
5810 size(4);
5811 format %{ "MOV $src,$dst\t! long" %}
5812 ins_encode( Set13( src, dst ) );
5813 ins_pipe(ialu_imm);
5814 %}
5815
5816 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
5817 match(Set dst con);
5818 effect(KILL tmp);
5819 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
5820 ins_encode %{
5821 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
5822 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
5823 %}
5824 ins_pipe(loadConFD);
5825 %}
5826
5827 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
5828 match(Set dst con);
5829 effect(KILL tmp);
5830 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
5831 ins_encode %{
5832 // XXX This is a quick fix for 6833573.
5833 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
5834 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
5835 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
5836 %}
5837 ins_pipe(loadConFD);
5838 %}
5839
5840 // Prefetch instructions for allocation.
5841 // Must be safe to execute with invalid address (cannot fault).
5842
5843 instruct prefetchAlloc( memory mem ) %{
5844 predicate(AllocatePrefetchInstr == 0);
5845 match( PrefetchAllocation mem );
5846 ins_cost(MEMORY_REF_COST);
5847
5848 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
5849 opcode(Assembler::prefetch_op3);
5850 ins_encode( form3_mem_prefetch_write( mem ) );
5851 ins_pipe(iload_mem);
5852 %}
5853
5854 // Use BIS instruction to prefetch for allocation.
5855 // Could fault, need space at the end of TLAB.
5856 instruct prefetchAlloc_bis( iRegP dst ) %{
5857 predicate(AllocatePrefetchInstr == 1);
5858 match( PrefetchAllocation dst );
5859 ins_cost(MEMORY_REF_COST);
5860 size(4);
5861
5862 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
5863 ins_encode %{
5864 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
5865 %}
5866 ins_pipe(istore_mem_reg);
5867 %}
5868
5869 // Next code is used for finding next cache line address to prefetch.
5870 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
5871 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
5872 ins_cost(DEFAULT_COST);
5873 size(4);
5874
5875 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
5876 ins_encode %{
5877 __ and3($src$$Register, $mask$$constant, $dst$$Register);
5878 %}
5879 ins_pipe(ialu_reg_imm);
5880 %}
5881
5882 //----------Store Instructions-------------------------------------------------
5883 // Store Byte
5884 instruct storeB(memory mem, iRegI src) %{
5885 match(Set mem (StoreB mem src));
5886 ins_cost(MEMORY_REF_COST);
5887
5888 format %{ "STB $src,$mem\t! byte" %}
5889 opcode(Assembler::stb_op3);
5890 ins_encode(simple_form3_mem_reg( mem, src ) );
5891 ins_pipe(istore_mem_reg);
5892 %}
5893
5894 instruct storeB0(memory mem, immI0 src) %{
5895 match(Set mem (StoreB mem src));
5896 ins_cost(MEMORY_REF_COST);
5897
5898 format %{ "STB $src,$mem\t! byte" %}
5899 opcode(Assembler::stb_op3);
5900 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5901 ins_pipe(istore_mem_zero);
5902 %}
5903
5904 instruct storeCM0(memory mem, immI0 src) %{
5905 match(Set mem (StoreCM mem src));
5906 ins_cost(MEMORY_REF_COST);
5907
5908 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
5909 opcode(Assembler::stb_op3);
5910 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5911 ins_pipe(istore_mem_zero);
5912 %}
5913
5914 // Store Char/Short
5915 instruct storeC(memory mem, iRegI src) %{
5916 match(Set mem (StoreC mem src));
5917 ins_cost(MEMORY_REF_COST);
5918
5919 format %{ "STH $src,$mem\t! short" %}
5920 opcode(Assembler::sth_op3);
5921 ins_encode(simple_form3_mem_reg( mem, src ) );
5922 ins_pipe(istore_mem_reg);
5923 %}
5924
5925 instruct storeC0(memory mem, immI0 src) %{
5926 match(Set mem (StoreC mem src));
5927 ins_cost(MEMORY_REF_COST);
5928
5929 format %{ "STH $src,$mem\t! short" %}
5930 opcode(Assembler::sth_op3);
5931 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5932 ins_pipe(istore_mem_zero);
5933 %}
5934
5935 // Store Integer
5936 instruct storeI(memory mem, iRegI src) %{
5937 match(Set mem (StoreI mem src));
5938 ins_cost(MEMORY_REF_COST);
5939
5940 format %{ "STW $src,$mem" %}
5941 opcode(Assembler::stw_op3);
5942 ins_encode(simple_form3_mem_reg( mem, src ) );
5943 ins_pipe(istore_mem_reg);
5944 %}
5945
5946 // Store Long
5947 instruct storeL(memory mem, iRegL src) %{
5948 match(Set mem (StoreL mem src));
5949 ins_cost(MEMORY_REF_COST);
5950 format %{ "STX $src,$mem\t! long" %}
5951 opcode(Assembler::stx_op3);
5952 ins_encode(simple_form3_mem_reg( mem, src ) );
5953 ins_pipe(istore_mem_reg);
5954 %}
5955
5956 instruct storeI0(memory mem, immI0 src) %{
5957 match(Set mem (StoreI mem src));
5958 ins_cost(MEMORY_REF_COST);
5959
5960 format %{ "STW $src,$mem" %}
5961 opcode(Assembler::stw_op3);
5962 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5963 ins_pipe(istore_mem_zero);
5964 %}
5965
5966 instruct storeL0(memory mem, immL0 src) %{
5967 match(Set mem (StoreL mem src));
5968 ins_cost(MEMORY_REF_COST);
5969
5970 format %{ "STX $src,$mem" %}
5971 opcode(Assembler::stx_op3);
5972 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5973 ins_pipe(istore_mem_zero);
5974 %}
5975
5976 // Store Integer from float register (used after fstoi)
5977 instruct storeI_Freg(memory mem, regF src) %{
5978 match(Set mem (StoreI mem src));
5979 ins_cost(MEMORY_REF_COST);
5980
5981 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
5982 opcode(Assembler::stf_op3);
5983 ins_encode(simple_form3_mem_reg( mem, src ) );
5984 ins_pipe(fstoreF_mem_reg);
5985 %}
5986
5987 // Store Pointer
5988 instruct storeP(memory dst, sp_ptr_RegP src) %{
5989 match(Set dst (StoreP dst src));
5990 ins_cost(MEMORY_REF_COST);
5991
5992 format %{ "STX $src,$dst\t! ptr" %}
5993 opcode(Assembler::stx_op3, 0, REGP_OP);
5994 ins_encode( form3_mem_reg( dst, src ) );
5995 ins_pipe(istore_mem_spORreg);
5996 %}
5997
5998 instruct storeP0(memory dst, immP0 src) %{
5999 match(Set dst (StoreP dst src));
6000 ins_cost(MEMORY_REF_COST);
6001
6002 format %{ "STX $src,$dst\t! ptr" %}
6003 opcode(Assembler::stx_op3, 0, REGP_OP);
6004 ins_encode( form3_mem_reg( dst, R_G0 ) );
6005 ins_pipe(istore_mem_zero);
6006 %}
6007
6008 // Store Compressed Pointer
6009 instruct storeN(memory dst, iRegN src) %{
6010 match(Set dst (StoreN dst src));
6011 ins_cost(MEMORY_REF_COST);
6012 size(4);
6013
6014 format %{ "STW $src,$dst\t! compressed ptr" %}
6015 ins_encode %{
6016 Register base = as_Register($dst$$base);
6017 Register index = as_Register($dst$$index);
6018 Register src = $src$$Register;
6019 if (index != G0) {
6020 __ stw(src, base, index);
6021 } else {
6022 __ stw(src, base, $dst$$disp);
6023 }
6024 %}
6025 ins_pipe(istore_mem_spORreg);
6026 %}
6027
6028 instruct storeNKlass(memory dst, iRegN src) %{
6029 match(Set dst (StoreNKlass dst src));
6030 ins_cost(MEMORY_REF_COST);
6031 size(4);
6032
6033 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6034 ins_encode %{
6035 Register base = as_Register($dst$$base);
6036 Register index = as_Register($dst$$index);
6037 Register src = $src$$Register;
6038 if (index != G0) {
6039 __ stw(src, base, index);
6040 } else {
6041 __ stw(src, base, $dst$$disp);
6042 }
6043 %}
6044 ins_pipe(istore_mem_spORreg);
6045 %}
6046
6047 instruct storeN0(memory dst, immN0 src) %{
6048 match(Set dst (StoreN dst src));
6049 ins_cost(MEMORY_REF_COST);
6050 size(4);
6051
6052 format %{ "STW $src,$dst\t! compressed ptr" %}
6053 ins_encode %{
6054 Register base = as_Register($dst$$base);
6055 Register index = as_Register($dst$$index);
6056 if (index != G0) {
6057 __ stw(0, base, index);
6058 } else {
6059 __ stw(0, base, $dst$$disp);
6060 }
6061 %}
6062 ins_pipe(istore_mem_zero);
6063 %}
6064
6065 // Store Double
6066 instruct storeD( memory mem, regD src) %{
6067 match(Set mem (StoreD mem src));
6068 ins_cost(MEMORY_REF_COST);
6069
6070 format %{ "STDF $src,$mem" %}
6071 opcode(Assembler::stdf_op3);
6072 ins_encode(simple_form3_mem_reg( mem, src ) );
6073 ins_pipe(fstoreD_mem_reg);
6074 %}
6075
6076 instruct storeD0( memory mem, immD0 src) %{
6077 match(Set mem (StoreD mem src));
6078 ins_cost(MEMORY_REF_COST);
6079
6080 format %{ "STX $src,$mem" %}
6081 opcode(Assembler::stx_op3);
6082 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6083 ins_pipe(fstoreD_mem_zero);
6084 %}
6085
6086 // Store Float
6087 instruct storeF( memory mem, regF src) %{
6088 match(Set mem (StoreF mem src));
6089 ins_cost(MEMORY_REF_COST);
6090
6091 format %{ "STF $src,$mem" %}
6092 opcode(Assembler::stf_op3);
6093 ins_encode(simple_form3_mem_reg( mem, src ) );
6094 ins_pipe(fstoreF_mem_reg);
6095 %}
6096
6097 instruct storeF0( memory mem, immF0 src) %{
6098 match(Set mem (StoreF mem src));
6099 ins_cost(MEMORY_REF_COST);
6100
6101 format %{ "STW $src,$mem\t! storeF0" %}
6102 opcode(Assembler::stw_op3);
6103 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6104 ins_pipe(fstoreF_mem_zero);
6105 %}
6106
6107 // Convert oop pointer into compressed form
6108 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6109 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6110 match(Set dst (EncodeP src));
6111 format %{ "encode_heap_oop $src, $dst" %}
6112 ins_encode %{
6113 __ encode_heap_oop($src$$Register, $dst$$Register);
6114 %}
6115 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6116 ins_pipe(ialu_reg);
6117 %}
6118
6119 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6120 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6121 match(Set dst (EncodeP src));
6122 format %{ "encode_heap_oop_not_null $src, $dst" %}
6123 ins_encode %{
6124 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6125 %}
6126 ins_pipe(ialu_reg);
6127 %}
6128
6129 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6130 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6131 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6132 match(Set dst (DecodeN src));
6133 format %{ "decode_heap_oop $src, $dst" %}
6134 ins_encode %{
6135 __ decode_heap_oop($src$$Register, $dst$$Register);
6136 %}
6137 ins_pipe(ialu_reg);
6138 %}
6139
6140 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6141 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6142 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6143 match(Set dst (DecodeN src));
6144 format %{ "decode_heap_oop_not_null $src, $dst" %}
6145 ins_encode %{
6146 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6147 %}
6148 ins_pipe(ialu_reg);
6149 %}
6150
6151 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6152 match(Set dst (EncodePKlass src));
6153 format %{ "encode_klass_not_null $src, $dst" %}
6154 ins_encode %{
6155 __ encode_klass_not_null($src$$Register, $dst$$Register);
6156 %}
6157 ins_pipe(ialu_reg);
6158 %}
6159
6160 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6161 match(Set dst (DecodeNKlass src));
6162 format %{ "decode_klass_not_null $src, $dst" %}
6163 ins_encode %{
6164 __ decode_klass_not_null($src$$Register, $dst$$Register);
6165 %}
6166 ins_pipe(ialu_reg);
6167 %}
6168
6169 //----------MemBar Instructions-----------------------------------------------
6170 // Memory barrier flavors
6171
6172 instruct membar_acquire() %{
6173 match(MemBarAcquire);
6174 match(LoadFence);
6175 ins_cost(4*MEMORY_REF_COST);
6176
6177 size(0);
6178 format %{ "MEMBAR-acquire" %}
6179 ins_encode( enc_membar_acquire );
6180 ins_pipe(long_memory_op);
6181 %}
6182
6183 instruct membar_acquire_lock() %{
6184 match(MemBarAcquireLock);
6185 ins_cost(0);
6186
6187 size(0);
6188 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6189 ins_encode( );
6190 ins_pipe(empty);
6191 %}
6192
6193 instruct membar_release() %{
6194 match(MemBarRelease);
6195 match(StoreFence);
6196 ins_cost(4*MEMORY_REF_COST);
6197
6198 size(0);
6199 format %{ "MEMBAR-release" %}
6200 ins_encode( enc_membar_release );
6201 ins_pipe(long_memory_op);
6202 %}
6203
6204 instruct membar_release_lock() %{
6205 match(MemBarReleaseLock);
6206 ins_cost(0);
6207
6208 size(0);
6209 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6210 ins_encode( );
6211 ins_pipe(empty);
6212 %}
6213
6214 instruct membar_volatile() %{
6215 match(MemBarVolatile);
6216 ins_cost(4*MEMORY_REF_COST);
6217
6218 size(4);
6219 format %{ "MEMBAR-volatile" %}
6220 ins_encode( enc_membar_volatile );
6221 ins_pipe(long_memory_op);
6222 %}
6223
6224 instruct unnecessary_membar_volatile() %{
6225 match(MemBarVolatile);
6226 predicate(Matcher::post_store_load_barrier(n));
6227 ins_cost(0);
6228
6229 size(0);
6230 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6231 ins_encode( );
6232 ins_pipe(empty);
6233 %}
6234
6235 instruct membar_storestore() %{
6236 match(MemBarStoreStore);
6237 ins_cost(0);
6238
6239 size(0);
6240 format %{ "!MEMBAR-storestore (empty encoding)" %}
6241 ins_encode( );
6242 ins_pipe(empty);
6243 %}
6244
6245 //----------Register Move Instructions-----------------------------------------
6246 instruct roundDouble_nop(regD dst) %{
6247 match(Set dst (RoundDouble dst));
6248 ins_cost(0);
6249 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6250 ins_encode( );
6251 ins_pipe(empty);
6252 %}
6253
6254
6255 instruct roundFloat_nop(regF dst) %{
6256 match(Set dst (RoundFloat dst));
6257 ins_cost(0);
6258 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6259 ins_encode( );
6260 ins_pipe(empty);
6261 %}
6262
6263
6264 // Cast Index to Pointer for unsafe natives
6265 instruct castX2P(iRegX src, iRegP dst) %{
6266 match(Set dst (CastX2P src));
6267
6268 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6269 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6270 ins_pipe(ialu_reg);
6271 %}
6272
6273 // Cast Pointer to Index for unsafe natives
6274 instruct castP2X(iRegP src, iRegX dst) %{
6275 match(Set dst (CastP2X src));
6276
6277 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6278 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6279 ins_pipe(ialu_reg);
6280 %}
6281
6282 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6283 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6284 match(Set stkSlot src); // chain rule
6285 ins_cost(MEMORY_REF_COST);
6286 format %{ "STDF $src,$stkSlot\t!stk" %}
6287 opcode(Assembler::stdf_op3);
6288 ins_encode(simple_form3_mem_reg(stkSlot, src));
6289 ins_pipe(fstoreD_stk_reg);
6290 %}
6291
6292 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6293 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6294 match(Set dst stkSlot); // chain rule
6295 ins_cost(MEMORY_REF_COST);
6296 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6297 opcode(Assembler::lddf_op3);
6298 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6299 ins_pipe(floadD_stk);
6300 %}
6301
6302 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6303 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6304 match(Set stkSlot src); // chain rule
6305 ins_cost(MEMORY_REF_COST);
6306 format %{ "STF $src,$stkSlot\t!stk" %}
6307 opcode(Assembler::stf_op3);
6308 ins_encode(simple_form3_mem_reg(stkSlot, src));
6309 ins_pipe(fstoreF_stk_reg);
6310 %}
6311
6312 //----------Conditional Move---------------------------------------------------
6313 // Conditional move
6314 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6315 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6316 ins_cost(150);
6317 format %{ "MOV$cmp $pcc,$src,$dst" %}
6318 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6319 ins_pipe(ialu_reg);
6320 %}
6321
6322 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6323 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6324 ins_cost(140);
6325 format %{ "MOV$cmp $pcc,$src,$dst" %}
6326 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6327 ins_pipe(ialu_imm);
6328 %}
6329
6330 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6331 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6332 ins_cost(150);
6333 size(4);
6334 format %{ "MOV$cmp $icc,$src,$dst" %}
6335 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6336 ins_pipe(ialu_reg);
6337 %}
6338
6339 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6340 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6341 ins_cost(140);
6342 size(4);
6343 format %{ "MOV$cmp $icc,$src,$dst" %}
6344 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6345 ins_pipe(ialu_imm);
6346 %}
6347
6348 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6349 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6350 ins_cost(150);
6351 size(4);
6352 format %{ "MOV$cmp $icc,$src,$dst" %}
6353 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6354 ins_pipe(ialu_reg);
6355 %}
6356
6357 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6358 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6359 ins_cost(140);
6360 size(4);
6361 format %{ "MOV$cmp $icc,$src,$dst" %}
6362 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6363 ins_pipe(ialu_imm);
6364 %}
6365
6366 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6367 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6368 ins_cost(150);
6369 size(4);
6370 format %{ "MOV$cmp $fcc,$src,$dst" %}
6371 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6372 ins_pipe(ialu_reg);
6373 %}
6374
6375 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6376 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6377 ins_cost(140);
6378 size(4);
6379 format %{ "MOV$cmp $fcc,$src,$dst" %}
6380 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6381 ins_pipe(ialu_imm);
6382 %}
6383
6384 // Conditional move for RegN. Only cmov(reg,reg).
6385 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6386 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6387 ins_cost(150);
6388 format %{ "MOV$cmp $pcc,$src,$dst" %}
6389 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6390 ins_pipe(ialu_reg);
6391 %}
6392
6393 // This instruction also works with CmpN so we don't need cmovNN_reg.
6394 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6395 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6396 ins_cost(150);
6397 size(4);
6398 format %{ "MOV$cmp $icc,$src,$dst" %}
6399 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6400 ins_pipe(ialu_reg);
6401 %}
6402
6403 // This instruction also works with CmpN so we don't need cmovNN_reg.
6404 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6405 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6406 ins_cost(150);
6407 size(4);
6408 format %{ "MOV$cmp $icc,$src,$dst" %}
6409 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6410 ins_pipe(ialu_reg);
6411 %}
6412
6413 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6414 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6415 ins_cost(150);
6416 size(4);
6417 format %{ "MOV$cmp $fcc,$src,$dst" %}
6418 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6419 ins_pipe(ialu_reg);
6420 %}
6421
6422 // Conditional move
6423 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6424 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6425 ins_cost(150);
6426 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6427 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6428 ins_pipe(ialu_reg);
6429 %}
6430
6431 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6432 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6433 ins_cost(140);
6434 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6435 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6436 ins_pipe(ialu_imm);
6437 %}
6438
6439 // This instruction also works with CmpN so we don't need cmovPN_reg.
6440 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6441 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6442 ins_cost(150);
6443
6444 size(4);
6445 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6446 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6447 ins_pipe(ialu_reg);
6448 %}
6449
6450 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6451 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6452 ins_cost(150);
6453
6454 size(4);
6455 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6456 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6457 ins_pipe(ialu_reg);
6458 %}
6459
6460 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6461 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6462 ins_cost(140);
6463
6464 size(4);
6465 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6466 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6467 ins_pipe(ialu_imm);
6468 %}
6469
6470 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6471 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6472 ins_cost(140);
6473
6474 size(4);
6475 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6476 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6477 ins_pipe(ialu_imm);
6478 %}
6479
6480 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6481 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6482 ins_cost(150);
6483 size(4);
6484 format %{ "MOV$cmp $fcc,$src,$dst" %}
6485 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6486 ins_pipe(ialu_imm);
6487 %}
6488
6489 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6490 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6491 ins_cost(140);
6492 size(4);
6493 format %{ "MOV$cmp $fcc,$src,$dst" %}
6494 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6495 ins_pipe(ialu_imm);
6496 %}
6497
6498 // Conditional move
6499 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6500 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6501 ins_cost(150);
6502 opcode(0x101);
6503 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6504 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6505 ins_pipe(int_conditional_float_move);
6506 %}
6507
6508 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6509 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6510 ins_cost(150);
6511
6512 size(4);
6513 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6514 opcode(0x101);
6515 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6516 ins_pipe(int_conditional_float_move);
6517 %}
6518
6519 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6520 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6521 ins_cost(150);
6522
6523 size(4);
6524 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6525 opcode(0x101);
6526 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6527 ins_pipe(int_conditional_float_move);
6528 %}
6529
6530 // Conditional move,
6531 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6532 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6533 ins_cost(150);
6534 size(4);
6535 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6536 opcode(0x1);
6537 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6538 ins_pipe(int_conditional_double_move);
6539 %}
6540
6541 // Conditional move
6542 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6543 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6544 ins_cost(150);
6545 size(4);
6546 opcode(0x102);
6547 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6548 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6549 ins_pipe(int_conditional_double_move);
6550 %}
6551
6552 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6553 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6554 ins_cost(150);
6555
6556 size(4);
6557 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6558 opcode(0x102);
6559 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6560 ins_pipe(int_conditional_double_move);
6561 %}
6562
6563 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6564 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6565 ins_cost(150);
6566
6567 size(4);
6568 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6569 opcode(0x102);
6570 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6571 ins_pipe(int_conditional_double_move);
6572 %}
6573
6574 // Conditional move,
6575 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6576 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6577 ins_cost(150);
6578 size(4);
6579 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6580 opcode(0x2);
6581 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6582 ins_pipe(int_conditional_double_move);
6583 %}
6584
6585 // Conditional move
6586 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6587 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6588 ins_cost(150);
6589 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6590 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6591 ins_pipe(ialu_reg);
6592 %}
6593
6594 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6595 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6596 ins_cost(140);
6597 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6598 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6599 ins_pipe(ialu_imm);
6600 %}
6601
6602 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6603 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6604 ins_cost(150);
6605
6606 size(4);
6607 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6608 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6609 ins_pipe(ialu_reg);
6610 %}
6611
6612
6613 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6614 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6615 ins_cost(150);
6616
6617 size(4);
6618 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6619 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6620 ins_pipe(ialu_reg);
6621 %}
6622
6623
6624 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6625 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6626 ins_cost(150);
6627
6628 size(4);
6629 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6630 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6631 ins_pipe(ialu_reg);
6632 %}
6633
6634
6635
6636 //----------OS and Locking Instructions----------------------------------------
6637
6638 // This name is KNOWN by the ADLC and cannot be changed.
6639 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6640 // for this guy.
6641 instruct tlsLoadP(g2RegP dst) %{
6642 match(Set dst (ThreadLocal));
6643
6644 size(0);
6645 ins_cost(0);
6646 format %{ "# TLS is in G2" %}
6647 ins_encode( /*empty encoding*/ );
6648 ins_pipe(ialu_none);
6649 %}
6650
6651 instruct checkCastPP( iRegP dst ) %{
6652 match(Set dst (CheckCastPP dst));
6653
6654 size(0);
6655 format %{ "# checkcastPP of $dst" %}
6656 ins_encode( /*empty encoding*/ );
6657 ins_pipe(empty);
6658 %}
6659
6660
6661 instruct castPP( iRegP dst ) %{
6662 match(Set dst (CastPP dst));
6663 format %{ "# castPP of $dst" %}
6664 ins_encode( /*empty encoding*/ );
6665 ins_pipe(empty);
6666 %}
6667
6668 instruct castII( iRegI dst ) %{
6669 match(Set dst (CastII dst));
6670 format %{ "# castII of $dst" %}
6671 ins_encode( /*empty encoding*/ );
6672 ins_cost(0);
6673 ins_pipe(empty);
6674 %}
6675
6676 //----------Arithmetic Instructions--------------------------------------------
6677 // Addition Instructions
6678 // Register Addition
6679 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6680 match(Set dst (AddI src1 src2));
6681
6682 size(4);
6683 format %{ "ADD $src1,$src2,$dst" %}
6684 ins_encode %{
6685 __ add($src1$$Register, $src2$$Register, $dst$$Register);
6686 %}
6687 ins_pipe(ialu_reg_reg);
6688 %}
6689
6690 // Immediate Addition
6691 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6692 match(Set dst (AddI src1 src2));
6693
6694 size(4);
6695 format %{ "ADD $src1,$src2,$dst" %}
6696 opcode(Assembler::add_op3, Assembler::arith_op);
6697 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6698 ins_pipe(ialu_reg_imm);
6699 %}
6700
6701 // Pointer Register Addition
6702 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
6703 match(Set dst (AddP src1 src2));
6704
6705 size(4);
6706 format %{ "ADD $src1,$src2,$dst" %}
6707 opcode(Assembler::add_op3, Assembler::arith_op);
6708 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6709 ins_pipe(ialu_reg_reg);
6710 %}
6711
6712 // Pointer Immediate Addition
6713 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
6714 match(Set dst (AddP src1 src2));
6715
6716 size(4);
6717 format %{ "ADD $src1,$src2,$dst" %}
6718 opcode(Assembler::add_op3, Assembler::arith_op);
6719 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6720 ins_pipe(ialu_reg_imm);
6721 %}
6722
6723 // Long Addition
6724 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6725 match(Set dst (AddL src1 src2));
6726
6727 size(4);
6728 format %{ "ADD $src1,$src2,$dst\t! long" %}
6729 opcode(Assembler::add_op3, Assembler::arith_op);
6730 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6731 ins_pipe(ialu_reg_reg);
6732 %}
6733
6734 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6735 match(Set dst (AddL src1 con));
6736
6737 size(4);
6738 format %{ "ADD $src1,$con,$dst" %}
6739 opcode(Assembler::add_op3, Assembler::arith_op);
6740 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6741 ins_pipe(ialu_reg_imm);
6742 %}
6743
6744 //----------Conditional_store--------------------------------------------------
6745 // Conditional-store of the updated heap-top.
6746 // Used during allocation of the shared heap.
6747 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
6748
6749 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
6750 instruct loadPLocked(iRegP dst, memory mem) %{
6751 match(Set dst (LoadPLocked mem));
6752 ins_cost(MEMORY_REF_COST);
6753
6754 format %{ "LDX $mem,$dst\t! ptr" %}
6755 opcode(Assembler::ldx_op3, 0, REGP_OP);
6756 ins_encode( form3_mem_reg( mem, dst ) );
6757 ins_pipe(iload_mem);
6758 %}
6759
6760 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
6761 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
6762 effect( KILL newval );
6763 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
6764 "CMP R_G3,$oldval\t\t! See if we made progress" %}
6765 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
6766 ins_pipe( long_memory_op );
6767 %}
6768
6769 // Conditional-store of an int value.
6770 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
6771 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
6772 effect( KILL newval );
6773 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6774 "CMP $oldval,$newval\t\t! See if we made progress" %}
6775 ins_encode( enc_cas(mem_ptr,oldval,newval) );
6776 ins_pipe( long_memory_op );
6777 %}
6778
6779 // Conditional-store of a long value.
6780 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
6781 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
6782 effect( KILL newval );
6783 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6784 "CMP $oldval,$newval\t\t! See if we made progress" %}
6785 ins_encode( enc_cas(mem_ptr,oldval,newval) );
6786 ins_pipe( long_memory_op );
6787 %}
6788
6789 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
6790
6791 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6792 predicate(VM_Version::supports_cx8());
6793 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
6794 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
6795 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6796 format %{
6797 "MOV $newval,O7\n\t"
6798 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6799 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6800 "MOV 1,$res\n\t"
6801 "MOVne xcc,R_G0,$res"
6802 %}
6803 ins_encode( enc_casx(mem_ptr, oldval, newval),
6804 enc_lflags_ne_to_boolean(res) );
6805 ins_pipe( long_memory_op );
6806 %}
6807
6808
6809 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6810 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
6811 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
6812 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6813 format %{
6814 "MOV $newval,O7\n\t"
6815 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6816 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6817 "MOV 1,$res\n\t"
6818 "MOVne icc,R_G0,$res"
6819 %}
6820 ins_encode( enc_casi(mem_ptr, oldval, newval),
6821 enc_iflags_ne_to_boolean(res) );
6822 ins_pipe( long_memory_op );
6823 %}
6824
6825 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6826 predicate(VM_Version::supports_cx8());
6827 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
6828 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
6829 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6830 format %{
6831 "MOV $newval,O7\n\t"
6832 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6833 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6834 "MOV 1,$res\n\t"
6835 "MOVne xcc,R_G0,$res"
6836 %}
6837 ins_encode( enc_casx(mem_ptr, oldval, newval),
6838 enc_lflags_ne_to_boolean(res) );
6839 ins_pipe( long_memory_op );
6840 %}
6841
6842 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6843 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
6844 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
6845 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6846 format %{
6847 "MOV $newval,O7\n\t"
6848 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6849 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6850 "MOV 1,$res\n\t"
6851 "MOVne icc,R_G0,$res"
6852 %}
6853 ins_encode( enc_casi(mem_ptr, oldval, newval),
6854 enc_iflags_ne_to_boolean(res) );
6855 ins_pipe( long_memory_op );
6856 %}
6857
6858 instruct compareAndExchangeI(iRegP mem_ptr, iRegI oldval, iRegI newval)
6859 %{
6860 match(Set newval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
6861 effect( USE mem_ptr );
6862
6863 format %{
6864 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t"
6865 %}
6866 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) );
6867 ins_pipe( long_memory_op );
6868 %}
6869
6870 instruct compareAndExchangeL(iRegP mem_ptr, iRegL oldval, iRegL newval)
6871 %{
6872 match(Set newval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
6873 effect( USE mem_ptr );
6874
6875 format %{
6876 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t"
6877 %}
6878 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) );
6879 ins_pipe( long_memory_op );
6880 %}
6881
6882 instruct compareAndExchangeP(iRegP mem_ptr, iRegP oldval, iRegP newval)
6883 %{
6884 match(Set newval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
6885 effect( USE mem_ptr );
6886
6887 format %{
6888 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t"
6889 %}
6890 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) );
6891 ins_pipe( long_memory_op );
6892 %}
6893
6894 instruct compareAndExchangeN(iRegP mem_ptr, iRegN oldval, iRegN newval)
6895 %{
6896 match(Set newval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
6897 effect( USE mem_ptr );
6898
6899 format %{
6900 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t"
6901 %}
6902 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) );
6903 ins_pipe( long_memory_op );
6904 %}
6905
6906 instruct xchgI( memory mem, iRegI newval) %{
6907 match(Set newval (GetAndSetI mem newval));
6908 format %{ "SWAP [$mem],$newval" %}
6909 size(4);
6910 ins_encode %{
6911 __ swap($mem$$Address, $newval$$Register);
6912 %}
6913 ins_pipe( long_memory_op );
6914 %}
6915
6916
6917 instruct xchgN( memory mem, iRegN newval) %{
6918 match(Set newval (GetAndSetN mem newval));
6919 format %{ "SWAP [$mem],$newval" %}
6920 size(4);
6921 ins_encode %{
6922 __ swap($mem$$Address, $newval$$Register);
6923 %}
6924 ins_pipe( long_memory_op );
6925 %}
6926
6927 //---------------------
6928 // Subtraction Instructions
6929 // Register Subtraction
6930 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6931 match(Set dst (SubI src1 src2));
6932
6933 size(4);
6934 format %{ "SUB $src1,$src2,$dst" %}
6935 opcode(Assembler::sub_op3, Assembler::arith_op);
6936 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6937 ins_pipe(ialu_reg_reg);
6938 %}
6939
6940 // Immediate Subtraction
6941 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6942 match(Set dst (SubI src1 src2));
6943
6944 size(4);
6945 format %{ "SUB $src1,$src2,$dst" %}
6946 opcode(Assembler::sub_op3, Assembler::arith_op);
6947 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6948 ins_pipe(ialu_reg_imm);
6949 %}
6950
6951 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
6952 match(Set dst (SubI zero src2));
6953
6954 size(4);
6955 format %{ "NEG $src2,$dst" %}
6956 opcode(Assembler::sub_op3, Assembler::arith_op);
6957 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
6958 ins_pipe(ialu_zero_reg);
6959 %}
6960
6961 // Long subtraction
6962 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6963 match(Set dst (SubL src1 src2));
6964
6965 size(4);
6966 format %{ "SUB $src1,$src2,$dst\t! long" %}
6967 opcode(Assembler::sub_op3, Assembler::arith_op);
6968 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6969 ins_pipe(ialu_reg_reg);
6970 %}
6971
6972 // Immediate Subtraction
6973 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6974 match(Set dst (SubL src1 con));
6975
6976 size(4);
6977 format %{ "SUB $src1,$con,$dst\t! long" %}
6978 opcode(Assembler::sub_op3, Assembler::arith_op);
6979 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6980 ins_pipe(ialu_reg_imm);
6981 %}
6982
6983 // Long negation
6984 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
6985 match(Set dst (SubL zero src2));
6986
6987 size(4);
6988 format %{ "NEG $src2,$dst\t! long" %}
6989 opcode(Assembler::sub_op3, Assembler::arith_op);
6990 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
6991 ins_pipe(ialu_zero_reg);
6992 %}
6993
6994 // Multiplication Instructions
6995 // Integer Multiplication
6996 // Register Multiplication
6997 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6998 match(Set dst (MulI src1 src2));
6999
7000 size(4);
7001 format %{ "MULX $src1,$src2,$dst" %}
7002 opcode(Assembler::mulx_op3, Assembler::arith_op);
7003 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7004 ins_pipe(imul_reg_reg);
7005 %}
7006
7007 // Immediate Multiplication
7008 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7009 match(Set dst (MulI src1 src2));
7010
7011 size(4);
7012 format %{ "MULX $src1,$src2,$dst" %}
7013 opcode(Assembler::mulx_op3, Assembler::arith_op);
7014 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7015 ins_pipe(imul_reg_imm);
7016 %}
7017
7018 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7019 match(Set dst (MulL src1 src2));
7020 ins_cost(DEFAULT_COST * 5);
7021 size(4);
7022 format %{ "MULX $src1,$src2,$dst\t! long" %}
7023 opcode(Assembler::mulx_op3, Assembler::arith_op);
7024 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7025 ins_pipe(mulL_reg_reg);
7026 %}
7027
7028 // Immediate Multiplication
7029 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7030 match(Set dst (MulL src1 src2));
7031 ins_cost(DEFAULT_COST * 5);
7032 size(4);
7033 format %{ "MULX $src1,$src2,$dst" %}
7034 opcode(Assembler::mulx_op3, Assembler::arith_op);
7035 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7036 ins_pipe(mulL_reg_imm);
7037 %}
7038
7039 // Integer Division
7040 // Register Division
7041 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7042 match(Set dst (DivI src1 src2));
7043 ins_cost((2+71)*DEFAULT_COST);
7044
7045 format %{ "SRA $src2,0,$src2\n\t"
7046 "SRA $src1,0,$src1\n\t"
7047 "SDIVX $src1,$src2,$dst" %}
7048 ins_encode( idiv_reg( src1, src2, dst ) );
7049 ins_pipe(sdiv_reg_reg);
7050 %}
7051
7052 // Immediate Division
7053 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7054 match(Set dst (DivI src1 src2));
7055 ins_cost((2+71)*DEFAULT_COST);
7056
7057 format %{ "SRA $src1,0,$src1\n\t"
7058 "SDIVX $src1,$src2,$dst" %}
7059 ins_encode( idiv_imm( src1, src2, dst ) );
7060 ins_pipe(sdiv_reg_imm);
7061 %}
7062
7063 //----------Div-By-10-Expansion------------------------------------------------
7064 // Extract hi bits of a 32x32->64 bit multiply.
7065 // Expand rule only, not matched
7066 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7067 effect( DEF dst, USE src1, USE src2 );
7068 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7069 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7070 ins_encode( enc_mul_hi(dst,src1,src2));
7071 ins_pipe(sdiv_reg_reg);
7072 %}
7073
7074 // Magic constant, reciprocal of 10
7075 instruct loadConI_x66666667(iRegIsafe dst) %{
7076 effect( DEF dst );
7077
7078 size(8);
7079 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7080 ins_encode( Set32(0x66666667, dst) );
7081 ins_pipe(ialu_hi_lo_reg);
7082 %}
7083
7084 // Register Shift Right Arithmetic Long by 32-63
7085 instruct sra_31( iRegI dst, iRegI src ) %{
7086 effect( DEF dst, USE src );
7087 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7088 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7089 ins_pipe(ialu_reg_reg);
7090 %}
7091
7092 // Arithmetic Shift Right by 8-bit immediate
7093 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7094 effect( DEF dst, USE src );
7095 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7096 opcode(Assembler::sra_op3, Assembler::arith_op);
7097 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7098 ins_pipe(ialu_reg_imm);
7099 %}
7100
7101 // Integer DIV with 10
7102 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7103 match(Set dst (DivI src div));
7104 ins_cost((6+6)*DEFAULT_COST);
7105 expand %{
7106 iRegIsafe tmp1; // Killed temps;
7107 iRegIsafe tmp2; // Killed temps;
7108 iRegI tmp3; // Killed temps;
7109 iRegI tmp4; // Killed temps;
7110 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7111 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7112 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7113 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7114 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7115 %}
7116 %}
7117
7118 // Register Long Division
7119 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7120 match(Set dst (DivL src1 src2));
7121 ins_cost(DEFAULT_COST*71);
7122 size(4);
7123 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7124 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7125 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7126 ins_pipe(divL_reg_reg);
7127 %}
7128
7129 // Register Long Division
7130 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7131 match(Set dst (DivL src1 src2));
7132 ins_cost(DEFAULT_COST*71);
7133 size(4);
7134 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7135 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7136 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7137 ins_pipe(divL_reg_imm);
7138 %}
7139
7140 // Integer Remainder
7141 // Register Remainder
7142 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7143 match(Set dst (ModI src1 src2));
7144 effect( KILL ccr, KILL temp);
7145
7146 format %{ "SREM $src1,$src2,$dst" %}
7147 ins_encode( irem_reg(src1, src2, dst, temp) );
7148 ins_pipe(sdiv_reg_reg);
7149 %}
7150
7151 // Immediate Remainder
7152 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7153 match(Set dst (ModI src1 src2));
7154 effect( KILL ccr, KILL temp);
7155
7156 format %{ "SREM $src1,$src2,$dst" %}
7157 ins_encode( irem_imm(src1, src2, dst, temp) );
7158 ins_pipe(sdiv_reg_imm);
7159 %}
7160
7161 // Register Long Remainder
7162 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7163 effect(DEF dst, USE src1, USE src2);
7164 size(4);
7165 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7166 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7167 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7168 ins_pipe(divL_reg_reg);
7169 %}
7170
7171 // Register Long Division
7172 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7173 effect(DEF dst, USE src1, USE src2);
7174 size(4);
7175 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7176 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7177 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7178 ins_pipe(divL_reg_imm);
7179 %}
7180
7181 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7182 effect(DEF dst, USE src1, USE src2);
7183 size(4);
7184 format %{ "MULX $src1,$src2,$dst\t! long" %}
7185 opcode(Assembler::mulx_op3, Assembler::arith_op);
7186 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7187 ins_pipe(mulL_reg_reg);
7188 %}
7189
7190 // Immediate Multiplication
7191 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7192 effect(DEF dst, USE src1, USE src2);
7193 size(4);
7194 format %{ "MULX $src1,$src2,$dst" %}
7195 opcode(Assembler::mulx_op3, Assembler::arith_op);
7196 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7197 ins_pipe(mulL_reg_imm);
7198 %}
7199
7200 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7201 effect(DEF dst, USE src1, USE src2);
7202 size(4);
7203 format %{ "SUB $src1,$src2,$dst\t! long" %}
7204 opcode(Assembler::sub_op3, Assembler::arith_op);
7205 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7206 ins_pipe(ialu_reg_reg);
7207 %}
7208
7209 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7210 effect(DEF dst, USE src1, USE src2);
7211 size(4);
7212 format %{ "SUB $src1,$src2,$dst\t! long" %}
7213 opcode(Assembler::sub_op3, Assembler::arith_op);
7214 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7215 ins_pipe(ialu_reg_reg);
7216 %}
7217
7218 // Register Long Remainder
7219 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7220 match(Set dst (ModL src1 src2));
7221 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7222 expand %{
7223 iRegL tmp1;
7224 iRegL tmp2;
7225 divL_reg_reg_1(tmp1, src1, src2);
7226 mulL_reg_reg_1(tmp2, tmp1, src2);
7227 subL_reg_reg_1(dst, src1, tmp2);
7228 %}
7229 %}
7230
7231 // Register Long Remainder
7232 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7233 match(Set dst (ModL src1 src2));
7234 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7235 expand %{
7236 iRegL tmp1;
7237 iRegL tmp2;
7238 divL_reg_imm13_1(tmp1, src1, src2);
7239 mulL_reg_imm13_1(tmp2, tmp1, src2);
7240 subL_reg_reg_2 (dst, src1, tmp2);
7241 %}
7242 %}
7243
7244 // Integer Shift Instructions
7245 // Register Shift Left
7246 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7247 match(Set dst (LShiftI src1 src2));
7248
7249 size(4);
7250 format %{ "SLL $src1,$src2,$dst" %}
7251 opcode(Assembler::sll_op3, Assembler::arith_op);
7252 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7253 ins_pipe(ialu_reg_reg);
7254 %}
7255
7256 // Register Shift Left Immediate
7257 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7258 match(Set dst (LShiftI src1 src2));
7259
7260 size(4);
7261 format %{ "SLL $src1,$src2,$dst" %}
7262 opcode(Assembler::sll_op3, Assembler::arith_op);
7263 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7264 ins_pipe(ialu_reg_imm);
7265 %}
7266
7267 // Register Shift Left
7268 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7269 match(Set dst (LShiftL src1 src2));
7270
7271 size(4);
7272 format %{ "SLLX $src1,$src2,$dst" %}
7273 opcode(Assembler::sllx_op3, Assembler::arith_op);
7274 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7275 ins_pipe(ialu_reg_reg);
7276 %}
7277
7278 // Register Shift Left Immediate
7279 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7280 match(Set dst (LShiftL src1 src2));
7281
7282 size(4);
7283 format %{ "SLLX $src1,$src2,$dst" %}
7284 opcode(Assembler::sllx_op3, Assembler::arith_op);
7285 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7286 ins_pipe(ialu_reg_imm);
7287 %}
7288
7289 // Register Arithmetic Shift Right
7290 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7291 match(Set dst (RShiftI src1 src2));
7292 size(4);
7293 format %{ "SRA $src1,$src2,$dst" %}
7294 opcode(Assembler::sra_op3, Assembler::arith_op);
7295 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7296 ins_pipe(ialu_reg_reg);
7297 %}
7298
7299 // Register Arithmetic Shift Right Immediate
7300 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7301 match(Set dst (RShiftI src1 src2));
7302
7303 size(4);
7304 format %{ "SRA $src1,$src2,$dst" %}
7305 opcode(Assembler::sra_op3, Assembler::arith_op);
7306 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7307 ins_pipe(ialu_reg_imm);
7308 %}
7309
7310 // Register Shift Right Arithmatic Long
7311 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7312 match(Set dst (RShiftL src1 src2));
7313
7314 size(4);
7315 format %{ "SRAX $src1,$src2,$dst" %}
7316 opcode(Assembler::srax_op3, Assembler::arith_op);
7317 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7318 ins_pipe(ialu_reg_reg);
7319 %}
7320
7321 // Register Shift Left Immediate
7322 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7323 match(Set dst (RShiftL src1 src2));
7324
7325 size(4);
7326 format %{ "SRAX $src1,$src2,$dst" %}
7327 opcode(Assembler::srax_op3, Assembler::arith_op);
7328 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7329 ins_pipe(ialu_reg_imm);
7330 %}
7331
7332 // Register Shift Right
7333 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7334 match(Set dst (URShiftI src1 src2));
7335
7336 size(4);
7337 format %{ "SRL $src1,$src2,$dst" %}
7338 opcode(Assembler::srl_op3, Assembler::arith_op);
7339 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7340 ins_pipe(ialu_reg_reg);
7341 %}
7342
7343 // Register Shift Right Immediate
7344 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7345 match(Set dst (URShiftI src1 src2));
7346
7347 size(4);
7348 format %{ "SRL $src1,$src2,$dst" %}
7349 opcode(Assembler::srl_op3, Assembler::arith_op);
7350 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7351 ins_pipe(ialu_reg_imm);
7352 %}
7353
7354 // Register Shift Right
7355 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7356 match(Set dst (URShiftL src1 src2));
7357
7358 size(4);
7359 format %{ "SRLX $src1,$src2,$dst" %}
7360 opcode(Assembler::srlx_op3, Assembler::arith_op);
7361 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7362 ins_pipe(ialu_reg_reg);
7363 %}
7364
7365 // Register Shift Right Immediate
7366 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7367 match(Set dst (URShiftL src1 src2));
7368
7369 size(4);
7370 format %{ "SRLX $src1,$src2,$dst" %}
7371 opcode(Assembler::srlx_op3, Assembler::arith_op);
7372 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7373 ins_pipe(ialu_reg_imm);
7374 %}
7375
7376 // Register Shift Right Immediate with a CastP2X
7377 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7378 match(Set dst (URShiftL (CastP2X src1) src2));
7379 size(4);
7380 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7381 opcode(Assembler::srlx_op3, Assembler::arith_op);
7382 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7383 ins_pipe(ialu_reg_imm);
7384 %}
7385
7386
7387 //----------Floating Point Arithmetic Instructions-----------------------------
7388
7389 // Add float single precision
7390 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7391 match(Set dst (AddF src1 src2));
7392
7393 size(4);
7394 format %{ "FADDS $src1,$src2,$dst" %}
7395 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7396 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7397 ins_pipe(faddF_reg_reg);
7398 %}
7399
7400 // Add float double precision
7401 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7402 match(Set dst (AddD src1 src2));
7403
7404 size(4);
7405 format %{ "FADDD $src1,$src2,$dst" %}
7406 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7407 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7408 ins_pipe(faddD_reg_reg);
7409 %}
7410
7411 // Sub float single precision
7412 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7413 match(Set dst (SubF src1 src2));
7414
7415 size(4);
7416 format %{ "FSUBS $src1,$src2,$dst" %}
7417 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7418 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7419 ins_pipe(faddF_reg_reg);
7420 %}
7421
7422 // Sub float double precision
7423 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7424 match(Set dst (SubD src1 src2));
7425
7426 size(4);
7427 format %{ "FSUBD $src1,$src2,$dst" %}
7428 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7429 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7430 ins_pipe(faddD_reg_reg);
7431 %}
7432
7433 // Mul float single precision
7434 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7435 match(Set dst (MulF src1 src2));
7436
7437 size(4);
7438 format %{ "FMULS $src1,$src2,$dst" %}
7439 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7440 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7441 ins_pipe(fmulF_reg_reg);
7442 %}
7443
7444 // Mul float double precision
7445 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7446 match(Set dst (MulD src1 src2));
7447
7448 size(4);
7449 format %{ "FMULD $src1,$src2,$dst" %}
7450 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7451 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7452 ins_pipe(fmulD_reg_reg);
7453 %}
7454
7455 // Div float single precision
7456 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7457 match(Set dst (DivF src1 src2));
7458
7459 size(4);
7460 format %{ "FDIVS $src1,$src2,$dst" %}
7461 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7462 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7463 ins_pipe(fdivF_reg_reg);
7464 %}
7465
7466 // Div float double precision
7467 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7468 match(Set dst (DivD src1 src2));
7469
7470 size(4);
7471 format %{ "FDIVD $src1,$src2,$dst" %}
7472 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7473 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7474 ins_pipe(fdivD_reg_reg);
7475 %}
7476
7477 // Absolute float double precision
7478 instruct absD_reg(regD dst, regD src) %{
7479 match(Set dst (AbsD src));
7480
7481 format %{ "FABSd $src,$dst" %}
7482 ins_encode(fabsd(dst, src));
7483 ins_pipe(faddD_reg);
7484 %}
7485
7486 // Absolute float single precision
7487 instruct absF_reg(regF dst, regF src) %{
7488 match(Set dst (AbsF src));
7489
7490 format %{ "FABSs $src,$dst" %}
7491 ins_encode(fabss(dst, src));
7492 ins_pipe(faddF_reg);
7493 %}
7494
7495 instruct negF_reg(regF dst, regF src) %{
7496 match(Set dst (NegF src));
7497
7498 size(4);
7499 format %{ "FNEGs $src,$dst" %}
7500 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7501 ins_encode(form3_opf_rs2F_rdF(src, dst));
7502 ins_pipe(faddF_reg);
7503 %}
7504
7505 instruct negD_reg(regD dst, regD src) %{
7506 match(Set dst (NegD src));
7507
7508 format %{ "FNEGd $src,$dst" %}
7509 ins_encode(fnegd(dst, src));
7510 ins_pipe(faddD_reg);
7511 %}
7512
7513 // Sqrt float double precision
7514 instruct sqrtF_reg_reg(regF dst, regF src) %{
7515 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7516
7517 size(4);
7518 format %{ "FSQRTS $src,$dst" %}
7519 ins_encode(fsqrts(dst, src));
7520 ins_pipe(fdivF_reg_reg);
7521 %}
7522
7523 // Sqrt float double precision
7524 instruct sqrtD_reg_reg(regD dst, regD src) %{
7525 match(Set dst (SqrtD src));
7526
7527 size(4);
7528 format %{ "FSQRTD $src,$dst" %}
7529 ins_encode(fsqrtd(dst, src));
7530 ins_pipe(fdivD_reg_reg);
7531 %}
7532
7533 //----------Logical Instructions-----------------------------------------------
7534 // And Instructions
7535 // Register And
7536 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7537 match(Set dst (AndI src1 src2));
7538
7539 size(4);
7540 format %{ "AND $src1,$src2,$dst" %}
7541 opcode(Assembler::and_op3, Assembler::arith_op);
7542 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7543 ins_pipe(ialu_reg_reg);
7544 %}
7545
7546 // Immediate And
7547 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7548 match(Set dst (AndI src1 src2));
7549
7550 size(4);
7551 format %{ "AND $src1,$src2,$dst" %}
7552 opcode(Assembler::and_op3, Assembler::arith_op);
7553 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7554 ins_pipe(ialu_reg_imm);
7555 %}
7556
7557 // Register And Long
7558 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7559 match(Set dst (AndL src1 src2));
7560
7561 ins_cost(DEFAULT_COST);
7562 size(4);
7563 format %{ "AND $src1,$src2,$dst\t! long" %}
7564 opcode(Assembler::and_op3, Assembler::arith_op);
7565 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7566 ins_pipe(ialu_reg_reg);
7567 %}
7568
7569 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7570 match(Set dst (AndL src1 con));
7571
7572 ins_cost(DEFAULT_COST);
7573 size(4);
7574 format %{ "AND $src1,$con,$dst\t! long" %}
7575 opcode(Assembler::and_op3, Assembler::arith_op);
7576 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7577 ins_pipe(ialu_reg_imm);
7578 %}
7579
7580 // Or Instructions
7581 // Register Or
7582 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7583 match(Set dst (OrI src1 src2));
7584
7585 size(4);
7586 format %{ "OR $src1,$src2,$dst" %}
7587 opcode(Assembler::or_op3, Assembler::arith_op);
7588 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7589 ins_pipe(ialu_reg_reg);
7590 %}
7591
7592 // Immediate Or
7593 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7594 match(Set dst (OrI src1 src2));
7595
7596 size(4);
7597 format %{ "OR $src1,$src2,$dst" %}
7598 opcode(Assembler::or_op3, Assembler::arith_op);
7599 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7600 ins_pipe(ialu_reg_imm);
7601 %}
7602
7603 // Register Or Long
7604 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7605 match(Set dst (OrL src1 src2));
7606
7607 ins_cost(DEFAULT_COST);
7608 size(4);
7609 format %{ "OR $src1,$src2,$dst\t! long" %}
7610 opcode(Assembler::or_op3, Assembler::arith_op);
7611 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7612 ins_pipe(ialu_reg_reg);
7613 %}
7614
7615 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7616 match(Set dst (OrL src1 con));
7617 ins_cost(DEFAULT_COST*2);
7618
7619 ins_cost(DEFAULT_COST);
7620 size(4);
7621 format %{ "OR $src1,$con,$dst\t! long" %}
7622 opcode(Assembler::or_op3, Assembler::arith_op);
7623 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7624 ins_pipe(ialu_reg_imm);
7625 %}
7626
7627 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7628 match(Set dst (OrL src1 (CastP2X src2)));
7629
7630 ins_cost(DEFAULT_COST);
7631 size(4);
7632 format %{ "OR $src1,$src2,$dst\t! long" %}
7633 opcode(Assembler::or_op3, Assembler::arith_op);
7634 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7635 ins_pipe(ialu_reg_reg);
7636 %}
7637
7638 // Xor Instructions
7639 // Register Xor
7640 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7641 match(Set dst (XorI src1 src2));
7642
7643 size(4);
7644 format %{ "XOR $src1,$src2,$dst" %}
7645 opcode(Assembler::xor_op3, Assembler::arith_op);
7646 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7647 ins_pipe(ialu_reg_reg);
7648 %}
7649
7650 // Immediate Xor
7651 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7652 match(Set dst (XorI src1 src2));
7653
7654 size(4);
7655 format %{ "XOR $src1,$src2,$dst" %}
7656 opcode(Assembler::xor_op3, Assembler::arith_op);
7657 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7658 ins_pipe(ialu_reg_imm);
7659 %}
7660
7661 // Register Xor Long
7662 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7663 match(Set dst (XorL src1 src2));
7664
7665 ins_cost(DEFAULT_COST);
7666 size(4);
7667 format %{ "XOR $src1,$src2,$dst\t! long" %}
7668 opcode(Assembler::xor_op3, Assembler::arith_op);
7669 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7670 ins_pipe(ialu_reg_reg);
7671 %}
7672
7673 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7674 match(Set dst (XorL src1 con));
7675
7676 ins_cost(DEFAULT_COST);
7677 size(4);
7678 format %{ "XOR $src1,$con,$dst\t! long" %}
7679 opcode(Assembler::xor_op3, Assembler::arith_op);
7680 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7681 ins_pipe(ialu_reg_imm);
7682 %}
7683
7684 //----------Convert to Boolean-------------------------------------------------
7685 // Nice hack for 32-bit tests but doesn't work for
7686 // 64-bit pointers.
7687 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7688 match(Set dst (Conv2B src));
7689 effect( KILL ccr );
7690 ins_cost(DEFAULT_COST*2);
7691 format %{ "CMP R_G0,$src\n\t"
7692 "ADDX R_G0,0,$dst" %}
7693 ins_encode( enc_to_bool( src, dst ) );
7694 ins_pipe(ialu_reg_ialu);
7695 %}
7696
7697 instruct convP2B( iRegI dst, iRegP src ) %{
7698 match(Set dst (Conv2B src));
7699 ins_cost(DEFAULT_COST*2);
7700 format %{ "MOV $src,$dst\n\t"
7701 "MOVRNZ $src,1,$dst" %}
7702 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
7703 ins_pipe(ialu_clr_and_mover);
7704 %}
7705
7706 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
7707 match(Set dst (CmpLTMask src zero));
7708 effect(KILL ccr);
7709 size(4);
7710 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
7711 ins_encode %{
7712 __ sra($src$$Register, 31, $dst$$Register);
7713 %}
7714 ins_pipe(ialu_reg_imm);
7715 %}
7716
7717 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
7718 match(Set dst (CmpLTMask p q));
7719 effect( KILL ccr );
7720 ins_cost(DEFAULT_COST*4);
7721 format %{ "CMP $p,$q\n\t"
7722 "MOV #0,$dst\n\t"
7723 "BLT,a .+8\n\t"
7724 "MOV #-1,$dst" %}
7725 ins_encode( enc_ltmask(p,q,dst) );
7726 ins_pipe(ialu_reg_reg_ialu);
7727 %}
7728
7729 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7730 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
7731 effect(KILL ccr, TEMP tmp);
7732 ins_cost(DEFAULT_COST*3);
7733
7734 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7735 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7736 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7737 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
7738 ins_pipe(cadd_cmpltmask);
7739 %}
7740
7741 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
7742 match(Set p (AndI (CmpLTMask p q) y));
7743 effect(KILL ccr);
7744 ins_cost(DEFAULT_COST*3);
7745
7746 format %{ "CMP $p,$q\n\t"
7747 "MOV $y,$p\n\t"
7748 "MOVge G0,$p" %}
7749 ins_encode %{
7750 __ cmp($p$$Register, $q$$Register);
7751 __ mov($y$$Register, $p$$Register);
7752 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
7753 %}
7754 ins_pipe(ialu_reg_reg_ialu);
7755 %}
7756
7757 //-----------------------------------------------------------------
7758 // Direct raw moves between float and general registers using VIS3.
7759
7760 // ins_pipe(faddF_reg);
7761 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
7762 predicate(UseVIS >= 3);
7763 match(Set dst (MoveF2I src));
7764
7765 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
7766 ins_encode %{
7767 __ movstouw($src$$FloatRegister, $dst$$Register);
7768 %}
7769 ins_pipe(ialu_reg_reg);
7770 %}
7771
7772 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
7773 predicate(UseVIS >= 3);
7774 match(Set dst (MoveI2F src));
7775
7776 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
7777 ins_encode %{
7778 __ movwtos($src$$Register, $dst$$FloatRegister);
7779 %}
7780 ins_pipe(ialu_reg_reg);
7781 %}
7782
7783 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
7784 predicate(UseVIS >= 3);
7785 match(Set dst (MoveD2L src));
7786
7787 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
7788 ins_encode %{
7789 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
7790 %}
7791 ins_pipe(ialu_reg_reg);
7792 %}
7793
7794 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
7795 predicate(UseVIS >= 3);
7796 match(Set dst (MoveL2D src));
7797
7798 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
7799 ins_encode %{
7800 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
7801 %}
7802 ins_pipe(ialu_reg_reg);
7803 %}
7804
7805
7806 // Raw moves between float and general registers using stack.
7807
7808 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
7809 match(Set dst (MoveF2I src));
7810 effect(DEF dst, USE src);
7811 ins_cost(MEMORY_REF_COST);
7812
7813 format %{ "LDUW $src,$dst\t! MoveF2I" %}
7814 opcode(Assembler::lduw_op3);
7815 ins_encode(simple_form3_mem_reg( src, dst ) );
7816 ins_pipe(iload_mem);
7817 %}
7818
7819 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
7820 match(Set dst (MoveI2F src));
7821 effect(DEF dst, USE src);
7822 ins_cost(MEMORY_REF_COST);
7823
7824 format %{ "LDF $src,$dst\t! MoveI2F" %}
7825 opcode(Assembler::ldf_op3);
7826 ins_encode(simple_form3_mem_reg(src, dst));
7827 ins_pipe(floadF_stk);
7828 %}
7829
7830 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
7831 match(Set dst (MoveD2L src));
7832 effect(DEF dst, USE src);
7833 ins_cost(MEMORY_REF_COST);
7834
7835 format %{ "LDX $src,$dst\t! MoveD2L" %}
7836 opcode(Assembler::ldx_op3);
7837 ins_encode(simple_form3_mem_reg( src, dst ) );
7838 ins_pipe(iload_mem);
7839 %}
7840
7841 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
7842 match(Set dst (MoveL2D src));
7843 effect(DEF dst, USE src);
7844 ins_cost(MEMORY_REF_COST);
7845
7846 format %{ "LDDF $src,$dst\t! MoveL2D" %}
7847 opcode(Assembler::lddf_op3);
7848 ins_encode(simple_form3_mem_reg(src, dst));
7849 ins_pipe(floadD_stk);
7850 %}
7851
7852 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
7853 match(Set dst (MoveF2I src));
7854 effect(DEF dst, USE src);
7855 ins_cost(MEMORY_REF_COST);
7856
7857 format %{ "STF $src,$dst\t! MoveF2I" %}
7858 opcode(Assembler::stf_op3);
7859 ins_encode(simple_form3_mem_reg(dst, src));
7860 ins_pipe(fstoreF_stk_reg);
7861 %}
7862
7863 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
7864 match(Set dst (MoveI2F src));
7865 effect(DEF dst, USE src);
7866 ins_cost(MEMORY_REF_COST);
7867
7868 format %{ "STW $src,$dst\t! MoveI2F" %}
7869 opcode(Assembler::stw_op3);
7870 ins_encode(simple_form3_mem_reg( dst, src ) );
7871 ins_pipe(istore_mem_reg);
7872 %}
7873
7874 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
7875 match(Set dst (MoveD2L src));
7876 effect(DEF dst, USE src);
7877 ins_cost(MEMORY_REF_COST);
7878
7879 format %{ "STDF $src,$dst\t! MoveD2L" %}
7880 opcode(Assembler::stdf_op3);
7881 ins_encode(simple_form3_mem_reg(dst, src));
7882 ins_pipe(fstoreD_stk_reg);
7883 %}
7884
7885 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
7886 match(Set dst (MoveL2D src));
7887 effect(DEF dst, USE src);
7888 ins_cost(MEMORY_REF_COST);
7889
7890 format %{ "STX $src,$dst\t! MoveL2D" %}
7891 opcode(Assembler::stx_op3);
7892 ins_encode(simple_form3_mem_reg( dst, src ) );
7893 ins_pipe(istore_mem_reg);
7894 %}
7895
7896
7897 //----------Arithmetic Conversion Instructions---------------------------------
7898 // The conversions operations are all Alpha sorted. Please keep it that way!
7899
7900 instruct convD2F_reg(regF dst, regD src) %{
7901 match(Set dst (ConvD2F src));
7902 size(4);
7903 format %{ "FDTOS $src,$dst" %}
7904 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
7905 ins_encode(form3_opf_rs2D_rdF(src, dst));
7906 ins_pipe(fcvtD2F);
7907 %}
7908
7909
7910 // Convert a double to an int in a float register.
7911 // If the double is a NAN, stuff a zero in instead.
7912 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
7913 effect(DEF dst, USE src, KILL fcc0);
7914 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7915 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7916 "FDTOI $src,$dst\t! convert in delay slot\n\t"
7917 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7918 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
7919 "skip:" %}
7920 ins_encode(form_d2i_helper(src,dst));
7921 ins_pipe(fcvtD2I);
7922 %}
7923
7924 instruct convD2I_stk(stackSlotI dst, regD src) %{
7925 match(Set dst (ConvD2I src));
7926 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7927 expand %{
7928 regF tmp;
7929 convD2I_helper(tmp, src);
7930 regF_to_stkI(dst, tmp);
7931 %}
7932 %}
7933
7934 instruct convD2I_reg(iRegI dst, regD src) %{
7935 predicate(UseVIS >= 3);
7936 match(Set dst (ConvD2I src));
7937 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
7938 expand %{
7939 regF tmp;
7940 convD2I_helper(tmp, src);
7941 MoveF2I_reg_reg(dst, tmp);
7942 %}
7943 %}
7944
7945
7946 // Convert a double to a long in a double register.
7947 // If the double is a NAN, stuff a zero in instead.
7948 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
7949 effect(DEF dst, USE src, KILL fcc0);
7950 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7951 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7952 "FDTOX $src,$dst\t! convert in delay slot\n\t"
7953 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
7954 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
7955 "skip:" %}
7956 ins_encode(form_d2l_helper(src,dst));
7957 ins_pipe(fcvtD2L);
7958 %}
7959
7960 instruct convD2L_stk(stackSlotL dst, regD src) %{
7961 match(Set dst (ConvD2L src));
7962 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7963 expand %{
7964 regD tmp;
7965 convD2L_helper(tmp, src);
7966 regD_to_stkL(dst, tmp);
7967 %}
7968 %}
7969
7970 instruct convD2L_reg(iRegL dst, regD src) %{
7971 predicate(UseVIS >= 3);
7972 match(Set dst (ConvD2L src));
7973 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
7974 expand %{
7975 regD tmp;
7976 convD2L_helper(tmp, src);
7977 MoveD2L_reg_reg(dst, tmp);
7978 %}
7979 %}
7980
7981
7982 instruct convF2D_reg(regD dst, regF src) %{
7983 match(Set dst (ConvF2D src));
7984 format %{ "FSTOD $src,$dst" %}
7985 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
7986 ins_encode(form3_opf_rs2F_rdD(src, dst));
7987 ins_pipe(fcvtF2D);
7988 %}
7989
7990
7991 // Convert a float to an int in a float register.
7992 // If the float is a NAN, stuff a zero in instead.
7993 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
7994 effect(DEF dst, USE src, KILL fcc0);
7995 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
7996 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7997 "FSTOI $src,$dst\t! convert in delay slot\n\t"
7998 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7999 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8000 "skip:" %}
8001 ins_encode(form_f2i_helper(src,dst));
8002 ins_pipe(fcvtF2I);
8003 %}
8004
8005 instruct convF2I_stk(stackSlotI dst, regF src) %{
8006 match(Set dst (ConvF2I src));
8007 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8008 expand %{
8009 regF tmp;
8010 convF2I_helper(tmp, src);
8011 regF_to_stkI(dst, tmp);
8012 %}
8013 %}
8014
8015 instruct convF2I_reg(iRegI dst, regF src) %{
8016 predicate(UseVIS >= 3);
8017 match(Set dst (ConvF2I src));
8018 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8019 expand %{
8020 regF tmp;
8021 convF2I_helper(tmp, src);
8022 MoveF2I_reg_reg(dst, tmp);
8023 %}
8024 %}
8025
8026
8027 // Convert a float to a long in a float register.
8028 // If the float is a NAN, stuff a zero in instead.
8029 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8030 effect(DEF dst, USE src, KILL fcc0);
8031 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8032 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8033 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8034 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8035 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8036 "skip:" %}
8037 ins_encode(form_f2l_helper(src,dst));
8038 ins_pipe(fcvtF2L);
8039 %}
8040
8041 instruct convF2L_stk(stackSlotL dst, regF src) %{
8042 match(Set dst (ConvF2L src));
8043 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8044 expand %{
8045 regD tmp;
8046 convF2L_helper(tmp, src);
8047 regD_to_stkL(dst, tmp);
8048 %}
8049 %}
8050
8051 instruct convF2L_reg(iRegL dst, regF src) %{
8052 predicate(UseVIS >= 3);
8053 match(Set dst (ConvF2L src));
8054 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8055 expand %{
8056 regD tmp;
8057 convF2L_helper(tmp, src);
8058 MoveD2L_reg_reg(dst, tmp);
8059 %}
8060 %}
8061
8062
8063 instruct convI2D_helper(regD dst, regF tmp) %{
8064 effect(USE tmp, DEF dst);
8065 format %{ "FITOD $tmp,$dst" %}
8066 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8067 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8068 ins_pipe(fcvtI2D);
8069 %}
8070
8071 instruct convI2D_stk(stackSlotI src, regD dst) %{
8072 match(Set dst (ConvI2D src));
8073 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8074 expand %{
8075 regF tmp;
8076 stkI_to_regF(tmp, src);
8077 convI2D_helper(dst, tmp);
8078 %}
8079 %}
8080
8081 instruct convI2D_reg(regD_low dst, iRegI src) %{
8082 predicate(UseVIS >= 3);
8083 match(Set dst (ConvI2D src));
8084 expand %{
8085 regF tmp;
8086 MoveI2F_reg_reg(tmp, src);
8087 convI2D_helper(dst, tmp);
8088 %}
8089 %}
8090
8091 instruct convI2D_mem(regD_low dst, memory mem) %{
8092 match(Set dst (ConvI2D (LoadI mem)));
8093 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8094 format %{ "LDF $mem,$dst\n\t"
8095 "FITOD $dst,$dst" %}
8096 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8097 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8098 ins_pipe(floadF_mem);
8099 %}
8100
8101
8102 instruct convI2F_helper(regF dst, regF tmp) %{
8103 effect(DEF dst, USE tmp);
8104 format %{ "FITOS $tmp,$dst" %}
8105 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8106 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8107 ins_pipe(fcvtI2F);
8108 %}
8109
8110 instruct convI2F_stk(regF dst, stackSlotI src) %{
8111 match(Set dst (ConvI2F src));
8112 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8113 expand %{
8114 regF tmp;
8115 stkI_to_regF(tmp,src);
8116 convI2F_helper(dst, tmp);
8117 %}
8118 %}
8119
8120 instruct convI2F_reg(regF dst, iRegI src) %{
8121 predicate(UseVIS >= 3);
8122 match(Set dst (ConvI2F src));
8123 ins_cost(DEFAULT_COST);
8124 expand %{
8125 regF tmp;
8126 MoveI2F_reg_reg(tmp, src);
8127 convI2F_helper(dst, tmp);
8128 %}
8129 %}
8130
8131 instruct convI2F_mem( regF dst, memory mem ) %{
8132 match(Set dst (ConvI2F (LoadI mem)));
8133 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8134 format %{ "LDF $mem,$dst\n\t"
8135 "FITOS $dst,$dst" %}
8136 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8137 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8138 ins_pipe(floadF_mem);
8139 %}
8140
8141
8142 instruct convI2L_reg(iRegL dst, iRegI src) %{
8143 match(Set dst (ConvI2L src));
8144 size(4);
8145 format %{ "SRA $src,0,$dst\t! int->long" %}
8146 opcode(Assembler::sra_op3, Assembler::arith_op);
8147 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8148 ins_pipe(ialu_reg_reg);
8149 %}
8150
8151 // Zero-extend convert int to long
8152 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8153 match(Set dst (AndL (ConvI2L src) mask) );
8154 size(4);
8155 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8156 opcode(Assembler::srl_op3, Assembler::arith_op);
8157 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8158 ins_pipe(ialu_reg_reg);
8159 %}
8160
8161 // Zero-extend long
8162 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8163 match(Set dst (AndL src mask) );
8164 size(4);
8165 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8166 opcode(Assembler::srl_op3, Assembler::arith_op);
8167 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8168 ins_pipe(ialu_reg_reg);
8169 %}
8170
8171
8172 //-----------
8173 // Long to Double conversion using V8 opcodes.
8174 // Still useful because cheetah traps and becomes
8175 // amazingly slow for some common numbers.
8176
8177 // Magic constant, 0x43300000
8178 instruct loadConI_x43300000(iRegI dst) %{
8179 effect(DEF dst);
8180 size(4);
8181 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8182 ins_encode(SetHi22(0x43300000, dst));
8183 ins_pipe(ialu_none);
8184 %}
8185
8186 // Magic constant, 0x41f00000
8187 instruct loadConI_x41f00000(iRegI dst) %{
8188 effect(DEF dst);
8189 size(4);
8190 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8191 ins_encode(SetHi22(0x41f00000, dst));
8192 ins_pipe(ialu_none);
8193 %}
8194
8195 // Construct a double from two float halves
8196 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8197 effect(DEF dst, USE src1, USE src2);
8198 size(8);
8199 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8200 "FMOVS $src2.lo,$dst.lo" %}
8201 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8202 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8203 ins_pipe(faddD_reg_reg);
8204 %}
8205
8206 // Convert integer in high half of a double register (in the lower half of
8207 // the double register file) to double
8208 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8209 effect(DEF dst, USE src);
8210 size(4);
8211 format %{ "FITOD $src,$dst" %}
8212 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8213 ins_encode(form3_opf_rs2D_rdD(src, dst));
8214 ins_pipe(fcvtLHi2D);
8215 %}
8216
8217 // Add float double precision
8218 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8219 effect(DEF dst, USE src1, USE src2);
8220 size(4);
8221 format %{ "FADDD $src1,$src2,$dst" %}
8222 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8223 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8224 ins_pipe(faddD_reg_reg);
8225 %}
8226
8227 // Sub float double precision
8228 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8229 effect(DEF dst, USE src1, USE src2);
8230 size(4);
8231 format %{ "FSUBD $src1,$src2,$dst" %}
8232 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8233 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8234 ins_pipe(faddD_reg_reg);
8235 %}
8236
8237 // Mul float double precision
8238 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8239 effect(DEF dst, USE src1, USE src2);
8240 size(4);
8241 format %{ "FMULD $src1,$src2,$dst" %}
8242 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8243 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8244 ins_pipe(fmulD_reg_reg);
8245 %}
8246
8247 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8248 match(Set dst (ConvL2D src));
8249 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8250
8251 expand %{
8252 regD_low tmpsrc;
8253 iRegI ix43300000;
8254 iRegI ix41f00000;
8255 stackSlotL lx43300000;
8256 stackSlotL lx41f00000;
8257 regD_low dx43300000;
8258 regD dx41f00000;
8259 regD tmp1;
8260 regD_low tmp2;
8261 regD tmp3;
8262 regD tmp4;
8263
8264 stkL_to_regD(tmpsrc, src);
8265
8266 loadConI_x43300000(ix43300000);
8267 loadConI_x41f00000(ix41f00000);
8268 regI_to_stkLHi(lx43300000, ix43300000);
8269 regI_to_stkLHi(lx41f00000, ix41f00000);
8270 stkL_to_regD(dx43300000, lx43300000);
8271 stkL_to_regD(dx41f00000, lx41f00000);
8272
8273 convI2D_regDHi_regD(tmp1, tmpsrc);
8274 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8275 subD_regD_regD(tmp3, tmp2, dx43300000);
8276 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8277 addD_regD_regD(dst, tmp3, tmp4);
8278 %}
8279 %}
8280
8281 // Long to Double conversion using fast fxtof
8282 instruct convL2D_helper(regD dst, regD tmp) %{
8283 effect(DEF dst, USE tmp);
8284 size(4);
8285 format %{ "FXTOD $tmp,$dst" %}
8286 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8287 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8288 ins_pipe(fcvtL2D);
8289 %}
8290
8291 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8292 predicate(VM_Version::has_fast_fxtof());
8293 match(Set dst (ConvL2D src));
8294 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8295 expand %{
8296 regD tmp;
8297 stkL_to_regD(tmp, src);
8298 convL2D_helper(dst, tmp);
8299 %}
8300 %}
8301
8302 instruct convL2D_reg(regD dst, iRegL src) %{
8303 predicate(UseVIS >= 3);
8304 match(Set dst (ConvL2D src));
8305 expand %{
8306 regD tmp;
8307 MoveL2D_reg_reg(tmp, src);
8308 convL2D_helper(dst, tmp);
8309 %}
8310 %}
8311
8312 // Long to Float conversion using fast fxtof
8313 instruct convL2F_helper(regF dst, regD tmp) %{
8314 effect(DEF dst, USE tmp);
8315 size(4);
8316 format %{ "FXTOS $tmp,$dst" %}
8317 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8318 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8319 ins_pipe(fcvtL2F);
8320 %}
8321
8322 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8323 match(Set dst (ConvL2F src));
8324 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8325 expand %{
8326 regD tmp;
8327 stkL_to_regD(tmp, src);
8328 convL2F_helper(dst, tmp);
8329 %}
8330 %}
8331
8332 instruct convL2F_reg(regF dst, iRegL src) %{
8333 predicate(UseVIS >= 3);
8334 match(Set dst (ConvL2F src));
8335 ins_cost(DEFAULT_COST);
8336 expand %{
8337 regD tmp;
8338 MoveL2D_reg_reg(tmp, src);
8339 convL2F_helper(dst, tmp);
8340 %}
8341 %}
8342
8343 //-----------
8344
8345 instruct convL2I_reg(iRegI dst, iRegL src) %{
8346 match(Set dst (ConvL2I src));
8347 size(4);
8348 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8349 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8350 ins_pipe(ialu_reg);
8351 %}
8352
8353 // Register Shift Right Immediate
8354 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8355 match(Set dst (ConvL2I (RShiftL src cnt)));
8356
8357 size(4);
8358 format %{ "SRAX $src,$cnt,$dst" %}
8359 opcode(Assembler::srax_op3, Assembler::arith_op);
8360 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8361 ins_pipe(ialu_reg_imm);
8362 %}
8363
8364 //----------Control Flow Instructions------------------------------------------
8365 // Compare Instructions
8366 // Compare Integers
8367 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8368 match(Set icc (CmpI op1 op2));
8369 effect( DEF icc, USE op1, USE op2 );
8370
8371 size(4);
8372 format %{ "CMP $op1,$op2" %}
8373 opcode(Assembler::subcc_op3, Assembler::arith_op);
8374 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8375 ins_pipe(ialu_cconly_reg_reg);
8376 %}
8377
8378 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8379 match(Set icc (CmpU op1 op2));
8380
8381 size(4);
8382 format %{ "CMP $op1,$op2\t! unsigned" %}
8383 opcode(Assembler::subcc_op3, Assembler::arith_op);
8384 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8385 ins_pipe(ialu_cconly_reg_reg);
8386 %}
8387
8388 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8389 match(Set icc (CmpI op1 op2));
8390 effect( DEF icc, USE op1 );
8391
8392 size(4);
8393 format %{ "CMP $op1,$op2" %}
8394 opcode(Assembler::subcc_op3, Assembler::arith_op);
8395 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8396 ins_pipe(ialu_cconly_reg_imm);
8397 %}
8398
8399 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8400 match(Set icc (CmpI (AndI op1 op2) zero));
8401
8402 size(4);
8403 format %{ "BTST $op2,$op1" %}
8404 opcode(Assembler::andcc_op3, Assembler::arith_op);
8405 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8406 ins_pipe(ialu_cconly_reg_reg_zero);
8407 %}
8408
8409 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8410 match(Set icc (CmpI (AndI op1 op2) zero));
8411
8412 size(4);
8413 format %{ "BTST $op2,$op1" %}
8414 opcode(Assembler::andcc_op3, Assembler::arith_op);
8415 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8416 ins_pipe(ialu_cconly_reg_imm_zero);
8417 %}
8418
8419 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8420 match(Set xcc (CmpL op1 op2));
8421 effect( DEF xcc, USE op1, USE op2 );
8422
8423 size(4);
8424 format %{ "CMP $op1,$op2\t\t! long" %}
8425 opcode(Assembler::subcc_op3, Assembler::arith_op);
8426 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8427 ins_pipe(ialu_cconly_reg_reg);
8428 %}
8429
8430 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8431 match(Set xcc (CmpL op1 con));
8432 effect( DEF xcc, USE op1, USE con );
8433
8434 size(4);
8435 format %{ "CMP $op1,$con\t\t! long" %}
8436 opcode(Assembler::subcc_op3, Assembler::arith_op);
8437 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8438 ins_pipe(ialu_cconly_reg_reg);
8439 %}
8440
8441 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8442 match(Set xcc (CmpL (AndL op1 op2) zero));
8443 effect( DEF xcc, USE op1, USE op2 );
8444
8445 size(4);
8446 format %{ "BTST $op1,$op2\t\t! long" %}
8447 opcode(Assembler::andcc_op3, Assembler::arith_op);
8448 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8449 ins_pipe(ialu_cconly_reg_reg);
8450 %}
8451
8452 // useful for checking the alignment of a pointer:
8453 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8454 match(Set xcc (CmpL (AndL op1 con) zero));
8455 effect( DEF xcc, USE op1, USE con );
8456
8457 size(4);
8458 format %{ "BTST $op1,$con\t\t! long" %}
8459 opcode(Assembler::andcc_op3, Assembler::arith_op);
8460 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8461 ins_pipe(ialu_cconly_reg_reg);
8462 %}
8463
8464 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8465 match(Set icc (CmpU op1 op2));
8466
8467 size(4);
8468 format %{ "CMP $op1,$op2\t! unsigned" %}
8469 opcode(Assembler::subcc_op3, Assembler::arith_op);
8470 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8471 ins_pipe(ialu_cconly_reg_imm);
8472 %}
8473
8474 // Compare Pointers
8475 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8476 match(Set pcc (CmpP op1 op2));
8477
8478 size(4);
8479 format %{ "CMP $op1,$op2\t! ptr" %}
8480 opcode(Assembler::subcc_op3, Assembler::arith_op);
8481 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8482 ins_pipe(ialu_cconly_reg_reg);
8483 %}
8484
8485 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8486 match(Set pcc (CmpP op1 op2));
8487
8488 size(4);
8489 format %{ "CMP $op1,$op2\t! ptr" %}
8490 opcode(Assembler::subcc_op3, Assembler::arith_op);
8491 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8492 ins_pipe(ialu_cconly_reg_imm);
8493 %}
8494
8495 // Compare Narrow oops
8496 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8497 match(Set icc (CmpN op1 op2));
8498
8499 size(4);
8500 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8501 opcode(Assembler::subcc_op3, Assembler::arith_op);
8502 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8503 ins_pipe(ialu_cconly_reg_reg);
8504 %}
8505
8506 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8507 match(Set icc (CmpN op1 op2));
8508
8509 size(4);
8510 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8511 opcode(Assembler::subcc_op3, Assembler::arith_op);
8512 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8513 ins_pipe(ialu_cconly_reg_imm);
8514 %}
8515
8516 //----------Max and Min--------------------------------------------------------
8517 // Min Instructions
8518 // Conditional move for min
8519 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8520 effect( USE_DEF op2, USE op1, USE icc );
8521
8522 size(4);
8523 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8524 opcode(Assembler::less);
8525 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8526 ins_pipe(ialu_reg_flags);
8527 %}
8528
8529 // Min Register with Register.
8530 instruct minI_eReg(iRegI op1, iRegI op2) %{
8531 match(Set op2 (MinI op1 op2));
8532 ins_cost(DEFAULT_COST*2);
8533 expand %{
8534 flagsReg icc;
8535 compI_iReg(icc,op1,op2);
8536 cmovI_reg_lt(op2,op1,icc);
8537 %}
8538 %}
8539
8540 // Max Instructions
8541 // Conditional move for max
8542 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8543 effect( USE_DEF op2, USE op1, USE icc );
8544 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8545 opcode(Assembler::greater);
8546 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8547 ins_pipe(ialu_reg_flags);
8548 %}
8549
8550 // Max Register with Register
8551 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8552 match(Set op2 (MaxI op1 op2));
8553 ins_cost(DEFAULT_COST*2);
8554 expand %{
8555 flagsReg icc;
8556 compI_iReg(icc,op1,op2);
8557 cmovI_reg_gt(op2,op1,icc);
8558 %}
8559 %}
8560
8561
8562 //----------Float Compares----------------------------------------------------
8563 // Compare floating, generate condition code
8564 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8565 match(Set fcc (CmpF src1 src2));
8566
8567 size(4);
8568 format %{ "FCMPs $fcc,$src1,$src2" %}
8569 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8570 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8571 ins_pipe(faddF_fcc_reg_reg_zero);
8572 %}
8573
8574 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8575 match(Set fcc (CmpD src1 src2));
8576
8577 size(4);
8578 format %{ "FCMPd $fcc,$src1,$src2" %}
8579 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8580 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8581 ins_pipe(faddD_fcc_reg_reg_zero);
8582 %}
8583
8584
8585 // Compare floating, generate -1,0,1
8586 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8587 match(Set dst (CmpF3 src1 src2));
8588 effect(KILL fcc0);
8589 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8590 format %{ "fcmpl $dst,$src1,$src2" %}
8591 // Primary = float
8592 opcode( true );
8593 ins_encode( floating_cmp( dst, src1, src2 ) );
8594 ins_pipe( floating_cmp );
8595 %}
8596
8597 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8598 match(Set dst (CmpD3 src1 src2));
8599 effect(KILL fcc0);
8600 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8601 format %{ "dcmpl $dst,$src1,$src2" %}
8602 // Primary = double (not float)
8603 opcode( false );
8604 ins_encode( floating_cmp( dst, src1, src2 ) );
8605 ins_pipe( floating_cmp );
8606 %}
8607
8608 //----------Branches---------------------------------------------------------
8609 // Jump
8610 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8611 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8612 match(Jump switch_val);
8613 effect(TEMP table);
8614
8615 ins_cost(350);
8616
8617 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
8618 "LD [O7 + $switch_val], O7\n\t"
8619 "JUMP O7" %}
8620 ins_encode %{
8621 // Calculate table address into a register.
8622 Register table_reg;
8623 Register label_reg = O7;
8624 // If we are calculating the size of this instruction don't trust
8625 // zero offsets because they might change when
8626 // MachConstantBaseNode decides to optimize the constant table
8627 // base.
8628 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
8629 table_reg = $constanttablebase;
8630 } else {
8631 table_reg = O7;
8632 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
8633 __ add($constanttablebase, con_offset, table_reg);
8634 }
8635
8636 // Jump to base address + switch value
8637 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
8638 __ jmp(label_reg, G0);
8639 __ delayed()->nop();
8640 %}
8641 ins_pipe(ialu_reg_reg);
8642 %}
8643
8644 // Direct Branch. Use V8 version with longer range.
8645 instruct branch(label labl) %{
8646 match(Goto);
8647 effect(USE labl);
8648
8649 size(8);
8650 ins_cost(BRANCH_COST);
8651 format %{ "BA $labl" %}
8652 ins_encode %{
8653 Label* L = $labl$$label;
8654 __ ba(*L);
8655 __ delayed()->nop();
8656 %}
8657 ins_avoid_back_to_back(AVOID_BEFORE);
8658 ins_pipe(br);
8659 %}
8660
8661 // Direct Branch, short with no delay slot
8662 instruct branch_short(label labl) %{
8663 match(Goto);
8664 predicate(UseCBCond);
8665 effect(USE labl);
8666
8667 size(4);
8668 ins_cost(BRANCH_COST);
8669 format %{ "BA $labl\t! short branch" %}
8670 ins_encode %{
8671 Label* L = $labl$$label;
8672 assert(__ use_cbcond(*L), "back to back cbcond");
8673 __ ba_short(*L);
8674 %}
8675 ins_short_branch(1);
8676 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
8677 ins_pipe(cbcond_reg_imm);
8678 %}
8679
8680 // Conditional Direct Branch
8681 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
8682 match(If cmp icc);
8683 effect(USE labl);
8684
8685 size(8);
8686 ins_cost(BRANCH_COST);
8687 format %{ "BP$cmp $icc,$labl" %}
8688 // Prim = bits 24-22, Secnd = bits 31-30
8689 ins_encode( enc_bp( labl, cmp, icc ) );
8690 ins_avoid_back_to_back(AVOID_BEFORE);
8691 ins_pipe(br_cc);
8692 %}
8693
8694 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
8695 match(If cmp icc);
8696 effect(USE labl);
8697
8698 ins_cost(BRANCH_COST);
8699 format %{ "BP$cmp $icc,$labl" %}
8700 // Prim = bits 24-22, Secnd = bits 31-30
8701 ins_encode( enc_bp( labl, cmp, icc ) );
8702 ins_avoid_back_to_back(AVOID_BEFORE);
8703 ins_pipe(br_cc);
8704 %}
8705
8706 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
8707 match(If cmp pcc);
8708 effect(USE labl);
8709
8710 size(8);
8711 ins_cost(BRANCH_COST);
8712 format %{ "BP$cmp $pcc,$labl" %}
8713 ins_encode %{
8714 Label* L = $labl$$label;
8715 Assembler::Predict predict_taken =
8716 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8717
8718 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
8719 __ delayed()->nop();
8720 %}
8721 ins_avoid_back_to_back(AVOID_BEFORE);
8722 ins_pipe(br_cc);
8723 %}
8724
8725 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
8726 match(If cmp fcc);
8727 effect(USE labl);
8728
8729 size(8);
8730 ins_cost(BRANCH_COST);
8731 format %{ "FBP$cmp $fcc,$labl" %}
8732 ins_encode %{
8733 Label* L = $labl$$label;
8734 Assembler::Predict predict_taken =
8735 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8736
8737 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
8738 __ delayed()->nop();
8739 %}
8740 ins_avoid_back_to_back(AVOID_BEFORE);
8741 ins_pipe(br_fcc);
8742 %}
8743
8744 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
8745 match(CountedLoopEnd cmp icc);
8746 effect(USE labl);
8747
8748 size(8);
8749 ins_cost(BRANCH_COST);
8750 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8751 // Prim = bits 24-22, Secnd = bits 31-30
8752 ins_encode( enc_bp( labl, cmp, icc ) );
8753 ins_avoid_back_to_back(AVOID_BEFORE);
8754 ins_pipe(br_cc);
8755 %}
8756
8757 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
8758 match(CountedLoopEnd cmp icc);
8759 effect(USE labl);
8760
8761 size(8);
8762 ins_cost(BRANCH_COST);
8763 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8764 // Prim = bits 24-22, Secnd = bits 31-30
8765 ins_encode( enc_bp( labl, cmp, icc ) );
8766 ins_avoid_back_to_back(AVOID_BEFORE);
8767 ins_pipe(br_cc);
8768 %}
8769
8770 // Compare and branch instructions
8771 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
8772 match(If cmp (CmpI op1 op2));
8773 effect(USE labl, KILL icc);
8774
8775 size(12);
8776 ins_cost(BRANCH_COST);
8777 format %{ "CMP $op1,$op2\t! int\n\t"
8778 "BP$cmp $labl" %}
8779 ins_encode %{
8780 Label* L = $labl$$label;
8781 Assembler::Predict predict_taken =
8782 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8783 __ cmp($op1$$Register, $op2$$Register);
8784 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8785 __ delayed()->nop();
8786 %}
8787 ins_pipe(cmp_br_reg_reg);
8788 %}
8789
8790 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
8791 match(If cmp (CmpI op1 op2));
8792 effect(USE labl, KILL icc);
8793
8794 size(12);
8795 ins_cost(BRANCH_COST);
8796 format %{ "CMP $op1,$op2\t! int\n\t"
8797 "BP$cmp $labl" %}
8798 ins_encode %{
8799 Label* L = $labl$$label;
8800 Assembler::Predict predict_taken =
8801 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8802 __ cmp($op1$$Register, $op2$$constant);
8803 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8804 __ delayed()->nop();
8805 %}
8806 ins_pipe(cmp_br_reg_imm);
8807 %}
8808
8809 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
8810 match(If cmp (CmpU op1 op2));
8811 effect(USE labl, KILL icc);
8812
8813 size(12);
8814 ins_cost(BRANCH_COST);
8815 format %{ "CMP $op1,$op2\t! unsigned\n\t"
8816 "BP$cmp $labl" %}
8817 ins_encode %{
8818 Label* L = $labl$$label;
8819 Assembler::Predict predict_taken =
8820 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8821 __ cmp($op1$$Register, $op2$$Register);
8822 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8823 __ delayed()->nop();
8824 %}
8825 ins_pipe(cmp_br_reg_reg);
8826 %}
8827
8828 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
8829 match(If cmp (CmpU op1 op2));
8830 effect(USE labl, KILL icc);
8831
8832 size(12);
8833 ins_cost(BRANCH_COST);
8834 format %{ "CMP $op1,$op2\t! unsigned\n\t"
8835 "BP$cmp $labl" %}
8836 ins_encode %{
8837 Label* L = $labl$$label;
8838 Assembler::Predict predict_taken =
8839 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8840 __ cmp($op1$$Register, $op2$$constant);
8841 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8842 __ delayed()->nop();
8843 %}
8844 ins_pipe(cmp_br_reg_imm);
8845 %}
8846
8847 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
8848 match(If cmp (CmpL op1 op2));
8849 effect(USE labl, KILL xcc);
8850
8851 size(12);
8852 ins_cost(BRANCH_COST);
8853 format %{ "CMP $op1,$op2\t! long\n\t"
8854 "BP$cmp $labl" %}
8855 ins_encode %{
8856 Label* L = $labl$$label;
8857 Assembler::Predict predict_taken =
8858 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8859 __ cmp($op1$$Register, $op2$$Register);
8860 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
8861 __ delayed()->nop();
8862 %}
8863 ins_pipe(cmp_br_reg_reg);
8864 %}
8865
8866 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
8867 match(If cmp (CmpL op1 op2));
8868 effect(USE labl, KILL xcc);
8869
8870 size(12);
8871 ins_cost(BRANCH_COST);
8872 format %{ "CMP $op1,$op2\t! long\n\t"
8873 "BP$cmp $labl" %}
8874 ins_encode %{
8875 Label* L = $labl$$label;
8876 Assembler::Predict predict_taken =
8877 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8878 __ cmp($op1$$Register, $op2$$constant);
8879 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
8880 __ delayed()->nop();
8881 %}
8882 ins_pipe(cmp_br_reg_imm);
8883 %}
8884
8885 // Compare Pointers and branch
8886 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
8887 match(If cmp (CmpP op1 op2));
8888 effect(USE labl, KILL pcc);
8889
8890 size(12);
8891 ins_cost(BRANCH_COST);
8892 format %{ "CMP $op1,$op2\t! ptr\n\t"
8893 "B$cmp $labl" %}
8894 ins_encode %{
8895 Label* L = $labl$$label;
8896 Assembler::Predict predict_taken =
8897 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8898 __ cmp($op1$$Register, $op2$$Register);
8899 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
8900 __ delayed()->nop();
8901 %}
8902 ins_pipe(cmp_br_reg_reg);
8903 %}
8904
8905 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
8906 match(If cmp (CmpP op1 null));
8907 effect(USE labl, KILL pcc);
8908
8909 size(12);
8910 ins_cost(BRANCH_COST);
8911 format %{ "CMP $op1,0\t! ptr\n\t"
8912 "B$cmp $labl" %}
8913 ins_encode %{
8914 Label* L = $labl$$label;
8915 Assembler::Predict predict_taken =
8916 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8917 __ cmp($op1$$Register, G0);
8918 // bpr() is not used here since it has shorter distance.
8919 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
8920 __ delayed()->nop();
8921 %}
8922 ins_pipe(cmp_br_reg_reg);
8923 %}
8924
8925 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
8926 match(If cmp (CmpN op1 op2));
8927 effect(USE labl, KILL icc);
8928
8929 size(12);
8930 ins_cost(BRANCH_COST);
8931 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
8932 "BP$cmp $labl" %}
8933 ins_encode %{
8934 Label* L = $labl$$label;
8935 Assembler::Predict predict_taken =
8936 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8937 __ cmp($op1$$Register, $op2$$Register);
8938 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8939 __ delayed()->nop();
8940 %}
8941 ins_pipe(cmp_br_reg_reg);
8942 %}
8943
8944 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
8945 match(If cmp (CmpN op1 null));
8946 effect(USE labl, KILL icc);
8947
8948 size(12);
8949 ins_cost(BRANCH_COST);
8950 format %{ "CMP $op1,0\t! compressed ptr\n\t"
8951 "BP$cmp $labl" %}
8952 ins_encode %{
8953 Label* L = $labl$$label;
8954 Assembler::Predict predict_taken =
8955 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8956 __ cmp($op1$$Register, G0);
8957 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8958 __ delayed()->nop();
8959 %}
8960 ins_pipe(cmp_br_reg_reg);
8961 %}
8962
8963 // Loop back branch
8964 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
8965 match(CountedLoopEnd cmp (CmpI op1 op2));
8966 effect(USE labl, KILL icc);
8967
8968 size(12);
8969 ins_cost(BRANCH_COST);
8970 format %{ "CMP $op1,$op2\t! int\n\t"
8971 "BP$cmp $labl\t! Loop end" %}
8972 ins_encode %{
8973 Label* L = $labl$$label;
8974 Assembler::Predict predict_taken =
8975 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8976 __ cmp($op1$$Register, $op2$$Register);
8977 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8978 __ delayed()->nop();
8979 %}
8980 ins_pipe(cmp_br_reg_reg);
8981 %}
8982
8983 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
8984 match(CountedLoopEnd cmp (CmpI op1 op2));
8985 effect(USE labl, KILL icc);
8986
8987 size(12);
8988 ins_cost(BRANCH_COST);
8989 format %{ "CMP $op1,$op2\t! int\n\t"
8990 "BP$cmp $labl\t! Loop end" %}
8991 ins_encode %{
8992 Label* L = $labl$$label;
8993 Assembler::Predict predict_taken =
8994 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8995 __ cmp($op1$$Register, $op2$$constant);
8996 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8997 __ delayed()->nop();
8998 %}
8999 ins_pipe(cmp_br_reg_imm);
9000 %}
9001
9002 // Short compare and branch instructions
9003 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9004 match(If cmp (CmpI op1 op2));
9005 predicate(UseCBCond);
9006 effect(USE labl, KILL icc);
9007
9008 size(4);
9009 ins_cost(BRANCH_COST);
9010 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9011 ins_encode %{
9012 Label* L = $labl$$label;
9013 assert(__ use_cbcond(*L), "back to back cbcond");
9014 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9015 %}
9016 ins_short_branch(1);
9017 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9018 ins_pipe(cbcond_reg_reg);
9019 %}
9020
9021 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9022 match(If cmp (CmpI op1 op2));
9023 predicate(UseCBCond);
9024 effect(USE labl, KILL icc);
9025
9026 size(4);
9027 ins_cost(BRANCH_COST);
9028 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9029 ins_encode %{
9030 Label* L = $labl$$label;
9031 assert(__ use_cbcond(*L), "back to back cbcond");
9032 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9033 %}
9034 ins_short_branch(1);
9035 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9036 ins_pipe(cbcond_reg_imm);
9037 %}
9038
9039 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9040 match(If cmp (CmpU op1 op2));
9041 predicate(UseCBCond);
9042 effect(USE labl, KILL icc);
9043
9044 size(4);
9045 ins_cost(BRANCH_COST);
9046 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9047 ins_encode %{
9048 Label* L = $labl$$label;
9049 assert(__ use_cbcond(*L), "back to back cbcond");
9050 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9051 %}
9052 ins_short_branch(1);
9053 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9054 ins_pipe(cbcond_reg_reg);
9055 %}
9056
9057 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9058 match(If cmp (CmpU op1 op2));
9059 predicate(UseCBCond);
9060 effect(USE labl, KILL icc);
9061
9062 size(4);
9063 ins_cost(BRANCH_COST);
9064 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9065 ins_encode %{
9066 Label* L = $labl$$label;
9067 assert(__ use_cbcond(*L), "back to back cbcond");
9068 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9069 %}
9070 ins_short_branch(1);
9071 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9072 ins_pipe(cbcond_reg_imm);
9073 %}
9074
9075 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9076 match(If cmp (CmpL op1 op2));
9077 predicate(UseCBCond);
9078 effect(USE labl, KILL xcc);
9079
9080 size(4);
9081 ins_cost(BRANCH_COST);
9082 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9083 ins_encode %{
9084 Label* L = $labl$$label;
9085 assert(__ use_cbcond(*L), "back to back cbcond");
9086 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9087 %}
9088 ins_short_branch(1);
9089 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9090 ins_pipe(cbcond_reg_reg);
9091 %}
9092
9093 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9094 match(If cmp (CmpL op1 op2));
9095 predicate(UseCBCond);
9096 effect(USE labl, KILL xcc);
9097
9098 size(4);
9099 ins_cost(BRANCH_COST);
9100 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9101 ins_encode %{
9102 Label* L = $labl$$label;
9103 assert(__ use_cbcond(*L), "back to back cbcond");
9104 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9105 %}
9106 ins_short_branch(1);
9107 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9108 ins_pipe(cbcond_reg_imm);
9109 %}
9110
9111 // Compare Pointers and branch
9112 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9113 match(If cmp (CmpP op1 op2));
9114 predicate(UseCBCond);
9115 effect(USE labl, KILL pcc);
9116
9117 size(4);
9118 ins_cost(BRANCH_COST);
9119 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9120 ins_encode %{
9121 Label* L = $labl$$label;
9122 assert(__ use_cbcond(*L), "back to back cbcond");
9123 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9124 %}
9125 ins_short_branch(1);
9126 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9127 ins_pipe(cbcond_reg_reg);
9128 %}
9129
9130 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9131 match(If cmp (CmpP op1 null));
9132 predicate(UseCBCond);
9133 effect(USE labl, KILL pcc);
9134
9135 size(4);
9136 ins_cost(BRANCH_COST);
9137 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9138 ins_encode %{
9139 Label* L = $labl$$label;
9140 assert(__ use_cbcond(*L), "back to back cbcond");
9141 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9142 %}
9143 ins_short_branch(1);
9144 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9145 ins_pipe(cbcond_reg_reg);
9146 %}
9147
9148 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9149 match(If cmp (CmpN op1 op2));
9150 predicate(UseCBCond);
9151 effect(USE labl, KILL icc);
9152
9153 size(4);
9154 ins_cost(BRANCH_COST);
9155 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %}
9156 ins_encode %{
9157 Label* L = $labl$$label;
9158 assert(__ use_cbcond(*L), "back to back cbcond");
9159 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9160 %}
9161 ins_short_branch(1);
9162 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9163 ins_pipe(cbcond_reg_reg);
9164 %}
9165
9166 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9167 match(If cmp (CmpN op1 null));
9168 predicate(UseCBCond);
9169 effect(USE labl, KILL icc);
9170
9171 size(4);
9172 ins_cost(BRANCH_COST);
9173 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9174 ins_encode %{
9175 Label* L = $labl$$label;
9176 assert(__ use_cbcond(*L), "back to back cbcond");
9177 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9178 %}
9179 ins_short_branch(1);
9180 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9181 ins_pipe(cbcond_reg_reg);
9182 %}
9183
9184 // Loop back branch
9185 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9186 match(CountedLoopEnd cmp (CmpI op1 op2));
9187 predicate(UseCBCond);
9188 effect(USE labl, KILL icc);
9189
9190 size(4);
9191 ins_cost(BRANCH_COST);
9192 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9193 ins_encode %{
9194 Label* L = $labl$$label;
9195 assert(__ use_cbcond(*L), "back to back cbcond");
9196 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9197 %}
9198 ins_short_branch(1);
9199 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9200 ins_pipe(cbcond_reg_reg);
9201 %}
9202
9203 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9204 match(CountedLoopEnd cmp (CmpI op1 op2));
9205 predicate(UseCBCond);
9206 effect(USE labl, KILL icc);
9207
9208 size(4);
9209 ins_cost(BRANCH_COST);
9210 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9211 ins_encode %{
9212 Label* L = $labl$$label;
9213 assert(__ use_cbcond(*L), "back to back cbcond");
9214 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9215 %}
9216 ins_short_branch(1);
9217 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9218 ins_pipe(cbcond_reg_imm);
9219 %}
9220
9221 // Branch-on-register tests all 64 bits. We assume that values
9222 // in 64-bit registers always remains zero or sign extended
9223 // unless our code munges the high bits. Interrupts can chop
9224 // the high order bits to zero or sign at any time.
9225 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9226 match(If cmp (CmpI op1 zero));
9227 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9228 effect(USE labl);
9229
9230 size(8);
9231 ins_cost(BRANCH_COST);
9232 format %{ "BR$cmp $op1,$labl" %}
9233 ins_encode( enc_bpr( labl, cmp, op1 ) );
9234 ins_avoid_back_to_back(AVOID_BEFORE);
9235 ins_pipe(br_reg);
9236 %}
9237
9238 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9239 match(If cmp (CmpP op1 null));
9240 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9241 effect(USE labl);
9242
9243 size(8);
9244 ins_cost(BRANCH_COST);
9245 format %{ "BR$cmp $op1,$labl" %}
9246 ins_encode( enc_bpr( labl, cmp, op1 ) );
9247 ins_avoid_back_to_back(AVOID_BEFORE);
9248 ins_pipe(br_reg);
9249 %}
9250
9251 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9252 match(If cmp (CmpL op1 zero));
9253 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9254 effect(USE labl);
9255
9256 size(8);
9257 ins_cost(BRANCH_COST);
9258 format %{ "BR$cmp $op1,$labl" %}
9259 ins_encode( enc_bpr( labl, cmp, op1 ) );
9260 ins_avoid_back_to_back(AVOID_BEFORE);
9261 ins_pipe(br_reg);
9262 %}
9263
9264
9265 // ============================================================================
9266 // Long Compare
9267 //
9268 // Currently we hold longs in 2 registers. Comparing such values efficiently
9269 // is tricky. The flavor of compare used depends on whether we are testing
9270 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9271 // The GE test is the negated LT test. The LE test can be had by commuting
9272 // the operands (yielding a GE test) and then negating; negate again for the
9273 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9274 // NE test is negated from that.
9275
9276 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9277 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9278 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9279 // are collapsed internally in the ADLC's dfa-gen code. The match for
9280 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9281 // foo match ends up with the wrong leaf. One fix is to not match both
9282 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9283 // both forms beat the trinary form of long-compare and both are very useful
9284 // on Intel which has so few registers.
9285
9286 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9287 match(If cmp xcc);
9288 effect(USE labl);
9289
9290 size(8);
9291 ins_cost(BRANCH_COST);
9292 format %{ "BP$cmp $xcc,$labl" %}
9293 ins_encode %{
9294 Label* L = $labl$$label;
9295 Assembler::Predict predict_taken =
9296 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9297
9298 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9299 __ delayed()->nop();
9300 %}
9301 ins_avoid_back_to_back(AVOID_BEFORE);
9302 ins_pipe(br_cc);
9303 %}
9304
9305 // Manifest a CmpL3 result in an integer register. Very painful.
9306 // This is the test to avoid.
9307 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9308 match(Set dst (CmpL3 src1 src2) );
9309 effect( KILL ccr );
9310 ins_cost(6*DEFAULT_COST);
9311 size(24);
9312 format %{ "CMP $src1,$src2\t\t! long\n"
9313 "\tBLT,a,pn done\n"
9314 "\tMOV -1,$dst\t! delay slot\n"
9315 "\tBGT,a,pn done\n"
9316 "\tMOV 1,$dst\t! delay slot\n"
9317 "\tCLR $dst\n"
9318 "done:" %}
9319 ins_encode( cmpl_flag(src1,src2,dst) );
9320 ins_pipe(cmpL_reg);
9321 %}
9322
9323 // Conditional move
9324 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9325 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9326 ins_cost(150);
9327 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9328 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9329 ins_pipe(ialu_reg);
9330 %}
9331
9332 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9333 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9334 ins_cost(140);
9335 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9336 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9337 ins_pipe(ialu_imm);
9338 %}
9339
9340 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9341 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9342 ins_cost(150);
9343 format %{ "MOV$cmp $xcc,$src,$dst" %}
9344 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9345 ins_pipe(ialu_reg);
9346 %}
9347
9348 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9349 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9350 ins_cost(140);
9351 format %{ "MOV$cmp $xcc,$src,$dst" %}
9352 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9353 ins_pipe(ialu_imm);
9354 %}
9355
9356 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9357 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9358 ins_cost(150);
9359 format %{ "MOV$cmp $xcc,$src,$dst" %}
9360 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9361 ins_pipe(ialu_reg);
9362 %}
9363
9364 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9365 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9366 ins_cost(150);
9367 format %{ "MOV$cmp $xcc,$src,$dst" %}
9368 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9369 ins_pipe(ialu_reg);
9370 %}
9371
9372 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9373 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9374 ins_cost(140);
9375 format %{ "MOV$cmp $xcc,$src,$dst" %}
9376 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9377 ins_pipe(ialu_imm);
9378 %}
9379
9380 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9381 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9382 ins_cost(150);
9383 opcode(0x101);
9384 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9385 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9386 ins_pipe(int_conditional_float_move);
9387 %}
9388
9389 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9390 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9391 ins_cost(150);
9392 opcode(0x102);
9393 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9394 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9395 ins_pipe(int_conditional_float_move);
9396 %}
9397
9398 // ============================================================================
9399 // Safepoint Instruction
9400 instruct safePoint_poll(iRegP poll) %{
9401 match(SafePoint poll);
9402 effect(USE poll);
9403
9404 size(4);
9405 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9406 ins_encode %{
9407 __ relocate(relocInfo::poll_type);
9408 __ ld_ptr($poll$$Register, 0, G0);
9409 %}
9410 ins_pipe(loadPollP);
9411 %}
9412
9413 // ============================================================================
9414 // Call Instructions
9415 // Call Java Static Instruction
9416 instruct CallStaticJavaDirect( method meth ) %{
9417 match(CallStaticJava);
9418 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9419 effect(USE meth);
9420
9421 size(8);
9422 ins_cost(CALL_COST);
9423 format %{ "CALL,static ; NOP ==> " %}
9424 ins_encode( Java_Static_Call( meth ), call_epilog );
9425 ins_avoid_back_to_back(AVOID_BEFORE);
9426 ins_pipe(simple_call);
9427 %}
9428
9429 // Call Java Static Instruction (method handle version)
9430 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9431 match(CallStaticJava);
9432 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9433 effect(USE meth, KILL l7_mh_SP_save);
9434
9435 size(16);
9436 ins_cost(CALL_COST);
9437 format %{ "CALL,static/MethodHandle" %}
9438 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9439 ins_pipe(simple_call);
9440 %}
9441
9442 // Call Java Dynamic Instruction
9443 instruct CallDynamicJavaDirect( method meth ) %{
9444 match(CallDynamicJava);
9445 effect(USE meth);
9446
9447 ins_cost(CALL_COST);
9448 format %{ "SET (empty),R_G5\n\t"
9449 "CALL,dynamic ; NOP ==> " %}
9450 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9451 ins_pipe(call);
9452 %}
9453
9454 // Call Runtime Instruction
9455 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9456 match(CallRuntime);
9457 effect(USE meth, KILL l7);
9458 ins_cost(CALL_COST);
9459 format %{ "CALL,runtime" %}
9460 ins_encode( Java_To_Runtime( meth ),
9461 call_epilog, adjust_long_from_native_call );
9462 ins_avoid_back_to_back(AVOID_BEFORE);
9463 ins_pipe(simple_call);
9464 %}
9465
9466 // Call runtime without safepoint - same as CallRuntime
9467 instruct CallLeafDirect(method meth, l7RegP l7) %{
9468 match(CallLeaf);
9469 effect(USE meth, KILL l7);
9470 ins_cost(CALL_COST);
9471 format %{ "CALL,runtime leaf" %}
9472 ins_encode( Java_To_Runtime( meth ),
9473 call_epilog,
9474 adjust_long_from_native_call );
9475 ins_avoid_back_to_back(AVOID_BEFORE);
9476 ins_pipe(simple_call);
9477 %}
9478
9479 // Call runtime without safepoint - same as CallLeaf
9480 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9481 match(CallLeafNoFP);
9482 effect(USE meth, KILL l7);
9483 ins_cost(CALL_COST);
9484 format %{ "CALL,runtime leaf nofp" %}
9485 ins_encode( Java_To_Runtime( meth ),
9486 call_epilog,
9487 adjust_long_from_native_call );
9488 ins_avoid_back_to_back(AVOID_BEFORE);
9489 ins_pipe(simple_call);
9490 %}
9491
9492 // Tail Call; Jump from runtime stub to Java code.
9493 // Also known as an 'interprocedural jump'.
9494 // Target of jump will eventually return to caller.
9495 // TailJump below removes the return address.
9496 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9497 match(TailCall jump_target method_oop );
9498
9499 ins_cost(CALL_COST);
9500 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9501 ins_encode(form_jmpl(jump_target));
9502 ins_avoid_back_to_back(AVOID_BEFORE);
9503 ins_pipe(tail_call);
9504 %}
9505
9506
9507 // Return Instruction
9508 instruct Ret() %{
9509 match(Return);
9510
9511 // The epilogue node did the ret already.
9512 size(0);
9513 format %{ "! return" %}
9514 ins_encode();
9515 ins_pipe(empty);
9516 %}
9517
9518
9519 // Tail Jump; remove the return address; jump to target.
9520 // TailCall above leaves the return address around.
9521 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9522 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9523 // "restore" before this instruction (in Epilogue), we need to materialize it
9524 // in %i0.
9525 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9526 match( TailJump jump_target ex_oop );
9527 ins_cost(CALL_COST);
9528 format %{ "! discard R_O7\n\t"
9529 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9530 ins_encode(form_jmpl_set_exception_pc(jump_target));
9531 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9532 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9533 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9534 ins_avoid_back_to_back(AVOID_BEFORE);
9535 ins_pipe(tail_call);
9536 %}
9537
9538 // Create exception oop: created by stack-crawling runtime code.
9539 // Created exception is now available to this handler, and is setup
9540 // just prior to jumping to this handler. No code emitted.
9541 instruct CreateException( o0RegP ex_oop )
9542 %{
9543 match(Set ex_oop (CreateEx));
9544 ins_cost(0);
9545
9546 size(0);
9547 // use the following format syntax
9548 format %{ "! exception oop is in R_O0; no code emitted" %}
9549 ins_encode();
9550 ins_pipe(empty);
9551 %}
9552
9553
9554 // Rethrow exception:
9555 // The exception oop will come in the first argument position.
9556 // Then JUMP (not call) to the rethrow stub code.
9557 instruct RethrowException()
9558 %{
9559 match(Rethrow);
9560 ins_cost(CALL_COST);
9561
9562 // use the following format syntax
9563 format %{ "Jmp rethrow_stub" %}
9564 ins_encode(enc_rethrow);
9565 ins_avoid_back_to_back(AVOID_BEFORE);
9566 ins_pipe(tail_call);
9567 %}
9568
9569
9570 // Die now
9571 instruct ShouldNotReachHere( )
9572 %{
9573 match(Halt);
9574 ins_cost(CALL_COST);
9575
9576 size(4);
9577 // Use the following format syntax
9578 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9579 ins_encode( form2_illtrap() );
9580 ins_pipe(tail_call);
9581 %}
9582
9583 // ============================================================================
9584 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9585 // array for an instance of the superklass. Set a hidden internal cache on a
9586 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9587 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9588 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9589 match(Set index (PartialSubtypeCheck sub super));
9590 effect( KILL pcc, KILL o7 );
9591 ins_cost(DEFAULT_COST*10);
9592 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9593 ins_encode( enc_PartialSubtypeCheck() );
9594 ins_avoid_back_to_back(AVOID_BEFORE);
9595 ins_pipe(partial_subtype_check_pipe);
9596 %}
9597
9598 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9599 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9600 effect( KILL idx, KILL o7 );
9601 ins_cost(DEFAULT_COST*10);
9602 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9603 ins_encode( enc_PartialSubtypeCheck() );
9604 ins_avoid_back_to_back(AVOID_BEFORE);
9605 ins_pipe(partial_subtype_check_pipe);
9606 %}
9607
9608
9609 // ============================================================================
9610 // inlined locking and unlocking
9611
9612 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9613 match(Set pcc (FastLock object box));
9614
9615 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9616 ins_cost(100);
9617
9618 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9619 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9620 ins_pipe(long_memory_op);
9621 %}
9622
9623
9624 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9625 match(Set pcc (FastUnlock object box));
9626 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9627 ins_cost(100);
9628
9629 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9630 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9631 ins_pipe(long_memory_op);
9632 %}
9633
9634 // The encodings are generic.
9635 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9636 predicate(!use_block_zeroing(n->in(2)) );
9637 match(Set dummy (ClearArray cnt base));
9638 effect(TEMP temp, KILL ccr);
9639 ins_cost(300);
9640 format %{ "MOV $cnt,$temp\n"
9641 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9642 " BRge loop\t\t! Clearing loop\n"
9643 " STX G0,[$base+$temp]\t! delay slot" %}
9644
9645 ins_encode %{
9646 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
9647 Register nof_bytes_arg = $cnt$$Register;
9648 Register nof_bytes_tmp = $temp$$Register;
9649 Register base_pointer_arg = $base$$Register;
9650
9651 Label loop;
9652 __ mov(nof_bytes_arg, nof_bytes_tmp);
9653
9654 // Loop and clear, walking backwards through the array.
9655 // nof_bytes_tmp (if >0) is always the number of bytes to zero
9656 __ bind(loop);
9657 __ deccc(nof_bytes_tmp, 8);
9658 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
9659 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
9660 // %%%% this mini-loop must not cross a cache boundary!
9661 %}
9662 ins_pipe(long_memory_op);
9663 %}
9664
9665 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
9666 predicate(use_block_zeroing(n->in(2)));
9667 match(Set dummy (ClearArray cnt base));
9668 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
9669 ins_cost(300);
9670 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
9671
9672 ins_encode %{
9673
9674 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
9675 Register to = $base$$Register;
9676 Register count = $cnt$$Register;
9677
9678 Label Ldone;
9679 __ nop(); // Separate short branches
9680 // Use BIS for zeroing (temp is not used).
9681 __ bis_zeroing(to, count, G0, Ldone);
9682 __ bind(Ldone);
9683
9684 %}
9685 ins_pipe(long_memory_op);
9686 %}
9687
9688 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
9689 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
9690 match(Set dummy (ClearArray cnt base));
9691 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
9692 ins_cost(300);
9693 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
9694
9695 ins_encode %{
9696
9697 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
9698 Register to = $base$$Register;
9699 Register count = $cnt$$Register;
9700 Register temp = $tmp$$Register;
9701
9702 Label Ldone;
9703 __ nop(); // Separate short branches
9704 // Use BIS for zeroing
9705 __ bis_zeroing(to, count, temp, Ldone);
9706 __ bind(Ldone);
9707
9708 %}
9709 ins_pipe(long_memory_op);
9710 %}
9711
9712 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9713 o7RegI tmp, flagsReg ccr) %{
9714 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
9715 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9716 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
9717 ins_cost(300);
9718 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
9719 ins_encode %{
9720 __ string_compare($str1$$Register, $str2$$Register,
9721 $cnt1$$Register, $cnt2$$Register,
9722 $tmp$$Register, $tmp$$Register,
9723 $result$$Register, StrIntrinsicNode::LL);
9724 %}
9725 ins_pipe(long_memory_op);
9726 %}
9727
9728 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9729 o7RegI tmp, flagsReg ccr) %{
9730 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
9731 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9732 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
9733 ins_cost(300);
9734 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
9735 ins_encode %{
9736 __ string_compare($str1$$Register, $str2$$Register,
9737 $cnt1$$Register, $cnt2$$Register,
9738 $tmp$$Register, $tmp$$Register,
9739 $result$$Register, StrIntrinsicNode::UU);
9740 %}
9741 ins_pipe(long_memory_op);
9742 %}
9743
9744 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9745 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
9746 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
9747 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9748 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
9749 ins_cost(300);
9750 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
9751 ins_encode %{
9752 __ string_compare($str1$$Register, $str2$$Register,
9753 $cnt1$$Register, $cnt2$$Register,
9754 $tmp1$$Register, $tmp2$$Register,
9755 $result$$Register, StrIntrinsicNode::LU);
9756 %}
9757 ins_pipe(long_memory_op);
9758 %}
9759
9760 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9761 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
9762 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
9763 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9764 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
9765 ins_cost(300);
9766 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
9767 ins_encode %{
9768 __ string_compare($str2$$Register, $str1$$Register,
9769 $cnt2$$Register, $cnt1$$Register,
9770 $tmp1$$Register, $tmp2$$Register,
9771 $result$$Register, StrIntrinsicNode::UL);
9772 %}
9773 ins_pipe(long_memory_op);
9774 %}
9775
9776 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
9777 o7RegI tmp, flagsReg ccr) %{
9778 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
9779 match(Set result (StrEquals (Binary str1 str2) cnt));
9780 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
9781 ins_cost(300);
9782 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
9783 ins_encode %{
9784 __ array_equals(false, $str1$$Register, $str2$$Register,
9785 $cnt$$Register, $tmp$$Register,
9786 $result$$Register, true /* byte */);
9787 %}
9788 ins_pipe(long_memory_op);
9789 %}
9790
9791 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
9792 o7RegI tmp, flagsReg ccr) %{
9793 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
9794 match(Set result (StrEquals (Binary str1 str2) cnt));
9795 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
9796 ins_cost(300);
9797 format %{ "String Equals char[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
9798 ins_encode %{
9799 __ array_equals(false, $str1$$Register, $str2$$Register,
9800 $cnt$$Register, $tmp$$Register,
9801 $result$$Register, false /* byte */);
9802 %}
9803 ins_pipe(long_memory_op);
9804 %}
9805
9806 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
9807 o7RegI tmp2, flagsReg ccr) %{
9808 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
9809 match(Set result (AryEq ary1 ary2));
9810 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9811 ins_cost(300);
9812 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
9813 ins_encode %{
9814 __ array_equals(true, $ary1$$Register, $ary2$$Register,
9815 $tmp1$$Register, $tmp2$$Register,
9816 $result$$Register, true /* byte */);
9817 %}
9818 ins_pipe(long_memory_op);
9819 %}
9820
9821 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
9822 o7RegI tmp2, flagsReg ccr) %{
9823 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
9824 match(Set result (AryEq ary1 ary2));
9825 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9826 ins_cost(300);
9827 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
9828 ins_encode %{
9829 __ array_equals(true, $ary1$$Register, $ary2$$Register,
9830 $tmp1$$Register, $tmp2$$Register,
9831 $result$$Register, false /* byte */);
9832 %}
9833 ins_pipe(long_memory_op);
9834 %}
9835
9836 instruct has_negatives(o0RegP pAryR, g3RegI iSizeR, notemp_iRegI resultR,
9837 iRegL tmp1L, iRegL tmp2L, iRegL tmp3L, iRegL tmp4L,
9838 flagsReg ccr)
9839 %{
9840 match(Set resultR (HasNegatives pAryR iSizeR));
9841 effect(TEMP resultR, TEMP tmp1L, TEMP tmp2L, TEMP tmp3L, TEMP tmp4L, USE pAryR, USE iSizeR, KILL ccr);
9842 format %{ "has negatives byte[] $pAryR,$iSizeR -> $resultR // KILL $tmp1L,$tmp2L,$tmp3L,$tmp4L" %}
9843 ins_encode %{
9844 __ has_negatives($pAryR$$Register, $iSizeR$$Register,
9845 $resultR$$Register,
9846 $tmp1L$$Register, $tmp2L$$Register,
9847 $tmp3L$$Register, $tmp4L$$Register);
9848 %}
9849 ins_pipe(long_memory_op);
9850 %}
9851
9852 // char[] to byte[] compression
9853 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{
9854 predicate(UseVIS < 3);
9855 match(Set result (StrCompressedCopy src (Binary dst len)));
9856 effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
9857 ins_cost(300);
9858 format %{ "String Compress $src,$dst,$len -> $result // KILL $tmp" %}
9859 ins_encode %{
9860 Label Ldone;
9861 __ signx($len$$Register);
9862 __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn);
9863 __ delayed()->mov($len$$Register, $result$$Register); // copy count
9864 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone);
9865 __ bind(Ldone);
9866 %}
9867 ins_pipe(long_memory_op);
9868 %}
9869
9870 // fast char[] to byte[] compression using VIS instructions
9871 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result,
9872 iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4,
9873 regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{
9874 predicate(UseVIS >= 3);
9875 match(Set result (StrCompressedCopy src (Binary dst len)));
9876 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
9877 ins_cost(300);
9878 format %{ "String Compress Fast $src,$dst,$len -> $result // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %}
9879 ins_encode %{
9880 Label Ldone;
9881 __ signx($len$$Register);
9882 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register,
9883 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
9884 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone);
9885 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
9886 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone);
9887 __ bind(Ldone);
9888 %}
9889 ins_pipe(long_memory_op);
9890 %}
9891
9892 // byte[] to char[] inflation
9893 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
9894 iRegL tmp, flagsReg ccr) %{
9895 match(Set dummy (StrInflatedCopy src (Binary dst len)));
9896 effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
9897 ins_cost(300);
9898 format %{ "String Inflate $src,$dst,$len // KILL $tmp" %}
9899 ins_encode %{
9900 Label Ldone;
9901 __ signx($len$$Register);
9902 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
9903 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
9904 __ bind(Ldone);
9905 %}
9906 ins_pipe(long_memory_op);
9907 %}
9908
9909 // fast byte[] to char[] inflation using VIS instructions
9910 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
9911 iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{
9912 predicate(UseVIS >= 3);
9913 match(Set dummy (StrInflatedCopy src (Binary dst len)));
9914 effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
9915 ins_cost(300);
9916 format %{ "String Inflate Fast $src,$dst,$len // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %}
9917 ins_encode %{
9918 Label Ldone;
9919 __ signx($len$$Register);
9920 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register,
9921 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone);
9922 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
9923 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
9924 __ bind(Ldone);
9925 %}
9926 ins_pipe(long_memory_op);
9927 %}
9928
9929
9930 //---------- Zeros Count Instructions ------------------------------------------
9931
9932 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
9933 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9934 match(Set dst (CountLeadingZerosI src));
9935 effect(TEMP dst, TEMP tmp, KILL cr);
9936
9937 // x |= (x >> 1);
9938 // x |= (x >> 2);
9939 // x |= (x >> 4);
9940 // x |= (x >> 8);
9941 // x |= (x >> 16);
9942 // return (WORDBITS - popc(x));
9943 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
9944 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
9945 "OR $dst,$tmp,$dst\n\t"
9946 "SRL $dst,2,$tmp\n\t"
9947 "OR $dst,$tmp,$dst\n\t"
9948 "SRL $dst,4,$tmp\n\t"
9949 "OR $dst,$tmp,$dst\n\t"
9950 "SRL $dst,8,$tmp\n\t"
9951 "OR $dst,$tmp,$dst\n\t"
9952 "SRL $dst,16,$tmp\n\t"
9953 "OR $dst,$tmp,$dst\n\t"
9954 "POPC $dst,$dst\n\t"
9955 "MOV 32,$tmp\n\t"
9956 "SUB $tmp,$dst,$dst" %}
9957 ins_encode %{
9958 Register Rdst = $dst$$Register;
9959 Register Rsrc = $src$$Register;
9960 Register Rtmp = $tmp$$Register;
9961 __ srl(Rsrc, 1, Rtmp);
9962 __ srl(Rsrc, 0, Rdst);
9963 __ or3(Rdst, Rtmp, Rdst);
9964 __ srl(Rdst, 2, Rtmp);
9965 __ or3(Rdst, Rtmp, Rdst);
9966 __ srl(Rdst, 4, Rtmp);
9967 __ or3(Rdst, Rtmp, Rdst);
9968 __ srl(Rdst, 8, Rtmp);
9969 __ or3(Rdst, Rtmp, Rdst);
9970 __ srl(Rdst, 16, Rtmp);
9971 __ or3(Rdst, Rtmp, Rdst);
9972 __ popc(Rdst, Rdst);
9973 __ mov(BitsPerInt, Rtmp);
9974 __ sub(Rtmp, Rdst, Rdst);
9975 %}
9976 ins_pipe(ialu_reg);
9977 %}
9978
9979 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
9980 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9981 match(Set dst (CountLeadingZerosL src));
9982 effect(TEMP dst, TEMP tmp, KILL cr);
9983
9984 // x |= (x >> 1);
9985 // x |= (x >> 2);
9986 // x |= (x >> 4);
9987 // x |= (x >> 8);
9988 // x |= (x >> 16);
9989 // x |= (x >> 32);
9990 // return (WORDBITS - popc(x));
9991 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
9992 "OR $src,$tmp,$dst\n\t"
9993 "SRLX $dst,2,$tmp\n\t"
9994 "OR $dst,$tmp,$dst\n\t"
9995 "SRLX $dst,4,$tmp\n\t"
9996 "OR $dst,$tmp,$dst\n\t"
9997 "SRLX $dst,8,$tmp\n\t"
9998 "OR $dst,$tmp,$dst\n\t"
9999 "SRLX $dst,16,$tmp\n\t"
10000 "OR $dst,$tmp,$dst\n\t"
10001 "SRLX $dst,32,$tmp\n\t"
10002 "OR $dst,$tmp,$dst\n\t"
10003 "POPC $dst,$dst\n\t"
10004 "MOV 64,$tmp\n\t"
10005 "SUB $tmp,$dst,$dst" %}
10006 ins_encode %{
10007 Register Rdst = $dst$$Register;
10008 Register Rsrc = $src$$Register;
10009 Register Rtmp = $tmp$$Register;
10010 __ srlx(Rsrc, 1, Rtmp);
10011 __ or3( Rsrc, Rtmp, Rdst);
10012 __ srlx(Rdst, 2, Rtmp);
10013 __ or3( Rdst, Rtmp, Rdst);
10014 __ srlx(Rdst, 4, Rtmp);
10015 __ or3( Rdst, Rtmp, Rdst);
10016 __ srlx(Rdst, 8, Rtmp);
10017 __ or3( Rdst, Rtmp, Rdst);
10018 __ srlx(Rdst, 16, Rtmp);
10019 __ or3( Rdst, Rtmp, Rdst);
10020 __ srlx(Rdst, 32, Rtmp);
10021 __ or3( Rdst, Rtmp, Rdst);
10022 __ popc(Rdst, Rdst);
10023 __ mov(BitsPerLong, Rtmp);
10024 __ sub(Rtmp, Rdst, Rdst);
10025 %}
10026 ins_pipe(ialu_reg);
10027 %}
10028
10029 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10030 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10031 match(Set dst (CountTrailingZerosI src));
10032 effect(TEMP dst, KILL cr);
10033
10034 // return popc(~x & (x - 1));
10035 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10036 "ANDN $dst,$src,$dst\n\t"
10037 "SRL $dst,R_G0,$dst\n\t"
10038 "POPC $dst,$dst" %}
10039 ins_encode %{
10040 Register Rdst = $dst$$Register;
10041 Register Rsrc = $src$$Register;
10042 __ sub(Rsrc, 1, Rdst);
10043 __ andn(Rdst, Rsrc, Rdst);
10044 __ srl(Rdst, G0, Rdst);
10045 __ popc(Rdst, Rdst);
10046 %}
10047 ins_pipe(ialu_reg);
10048 %}
10049
10050 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10051 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10052 match(Set dst (CountTrailingZerosL src));
10053 effect(TEMP dst, KILL cr);
10054
10055 // return popc(~x & (x - 1));
10056 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10057 "ANDN $dst,$src,$dst\n\t"
10058 "POPC $dst,$dst" %}
10059 ins_encode %{
10060 Register Rdst = $dst$$Register;
10061 Register Rsrc = $src$$Register;
10062 __ sub(Rsrc, 1, Rdst);
10063 __ andn(Rdst, Rsrc, Rdst);
10064 __ popc(Rdst, Rdst);
10065 %}
10066 ins_pipe(ialu_reg);
10067 %}
10068
10069
10070 //---------- Population Count Instructions -------------------------------------
10071
10072 instruct popCountI(iRegIsafe dst, iRegI src) %{
10073 predicate(UsePopCountInstruction);
10074 match(Set dst (PopCountI src));
10075
10076 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10077 "POPC $dst, $dst" %}
10078 ins_encode %{
10079 __ srl($src$$Register, G0, $dst$$Register);
10080 __ popc($dst$$Register, $dst$$Register);
10081 %}
10082 ins_pipe(ialu_reg);
10083 %}
10084
10085 // Note: Long.bitCount(long) returns an int.
10086 instruct popCountL(iRegIsafe dst, iRegL src) %{
10087 predicate(UsePopCountInstruction);
10088 match(Set dst (PopCountL src));
10089
10090 format %{ "POPC $src, $dst" %}
10091 ins_encode %{
10092 __ popc($src$$Register, $dst$$Register);
10093 %}
10094 ins_pipe(ialu_reg);
10095 %}
10096
10097
10098 // ============================================================================
10099 //------------Bytes reverse--------------------------------------------------
10100
10101 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10102 match(Set dst (ReverseBytesI src));
10103
10104 // Op cost is artificially doubled to make sure that load or store
10105 // instructions are preferred over this one which requires a spill
10106 // onto a stack slot.
10107 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10108 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10109
10110 ins_encode %{
10111 __ set($src$$disp + STACK_BIAS, O7);
10112 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10113 %}
10114 ins_pipe( iload_mem );
10115 %}
10116
10117 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10118 match(Set dst (ReverseBytesL src));
10119
10120 // Op cost is artificially doubled to make sure that load or store
10121 // instructions are preferred over this one which requires a spill
10122 // onto a stack slot.
10123 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10124 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10125
10126 ins_encode %{
10127 __ set($src$$disp + STACK_BIAS, O7);
10128 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10129 %}
10130 ins_pipe( iload_mem );
10131 %}
10132
10133 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10134 match(Set dst (ReverseBytesUS src));
10135
10136 // Op cost is artificially doubled to make sure that load or store
10137 // instructions are preferred over this one which requires a spill
10138 // onto a stack slot.
10139 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10140 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10141
10142 ins_encode %{
10143 // the value was spilled as an int so bias the load
10144 __ set($src$$disp + STACK_BIAS + 2, O7);
10145 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10146 %}
10147 ins_pipe( iload_mem );
10148 %}
10149
10150 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10151 match(Set dst (ReverseBytesS src));
10152
10153 // Op cost is artificially doubled to make sure that load or store
10154 // instructions are preferred over this one which requires a spill
10155 // onto a stack slot.
10156 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10157 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10158
10159 ins_encode %{
10160 // the value was spilled as an int so bias the load
10161 __ set($src$$disp + STACK_BIAS + 2, O7);
10162 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10163 %}
10164 ins_pipe( iload_mem );
10165 %}
10166
10167 // Load Integer reversed byte order
10168 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10169 match(Set dst (ReverseBytesI (LoadI src)));
10170
10171 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10172 size(4);
10173 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10174
10175 ins_encode %{
10176 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10177 %}
10178 ins_pipe(iload_mem);
10179 %}
10180
10181 // Load Long - aligned and reversed
10182 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10183 match(Set dst (ReverseBytesL (LoadL src)));
10184
10185 ins_cost(MEMORY_REF_COST);
10186 size(4);
10187 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10188
10189 ins_encode %{
10190 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10191 %}
10192 ins_pipe(iload_mem);
10193 %}
10194
10195 // Load unsigned short / char reversed byte order
10196 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10197 match(Set dst (ReverseBytesUS (LoadUS src)));
10198
10199 ins_cost(MEMORY_REF_COST);
10200 size(4);
10201 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10202
10203 ins_encode %{
10204 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10205 %}
10206 ins_pipe(iload_mem);
10207 %}
10208
10209 // Load short reversed byte order
10210 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10211 match(Set dst (ReverseBytesS (LoadS src)));
10212
10213 ins_cost(MEMORY_REF_COST);
10214 size(4);
10215 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10216
10217 ins_encode %{
10218 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10219 %}
10220 ins_pipe(iload_mem);
10221 %}
10222
10223 // Store Integer reversed byte order
10224 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10225 match(Set dst (StoreI dst (ReverseBytesI src)));
10226
10227 ins_cost(MEMORY_REF_COST);
10228 size(4);
10229 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10230
10231 ins_encode %{
10232 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10233 %}
10234 ins_pipe(istore_mem_reg);
10235 %}
10236
10237 // Store Long reversed byte order
10238 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10239 match(Set dst (StoreL dst (ReverseBytesL src)));
10240
10241 ins_cost(MEMORY_REF_COST);
10242 size(4);
10243 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10244
10245 ins_encode %{
10246 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10247 %}
10248 ins_pipe(istore_mem_reg);
10249 %}
10250
10251 // Store unsighed short/char reversed byte order
10252 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10253 match(Set dst (StoreC dst (ReverseBytesUS src)));
10254
10255 ins_cost(MEMORY_REF_COST);
10256 size(4);
10257 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10258
10259 ins_encode %{
10260 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10261 %}
10262 ins_pipe(istore_mem_reg);
10263 %}
10264
10265 // Store short reversed byte order
10266 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10267 match(Set dst (StoreC dst (ReverseBytesS src)));
10268
10269 ins_cost(MEMORY_REF_COST);
10270 size(4);
10271 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10272
10273 ins_encode %{
10274 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10275 %}
10276 ins_pipe(istore_mem_reg);
10277 %}
10278
10279 // ====================VECTOR INSTRUCTIONS=====================================
10280
10281 // Load Aligned Packed values into a Double Register
10282 instruct loadV8(regD dst, memory mem) %{
10283 predicate(n->as_LoadVector()->memory_size() == 8);
10284 match(Set dst (LoadVector mem));
10285 ins_cost(MEMORY_REF_COST);
10286 size(4);
10287 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10288 ins_encode %{
10289 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10290 %}
10291 ins_pipe(floadD_mem);
10292 %}
10293
10294 // Store Vector in Double register to memory
10295 instruct storeV8(memory mem, regD src) %{
10296 predicate(n->as_StoreVector()->memory_size() == 8);
10297 match(Set mem (StoreVector mem src));
10298 ins_cost(MEMORY_REF_COST);
10299 size(4);
10300 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10301 ins_encode %{
10302 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10303 %}
10304 ins_pipe(fstoreD_mem_reg);
10305 %}
10306
10307 // Store Zero into vector in memory
10308 instruct storeV8B_zero(memory mem, immI0 zero) %{
10309 predicate(n->as_StoreVector()->memory_size() == 8);
10310 match(Set mem (StoreVector mem (ReplicateB zero)));
10311 ins_cost(MEMORY_REF_COST);
10312 size(4);
10313 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10314 ins_encode %{
10315 __ stx(G0, $mem$$Address);
10316 %}
10317 ins_pipe(fstoreD_mem_zero);
10318 %}
10319
10320 instruct storeV4S_zero(memory mem, immI0 zero) %{
10321 predicate(n->as_StoreVector()->memory_size() == 8);
10322 match(Set mem (StoreVector mem (ReplicateS zero)));
10323 ins_cost(MEMORY_REF_COST);
10324 size(4);
10325 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10326 ins_encode %{
10327 __ stx(G0, $mem$$Address);
10328 %}
10329 ins_pipe(fstoreD_mem_zero);
10330 %}
10331
10332 instruct storeV2I_zero(memory mem, immI0 zero) %{
10333 predicate(n->as_StoreVector()->memory_size() == 8);
10334 match(Set mem (StoreVector mem (ReplicateI zero)));
10335 ins_cost(MEMORY_REF_COST);
10336 size(4);
10337 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10338 ins_encode %{
10339 __ stx(G0, $mem$$Address);
10340 %}
10341 ins_pipe(fstoreD_mem_zero);
10342 %}
10343
10344 instruct storeV2F_zero(memory mem, immF0 zero) %{
10345 predicate(n->as_StoreVector()->memory_size() == 8);
10346 match(Set mem (StoreVector mem (ReplicateF zero)));
10347 ins_cost(MEMORY_REF_COST);
10348 size(4);
10349 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10350 ins_encode %{
10351 __ stx(G0, $mem$$Address);
10352 %}
10353 ins_pipe(fstoreD_mem_zero);
10354 %}
10355
10356 // Replicate scalar to packed byte values into Double register
10357 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10358 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10359 match(Set dst (ReplicateB src));
10360 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10361 format %{ "SLLX $src,56,$tmp\n\t"
10362 "SRLX $tmp, 8,$tmp2\n\t"
10363 "OR $tmp,$tmp2,$tmp\n\t"
10364 "SRLX $tmp,16,$tmp2\n\t"
10365 "OR $tmp,$tmp2,$tmp\n\t"
10366 "SRLX $tmp,32,$tmp2\n\t"
10367 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10368 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10369 ins_encode %{
10370 Register Rsrc = $src$$Register;
10371 Register Rtmp = $tmp$$Register;
10372 Register Rtmp2 = $tmp2$$Register;
10373 __ sllx(Rsrc, 56, Rtmp);
10374 __ srlx(Rtmp, 8, Rtmp2);
10375 __ or3 (Rtmp, Rtmp2, Rtmp);
10376 __ srlx(Rtmp, 16, Rtmp2);
10377 __ or3 (Rtmp, Rtmp2, Rtmp);
10378 __ srlx(Rtmp, 32, Rtmp2);
10379 __ or3 (Rtmp, Rtmp2, Rtmp);
10380 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10381 %}
10382 ins_pipe(ialu_reg);
10383 %}
10384
10385 // Replicate scalar to packed byte values into Double stack
10386 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10387 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10388 match(Set dst (ReplicateB src));
10389 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10390 format %{ "SLLX $src,56,$tmp\n\t"
10391 "SRLX $tmp, 8,$tmp2\n\t"
10392 "OR $tmp,$tmp2,$tmp\n\t"
10393 "SRLX $tmp,16,$tmp2\n\t"
10394 "OR $tmp,$tmp2,$tmp\n\t"
10395 "SRLX $tmp,32,$tmp2\n\t"
10396 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10397 "STX $tmp,$dst\t! regL to stkD" %}
10398 ins_encode %{
10399 Register Rsrc = $src$$Register;
10400 Register Rtmp = $tmp$$Register;
10401 Register Rtmp2 = $tmp2$$Register;
10402 __ sllx(Rsrc, 56, Rtmp);
10403 __ srlx(Rtmp, 8, Rtmp2);
10404 __ or3 (Rtmp, Rtmp2, Rtmp);
10405 __ srlx(Rtmp, 16, Rtmp2);
10406 __ or3 (Rtmp, Rtmp2, Rtmp);
10407 __ srlx(Rtmp, 32, Rtmp2);
10408 __ or3 (Rtmp, Rtmp2, Rtmp);
10409 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10410 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10411 %}
10412 ins_pipe(ialu_reg);
10413 %}
10414
10415 // Replicate scalar constant to packed byte values in Double register
10416 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10417 predicate(n->as_Vector()->length() == 8);
10418 match(Set dst (ReplicateB con));
10419 effect(KILL tmp);
10420 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10421 ins_encode %{
10422 // XXX This is a quick fix for 6833573.
10423 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10424 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10425 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10426 %}
10427 ins_pipe(loadConFD);
10428 %}
10429
10430 // Replicate scalar to packed char/short values into Double register
10431 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10432 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10433 match(Set dst (ReplicateS src));
10434 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10435 format %{ "SLLX $src,48,$tmp\n\t"
10436 "SRLX $tmp,16,$tmp2\n\t"
10437 "OR $tmp,$tmp2,$tmp\n\t"
10438 "SRLX $tmp,32,$tmp2\n\t"
10439 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10440 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10441 ins_encode %{
10442 Register Rsrc = $src$$Register;
10443 Register Rtmp = $tmp$$Register;
10444 Register Rtmp2 = $tmp2$$Register;
10445 __ sllx(Rsrc, 48, Rtmp);
10446 __ srlx(Rtmp, 16, Rtmp2);
10447 __ or3 (Rtmp, Rtmp2, Rtmp);
10448 __ srlx(Rtmp, 32, Rtmp2);
10449 __ or3 (Rtmp, Rtmp2, Rtmp);
10450 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10451 %}
10452 ins_pipe(ialu_reg);
10453 %}
10454
10455 // Replicate scalar to packed char/short values into Double stack
10456 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10457 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10458 match(Set dst (ReplicateS src));
10459 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10460 format %{ "SLLX $src,48,$tmp\n\t"
10461 "SRLX $tmp,16,$tmp2\n\t"
10462 "OR $tmp,$tmp2,$tmp\n\t"
10463 "SRLX $tmp,32,$tmp2\n\t"
10464 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10465 "STX $tmp,$dst\t! regL to stkD" %}
10466 ins_encode %{
10467 Register Rsrc = $src$$Register;
10468 Register Rtmp = $tmp$$Register;
10469 Register Rtmp2 = $tmp2$$Register;
10470 __ sllx(Rsrc, 48, Rtmp);
10471 __ srlx(Rtmp, 16, Rtmp2);
10472 __ or3 (Rtmp, Rtmp2, Rtmp);
10473 __ srlx(Rtmp, 32, Rtmp2);
10474 __ or3 (Rtmp, Rtmp2, Rtmp);
10475 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10476 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10477 %}
10478 ins_pipe(ialu_reg);
10479 %}
10480
10481 // Replicate scalar constant to packed char/short values in Double register
10482 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10483 predicate(n->as_Vector()->length() == 4);
10484 match(Set dst (ReplicateS con));
10485 effect(KILL tmp);
10486 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10487 ins_encode %{
10488 // XXX This is a quick fix for 6833573.
10489 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10490 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10491 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10492 %}
10493 ins_pipe(loadConFD);
10494 %}
10495
10496 // Replicate scalar to packed int values into Double register
10497 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10498 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10499 match(Set dst (ReplicateI src));
10500 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10501 format %{ "SLLX $src,32,$tmp\n\t"
10502 "SRLX $tmp,32,$tmp2\n\t"
10503 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10504 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10505 ins_encode %{
10506 Register Rsrc = $src$$Register;
10507 Register Rtmp = $tmp$$Register;
10508 Register Rtmp2 = $tmp2$$Register;
10509 __ sllx(Rsrc, 32, Rtmp);
10510 __ srlx(Rtmp, 32, Rtmp2);
10511 __ or3 (Rtmp, Rtmp2, Rtmp);
10512 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10513 %}
10514 ins_pipe(ialu_reg);
10515 %}
10516
10517 // Replicate scalar to packed int values into Double stack
10518 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10519 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10520 match(Set dst (ReplicateI src));
10521 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10522 format %{ "SLLX $src,32,$tmp\n\t"
10523 "SRLX $tmp,32,$tmp2\n\t"
10524 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10525 "STX $tmp,$dst\t! regL to stkD" %}
10526 ins_encode %{
10527 Register Rsrc = $src$$Register;
10528 Register Rtmp = $tmp$$Register;
10529 Register Rtmp2 = $tmp2$$Register;
10530 __ sllx(Rsrc, 32, Rtmp);
10531 __ srlx(Rtmp, 32, Rtmp2);
10532 __ or3 (Rtmp, Rtmp2, Rtmp);
10533 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10534 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10535 %}
10536 ins_pipe(ialu_reg);
10537 %}
10538
10539 // Replicate scalar zero constant to packed int values in Double register
10540 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10541 predicate(n->as_Vector()->length() == 2);
10542 match(Set dst (ReplicateI con));
10543 effect(KILL tmp);
10544 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10545 ins_encode %{
10546 // XXX This is a quick fix for 6833573.
10547 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10548 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10549 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10550 %}
10551 ins_pipe(loadConFD);
10552 %}
10553
10554 // Replicate scalar to packed float values into Double stack
10555 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10556 predicate(n->as_Vector()->length() == 2);
10557 match(Set dst (ReplicateF src));
10558 ins_cost(MEMORY_REF_COST*2);
10559 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10560 "STF $src,$dst.lo" %}
10561 opcode(Assembler::stf_op3);
10562 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10563 ins_pipe(fstoreF_stk_reg);
10564 %}
10565
10566 // Replicate scalar zero constant to packed float values in Double register
10567 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10568 predicate(n->as_Vector()->length() == 2);
10569 match(Set dst (ReplicateF con));
10570 effect(KILL tmp);
10571 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10572 ins_encode %{
10573 // XXX This is a quick fix for 6833573.
10574 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10575 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10576 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10577 %}
10578 ins_pipe(loadConFD);
10579 %}
10580
10581 //----------PEEPHOLE RULES-----------------------------------------------------
10582 // These must follow all instruction definitions as they use the names
10583 // defined in the instructions definitions.
10584 //
10585 // peepmatch ( root_instr_name [preceding_instruction]* );
10586 //
10587 // peepconstraint %{
10588 // (instruction_number.operand_name relational_op instruction_number.operand_name
10589 // [, ...] );
10590 // // instruction numbers are zero-based using left to right order in peepmatch
10591 //
10592 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10593 // // provide an instruction_number.operand_name for each operand that appears
10594 // // in the replacement instruction's match rule
10595 //
10596 // ---------VM FLAGS---------------------------------------------------------
10597 //
10598 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10599 //
10600 // Each peephole rule is given an identifying number starting with zero and
10601 // increasing by one in the order seen by the parser. An individual peephole
10602 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10603 // on the command-line.
10604 //
10605 // ---------CURRENT LIMITATIONS----------------------------------------------
10606 //
10607 // Only match adjacent instructions in same basic block
10608 // Only equality constraints
10609 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10610 // Only one replacement instruction
10611 //
10612 // ---------EXAMPLE----------------------------------------------------------
10613 //
10614 // // pertinent parts of existing instructions in architecture description
10615 // instruct movI(eRegI dst, eRegI src) %{
10616 // match(Set dst (CopyI src));
10617 // %}
10618 //
10619 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10620 // match(Set dst (AddI dst src));
10621 // effect(KILL cr);
10622 // %}
10623 //
10624 // // Change (inc mov) to lea
10625 // peephole %{
10626 // // increment preceeded by register-register move
10627 // peepmatch ( incI_eReg movI );
10628 // // require that the destination register of the increment
10629 // // match the destination register of the move
10630 // peepconstraint ( 0.dst == 1.dst );
10631 // // construct a replacement instruction that sets
10632 // // the destination to ( move's source register + one )
10633 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10634 // %}
10635 //
10636
10637 // // Change load of spilled value to only a spill
10638 // instruct storeI(memory mem, eRegI src) %{
10639 // match(Set mem (StoreI mem src));
10640 // %}
10641 //
10642 // instruct loadI(eRegI dst, memory mem) %{
10643 // match(Set dst (LoadI mem));
10644 // %}
10645 //
10646 // peephole %{
10647 // peepmatch ( loadI storeI );
10648 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10649 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10650 // %}
10651
10652 //----------SMARTSPILL RULES---------------------------------------------------
10653 // These must follow all instruction definitions as they use the names
10654 // defined in the instructions definitions.
10655 //
10656 // SPARC will probably not have any of these rules due to RISC instruction set.
10657
10658 //----------PIPELINE-----------------------------------------------------------
10659 // Rules which define the behavior of the target architectures pipeline.