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src/cpu/sparc/vm/templateTable_sparc.cpp
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@@ -246,16 +246,11 @@
void TemplateTable::lconst(int value) {
transition(vtos, ltos);
assert(value >= 0, "check this code");
-#ifdef _LP64
__ set(value, Otos_l);
-#else
- __ set(value, Otos_l2);
- __ clr( Otos_l1);
-#endif
}
void TemplateTable::fconst(int value) {
transition(vtos, ftos);
@@ -404,28 +399,16 @@
__ cmp_and_brx_short(O2, JVM_CONSTANT_Double, Assembler::notEqual, Assembler::pt, Long);
// A double can be placed at word-aligned locations in the constant pool.
// Check out Conversions.java for an example.
// Also ConstantPool::header_size() is 20, which makes it very difficult
// to double-align double on the constant pool. SG, 11/7/97
-#ifdef _LP64
__ ldf(FloatRegisterImpl::D, G3_scratch, base_offset, Ftos_d);
-#else
- FloatRegister f = Ftos_d;
- __ ldf(FloatRegisterImpl::S, G3_scratch, base_offset, f);
- __ ldf(FloatRegisterImpl::S, G3_scratch, base_offset + sizeof(jdouble)/2,
- f->successor());
-#endif
__ push(dtos);
__ ba_short(exit);
__ bind(Long);
-#ifdef _LP64
__ ldx(G3_scratch, base_offset, Otos_l);
-#else
- __ ld(G3_scratch, base_offset, Otos_l);
- __ ld(G3_scratch, base_offset + sizeof(jlong)/2, Otos_l->successor());
-#endif
__ push(ltos);
__ bind(exit);
}
@@ -1126,23 +1109,15 @@
void TemplateTable::lop2(Operation op) {
transition(ltos, ltos);
__ pop_l(O2);
switch (op) {
-#ifdef _LP64
case add: __ add(O2, Otos_l, Otos_l); break;
case sub: __ sub(O2, Otos_l, Otos_l); break;
case _and: __ and3(O2, Otos_l, Otos_l); break;
case _or: __ or3(O2, Otos_l, Otos_l); break;
case _xor: __ xor3(O2, Otos_l, Otos_l); break;
-#else
- case add: __ addcc(O3, Otos_l2, Otos_l2); __ addc(O2, Otos_l1, Otos_l1); break;
- case sub: __ subcc(O3, Otos_l2, Otos_l2); __ subc(O2, Otos_l1, Otos_l1); break;
- case _and: __ and3(O3, Otos_l2, Otos_l2); __ and3(O2, Otos_l1, Otos_l1); break;
- case _or: __ or3(O3, Otos_l2, Otos_l2); __ or3(O2, Otos_l1, Otos_l1); break;
- case _xor: __ xor3(O3, Otos_l2, Otos_l2); __ xor3(O2, Otos_l1, Otos_l1); break;
-#endif
default: ShouldNotReachHere();
}
}
@@ -1169,18 +1144,14 @@
const int min_int = 0x80000000;
Label regular;
__ cmp(Otos_i, -1);
__ br(Assembler::notEqual, false, Assembler::pt, regular);
-#ifdef _LP64
// Don't put set in delay slot
// Set will turn into multiple instructions in 64 bit mode
__ delayed()->nop();
__ set(min_int, G4_scratch);
-#else
- __ delayed()->set(min_int, G4_scratch);
-#endif
Label done;
__ cmp(O1, G4_scratch);
__ br(Assembler::equal, true, Assembler::pt, done);
__ delayed()->mov(O1, Otos_i); // (mov only executed if branch taken)
@@ -1200,89 +1171,61 @@
void TemplateTable::lmul() {
transition(ltos, ltos);
__ pop_l(O2);
-#ifdef _LP64
__ mulx(Otos_l, O2, Otos_l);
-#else
- __ call_VM_leaf(Lscratch, CAST_FROM_FN_PTR(address, SharedRuntime::lmul));
-#endif
}
void TemplateTable::ldiv() {
transition(ltos, ltos);
// check for zero
__ pop_l(O2);
-#ifdef _LP64
__ tst(Otos_l);
__ throw_if_not_xcc( Assembler::notZero, Interpreter::_throw_ArithmeticException_entry, G3_scratch);
__ sdivx(O2, Otos_l, Otos_l);
-#else
- __ orcc(Otos_l1, Otos_l2, G0);
- __ throw_if_not_icc( Assembler::notZero, Interpreter::_throw_ArithmeticException_entry, G3_scratch);
- __ call_VM_leaf(Lscratch, CAST_FROM_FN_PTR(address, SharedRuntime::ldiv));
-#endif
}
void TemplateTable::lrem() {
transition(ltos, ltos);
// check for zero
__ pop_l(O2);
-#ifdef _LP64
__ tst(Otos_l);
__ throw_if_not_xcc( Assembler::notZero, Interpreter::_throw_ArithmeticException_entry, G3_scratch);
__ sdivx(O2, Otos_l, Otos_l2);
__ mulx (Otos_l2, Otos_l, Otos_l2);
__ sub (O2, Otos_l2, Otos_l);
-#else
- __ orcc(Otos_l1, Otos_l2, G0);
- __ throw_if_not_icc(Assembler::notZero, Interpreter::_throw_ArithmeticException_entry, G3_scratch);
- __ call_VM_leaf(Lscratch, CAST_FROM_FN_PTR(address, SharedRuntime::lrem));
-#endif
}
void TemplateTable::lshl() {
transition(itos, ltos); // %%%% could optimize, fill delay slot or opt for ultra
__ pop_l(O2); // shift value in O2, O3
-#ifdef _LP64
__ sllx(O2, Otos_i, Otos_l);
-#else
- __ lshl(O2, O3, Otos_i, Otos_l1, Otos_l2, O4);
-#endif
}
void TemplateTable::lshr() {
transition(itos, ltos); // %%%% see lshl comment
__ pop_l(O2); // shift value in O2, O3
-#ifdef _LP64
__ srax(O2, Otos_i, Otos_l);
-#else
- __ lshr(O2, O3, Otos_i, Otos_l1, Otos_l2, O4);
-#endif
}
void TemplateTable::lushr() {
transition(itos, ltos); // %%%% see lshl comment
__ pop_l(O2); // shift value in O2, O3
-#ifdef _LP64
__ srlx(O2, Otos_i, Otos_l);
-#else
- __ lushr(O2, O3, Otos_i, Otos_l1, Otos_l2, O4);
-#endif
}
void TemplateTable::fop2(Operation op) {
transition(ftos, ftos);
@@ -1291,19 +1234,13 @@
case sub: __ pop_f(F4); __ fsub(FloatRegisterImpl::S, F4, Ftos_f, Ftos_f); break;
case mul: __ pop_f(F4); __ fmul(FloatRegisterImpl::S, F4, Ftos_f, Ftos_f); break;
case div: __ pop_f(F4); __ fdiv(FloatRegisterImpl::S, F4, Ftos_f, Ftos_f); break;
case rem:
assert(Ftos_f == F0, "just checking");
-#ifdef _LP64
// LP64 calling conventions use F1, F3 for passing 2 floats
__ pop_f(F1);
__ fmov(FloatRegisterImpl::S, Ftos_f, F3);
-#else
- __ pop_i(O0);
- __ stf(FloatRegisterImpl::S, Ftos_f, __ d_tmp);
- __ ld( __ d_tmp, O1 );
-#endif
__ call_VM_leaf(Lscratch, CAST_FROM_FN_PTR(address, SharedRuntime::frem));
assert( Ftos_f == F0, "fix this code" );
break;
default: ShouldNotReachHere();
@@ -1317,22 +1254,13 @@
case add: __ pop_d(F4); __ fadd(FloatRegisterImpl::D, F4, Ftos_d, Ftos_d); break;
case sub: __ pop_d(F4); __ fsub(FloatRegisterImpl::D, F4, Ftos_d, Ftos_d); break;
case mul: __ pop_d(F4); __ fmul(FloatRegisterImpl::D, F4, Ftos_d, Ftos_d); break;
case div: __ pop_d(F4); __ fdiv(FloatRegisterImpl::D, F4, Ftos_d, Ftos_d); break;
case rem:
-#ifdef _LP64
// Pass arguments in D0, D2
__ fmov(FloatRegisterImpl::D, Ftos_f, F2 );
__ pop_d( F0 );
-#else
- // Pass arguments in O0O1, O2O3
- __ stf(FloatRegisterImpl::D, Ftos_f, __ d_tmp);
- __ ldd( __ d_tmp, O2 );
- __ pop_d(Ftos_f);
- __ stf(FloatRegisterImpl::D, Ftos_f, __ d_tmp);
- __ ldd( __ d_tmp, O0 );
-#endif
__ call_VM_leaf(Lscratch, CAST_FROM_FN_PTR(address, SharedRuntime::drem));
assert( Ftos_d == F0, "fix this code" );
break;
default: ShouldNotReachHere();
@@ -1346,15 +1274,11 @@
}
void TemplateTable::lneg() {
transition(ltos, ltos);
-#ifdef _LP64
__ sub(G0, Otos_l, Otos_l);
-#else
- __ lneg(Otos_l1, Otos_l2);
-#endif
}
void TemplateTable::fneg() {
transition(ftos, ftos);
@@ -1435,19 +1359,12 @@
// Conversion
Label done;
switch (bytecode()) {
case Bytecodes::_i2l:
-#ifdef _LP64
// Sign extend the 32 bits
__ sra ( Otos_i, 0, Otos_l );
-#else
- __ addcc(Otos_i, 0, Otos_l2);
- __ br(Assembler::greaterEqual, true, Assembler::pt, done);
- __ delayed()->clr(Otos_l1);
- __ set(~0, Otos_l1);
-#endif
break;
case Bytecodes::_i2f:
__ st(Otos_i, __ d_tmp );
__ ldf(FloatRegisterImpl::S, __ d_tmp, F0);
@@ -1474,16 +1391,12 @@
__ sll(Otos_i, 16, Otos_i);
__ sra(Otos_i, 16, Otos_i);
break;
case Bytecodes::_l2i:
-#ifndef _LP64
- __ mov(Otos_l2, Otos_i);
-#else
// Sign-extend into the high 32 bits
__ sra(Otos_l, 0, Otos_i);
-#endif
break;
case Bytecodes::_l2f:
case Bytecodes::_l2d:
__ st_long(Otos_l, __ d_tmp);
@@ -1510,15 +1423,11 @@
break;
case Bytecodes::_f2l:
// must uncache tos
__ push_f();
-#ifdef _LP64
__ pop_f(F1);
-#else
- __ pop_i(O0);
-#endif
__ call_VM_leaf(Lscratch, CAST_FROM_FN_PTR(address, SharedRuntime::f2l));
break;
case Bytecodes::_f2d:
__ ftof( FloatRegisterImpl::S, FloatRegisterImpl::D, Ftos_f, Ftos_f);
@@ -1526,17 +1435,12 @@
case Bytecodes::_d2i:
case Bytecodes::_d2l:
// must uncache tos
__ push_d();
-#ifdef _LP64
// LP64 calling conventions pass first double arg in D0
__ pop_d( Ftos_d );
-#else
- __ pop_i( O0 );
- __ pop_i( O1 );
-#endif
__ call_VM_leaf(Lscratch,
bytecode() == Bytecodes::_d2i
? CAST_FROM_FN_PTR(address, SharedRuntime::d2i)
: CAST_FROM_FN_PTR(address, SharedRuntime::d2l));
break;
@@ -1552,17 +1456,12 @@
void TemplateTable::lcmp() {
transition(ltos, itos);
-#ifdef _LP64
__ pop_l(O1); // pop off value 1, value 2 is in O0
__ lcmp( O1, Otos_l, Otos_i );
-#else
- __ pop_l(O2); // cmp O2,3 to O0,1
- __ lcmp( O2, O3, Otos_l1, Otos_l2, Otos_i );
-#endif
}
void TemplateTable::float_cmp(bool is_float, int unordered_result) {
@@ -1754,11 +1653,10 @@
transition(vtos, vtos);
locals_index(G3_scratch);
__ access_local_returnAddress(G3_scratch, Otos_i);
// Otos_i contains the bci, compute the bcp from that
-#ifdef _LP64
#ifdef ASSERT
// jsr result was labeled as an 'itos' not an 'atos' because we cannot GC
// the result. The return address (really a BCI) was stored with an
// 'astore' because JVM specs claim it's a pointer-sized thing. Hence in
// the 64-bit build the 32-bit BCI is actually in the low bits of a 64-bit
@@ -1770,11 +1668,10 @@
__ delayed()->nop();
__ stop("BCI is in the wrong register half?");
__ bind (zzz) ;
}
#endif
-#endif
__ profile_ret(vtos, Otos_i, G4_scratch);
__ ld_ptr(Lmethod, Method::const_offset(), G3_scratch);
__ add(G3_scratch, Otos_i, G3_scratch);
@@ -1806,14 +1703,12 @@
__ add(Lbcp, BytesPerInt, O1);
__ and3(O1, -BytesPerInt, O1);
// load lo, hi
__ ld(O1, 1 * BytesPerInt, O2); // Low Byte
__ ld(O1, 2 * BytesPerInt, O3); // High Byte
-#ifdef _LP64
// Sign extend the 32 bits
__ sra ( Otos_i, 0, Otos_i );
-#endif /* _LP64 */
// check against lo & hi
__ cmp( Otos_i, O2);
__ br( Assembler::less, false, Assembler::pn, default_case);
__ delayed()->cmp( Otos_i, O3 );
@@ -3398,15 +3293,11 @@
if (allow_shared_alloc) {
// Check if tlab should be discarded (refill_waste_limit >= free)
__ ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), RtlabWasteLimitValue);
__ sub(RendValue, RoldTopValue, RfreeValue);
-#ifdef _LP64
__ srlx(RfreeValue, LogHeapWordSize, RfreeValue);
-#else
- __ srl(RfreeValue, LogHeapWordSize, RfreeValue);
-#endif
__ cmp_and_brx_short(RtlabWasteLimitValue, RfreeValue, Assembler::greaterEqualUnsigned, Assembler::pt, slow_case); // tlab waste is small
// increment waste limit to prevent getting stuck on this slow path
if (Assembler::is_simm13(ThreadLocalAllocBuffer::refill_waste_limit_increment())) {
__ add(RtlabWasteLimitValue, ThreadLocalAllocBuffer::refill_waste_limit_increment(), RtlabWasteLimitValue);
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