1 /*
2 * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2013 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
452
453 FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM
454 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM
455
456 // Vector instruction support for >= Power6
457 // Vector Storage Access
458 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1),
459 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1),
460 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1),
461 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1),
462 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1),
463 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1),
464 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1),
465 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1),
466 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1),
467 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1),
468 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1),
469 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
470
471 // Vector-Scalar (VSX) instruction support.
472 MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
473 MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1),
474
475 // Vector Permute and Formatting
476 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
477 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ),
478 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ),
479 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ),
480 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ),
481 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ),
482 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ),
483 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ),
484 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ),
485 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ),
486 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ),
487 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ),
488 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ),
489 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ),
490 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ),
491
653
654 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1),
655 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1),
656 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1),
657
658 // Instruction synchronization
659 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1),
660 // Memory barriers
661 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1),
662 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1),
663
664 // Trap instructions
665 TDI_OPCODE = (2u << OPCODE_SHIFT),
666 TWI_OPCODE = (3u << OPCODE_SHIFT),
667 TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1),
668 TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1),
669
670 // Atomics.
671 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1),
672 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1),
673 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1),
674 STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1)
675
676 };
677
678 // Trap instructions TO bits
679 enum trap_to_bits {
680 // single bits
681 traptoLessThanSigned = 1 << 4, // 0, left end
682 traptoGreaterThanSigned = 1 << 3,
683 traptoEqual = 1 << 2,
684 traptoLessThanUnsigned = 1 << 1,
685 traptoGreaterThanUnsigned = 1 << 0, // 4, right end
686
687 // compound ones
688 traptoUnconditional = (traptoLessThanSigned |
689 traptoGreaterThanSigned |
690 traptoEqual |
691 traptoLessThanUnsigned |
692 traptoGreaterThanUnsigned)
693 };
694
1035 static int th( int x) { return opp_u_field(x, 10, 7); }
1036 static int thct( int x) { assert((x&8) == 0, "must be valid cache specification"); return th(x); }
1037 static int thds( int x) { assert((x&8) == 8, "must be valid stream specification"); return th(x); }
1038 static int to( int x) { return opp_u_field(x, 10, 6); }
1039 static int u( int x) { return opp_u_field(x, 19, 16); }
1040 static int ui( int x) { return opp_u_field(x, 31, 16); }
1041
1042 // Support vector instructions for >= Power6.
1043 static int vra( int x) { return opp_u_field(x, 15, 11); }
1044 static int vrb( int x) { return opp_u_field(x, 20, 16); }
1045 static int vrc( int x) { return opp_u_field(x, 25, 21); }
1046 static int vrs( int x) { return opp_u_field(x, 10, 6); }
1047 static int vrt( int x) { return opp_u_field(x, 10, 6); }
1048
1049 static int vra( VectorRegister r) { return vra(r->encoding());}
1050 static int vrb( VectorRegister r) { return vrb(r->encoding());}
1051 static int vrc( VectorRegister r) { return vrc(r->encoding());}
1052 static int vrs( VectorRegister r) { return vrs(r->encoding());}
1053 static int vrt( VectorRegister r) { return vrt(r->encoding());}
1054
1055 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions
1056 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions
1057 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction
1058 static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions
1059
1060 //static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes
1061 //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes
1062 //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes
1063 //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes
1064 //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes
1065 //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes
1066 //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes
1067
1068 protected:
1069 // Compute relative address for branch.
1070 static intptr_t disp(intptr_t x, intptr_t off) {
1071 int xx = x - off;
1072 xx = xx >> 2;
1073 return xx;
1074 }
1646 // - acquire orders Load|Store, (maps to lwsync)
1647 // Load|Load
1648 // - fence orders Store|Store, (maps to sync)
1649 // Load|Store,
1650 // Load|Load,
1651 // Store|Load
1652 //
1653 private:
1654 inline void sync(int l);
1655 public:
1656 inline void sync();
1657 inline void lwsync();
1658 inline void ptesync();
1659 inline void eieio();
1660 inline void isync();
1661 inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8)
1662
1663 // atomics
1664 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1665 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1666 inline bool lxarx_hint_exclusive_access();
1667 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1668 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1669 inline void stwcx_( Register s, Register a, Register b);
1670 inline void stdcx_( Register s, Register a, Register b);
1671
1672 // Instructions for adjusting thread priority for simultaneous
1673 // multithreading (SMT) on Power5.
1674 private:
1675 inline void smt_prio_very_low();
1676 inline void smt_prio_medium_high();
1677 inline void smt_prio_high();
1678
1679 public:
1680 inline void smt_prio_low();
1681 inline void smt_prio_medium_low();
1682 inline void smt_prio_medium();
1683
1684 // trap instructions
1685 inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur)
1686 // NOT FOR DIRECT USE!!
1687 protected:
1688 inline void tdi_unchecked(int tobits, Register a, int si16);
1689 inline void twi_unchecked(int tobits, Register a, int si16);
1690 inline void tdi( int tobits, Register a, int si16); // asserts UseSIGTRAP
1926 inline void vor( VectorRegister d, VectorRegister a, VectorRegister b);
1927 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b);
1928 inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b);
1929 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b);
1930 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b);
1931 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b);
1932 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b);
1933 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b);
1934 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b);
1935 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b);
1936 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b);
1937 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b);
1938 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b);
1939 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b);
1940 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
1941 // Vector Floating-Point not implemented yet
1942 inline void mtvscr( VectorRegister b);
1943 inline void mfvscr( VectorRegister d);
1944
1945 // Vector-Scalar (VSX) instructions.
1946 inline void mtvrd( VectorRegister d, Register a);
1947 inline void mfvrd( Register a, VectorRegister d);
1948
1949 // AES (introduced with Power 8)
1950 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
1951 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
1952 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b);
1953 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
1954 inline void vsbox( VectorRegister d, VectorRegister a);
1955
1956 // SHA (introduced with Power 8)
1957 // Not yet implemented.
1958
1959 // Vector Binary Polynomial Multiplication (introduced with Power 8)
1960 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b);
1961 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b);
1962 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b);
1963 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b);
1964
1965 // Vector Permute and Xor (introduced with Power 8)
2005 inline void std( Register d, int si16);
2006
2007 // PPC 2, section 3.2.1 Instruction Cache Instructions
2008 inline void icbi( Register s2);
2009 // PPC 2, section 3.2.2 Data Cache Instructions
2010 //inlinevoid dcba( Register s2); // Instruction for embedded processor only.
2011 inline void dcbz( Register s2);
2012 inline void dcbst( Register s2);
2013 inline void dcbf( Register s2);
2014 // dcache read hint
2015 inline void dcbt( Register s2);
2016 inline void dcbtct( Register s2, int ct);
2017 inline void dcbtds( Register s2, int ds);
2018 // dcache write hint
2019 inline void dcbtst( Register s2);
2020 inline void dcbtstct(Register s2, int ct);
2021
2022 // Atomics: use ra0mem to disallow R0 as base.
2023 inline void lwarx_unchecked(Register d, Register b, int eh1);
2024 inline void ldarx_unchecked(Register d, Register b, int eh1);
2025 inline void lwarx( Register d, Register b, bool hint_exclusive_access);
2026 inline void ldarx( Register d, Register b, bool hint_exclusive_access);
2027 inline void stwcx_(Register s, Register b);
2028 inline void stdcx_(Register s, Register b);
2029 inline void lfs( FloatRegister d, int si16);
2030 inline void lfsx( FloatRegister d, Register b);
2031 inline void lfd( FloatRegister d, int si16);
2032 inline void lfdx( FloatRegister d, Register b);
2033 inline void stfs( FloatRegister s, int si16);
2034 inline void stfsx( FloatRegister s, Register b);
2035 inline void stfd( FloatRegister s, int si16);
2036 inline void stfdx( FloatRegister s, Register b);
2037 inline void lvebx( VectorRegister d, Register s2);
2038 inline void lvehx( VectorRegister d, Register s2);
2039 inline void lvewx( VectorRegister d, Register s2);
2040 inline void lvx( VectorRegister d, Register s2);
2041 inline void lvxl( VectorRegister d, Register s2);
2042 inline void stvebx(VectorRegister d, Register s2);
2043 inline void stvehx(VectorRegister d, Register s2);
2044 inline void stvewx(VectorRegister d, Register s2);
2045 inline void stvx( VectorRegister d, Register s2);
2046 inline void stvxl( VectorRegister d, Register s2);
2047 inline void lvsl( VectorRegister d, Register s2);
2048 inline void lvsr( VectorRegister d, Register s2);
|
1 /*
2 * Copyright (c) 2002, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2018 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
452
453 FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM
454 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM
455
456 // Vector instruction support for >= Power6
457 // Vector Storage Access
458 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1),
459 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1),
460 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1),
461 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1),
462 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1),
463 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1),
464 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1),
465 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1),
466 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1),
467 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1),
468 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1),
469 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
470
471 // Vector-Scalar (VSX) instruction support.
472 LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
473 STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
474 MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
475 MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1),
476
477 // Vector Permute and Formatting
478 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
479 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ),
480 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ),
481 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ),
482 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ),
483 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ),
484 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ),
485 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ),
486 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ),
487 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ),
488 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ),
489 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ),
490 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ),
491 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ),
492 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ),
493
655
656 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1),
657 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1),
658 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1),
659
660 // Instruction synchronization
661 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1),
662 // Memory barriers
663 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1),
664 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1),
665
666 // Trap instructions
667 TDI_OPCODE = (2u << OPCODE_SHIFT),
668 TWI_OPCODE = (3u << OPCODE_SHIFT),
669 TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1),
670 TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1),
671
672 // Atomics.
673 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1),
674 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1),
675 LQARX_OPCODE = (31u << OPCODE_SHIFT | 276u << 1),
676 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1),
677 STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1),
678 STQCX_OPCODE = (31u << OPCODE_SHIFT | 182u << 1)
679
680 };
681
682 // Trap instructions TO bits
683 enum trap_to_bits {
684 // single bits
685 traptoLessThanSigned = 1 << 4, // 0, left end
686 traptoGreaterThanSigned = 1 << 3,
687 traptoEqual = 1 << 2,
688 traptoLessThanUnsigned = 1 << 1,
689 traptoGreaterThanUnsigned = 1 << 0, // 4, right end
690
691 // compound ones
692 traptoUnconditional = (traptoLessThanSigned |
693 traptoGreaterThanSigned |
694 traptoEqual |
695 traptoLessThanUnsigned |
696 traptoGreaterThanUnsigned)
697 };
698
1039 static int th( int x) { return opp_u_field(x, 10, 7); }
1040 static int thct( int x) { assert((x&8) == 0, "must be valid cache specification"); return th(x); }
1041 static int thds( int x) { assert((x&8) == 8, "must be valid stream specification"); return th(x); }
1042 static int to( int x) { return opp_u_field(x, 10, 6); }
1043 static int u( int x) { return opp_u_field(x, 19, 16); }
1044 static int ui( int x) { return opp_u_field(x, 31, 16); }
1045
1046 // Support vector instructions for >= Power6.
1047 static int vra( int x) { return opp_u_field(x, 15, 11); }
1048 static int vrb( int x) { return opp_u_field(x, 20, 16); }
1049 static int vrc( int x) { return opp_u_field(x, 25, 21); }
1050 static int vrs( int x) { return opp_u_field(x, 10, 6); }
1051 static int vrt( int x) { return opp_u_field(x, 10, 6); }
1052
1053 static int vra( VectorRegister r) { return vra(r->encoding());}
1054 static int vrb( VectorRegister r) { return vrb(r->encoding());}
1055 static int vrc( VectorRegister r) { return vrc(r->encoding());}
1056 static int vrs( VectorRegister r) { return vrs(r->encoding());}
1057 static int vrt( VectorRegister r) { return vrt(r->encoding());}
1058
1059 // Support Vector-Scalar (VSX) instructions.
1060 static int vsra( int x) { return opp_u_field(x, 15, 11); }
1061 static int vsrb( int x) { return opp_u_field(x, 20, 16); }
1062 static int vsrc( int x) { return opp_u_field(x, 25, 21); }
1063 static int vsrs( int x) { return opp_u_field(x, 10, 6); }
1064 static int vsrt( int x) { return opp_u_field(x, 10, 6); }
1065
1066 static int vsra( VectorSRegister r) { return vsra(r->encoding());}
1067 static int vsrb( VectorSRegister r) { return vsrb(r->encoding());}
1068 static int vsrc( VectorSRegister r) { return vsrc(r->encoding());}
1069 static int vsrs( VectorSRegister r) { return vsrs(r->encoding());}
1070 static int vsrt( VectorSRegister r) { return vsrt(r->encoding());}
1071
1072 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions
1073 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions
1074 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction
1075 static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions
1076
1077 //static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes
1078 //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes
1079 //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes
1080 //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes
1081 //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes
1082 //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes
1083 //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes
1084
1085 protected:
1086 // Compute relative address for branch.
1087 static intptr_t disp(intptr_t x, intptr_t off) {
1088 int xx = x - off;
1089 xx = xx >> 2;
1090 return xx;
1091 }
1663 // - acquire orders Load|Store, (maps to lwsync)
1664 // Load|Load
1665 // - fence orders Store|Store, (maps to sync)
1666 // Load|Store,
1667 // Load|Load,
1668 // Store|Load
1669 //
1670 private:
1671 inline void sync(int l);
1672 public:
1673 inline void sync();
1674 inline void lwsync();
1675 inline void ptesync();
1676 inline void eieio();
1677 inline void isync();
1678 inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8)
1679
1680 // atomics
1681 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1682 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1683 inline void lqarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1684 inline bool lxarx_hint_exclusive_access();
1685 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1686 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1687 inline void lqarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1688 inline void stwcx_( Register s, Register a, Register b);
1689 inline void stdcx_( Register s, Register a, Register b);
1690 inline void stqcx_( Register s, Register a, Register b);
1691
1692 // Instructions for adjusting thread priority for simultaneous
1693 // multithreading (SMT) on Power5.
1694 private:
1695 inline void smt_prio_very_low();
1696 inline void smt_prio_medium_high();
1697 inline void smt_prio_high();
1698
1699 public:
1700 inline void smt_prio_low();
1701 inline void smt_prio_medium_low();
1702 inline void smt_prio_medium();
1703
1704 // trap instructions
1705 inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur)
1706 // NOT FOR DIRECT USE!!
1707 protected:
1708 inline void tdi_unchecked(int tobits, Register a, int si16);
1709 inline void twi_unchecked(int tobits, Register a, int si16);
1710 inline void tdi( int tobits, Register a, int si16); // asserts UseSIGTRAP
1946 inline void vor( VectorRegister d, VectorRegister a, VectorRegister b);
1947 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b);
1948 inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b);
1949 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b);
1950 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b);
1951 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b);
1952 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b);
1953 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b);
1954 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b);
1955 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b);
1956 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b);
1957 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b);
1958 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b);
1959 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b);
1960 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
1961 // Vector Floating-Point not implemented yet
1962 inline void mtvscr( VectorRegister b);
1963 inline void mfvscr( VectorRegister d);
1964
1965 // Vector-Scalar (VSX) instructions.
1966 inline void lxvd2x( VectorSRegister d, Register a, Register b);
1967 inline void stxvd2x( VectorSRegister d, Register a, Register b);
1968 inline void mtvrd( VectorRegister d, Register a);
1969 inline void mfvrd( Register a, VectorRegister d);
1970
1971 // AES (introduced with Power 8)
1972 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
1973 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
1974 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b);
1975 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
1976 inline void vsbox( VectorRegister d, VectorRegister a);
1977
1978 // SHA (introduced with Power 8)
1979 // Not yet implemented.
1980
1981 // Vector Binary Polynomial Multiplication (introduced with Power 8)
1982 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b);
1983 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b);
1984 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b);
1985 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b);
1986
1987 // Vector Permute and Xor (introduced with Power 8)
2027 inline void std( Register d, int si16);
2028
2029 // PPC 2, section 3.2.1 Instruction Cache Instructions
2030 inline void icbi( Register s2);
2031 // PPC 2, section 3.2.2 Data Cache Instructions
2032 //inlinevoid dcba( Register s2); // Instruction for embedded processor only.
2033 inline void dcbz( Register s2);
2034 inline void dcbst( Register s2);
2035 inline void dcbf( Register s2);
2036 // dcache read hint
2037 inline void dcbt( Register s2);
2038 inline void dcbtct( Register s2, int ct);
2039 inline void dcbtds( Register s2, int ds);
2040 // dcache write hint
2041 inline void dcbtst( Register s2);
2042 inline void dcbtstct(Register s2, int ct);
2043
2044 // Atomics: use ra0mem to disallow R0 as base.
2045 inline void lwarx_unchecked(Register d, Register b, int eh1);
2046 inline void ldarx_unchecked(Register d, Register b, int eh1);
2047 inline void lqarx_unchecked(Register d, Register b, int eh1);
2048 inline void lwarx( Register d, Register b, bool hint_exclusive_access);
2049 inline void ldarx( Register d, Register b, bool hint_exclusive_access);
2050 inline void lqarx( Register d, Register b, bool hint_exclusive_access);
2051 inline void stwcx_(Register s, Register b);
2052 inline void stdcx_(Register s, Register b);
2053 inline void stqcx_(Register s, Register b);
2054 inline void lfs( FloatRegister d, int si16);
2055 inline void lfsx( FloatRegister d, Register b);
2056 inline void lfd( FloatRegister d, int si16);
2057 inline void lfdx( FloatRegister d, Register b);
2058 inline void stfs( FloatRegister s, int si16);
2059 inline void stfsx( FloatRegister s, Register b);
2060 inline void stfd( FloatRegister s, int si16);
2061 inline void stfdx( FloatRegister s, Register b);
2062 inline void lvebx( VectorRegister d, Register s2);
2063 inline void lvehx( VectorRegister d, Register s2);
2064 inline void lvewx( VectorRegister d, Register s2);
2065 inline void lvx( VectorRegister d, Register s2);
2066 inline void lvxl( VectorRegister d, Register s2);
2067 inline void stvebx(VectorRegister d, Register s2);
2068 inline void stvehx(VectorRegister d, Register s2);
2069 inline void stvewx(VectorRegister d, Register s2);
2070 inline void stvx( VectorRegister d, Register s2);
2071 inline void stvxl( VectorRegister d, Register s2);
2072 inline void lvsl( VectorRegister d, Register s2);
2073 inline void lvsr( VectorRegister d, Register s2);
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