1 /* 2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. 3 * Copyright 2012, 2018 SAP AG. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "asm/macroAssembler.inline.hpp" 29 #include "compiler/disassembler.hpp" 30 #include "memory/resourceArea.hpp" 31 #include "runtime/java.hpp" 32 #include "runtime/stubCodeGenerator.hpp" 33 #include "utilities/defaultStream.hpp" 34 #include "vm_version_ppc.hpp" 35 #ifdef TARGET_OS_FAMILY_aix 36 # include "os_aix.inline.hpp" 37 #endif 38 #ifdef TARGET_OS_FAMILY_linux 39 # include "os_linux.inline.hpp" 40 #endif 41 42 # include <sys/sysinfo.h> 43 44 int VM_Version::_features = VM_Version::unknown_m; 45 int VM_Version::_measured_cache_line_size = 128; // default value 46 const char* VM_Version::_features_str = ""; 47 bool VM_Version::_is_determine_features_test_running = false; 48 uint64_t VM_Version::_dscr_val = 0; 49 50 #define MSG(flag) \ 51 if (flag && !FLAG_IS_DEFAULT(flag)) \ 52 jio_fprintf(defaultStream::error_stream(), \ 53 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \ 54 " -XX:+" #flag " will be disabled!\n"); 55 56 void VM_Version::initialize() { 57 58 // Test which instructions are supported and measure cache line size. 59 determine_features(); 60 61 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features. 62 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) { 63 if (VM_Version::has_lqarx()) { 64 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8); 65 } else if (VM_Version::has_popcntw()) { 66 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7); 67 } else if (VM_Version::has_cmpb()) { 68 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6); 69 } else if (VM_Version::has_popcntb()) { 70 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5); 71 } else { 72 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0); 73 } 74 } 75 guarantee(PowerArchitecturePPC64 == 0 || PowerArchitecturePPC64 == 5 || 76 PowerArchitecturePPC64 == 6 || PowerArchitecturePPC64 == 7 || 77 PowerArchitecturePPC64 == 8, 78 "PowerArchitecturePPC64 should be 0, 5, 6, 7, or 8"); 79 80 // Power 8: Configure Data Stream Control Register. 81 if (PowerArchitecturePPC64 >= 8) { 82 config_dscr(); 83 } 84 85 if (!UseSIGTRAP) { 86 MSG(TrapBasedICMissChecks); 87 MSG(TrapBasedNotEntrantChecks); 88 MSG(TrapBasedNullChecks); 89 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false); 90 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false); 91 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false); 92 } 93 94 #ifdef COMPILER2 95 if (!UseSIGTRAP) { 96 MSG(TrapBasedRangeChecks); 97 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false); 98 } 99 100 // On Power6 test for section size. 101 if (PowerArchitecturePPC64 == 6) { 102 determine_section_size(); 103 // TODO: PPC port } else { 104 // TODO: PPC port PdScheduling::power6SectorSize = 0x20; 105 } 106 107 MaxVectorSize = 8; 108 #endif 109 110 // Create and print feature-string. 111 char buf[(num_features+1) * 16]; // Max 16 chars per feature. 112 jio_snprintf(buf, sizeof(buf), 113 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s", 114 (has_fsqrt() ? " fsqrt" : ""), 115 (has_isel() ? " isel" : ""), 116 (has_lxarxeh() ? " lxarxeh" : ""), 117 (has_cmpb() ? " cmpb" : ""), 118 //(has_mftgpr()? " mftgpr" : ""), 119 (has_popcntb() ? " popcntb" : ""), 120 (has_popcntw() ? " popcntw" : ""), 121 (has_fcfids() ? " fcfids" : ""), 122 (has_vand() ? " vand" : ""), 123 (has_lqarx() ? " lqarx" : ""), 124 (has_vcipher() ? " aes" : ""), 125 (has_vpmsumb() ? " vpmsumb" : ""), 126 (has_mfdscr() ? " mfdscr" : ""), 127 (has_vsx() ? " vsx" : "") 128 // Make sure number of %s matches num_features! 129 ); 130 _features_str = strdup(buf); 131 if (Verbose) { 132 print_features(); 133 } 134 135 // PPC64 supports 8-byte compare-exchange operations (see 136 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr) 137 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile). 138 _supports_cx8 = true; 139 140 UseSSE = 0; // Only on x86 and x64 141 142 intx cache_line_size = _measured_cache_line_size; 143 144 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1; 145 146 if (AllocatePrefetchStyle == 4) { 147 AllocatePrefetchStepSize = cache_line_size; // Need exact value. 148 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default. 149 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined? 150 } else { 151 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size; 152 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value. 153 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined? 154 } 155 156 assert(AllocatePrefetchLines > 0, "invalid value"); 157 if (AllocatePrefetchLines < 1) { // Set valid value in product VM. 158 AllocatePrefetchLines = 1; // Conservative value. 159 } 160 161 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) { 162 AllocatePrefetchStyle = 1; // Fall back if inappropriate. 163 } 164 165 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); 166 167 // Implementation does not use any of the vector instructions 168 // available with Power8. Their exploitation is still pending. 169 if (!UseCRC32Intrinsics) { 170 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 171 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true); 172 } 173 } 174 175 // The AES intrinsic stubs require AES instruction support. 176 #if defined(VM_LITTLE_ENDIAN) 177 if (has_vcipher()) { 178 if (FLAG_IS_DEFAULT(UseAES)) { 179 UseAES = true; 180 } 181 } else if (UseAES) { 182 if (!FLAG_IS_DEFAULT(UseAES)) 183 warning("AES instructions are not available on this CPU"); 184 FLAG_SET_DEFAULT(UseAES, false); 185 } 186 187 if (UseAES && has_vcipher()) { 188 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { 189 UseAESIntrinsics = true; 190 } 191 } else if (UseAESIntrinsics) { 192 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) 193 warning("AES intrinsics are not available on this CPU"); 194 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 195 } 196 197 #else 198 if (UseAES) { 199 warning("AES instructions are not available on this CPU"); 200 FLAG_SET_DEFAULT(UseAES, false); 201 } 202 if (UseAESIntrinsics) { 203 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) 204 warning("AES intrinsics are not available on this CPU"); 205 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 206 } 207 #endif 208 209 if (UseSHA) { 210 warning("SHA instructions are not available on this CPU"); 211 FLAG_SET_DEFAULT(UseSHA, false); 212 } 213 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) { 214 warning("SHA intrinsics are not available on this CPU"); 215 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 216 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 217 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 218 } 219 220 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { 221 UseMontgomeryMultiplyIntrinsic = true; 222 } 223 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { 224 UseMontgomerySquareIntrinsic = true; 225 } 226 } 227 228 void VM_Version::print_features() { 229 tty->print_cr("Version: %s cache_line_size = %d", cpu_features(), (int) get_cache_line_size()); 230 } 231 232 #ifdef COMPILER2 233 // Determine section size on power6: If section size is 8 instructions, 234 // there should be a difference between the two testloops of ~15 %. If 235 // no difference is detected the section is assumed to be 32 instructions. 236 void VM_Version::determine_section_size() { 237 238 int unroll = 80; 239 240 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord; 241 242 // Allocate space for the code. 243 ResourceMark rm; 244 CodeBuffer cb("detect_section_size", code_size, 0); 245 MacroAssembler* a = new MacroAssembler(&cb); 246 247 uint32_t *code = (uint32_t *)a->pc(); 248 // Emit code. 249 void (*test1)() = (void(*)())(void *)a->function_entry(); 250 251 Label l1; 252 253 a->li(R4, 1); 254 a->sldi(R4, R4, 28); 255 a->b(l1); 256 a->align(CodeEntryAlignment); 257 258 a->bind(l1); 259 260 for (int i = 0; i < unroll; i++) { 261 // Schleife 1 262 // ------- sector 0 ------------ 263 // ;; 0 264 a->nop(); // 1 265 a->fpnop0(); // 2 266 a->fpnop1(); // 3 267 a->addi(R4,R4, -1); // 4 268 269 // ;; 1 270 a->nop(); // 5 271 a->fmr(F6, F6); // 6 272 a->fmr(F7, F7); // 7 273 a->endgroup(); // 8 274 // ------- sector 8 ------------ 275 276 // ;; 2 277 a->nop(); // 9 278 a->nop(); // 10 279 a->fmr(F8, F8); // 11 280 a->fmr(F9, F9); // 12 281 282 // ;; 3 283 a->nop(); // 13 284 a->fmr(F10, F10); // 14 285 a->fmr(F11, F11); // 15 286 a->endgroup(); // 16 287 // -------- sector 16 ------------- 288 289 // ;; 4 290 a->nop(); // 17 291 a->nop(); // 18 292 a->fmr(F15, F15); // 19 293 a->fmr(F16, F16); // 20 294 295 // ;; 5 296 a->nop(); // 21 297 a->fmr(F17, F17); // 22 298 a->fmr(F18, F18); // 23 299 a->endgroup(); // 24 300 // ------- sector 24 ------------ 301 302 // ;; 6 303 a->nop(); // 25 304 a->nop(); // 26 305 a->fmr(F19, F19); // 27 306 a->fmr(F20, F20); // 28 307 308 // ;; 7 309 a->nop(); // 29 310 a->fmr(F21, F21); // 30 311 a->fmr(F22, F22); // 31 312 a->brnop0(); // 32 313 314 // ------- sector 32 ------------ 315 } 316 317 // ;; 8 318 a->cmpdi(CCR0, R4, unroll); // 33 319 a->bge(CCR0, l1); // 34 320 a->blr(); 321 322 // Emit code. 323 void (*test2)() = (void(*)())(void *)a->function_entry(); 324 // uint32_t *code = (uint32_t *)a->pc(); 325 326 Label l2; 327 328 a->li(R4, 1); 329 a->sldi(R4, R4, 28); 330 a->b(l2); 331 a->align(CodeEntryAlignment); 332 333 a->bind(l2); 334 335 for (int i = 0; i < unroll; i++) { 336 // Schleife 2 337 // ------- sector 0 ------------ 338 // ;; 0 339 a->brnop0(); // 1 340 a->nop(); // 2 341 //a->cmpdi(CCR0, R4, unroll); 342 a->fpnop0(); // 3 343 a->fpnop1(); // 4 344 a->addi(R4,R4, -1); // 5 345 346 // ;; 1 347 348 a->nop(); // 6 349 a->fmr(F6, F6); // 7 350 a->fmr(F7, F7); // 8 351 // ------- sector 8 --------------- 352 353 // ;; 2 354 a->endgroup(); // 9 355 356 // ;; 3 357 a->nop(); // 10 358 a->nop(); // 11 359 a->fmr(F8, F8); // 12 360 361 // ;; 4 362 a->fmr(F9, F9); // 13 363 a->nop(); // 14 364 a->fmr(F10, F10); // 15 365 366 // ;; 5 367 a->fmr(F11, F11); // 16 368 // -------- sector 16 ------------- 369 370 // ;; 6 371 a->endgroup(); // 17 372 373 // ;; 7 374 a->nop(); // 18 375 a->nop(); // 19 376 a->fmr(F15, F15); // 20 377 378 // ;; 8 379 a->fmr(F16, F16); // 21 380 a->nop(); // 22 381 a->fmr(F17, F17); // 23 382 383 // ;; 9 384 a->fmr(F18, F18); // 24 385 // -------- sector 24 ------------- 386 387 // ;; 10 388 a->endgroup(); // 25 389 390 // ;; 11 391 a->nop(); // 26 392 a->nop(); // 27 393 a->fmr(F19, F19); // 28 394 395 // ;; 12 396 a->fmr(F20, F20); // 29 397 a->nop(); // 30 398 a->fmr(F21, F21); // 31 399 400 // ;; 13 401 a->fmr(F22, F22); // 32 402 } 403 404 // -------- sector 32 ------------- 405 // ;; 14 406 a->cmpdi(CCR0, R4, unroll); // 33 407 a->bge(CCR0, l2); // 34 408 409 a->blr(); 410 uint32_t *code_end = (uint32_t *)a->pc(); 411 a->flush(); 412 413 double loop1_seconds,loop2_seconds, rel_diff; 414 uint64_t start1, stop1; 415 416 start1 = os::current_thread_cpu_time(false); 417 (*test1)(); 418 stop1 = os::current_thread_cpu_time(false); 419 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0); 420 421 422 start1 = os::current_thread_cpu_time(false); 423 (*test2)(); 424 stop1 = os::current_thread_cpu_time(false); 425 426 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0); 427 428 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100; 429 430 if (PrintAssembly) { 431 ttyLocker ttyl; 432 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 433 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 434 tty->print_cr("Time loop1 :%f", loop1_seconds); 435 tty->print_cr("Time loop2 :%f", loop2_seconds); 436 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff); 437 438 if (rel_diff > 12.0) { 439 tty->print_cr("Section Size 8 Instructions"); 440 } else{ 441 tty->print_cr("Section Size 32 Instructions or Power5"); 442 } 443 } 444 445 #if 0 // TODO: PPC port 446 // Set sector size (if not set explicitly). 447 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) { 448 if (rel_diff > 12.0) { 449 PdScheduling::power6SectorSize = 0x20; 450 } else { 451 PdScheduling::power6SectorSize = 0x80; 452 } 453 } else if (Power6SectorSize128PPC64) { 454 PdScheduling::power6SectorSize = 0x80; 455 } else { 456 PdScheduling::power6SectorSize = 0x20; 457 } 458 #endif 459 if (UsePower6SchedulerPPC64) Unimplemented(); 460 } 461 #endif // COMPILER2 462 463 void VM_Version::determine_features() { 464 #if defined(ABI_ELFv2) 465 const int code_size = (num_features+1+2*7)*BytesPerInstWord; // TODO(asmundak): calculation is incorrect. 466 #else 467 // 7 InstWords for each call (function descriptor + blr instruction). 468 const int code_size = (num_features+1+2*7)*BytesPerInstWord; 469 #endif 470 int features = 0; 471 472 // create test area 473 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size). 474 char test_area[BUFFER_SIZE]; 475 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1]; 476 477 // Allocate space for the code. 478 ResourceMark rm; 479 CodeBuffer cb("detect_cpu_features", code_size, 0); 480 MacroAssembler* a = new MacroAssembler(&cb); 481 482 // Must be set to true so we can generate the test code. 483 _features = VM_Version::all_features_m; 484 485 // Emit code. 486 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry(); 487 uint32_t *code = (uint32_t *)a->pc(); 488 // Don't use R0 in ldarx. 489 // Keep R3_ARG1 unmodified, it contains &field (see below). 490 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below). 491 a->fsqrt(F3, F4); // code[0] -> fsqrt_m 492 a->fsqrts(F3, F4); // code[1] -> fsqrts_m 493 a->isel(R7, R5, R6, 0); // code[2] -> isel_m 494 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m 495 a->cmpb(R7, R5, R6); // code[4] -> bcmp 496 //a->mftgpr(R7, F3); // code[5] -> mftgpr 497 a->popcntb(R7, R5); // code[6] -> popcntb 498 a->popcntw(R7, R5); // code[7] -> popcntw 499 a->fcfids(F3, F4); // code[8] -> fcfids 500 a->vand(VR0, VR0, VR0); // code[9] -> vand 501 a->lqarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[10] -> lqarx_m 502 a->vcipher(VR0, VR1, VR2); // code[11] -> vcipher 503 a->vpmsumb(VR0, VR1, VR2); // code[12] -> vpmsumb 504 a->mfdscr(R0); // code[13] -> mfdscr 505 a->lxvd2x(VSR0, 0, R3_ARG1); // code[14] -> vsx 506 a->blr(); 507 508 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it. 509 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry(); 510 a->dcbz(R3_ARG1); // R3_ARG1 = addr 511 a->blr(); 512 513 uint32_t *code_end = (uint32_t *)a->pc(); 514 a->flush(); 515 _features = VM_Version::unknown_m; 516 517 // Print the detection code. 518 if (PrintAssembly) { 519 ttyLocker ttyl; 520 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 521 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 522 } 523 524 // Measure cache line size. 525 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF. 526 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle. 527 int count = 0; // count zeroed bytes 528 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++; 529 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2"); 530 _measured_cache_line_size = count; 531 532 // Execute code. Illegal instructions will be replaced by 0 in the signal handler. 533 VM_Version::_is_determine_features_test_running = true; 534 (*test)((address)mid_of_test_area, (uint64_t)0); 535 VM_Version::_is_determine_features_test_running = false; 536 537 // determine which instructions are legal. 538 int feature_cntr = 0; 539 if (code[feature_cntr++]) features |= fsqrt_m; 540 if (code[feature_cntr++]) features |= fsqrts_m; 541 if (code[feature_cntr++]) features |= isel_m; 542 if (code[feature_cntr++]) features |= lxarxeh_m; 543 if (code[feature_cntr++]) features |= cmpb_m; 544 //if(code[feature_cntr++])features |= mftgpr_m; 545 if (code[feature_cntr++]) features |= popcntb_m; 546 if (code[feature_cntr++]) features |= popcntw_m; 547 if (code[feature_cntr++]) features |= fcfids_m; 548 if (code[feature_cntr++]) features |= vand_m; 549 if (code[feature_cntr++]) features |= lqarx_m; 550 if (code[feature_cntr++]) features |= vcipher_m; 551 if (code[feature_cntr++]) features |= vpmsumb_m; 552 if (code[feature_cntr++]) features |= mfdscr_m; 553 if (code[feature_cntr++]) features |= vsx_m; 554 555 // Print the detection code. 556 if (PrintAssembly) { 557 ttyLocker ttyl; 558 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code)); 559 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 560 } 561 562 _features = features; 563 } 564 565 // Power 8: Configure Data Stream Control Register. 566 void VM_Version::config_dscr() { 567 assert(has_lqarx(), "Only execute on Power 8 or later!"); 568 569 // 7 InstWords for each call (function descriptor + blr instruction). 570 const int code_size = (2+2*7)*BytesPerInstWord; 571 572 // Allocate space for the code. 573 ResourceMark rm; 574 CodeBuffer cb("config_dscr", code_size, 0); 575 MacroAssembler* a = new MacroAssembler(&cb); 576 577 // Emit code. 578 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry(); 579 uint32_t *code = (uint32_t *)a->pc(); 580 a->mfdscr(R3); 581 a->blr(); 582 583 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry(); 584 a->mtdscr(R3); 585 a->blr(); 586 587 uint32_t *code_end = (uint32_t *)a->pc(); 588 a->flush(); 589 590 // Print the detection code. 591 if (PrintAssembly) { 592 ttyLocker ttyl; 593 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", code); 594 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 595 } 596 597 // Apply the configuration if needed. 598 _dscr_val = (*get_dscr)(); 599 if (Verbose) { 600 tty->print_cr("dscr value was 0x%lx" , _dscr_val); 601 } 602 bool change_requested = false; 603 if (DSCR_PPC64 != (uintx)-1) { 604 _dscr_val = DSCR_PPC64; 605 change_requested = true; 606 } 607 if (DSCR_DPFD_PPC64 <= 7) { 608 uint64_t mask = 0x7; 609 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) { 610 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64); 611 change_requested = true; 612 } 613 } 614 if (DSCR_URG_PPC64 <= 7) { 615 uint64_t mask = 0x7 << 6; 616 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) { 617 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6); 618 change_requested = true; 619 } 620 } 621 if (change_requested) { 622 (*set_dscr)(_dscr_val); 623 if (Verbose) { 624 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)()); 625 } 626 } 627 } 628 629 static int saved_features = 0; 630 631 void VM_Version::allow_all() { 632 saved_features = _features; 633 _features = all_features_m; 634 } 635 636 void VM_Version::revert() { 637 _features = saved_features; 638 }