1 /* 2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "c1/c1_Compilation.hpp" 29 #include "c1/c1_LIRAssembler.hpp" 30 #include "c1/c1_MacroAssembler.hpp" 31 #include "c1/c1_Runtime1.hpp" 32 #include "c1/c1_ValueStack.hpp" 33 #include "ci/ciArrayKlass.hpp" 34 #include "ci/ciInstance.hpp" 35 #include "gc_interface/collectedHeap.hpp" 36 #include "memory/barrierSet.hpp" 37 #include "memory/cardTableModRefBS.hpp" 38 #include "nativeInst_x86.hpp" 39 #include "oops/objArrayKlass.hpp" 40 #include "runtime/sharedRuntime.hpp" 41 #include "vmreg_x86.inline.hpp" 42 43 44 // These masks are used to provide 128-bit aligned bitmasks to the XMM 45 // instructions, to allow sign-masking or sign-bit flipping. They allow 46 // fast versions of NegF/NegD and AbsF/AbsD. 47 48 // Note: 'double' and 'long long' have 32-bits alignment on x86. 49 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 50 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 51 // of 128-bits operands for SSE instructions. 52 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); 53 // Store the value to a 128-bits operand. 54 operand[0] = lo; 55 operand[1] = hi; 56 return operand; 57 } 58 59 // Buffer for 128-bits masks used by SSE instructions. 60 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 61 62 // Static initialization during VM startup. 63 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 64 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 65 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); 66 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); 67 68 69 70 NEEDS_CLEANUP // remove this definitions ? 71 const Register IC_Klass = rax; // where the IC klass is cached 72 const Register SYNC_header = rax; // synchronization header 73 const Register SHIFT_count = rcx; // where count for shift operations must be 74 75 #define __ _masm-> 76 77 78 static void select_different_registers(Register preserve, 79 Register extra, 80 Register &tmp1, 81 Register &tmp2) { 82 if (tmp1 == preserve) { 83 assert_different_registers(tmp1, tmp2, extra); 84 tmp1 = extra; 85 } else if (tmp2 == preserve) { 86 assert_different_registers(tmp1, tmp2, extra); 87 tmp2 = extra; 88 } 89 assert_different_registers(preserve, tmp1, tmp2); 90 } 91 92 93 94 static void select_different_registers(Register preserve, 95 Register extra, 96 Register &tmp1, 97 Register &tmp2, 98 Register &tmp3) { 99 if (tmp1 == preserve) { 100 assert_different_registers(tmp1, tmp2, tmp3, extra); 101 tmp1 = extra; 102 } else if (tmp2 == preserve) { 103 assert_different_registers(tmp1, tmp2, tmp3, extra); 104 tmp2 = extra; 105 } else if (tmp3 == preserve) { 106 assert_different_registers(tmp1, tmp2, tmp3, extra); 107 tmp3 = extra; 108 } 109 assert_different_registers(preserve, tmp1, tmp2, tmp3); 110 } 111 112 113 114 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 115 if (opr->is_constant()) { 116 LIR_Const* constant = opr->as_constant_ptr(); 117 switch (constant->type()) { 118 case T_INT: { 119 return true; 120 } 121 122 default: 123 return false; 124 } 125 } 126 return false; 127 } 128 129 130 LIR_Opr LIR_Assembler::receiverOpr() { 131 return FrameMap::receiver_opr; 132 } 133 134 LIR_Opr LIR_Assembler::osrBufferPointer() { 135 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 136 } 137 138 //--------------fpu register translations----------------------- 139 140 141 address LIR_Assembler::float_constant(float f) { 142 address const_addr = __ float_constant(f); 143 if (const_addr == NULL) { 144 bailout("const section overflow"); 145 return __ code()->consts()->start(); 146 } else { 147 return const_addr; 148 } 149 } 150 151 152 address LIR_Assembler::double_constant(double d) { 153 address const_addr = __ double_constant(d); 154 if (const_addr == NULL) { 155 bailout("const section overflow"); 156 return __ code()->consts()->start(); 157 } else { 158 return const_addr; 159 } 160 } 161 162 163 void LIR_Assembler::set_24bit_FPU() { 164 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 165 } 166 167 void LIR_Assembler::reset_FPU() { 168 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 169 } 170 171 void LIR_Assembler::fpop() { 172 __ fpop(); 173 } 174 175 void LIR_Assembler::fxch(int i) { 176 __ fxch(i); 177 } 178 179 void LIR_Assembler::fld(int i) { 180 __ fld_s(i); 181 } 182 183 void LIR_Assembler::ffree(int i) { 184 __ ffree(i); 185 } 186 187 void LIR_Assembler::breakpoint() { 188 __ int3(); 189 } 190 191 void LIR_Assembler::push(LIR_Opr opr) { 192 if (opr->is_single_cpu()) { 193 __ push_reg(opr->as_register()); 194 } else if (opr->is_double_cpu()) { 195 NOT_LP64(__ push_reg(opr->as_register_hi())); 196 __ push_reg(opr->as_register_lo()); 197 } else if (opr->is_stack()) { 198 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 199 } else if (opr->is_constant()) { 200 LIR_Const* const_opr = opr->as_constant_ptr(); 201 if (const_opr->type() == T_OBJECT) { 202 __ push_oop(const_opr->as_jobject()); 203 } else if (const_opr->type() == T_INT) { 204 __ push_jint(const_opr->as_jint()); 205 } else { 206 ShouldNotReachHere(); 207 } 208 209 } else { 210 ShouldNotReachHere(); 211 } 212 } 213 214 void LIR_Assembler::pop(LIR_Opr opr) { 215 if (opr->is_single_cpu()) { 216 __ pop_reg(opr->as_register()); 217 } else { 218 ShouldNotReachHere(); 219 } 220 } 221 222 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 223 return addr->base()->is_illegal() && addr->index()->is_illegal(); 224 } 225 226 //------------------------------------------- 227 228 Address LIR_Assembler::as_Address(LIR_Address* addr) { 229 return as_Address(addr, rscratch1); 230 } 231 232 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 233 if (addr->base()->is_illegal()) { 234 assert(addr->index()->is_illegal(), "must be illegal too"); 235 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 236 if (! __ reachable(laddr)) { 237 __ movptr(tmp, laddr.addr()); 238 Address res(tmp, 0); 239 return res; 240 } else { 241 return __ as_Address(laddr); 242 } 243 } 244 245 Register base = addr->base()->as_pointer_register(); 246 247 if (addr->index()->is_illegal()) { 248 return Address( base, addr->disp()); 249 } else if (addr->index()->is_cpu_register()) { 250 Register index = addr->index()->as_pointer_register(); 251 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 252 } else if (addr->index()->is_constant()) { 253 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 254 assert(Assembler::is_simm32(addr_offset), "must be"); 255 256 return Address(base, addr_offset); 257 } else { 258 Unimplemented(); 259 return Address(); 260 } 261 } 262 263 264 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 265 Address base = as_Address(addr); 266 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 267 } 268 269 270 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 271 return as_Address(addr); 272 } 273 274 275 void LIR_Assembler::osr_entry() { 276 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 277 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 278 ValueStack* entry_state = osr_entry->state(); 279 int number_of_locks = entry_state->locks_size(); 280 281 // we jump here if osr happens with the interpreter 282 // state set up to continue at the beginning of the 283 // loop that triggered osr - in particular, we have 284 // the following registers setup: 285 // 286 // rcx: osr buffer 287 // 288 289 // build frame 290 ciMethod* m = compilation()->method(); 291 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 292 293 // OSR buffer is 294 // 295 // locals[nlocals-1..0] 296 // monitors[0..number_of_locks] 297 // 298 // locals is a direct copy of the interpreter frame so in the osr buffer 299 // so first slot in the local array is the last local from the interpreter 300 // and last slot is local[0] (receiver) from the interpreter 301 // 302 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 303 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 304 // in the interpreter frame (the method lock if a sync method) 305 306 // Initialize monitors in the compiled activation. 307 // rcx: pointer to osr buffer 308 // 309 // All other registers are dead at this point and the locals will be 310 // copied into place by code emitted in the IR. 311 312 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 313 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 314 int monitor_offset = BytesPerWord * method()->max_locals() + 315 (2 * BytesPerWord) * (number_of_locks - 1); 316 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 317 // the OSR buffer using 2 word entries: first the lock and then 318 // the oop. 319 for (int i = 0; i < number_of_locks; i++) { 320 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 321 #ifdef ASSERT 322 // verify the interpreter's monitor has a non-null object 323 { 324 Label L; 325 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); 326 __ jcc(Assembler::notZero, L); 327 __ stop("locked object is NULL"); 328 __ bind(L); 329 } 330 #endif 331 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 332 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 333 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 334 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 335 } 336 } 337 } 338 339 340 // inline cache check; done before the frame is built. 341 int LIR_Assembler::check_icache() { 342 Register receiver = FrameMap::receiver_opr->as_register(); 343 Register ic_klass = IC_Klass; 344 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 345 const bool do_post_padding = VerifyOops || UseCompressedClassPointers; 346 if (!do_post_padding) { 347 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 348 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { 349 __ nop(); 350 } 351 } 352 int offset = __ offset(); 353 __ inline_cache_check(receiver, IC_Klass); 354 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); 355 if (do_post_padding) { 356 // force alignment after the cache check. 357 // It's been verified to be aligned if !VerifyOops 358 __ align(CodeEntryAlignment); 359 } 360 return offset; 361 } 362 363 364 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 365 jobject o = NULL; 366 PatchingStub* patch = new PatchingStub(_masm, patching_id(info)); 367 __ movoop(reg, o); 368 patching_epilog(patch, lir_patch_normal, reg, info); 369 } 370 371 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { 372 Metadata* o = NULL; 373 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 374 __ mov_metadata(reg, o); 375 patching_epilog(patch, lir_patch_normal, reg, info); 376 } 377 378 // This specifies the rsp decrement needed to build the frame 379 int LIR_Assembler::initial_frame_size_in_bytes() const { 380 // if rounding, must let FrameMap know! 381 382 // The frame_map records size in slots (32bit word) 383 384 // subtract two words to account for return address and link 385 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 386 } 387 388 389 int LIR_Assembler::emit_exception_handler() { 390 // if the last instruction is a call (typically to do a throw which 391 // is coming at the end after block reordering) the return address 392 // must still point into the code area in order to avoid assertion 393 // failures when searching for the corresponding bci => add a nop 394 // (was bug 5/14/1999 - gri) 395 __ nop(); 396 397 // generate code for exception handler 398 address handler_base = __ start_a_stub(exception_handler_size); 399 if (handler_base == NULL) { 400 // not enough space left for the handler 401 bailout("exception handler overflow"); 402 return -1; 403 } 404 405 int offset = code_offset(); 406 407 // the exception oop and pc are in rax, and rdx 408 // no other registers need to be preserved, so invalidate them 409 __ invalidate_registers(false, true, true, false, true, true); 410 411 // check that there is really an exception 412 __ verify_not_null_oop(rax); 413 414 // search an exception handler (rax: exception oop, rdx: throwing pc) 415 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 416 __ should_not_reach_here(); 417 guarantee(code_offset() - offset <= exception_handler_size, "overflow"); 418 __ end_a_stub(); 419 420 return offset; 421 } 422 423 424 // Emit the code to remove the frame from the stack in the exception 425 // unwind path. 426 int LIR_Assembler::emit_unwind_handler() { 427 #ifndef PRODUCT 428 if (CommentedAssembly) { 429 _masm->block_comment("Unwind handler"); 430 } 431 #endif 432 433 int offset = code_offset(); 434 435 // Fetch the exception from TLS and clear out exception related thread state 436 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 437 NOT_LP64(__ get_thread(rsi)); 438 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset())); 439 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD); 440 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD); 441 442 __ bind(_unwind_handler_entry); 443 __ verify_not_null_oop(rax); 444 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 445 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved) 446 } 447 448 // Preform needed unlocking 449 MonitorExitStub* stub = NULL; 450 if (method()->is_synchronized()) { 451 monitor_address(0, FrameMap::rax_opr); 452 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); 453 __ unlock_object(rdi, rsi, rax, *stub->entry()); 454 __ bind(*stub->continuation()); 455 } 456 457 if (compilation()->env()->dtrace_method_probes()) { 458 #ifdef _LP64 459 __ mov(rdi, r15_thread); 460 __ mov_metadata(rsi, method()->constant_encoding()); 461 #else 462 __ get_thread(rax); 463 __ movptr(Address(rsp, 0), rax); 464 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding()); 465 #endif 466 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 467 } 468 469 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 470 __ mov(rax, rbx); // Restore the exception 471 } 472 473 // remove the activation and dispatch to the unwind handler 474 __ remove_frame(initial_frame_size_in_bytes()); 475 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 476 477 // Emit the slow path assembly 478 if (stub != NULL) { 479 stub->emit_code(this); 480 } 481 482 return offset; 483 } 484 485 486 int LIR_Assembler::emit_deopt_handler() { 487 // if the last instruction is a call (typically to do a throw which 488 // is coming at the end after block reordering) the return address 489 // must still point into the code area in order to avoid assertion 490 // failures when searching for the corresponding bci => add a nop 491 // (was bug 5/14/1999 - gri) 492 __ nop(); 493 494 // generate code for exception handler 495 address handler_base = __ start_a_stub(deopt_handler_size); 496 if (handler_base == NULL) { 497 // not enough space left for the handler 498 bailout("deopt handler overflow"); 499 return -1; 500 } 501 502 int offset = code_offset(); 503 InternalAddress here(__ pc()); 504 505 __ pushptr(here.addr()); 506 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 507 guarantee(code_offset() - offset <= deopt_handler_size, "overflow"); 508 __ end_a_stub(); 509 510 return offset; 511 } 512 513 514 // This is the fast version of java.lang.String.compare; it has not 515 // OSR-entry and therefore, we generate a slow version for OSR's 516 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { 517 __ movptr (rbx, rcx); // receiver is in rcx 518 __ movptr (rax, arg1->as_register()); 519 520 // Get addresses of first characters from both Strings 521 __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes())); 522 if (java_lang_String::has_offset_field()) { 523 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); 524 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); 525 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 526 } else { 527 __ movl (rax, Address(rsi, arrayOopDesc::length_offset_in_bytes())); 528 __ lea (rsi, Address(rsi, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 529 } 530 531 // rbx, may be NULL 532 add_debug_info_for_null_check_here(info); 533 __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); 534 if (java_lang_String::has_offset_field()) { 535 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); 536 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); 537 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 538 } else { 539 __ movl (rbx, Address(rdi, arrayOopDesc::length_offset_in_bytes())); 540 __ lea (rdi, Address(rdi, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 541 } 542 543 // compute minimum length (in rax) and difference of lengths (on top of stack) 544 __ mov (rcx, rbx); 545 __ subptr(rbx, rax); // subtract lengths 546 __ push (rbx); // result 547 __ cmov (Assembler::lessEqual, rax, rcx); 548 549 // is minimum length 0? 550 Label noLoop, haveResult; 551 __ testptr (rax, rax); 552 __ jcc (Assembler::zero, noLoop); 553 554 // compare first characters 555 __ load_unsigned_short(rcx, Address(rdi, 0)); 556 __ load_unsigned_short(rbx, Address(rsi, 0)); 557 __ subl(rcx, rbx); 558 __ jcc(Assembler::notZero, haveResult); 559 // starting loop 560 __ decrement(rax); // we already tested index: skip one 561 __ jcc(Assembler::zero, noLoop); 562 563 // set rsi.edi to the end of the arrays (arrays have same length) 564 // negate the index 565 566 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); 567 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); 568 __ negptr(rax); 569 570 // compare the strings in a loop 571 572 Label loop; 573 __ align(wordSize); 574 __ bind(loop); 575 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); 576 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); 577 __ subl(rcx, rbx); 578 __ jcc(Assembler::notZero, haveResult); 579 __ increment(rax); 580 __ jcc(Assembler::notZero, loop); 581 582 // strings are equal up to min length 583 584 __ bind(noLoop); 585 __ pop(rax); 586 return_op(LIR_OprFact::illegalOpr); 587 588 __ bind(haveResult); 589 // leave instruction is going to discard the TOS value 590 __ mov (rax, rcx); // result of call is in rax, 591 } 592 593 594 void LIR_Assembler::return_op(LIR_Opr result) { 595 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 596 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 597 assert(result->fpu() == 0, "result must already be on TOS"); 598 } 599 600 // Pop the stack before the safepoint code 601 __ remove_frame(initial_frame_size_in_bytes()); 602 603 bool result_is_oop = result->is_valid() ? result->is_oop() : false; 604 605 // Note: we do not need to round double result; float result has the right precision 606 // the poll sets the condition code, but no data registers 607 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); 608 609 if (Assembler::is_polling_page_far()) { 610 __ lea(rscratch1, polling_page); 611 __ relocate(relocInfo::poll_return_type); 612 __ testl(rax, Address(rscratch1, 0)); 613 } else { 614 __ testl(rax, polling_page); 615 } 616 __ ret(0); 617 } 618 619 620 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 621 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type); 622 guarantee(info != NULL, "Shouldn't be NULL"); 623 int offset = __ offset(); 624 if (Assembler::is_polling_page_far()) { 625 __ lea(rscratch1, polling_page); 626 offset = __ offset(); 627 add_debug_info_for_branch(info); 628 __ testl(rax, Address(rscratch1, 0)); 629 } else { 630 add_debug_info_for_branch(info); 631 __ testl(rax, polling_page); 632 } 633 return offset; 634 } 635 636 637 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 638 if (from_reg != to_reg) __ mov(to_reg, from_reg); 639 } 640 641 void LIR_Assembler::swap_reg(Register a, Register b) { 642 __ xchgptr(a, b); 643 } 644 645 646 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 647 assert(src->is_constant(), "should not call otherwise"); 648 assert(dest->is_register(), "should not call otherwise"); 649 LIR_Const* c = src->as_constant_ptr(); 650 651 switch (c->type()) { 652 case T_INT: { 653 assert(patch_code == lir_patch_none, "no patching handled here"); 654 __ movl(dest->as_register(), c->as_jint()); 655 break; 656 } 657 658 case T_ADDRESS: { 659 assert(patch_code == lir_patch_none, "no patching handled here"); 660 __ movptr(dest->as_register(), c->as_jint()); 661 break; 662 } 663 664 case T_LONG: { 665 assert(patch_code == lir_patch_none, "no patching handled here"); 666 #ifdef _LP64 667 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 668 #else 669 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 670 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 671 #endif // _LP64 672 break; 673 } 674 675 case T_OBJECT: { 676 if (patch_code != lir_patch_none) { 677 jobject2reg_with_patching(dest->as_register(), info); 678 } else { 679 __ movoop(dest->as_register(), c->as_jobject()); 680 } 681 break; 682 } 683 684 case T_METADATA: { 685 if (patch_code != lir_patch_none) { 686 klass2reg_with_patching(dest->as_register(), info); 687 } else { 688 __ mov_metadata(dest->as_register(), c->as_metadata()); 689 } 690 break; 691 } 692 693 case T_FLOAT: { 694 if (dest->is_single_xmm()) { 695 if (c->is_zero_float()) { 696 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 697 } else { 698 __ movflt(dest->as_xmm_float_reg(), 699 InternalAddress(float_constant(c->as_jfloat()))); 700 } 701 } else { 702 assert(dest->is_single_fpu(), "must be"); 703 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 704 if (c->is_zero_float()) { 705 __ fldz(); 706 } else if (c->is_one_float()) { 707 __ fld1(); 708 } else { 709 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 710 } 711 } 712 break; 713 } 714 715 case T_DOUBLE: { 716 if (dest->is_double_xmm()) { 717 if (c->is_zero_double()) { 718 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 719 } else { 720 __ movdbl(dest->as_xmm_double_reg(), 721 InternalAddress(double_constant(c->as_jdouble()))); 722 } 723 } else { 724 assert(dest->is_double_fpu(), "must be"); 725 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 726 if (c->is_zero_double()) { 727 __ fldz(); 728 } else if (c->is_one_double()) { 729 __ fld1(); 730 } else { 731 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 732 } 733 } 734 break; 735 } 736 737 default: 738 ShouldNotReachHere(); 739 } 740 } 741 742 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 743 assert(src->is_constant(), "should not call otherwise"); 744 assert(dest->is_stack(), "should not call otherwise"); 745 LIR_Const* c = src->as_constant_ptr(); 746 747 switch (c->type()) { 748 case T_INT: // fall through 749 case T_FLOAT: 750 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 751 break; 752 753 case T_ADDRESS: 754 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 755 break; 756 757 case T_OBJECT: 758 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); 759 break; 760 761 case T_LONG: // fall through 762 case T_DOUBLE: 763 #ifdef _LP64 764 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 765 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); 766 #else 767 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 768 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 769 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 770 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 771 #endif // _LP64 772 break; 773 774 default: 775 ShouldNotReachHere(); 776 } 777 } 778 779 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 780 assert(src->is_constant(), "should not call otherwise"); 781 assert(dest->is_address(), "should not call otherwise"); 782 LIR_Const* c = src->as_constant_ptr(); 783 LIR_Address* addr = dest->as_address_ptr(); 784 785 int null_check_here = code_offset(); 786 switch (type) { 787 case T_INT: // fall through 788 case T_FLOAT: 789 __ movl(as_Address(addr), c->as_jint_bits()); 790 break; 791 792 case T_ADDRESS: 793 __ movptr(as_Address(addr), c->as_jint_bits()); 794 break; 795 796 case T_OBJECT: // fall through 797 case T_ARRAY: 798 if (c->as_jobject() == NULL) { 799 if (UseCompressedOops && !wide) { 800 __ movl(as_Address(addr), (int32_t)NULL_WORD); 801 } else { 802 #ifdef _LP64 803 __ xorptr(rscratch1, rscratch1); 804 null_check_here = code_offset(); 805 __ movptr(as_Address(addr), rscratch1); 806 #else 807 __ movptr(as_Address(addr), NULL_WORD); 808 #endif 809 } 810 } else { 811 if (is_literal_address(addr)) { 812 ShouldNotReachHere(); 813 __ movoop(as_Address(addr, noreg), c->as_jobject()); 814 } else { 815 #ifdef _LP64 816 __ movoop(rscratch1, c->as_jobject()); 817 if (UseCompressedOops && !wide) { 818 __ encode_heap_oop(rscratch1); 819 null_check_here = code_offset(); 820 __ movl(as_Address_lo(addr), rscratch1); 821 } else { 822 null_check_here = code_offset(); 823 __ movptr(as_Address_lo(addr), rscratch1); 824 } 825 #else 826 __ movoop(as_Address(addr), c->as_jobject()); 827 #endif 828 } 829 } 830 break; 831 832 case T_LONG: // fall through 833 case T_DOUBLE: 834 #ifdef _LP64 835 if (is_literal_address(addr)) { 836 ShouldNotReachHere(); 837 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 838 } else { 839 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 840 null_check_here = code_offset(); 841 __ movptr(as_Address_lo(addr), r10); 842 } 843 #else 844 // Always reachable in 32bit so this doesn't produce useless move literal 845 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 846 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 847 #endif // _LP64 848 break; 849 850 case T_BOOLEAN: // fall through 851 case T_BYTE: 852 __ movb(as_Address(addr), c->as_jint() & 0xFF); 853 break; 854 855 case T_CHAR: // fall through 856 case T_SHORT: 857 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 858 break; 859 860 default: 861 ShouldNotReachHere(); 862 }; 863 864 if (info != NULL) { 865 add_debug_info_for_null_check(null_check_here, info); 866 } 867 } 868 869 870 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 871 assert(src->is_register(), "should not call otherwise"); 872 assert(dest->is_register(), "should not call otherwise"); 873 874 // move between cpu-registers 875 if (dest->is_single_cpu()) { 876 #ifdef _LP64 877 if (src->type() == T_LONG) { 878 // Can do LONG -> OBJECT 879 move_regs(src->as_register_lo(), dest->as_register()); 880 return; 881 } 882 #endif 883 assert(src->is_single_cpu(), "must match"); 884 if (src->type() == T_OBJECT) { 885 __ verify_oop(src->as_register()); 886 } 887 move_regs(src->as_register(), dest->as_register()); 888 889 } else if (dest->is_double_cpu()) { 890 #ifdef _LP64 891 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { 892 // Surprising to me but we can see move of a long to t_object 893 __ verify_oop(src->as_register()); 894 move_regs(src->as_register(), dest->as_register_lo()); 895 return; 896 } 897 #endif 898 assert(src->is_double_cpu(), "must match"); 899 Register f_lo = src->as_register_lo(); 900 Register f_hi = src->as_register_hi(); 901 Register t_lo = dest->as_register_lo(); 902 Register t_hi = dest->as_register_hi(); 903 #ifdef _LP64 904 assert(f_hi == f_lo, "must be same"); 905 assert(t_hi == t_lo, "must be same"); 906 move_regs(f_lo, t_lo); 907 #else 908 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 909 910 911 if (f_lo == t_hi && f_hi == t_lo) { 912 swap_reg(f_lo, f_hi); 913 } else if (f_hi == t_lo) { 914 assert(f_lo != t_hi, "overwriting register"); 915 move_regs(f_hi, t_hi); 916 move_regs(f_lo, t_lo); 917 } else { 918 assert(f_hi != t_lo, "overwriting register"); 919 move_regs(f_lo, t_lo); 920 move_regs(f_hi, t_hi); 921 } 922 #endif // LP64 923 924 // special moves from fpu-register to xmm-register 925 // necessary for method results 926 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 927 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 928 __ fld_s(Address(rsp, 0)); 929 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 930 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 931 __ fld_d(Address(rsp, 0)); 932 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 933 __ fstp_s(Address(rsp, 0)); 934 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 935 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 936 __ fstp_d(Address(rsp, 0)); 937 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 938 939 // move between xmm-registers 940 } else if (dest->is_single_xmm()) { 941 assert(src->is_single_xmm(), "must match"); 942 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 943 } else if (dest->is_double_xmm()) { 944 assert(src->is_double_xmm(), "must match"); 945 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 946 947 // move between fpu-registers (no instruction necessary because of fpu-stack) 948 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 949 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 950 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 951 } else { 952 ShouldNotReachHere(); 953 } 954 } 955 956 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 957 assert(src->is_register(), "should not call otherwise"); 958 assert(dest->is_stack(), "should not call otherwise"); 959 960 if (src->is_single_cpu()) { 961 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 962 if (type == T_OBJECT || type == T_ARRAY) { 963 __ verify_oop(src->as_register()); 964 __ movptr (dst, src->as_register()); 965 } else if (type == T_METADATA) { 966 __ movptr (dst, src->as_register()); 967 } else { 968 __ movl (dst, src->as_register()); 969 } 970 971 } else if (src->is_double_cpu()) { 972 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 973 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 974 __ movptr (dstLO, src->as_register_lo()); 975 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 976 977 } else if (src->is_single_xmm()) { 978 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 979 __ movflt(dst_addr, src->as_xmm_float_reg()); 980 981 } else if (src->is_double_xmm()) { 982 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 983 __ movdbl(dst_addr, src->as_xmm_double_reg()); 984 985 } else if (src->is_single_fpu()) { 986 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 987 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 988 if (pop_fpu_stack) __ fstp_s (dst_addr); 989 else __ fst_s (dst_addr); 990 991 } else if (src->is_double_fpu()) { 992 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 993 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 994 if (pop_fpu_stack) __ fstp_d (dst_addr); 995 else __ fst_d (dst_addr); 996 997 } else { 998 ShouldNotReachHere(); 999 } 1000 } 1001 1002 1003 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { 1004 LIR_Address* to_addr = dest->as_address_ptr(); 1005 PatchingStub* patch = NULL; 1006 Register compressed_src = rscratch1; 1007 1008 if (type == T_ARRAY || type == T_OBJECT) { 1009 __ verify_oop(src->as_register()); 1010 #ifdef _LP64 1011 if (UseCompressedOops && !wide) { 1012 __ movptr(compressed_src, src->as_register()); 1013 __ encode_heap_oop(compressed_src); 1014 if (patch_code != lir_patch_none) { 1015 info->oop_map()->set_narrowoop(compressed_src->as_VMReg()); 1016 } 1017 } 1018 #endif 1019 } 1020 1021 if (patch_code != lir_patch_none) { 1022 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1023 Address toa = as_Address(to_addr); 1024 assert(toa.disp() != 0, "must have"); 1025 } 1026 1027 int null_check_here = code_offset(); 1028 switch (type) { 1029 case T_FLOAT: { 1030 if (src->is_single_xmm()) { 1031 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 1032 } else { 1033 assert(src->is_single_fpu(), "must be"); 1034 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 1035 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 1036 else __ fst_s (as_Address(to_addr)); 1037 } 1038 break; 1039 } 1040 1041 case T_DOUBLE: { 1042 if (src->is_double_xmm()) { 1043 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 1044 } else { 1045 assert(src->is_double_fpu(), "must be"); 1046 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 1047 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 1048 else __ fst_d (as_Address(to_addr)); 1049 } 1050 break; 1051 } 1052 1053 case T_ARRAY: // fall through 1054 case T_OBJECT: // fall through 1055 if (UseCompressedOops && !wide) { 1056 __ movl(as_Address(to_addr), compressed_src); 1057 } else { 1058 __ movptr(as_Address(to_addr), src->as_register()); 1059 } 1060 break; 1061 case T_METADATA: 1062 // We get here to store a method pointer to the stack to pass to 1063 // a dtrace runtime call. This can't work on 64 bit with 1064 // compressed klass ptrs: T_METADATA can be a compressed klass 1065 // ptr or a 64 bit method pointer. 1066 LP64_ONLY(ShouldNotReachHere()); 1067 __ movptr(as_Address(to_addr), src->as_register()); 1068 break; 1069 case T_ADDRESS: 1070 __ movptr(as_Address(to_addr), src->as_register()); 1071 break; 1072 case T_INT: 1073 __ movl(as_Address(to_addr), src->as_register()); 1074 break; 1075 1076 case T_LONG: { 1077 Register from_lo = src->as_register_lo(); 1078 Register from_hi = src->as_register_hi(); 1079 #ifdef _LP64 1080 __ movptr(as_Address_lo(to_addr), from_lo); 1081 #else 1082 Register base = to_addr->base()->as_register(); 1083 Register index = noreg; 1084 if (to_addr->index()->is_register()) { 1085 index = to_addr->index()->as_register(); 1086 } 1087 if (base == from_lo || index == from_lo) { 1088 assert(base != from_hi, "can't be"); 1089 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1090 __ movl(as_Address_hi(to_addr), from_hi); 1091 if (patch != NULL) { 1092 patching_epilog(patch, lir_patch_high, base, info); 1093 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1094 patch_code = lir_patch_low; 1095 } 1096 __ movl(as_Address_lo(to_addr), from_lo); 1097 } else { 1098 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1099 __ movl(as_Address_lo(to_addr), from_lo); 1100 if (patch != NULL) { 1101 patching_epilog(patch, lir_patch_low, base, info); 1102 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1103 patch_code = lir_patch_high; 1104 } 1105 __ movl(as_Address_hi(to_addr), from_hi); 1106 } 1107 #endif // _LP64 1108 break; 1109 } 1110 1111 case T_BYTE: // fall through 1112 case T_BOOLEAN: { 1113 Register src_reg = src->as_register(); 1114 Address dst_addr = as_Address(to_addr); 1115 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1116 __ movb(dst_addr, src_reg); 1117 break; 1118 } 1119 1120 case T_CHAR: // fall through 1121 case T_SHORT: 1122 __ movw(as_Address(to_addr), src->as_register()); 1123 break; 1124 1125 default: 1126 ShouldNotReachHere(); 1127 } 1128 if (info != NULL) { 1129 add_debug_info_for_null_check(null_check_here, info); 1130 } 1131 1132 if (patch_code != lir_patch_none) { 1133 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1134 } 1135 } 1136 1137 1138 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1139 assert(src->is_stack(), "should not call otherwise"); 1140 assert(dest->is_register(), "should not call otherwise"); 1141 1142 if (dest->is_single_cpu()) { 1143 if (type == T_ARRAY || type == T_OBJECT) { 1144 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1145 __ verify_oop(dest->as_register()); 1146 } else if (type == T_METADATA) { 1147 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1148 } else { 1149 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1150 } 1151 1152 } else if (dest->is_double_cpu()) { 1153 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1154 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1155 __ movptr(dest->as_register_lo(), src_addr_LO); 1156 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1157 1158 } else if (dest->is_single_xmm()) { 1159 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1160 __ movflt(dest->as_xmm_float_reg(), src_addr); 1161 1162 } else if (dest->is_double_xmm()) { 1163 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1164 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1165 1166 } else if (dest->is_single_fpu()) { 1167 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1168 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1169 __ fld_s(src_addr); 1170 1171 } else if (dest->is_double_fpu()) { 1172 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1173 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1174 __ fld_d(src_addr); 1175 1176 } else { 1177 ShouldNotReachHere(); 1178 } 1179 } 1180 1181 1182 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1183 if (src->is_single_stack()) { 1184 if (type == T_OBJECT || type == T_ARRAY) { 1185 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1186 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1187 } else { 1188 #ifndef _LP64 1189 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1190 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1191 #else 1192 //no pushl on 64bits 1193 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1194 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1195 #endif 1196 } 1197 1198 } else if (src->is_double_stack()) { 1199 #ifdef _LP64 1200 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1201 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1202 #else 1203 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1204 // push and pop the part at src + wordSize, adding wordSize for the previous push 1205 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1206 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1207 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1208 #endif // _LP64 1209 1210 } else { 1211 ShouldNotReachHere(); 1212 } 1213 } 1214 1215 1216 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { 1217 assert(src->is_address(), "should not call otherwise"); 1218 assert(dest->is_register(), "should not call otherwise"); 1219 1220 LIR_Address* addr = src->as_address_ptr(); 1221 Address from_addr = as_Address(addr); 1222 1223 if (addr->base()->type() == T_OBJECT) { 1224 __ verify_oop(addr->base()->as_pointer_register()); 1225 } 1226 1227 switch (type) { 1228 case T_BOOLEAN: // fall through 1229 case T_BYTE: // fall through 1230 case T_CHAR: // fall through 1231 case T_SHORT: 1232 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1233 // on pre P6 processors we may get partial register stalls 1234 // so blow away the value of to_rinfo before loading a 1235 // partial word into it. Do it here so that it precedes 1236 // the potential patch point below. 1237 __ xorptr(dest->as_register(), dest->as_register()); 1238 } 1239 break; 1240 } 1241 1242 PatchingStub* patch = NULL; 1243 if (patch_code != lir_patch_none) { 1244 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1245 assert(from_addr.disp() != 0, "must have"); 1246 } 1247 if (info != NULL) { 1248 add_debug_info_for_null_check_here(info); 1249 } 1250 1251 switch (type) { 1252 case T_FLOAT: { 1253 if (dest->is_single_xmm()) { 1254 __ movflt(dest->as_xmm_float_reg(), from_addr); 1255 } else { 1256 assert(dest->is_single_fpu(), "must be"); 1257 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1258 __ fld_s(from_addr); 1259 } 1260 break; 1261 } 1262 1263 case T_DOUBLE: { 1264 if (dest->is_double_xmm()) { 1265 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1266 } else { 1267 assert(dest->is_double_fpu(), "must be"); 1268 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1269 __ fld_d(from_addr); 1270 } 1271 break; 1272 } 1273 1274 case T_OBJECT: // fall through 1275 case T_ARRAY: // fall through 1276 if (UseCompressedOops && !wide) { 1277 __ movl(dest->as_register(), from_addr); 1278 } else { 1279 __ movptr(dest->as_register(), from_addr); 1280 } 1281 break; 1282 1283 case T_ADDRESS: 1284 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1285 __ movl(dest->as_register(), from_addr); 1286 } else { 1287 __ movptr(dest->as_register(), from_addr); 1288 } 1289 break; 1290 case T_INT: 1291 __ movl(dest->as_register(), from_addr); 1292 break; 1293 1294 case T_LONG: { 1295 Register to_lo = dest->as_register_lo(); 1296 Register to_hi = dest->as_register_hi(); 1297 #ifdef _LP64 1298 __ movptr(to_lo, as_Address_lo(addr)); 1299 #else 1300 Register base = addr->base()->as_register(); 1301 Register index = noreg; 1302 if (addr->index()->is_register()) { 1303 index = addr->index()->as_register(); 1304 } 1305 if ((base == to_lo && index == to_hi) || 1306 (base == to_hi && index == to_lo)) { 1307 // addresses with 2 registers are only formed as a result of 1308 // array access so this code will never have to deal with 1309 // patches or null checks. 1310 assert(info == NULL && patch == NULL, "must be"); 1311 __ lea(to_hi, as_Address(addr)); 1312 __ movl(to_lo, Address(to_hi, 0)); 1313 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1314 } else if (base == to_lo || index == to_lo) { 1315 assert(base != to_hi, "can't be"); 1316 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1317 __ movl(to_hi, as_Address_hi(addr)); 1318 if (patch != NULL) { 1319 patching_epilog(patch, lir_patch_high, base, info); 1320 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1321 patch_code = lir_patch_low; 1322 } 1323 __ movl(to_lo, as_Address_lo(addr)); 1324 } else { 1325 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1326 __ movl(to_lo, as_Address_lo(addr)); 1327 if (patch != NULL) { 1328 patching_epilog(patch, lir_patch_low, base, info); 1329 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1330 patch_code = lir_patch_high; 1331 } 1332 __ movl(to_hi, as_Address_hi(addr)); 1333 } 1334 #endif // _LP64 1335 break; 1336 } 1337 1338 case T_BOOLEAN: // fall through 1339 case T_BYTE: { 1340 Register dest_reg = dest->as_register(); 1341 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1342 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1343 __ movsbl(dest_reg, from_addr); 1344 } else { 1345 __ movb(dest_reg, from_addr); 1346 __ shll(dest_reg, 24); 1347 __ sarl(dest_reg, 24); 1348 } 1349 break; 1350 } 1351 1352 case T_CHAR: { 1353 Register dest_reg = dest->as_register(); 1354 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1355 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1356 __ movzwl(dest_reg, from_addr); 1357 } else { 1358 __ movw(dest_reg, from_addr); 1359 } 1360 break; 1361 } 1362 1363 case T_SHORT: { 1364 Register dest_reg = dest->as_register(); 1365 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1366 __ movswl(dest_reg, from_addr); 1367 } else { 1368 __ movw(dest_reg, from_addr); 1369 __ shll(dest_reg, 16); 1370 __ sarl(dest_reg, 16); 1371 } 1372 break; 1373 } 1374 1375 default: 1376 ShouldNotReachHere(); 1377 } 1378 1379 if (patch != NULL) { 1380 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1381 } 1382 1383 if (type == T_ARRAY || type == T_OBJECT) { 1384 #ifdef _LP64 1385 if (UseCompressedOops && !wide) { 1386 __ decode_heap_oop(dest->as_register()); 1387 } 1388 #endif 1389 __ verify_oop(dest->as_register()); 1390 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1391 #ifdef _LP64 1392 if (UseCompressedClassPointers) { 1393 __ decode_klass_not_null(dest->as_register()); 1394 } 1395 #endif 1396 } 1397 } 1398 1399 1400 void LIR_Assembler::prefetchr(LIR_Opr src) { 1401 LIR_Address* addr = src->as_address_ptr(); 1402 Address from_addr = as_Address(addr); 1403 1404 if (VM_Version::supports_sse()) { 1405 switch (ReadPrefetchInstr) { 1406 case 0: 1407 __ prefetchnta(from_addr); break; 1408 case 1: 1409 __ prefetcht0(from_addr); break; 1410 case 2: 1411 __ prefetcht2(from_addr); break; 1412 default: 1413 ShouldNotReachHere(); break; 1414 } 1415 } else if (VM_Version::supports_3dnow_prefetch()) { 1416 __ prefetchr(from_addr); 1417 } 1418 } 1419 1420 1421 void LIR_Assembler::prefetchw(LIR_Opr src) { 1422 LIR_Address* addr = src->as_address_ptr(); 1423 Address from_addr = as_Address(addr); 1424 1425 if (VM_Version::supports_sse()) { 1426 switch (AllocatePrefetchInstr) { 1427 case 0: 1428 __ prefetchnta(from_addr); break; 1429 case 1: 1430 __ prefetcht0(from_addr); break; 1431 case 2: 1432 __ prefetcht2(from_addr); break; 1433 case 3: 1434 __ prefetchw(from_addr); break; 1435 default: 1436 ShouldNotReachHere(); break; 1437 } 1438 } else if (VM_Version::supports_3dnow_prefetch()) { 1439 __ prefetchw(from_addr); 1440 } 1441 } 1442 1443 1444 NEEDS_CLEANUP; // This could be static? 1445 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1446 int elem_size = type2aelembytes(type); 1447 switch (elem_size) { 1448 case 1: return Address::times_1; 1449 case 2: return Address::times_2; 1450 case 4: return Address::times_4; 1451 case 8: return Address::times_8; 1452 } 1453 ShouldNotReachHere(); 1454 return Address::no_scale; 1455 } 1456 1457 1458 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1459 switch (op->code()) { 1460 case lir_idiv: 1461 case lir_irem: 1462 arithmetic_idiv(op->code(), 1463 op->in_opr1(), 1464 op->in_opr2(), 1465 op->in_opr3(), 1466 op->result_opr(), 1467 op->info()); 1468 break; 1469 default: ShouldNotReachHere(); break; 1470 } 1471 } 1472 1473 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1474 #ifdef ASSERT 1475 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1476 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1477 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1478 #endif 1479 1480 if (op->cond() == lir_cond_always) { 1481 if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1482 __ jmp (*(op->label())); 1483 } else { 1484 Assembler::Condition acond = Assembler::zero; 1485 if (op->code() == lir_cond_float_branch) { 1486 assert(op->ublock() != NULL, "must have unordered successor"); 1487 __ jcc(Assembler::parity, *(op->ublock()->label())); 1488 switch(op->cond()) { 1489 case lir_cond_equal: acond = Assembler::equal; break; 1490 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1491 case lir_cond_less: acond = Assembler::below; break; 1492 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1493 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1494 case lir_cond_greater: acond = Assembler::above; break; 1495 default: ShouldNotReachHere(); 1496 } 1497 } else { 1498 switch (op->cond()) { 1499 case lir_cond_equal: acond = Assembler::equal; break; 1500 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1501 case lir_cond_less: acond = Assembler::less; break; 1502 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1503 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1504 case lir_cond_greater: acond = Assembler::greater; break; 1505 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1506 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1507 default: ShouldNotReachHere(); 1508 } 1509 } 1510 __ jcc(acond,*(op->label())); 1511 } 1512 } 1513 1514 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1515 LIR_Opr src = op->in_opr(); 1516 LIR_Opr dest = op->result_opr(); 1517 1518 switch (op->bytecode()) { 1519 case Bytecodes::_i2l: 1520 #ifdef _LP64 1521 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1522 #else 1523 move_regs(src->as_register(), dest->as_register_lo()); 1524 move_regs(src->as_register(), dest->as_register_hi()); 1525 __ sarl(dest->as_register_hi(), 31); 1526 #endif // LP64 1527 break; 1528 1529 case Bytecodes::_l2i: 1530 #ifdef _LP64 1531 __ movl(dest->as_register(), src->as_register_lo()); 1532 #else 1533 move_regs(src->as_register_lo(), dest->as_register()); 1534 #endif 1535 break; 1536 1537 case Bytecodes::_i2b: 1538 move_regs(src->as_register(), dest->as_register()); 1539 __ sign_extend_byte(dest->as_register()); 1540 break; 1541 1542 case Bytecodes::_i2c: 1543 move_regs(src->as_register(), dest->as_register()); 1544 __ andl(dest->as_register(), 0xFFFF); 1545 break; 1546 1547 case Bytecodes::_i2s: 1548 move_regs(src->as_register(), dest->as_register()); 1549 __ sign_extend_short(dest->as_register()); 1550 break; 1551 1552 1553 case Bytecodes::_f2d: 1554 case Bytecodes::_d2f: 1555 if (dest->is_single_xmm()) { 1556 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1557 } else if (dest->is_double_xmm()) { 1558 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1559 } else { 1560 assert(src->fpu() == dest->fpu(), "register must be equal"); 1561 // do nothing (float result is rounded later through spilling) 1562 } 1563 break; 1564 1565 case Bytecodes::_i2f: 1566 case Bytecodes::_i2d: 1567 if (dest->is_single_xmm()) { 1568 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1569 } else if (dest->is_double_xmm()) { 1570 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1571 } else { 1572 assert(dest->fpu() == 0, "result must be on TOS"); 1573 __ movl(Address(rsp, 0), src->as_register()); 1574 __ fild_s(Address(rsp, 0)); 1575 } 1576 break; 1577 1578 case Bytecodes::_f2i: 1579 case Bytecodes::_d2i: 1580 if (src->is_single_xmm()) { 1581 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1582 } else if (src->is_double_xmm()) { 1583 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1584 } else { 1585 assert(src->fpu() == 0, "input must be on TOS"); 1586 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 1587 __ fist_s(Address(rsp, 0)); 1588 __ movl(dest->as_register(), Address(rsp, 0)); 1589 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1590 } 1591 1592 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1593 assert(op->stub() != NULL, "stub required"); 1594 __ cmpl(dest->as_register(), 0x80000000); 1595 __ jcc(Assembler::equal, *op->stub()->entry()); 1596 __ bind(*op->stub()->continuation()); 1597 break; 1598 1599 case Bytecodes::_l2f: 1600 case Bytecodes::_l2d: 1601 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1602 assert(dest->fpu() == 0, "result must be on TOS"); 1603 1604 __ movptr(Address(rsp, 0), src->as_register_lo()); 1605 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); 1606 __ fild_d(Address(rsp, 0)); 1607 // float result is rounded later through spilling 1608 break; 1609 1610 case Bytecodes::_f2l: 1611 case Bytecodes::_d2l: 1612 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1613 assert(src->fpu() == 0, "input must be on TOS"); 1614 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1615 1616 // instruction sequence too long to inline it here 1617 { 1618 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1619 } 1620 break; 1621 1622 default: ShouldNotReachHere(); 1623 } 1624 } 1625 1626 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1627 if (op->init_check()) { 1628 __ cmpb(Address(op->klass()->as_register(), 1629 InstanceKlass::init_state_offset()), 1630 InstanceKlass::fully_initialized); 1631 add_debug_info_for_null_check_here(op->stub()->info()); 1632 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1633 } 1634 __ allocate_object(op->obj()->as_register(), 1635 op->tmp1()->as_register(), 1636 op->tmp2()->as_register(), 1637 op->header_size(), 1638 op->object_size(), 1639 op->klass()->as_register(), 1640 *op->stub()->entry()); 1641 __ bind(*op->stub()->continuation()); 1642 } 1643 1644 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1645 Register len = op->len()->as_register(); 1646 LP64_ONLY( __ movslq(len, len); ) 1647 1648 if (UseSlowPath || 1649 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 1650 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 1651 __ jmp(*op->stub()->entry()); 1652 } else { 1653 Register tmp1 = op->tmp1()->as_register(); 1654 Register tmp2 = op->tmp2()->as_register(); 1655 Register tmp3 = op->tmp3()->as_register(); 1656 if (len == tmp1) { 1657 tmp1 = tmp3; 1658 } else if (len == tmp2) { 1659 tmp2 = tmp3; 1660 } else if (len == tmp3) { 1661 // everything is ok 1662 } else { 1663 __ mov(tmp3, len); 1664 } 1665 __ allocate_array(op->obj()->as_register(), 1666 len, 1667 tmp1, 1668 tmp2, 1669 arrayOopDesc::header_size(op->type()), 1670 array_element_size(op->type()), 1671 op->klass()->as_register(), 1672 *op->stub()->entry()); 1673 } 1674 __ bind(*op->stub()->continuation()); 1675 } 1676 1677 void LIR_Assembler::type_profile_helper(Register mdo, 1678 ciMethodData *md, ciProfileData *data, 1679 Register recv, Label* update_done) { 1680 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1681 Label next_test; 1682 // See if the receiver is receiver[n]. 1683 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1684 __ jccb(Assembler::notEqual, next_test); 1685 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1686 __ addptr(data_addr, DataLayout::counter_increment); 1687 __ jmp(*update_done); 1688 __ bind(next_test); 1689 } 1690 1691 // Didn't find receiver; find next empty slot and fill it in 1692 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1693 Label next_test; 1694 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 1695 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); 1696 __ jccb(Assembler::notEqual, next_test); 1697 __ movptr(recv_addr, recv); 1698 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); 1699 __ jmp(*update_done); 1700 __ bind(next_test); 1701 } 1702 } 1703 1704 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1705 // we always need a stub for the failure case. 1706 CodeStub* stub = op->stub(); 1707 Register obj = op->object()->as_register(); 1708 Register k_RInfo = op->tmp1()->as_register(); 1709 Register klass_RInfo = op->tmp2()->as_register(); 1710 Register dst = op->result_opr()->as_register(); 1711 ciKlass* k = op->klass(); 1712 Register Rtmp1 = noreg; 1713 1714 // check if it needs to be profiled 1715 ciMethodData* md; 1716 ciProfileData* data; 1717 1718 if (op->should_profile()) { 1719 ciMethod* method = op->profiled_method(); 1720 assert(method != NULL, "Should have method"); 1721 int bci = op->profiled_bci(); 1722 md = method->method_data_or_null(); 1723 assert(md != NULL, "Sanity"); 1724 data = md->bci_to_data(bci); 1725 assert(data != NULL, "need data for type check"); 1726 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1727 } 1728 Label profile_cast_success, profile_cast_failure; 1729 Label *success_target = op->should_profile() ? &profile_cast_success : success; 1730 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 1731 1732 if (obj == k_RInfo) { 1733 k_RInfo = dst; 1734 } else if (obj == klass_RInfo) { 1735 klass_RInfo = dst; 1736 } 1737 if (k->is_loaded() && !UseCompressedClassPointers) { 1738 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1739 } else { 1740 Rtmp1 = op->tmp3()->as_register(); 1741 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1742 } 1743 1744 assert_different_registers(obj, k_RInfo, klass_RInfo); 1745 1746 __ cmpptr(obj, (int32_t)NULL_WORD); 1747 if (op->should_profile()) { 1748 Label not_null; 1749 __ jccb(Assembler::notEqual, not_null); 1750 // Object is null; update MDO and exit 1751 Register mdo = klass_RInfo; 1752 __ mov_metadata(mdo, md->constant_encoding()); 1753 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1754 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1755 __ orl(data_addr, header_bits); 1756 __ jmp(*obj_is_null); 1757 __ bind(not_null); 1758 } else { 1759 __ jcc(Assembler::equal, *obj_is_null); 1760 } 1761 1762 if (!k->is_loaded()) { 1763 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 1764 } else { 1765 #ifdef _LP64 1766 __ mov_metadata(k_RInfo, k->constant_encoding()); 1767 #endif // _LP64 1768 } 1769 __ verify_oop(obj); 1770 1771 if (op->fast_check()) { 1772 // get object class 1773 // not a safepoint as obj null check happens earlier 1774 #ifdef _LP64 1775 if (UseCompressedClassPointers) { 1776 __ load_klass(Rtmp1, obj); 1777 __ cmpptr(k_RInfo, Rtmp1); 1778 } else { 1779 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1780 } 1781 #else 1782 if (k->is_loaded()) { 1783 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 1784 } else { 1785 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1786 } 1787 #endif 1788 __ jcc(Assembler::notEqual, *failure_target); 1789 // successful cast, fall through to profile or jump 1790 } else { 1791 // get object class 1792 // not a safepoint as obj null check happens earlier 1793 __ load_klass(klass_RInfo, obj); 1794 if (k->is_loaded()) { 1795 // See if we get an immediate positive hit 1796 #ifdef _LP64 1797 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1798 #else 1799 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1800 #endif // _LP64 1801 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1802 __ jcc(Assembler::notEqual, *failure_target); 1803 // successful cast, fall through to profile or jump 1804 } else { 1805 // See if we get an immediate positive hit 1806 __ jcc(Assembler::equal, *success_target); 1807 // check for self 1808 #ifdef _LP64 1809 __ cmpptr(klass_RInfo, k_RInfo); 1810 #else 1811 __ cmpklass(klass_RInfo, k->constant_encoding()); 1812 #endif // _LP64 1813 __ jcc(Assembler::equal, *success_target); 1814 1815 __ push(klass_RInfo); 1816 #ifdef _LP64 1817 __ push(k_RInfo); 1818 #else 1819 __ pushklass(k->constant_encoding()); 1820 #endif // _LP64 1821 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1822 __ pop(klass_RInfo); 1823 __ pop(klass_RInfo); 1824 // result is a boolean 1825 __ cmpl(klass_RInfo, 0); 1826 __ jcc(Assembler::equal, *failure_target); 1827 // successful cast, fall through to profile or jump 1828 } 1829 } else { 1830 // perform the fast part of the checking logic 1831 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1832 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1833 __ push(klass_RInfo); 1834 __ push(k_RInfo); 1835 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1836 __ pop(klass_RInfo); 1837 __ pop(k_RInfo); 1838 // result is a boolean 1839 __ cmpl(k_RInfo, 0); 1840 __ jcc(Assembler::equal, *failure_target); 1841 // successful cast, fall through to profile or jump 1842 } 1843 } 1844 if (op->should_profile()) { 1845 Register mdo = klass_RInfo, recv = k_RInfo; 1846 __ bind(profile_cast_success); 1847 __ mov_metadata(mdo, md->constant_encoding()); 1848 __ load_klass(recv, obj); 1849 Label update_done; 1850 type_profile_helper(mdo, md, data, recv, success); 1851 __ jmp(*success); 1852 1853 __ bind(profile_cast_failure); 1854 __ mov_metadata(mdo, md->constant_encoding()); 1855 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1856 __ subptr(counter_addr, DataLayout::counter_increment); 1857 __ jmp(*failure); 1858 } 1859 __ jmp(*success); 1860 } 1861 1862 1863 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1864 LIR_Code code = op->code(); 1865 if (code == lir_store_check) { 1866 Register value = op->object()->as_register(); 1867 Register array = op->array()->as_register(); 1868 Register k_RInfo = op->tmp1()->as_register(); 1869 Register klass_RInfo = op->tmp2()->as_register(); 1870 Register Rtmp1 = op->tmp3()->as_register(); 1871 1872 CodeStub* stub = op->stub(); 1873 1874 // check if it needs to be profiled 1875 ciMethodData* md; 1876 ciProfileData* data; 1877 1878 if (op->should_profile()) { 1879 ciMethod* method = op->profiled_method(); 1880 assert(method != NULL, "Should have method"); 1881 int bci = op->profiled_bci(); 1882 md = method->method_data_or_null(); 1883 assert(md != NULL, "Sanity"); 1884 data = md->bci_to_data(bci); 1885 assert(data != NULL, "need data for type check"); 1886 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1887 } 1888 Label profile_cast_success, profile_cast_failure, done; 1889 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 1890 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 1891 1892 __ cmpptr(value, (int32_t)NULL_WORD); 1893 if (op->should_profile()) { 1894 Label not_null; 1895 __ jccb(Assembler::notEqual, not_null); 1896 // Object is null; update MDO and exit 1897 Register mdo = klass_RInfo; 1898 __ mov_metadata(mdo, md->constant_encoding()); 1899 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1900 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1901 __ orl(data_addr, header_bits); 1902 __ jmp(done); 1903 __ bind(not_null); 1904 } else { 1905 __ jcc(Assembler::equal, done); 1906 } 1907 1908 add_debug_info_for_null_check_here(op->info_for_exception()); 1909 __ load_klass(k_RInfo, array); 1910 __ load_klass(klass_RInfo, value); 1911 1912 // get instance klass (it's already uncompressed) 1913 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 1914 // perform the fast part of the checking logic 1915 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1916 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1917 __ push(klass_RInfo); 1918 __ push(k_RInfo); 1919 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1920 __ pop(klass_RInfo); 1921 __ pop(k_RInfo); 1922 // result is a boolean 1923 __ cmpl(k_RInfo, 0); 1924 __ jcc(Assembler::equal, *failure_target); 1925 // fall through to the success case 1926 1927 if (op->should_profile()) { 1928 Register mdo = klass_RInfo, recv = k_RInfo; 1929 __ bind(profile_cast_success); 1930 __ mov_metadata(mdo, md->constant_encoding()); 1931 __ load_klass(recv, value); 1932 Label update_done; 1933 type_profile_helper(mdo, md, data, recv, &done); 1934 __ jmpb(done); 1935 1936 __ bind(profile_cast_failure); 1937 __ mov_metadata(mdo, md->constant_encoding()); 1938 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1939 __ subptr(counter_addr, DataLayout::counter_increment); 1940 __ jmp(*stub->entry()); 1941 } 1942 1943 __ bind(done); 1944 } else 1945 if (code == lir_checkcast) { 1946 Register obj = op->object()->as_register(); 1947 Register dst = op->result_opr()->as_register(); 1948 Label success; 1949 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1950 __ bind(success); 1951 if (dst != obj) { 1952 __ mov(dst, obj); 1953 } 1954 } else 1955 if (code == lir_instanceof) { 1956 Register obj = op->object()->as_register(); 1957 Register dst = op->result_opr()->as_register(); 1958 Label success, failure, done; 1959 emit_typecheck_helper(op, &success, &failure, &failure); 1960 __ bind(failure); 1961 __ xorptr(dst, dst); 1962 __ jmpb(done); 1963 __ bind(success); 1964 __ movptr(dst, 1); 1965 __ bind(done); 1966 } else { 1967 ShouldNotReachHere(); 1968 } 1969 1970 } 1971 1972 1973 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1974 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { 1975 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1976 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1977 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1978 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1979 Register addr = op->addr()->as_register(); 1980 if (os::is_MP()) { 1981 __ lock(); 1982 } 1983 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1984 1985 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1986 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1987 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1988 Register newval = op->new_value()->as_register(); 1989 Register cmpval = op->cmp_value()->as_register(); 1990 assert(cmpval == rax, "wrong register"); 1991 assert(newval != NULL, "new val must be register"); 1992 assert(cmpval != newval, "cmp and new values must be in different registers"); 1993 assert(cmpval != addr, "cmp and addr must be in different registers"); 1994 assert(newval != addr, "new value and addr must be in different registers"); 1995 1996 if ( op->code() == lir_cas_obj) { 1997 #ifdef _LP64 1998 if (UseCompressedOops) { 1999 __ encode_heap_oop(cmpval); 2000 __ mov(rscratch1, newval); 2001 __ encode_heap_oop(rscratch1); 2002 if (os::is_MP()) { 2003 __ lock(); 2004 } 2005 // cmpval (rax) is implicitly used by this instruction 2006 __ cmpxchgl(rscratch1, Address(addr, 0)); 2007 } else 2008 #endif 2009 { 2010 if (os::is_MP()) { 2011 __ lock(); 2012 } 2013 __ cmpxchgptr(newval, Address(addr, 0)); 2014 } 2015 } else { 2016 assert(op->code() == lir_cas_int, "lir_cas_int expected"); 2017 if (os::is_MP()) { 2018 __ lock(); 2019 } 2020 __ cmpxchgl(newval, Address(addr, 0)); 2021 } 2022 #ifdef _LP64 2023 } else if (op->code() == lir_cas_long) { 2024 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 2025 Register newval = op->new_value()->as_register_lo(); 2026 Register cmpval = op->cmp_value()->as_register_lo(); 2027 assert(cmpval == rax, "wrong register"); 2028 assert(newval != NULL, "new val must be register"); 2029 assert(cmpval != newval, "cmp and new values must be in different registers"); 2030 assert(cmpval != addr, "cmp and addr must be in different registers"); 2031 assert(newval != addr, "new value and addr must be in different registers"); 2032 if (os::is_MP()) { 2033 __ lock(); 2034 } 2035 __ cmpxchgq(newval, Address(addr, 0)); 2036 #endif // _LP64 2037 } else { 2038 Unimplemented(); 2039 } 2040 } 2041 2042 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 2043 Assembler::Condition acond, ncond; 2044 switch (condition) { 2045 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 2046 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 2047 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 2048 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 2049 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 2050 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 2051 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 2052 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 2053 default: ShouldNotReachHere(); 2054 } 2055 2056 if (opr1->is_cpu_register()) { 2057 reg2reg(opr1, result); 2058 } else if (opr1->is_stack()) { 2059 stack2reg(opr1, result, result->type()); 2060 } else if (opr1->is_constant()) { 2061 const2reg(opr1, result, lir_patch_none, NULL); 2062 } else { 2063 ShouldNotReachHere(); 2064 } 2065 2066 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 2067 // optimized version that does not require a branch 2068 if (opr2->is_single_cpu()) { 2069 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 2070 __ cmov(ncond, result->as_register(), opr2->as_register()); 2071 } else if (opr2->is_double_cpu()) { 2072 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2073 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2074 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 2075 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 2076 } else if (opr2->is_single_stack()) { 2077 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 2078 } else if (opr2->is_double_stack()) { 2079 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 2080 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 2081 } else { 2082 ShouldNotReachHere(); 2083 } 2084 2085 } else { 2086 Label skip; 2087 __ jcc (acond, skip); 2088 if (opr2->is_cpu_register()) { 2089 reg2reg(opr2, result); 2090 } else if (opr2->is_stack()) { 2091 stack2reg(opr2, result, result->type()); 2092 } else if (opr2->is_constant()) { 2093 const2reg(opr2, result, lir_patch_none, NULL); 2094 } else { 2095 ShouldNotReachHere(); 2096 } 2097 __ bind(skip); 2098 } 2099 } 2100 2101 2102 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 2103 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 2104 2105 if (left->is_single_cpu()) { 2106 assert(left == dest, "left and dest must be equal"); 2107 Register lreg = left->as_register(); 2108 2109 if (right->is_single_cpu()) { 2110 // cpu register - cpu register 2111 Register rreg = right->as_register(); 2112 switch (code) { 2113 case lir_add: __ addl (lreg, rreg); break; 2114 case lir_sub: __ subl (lreg, rreg); break; 2115 case lir_mul: __ imull(lreg, rreg); break; 2116 default: ShouldNotReachHere(); 2117 } 2118 2119 } else if (right->is_stack()) { 2120 // cpu register - stack 2121 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2122 switch (code) { 2123 case lir_add: __ addl(lreg, raddr); break; 2124 case lir_sub: __ subl(lreg, raddr); break; 2125 default: ShouldNotReachHere(); 2126 } 2127 2128 } else if (right->is_constant()) { 2129 // cpu register - constant 2130 jint c = right->as_constant_ptr()->as_jint(); 2131 switch (code) { 2132 case lir_add: { 2133 __ incrementl(lreg, c); 2134 break; 2135 } 2136 case lir_sub: { 2137 __ decrementl(lreg, c); 2138 break; 2139 } 2140 default: ShouldNotReachHere(); 2141 } 2142 2143 } else { 2144 ShouldNotReachHere(); 2145 } 2146 2147 } else if (left->is_double_cpu()) { 2148 assert(left == dest, "left and dest must be equal"); 2149 Register lreg_lo = left->as_register_lo(); 2150 Register lreg_hi = left->as_register_hi(); 2151 2152 if (right->is_double_cpu()) { 2153 // cpu register - cpu register 2154 Register rreg_lo = right->as_register_lo(); 2155 Register rreg_hi = right->as_register_hi(); 2156 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2157 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2158 switch (code) { 2159 case lir_add: 2160 __ addptr(lreg_lo, rreg_lo); 2161 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2162 break; 2163 case lir_sub: 2164 __ subptr(lreg_lo, rreg_lo); 2165 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2166 break; 2167 case lir_mul: 2168 #ifdef _LP64 2169 __ imulq(lreg_lo, rreg_lo); 2170 #else 2171 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2172 __ imull(lreg_hi, rreg_lo); 2173 __ imull(rreg_hi, lreg_lo); 2174 __ addl (rreg_hi, lreg_hi); 2175 __ mull (rreg_lo); 2176 __ addl (lreg_hi, rreg_hi); 2177 #endif // _LP64 2178 break; 2179 default: 2180 ShouldNotReachHere(); 2181 } 2182 2183 } else if (right->is_constant()) { 2184 // cpu register - constant 2185 #ifdef _LP64 2186 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2187 __ movptr(r10, (intptr_t) c); 2188 switch (code) { 2189 case lir_add: 2190 __ addptr(lreg_lo, r10); 2191 break; 2192 case lir_sub: 2193 __ subptr(lreg_lo, r10); 2194 break; 2195 default: 2196 ShouldNotReachHere(); 2197 } 2198 #else 2199 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2200 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2201 switch (code) { 2202 case lir_add: 2203 __ addptr(lreg_lo, c_lo); 2204 __ adcl(lreg_hi, c_hi); 2205 break; 2206 case lir_sub: 2207 __ subptr(lreg_lo, c_lo); 2208 __ sbbl(lreg_hi, c_hi); 2209 break; 2210 default: 2211 ShouldNotReachHere(); 2212 } 2213 #endif // _LP64 2214 2215 } else { 2216 ShouldNotReachHere(); 2217 } 2218 2219 } else if (left->is_single_xmm()) { 2220 assert(left == dest, "left and dest must be equal"); 2221 XMMRegister lreg = left->as_xmm_float_reg(); 2222 2223 if (right->is_single_xmm()) { 2224 XMMRegister rreg = right->as_xmm_float_reg(); 2225 switch (code) { 2226 case lir_add: __ addss(lreg, rreg); break; 2227 case lir_sub: __ subss(lreg, rreg); break; 2228 case lir_mul_strictfp: // fall through 2229 case lir_mul: __ mulss(lreg, rreg); break; 2230 case lir_div_strictfp: // fall through 2231 case lir_div: __ divss(lreg, rreg); break; 2232 default: ShouldNotReachHere(); 2233 } 2234 } else { 2235 Address raddr; 2236 if (right->is_single_stack()) { 2237 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2238 } else if (right->is_constant()) { 2239 // hack for now 2240 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2241 } else { 2242 ShouldNotReachHere(); 2243 } 2244 switch (code) { 2245 case lir_add: __ addss(lreg, raddr); break; 2246 case lir_sub: __ subss(lreg, raddr); break; 2247 case lir_mul_strictfp: // fall through 2248 case lir_mul: __ mulss(lreg, raddr); break; 2249 case lir_div_strictfp: // fall through 2250 case lir_div: __ divss(lreg, raddr); break; 2251 default: ShouldNotReachHere(); 2252 } 2253 } 2254 2255 } else if (left->is_double_xmm()) { 2256 assert(left == dest, "left and dest must be equal"); 2257 2258 XMMRegister lreg = left->as_xmm_double_reg(); 2259 if (right->is_double_xmm()) { 2260 XMMRegister rreg = right->as_xmm_double_reg(); 2261 switch (code) { 2262 case lir_add: __ addsd(lreg, rreg); break; 2263 case lir_sub: __ subsd(lreg, rreg); break; 2264 case lir_mul_strictfp: // fall through 2265 case lir_mul: __ mulsd(lreg, rreg); break; 2266 case lir_div_strictfp: // fall through 2267 case lir_div: __ divsd(lreg, rreg); break; 2268 default: ShouldNotReachHere(); 2269 } 2270 } else { 2271 Address raddr; 2272 if (right->is_double_stack()) { 2273 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2274 } else if (right->is_constant()) { 2275 // hack for now 2276 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2277 } else { 2278 ShouldNotReachHere(); 2279 } 2280 switch (code) { 2281 case lir_add: __ addsd(lreg, raddr); break; 2282 case lir_sub: __ subsd(lreg, raddr); break; 2283 case lir_mul_strictfp: // fall through 2284 case lir_mul: __ mulsd(lreg, raddr); break; 2285 case lir_div_strictfp: // fall through 2286 case lir_div: __ divsd(lreg, raddr); break; 2287 default: ShouldNotReachHere(); 2288 } 2289 } 2290 2291 } else if (left->is_single_fpu()) { 2292 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2293 2294 if (right->is_single_fpu()) { 2295 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2296 2297 } else { 2298 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2299 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2300 2301 Address raddr; 2302 if (right->is_single_stack()) { 2303 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2304 } else if (right->is_constant()) { 2305 address const_addr = float_constant(right->as_jfloat()); 2306 assert(const_addr != NULL, "incorrect float/double constant maintainance"); 2307 // hack for now 2308 raddr = __ as_Address(InternalAddress(const_addr)); 2309 } else { 2310 ShouldNotReachHere(); 2311 } 2312 2313 switch (code) { 2314 case lir_add: __ fadd_s(raddr); break; 2315 case lir_sub: __ fsub_s(raddr); break; 2316 case lir_mul_strictfp: // fall through 2317 case lir_mul: __ fmul_s(raddr); break; 2318 case lir_div_strictfp: // fall through 2319 case lir_div: __ fdiv_s(raddr); break; 2320 default: ShouldNotReachHere(); 2321 } 2322 } 2323 2324 } else if (left->is_double_fpu()) { 2325 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2326 2327 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2328 // Double values require special handling for strictfp mul/div on x86 2329 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); 2330 __ fmulp(left->fpu_regnrLo() + 1); 2331 } 2332 2333 if (right->is_double_fpu()) { 2334 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2335 2336 } else { 2337 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2338 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2339 2340 Address raddr; 2341 if (right->is_double_stack()) { 2342 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2343 } else if (right->is_constant()) { 2344 // hack for now 2345 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2346 } else { 2347 ShouldNotReachHere(); 2348 } 2349 2350 switch (code) { 2351 case lir_add: __ fadd_d(raddr); break; 2352 case lir_sub: __ fsub_d(raddr); break; 2353 case lir_mul_strictfp: // fall through 2354 case lir_mul: __ fmul_d(raddr); break; 2355 case lir_div_strictfp: // fall through 2356 case lir_div: __ fdiv_d(raddr); break; 2357 default: ShouldNotReachHere(); 2358 } 2359 } 2360 2361 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2362 // Double values require special handling for strictfp mul/div on x86 2363 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); 2364 __ fmulp(dest->fpu_regnrLo() + 1); 2365 } 2366 2367 } else if (left->is_single_stack() || left->is_address()) { 2368 assert(left == dest, "left and dest must be equal"); 2369 2370 Address laddr; 2371 if (left->is_single_stack()) { 2372 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2373 } else if (left->is_address()) { 2374 laddr = as_Address(left->as_address_ptr()); 2375 } else { 2376 ShouldNotReachHere(); 2377 } 2378 2379 if (right->is_single_cpu()) { 2380 Register rreg = right->as_register(); 2381 switch (code) { 2382 case lir_add: __ addl(laddr, rreg); break; 2383 case lir_sub: __ subl(laddr, rreg); break; 2384 default: ShouldNotReachHere(); 2385 } 2386 } else if (right->is_constant()) { 2387 jint c = right->as_constant_ptr()->as_jint(); 2388 switch (code) { 2389 case lir_add: { 2390 __ incrementl(laddr, c); 2391 break; 2392 } 2393 case lir_sub: { 2394 __ decrementl(laddr, c); 2395 break; 2396 } 2397 default: ShouldNotReachHere(); 2398 } 2399 } else { 2400 ShouldNotReachHere(); 2401 } 2402 2403 } else { 2404 ShouldNotReachHere(); 2405 } 2406 } 2407 2408 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2409 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2410 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2411 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2412 2413 bool left_is_tos = (left_index == 0); 2414 bool dest_is_tos = (dest_index == 0); 2415 int non_tos_index = (left_is_tos ? right_index : left_index); 2416 2417 switch (code) { 2418 case lir_add: 2419 if (pop_fpu_stack) __ faddp(non_tos_index); 2420 else if (dest_is_tos) __ fadd (non_tos_index); 2421 else __ fadda(non_tos_index); 2422 break; 2423 2424 case lir_sub: 2425 if (left_is_tos) { 2426 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2427 else if (dest_is_tos) __ fsub (non_tos_index); 2428 else __ fsubra(non_tos_index); 2429 } else { 2430 if (pop_fpu_stack) __ fsubp (non_tos_index); 2431 else if (dest_is_tos) __ fsubr (non_tos_index); 2432 else __ fsuba (non_tos_index); 2433 } 2434 break; 2435 2436 case lir_mul_strictfp: // fall through 2437 case lir_mul: 2438 if (pop_fpu_stack) __ fmulp(non_tos_index); 2439 else if (dest_is_tos) __ fmul (non_tos_index); 2440 else __ fmula(non_tos_index); 2441 break; 2442 2443 case lir_div_strictfp: // fall through 2444 case lir_div: 2445 if (left_is_tos) { 2446 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2447 else if (dest_is_tos) __ fdiv (non_tos_index); 2448 else __ fdivra(non_tos_index); 2449 } else { 2450 if (pop_fpu_stack) __ fdivp (non_tos_index); 2451 else if (dest_is_tos) __ fdivr (non_tos_index); 2452 else __ fdiva (non_tos_index); 2453 } 2454 break; 2455 2456 case lir_rem: 2457 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2458 __ fremr(noreg); 2459 break; 2460 2461 default: 2462 ShouldNotReachHere(); 2463 } 2464 } 2465 2466 2467 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { 2468 if (value->is_double_xmm()) { 2469 switch(code) { 2470 case lir_abs : 2471 { 2472 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2473 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2474 } 2475 __ andpd(dest->as_xmm_double_reg(), 2476 ExternalAddress((address)double_signmask_pool)); 2477 } 2478 break; 2479 2480 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2481 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2482 default : ShouldNotReachHere(); 2483 } 2484 2485 } else if (value->is_double_fpu()) { 2486 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2487 switch(code) { 2488 case lir_log : __ flog() ; break; 2489 case lir_log10 : __ flog10() ; break; 2490 case lir_abs : __ fabs() ; break; 2491 case lir_sqrt : __ fsqrt(); break; 2492 case lir_sin : 2493 // Should consider not saving rbx, if not necessary 2494 __ trigfunc('s', op->as_Op2()->fpu_stack_size()); 2495 break; 2496 case lir_cos : 2497 // Should consider not saving rbx, if not necessary 2498 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); 2499 __ trigfunc('c', op->as_Op2()->fpu_stack_size()); 2500 break; 2501 case lir_tan : 2502 // Should consider not saving rbx, if not necessary 2503 __ trigfunc('t', op->as_Op2()->fpu_stack_size()); 2504 break; 2505 case lir_exp : 2506 __ exp_with_fallback(op->as_Op2()->fpu_stack_size()); 2507 break; 2508 case lir_pow : 2509 __ pow_with_fallback(op->as_Op2()->fpu_stack_size()); 2510 break; 2511 default : ShouldNotReachHere(); 2512 } 2513 } else { 2514 Unimplemented(); 2515 } 2516 } 2517 2518 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2519 // assert(left->destroys_register(), "check"); 2520 if (left->is_single_cpu()) { 2521 Register reg = left->as_register(); 2522 if (right->is_constant()) { 2523 int val = right->as_constant_ptr()->as_jint(); 2524 switch (code) { 2525 case lir_logic_and: __ andl (reg, val); break; 2526 case lir_logic_or: __ orl (reg, val); break; 2527 case lir_logic_xor: __ xorl (reg, val); break; 2528 default: ShouldNotReachHere(); 2529 } 2530 } else if (right->is_stack()) { 2531 // added support for stack operands 2532 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2533 switch (code) { 2534 case lir_logic_and: __ andl (reg, raddr); break; 2535 case lir_logic_or: __ orl (reg, raddr); break; 2536 case lir_logic_xor: __ xorl (reg, raddr); break; 2537 default: ShouldNotReachHere(); 2538 } 2539 } else { 2540 Register rright = right->as_register(); 2541 switch (code) { 2542 case lir_logic_and: __ andptr (reg, rright); break; 2543 case lir_logic_or : __ orptr (reg, rright); break; 2544 case lir_logic_xor: __ xorptr (reg, rright); break; 2545 default: ShouldNotReachHere(); 2546 } 2547 } 2548 move_regs(reg, dst->as_register()); 2549 } else { 2550 Register l_lo = left->as_register_lo(); 2551 Register l_hi = left->as_register_hi(); 2552 if (right->is_constant()) { 2553 #ifdef _LP64 2554 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2555 switch (code) { 2556 case lir_logic_and: 2557 __ andq(l_lo, rscratch1); 2558 break; 2559 case lir_logic_or: 2560 __ orq(l_lo, rscratch1); 2561 break; 2562 case lir_logic_xor: 2563 __ xorq(l_lo, rscratch1); 2564 break; 2565 default: ShouldNotReachHere(); 2566 } 2567 #else 2568 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2569 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2570 switch (code) { 2571 case lir_logic_and: 2572 __ andl(l_lo, r_lo); 2573 __ andl(l_hi, r_hi); 2574 break; 2575 case lir_logic_or: 2576 __ orl(l_lo, r_lo); 2577 __ orl(l_hi, r_hi); 2578 break; 2579 case lir_logic_xor: 2580 __ xorl(l_lo, r_lo); 2581 __ xorl(l_hi, r_hi); 2582 break; 2583 default: ShouldNotReachHere(); 2584 } 2585 #endif // _LP64 2586 } else { 2587 #ifdef _LP64 2588 Register r_lo; 2589 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { 2590 r_lo = right->as_register(); 2591 } else { 2592 r_lo = right->as_register_lo(); 2593 } 2594 #else 2595 Register r_lo = right->as_register_lo(); 2596 Register r_hi = right->as_register_hi(); 2597 assert(l_lo != r_hi, "overwriting registers"); 2598 #endif 2599 switch (code) { 2600 case lir_logic_and: 2601 __ andptr(l_lo, r_lo); 2602 NOT_LP64(__ andptr(l_hi, r_hi);) 2603 break; 2604 case lir_logic_or: 2605 __ orptr(l_lo, r_lo); 2606 NOT_LP64(__ orptr(l_hi, r_hi);) 2607 break; 2608 case lir_logic_xor: 2609 __ xorptr(l_lo, r_lo); 2610 NOT_LP64(__ xorptr(l_hi, r_hi);) 2611 break; 2612 default: ShouldNotReachHere(); 2613 } 2614 } 2615 2616 Register dst_lo = dst->as_register_lo(); 2617 Register dst_hi = dst->as_register_hi(); 2618 2619 #ifdef _LP64 2620 move_regs(l_lo, dst_lo); 2621 #else 2622 if (dst_lo == l_hi) { 2623 assert(dst_hi != l_lo, "overwriting registers"); 2624 move_regs(l_hi, dst_hi); 2625 move_regs(l_lo, dst_lo); 2626 } else { 2627 assert(dst_lo != l_hi, "overwriting registers"); 2628 move_regs(l_lo, dst_lo); 2629 move_regs(l_hi, dst_hi); 2630 } 2631 #endif // _LP64 2632 } 2633 } 2634 2635 2636 // we assume that rax, and rdx can be overwritten 2637 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2638 2639 assert(left->is_single_cpu(), "left must be register"); 2640 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2641 assert(result->is_single_cpu(), "result must be register"); 2642 2643 // assert(left->destroys_register(), "check"); 2644 // assert(right->destroys_register(), "check"); 2645 2646 Register lreg = left->as_register(); 2647 Register dreg = result->as_register(); 2648 2649 if (right->is_constant()) { 2650 int divisor = right->as_constant_ptr()->as_jint(); 2651 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2652 if (code == lir_idiv) { 2653 assert(lreg == rax, "must be rax,"); 2654 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2655 __ cdql(); // sign extend into rdx:rax 2656 if (divisor == 2) { 2657 __ subl(lreg, rdx); 2658 } else { 2659 __ andl(rdx, divisor - 1); 2660 __ addl(lreg, rdx); 2661 } 2662 __ sarl(lreg, log2_intptr(divisor)); 2663 move_regs(lreg, dreg); 2664 } else if (code == lir_irem) { 2665 Label done; 2666 __ mov(dreg, lreg); 2667 __ andl(dreg, 0x80000000 | (divisor - 1)); 2668 __ jcc(Assembler::positive, done); 2669 __ decrement(dreg); 2670 __ orl(dreg, ~(divisor - 1)); 2671 __ increment(dreg); 2672 __ bind(done); 2673 } else { 2674 ShouldNotReachHere(); 2675 } 2676 } else { 2677 Register rreg = right->as_register(); 2678 assert(lreg == rax, "left register must be rax,"); 2679 assert(rreg != rdx, "right register must not be rdx"); 2680 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2681 2682 move_regs(lreg, rax); 2683 2684 int idivl_offset = __ corrected_idivl(rreg); 2685 add_debug_info_for_div0(idivl_offset, info); 2686 if (code == lir_irem) { 2687 move_regs(rdx, dreg); // result is in rdx 2688 } else { 2689 move_regs(rax, dreg); 2690 } 2691 } 2692 } 2693 2694 2695 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2696 if (opr1->is_single_cpu()) { 2697 Register reg1 = opr1->as_register(); 2698 if (opr2->is_single_cpu()) { 2699 // cpu register - cpu register 2700 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2701 __ cmpptr(reg1, opr2->as_register()); 2702 } else { 2703 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); 2704 __ cmpl(reg1, opr2->as_register()); 2705 } 2706 } else if (opr2->is_stack()) { 2707 // cpu register - stack 2708 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2709 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2710 } else { 2711 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2712 } 2713 } else if (opr2->is_constant()) { 2714 // cpu register - constant 2715 LIR_Const* c = opr2->as_constant_ptr(); 2716 if (c->type() == T_INT) { 2717 __ cmpl(reg1, c->as_jint()); 2718 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2719 // In 64bit oops are single register 2720 jobject o = c->as_jobject(); 2721 if (o == NULL) { 2722 __ cmpptr(reg1, (int32_t)NULL_WORD); 2723 } else { 2724 #ifdef _LP64 2725 __ movoop(rscratch1, o); 2726 __ cmpptr(reg1, rscratch1); 2727 #else 2728 __ cmpoop(reg1, c->as_jobject()); 2729 #endif // _LP64 2730 } 2731 } else { 2732 fatal(err_msg("unexpected type: %s", basictype_to_str(c->type()))); 2733 } 2734 // cpu register - address 2735 } else if (opr2->is_address()) { 2736 if (op->info() != NULL) { 2737 add_debug_info_for_null_check_here(op->info()); 2738 } 2739 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2740 } else { 2741 ShouldNotReachHere(); 2742 } 2743 2744 } else if(opr1->is_double_cpu()) { 2745 Register xlo = opr1->as_register_lo(); 2746 Register xhi = opr1->as_register_hi(); 2747 if (opr2->is_double_cpu()) { 2748 #ifdef _LP64 2749 __ cmpptr(xlo, opr2->as_register_lo()); 2750 #else 2751 // cpu register - cpu register 2752 Register ylo = opr2->as_register_lo(); 2753 Register yhi = opr2->as_register_hi(); 2754 __ subl(xlo, ylo); 2755 __ sbbl(xhi, yhi); 2756 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2757 __ orl(xhi, xlo); 2758 } 2759 #endif // _LP64 2760 } else if (opr2->is_constant()) { 2761 // cpu register - constant 0 2762 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2763 #ifdef _LP64 2764 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2765 #else 2766 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2767 __ orl(xhi, xlo); 2768 #endif // _LP64 2769 } else { 2770 ShouldNotReachHere(); 2771 } 2772 2773 } else if (opr1->is_single_xmm()) { 2774 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2775 if (opr2->is_single_xmm()) { 2776 // xmm register - xmm register 2777 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2778 } else if (opr2->is_stack()) { 2779 // xmm register - stack 2780 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2781 } else if (opr2->is_constant()) { 2782 // xmm register - constant 2783 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2784 } else if (opr2->is_address()) { 2785 // xmm register - address 2786 if (op->info() != NULL) { 2787 add_debug_info_for_null_check_here(op->info()); 2788 } 2789 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2790 } else { 2791 ShouldNotReachHere(); 2792 } 2793 2794 } else if (opr1->is_double_xmm()) { 2795 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2796 if (opr2->is_double_xmm()) { 2797 // xmm register - xmm register 2798 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2799 } else if (opr2->is_stack()) { 2800 // xmm register - stack 2801 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2802 } else if (opr2->is_constant()) { 2803 // xmm register - constant 2804 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2805 } else if (opr2->is_address()) { 2806 // xmm register - address 2807 if (op->info() != NULL) { 2808 add_debug_info_for_null_check_here(op->info()); 2809 } 2810 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2811 } else { 2812 ShouldNotReachHere(); 2813 } 2814 2815 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2816 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2817 assert(opr2->is_fpu_register(), "both must be registers"); 2818 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2819 2820 } else if (opr1->is_address() && opr2->is_constant()) { 2821 LIR_Const* c = opr2->as_constant_ptr(); 2822 #ifdef _LP64 2823 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2824 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2825 __ movoop(rscratch1, c->as_jobject()); 2826 } 2827 #endif // LP64 2828 if (op->info() != NULL) { 2829 add_debug_info_for_null_check_here(op->info()); 2830 } 2831 // special case: address - constant 2832 LIR_Address* addr = opr1->as_address_ptr(); 2833 if (c->type() == T_INT) { 2834 __ cmpl(as_Address(addr), c->as_jint()); 2835 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2836 #ifdef _LP64 2837 // %%% Make this explode if addr isn't reachable until we figure out a 2838 // better strategy by giving noreg as the temp for as_Address 2839 __ cmpptr(rscratch1, as_Address(addr, noreg)); 2840 #else 2841 __ cmpoop(as_Address(addr), c->as_jobject()); 2842 #endif // _LP64 2843 } else { 2844 ShouldNotReachHere(); 2845 } 2846 2847 } else { 2848 ShouldNotReachHere(); 2849 } 2850 } 2851 2852 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2853 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2854 if (left->is_single_xmm()) { 2855 assert(right->is_single_xmm(), "must match"); 2856 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2857 } else if (left->is_double_xmm()) { 2858 assert(right->is_double_xmm(), "must match"); 2859 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2860 2861 } else { 2862 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2863 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2864 2865 assert(left->fpu() == 0, "left must be on TOS"); 2866 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2867 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2868 } 2869 } else { 2870 assert(code == lir_cmp_l2i, "check"); 2871 #ifdef _LP64 2872 Label done; 2873 Register dest = dst->as_register(); 2874 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2875 __ movl(dest, -1); 2876 __ jccb(Assembler::less, done); 2877 __ set_byte_if_not_zero(dest); 2878 __ movzbl(dest, dest); 2879 __ bind(done); 2880 #else 2881 __ lcmp2int(left->as_register_hi(), 2882 left->as_register_lo(), 2883 right->as_register_hi(), 2884 right->as_register_lo()); 2885 move_regs(left->as_register_hi(), dst->as_register()); 2886 #endif // _LP64 2887 } 2888 } 2889 2890 2891 void LIR_Assembler::align_call(LIR_Code code) { 2892 if (os::is_MP()) { 2893 // make sure that the displacement word of the call ends up word aligned 2894 int offset = __ offset(); 2895 switch (code) { 2896 case lir_static_call: 2897 case lir_optvirtual_call: 2898 case lir_dynamic_call: 2899 offset += NativeCall::displacement_offset; 2900 break; 2901 case lir_icvirtual_call: 2902 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2903 break; 2904 case lir_virtual_call: // currently, sparc-specific for niagara 2905 default: ShouldNotReachHere(); 2906 } 2907 while (offset++ % BytesPerWord != 0) { 2908 __ nop(); 2909 } 2910 } 2911 } 2912 2913 2914 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2915 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2916 "must be aligned"); 2917 __ call(AddressLiteral(op->addr(), rtype)); 2918 add_call_info(code_offset(), op->info()); 2919 } 2920 2921 2922 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2923 __ ic_call(op->addr()); 2924 add_call_info(code_offset(), op->info()); 2925 assert(!os::is_MP() || 2926 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0, 2927 "must be aligned"); 2928 } 2929 2930 2931 /* Currently, vtable-dispatch is only enabled for sparc platforms */ 2932 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 2933 ShouldNotReachHere(); 2934 } 2935 2936 2937 void LIR_Assembler::emit_static_call_stub() { 2938 address call_pc = __ pc(); 2939 address stub = __ start_a_stub(call_stub_size); 2940 if (stub == NULL) { 2941 bailout("static call stub overflow"); 2942 return; 2943 } 2944 2945 int start = __ offset(); 2946 if (os::is_MP()) { 2947 // make sure that the displacement word of the call ends up word aligned 2948 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; 2949 while (offset++ % BytesPerWord != 0) { 2950 __ nop(); 2951 } 2952 } 2953 __ relocate(static_stub_Relocation::spec(call_pc)); 2954 __ mov_metadata(rbx, (Metadata*)NULL); 2955 // must be set to -1 at code generation time 2956 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); 2957 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2958 __ jump(RuntimeAddress(__ pc())); 2959 2960 assert(__ offset() - start <= call_stub_size, "stub too big"); 2961 __ end_a_stub(); 2962 } 2963 2964 2965 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2966 assert(exceptionOop->as_register() == rax, "must match"); 2967 assert(exceptionPC->as_register() == rdx, "must match"); 2968 2969 // exception object is not added to oop map by LinearScan 2970 // (LinearScan assumes that no oops are in fixed registers) 2971 info->add_register_oop(exceptionOop); 2972 Runtime1::StubID unwind_id; 2973 2974 // get current pc information 2975 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2976 int pc_for_athrow_offset = __ offset(); 2977 InternalAddress pc_for_athrow(__ pc()); 2978 __ lea(exceptionPC->as_register(), pc_for_athrow); 2979 add_call_info(pc_for_athrow_offset, info); // for exception handler 2980 2981 __ verify_not_null_oop(rax); 2982 // search an exception handler (rax: exception oop, rdx: throwing pc) 2983 if (compilation()->has_fpu_code()) { 2984 unwind_id = Runtime1::handle_exception_id; 2985 } else { 2986 unwind_id = Runtime1::handle_exception_nofpu_id; 2987 } 2988 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2989 2990 // enough room for two byte trap 2991 __ nop(); 2992 } 2993 2994 2995 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2996 assert(exceptionOop->as_register() == rax, "must match"); 2997 2998 __ jmp(_unwind_handler_entry); 2999 } 3000 3001 3002 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 3003 3004 // optimized version for linear scan: 3005 // * count must be already in ECX (guaranteed by LinearScan) 3006 // * left and dest must be equal 3007 // * tmp must be unused 3008 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 3009 assert(left == dest, "left and dest must be equal"); 3010 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 3011 3012 if (left->is_single_cpu()) { 3013 Register value = left->as_register(); 3014 assert(value != SHIFT_count, "left cannot be ECX"); 3015 3016 switch (code) { 3017 case lir_shl: __ shll(value); break; 3018 case lir_shr: __ sarl(value); break; 3019 case lir_ushr: __ shrl(value); break; 3020 default: ShouldNotReachHere(); 3021 } 3022 } else if (left->is_double_cpu()) { 3023 Register lo = left->as_register_lo(); 3024 Register hi = left->as_register_hi(); 3025 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 3026 #ifdef _LP64 3027 switch (code) { 3028 case lir_shl: __ shlptr(lo); break; 3029 case lir_shr: __ sarptr(lo); break; 3030 case lir_ushr: __ shrptr(lo); break; 3031 default: ShouldNotReachHere(); 3032 } 3033 #else 3034 3035 switch (code) { 3036 case lir_shl: __ lshl(hi, lo); break; 3037 case lir_shr: __ lshr(hi, lo, true); break; 3038 case lir_ushr: __ lshr(hi, lo, false); break; 3039 default: ShouldNotReachHere(); 3040 } 3041 #endif // LP64 3042 } else { 3043 ShouldNotReachHere(); 3044 } 3045 } 3046 3047 3048 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 3049 if (dest->is_single_cpu()) { 3050 // first move left into dest so that left is not destroyed by the shift 3051 Register value = dest->as_register(); 3052 count = count & 0x1F; // Java spec 3053 3054 move_regs(left->as_register(), value); 3055 switch (code) { 3056 case lir_shl: __ shll(value, count); break; 3057 case lir_shr: __ sarl(value, count); break; 3058 case lir_ushr: __ shrl(value, count); break; 3059 default: ShouldNotReachHere(); 3060 } 3061 } else if (dest->is_double_cpu()) { 3062 #ifndef _LP64 3063 Unimplemented(); 3064 #else 3065 // first move left into dest so that left is not destroyed by the shift 3066 Register value = dest->as_register_lo(); 3067 count = count & 0x1F; // Java spec 3068 3069 move_regs(left->as_register_lo(), value); 3070 switch (code) { 3071 case lir_shl: __ shlptr(value, count); break; 3072 case lir_shr: __ sarptr(value, count); break; 3073 case lir_ushr: __ shrptr(value, count); break; 3074 default: ShouldNotReachHere(); 3075 } 3076 #endif // _LP64 3077 } else { 3078 ShouldNotReachHere(); 3079 } 3080 } 3081 3082 3083 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 3084 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3085 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3086 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3087 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 3088 } 3089 3090 3091 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 3092 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3093 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3094 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3095 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 3096 } 3097 3098 3099 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 3100 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3101 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3102 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3103 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); 3104 } 3105 3106 3107 // This code replaces a call to arraycopy; no exception may 3108 // be thrown in this code, they must be thrown in the System.arraycopy 3109 // activation frame; we could save some checks if this would not be the case 3110 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 3111 ciArrayKlass* default_type = op->expected_type(); 3112 Register src = op->src()->as_register(); 3113 Register dst = op->dst()->as_register(); 3114 Register src_pos = op->src_pos()->as_register(); 3115 Register dst_pos = op->dst_pos()->as_register(); 3116 Register length = op->length()->as_register(); 3117 Register tmp = op->tmp()->as_register(); 3118 3119 CodeStub* stub = op->stub(); 3120 int flags = op->flags(); 3121 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 3122 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 3123 3124 // if we don't know anything, just go through the generic arraycopy 3125 if (default_type == NULL) { 3126 Label done; 3127 // save outgoing arguments on stack in case call to System.arraycopy is needed 3128 // HACK ALERT. This code used to push the parameters in a hardwired fashion 3129 // for interpreter calling conventions. Now we have to do it in new style conventions. 3130 // For the moment until C1 gets the new register allocator I just force all the 3131 // args to the right place (except the register args) and then on the back side 3132 // reload the register args properly if we go slow path. Yuck 3133 3134 // These are proper for the calling convention 3135 store_parameter(length, 2); 3136 store_parameter(dst_pos, 1); 3137 store_parameter(dst, 0); 3138 3139 // these are just temporary placements until we need to reload 3140 store_parameter(src_pos, 3); 3141 store_parameter(src, 4); 3142 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3143 3144 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); 3145 3146 address copyfunc_addr = StubRoutines::generic_arraycopy(); 3147 3148 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3149 #ifdef _LP64 3150 // The arguments are in java calling convention so we can trivially shift them to C 3151 // convention 3152 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3153 __ mov(c_rarg0, j_rarg0); 3154 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3155 __ mov(c_rarg1, j_rarg1); 3156 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3157 __ mov(c_rarg2, j_rarg2); 3158 assert_different_registers(c_rarg3, j_rarg4); 3159 __ mov(c_rarg3, j_rarg3); 3160 #ifdef _WIN64 3161 // Allocate abi space for args but be sure to keep stack aligned 3162 __ subptr(rsp, 6*wordSize); 3163 store_parameter(j_rarg4, 4); 3164 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3165 __ call(RuntimeAddress(C_entry)); 3166 } else { 3167 #ifndef PRODUCT 3168 if (PrintC1Statistics) { 3169 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3170 } 3171 #endif 3172 __ call(RuntimeAddress(copyfunc_addr)); 3173 } 3174 __ addptr(rsp, 6*wordSize); 3175 #else 3176 __ mov(c_rarg4, j_rarg4); 3177 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3178 __ call(RuntimeAddress(C_entry)); 3179 } else { 3180 #ifndef PRODUCT 3181 if (PrintC1Statistics) { 3182 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3183 } 3184 #endif 3185 __ call(RuntimeAddress(copyfunc_addr)); 3186 } 3187 #endif // _WIN64 3188 #else 3189 __ push(length); 3190 __ push(dst_pos); 3191 __ push(dst); 3192 __ push(src_pos); 3193 __ push(src); 3194 3195 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3196 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack 3197 } else { 3198 #ifndef PRODUCT 3199 if (PrintC1Statistics) { 3200 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3201 } 3202 #endif 3203 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack 3204 } 3205 3206 #endif // _LP64 3207 3208 __ cmpl(rax, 0); 3209 __ jcc(Assembler::equal, *stub->continuation()); 3210 3211 if (copyfunc_addr != NULL) { 3212 __ mov(tmp, rax); 3213 __ xorl(tmp, -1); 3214 } 3215 3216 // Reload values from the stack so they are where the stub 3217 // expects them. 3218 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3219 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3220 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3221 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3222 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3223 3224 if (copyfunc_addr != NULL) { 3225 __ subl(length, tmp); 3226 __ addl(src_pos, tmp); 3227 __ addl(dst_pos, tmp); 3228 } 3229 __ jmp(*stub->entry()); 3230 3231 __ bind(*stub->continuation()); 3232 return; 3233 } 3234 3235 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3236 3237 int elem_size = type2aelembytes(basic_type); 3238 int shift_amount; 3239 Address::ScaleFactor scale; 3240 3241 switch (elem_size) { 3242 case 1 : 3243 shift_amount = 0; 3244 scale = Address::times_1; 3245 break; 3246 case 2 : 3247 shift_amount = 1; 3248 scale = Address::times_2; 3249 break; 3250 case 4 : 3251 shift_amount = 2; 3252 scale = Address::times_4; 3253 break; 3254 case 8 : 3255 shift_amount = 3; 3256 scale = Address::times_8; 3257 break; 3258 default: 3259 ShouldNotReachHere(); 3260 } 3261 3262 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3263 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3264 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3265 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3266 3267 // length and pos's are all sign extended at this point on 64bit 3268 3269 // test for NULL 3270 if (flags & LIR_OpArrayCopy::src_null_check) { 3271 __ testptr(src, src); 3272 __ jcc(Assembler::zero, *stub->entry()); 3273 } 3274 if (flags & LIR_OpArrayCopy::dst_null_check) { 3275 __ testptr(dst, dst); 3276 __ jcc(Assembler::zero, *stub->entry()); 3277 } 3278 3279 // check if negative 3280 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3281 __ testl(src_pos, src_pos); 3282 __ jcc(Assembler::less, *stub->entry()); 3283 } 3284 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3285 __ testl(dst_pos, dst_pos); 3286 __ jcc(Assembler::less, *stub->entry()); 3287 } 3288 3289 if (flags & LIR_OpArrayCopy::src_range_check) { 3290 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3291 __ cmpl(tmp, src_length_addr); 3292 __ jcc(Assembler::above, *stub->entry()); 3293 } 3294 if (flags & LIR_OpArrayCopy::dst_range_check) { 3295 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3296 __ cmpl(tmp, dst_length_addr); 3297 __ jcc(Assembler::above, *stub->entry()); 3298 } 3299 3300 if (flags & LIR_OpArrayCopy::length_positive_check) { 3301 __ testl(length, length); 3302 __ jcc(Assembler::less, *stub->entry()); 3303 __ jcc(Assembler::zero, *stub->continuation()); 3304 } 3305 3306 #ifdef _LP64 3307 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3308 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3309 #endif 3310 3311 if (flags & LIR_OpArrayCopy::type_check) { 3312 // We don't know the array types are compatible 3313 if (basic_type != T_OBJECT) { 3314 // Simple test for basic type arrays 3315 if (UseCompressedClassPointers) { 3316 __ movl(tmp, src_klass_addr); 3317 __ cmpl(tmp, dst_klass_addr); 3318 } else { 3319 __ movptr(tmp, src_klass_addr); 3320 __ cmpptr(tmp, dst_klass_addr); 3321 } 3322 __ jcc(Assembler::notEqual, *stub->entry()); 3323 } else { 3324 // For object arrays, if src is a sub class of dst then we can 3325 // safely do the copy. 3326 Label cont, slow; 3327 3328 __ push(src); 3329 __ push(dst); 3330 3331 __ load_klass(src, src); 3332 __ load_klass(dst, dst); 3333 3334 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); 3335 3336 __ push(src); 3337 __ push(dst); 3338 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 3339 __ pop(dst); 3340 __ pop(src); 3341 3342 __ cmpl(src, 0); 3343 __ jcc(Assembler::notEqual, cont); 3344 3345 __ bind(slow); 3346 __ pop(dst); 3347 __ pop(src); 3348 3349 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 3350 if (copyfunc_addr != NULL) { // use stub if available 3351 // src is not a sub class of dst so we have to do a 3352 // per-element check. 3353 3354 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 3355 if ((flags & mask) != mask) { 3356 // Check that at least both of them object arrays. 3357 assert(flags & mask, "one of the two should be known to be an object array"); 3358 3359 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3360 __ load_klass(tmp, src); 3361 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3362 __ load_klass(tmp, dst); 3363 } 3364 int lh_offset = in_bytes(Klass::layout_helper_offset()); 3365 Address klass_lh_addr(tmp, lh_offset); 3366 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 3367 __ cmpl(klass_lh_addr, objArray_lh); 3368 __ jcc(Assembler::notEqual, *stub->entry()); 3369 } 3370 3371 // Spill because stubs can use any register they like and it's 3372 // easier to restore just those that we care about. 3373 store_parameter(dst, 0); 3374 store_parameter(dst_pos, 1); 3375 store_parameter(length, 2); 3376 store_parameter(src_pos, 3); 3377 store_parameter(src, 4); 3378 3379 #ifndef _LP64 3380 __ movptr(tmp, dst_klass_addr); 3381 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset())); 3382 __ push(tmp); 3383 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); 3384 __ push(tmp); 3385 __ push(length); 3386 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3387 __ push(tmp); 3388 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3389 __ push(tmp); 3390 3391 __ call_VM_leaf(copyfunc_addr, 5); 3392 #else 3393 __ movl2ptr(length, length); //higher 32bits must be null 3394 3395 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3396 assert_different_registers(c_rarg0, dst, dst_pos, length); 3397 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3398 assert_different_registers(c_rarg1, dst, length); 3399 3400 __ mov(c_rarg2, length); 3401 assert_different_registers(c_rarg2, dst); 3402 3403 #ifdef _WIN64 3404 // Allocate abi space for args but be sure to keep stack aligned 3405 __ subptr(rsp, 6*wordSize); 3406 __ load_klass(c_rarg3, dst); 3407 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset())); 3408 store_parameter(c_rarg3, 4); 3409 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); 3410 __ call(RuntimeAddress(copyfunc_addr)); 3411 __ addptr(rsp, 6*wordSize); 3412 #else 3413 __ load_klass(c_rarg4, dst); 3414 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); 3415 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 3416 __ call(RuntimeAddress(copyfunc_addr)); 3417 #endif 3418 3419 #endif 3420 3421 #ifndef PRODUCT 3422 if (PrintC1Statistics) { 3423 Label failed; 3424 __ testl(rax, rax); 3425 __ jcc(Assembler::notZero, failed); 3426 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); 3427 __ bind(failed); 3428 } 3429 #endif 3430 3431 __ testl(rax, rax); 3432 __ jcc(Assembler::zero, *stub->continuation()); 3433 3434 #ifndef PRODUCT 3435 if (PrintC1Statistics) { 3436 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); 3437 } 3438 #endif 3439 3440 __ mov(tmp, rax); 3441 3442 __ xorl(tmp, -1); 3443 3444 // Restore previously spilled arguments 3445 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3446 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3447 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3448 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3449 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3450 3451 3452 __ subl(length, tmp); 3453 __ addl(src_pos, tmp); 3454 __ addl(dst_pos, tmp); 3455 } 3456 3457 __ jmp(*stub->entry()); 3458 3459 __ bind(cont); 3460 __ pop(dst); 3461 __ pop(src); 3462 } 3463 } 3464 3465 #ifdef ASSERT 3466 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3467 // Sanity check the known type with the incoming class. For the 3468 // primitive case the types must match exactly with src.klass and 3469 // dst.klass each exactly matching the default type. For the 3470 // object array case, if no type check is needed then either the 3471 // dst type is exactly the expected type and the src type is a 3472 // subtype which we can't check or src is the same array as dst 3473 // but not necessarily exactly of type default_type. 3474 Label known_ok, halt; 3475 __ mov_metadata(tmp, default_type->constant_encoding()); 3476 #ifdef _LP64 3477 if (UseCompressedClassPointers) { 3478 __ encode_klass_not_null(tmp); 3479 } 3480 #endif 3481 3482 if (basic_type != T_OBJECT) { 3483 3484 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3485 else __ cmpptr(tmp, dst_klass_addr); 3486 __ jcc(Assembler::notEqual, halt); 3487 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr); 3488 else __ cmpptr(tmp, src_klass_addr); 3489 __ jcc(Assembler::equal, known_ok); 3490 } else { 3491 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3492 else __ cmpptr(tmp, dst_klass_addr); 3493 __ jcc(Assembler::equal, known_ok); 3494 __ cmpptr(src, dst); 3495 __ jcc(Assembler::equal, known_ok); 3496 } 3497 __ bind(halt); 3498 __ stop("incorrect type information in arraycopy"); 3499 __ bind(known_ok); 3500 } 3501 #endif 3502 3503 #ifndef PRODUCT 3504 if (PrintC1Statistics) { 3505 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); 3506 } 3507 #endif 3508 3509 #ifdef _LP64 3510 assert_different_registers(c_rarg0, dst, dst_pos, length); 3511 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3512 assert_different_registers(c_rarg1, length); 3513 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3514 __ mov(c_rarg2, length); 3515 3516 #else 3517 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3518 store_parameter(tmp, 0); 3519 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3520 store_parameter(tmp, 1); 3521 store_parameter(length, 2); 3522 #endif // _LP64 3523 3524 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 3525 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 3526 const char *name; 3527 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 3528 __ call_VM_leaf(entry, 0); 3529 3530 __ bind(*stub->continuation()); 3531 } 3532 3533 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3534 assert(op->crc()->is_single_cpu(), "crc must be register"); 3535 assert(op->val()->is_single_cpu(), "byte value must be register"); 3536 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3537 Register crc = op->crc()->as_register(); 3538 Register val = op->val()->as_register(); 3539 Register res = op->result_opr()->as_register(); 3540 3541 assert_different_registers(val, crc, res); 3542 3543 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr())); 3544 __ notl(crc); // ~crc 3545 __ update_byte_crc32(crc, val, res); 3546 __ notl(crc); // ~crc 3547 __ mov(res, crc); 3548 } 3549 3550 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3551 Register obj = op->obj_opr()->as_register(); // may not be an oop 3552 Register hdr = op->hdr_opr()->as_register(); 3553 Register lock = op->lock_opr()->as_register(); 3554 if (!UseFastLocking) { 3555 __ jmp(*op->stub()->entry()); 3556 } else if (op->code() == lir_lock) { 3557 Register scratch = noreg; 3558 if (UseBiasedLocking) { 3559 scratch = op->scratch_opr()->as_register(); 3560 } 3561 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3562 // add debug info for NullPointerException only if one is possible 3563 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); 3564 if (op->info() != NULL) { 3565 add_debug_info_for_null_check(null_check_offset, op->info()); 3566 } 3567 // done 3568 } else if (op->code() == lir_unlock) { 3569 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3570 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3571 } else { 3572 Unimplemented(); 3573 } 3574 __ bind(*op->stub()->continuation()); 3575 } 3576 3577 3578 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3579 ciMethod* method = op->profiled_method(); 3580 int bci = op->profiled_bci(); 3581 ciMethod* callee = op->profiled_callee(); 3582 3583 // Update counter for all call types 3584 ciMethodData* md = method->method_data_or_null(); 3585 assert(md != NULL, "Sanity"); 3586 ciProfileData* data = md->bci_to_data(bci); 3587 assert(data->is_CounterData(), "need CounterData for calls"); 3588 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3589 Register mdo = op->mdo()->as_register(); 3590 __ mov_metadata(mdo, md->constant_encoding()); 3591 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3592 Bytecodes::Code bc = method->java_code_at_bci(bci); 3593 const bool callee_is_static = callee->is_loaded() && callee->is_static(); 3594 // Perform additional virtual call profiling for invokevirtual and 3595 // invokeinterface bytecodes 3596 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && 3597 !callee_is_static && // required for optimized MH invokes 3598 C1ProfileVirtualCalls) { 3599 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3600 Register recv = op->recv()->as_register(); 3601 assert_different_registers(mdo, recv); 3602 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3603 ciKlass* known_klass = op->known_holder(); 3604 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 3605 // We know the type that will be seen at this call site; we can 3606 // statically update the MethodData* rather than needing to do 3607 // dynamic tests on the receiver type 3608 3609 // NOTE: we should probably put a lock around this search to 3610 // avoid collisions by concurrent compilations 3611 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3612 uint i; 3613 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3614 ciKlass* receiver = vc_data->receiver(i); 3615 if (known_klass->equals(receiver)) { 3616 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3617 __ addptr(data_addr, DataLayout::counter_increment); 3618 return; 3619 } 3620 } 3621 3622 // Receiver type not found in profile data; select an empty slot 3623 3624 // Note that this is less efficient than it should be because it 3625 // always does a write to the receiver part of the 3626 // VirtualCallData rather than just the first time 3627 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3628 ciKlass* receiver = vc_data->receiver(i); 3629 if (receiver == NULL) { 3630 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3631 __ mov_metadata(recv_addr, known_klass->constant_encoding()); 3632 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3633 __ addptr(data_addr, DataLayout::counter_increment); 3634 return; 3635 } 3636 } 3637 } else { 3638 __ load_klass(recv, recv); 3639 Label update_done; 3640 type_profile_helper(mdo, md, data, recv, &update_done); 3641 // Receiver did not match any saved receiver and there is no empty row for it. 3642 // Increment total counter to indicate polymorphic case. 3643 __ addptr(counter_addr, DataLayout::counter_increment); 3644 3645 __ bind(update_done); 3646 } 3647 } else { 3648 // Static call 3649 __ addptr(counter_addr, DataLayout::counter_increment); 3650 } 3651 } 3652 3653 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 3654 Register obj = op->obj()->as_register(); 3655 Register tmp = op->tmp()->as_pointer_register(); 3656 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 3657 ciKlass* exact_klass = op->exact_klass(); 3658 intptr_t current_klass = op->current_klass(); 3659 bool not_null = op->not_null(); 3660 bool no_conflict = op->no_conflict(); 3661 3662 Label update, next, none; 3663 3664 bool do_null = !not_null; 3665 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 3666 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 3667 3668 assert(do_null || do_update, "why are we here?"); 3669 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 3670 3671 __ verify_oop(obj); 3672 3673 if (tmp != obj) { 3674 __ mov(tmp, obj); 3675 } 3676 if (do_null) { 3677 __ testptr(tmp, tmp); 3678 __ jccb(Assembler::notZero, update); 3679 if (!TypeEntries::was_null_seen(current_klass)) { 3680 __ orptr(mdo_addr, TypeEntries::null_seen); 3681 } 3682 if (do_update) { 3683 #ifndef ASSERT 3684 __ jmpb(next); 3685 } 3686 #else 3687 __ jmp(next); 3688 } 3689 } else { 3690 __ testptr(tmp, tmp); 3691 __ jccb(Assembler::notZero, update); 3692 __ stop("unexpect null obj"); 3693 #endif 3694 } 3695 3696 __ bind(update); 3697 3698 if (do_update) { 3699 #ifdef ASSERT 3700 if (exact_klass != NULL) { 3701 Label ok; 3702 __ load_klass(tmp, tmp); 3703 __ push(tmp); 3704 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3705 __ cmpptr(tmp, Address(rsp, 0)); 3706 __ jccb(Assembler::equal, ok); 3707 __ stop("exact klass and actual klass differ"); 3708 __ bind(ok); 3709 __ pop(tmp); 3710 } 3711 #endif 3712 if (!no_conflict) { 3713 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 3714 if (exact_klass != NULL) { 3715 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3716 } else { 3717 __ load_klass(tmp, tmp); 3718 } 3719 3720 __ xorptr(tmp, mdo_addr); 3721 __ testptr(tmp, TypeEntries::type_klass_mask); 3722 // klass seen before, nothing to do. The unknown bit may have been 3723 // set already but no need to check. 3724 __ jccb(Assembler::zero, next); 3725 3726 __ testptr(tmp, TypeEntries::type_unknown); 3727 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3728 3729 if (TypeEntries::is_type_none(current_klass)) { 3730 __ cmpptr(mdo_addr, 0); 3731 __ jccb(Assembler::equal, none); 3732 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3733 __ jccb(Assembler::equal, none); 3734 // There is a chance that the checks above (re-reading profiling 3735 // data from memory) fail if another thread has just set the 3736 // profiling to this obj's klass 3737 __ xorptr(tmp, mdo_addr); 3738 __ testptr(tmp, TypeEntries::type_klass_mask); 3739 __ jccb(Assembler::zero, next); 3740 } 3741 } else { 3742 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3743 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 3744 3745 __ movptr(tmp, mdo_addr); 3746 __ testptr(tmp, TypeEntries::type_unknown); 3747 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3748 } 3749 3750 // different than before. Cannot keep accurate profile. 3751 __ orptr(mdo_addr, TypeEntries::type_unknown); 3752 3753 if (TypeEntries::is_type_none(current_klass)) { 3754 __ jmpb(next); 3755 3756 __ bind(none); 3757 // first time here. Set profile type. 3758 __ movptr(mdo_addr, tmp); 3759 } 3760 } else { 3761 // There's a single possible klass at this profile point 3762 assert(exact_klass != NULL, "should be"); 3763 if (TypeEntries::is_type_none(current_klass)) { 3764 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3765 __ xorptr(tmp, mdo_addr); 3766 __ testptr(tmp, TypeEntries::type_klass_mask); 3767 #ifdef ASSERT 3768 __ jcc(Assembler::zero, next); 3769 3770 { 3771 Label ok; 3772 __ push(tmp); 3773 __ cmpptr(mdo_addr, 0); 3774 __ jcc(Assembler::equal, ok); 3775 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3776 __ jcc(Assembler::equal, ok); 3777 // may have been set by another thread 3778 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3779 __ xorptr(tmp, mdo_addr); 3780 __ testptr(tmp, TypeEntries::type_mask); 3781 __ jcc(Assembler::zero, ok); 3782 3783 __ stop("unexpected profiling mismatch"); 3784 __ bind(ok); 3785 __ pop(tmp); 3786 } 3787 #else 3788 __ jccb(Assembler::zero, next); 3789 #endif 3790 // first time here. Set profile type. 3791 __ movptr(mdo_addr, tmp); 3792 } else { 3793 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3794 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3795 3796 __ movptr(tmp, mdo_addr); 3797 __ testptr(tmp, TypeEntries::type_unknown); 3798 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3799 3800 __ orptr(mdo_addr, TypeEntries::type_unknown); 3801 } 3802 } 3803 3804 __ bind(next); 3805 } 3806 } 3807 3808 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3809 Unimplemented(); 3810 } 3811 3812 3813 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3814 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3815 } 3816 3817 3818 void LIR_Assembler::align_backward_branch_target() { 3819 __ align(BytesPerWord); 3820 } 3821 3822 3823 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3824 if (left->is_single_cpu()) { 3825 __ negl(left->as_register()); 3826 move_regs(left->as_register(), dest->as_register()); 3827 3828 } else if (left->is_double_cpu()) { 3829 Register lo = left->as_register_lo(); 3830 #ifdef _LP64 3831 Register dst = dest->as_register_lo(); 3832 __ movptr(dst, lo); 3833 __ negptr(dst); 3834 #else 3835 Register hi = left->as_register_hi(); 3836 __ lneg(hi, lo); 3837 if (dest->as_register_lo() == hi) { 3838 assert(dest->as_register_hi() != lo, "destroying register"); 3839 move_regs(hi, dest->as_register_hi()); 3840 move_regs(lo, dest->as_register_lo()); 3841 } else { 3842 move_regs(lo, dest->as_register_lo()); 3843 move_regs(hi, dest->as_register_hi()); 3844 } 3845 #endif // _LP64 3846 3847 } else if (dest->is_single_xmm()) { 3848 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3849 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3850 } 3851 __ xorps(dest->as_xmm_float_reg(), 3852 ExternalAddress((address)float_signflip_pool)); 3853 3854 } else if (dest->is_double_xmm()) { 3855 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3856 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3857 } 3858 __ xorpd(dest->as_xmm_double_reg(), 3859 ExternalAddress((address)double_signflip_pool)); 3860 3861 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3862 assert(left->fpu() == 0, "arg must be on TOS"); 3863 assert(dest->fpu() == 0, "dest must be TOS"); 3864 __ fchs(); 3865 3866 } else { 3867 ShouldNotReachHere(); 3868 } 3869 } 3870 3871 3872 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { 3873 assert(addr->is_address() && dest->is_register(), "check"); 3874 Register reg; 3875 reg = dest->as_pointer_register(); 3876 __ lea(reg, as_Address(addr->as_address_ptr())); 3877 } 3878 3879 3880 3881 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3882 assert(!tmp->is_valid(), "don't need temporary"); 3883 __ call(RuntimeAddress(dest)); 3884 if (info != NULL) { 3885 add_call_info_here(info); 3886 } 3887 } 3888 3889 3890 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3891 assert(type == T_LONG, "only for volatile long fields"); 3892 3893 if (info != NULL) { 3894 add_debug_info_for_null_check_here(info); 3895 } 3896 3897 if (src->is_double_xmm()) { 3898 if (dest->is_double_cpu()) { 3899 #ifdef _LP64 3900 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3901 #else 3902 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3903 __ psrlq(src->as_xmm_double_reg(), 32); 3904 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3905 #endif // _LP64 3906 } else if (dest->is_double_stack()) { 3907 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3908 } else if (dest->is_address()) { 3909 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3910 } else { 3911 ShouldNotReachHere(); 3912 } 3913 3914 } else if (dest->is_double_xmm()) { 3915 if (src->is_double_stack()) { 3916 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3917 } else if (src->is_address()) { 3918 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3919 } else { 3920 ShouldNotReachHere(); 3921 } 3922 3923 } else if (src->is_double_fpu()) { 3924 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3925 if (dest->is_double_stack()) { 3926 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3927 } else if (dest->is_address()) { 3928 __ fistp_d(as_Address(dest->as_address_ptr())); 3929 } else { 3930 ShouldNotReachHere(); 3931 } 3932 3933 } else if (dest->is_double_fpu()) { 3934 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3935 if (src->is_double_stack()) { 3936 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3937 } else if (src->is_address()) { 3938 __ fild_d(as_Address(src->as_address_ptr())); 3939 } else { 3940 ShouldNotReachHere(); 3941 } 3942 } else { 3943 ShouldNotReachHere(); 3944 } 3945 } 3946 3947 #ifdef ASSERT 3948 // emit run-time assertion 3949 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 3950 assert(op->code() == lir_assert, "must be"); 3951 3952 if (op->in_opr1()->is_valid()) { 3953 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 3954 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 3955 } else { 3956 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 3957 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 3958 } 3959 3960 Label ok; 3961 if (op->condition() != lir_cond_always) { 3962 Assembler::Condition acond = Assembler::zero; 3963 switch (op->condition()) { 3964 case lir_cond_equal: acond = Assembler::equal; break; 3965 case lir_cond_notEqual: acond = Assembler::notEqual; break; 3966 case lir_cond_less: acond = Assembler::less; break; 3967 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 3968 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 3969 case lir_cond_greater: acond = Assembler::greater; break; 3970 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 3971 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 3972 default: ShouldNotReachHere(); 3973 } 3974 __ jcc(acond, ok); 3975 } 3976 if (op->halt()) { 3977 const char* str = __ code_string(op->msg()); 3978 __ stop(str); 3979 } else { 3980 breakpoint(); 3981 } 3982 __ bind(ok); 3983 } 3984 #endif 3985 3986 void LIR_Assembler::membar() { 3987 // QQQ sparc TSO uses this, 3988 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3989 } 3990 3991 void LIR_Assembler::membar_acquire() { 3992 // No x86 machines currently require load fences 3993 // __ load_fence(); 3994 } 3995 3996 void LIR_Assembler::membar_release() { 3997 // No x86 machines currently require store fences 3998 // __ store_fence(); 3999 } 4000 4001 void LIR_Assembler::membar_loadload() { 4002 // no-op 4003 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 4004 } 4005 4006 void LIR_Assembler::membar_storestore() { 4007 // no-op 4008 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 4009 } 4010 4011 void LIR_Assembler::membar_loadstore() { 4012 // no-op 4013 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 4014 } 4015 4016 void LIR_Assembler::membar_storeload() { 4017 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 4018 } 4019 4020 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 4021 assert(result_reg->is_register(), "check"); 4022 #ifdef _LP64 4023 // __ get_thread(result_reg->as_register_lo()); 4024 __ mov(result_reg->as_register(), r15_thread); 4025 #else 4026 __ get_thread(result_reg->as_register()); 4027 #endif // _LP64 4028 } 4029 4030 4031 void LIR_Assembler::peephole(LIR_List*) { 4032 // do nothing for now 4033 } 4034 4035 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 4036 assert(data == dest, "xchg/xadd uses only 2 operands"); 4037 4038 if (data->type() == T_INT) { 4039 if (code == lir_xadd) { 4040 if (os::is_MP()) { 4041 __ lock(); 4042 } 4043 __ xaddl(as_Address(src->as_address_ptr()), data->as_register()); 4044 } else { 4045 __ xchgl(data->as_register(), as_Address(src->as_address_ptr())); 4046 } 4047 } else if (data->is_oop()) { 4048 assert (code == lir_xchg, "xadd for oops"); 4049 Register obj = data->as_register(); 4050 #ifdef _LP64 4051 if (UseCompressedOops) { 4052 __ encode_heap_oop(obj); 4053 __ xchgl(obj, as_Address(src->as_address_ptr())); 4054 __ decode_heap_oop(obj); 4055 } else { 4056 __ xchgptr(obj, as_Address(src->as_address_ptr())); 4057 } 4058 #else 4059 __ xchgl(obj, as_Address(src->as_address_ptr())); 4060 #endif 4061 } else if (data->type() == T_LONG) { 4062 #ifdef _LP64 4063 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register"); 4064 if (code == lir_xadd) { 4065 if (os::is_MP()) { 4066 __ lock(); 4067 } 4068 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo()); 4069 } else { 4070 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr())); 4071 } 4072 #else 4073 ShouldNotReachHere(); 4074 #endif 4075 } else { 4076 ShouldNotReachHere(); 4077 } 4078 } 4079 4080 #undef __